├── .gitignore ├── Java ├── SignatureGenerator │ ├── pom.xml │ └── src │ │ └── main │ │ └── java │ │ └── converter │ │ ├── Main.java │ │ └── Signature.java └── signature-june2016.txt ├── LICENSE ├── Python ├── extract.py ├── html │ └── style.css ├── htmltext.py ├── htmltext.py.orig ├── pdftable.py ├── pdftable.py.orig ├── x86manual.py └── x86manual.py.orig ├── README.md ├── html ├── AAA.html ├── AAD.html ├── AAM.html ├── AAS.html ├── ADC.html ├── ADCX.html ├── ADD.html ├── ADDPD.html ├── ADDPS.html ├── ADDSD.html ├── ADDSS.html ├── ADDSUBPD.html ├── ADDSUBPS.html ├── ADOX.html ├── AESDEC.html ├── AESDECLAST.html ├── AESENC.html ├── AESENCLAST.html ├── AESIMC.html ├── AESKEYGENASSIST.html ├── AND.html ├── ANDN.html ├── ANDNPD.html ├── ANDNPS.html ├── ANDPD.html ├── ANDPS.html ├── ARPL.html ├── BEXTR.html ├── BLENDPD.html ├── BLENDPS.html ├── BLENDVPD.html ├── BLENDVPS.html ├── BLSI.html ├── BLSMSK.html ├── BLSR.html ├── BNDCL.html ├── BNDCU_BNDCN.html ├── BNDLDX.html ├── BNDMK.html ├── BNDMOV.html ├── BNDSTX.html ├── BOUND.html ├── BSF.html ├── BSR.html ├── BSWAP.html ├── BT.html ├── BTC.html ├── BTR.html ├── BTS.html ├── BZHI.html ├── CALL.html ├── CBW_CWDE_CDQE.html ├── CLAC.html ├── CLC.html ├── CLD.html ├── CLFLUSH.html ├── CLFLUSHOPT.html ├── CLI.html ├── CLTS.html ├── CMC.html ├── CMOVcc.html ├── CMP.html ├── CMPPD.html ├── CMPPS.html ├── CMPSD.html ├── CMPSS.html ├── CMPS_CMPSB_CMPSW_CMPSD_CMPSQ.html ├── CMPXCHG.html ├── CMPXCHG8B_CMPXCHG16B.html ├── COMISD.html ├── COMISS.html ├── CPUID.html ├── CRC32.html ├── CVTDQ2PD.html ├── CVTDQ2PS.html ├── CVTPD2DQ.html ├── CVTPD2PI.html ├── CVTPD2PS.html ├── CVTPI2PD.html ├── CVTPI2PS.html ├── CVTPS2DQ.html ├── CVTPS2PD.html ├── CVTPS2PI.html ├── CVTSD2SI.html ├── CVTSD2SS.html ├── CVTSI2SD.html ├── CVTSI2SS.html ├── CVTSS2SD.html ├── CVTSS2SI.html ├── CVTTPD2DQ.html ├── CVTTPD2PI.html ├── CVTTPS2DQ.html ├── CVTTPS2PI.html ├── CVTTSD2SI.html ├── CVTTSS2SI.html ├── CWD_CDQ_CQO.html ├── DAA.html ├── DAS.html ├── DEC.html ├── DIV.html ├── DIVPD.html ├── DIVPS.html ├── DIVSD.html ├── DIVSS.html ├── DPPD.html ├── DPPS.html ├── EMMS.html ├── ENTER.html ├── EXTRACTPS.html ├── F2XM1.html ├── FABS.html ├── FADD_FADDP_FIADD.html ├── FBLD.html ├── FBSTP.html ├── FCHS.html ├── FCLEX_FNCLEX.html ├── FCMOVcc.html ├── FCOMI_FCOMIP_FUCOMI_FUCOMIP.html ├── FCOM_FCOMP_FCOMPP.html ├── FCOS.html ├── FDECSTP.html ├── FDIVR_FDIVRP_FIDIVR.html ├── FDIV_FDIVP_FIDIV.html ├── FFREE.html ├── FICOM_FICOMP.html ├── FILD.html ├── FINCSTP.html ├── FINIT_FNINIT.html ├── FISTTP.html ├── FIST_FISTP.html ├── FLD.html ├── FLD1_FLDL2T_FLDL2E_FLDPI_FLDLG2_FLDLN2_FLDZ.html ├── FLDCW.html ├── FLDENV.html ├── FMUL_FMULP_FIMUL.html ├── FNOP.html ├── FPATAN.html ├── FPREM.html ├── FPREM1.html ├── FPTAN.html ├── FRNDINT.html ├── FRSTOR.html ├── FSAVE_FNSAVE.html ├── FSCALE.html ├── FSIN.html ├── FSINCOS.html ├── FSQRT.html ├── FSTCW_FNSTCW.html ├── FSTENV_FNSTENV.html ├── FSTSW_FNSTSW.html ├── FST_FSTP.html ├── FSUBR_FSUBRP_FISUBR.html ├── FSUB_FSUBP_FISUB.html ├── FTST.html ├── FUCOM_FUCOMP_FUCOMPP.html ├── FXAM.html ├── FXCH.html ├── FXRSTOR.html ├── FXSAVE.html ├── FXTRACT.html ├── FYL2X.html ├── FYL2XP1.html ├── HADDPD.html ├── HADDPS.html ├── HLT.html ├── HSUBPD.html ├── HSUBPS.html ├── IDIV.html ├── IMUL.html ├── IN.html ├── INC.html ├── INSERTPS.html ├── INS_INSB_INSW_INSD.html ├── INT n_INTO_INT 3.html ├── INVD.html ├── INVLPG.html ├── INVPCID.html ├── IRET_IRETD.html ├── JMP.html ├── Jcc.html ├── KADDW_KADDB_KADDQ_KADDD.html ├── KANDNW_KANDNB_KANDNQ_KANDND.html ├── KANDW_KANDB_KANDQ_KANDD.html ├── KMOVW_KMOVB_KMOVQ_KMOVD.html ├── KNOTW_KNOTB_KNOTQ_KNOTD.html ├── KORTESTW_KORTESTB_KORTESTQ_KORTESTD.html ├── KORW_KORB_KORQ_KORD.html ├── KSHIFTLW_KSHIFTLB_KSHIFTLQ_KSHIFTLD.html ├── KSHIFTRW_KSHIFTRB_KSHIFTRQ_KSHIFTRD.html ├── KTESTW_KTESTB_KTESTQ_KTESTD.html ├── KUNPCKBW_KUNPCKWD_KUNPCKDQ.html ├── KXNORW_KXNORB_KXNORQ_KXNORD.html ├── KXORW_KXORB_KXORQ_KXORD.html ├── LAHF.html ├── LAR.html ├── LDDQU.html ├── LDMXCSR.html ├── LDS_LES_LFS_LGS_LSS.html ├── LEA.html ├── LEAVE.html ├── LFENCE.html ├── LGDT_LIDT.html ├── LLDT.html ├── LMSW.html ├── LOCK.html ├── LODS_LODSB_LODSW_LODSD_LODSQ.html ├── LOOP_LOOPcc.html ├── LSL.html ├── LTR.html ├── LZCNT.html ├── MASKMOVDQU.html ├── MASKMOVQ.html ├── MAXPD.html ├── MAXPS.html ├── MAXSD.html ├── MAXSS.html ├── MFENCE.html ├── MINPD.html ├── MINPS.html ├── MINSD.html ├── MINSS.html ├── MONITOR.html ├── MOV-1.html ├── MOV-2.html ├── MOV.html ├── MOVAPD.html ├── MOVAPS.html ├── MOVBE.html ├── MOVDDUP.html ├── MOVDQ2Q.html ├── MOVDQA,VMOVDQA32_64.html ├── MOVDQU,VMOVDQU8_16_32_64.html ├── MOVD_MOVQ.html ├── MOVHLPS.html ├── MOVHPD.html ├── MOVHPS.html ├── MOVLHPS.html ├── MOVLPD.html ├── MOVLPS.html ├── MOVMSKPD.html ├── MOVMSKPS.html ├── MOVNTDQ.html ├── MOVNTDQA.html ├── MOVNTI.html ├── MOVNTPD.html ├── MOVNTPS.html ├── MOVNTQ.html ├── MOVQ.html ├── MOVQ2DQ.html ├── MOVSD.html ├── MOVSHDUP.html ├── MOVSLDUP.html ├── MOVSS.html ├── MOVSX_MOVSXD.html ├── MOVS_MOVSB_MOVSW_MOVSD_MOVSQ.html ├── MOVUPD.html ├── MOVUPS.html ├── MOVZX.html ├── MPSADBW.html ├── MUL.html ├── MULPD.html ├── MULPS.html ├── MULSD.html ├── MULSS.html ├── MULX.html ├── MWAIT.html ├── NEG.html ├── NOP.html ├── NOT.html ├── OR.html ├── ORPD.html ├── ORPS.html ├── OUT.html ├── OUTS_OUTSB_OUTSW_OUTSD.html ├── PABSB_PABSW_PABSD_PABSQ.html ├── PACKSSWB_PACKSSDW.html ├── PACKUSDW.html ├── PACKUSWB.html ├── PADDB_PADDW_PADDD_PADDQ.html ├── PADDSB_PADDSW.html ├── PADDUSB_PADDUSW.html ├── PALIGNR.html ├── PAND.html ├── PANDN.html ├── PAUSE.html ├── PAVGB_PAVGW.html ├── PBLENDVB.html ├── PBLENDW.html ├── PCLMULQDQ.html ├── PCMPEQB_PCMPEQW_PCMPEQD.html ├── PCMPEQQ.html ├── PCMPESTRI.html ├── PCMPESTRM.html ├── PCMPGTB_PCMPGTW_PCMPGTD.html ├── PCMPGTQ.html ├── PCMPISTRI.html ├── PCMPISTRM.html ├── PDEP.html ├── PEXT.html ├── PEXTRB_PEXTRD_PEXTRQ.html ├── PEXTRW.html ├── PHADDSW.html ├── PHADDW_PHADDD.html ├── PHMINPOSUW.html ├── PHSUBSW.html ├── PHSUBW_PHSUBD.html ├── PINSRB_PINSRD_PINSRQ.html ├── PINSRW.html ├── PMADDUBSW.html ├── PMADDWD.html ├── PMAXSB_PMAXSW_PMAXSD_PMAXSQ.html ├── PMAXUB_PMAXUW.html ├── PMAXUD_PMAXUQ.html ├── PMINSB_PMINSW.html ├── PMINSD_PMINSQ.html ├── PMINUB_PMINUW.html ├── PMINUD_PMINUQ.html ├── PMOVMSKB.html ├── PMOVSX.html ├── PMOVZX.html ├── PMULDQ.html ├── PMULHRSW.html ├── PMULHUW.html ├── PMULHW.html ├── PMULLD_PMULLQ.html ├── PMULLW.html ├── PMULUDQ.html ├── POP.html ├── POPA_POPAD.html ├── POPCNT.html ├── POPF_POPFD_POPFQ.html ├── POR.html ├── PREFETCHW.html ├── PREFETCHWT1.html ├── PREFETCHh.html ├── PROLD_PROLVD_PROLQ_PROLVQ.html ├── PRORD_PRORVD_PRORQ_PRORVQ.html ├── PSADBW.html ├── PSHUFB.html ├── PSHUFD.html ├── PSHUFHW.html ├── PSHUFLW.html ├── PSHUFW.html ├── PSIGNB_PSIGNW_PSIGND.html ├── PSLLDQ.html ├── PSLLW_PSLLD_PSLLQ.html ├── PSRAW_PSRAD_PSRAQ.html ├── PSRLDQ.html ├── PSRLW_PSRLD_PSRLQ.html ├── PSUBB_PSUBW_PSUBD.html ├── PSUBQ.html ├── PSUBSB_PSUBSW.html ├── PSUBUSB_PSUBUSW.html ├── PTEST.html ├── PTWRITE.html ├── PUNPCKHBW_PUNPCKHWD_PUNPCKHDQ_PUNPCKHQDQ.html ├── PUNPCKLBW_PUNPCKLWD_PUNPCKLDQ_PUNPCKLQDQ.html ├── PUSH.html ├── PUSHA_PUSHAD.html ├── PUSHF_PUSHFD.html ├── PXOR.html ├── RCL_RCR_ROL_ROR.html ├── RCPPS.html ├── RCPSS.html ├── RDFSBASE_RDGSBASE.html ├── RDMSR.html ├── RDPID.html ├── RDPKRU.html ├── RDPMC.html ├── RDRAND.html ├── RDSEED.html ├── RDTSC.html ├── RDTSCP.html ├── REP_REPE_REPZ_REPNE_REPNZ.html ├── RET.html ├── RORX.html ├── ROUNDPD.html ├── ROUNDPS.html ├── ROUNDSD.html ├── ROUNDSS.html ├── RSM.html ├── RSQRTPS.html ├── RSQRTSS.html ├── SAHF.html ├── SAL_SAR_SHL_SHR.html ├── SARX_SHLX_SHRX.html ├── SBB.html ├── SCAS_SCASB_SCASW_SCASD.html ├── SETcc.html ├── SFENCE.html ├── SGDT.html ├── SHA1MSG1.html ├── SHA1MSG2.html ├── SHA1NEXTE.html ├── SHA1RNDS4.html ├── SHA256MSG1.html ├── SHA256MSG2.html ├── SHA256RNDS2.html ├── SHLD.html ├── SHRD.html ├── SHUFPD.html ├── SHUFPS.html ├── SIDT.html ├── SLDT.html ├── SMSW.html ├── SQRTPD.html ├── SQRTPS.html ├── SQRTSD.html ├── SQRTSS.html ├── STAC.html ├── STC.html ├── STD.html ├── STI.html ├── STMXCSR.html ├── STOS_STOSB_STOSW_STOSD_STOSQ.html ├── STR.html ├── SUB.html ├── SUBPD.html ├── SUBPS.html ├── SUBSD.html ├── SUBSS.html ├── SWAPGS.html ├── SYSCALL.html ├── SYSENTER.html ├── SYSEXIT.html ├── SYSRET.html ├── TEST.html ├── TZCNT.html ├── UCOMISD.html ├── UCOMISS.html ├── UD2.html ├── UNPCKHPD.html ├── UNPCKHPS.html ├── UNPCKLPD.html ├── UNPCKLPS.html ├── VALIGND_VALIGNQ.html ├── VBLENDMPD_VBLENDMPS.html ├── VBROADCAST.html ├── VCOMPRESSPD.html ├── VCOMPRESSPS.html ├── VCVTPD2QQ.html ├── VCVTPD2UDQ.html ├── VCVTPD2UQQ.html ├── VCVTPH2PS.html ├── VCVTPS2PH.html ├── VCVTPS2QQ.html ├── VCVTPS2UDQ.html ├── VCVTPS2UQQ.html ├── VCVTQQ2PD.html ├── VCVTQQ2PS.html ├── VCVTSD2USI.html ├── VCVTSS2USI.html ├── VCVTTPD2QQ.html ├── VCVTTPD2UDQ.html ├── VCVTTPD2UQQ.html ├── VCVTTPS2QQ.html ├── VCVTTPS2UDQ.html ├── VCVTTPS2UQQ.html ├── VCVTTSD2USI.html ├── VCVTTSS2USI.html ├── VCVTUDQ2PD.html ├── VCVTUDQ2PS.html ├── VCVTUQQ2PD.html ├── VCVTUQQ2PS.html ├── VCVTUSI2SD.html ├── VCVTUSI2SS.html ├── VDBPSADBW.html ├── VERR_VERW.html ├── VEXP2PD.html ├── VEXP2PS.html ├── VEXPANDPD.html ├── VEXPANDPS.html ├── VEXTRACTF128_VEXTRACTF32x4_VEXTRACTF64x2_VEXTRACTF32x8_VEXTRACTF64x4.html ├── VEXTRACTI128_VEXTRACTI32x4_VEXTRACTI64x2_VEXTRACTI32x8_VEXTRACTI64x4.html ├── VFIXUPIMMPD.html ├── VFIXUPIMMPS.html ├── VFIXUPIMMSD.html ├── VFIXUPIMMSS.html ├── VFMADD132PD_VFMADD213PD_VFMADD231PD.html ├── VFMADD132PS_VFMADD213PS_VFMADD231PS.html ├── VFMADD132SD_VFMADD213SD_VFMADD231SD.html ├── VFMADD132SS_VFMADD213SS_VFMADD231SS.html ├── VFMADDSUB132PD_VFMADDSUB213PD_VFMADDSUB231PD.html ├── VFMADDSUB132PS_VFMADDSUB213PS_VFMADDSUB231PS.html ├── VFMSUB132PD_VFMSUB213PD_VFMSUB231PD.html ├── VFMSUB132PS_VFMSUB213PS_VFMSUB231PS.html ├── VFMSUB132SD_VFMSUB213SD_VFMSUB231SD.html ├── VFMSUB132SS_VFMSUB213SS_VFMSUB231SS.html ├── VFMSUBADD132PD_VFMSUBADD213PD_VFMSUBADD231PD.html ├── VFMSUBADD132PS_VFMSUBADD213PS_VFMSUBADD231PS.html ├── VFNMADD132PD_VFNMADD213PD_VFNMADD231PD.html ├── VFNMADD132PS_VFNMADD213PS_VFNMADD231PS.html ├── VFNMADD132SD_VFNMADD213SD_VFNMADD231SD.html ├── VFNMADD132SS_VFNMADD213SS_VFNMADD231SS.html ├── VFNMSUB132PD_VFNMSUB213PD_VFNMSUB231PD.html ├── VFNMSUB132PS_VFNMSUB213PS_VFNMSUB231PS.html ├── VFNMSUB132SD_VFNMSUB213SD_VFNMSUB231SD.html ├── VFNMSUB132SS_VFNMSUB213SS_VFNMSUB231SS.html ├── VFPCLASSPD.html ├── VFPCLASSPS.html ├── VFPCLASSSD.html ├── VFPCLASSSS.html ├── VGATHERDPD_VGATHERQPD.html ├── VGATHERDPS_VGATHERDPD.html ├── VGATHERDPS_VGATHERQPS.html ├── VGATHERPF0DPS_VGATHERPF0QPS_VGATHERPF0DPD_VGATHERPF0QPD.html ├── VGATHERPF1DPS_VGATHERPF1QPS_VGATHERPF1DPD_VGATHERPF1QPD.html ├── VGATHERQPS_VGATHERQPD.html ├── VGETEXPPD.html ├── VGETEXPPS.html ├── VGETEXPSD.html ├── VGETEXPSS.html ├── VGETMANTPD.html ├── VGETMANTPS.html ├── VGETMANTSD.html ├── VGETMANTSS.html ├── VINSERTF128_VINSERTF32x4_VINSERTF64x2_VINSERTF32x8_VINSERTF64x4.html ├── VINSERTI128_VINSERTI32x4_VINSERTI64x2_VINSERTI32x8_VINSERTI64x4.html ├── VMASKMOV.html ├── VPBLENDD.html ├── VPBLENDMB_VPBLENDMW.html ├── VPBLENDMD_VPBLENDMQ.html ├── VPBROADCAST.html ├── VPBROADCASTB_W_D_Q.html ├── VPBROADCASTM.html ├── VPCMPB_VPCMPUB.html ├── VPCMPD_VPCMPUD.html ├── VPCMPQ_VPCMPUQ.html ├── VPCMPW_VPCMPUW.html ├── VPCOMPRESSD.html ├── VPCOMPRESSQ.html ├── VPCONFLICTD_Q.html ├── VPERM2F128.html ├── VPERM2I128.html ├── VPERMD_VPERMW.html ├── VPERMI2W_D_Q_PS_PD.html ├── VPERMILPD.html ├── VPERMILPS.html ├── VPERMPD.html ├── VPERMPS.html ├── VPERMQ.html ├── VPEXPANDD.html ├── VPEXPANDQ.html ├── VPGATHERDD_VPGATHERDQ.html ├── VPGATHERDD_VPGATHERQD.html ├── VPGATHERDQ_VPGATHERQQ.html ├── VPGATHERQD_VPGATHERQQ.html ├── VPLZCNTD_Q.html ├── VPMASKMOV.html ├── VPMOVB2M_VPMOVW2M_VPMOVD2M_VPMOVQ2M.html ├── VPMOVDB_VPMOVSDB_VPMOVUSDB.html ├── VPMOVDW_VPMOVSDW_VPMOVUSDW.html ├── VPMOVM2B_VPMOVM2W_VPMOVM2D_VPMOVM2Q.html ├── VPMOVQB_VPMOVSQB_VPMOVUSQB.html ├── VPMOVQD_VPMOVSQD_VPMOVUSQD.html ├── VPMOVQW_VPMOVSQW_VPMOVUSQW.html ├── VPMOVWB_VPMOVSWB_VPMOVUSWB.html ├── VPSCATTERDD_VPSCATTERDQ_VPSCATTERQD_VPSCATTERQQ.html ├── VPSLLVW_VPSLLVD_VPSLLVQ.html ├── VPSRAVW_VPSRAVD_VPSRAVQ.html ├── VPSRLVW_VPSRLVD_VPSRLVQ.html ├── VPTERNLOGD_VPTERNLOGQ.html ├── VPTESTMB_VPTESTMW_VPTESTMD_VPTESTMQ.html ├── VPTESTNMB_W_D_Q.html ├── VRANGEPD.html ├── VRANGEPS.html ├── VRANGESD.html ├── VRANGESS.html ├── VRCP14PD.html ├── VRCP14PS.html ├── VRCP14SD.html ├── VRCP14SS.html ├── VRCP28PD.html ├── VRCP28PS.html ├── VRCP28SD.html ├── VRCP28SS.html ├── VREDUCEPD.html ├── VREDUCEPS.html ├── VREDUCESD.html ├── VREDUCESS.html ├── VRNDSCALEPD.html ├── VRNDSCALEPS.html ├── VRNDSCALESD.html ├── VRNDSCALESS.html ├── VRSQRT14PD.html ├── VRSQRT14PS.html ├── VRSQRT14SD.html ├── VRSQRT14SS.html ├── VRSQRT28PD.html ├── VRSQRT28PS.html ├── VRSQRT28SD.html ├── VRSQRT28SS.html ├── VSCALEFPD.html ├── VSCALEFPS.html ├── VSCALEFSD.html ├── VSCALEFSS.html ├── VSCATTERDPS_VSCATTERDPD_VSCATTERQPS_VSCATTERQPD.html ├── VSCATTERPF0DPS_VSCATTERPF0QPS_VSCATTERPF0DPD_VSCATTERPF0QPD.html ├── VSCATTERPF1DPS_VSCATTERPF1QPS_VSCATTERPF1DPD_VSCATTERPF1QPD.html ├── VSHUFF32x4_VSHUFF64x2_VSHUFI32x4_VSHUFI64x2.html ├── VTESTPD_VTESTPS.html ├── VZEROALL.html ├── VZEROUPPER.html ├── WAIT_FWAIT.html ├── WBINVD.html ├── WRFSBASE_WRGSBASE.html ├── WRMSR.html ├── WRPKRU.html ├── XABORT.html ├── XACQUIRE_XRELEASE.html ├── XADD.html ├── XBEGIN.html ├── XCHG.html ├── XEND.html ├── XGETBV.html ├── XLAT_XLATB.html ├── XOR.html ├── XORPD.html ├── XORPS.html ├── XRSTOR.html ├── XRSTORS.html ├── XSAVE.html ├── XSAVEC.html ├── XSAVEOPT.html ├── XSAVES.html ├── XSETBV.html ├── XTEST.html └── style.css ├── index.html └── parsejson.py /.gitignore: -------------------------------------------------------------------------------- 1 | .* 2 | *.pdf 3 | *.pyc 4 | *.pyo 5 | *.json 6 | pdfminer/* 7 | html/* 8 | **/target/* 9 | -------------------------------------------------------------------------------- /Java/SignatureGenerator/pom.xml: -------------------------------------------------------------------------------- 1 | 2 | 4.0.0 3 | 4 | hjlebbink 5 | SignatureGenerator 6 | 1.0.0-SNAPSHOT 7 | 8 | 9 | 10 | 11 | org.slf4j 12 | slf4j-api 13 | 1.7.16 14 | 15 | 16 | ch.qos.logback 17 | logback-core 18 | 1.1.5 19 | 20 | 21 | ch.qos.logback 22 | logback-classic 23 | 1.1.5 24 | 25 | 26 | 27 | 45 | 46 | -------------------------------------------------------------------------------- /Java/SignatureGenerator/src/main/java/converter/Signature.java: -------------------------------------------------------------------------------- 1 | package converter; 2 | 3 | public class Signature implements Comparable { 4 | public String mnemonic; 5 | public String operands; 6 | public String operandsDoc; 7 | public String cpuFlags; 8 | public String description; 9 | public Signature(String mnemonic, String operands, String cpuFlags, String operandsDoc, String description) { 10 | this.mnemonic = mnemonic; 11 | this.operands = operands; 12 | this.operandsDoc = operandsDoc; 13 | this.cpuFlags = cpuFlags; 14 | this.description = description; 15 | } 16 | public int compareTo(Signature o) { 17 | final int i1 = this.mnemonic.compareTo(o.mnemonic); 18 | if (i1 != 0) return i1; 19 | return this.operands.compareTo(o.operands); 20 | } 21 | } 22 | 23 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | The MIT License (MIT) 2 | 3 | Copyright (c) 2016 Henk-Jan Lebbink 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Python/extract.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | # -*- coding: UTF-8 -*- 3 | 4 | import sys 5 | from pdfminer.pdfdocument import PDFDocument 6 | from pdfminer.pdfparser import PDFParser 7 | from pdfminer.pdfinterp import PDFResourceManager, PDFPageInterpreter 8 | from pdfminer.pdfpage import PDFPage 9 | from pdfminer.layout import LAParams 10 | from pdfminer.converter import PDFPageAggregator 11 | from x86manual import x86ManParser 12 | 13 | def main(argv): 14 | for arg in argv[1:]: 15 | fd = open(arg) 16 | parser = PDFParser(fd) 17 | document = PDFDocument(parser) 18 | if not document.is_extractable: 19 | print "Document not extractable." 20 | return 1 21 | 22 | params = LAParams(char_margin=1) 23 | resMan = PDFResourceManager(caching=True) 24 | device = PDFPageAggregator(resMan, laparams=params) 25 | interpreter = PDFPageInterpreter(resMan, device) 26 | parser = x86ManParser("html", params) 27 | 28 | i = 1 29 | for page in PDFPage.get_pages(fd, set(), caching=True, check_extractable=True): 30 | print "Processing page %i" % i 31 | interpreter.process_page(page) 32 | page = device.get_result() 33 | parser.process_page(page) 34 | i += 1 35 | parser.flush() 36 | fd.close() 37 | 38 | print "Conversion result: %i/%i" % (parser.success, parser.success + parser.fail) 39 | 40 | with open("opcodes.json", "wb") as fd: 41 | fd.write(parser.output_opcodes_json()) 42 | 43 | if __name__ == "__main__": 44 | result = main(sys.argv) 45 | sys.exit(result) 46 | -------------------------------------------------------------------------------- /Python/html/style.css: -------------------------------------------------------------------------------- 1 | table { border-collapse: collapse } 2 | th, td { padding: 0px 10px; border: 1px #ddd solid; vertical-align: top } 3 | svg { display: block; margin: 0px auto } 4 | svg + h3 { text-align: center; } 5 | 6 | .notes { font-size: 9pt; } -------------------------------------------------------------------------------- /html/AAA.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | AAA—ASCII Adjust After Addition 8 | 9 |

AAA—ASCII Adjust After Addition

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-bit ModeCompat/Leg ModeDescription
37AAANPInvalidValidASCII adjust AL after addition.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Adjusts the sum of two unpacked BCD values to create an unpacked BCD result. The AL register is the implied source and destination operand for this instruction. The AAA instruction is only useful when it follows an ADD instruction that adds (binary addition) two unpacked BCD values and stores a byte result in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result.

41 |

If the addition produces a decimal carry, the AH register increments by 1, and the CF and AF flags are set. If there was no decimal carry, the CF and AF flags are cleared and the AH register is unchanged. In either case, bits 4 through 7 of the AL register are set to 0.

42 |

This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.

43 |

Operation

44 | 
IF 64-Bit Mode
45 |     THEN
46 |          #UD;
47 |     ELSE
48 |          IF ((AL AND 0FH) > 9) or (AF = 1)
49 |               THEN
50 |                     AX ← AX + 106H;
51 |                     AF ← 1;
52 |                     CF ← 1;
53 |               ELSE
54 |                     AF ← 0;
55 |                     CF ← 0;
56 |          FI;
57 |          AL ← AL AND 0FH;
58 | FI;
59 |

Flags Affected

60 |

The AF and CF flags are set to 1 if the adjustment results in a decimal carry; otherwise they are set to 0. The OF, SF, ZF, and PF flags are undefined.

61 |

Protected Mode Exceptions

62 | 63 | 64 | 65 |
#UDIf the LOCK prefix is used.
66 |

Real-Address Mode Exceptions

67 |

Same exceptions as protected mode.

68 |

Virtual-8086 Mode Exceptions

69 |

Same exceptions as protected mode.

70 |

Compatibility Mode Exceptions

71 |

Same exceptions as protected mode.

72 |

64-Bit Mode Exceptions

73 | 74 | 75 | 76 |
#UDIf in 64-bit mode.
-------------------------------------------------------------------------------- /html/AAS.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | AAS—ASCII Adjust AL After Subtraction 8 | 9 |

AAS—ASCII Adjust AL After Subtraction

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-bit ModeCompat/Leg ModeDescription
3FAASNPInvalidValidASCII adjust AL after subtraction.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Adjusts the result of the subtraction of two unpacked BCD values to create a unpacked BCD result. The AL register is the implied source and destination operand for this instruction. The AAS instruction is only useful when it follows a SUB instruction that subtracts (binary subtraction) one unpacked BCD value from another and stores a byte result in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result.

41 |

If the subtraction produced a decimal carry, the AH register decrements by 1, and the CF and AF flags are set. If no decimal carry occurred, the CF and AF flags are cleared, and the AH register is unchanged. In either case, the AL register is left with its top four bits set to 0.

42 |

This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.

43 |

Operation

44 | 
IF 64-bit mode
45 |     THEN
46 |          #UD;
47 |     ELSE
48 |          IF ((AL AND 0FH) > 9) or (AF = 1)
49 |               THEN
50 |                     AX ← AX – 6;
51 |                     AH ← AH – 1;
52 |                     AF ← 1;
53 |                     CF ← 1;
54 |                     AL ← AL AND 0FH;
55 |               ELSE
56 |                     CF ← 0;
57 |                     AF ← 0;
58 |                     AL ← AL AND 0FH;
59 |          FI;
60 | FI;
61 |

Flags Affected

62 |

The AF and CF flags are set to 1 if there is a decimal borrow; otherwise, they are cleared to 0. The OF, SF, ZF, and PF flags are undefined.

63 |

Protected Mode Exceptions

64 | 65 | 66 | 67 |
#UDIf the LOCK prefix is used.
68 |

Real-Address Mode Exceptions

69 |

Same exceptions as protected mode.

70 |

Virtual-8086 Mode Exceptions

71 |

Same exceptions as protected mode.

72 |

Compatibility Mode Exceptions

73 |

Same exceptions as protected mode.

74 |

64-Bit Mode Exceptions

75 | 76 | 77 | 78 |
#UDIf in 64-bit mode.
-------------------------------------------------------------------------------- /html/AESDEC.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | AESDEC—Perform One Round of an AES Decryption Flow 8 | 9 |

AESDEC—Perform One Round of an AES Decryption Flow

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 |
Opcode/InstructionOp/En64/32-bit ModeCPUID Feature FlagDescription
66 0F 38 DE /r AESDEC xmm1, xmm2/m128RMV/VAESPerform one round of an AES decryption flow, using the Equivalent Inverse Cipher, operating on a 128-bit data (state) from xmm1 with a 128-bit round key from xmm2/m128.
VEX.NDS.128.66.0F38.WIG DE /r VAESDEC xmm1, xmm2, xmm3/m128RVMV/VBoth AES and AVX flagsPerform one round of an AES decryption flow, using the Equivalent Inverse Cipher, operating on a 128-bit data (state) from xmm2 with a 128-bit round key from xmm3/m128; store the result in xmm1.
29 |

Instruction Operand Encoding

30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 |
Op/EnOperand 1Operand2Operand3Operand4
RMModRM:reg (r, w)ModRM:r/m (r)NANA
RVMModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NA
49 |

Description

50 |

This instruction performs a single round of the AES decryption flow using the Equivalent Inverse Cipher, with the round key from the second source operand, operating on a 128-bit data (state) from the first source operand, and store the result in the destination operand.

51 |

Use the AESDEC instruction for all but the last decryption round. For the last decryption round, use the AESDE-CLAST instruction.

52 |

128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an XMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.

53 |

VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.

54 |

Operation

55 |

AESDEC

56 | 
STATE ← SRC1;
57 | RoundKey ← SRC2;
58 | STATE ← InvShiftRows( STATE );
59 | STATE ← InvSubBytes( STATE );
60 | STATE ← InvMixColumns( STATE );
61 | DEST[127:0] ← STATE XOR RoundKey;
62 | DEST[VLMAX-1:128] (Unmodified)
63 |

VAESDEC

64 | 
STATE ← SRC1;
65 | RoundKey ← SRC2;
66 | STATE ← InvShiftRows( STATE );
67 | STATE ← InvSubBytes( STATE );
68 | STATE ← InvMixColumns( STATE );
69 | DEST[127:0] ← STATE XOR RoundKey;
70 | DEST[VLMAX-1:128] ← 0
71 |

Intel C/C++ Compiler Intrinsic Equivalent

72 |

(V)AESDEC:

73 |

__m128i _mm_aesdec (__m128i, __m128i)

74 |

SIMD Floating-Point Exceptions

75 |

None

76 |

Other Exceptions

77 |

See Exceptions Type 4.

-------------------------------------------------------------------------------- /html/AESDECLAST.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | AESDECLAST—Perform Last Round of an AES Decryption Flow 8 | 9 |

AESDECLAST—Perform Last Round of an AES Decryption Flow

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 |
Opcode/InstructionOp/En64/32-bit ModeCPUID Feature FlagDescription
66 0F 38 DF /r AESDECLAST xmm1, xmm2/m128RMV/VAESPerform the last round of an AES decryption flow, using the Equivalent Inverse Cipher, operating on a 128-bit data (state) from xmm1 with a 128-bit round key from xmm2/m128.
VEX.NDS.128.66.0F38.WIG DF /r VAESDECLAST xmm1, xmm2, xmm3/m128RVMV/VBoth AES and AVX flagsPerform the last round of an AES decryption flow, using the Equivalent Inverse Cipher, operating on a 128-bit data (state) from xmm2 with a 128-bit round key from xmm3/m128; store the result in xmm1.
29 |

Instruction Operand Encoding

30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 |
Op/EnOperand 1Operand2Operand3Operand4
RMModRM:reg (r, w)ModRM:r/m (r)NANA
RVMModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NA
49 |

Description

50 |

This instruction performs the last round of the AES decryption flow using the Equivalent Inverse Cipher, with the round key from the second source operand, operating on a 128-bit data (state) from the first source operand, and store the result in the destination operand.

51 |

128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an XMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.

52 |

VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.

53 |

Operation

54 |

AESDECLAST

55 | 
STATE ← SRC1;
56 | RoundKey ← SRC2;
57 | STATE ← InvShiftRows( STATE );
58 | STATE ← InvSubBytes( STATE );
59 | DEST[127:0] ← STATE XOR RoundKey;
60 | DEST[VLMAX-1:128] (Unmodified)
61 |

VAESDECLAST

62 | 
STATE ← SRC1;
63 | RoundKey ← SRC2;
64 | STATE ← InvShiftRows( STATE );
65 | STATE ← InvSubBytes( STATE );
66 | DEST[127:0] ← STATE XOR RoundKey;
67 | DEST[VLMAX-1:128] ← 0
68 |

Intel C/C++ Compiler Intrinsic Equivalent

69 |

(V)AESDECLAST:

70 |

__m128i _mm_aesdeclast (__m128i, __m128i)

71 |

SIMD Floating-Point Exceptions

72 |

None

73 |

Other Exceptions

74 |

See Exceptions Type 4.

-------------------------------------------------------------------------------- /html/AESENC.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | AESENC—Perform One Round of an AES Encryption Flow 8 | 9 |

AESENC—Perform One Round of an AES Encryption Flow

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 |
Opcode/InstructionOp/En64/32-bit ModeCPUID Feature FlagDescription
66 0F 38 DC /r AESENC xmm1, xmm2/m128RMV/VAESPerform one round of an AES encryption flow, operating on a 128-bit data (state) from xmm1 with a 128-bit round key from xmm2/m128.
VEX.NDS.128.66.0F38.WIG DC /r VAESENC xmm1, xmm2, xmm3/m128RVMV/VBoth AES and AVX flagsPerform one round of an AES encryption flow, operating on a 128-bit data (state) from xmm2 with a 128-bit round key from the xmm3/m128; store the result in xmm1.
29 |

Instruction Operand Encoding

30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 |
Op/EnOperand 1Operand2Operand3Operand4
RMModRM:reg (r, w)ModRM:r/m (r)NANA
RVMModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NA
49 |

Description

50 |

This instruction performs a single round of an AES encryption flow using a round key from the second source operand, operating on 128-bit data (state) from the first source operand, and store the result in the destination operand.

51 |

Use the AESENC instruction for all but the last encryption rounds. For the last encryption round, use the AESENC-CLAST instruction.

52 |

128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an XMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.

53 |

VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.

54 |

Operation

55 |

AESENC

56 | 
STATE ← SRC1;
57 | RoundKey ← SRC2;
58 | STATE ← ShiftRows( STATE );
59 | STATE ← SubBytes( STATE );
60 | STATE ← MixColumns( STATE );
61 | DEST[127:0] ← STATE XOR RoundKey;
62 | DEST[VLMAX-1:128] (Unmodified)
63 |

VAESENC

64 | 
STATE (cid:197) SRC1;
65 | RoundKey (cid:197) SRC2;
66 | STATE (cid:197) ShiftRows( STATE );
67 | STATE (cid:197) SubBytes( STATE );
68 | STATE (cid:197) MixColumns( STATE );
69 | DEST[127:0] (cid:197) STATE XOR RoundKey;
70 | DEST[VLMAX-1:128] (cid:197) 0
71 |

Intel C/C++ Compiler Intrinsic Equivalent

72 |

(V)AESENC:

73 |

__m128i _mm_aesenc (__m128i, __m128i)

74 |

SIMD Floating-Point Exceptions

75 |

None

76 |

Other Exceptions

77 |

See Exceptions Type 4.

-------------------------------------------------------------------------------- /html/AESENCLAST.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | AESENCLAST—Perform Last Round of an AES Encryption Flow 8 | 9 |

AESENCLAST—Perform Last Round of an AES Encryption Flow

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 |
Opcode/InstructionOp/En64/32-bit ModeCPUID Feature FlagDescription
66 0F 38 DD /r AESENCLAST xmm1, xmm2/m128RMV/VAESPerform the last round of an AES encryption flow, operating on a 128-bit data (state) from xmm1 with a 128-bit round key from xmm2/m128.
VEX.NDS.128.66.0F38.WIG DD /r VAESENCLAST xmm1, xmm2, xmm3/m128RVMV/VBoth AES and AVX flagsPerform the last round of an AES encryption flow, operating on a 128-bit data (state) from xmm2 with a 128 bit round key from xmm3/m128; store the result in xmm1.
29 |

Instruction Operand Encoding

30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 |
Op/EnOperand 1Operand2Operand3Operand4
RMModRM:reg (r, w)ModRM:r/m (r)NANA
RVMModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NA
49 |

Description

50 |

This instruction performs the last round of an AES encryption flow using a round key from the second source operand, operating on 128-bit data (state) from the first source operand, and store the result in the destination operand.

51 |

128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an XMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.

52 |

VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.

53 |

Operation

54 |

AESENCLAST

55 | 
STATE ← SRC1;
56 | RoundKey ← SRC2;
57 | STATE ← ShiftRows( STATE );
58 | STATE ← SubBytes( STATE );
59 | DEST[127:0] ← STATE XOR RoundKey;
60 | DEST[VLMAX-1:128] (Unmodified)
61 |

VAESENCLAST

62 | 
STATE (cid:197) SRC1;
63 | RoundKey (cid:197) SRC2;
64 | STATE (cid:197) ShiftRows( STATE );
65 | STATE (cid:197) SubBytes( STATE );
66 | DEST[127:0] (cid:197) STATE XOR RoundKey;
67 | DEST[VLMAX-1:128] (cid:197) 0
68 |

Intel C/C++ Compiler Intrinsic Equivalent

69 |

(V)AESENCLAST:

70 |

__m128i _mm_aesenclast (__m128i, __m128i)

71 |

SIMD Floating-Point Exceptions

72 |

None

73 |

Other Exceptions

74 |

See Exceptions Type 4.

-------------------------------------------------------------------------------- /html/AESIMC.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | AESIMC—Perform the AES InvMixColumn Transformation 8 | 9 |

AESIMC—Perform the AES InvMixColumn Transformation

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 |
Opcode/InstructionOp/En64/32-bit ModeCPUID Feature FlagDescription
66 0F 38 DB /r AESIMC xmm1, xmm2/m128RMV/VAESPerform the InvMixColumn transformation on a 128-bit round key from xmm2/m128 and store the result in xmm1.
VEX.128.66.0F38.WIG DB /r VAESIMC xmm1, xmm2/m128RMV/VBoth AES and AVX flagsPerform the InvMixColumn transformation on a 128-bit round key from xmm2/m128 and store the result in xmm1.
29 |

Instruction Operand Encoding

30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 |
Op/EnOperand 1Operand2Operand3Operand4
RMModRM:reg (w)ModRM:r/m (r)NANA
43 |

Description

44 |

Perform the InvMixColumns transformation on the source operand and store the result in the destination operand. The destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory loca-tion.

45 |

Note: the AESIMC instruction should be applied to the expanded AES round keys (except for the first and last round key) in order to prepare them for decryption using the “Equivalent Inverse Cipher” (defined in FIPS 197).

46 |

128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.

47 |

VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.

48 |

Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

49 |

Operation

50 |

AESIMC

51 | 
DEST[127:0] ← InvMixColumns( SRC );
52 | DEST[VLMAX-1:128] (Unmodified)
53 |

VAESIMC

54 | 
DEST[127:0] (cid:197) InvMixColumns( SRC );
55 | DEST[VLMAX-1:128] (cid:197) 0;
56 |

Intel C/C++ Compiler Intrinsic Equivalent

57 |

(V)AESIMC:

58 |

__m128i _mm_aesimc (__m128i)

59 |

SIMD Floating-Point Exceptions

60 |

None

61 |

Other Exceptions

62 |

See Exceptions Type 4; additionally

63 | 64 | 65 | 66 |
#UDIf VEX.vvvv ≠ 1111B.
-------------------------------------------------------------------------------- /html/ANDN.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | ANDN — Logical AND NOT 8 | 9 |

ANDN — Logical AND NOT

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 |
Opcode/InstructionOp/En64/32 -bit ModeCPUID Feature FlagDescription
VEX.NDS.LZ.0F38.W0 F2 /r ANDN r32a, r32b, r/m32RVMV/VBMI1Bitwise AND of inverted r32b with r/m32, store result in r32a.
VEX.NDS.LZ. 0F38.W1 F2 /r ANDN r64a, r64b, r/m64RVMV/NEBMI1Bitwise AND of inverted r64b with r/m64, store result in r64a.
29 |

Instruction Operand Encoding

30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RVMModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NA
43 |

Description

44 |

Performs a bitwise logical AND of inverted second operand (the first source operand) with the third operand (the second source operand). The result is stored in the first operand (destination operand).

45 |

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

46 |

Operation

47 | 
DEST ← (NOT SRC1) bitwiseAND SRC2;
48 | SF ← DEST[OperandSize -1];
49 | ZF ← (DEST = 0);
50 |

Flags Affected

51 |

SF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined.

52 |

Intel C/C++ Compiler Intrinsic Equivalent

53 |

Auto-generated from high-level language.

54 |

SIMD Floating-Point Exceptions

55 |

None

56 |

Other Exceptions

57 |

See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally

58 | 59 | 60 | 61 |
#UDIf VEX.W = 1.
-------------------------------------------------------------------------------- /html/BLSI.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | BLSI — Extract Lowest Set Isolated Bit 8 | 9 |

BLSI — Extract Lowest Set Isolated Bit

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 |
Opcode/InstructionOp/En64/32 -bit ModeCPUID Feature FlagDescription
VEX.NDD.LZ.0F38.W0 F3 /3 BLSI r32, r/m32VMV/VBMI1Extract lowest set bit from r/m32 and set that bit in r32.
VEX.NDD.LZ.0F38.W1 F3 /3 BLSI r64, r/m64VMV/N.E.BMI1Extract lowest set bit from r/m64, and set that bit in r64.
29 |

Instruction Operand Encoding

30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 |
Op/EnOperand 1Operand 2Operand 3Operand 4
VMVEX.vvvv (w)ModRM:r/m (r)NANA
43 |

Description

44 |

Extracts the lowest set bit from the source operand and set the corresponding bit in the destination register. All other bits in the destination operand are zeroed. If no bits are set in the source operand, BLSI sets all the bits in the destination to 0 and sets ZF and CF.

45 |

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

46 |

Operation

47 | 
temp ← (-SRC) bitwiseAND (SRC);
48 | SF ← temp[OperandSize -1];
49 | ZF ← (temp = 0);
50 | IF SRC = 0
51 |     CF ← 0;
52 | ELSE
53 |     CF ← 1;
54 | FI
55 | DEST ← temp;
56 |

Flags Affected

57 |

ZF and SF are updated based on the result. CF is set if the source is not zero. OF flags are cleared. AF and PF flags are undefined.

58 |

Intel C/C++ Compiler Intrinsic Equivalent

59 |

BLSI:

60 |

unsigned __int32 _blsi_u32(unsigned __int32 src);

61 |

BLSI:

62 |

unsigned __int64 _blsi_u64(unsigned __int64 src);

63 |

SIMD Floating-Point Exceptions

64 |

None

65 |

Other Exceptions

66 |

See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally

67 | 68 | 69 | 70 |
#UDIf VEX.W = 1.
-------------------------------------------------------------------------------- /html/BLSMSK.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | BLSMSK — Get Mask Up to Lowest Set Bit 8 | 9 |

BLSMSK — Get Mask Up to Lowest Set Bit

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 |
Opcode/InstructionOp/En64/32 -bit ModeCPUID Feature FlagDescription
VEX.NDD.LZ.0F38.W0 F3 /2 BLSMSK r32, r/m32VMV/VBMI1Set all lower bits in r32 to “1” starting from bit 0 to lowest set bit in r/m32.
VEX.NDD.LZ.0F38.W1 F3 /2 BLSMSK r64, r/m64VMV/N.E.BMI1Set all lower bits in r64 to “1” starting from bit 0 to lowest set bit in r/m64.
29 |

Instruction Operand Encoding

30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 |
Op/EnOperand 1Operand 2Operand 3Operand 4
VMVEX.vvvv (w)ModRM:r/m (r)NANA
43 |

Description

44 |

Sets all the lower bits of the destination operand to “1” up to and including lowest set bit (=1) in the source operand. If source operand is zero, BLSMSK sets all bits of the destination operand to 1 and also sets CF to 1.

45 |

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

46 |

Operation

47 | 
temp ← (SRC-1) XOR (SRC) ;
48 | SF ← temp[OperandSize -1];
49 | ZF ← 0;
50 | IF SRC = 0
51 |     CF ← 1;
52 | ELSE
53 |     CF ← 0;
54 | FI
55 | DEST ← temp;
56 |

Flags Affected

57 |

SF is updated based on the result. CF is set if the source if zero. ZF and OF flags are cleared. AF and PF flag are undefined.

58 |

Intel C/C++ Compiler Intrinsic Equivalent

59 |

BLSMSK:

60 |

unsigned __int32 _blsmsk_u32(unsigned __int32 src);

61 |

BLSMSK:

62 |

unsigned __int64 _blsmsk_u64(unsigned __int64 src);

63 |

SIMD Floating-Point Exceptions

64 |

None

65 |

Other Exceptions

66 |

See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally

67 | 68 | 69 | 70 |
#UDIf VEX.W = 1.
-------------------------------------------------------------------------------- /html/BLSR.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | BLSR — Reset Lowest Set Bit 8 | 9 |

BLSR — Reset Lowest Set Bit

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 |
Opcode/InstructionOp/En64/32 -bit ModeCPUID Feature FlagDescription
VEX.NDD.LZ.0F38.W0 F3 /1 BLSR r32, r/m32VMV/VBMI1Reset lowest set bit of r/m32, keep all other bits of r/m32 and write result to r32.
VEX.NDD.LZ.0F38.W1 F3 /1 BLSR r64, r/m64VMV/N.E.BMI1Reset lowest set bit of r/m64, keep all other bits of r/m64 and write result to r64.
29 |

Instruction Operand Encoding

30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 |
Op/EnOperand 1Operand 2Operand 3Operand 4
VMVEX.vvvv (w)ModRM:r/m (r)NANA
43 |

Description

44 |

Copies all bits from the source operand to the destination operand and resets (=0) the bit position in the destina-tion operand that corresponds to the lowest set bit of the source operand. If the source operand is zero BLSR sets CF.

45 |

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

46 |

Operation

47 | 
temp ← (SRC-1) bitwiseAND ( SRC );
48 | SF ← temp[OperandSize -1];
49 | ZF ← (temp = 0);
50 | IF SRC = 0
51 |     CF ← 1;
52 | ELSE
53 |     CF ← 0;
54 | FI
55 | DEST ← temp;
56 |

Flags Affected

57 |

ZF and SF flags are updated based on the result. CF is set if the source is zero. OF flag is cleared. AF and PF flags are undefined.

58 |

Intel C/C++ Compiler Intrinsic Equivalent

59 |

BLSR:

60 |

unsigned __int32 _blsr_u32(unsigned __int32 src);

61 |

BLSR:

62 |

unsigned __int64 _blsr_u64(unsigned __int64 src);

63 |

SIMD Floating-Point Exceptions

64 |

None

65 |

Other Exceptions

66 |

See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally

67 | 68 | 69 | 70 |
#UDIf VEX.W = 1.
-------------------------------------------------------------------------------- /html/BSWAP.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | BSWAP—Byte Swap 8 | 9 |

BSWAP—Byte Swap

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 |
OpcodeInstructionOp/En64-bit ModeCompat/Leg ModeDescription
0F C8+rdBSWAP r32OValid*ValidReverses the byte order of a 32-bit register.
REX.W + 0F C8+rdBSWAP r64OValidN.E.Reverses the byte order of a 64-bit register.
32 |

NOTES:

33 |

*

34 |

See IA-32 Architecture Compatibility section below.

35 |

Instruction Operand Encoding

36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 |
Op/EnOperand 1Operand 2Operand 3Operand 4
Oopcode + rd (r, w)NANANA
49 |

Description

50 |

Reverses the byte order of a 32-bit or 64-bit (destination) register. This instruction is provided for converting little-endian values to big-endian format and vice versa. To swap bytes in a word value (16-bit register), use the XCHG instruction. When the BSWAP instruction references a 16-bit register, the result is undefined.

51 |

In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.

52 |

IA-32 Architecture Legacy Compatibility

53 |

The BSWAP instruction is not supported on IA-32 processors earlier than the Intel486™ processor family. For compatibility with this instruction, software should include functionally equivalent code for execution on Intel processors earlier than the Intel486 processor family.

54 |

Operation

55 | 
TEMP ← DEST
56 | IF 64-bit mode AND OperandSize = 64
57 |     THEN
58 |          DEST[7:0] ← TEMP[63:56];
59 |          DEST[15:8] ← TEMP[55:48];
60 |          DEST[23:16] ← TEMP[47:40];
61 |          DEST[31:24] ← TEMP[39:32];
62 |          DEST[39:32] ← TEMP[31:24];
63 |          DEST[47:40] ← TEMP[23:16];
64 |          DEST[55:48] ← TEMP[15:8];
65 |          DEST[63:56] ← TEMP[7:0];
66 |     ELSE
67 |          DEST[7:0] ← TEMP[31:24];
68 |          DEST[15:8] ← TEMP[23:16];
69 |          DEST[23:16] ← TEMP[15:8];
70 |          DEST[31:24] ← TEMP[7:0];
71 | FI;
72 |

Flags Affected

73 |

None.

74 |

Exceptions (All Operating Modes)

75 |

#UD

76 |

If the LOCK prefix is used.

-------------------------------------------------------------------------------- /html/BZHI.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | BZHI — Zero High Bits Starting with Specified Bit Position 8 | 9 |

BZHI — Zero High Bits Starting with Specified Bit Position

10 | 11 | 12 | 16 | 20 | 24 | 28 |
13 |

Opcode/Instruction

14 |

VEX.NDS1.LZ.0F38.W0 F5 /r BZHI r32a, r/m32, r32b

15 |

VEX.NDS1.LZ.0F38.W1 F5 /r BZHI r64a, r/m64, r64b

 17 |

Op/En

18 |

RMV

19 |

RMV

 21 |

64/32 -bit Mode

22 |

V/V

23 |

V/N.E.

 25 |

CPUID Feature Flag

26 |

BMI2

27 |

BMI2

 29 |

Description

30 |

Zero bits in r/m32 starting with the position in r32b, write result to r32a.

31 |

Zero bits in r/m64 starting with the position in r64b, write result to r64a.

32 |

NOTES:

33 |

1. ModRM:r/m is used to encode the first source operand (second operand) and VEX.vvvv encodes the second source operand (third

34 |

operand).

35 |

Instruction Operand Encoding

36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RMVModRM:reg (w)ModRM:r/m (r)VEX.vvvv (r)NA
49 |

Description

50 |

BZHI copies the bits of the first source operand (the second operand) into the destination operand (the first operand) and clears the higher bits in the destination according to the INDEX value specified by the second source operand (the third operand). The INDEX is specified by bits 7:0 of the second source operand. The INDEX value is saturated at the value of OperandSize -1. CF is set, if the number contained in the 8 low bits of the third operand is greater than OperandSize -1.

51 |

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

52 |

Operation

53 | 
N ← SRC2[7:0]
54 | DEST ← SRC1
55 | IF (N < OperandSize)
56 |     DEST[OperandSize-1:N] ← 0
57 | FI
58 | IF (N > OperandSize - 1)
59 |     CF ← 1
60 | ELSE
61 |     CF ← 0
62 | FI
63 |

Flags Affected

64 |

ZF, CF and SF flags are updated based on the result. OF flag is cleared. AF and PF flags are undefined.

65 |

Intel C/C++ Compiler Intrinsic Equivalent

66 |

BZHI:

67 |

unsigned __int32 _bzhi_u32(unsigned __int32 src, unsigned __int32 index);

68 |

BZHI:

69 |

unsigned __int64 _bzhi_u64(unsigned __int64 src, unsigned __int32 index);

70 |

SIMD Floating-Point Exceptions

71 |

None

72 |

Other Exceptions

73 |

See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally

74 | 75 | 76 | 77 |
#UDIf VEX.W = 1.
-------------------------------------------------------------------------------- /html/CBW_CWDE_CDQE.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword 8 | 9 |

CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
OpcodeInstructionOp/En64-bit ModeCompat/Leg ModeDescription
98CBWNPValidValidAX ← sign-extend of AL.
98CWDENPValidValidEAX ← sign-extend of AX.
REX.W + 98CDQENPValidN.E.RAX ← sign-extend of EAX.
39 |

Instruction Operand Encoding

40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
53 |

Description

54 |

Double the size of the source operand by means of sign extension. The CBW (convert byte to word) instruction copies the sign (bit 7) in the source operand into every bit in the AH register. The CWDE (convert word to double-word) instruction copies the sign (bit 15) of the word in the AX register into the high 16 bits of the EAX register.

55 |

CBW and CWDE reference the same opcode. The CBW instruction is intended for use when the operand-size attri-bute is 16; CWDE is intended for use when the operand-size attribute is 32. Some assemblers may force the operand size. Others may treat these two mnemonics as synonyms (CBW/CWDE) and use the setting of the operand-size attribute to determine the size of values to be converted.

56 |

In 64-bit mode, the default operation size is the size of the destination register. Use of the REX.W prefix promotes this instruction (CDQE when promoted) to operate on 64-bit operands. In which case, CDQE copies the sign (bit 31) of the doubleword in the EAX register into the high 32 bits of RAX.

57 |

Operation

58 | 
IF OperandSize = 16 (* Instruction = CBW *)
59 |     THEN
60 |          AX ← SignExtend(AL);
61 |     ELSE IF (OperandSize = 32, Instruction = CWDE)
62 |          EAX ← SignExtend(AX); FI;
63 |     ELSE (* 64-Bit Mode, OperandSize = 64, Instruction = CDQE*)
64 |          RAX ← SignExtend(EAX);
65 | FI;
66 |

Flags Affected

67 |

None.

68 |

Exceptions (All Operating Modes)

69 |

#UD

70 |

If the LOCK prefix is used.

-------------------------------------------------------------------------------- /html/CLAC.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | CLAC—Clear AC Flag in EFLAGS Register 8 | 9 |

CLAC—Clear AC Flag in EFLAGS Register

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-bit ModeCompat/Leg ModeDescription
0F 01 CACLACNPValidValidClear the AC flag in the EFLAGS register.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Clears the AC flag bit in EFLAGS register. This disables any alignment checking of user-mode data accesses. If the SMAP bit is set in the CR4 register, this disallows explicit supervisor-mode data accesses to user-mode pages.

41 |

This instruction's operation is the same in non-64-bit modes and 64-bit mode. Attempts to execute CLAC when CPL > 0 cause #UD.

42 |

Operation

43 | 
EFLAGS.AC ← 0;
44 |

Flags Affected

45 |

AC cleared. Other flags are unaffected.

46 |

Protected Mode Exceptions

47 | 48 | 49 | 50 |
#UD 51 |

If the LOCK prefix is used.

52 |

If the CPL > 0.

53 |

If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

54 |

Real-Address Mode Exceptions

55 | 56 | 57 | 58 |
#UD 59 |

If the LOCK prefix is used.

60 |

If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

61 |

Virtual-8086 Mode Exceptions

62 | 63 | 64 | 65 |
#UDThe CLAC instruction is not recognized in virtual-8086 mode.
66 |

Compatibility Mode Exceptions

67 | 68 | 69 | 70 |
#UD 71 |

If the LOCK prefix is used.

72 |

If the CPL > 0.

73 |

If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

74 |

64-Bit Mode Exceptions

75 | 76 | 77 | 78 |
#UD 79 |

If the LOCK prefix is used.

80 |

If the CPL > 0.

81 |

If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

-------------------------------------------------------------------------------- /html/CLC.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | CLC—Clear Carry Flag 8 | 9 |

CLC—Clear Carry Flag

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-bit ModeCompat/Leg ModeDescription
F8CLCNPValidValidClear CF flag.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Clears the CF flag in the EFLAGS register. Operation is the same in all modes.

41 |

Operation

42 | 
CF ← 0;
43 |

Flags Affected

44 |

The CF flag is set to 0. The OF, ZF, SF, AF, and PF flags are unaffected.

45 |

Exceptions (All Operating Modes)

46 |

#UD

47 |

If the LOCK prefix is used.

-------------------------------------------------------------------------------- /html/CLD.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | CLD—Clear Direction Flag 8 | 9 |

CLD—Clear Direction Flag

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-bit ModeCompat/Leg ModeDescription
FCCLDNPValidValidClear DF flag.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Clears the DF flag in the EFLAGS register. When the DF flag is set to 0, string operations increment the index regis-ters (ESI and/or EDI). Operation is the same in all modes.

41 |

Operation

42 | 
DF ← 0;
43 |

Flags Affected

44 |

The DF flag is set to 0. The CF, OF, ZF, SF, AF, and PF flags are unaffected.

45 |

Exceptions (All Operating Modes)

46 |

#UD

47 |

If the LOCK prefix is used.

-------------------------------------------------------------------------------- /html/CLTS.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | CLTS—Clear Task-Switched Flag in CR0 8 | 9 |

CLTS—Clear Task-Switched Flag in CR0

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-bit ModeCompat/Leg ModeDescription
0F 06CLTSNPValidValidClears TS flag in CR0.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Clears the task-switched (TS) flag in the CR0 register. This instruction is intended for use in operating-system procedures. It is a privileged instruction that can only be executed at a CPL of 0. It is allowed to be executed in real-address mode to allow initialization for protected mode.

41 |

The processor sets the TS flag every time a task switch occurs. The flag is used to synchronize the saving of FPU context in multitasking applications. See the description of the TS flag in the section titled “Control Registers” in Chapter 2 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information about this flag.

42 |

CLTS operation is the same in non-64-bit modes and 64-bit mode.

43 |

See Chapter 25, “VMX Non-Root Operation,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, for more information about the behavior of this instruction in VMX non-root operation.

44 |

Operation

45 | 
CR0.TS[bit 3] ← 0;
46 |

Flags Affected

47 |

The TS flag in CR0 register is cleared.

48 |

Protected Mode Exceptions

49 | 50 | 51 | 52 | 53 | 54 | 55 |
#GP(0)If the current privilege level is not 0.
#UDIf the LOCK prefix is used.
56 |

Real-Address Mode Exceptions

57 | 58 | 59 | 60 |
#UDIf the LOCK prefix is used.
61 |

Virtual-8086 Mode Exceptions

62 | 63 | 64 | 65 | 66 | 67 | 68 |
#GP(0)CLTS is not recognized in virtual-8086 mode.
#UDIf the LOCK prefix is used.
69 |

Compatibility Mode Exceptions

70 |

Same exceptions as in protected mode.

71 |

64-Bit Mode Exceptions

72 | 73 | 74 | 75 | 76 | 77 | 78 |
#GP(0)If the CPL is greater than 0.
#UDIf the LOCK prefix is used.
-------------------------------------------------------------------------------- /html/CMC.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | CMC—Complement Carry Flag 8 | 9 |

CMC—Complement Carry Flag

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-bit ModeCompat/Leg ModeDescription
F5CMCNPValidValidComplement CF flag.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Complements the CF flag in the EFLAGS register. CMC operation is the same in non-64-bit modes and 64-bit mode.

41 |

Operation

42 | 
EFLAGS.CF[bit 0]← NOT EFLAGS.CF[bit 0];
43 |

Flags Affected

44 |

The CF flag contains the complement of its original value. The OF, ZF, SF, AF, and PF flags are unaffected.

45 |

Exceptions (All Operating Modes)

46 |

#UD

47 |

If the LOCK prefix is used.

-------------------------------------------------------------------------------- /html/CVTPD2PI.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | CVTPD2PI—Convert Packed Double-Precision FP Values to Packed Dword Integers 8 | 9 |

CVTPD2PI—Convert Packed Double-Precision FP Values to Packed Dword Integers

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64-Bit ModeCompat/Leg ModeDescription
19 |

66 0F 2D /r

20 |

CVTPD2PI mm, xmm/m128

RMValidValidConvert two packed double-precision floating-point values from xmm/m128 to two packed signed doubleword integers in mm.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RMModRM:reg (w)ModRM:r/m (r)NANA
39 |

Description

40 |

Converts two packed double-precision floating-point values in the source operand (second operand) to two packed signed doubleword integers in the destination operand (first operand).

41 |

The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX tech-nology register.

42 |

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.

43 |

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the CVTPD2PI instruction is executed.

44 |

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

45 |

Operation

46 | 
DEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer32(SRC[63:0]);
47 | DEST[63:32] ← Convert_Double_Precision_Floating_Point_To_Integer32(SRC[127:64]);
48 |

Intel C/C++ Compiler Intrinsic Equivalent

49 |

CVTPD1PI:

50 |

__m64 _mm_cvtpd_pi32(__m128d a)

51 |

SIMD Floating-Point Exceptions

52 |

Invalid, Precision.

53 |

Other Exceptions

54 |

See Table 22-4, “Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Align-ment,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

-------------------------------------------------------------------------------- /html/CVTPI2PD.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | CVTPI2PD—Convert Packed Dword Integers to Packed Double-Precision FP Values 8 | 9 |

CVTPI2PD—Convert Packed Dword Integers to Packed Double-Precision FP Values

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64-Bit ModeCompat/Leg ModeDescription
19 |

66 0F 2A /r

20 |

CVTPI2PD xmm, mm/m64*

RMValidValidConvert two packed signed doubleword integers from mm/mem64 to two packed double-precision floating-point values in xmm.
25 |

NOTES: *Operation is different for different operand sets; see the Description section.

26 |

Instruction Operand Encoding

27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RMModRM:reg (w)ModRM:r/m (r)NANA
40 |

Description

41 |

Converts two packed signed doubleword integers in the source operand (second operand) to two packed double-precision floating-point values in the destination operand (first operand).

42 |

The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an XMM register. In addition, depending on the operand configuration:

43 |

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

44 |

Operation

45 | 
DEST[63:0] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);
46 | DEST[127:64] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]);
47 |

Intel C/C++ Compiler Intrinsic Equivalent

48 |

CVTPI2PD:

49 |

__m128d _mm_cvtpi32_pd(__m64 a)

50 |

SIMD Floating-Point Exceptions

51 |

None

52 |

Other Exceptions

53 |

See Table 22-6, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and without FP Exception,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

-------------------------------------------------------------------------------- /html/CVTPI2PS.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | CVTPI2PS—Convert Packed Dword Integers to Packed Single-Precision FP Values 8 | 9 |

CVTPI2PS—Convert Packed Dword Integers to Packed Single-Precision FP Values

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64-Bit ModeCompat/Leg ModeDescription
19 |

0F 2A /r

20 |

CVTPI2PS xmm, mm/m64

RMValidValidConvert two signed doubleword integers from mm/m64 to two single-precision floating-point values in xmm.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RMModRM:reg (w)ModRM:r/m (r)NANA
39 |

Description

40 |

Converts two packed signed doubleword integers in the source operand (second operand) to two packed single-precision floating-point values in the destination operand (first operand).

41 |

The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an XMM register. The results are stored in the low quadword of the destination operand, and the high quadword remains unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.

42 |

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the CVTPI2PS instruction is executed.

43 |

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

44 |

Operation

45 | 
DEST[31:0] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
46 | DEST[63:32] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]);
47 | (* High quadword of destination unchanged *)
48 |

Intel C/C++ Compiler Intrinsic Equivalent

49 |

CVTPI2PS:

50 |

__m128 _mm_cvtpi32_ps(__m128 a, __m64 b)

51 |

SIMD Floating-Point Exceptions

52 |

Precision

53 |

Other Exceptions

54 |

See Table 22-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

-------------------------------------------------------------------------------- /html/CVTPS2PI.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | CVTPS2PI—Convert Packed Single-Precision FP Values to Packed Dword Integers 8 | 9 |

CVTPS2PI—Convert Packed Single-Precision FP Values to Packed Dword Integers

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64-Bit ModeCompat/Leg ModeDescription
19 |

0F 2D /r

20 |

CVTPS2PI mm, xmm/m64

RMValidValidConvert two packed single-precision floating-point values from xmm/m64 to two packed signed doubleword integers in mm.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RMModRM:reg (w)ModRM:r/m (r)NANA
39 |

Description

40 |

Converts two packed single-precision floating-point values in the source operand (second operand) to two packed signed doubleword integers in the destination operand (first operand).

41 |

The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX tech-nology register. When the source operand is an XMM register, the two single-precision floating-point values are contained in the low quadword of the register. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indef-inite integer value (80000000H) is returned.

42 |

CVTPS2PI causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the CVTPS2PI instruction is executed.

43 |

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

44 |

Operation

45 | 
DEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
46 | DEST[63:32] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);
47 |

Intel C/C++ Compiler Intrinsic Equivalent

48 |

CVTPS2PI:

49 |

__m64 _mm_cvtps_pi32(__m128 a)

50 |

SIMD Floating-Point Exceptions

51 |

Invalid, Precision

52 |

Other Exceptions

53 |

See Table 22-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

-------------------------------------------------------------------------------- /html/CVTTPD2PI.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | CVTTPD2PI—Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers 8 | 9 |

CVTTPD2PI—Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64-Bit ModeCompat/Leg ModeDescription
19 |

66 0F 2C /r

20 |

CVTTPD2PI mm, xmm/m128

RMValidValidConvert two packer double-precision floating-point values from xmm/m128 to two packed signed doubleword integers in mm using truncation.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RMModRM:reg (w)ModRM:r/m (r)NANA
39 |

Description

40 |

Converts two packed double-precision floating-point values in the source operand (second operand) to two packed signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX technology register.

41 |

When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.

42 |

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the CVTTPD2PI instruction is executed.

43 |

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

44 |

Operation

45 | 
DEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[63:0]);
46 | DEST[63:32] ← Convert_Double_Precision_Floating_Point_To_Integer32_
47 |                     Truncate(SRC[127:64]);
48 |

Intel C/C++ Compiler Intrinsic Equivalent

49 |

CVTTPD1PI:

50 |

__m64 _mm_cvttpd_pi32(__m128d a)

51 |

SIMD Floating-Point Exceptions

52 |

Invalid, Precision

53 |

Other Mode Exceptions

54 |

See Table 22-4, “Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Align-ment,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

-------------------------------------------------------------------------------- /html/CVTTPS2PI.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | CVTTPS2PI—Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers 8 | 9 |

CVTTPS2PI—Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64-Bit ModeCompat/Leg ModeDescription
19 |

0F 2C /r

20 |

CVTTPS2PI mm, xmm/m64

RMValidValidConvert two single-precision floating-point values from xmm/m64 to two signed doubleword signed integers in mm using truncation.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RMModRM:reg (w)ModRM:r/m (r)NANA
39 |

Description

40 |

Converts two packed single-precision floating-point values in the source operand (second operand) to two packed signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register or a 64-bit memory location. The destination operand is an MMX technology register. When the source operand is an XMM register, the two single-precision floating-point values are contained in the low quadword of the register.

41 |

When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.

42 |

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the CVTTPS2PI instruction is executed.

43 |

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

44 |

Operation

45 | 
DEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
46 | DEST[63:32] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32]);
47 |

Intel C/C++ Compiler Intrinsic Equivalent

48 |

CVTTPS2PI:

49 |

__m64 _mm_cvttps_pi32(__m128 a)

50 |

SIMD Floating-Point Exceptions

51 |

Invalid, Precision

52 |

Other Exceptions

53 |

See Table 22-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

-------------------------------------------------------------------------------- /html/EMMS.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | EMMS—Empty MMX Technology State 8 | 9 |

EMMS—Empty MMX Technology State

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-Bit ModeCompat/Leg ModeDescription
0F 77EMMSNPValidValidSet the x87 FPU tag word to empty.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Sets the values of all the tags in the x87 FPU tag word to empty (all 1s). This operation marks the x87 FPU data registers (which are aliased to the MMX technology registers) as available for use by x87 FPU floating-point instruc-tions. (See Figure 8-7 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for the format of the x87 FPU tag word.) All other MMX instructions (other than the EMMS instruction) set all the tags in x87 FPU tag word to valid (all 0s).

41 |

The EMMS instruction must be used to clear the MMX technology state at the end of all MMX technology procedures or subroutines and before calling other procedures or subroutines that may execute x87 floating-point instructions. If a floating-point instruction loads one of the registers in the x87 FPU data register stack before the x87 FPU tag word has been reset by the EMMS instruction, an x87 floating-point register stack overflow can occur that will result in an x87 floating-point exception or incorrect result.

42 |

EMMS operation is the same in non-64-bit modes and 64-bit mode.

43 |

Operation

44 | 
x87FPUTagWord ← FFFFH;
45 |

Intel C/C++ Compiler Intrinsic Equivalent

46 |

void _mm_empty()

47 |

Flags Affected

48 |

None

49 |

Protected Mode Exceptions

50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 |
#UDIf CR0.EM[bit 2] = 1.
#NMIf CR0.TS[bit 3] = 1.
#MFIf there is a pending FPU exception.
#UDIf the LOCK prefix is used.
63 |

Real-Address Mode Exceptions

64 |

Same exceptions as in protected mode.

65 |

Virtual-8086 Mode Exceptions

66 |

Same exceptions as in protected mode.

67 |

Compatibility Mode Exceptions

68 |

Same exceptions as in protected mode.

69 |

64-Bit Mode Exceptions

70 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/F2XM1.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | F2XM1—Compute 2x–1 8 | 9 |

F2XM1—Compute 2x–1

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 |
OpcodeInstruction64-Bit ModeCompat/Leg ModeDescription
D9 F0F2XM1ValidValidReplace ST(0) with (2ST(0) – 1).
23 |

Description

24 |

Computes the exponential value of 2 to the power of the source operand minus 1. The source operand is located in register ST(0) and the result is also stored in ST(0). The value of the source operand must lie in the range –1.0 to +1.0. If the source value is outside this range, the result is undefined.

25 |

The following table shows the results obtained when computing the exponential value of various classes of numbers, assuming that neither overflow nor underflow occurs.

26 |

Table 3-16. Results Obtained from F2XM1

27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 |
ST(0) SRCST(0) DEST
− 1.0 to −0− 0.5 to − 0
− 0− 0
+ 0+ 0
+ 0 to +1.0+ 0 to 1.0
43 |

Values other than 2 can be exponentiated using the following formula:

44 |

xy ← 2(y ∗ log2x)

45 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

46 |

Operation

47 | 
ST(0) ← (2ST(0) − 1);
48 |

FPU Flags Affected

49 | 50 | 51 | 52 | 55 | 56 | 57 |
C1 53 |

Set to 0 if stack underflow occurred.

54 |

Set if result was rounded up; cleared otherwise.

C0, C2, C3Undefined.
58 |

Floating-Point Exceptions

59 | 60 | 61 | 62 | 63 | 64 | 65 |
#ISStack underflow occurred.
#IASource operand is an SNaN value or unsupported format.
66 |

#D

67 |

Source is a denormal value.

68 |

#U

69 |

Result is too small for destination format.

70 |

#P

71 |

Value cannot be represented exactly in destination format.

72 |

Protected Mode Exceptions

73 | 74 | 75 | 76 | 77 | 78 | 79 |
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UDIf the LOCK prefix is used.
80 |

Real-Address Mode Exceptions

81 |

Same exceptions as in protected mode.

82 |

Virtual-8086 Mode Exceptions

83 |

Same exceptions as in protected mode.

84 |

Compatibility Mode Exceptions

85 |

Same exceptions as in protected mode.

86 |

64-Bit Mode Exceptions

87 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/FABS.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | FABS—Absolute Value 8 | 9 |

FABS—Absolute Value

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 |
OpcodeInstruction64-Bit ModeCompat/Leg ModeDescription
D9 E1FABSValidValidReplace ST with its absolute value.
23 |

Description

24 |

Clears the sign bit of ST(0) to create the absolute value of the operand. The following table shows the results obtained when creating the absolute value of various classes of numbers.

25 |

Table 3-17. Results Obtained from FABS

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 |
ST(0) SRCST(0) DEST
− ∞+ ∞
− F+ F
− 0+ 0
+ 0+ 0
+ F+ F
+ ∞+ ∞
NaNNaN
51 |

NOTES:

52 |

F Means finite floating-point value.

53 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

54 |

Operation

55 | 
ST(0) ← |ST(0)|;
56 |

FPU Flags Affected

57 | 58 | 59 | 60 | 61 | 62 | 63 |
C1Set to 0.
C0, C2, C3Undefined.
64 |

Floating-Point Exceptions

65 | 66 | 67 | 68 |
#ISStack underflow occurred.
69 |

Protected Mode Exceptions

70 | 71 | 72 | 73 | 74 | 75 | 76 |
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UDIf the LOCK prefix is used.
77 |

Real-Address Mode Exceptions

78 |

Same exceptions as in protected mode.

79 |

Virtual-8086 Mode Exceptions

80 |

Same exceptions as in protected mode.

81 |

Compatibility Mode Exceptions

82 |

Same exceptions as in protected mode.

83 |

64-Bit Mode Exceptions

84 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/FCHS.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | FCHS—Change Sign 8 | 9 |

FCHS—Change Sign

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 |
OpcodeInstruction64-Bit ModeCompat/Leg ModeDescription
D9 E0FCHSValidValidComplements sign of ST(0).
23 |

Description

24 |

Complements the sign bit of ST(0). This operation changes a positive value into a negative value of equal magni-tude or vice versa. The following table shows the results obtained when changing the sign of various classes of numbers.

25 |

Table 3-20. FCHS Results

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 |
ST(0) SRCST(0) DEST
− ∞+ ∞
− F+ F
− 0+ 0
+ 0− 0
+ F− F
+ ∞− ∞
NaNNaN
51 |

NOTES:

52 |

*

53 |

F means finite floating-point value.

54 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

55 |

Operation

56 | 
SignBit(ST(0)) ← NOT (SignBit(ST(0)));
57 |

FPU Flags Affected

58 | 59 | 60 | 61 | 62 | 63 | 64 |
C1Set to 0.
C0, C2, C3Undefined.
65 |

Floating-Point Exceptions

66 | 67 | 68 | 69 |
#ISStack underflow occurred.
70 |

Protected Mode Exceptions

71 | 72 | 73 | 74 | 75 | 76 | 77 |
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UDIf the LOCK prefix is used.
78 |

Real-Address Mode Exceptions

79 |

Same exceptions as in protected mode.

80 |

Virtual-8086 Mode Exceptions

81 |

Same exceptions as in protected mode.

82 |

Compatibility Mode Exceptions

83 |

Same exceptions as in protected mode.

84 |

64-Bit Mode Exceptions

85 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/FDECSTP.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | FDECSTP—Decrement Stack-Top Pointer 8 | 9 |

FDECSTP—Decrement Stack-Top Pointer

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 |
OpcodeInstruction64-Bit ModeCompat/Leg ModeDescription
D9 F6FDECSTPValidValidDecrement TOP field in FPU status word.
23 |

Description

24 |

Subtracts one from the TOP field of the FPU status word (decrements the top-of-stack pointer). If the TOP field contains a 0, it is set to 7. The effect of this instruction is to rotate the stack by one position. The contents of the FPU data registers and tag register are not affected.

25 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

26 |

Operation

27 | 
IF TOP = 0
28 |     THEN TOP ← 7;
29 |     ELSE TOP ← TOP – 1;
30 | FI;
31 |

FPU Flags Affected

32 |

The C1 flag is set to 0. The C0, C2, and C3 flags are undefined.

33 |

Floating-Point Exceptions

34 |

None.

35 |

Protected Mode Exceptions

36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 |
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MFIf there is a pending x87 FPU exception.
#UDIf the LOCK prefix is used.
46 |

Real-Address Mode Exceptions

47 |

Same exceptions as in protected mode.

48 |

Virtual-8086 Mode Exceptions

49 |

Same exceptions as in protected mode.

50 |

Compatibility Mode Exceptions

51 |

Same exceptions as in protected mode.

52 |

64-Bit Mode Exceptions

53 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/FFREE.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | FFREE—Free Floating-Point Register 8 | 9 |

FFREE—Free Floating-Point Register

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 |
OpcodeInstruction64-Bit ModeCompat/Leg ModeDescription
DD C0+iFFREE ST(i)ValidValidSets tag for ST(i) to empty.
23 |

Description

24 |

Sets the tag in the FPU tag register associated with register ST(i) to empty (11B). The contents of ST(i) and the FPU stack-top pointer (TOP) are not affected.

25 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

26 |

Operation

27 | 
TAG(i) ← 11B;
28 |

FPU Flags Affected

29 |

C0, C1, C2, C3 undefined.

30 |

Floating-Point Exceptions

31 |

None

32 |

Protected Mode Exceptions

33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 |
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MFIf there is a pending x87 FPU exception.
#UDIf the LOCK prefix is used.
43 |

Real-Address Mode Exceptions

44 |

Same exceptions as in protected mode.

45 |

Virtual-8086 Mode Exceptions

46 |

Same exceptions as in protected mode.

47 |

Compatibility Mode Exceptions

48 |

Same exceptions as in protected mode.

49 |

64-Bit Mode Exceptions

50 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/FINCSTP.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | FINCSTP—Increment Stack-Top Pointer 8 | 9 |

FINCSTP—Increment Stack-Top Pointer

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 |
OpcodeInstruction64-Bit ModeCompat/Leg ModeDescription
D9 F7FINCSTPValidValidIncrement the TOP field in the FPU status register.
23 |

Description

24 |

Adds one to the TOP field of the FPU status word (increments the top-of-stack pointer). If the TOP field contains a 7, it is set to 0. The effect of this instruction is to rotate the stack by one position. The contents of the FPU data registers and tag register are not affected. This operation is not equivalent to popping the stack, because the tag for the previous top-of-stack register is not marked empty.

25 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

26 |

Operation

27 | 
IF TOP = 7
28 |     THEN TOP ← 0;
29 |     ELSE TOP ← TOP + 1;
30 | FI;
31 |

FPU Flags Affected

32 |

The C1 flag is set to 0. The C0, C2, and C3 flags are undefined.

33 |

Floating-Point Exceptions

34 |

None

35 |

Protected Mode Exceptions

36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 |
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MFIf there is a pending x87 FPU exception.
#UDIf the LOCK prefix is used.
46 |

Real-Address Mode Exceptions

47 |

Same exceptions as in protected mode.

48 |

Virtual-8086 Mode Exceptions

49 |

Same exceptions as in protected mode.

50 |

Compatibility Mode Exceptions

51 |

Same exceptions as in protected mode.

52 |

64-Bit Mode Exceptions

53 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/FNOP.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | FNOP—No Operation 8 | 9 |

FNOP—No Operation

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 |
OpcodeInstruction64-Bit ModeCompat/Leg ModeDescription
D9 D0FNOPValidValidNo operation is performed.
23 |

Description

24 |

Performs no FPU operation. This instruction takes up space in the instruction stream but does not affect the FPU or machine context, except the EIP register and the FPU Instruction Pointer.

25 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

26 |

FPU Flags Affected

27 |

C0, C1, C2, C3 undefined.

28 |

Floating-Point Exceptions

29 |

None

30 |

Protected Mode Exceptions

31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 |
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MFIf there is a pending x87 FPU exception.
#UDIf the LOCK prefix is used.
41 |

Real-Address Mode Exceptions

42 |

Same exceptions as in protected mode.

43 |

Virtual-8086 Mode Exceptions

44 |

Same exceptions as in protected mode.

45 |

Compatibility Mode Exceptions

46 |

Same exceptions as in protected mode.

47 |

64-Bit Mode Exceptions

48 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/FRNDINT.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | FRNDINT—Round to Integer 8 | 9 |

FRNDINT—Round to Integer

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 |
OpcodeInstruction64-Bit ModeCompat/Leg ModeDescription
D9 FCFRNDINTValidValidRound ST(0) to an integer.
23 |

Description

24 |

Rounds the source value in the ST(0) register to the nearest integral value, depending on the current rounding mode (setting of the RC field of the FPU control word), and stores the result in ST(0).

25 |

If the source value is ∞, the value is not changed. If the source value is not an integral value, the floating-point inexact-result exception (#P) is generated.

26 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

27 |

Operation

28 | 
ST(0) ← RoundToIntegralValue(ST(0));
29 |

FPU Flags Affected

30 | 31 | 32 | 33 | 36 | 37 | 38 |
C1 34 |

Set to 0 if stack underflow occurred.

35 |

Set if result was rounded up; cleared otherwise.

C0, C2, C3Undefined.
39 |

Floating-Point Exceptions

40 | 41 | 42 | 43 | 44 | 45 | 46 |
#ISStack underflow occurred.
#IASource operand is an SNaN value or unsupported format.
47 |

#D

48 |

Source operand is a denormal value.

49 |

#P

50 |

Source operand is not an integral value.

51 |

Protected Mode Exceptions

52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 |
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MFIf there is a pending x87 FPU exception.
#UDIf the LOCK prefix is used.
62 |

Real-Address Mode Exceptions

63 |

Same exceptions as in protected mode.

64 |

Virtual-8086 Mode Exceptions

65 |

Same exceptions as in protected mode.

66 |

Compatibility Mode Exceptions

67 |

Same exceptions as in protected mode.

68 |

64-Bit Mode Exceptions

69 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/FSQRT.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | FSQRT—Square Root 8 | 9 |

FSQRT—Square Root

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 |
OpcodeInstruction64-Bit ModeCompat/Leg ModeDescription
D9 FAFSQRTValidValidComputes square root of ST(0) and stores the result in ST(0).
23 |

Description

24 |

Computes the square root of the source value in the ST(0) register and stores the result in ST(0).

25 |

The following table shows the results obtained when taking the square root of various classes of numbers, assuming that neither overflow nor underflow occurs.

26 |

Table 3-37. FSQRT Results

27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 |
SRC (ST(0))DEST (ST(0))
− ∞*
− F*
− 0− 0
+ 0+ 0
+ F+ F
+ ∞+ ∞
NaNNaN
52 |

NOTES:

53 |

F Means finite floating-point value.

54 |

*

55 |

Indicates floating-point invalid-arithmetic-operand (#IA) exception.

56 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

57 |

Operation

58 | 
ST(0) ← SquareRoot(ST(0));
59 |

FPU Flags Affected

60 | 61 | 62 | 63 | 66 | 67 | 68 |
C1 64 |

Set to 0 if stack underflow occurred.

65 |

Set if result was rounded up; cleared otherwise.

C0, C2, C3Undefined.
69 |

Floating-Point Exceptions

70 | 71 | 72 | 73 | 74 | 75 | 76 |
#ISStack underflow occurred.
#IA 77 |

Source operand is an SNaN value or unsupported format.

78 |

Source operand is a negative value (except for −0).

79 |

#D

80 |

Source operand is a denormal value.

81 |

#P

82 |

Value cannot be represented exactly in destination format.

83 |

Protected Mode Exceptions

84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 |
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MFIf there is a pending x87 FPU exception.
#UDIf the LOCK prefix is used.
94 |

Real-Address Mode Exceptions

95 |

Same exceptions as in protected mode.

96 |

Virtual-8086 Mode Exceptions

97 |

Same exceptions as in protected mode.

98 |

Compatibility Mode Exceptions

99 |

Same exceptions as in protected mode.

100 |

64-Bit Mode Exceptions

101 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/FXAM.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | FXAM—Examine Floating-Point 8 | 9 |

FXAM—Examine Floating-Point

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 |
OpcodeInstruction64-Bit ModeCompat/Leg ModeDescription
D9 E5FXAMValidValidClassify value or number in ST(0).
23 |

Description

24 |

Examines the contents of the ST(0) register and sets the condition code flags C0, C2, and C3 in the FPU status word to indicate the class of value or number in the register (see the table below).

25 |

Table 3-42. FXAM Results

26 |

.

27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 |
ClassC3C2C0
Unsupported000
NaN001
Normal finite number010
Infinity011
Zero100
Empty101
Denormal number110
68 |

The C1 flag is set to the sign of the value in ST(0), regardless of whether the register is empty or full.

69 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

70 |

Operation

71 | 
C1 ← sign bit of ST; (* 0 for positive, 1 for negative *)
 72 | CASE (class of value or number in ST(0)) OF
 73 |     Unsupported:C3, C2, C0 ← 000;
 74 |     NaN:
 75 |                     C3, C2, C0 ← 001;
 76 |     Normal:
 77 |                     C3, C2, C0 ← 010;
 78 |     Infinity:
 79 |                     C3, C2, C0 ← 011;
 80 |     Zero:
 81 |                     C3, C2, C0 ← 100;
 82 |     Empty:
 83 |                     C3, C2, C0 ← 101;
 84 |     Denormal:
 85 |                     C3, C2, C0 ← 110;
 86 | ESAC;
87 |

FPU Flags Affected

88 | 89 | 90 | 91 | 92 | 93 | 94 |
C1Sign of value in ST(0).
C0, C2, C3See Table 3-42.
95 |

Floating-Point Exceptions

96 |

None

97 |

Protected Mode Exceptions

98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 |
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MFIf there is a pending x87 FPU exception.
#UDIf the LOCK prefix is used.
108 |

Real-Address Mode Exceptions

109 |

Same exceptions as in protected mode.

110 |

Virtual-8086 Mode Exceptions

111 |

Same exceptions as in protected mode.

112 |

Compatibility Mode Exceptions

113 |

Same exceptions as in protected mode.

114 |

64-Bit Mode Exceptions

115 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/FXCH.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | FXCH—Exchange Register Contents 8 | 9 |

FXCH—Exchange Register Contents

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 |
OpcodeInstruction64-Bit ModeCompat/Leg ModeDescription
D9 C8+iFXCH ST(i)ValidValidExchange the contents of ST(0) and ST(i).
D9 C9FXCHValidValidExchange the contents of ST(0) and ST(1).
29 |

Description

30 |

Exchanges the contents of registers ST(0) and ST(i). If no source operand is specified, the contents of ST(0) and ST(1) are exchanged.

31 |

This instruction provides a simple means of moving values in the FPU register stack to the top of the stack [ST(0)], so that they can be operated on by those floating-point instructions that can only operate on values in ST(0). For example, the following instruction sequence takes the square root of the third register from the top of the register stack:

32 |

FXCH ST(3);

33 |

FSQRT;

34 |

FXCH ST(3);

35 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

36 |

Operation

37 | 
IF (Number-of-operands) is 1
38 |     THEN
39 |          temp ← ST(0);
40 |          ST(0) ← SRC;
41 |          SRC ← temp;
42 |     ELSE
43 |          temp ← ST(0);
44 |          ST(0) ← ST(1);
45 |          ST(1) ← temp;
46 | FI;
47 |

FPU Flags Affected

48 | 49 | 50 | 51 | 52 | 53 | 54 |
C1Set to 0.
C0, C2, C3Undefined.
55 |

Floating-Point Exceptions

56 | 57 | 58 | 59 |
#ISStack underflow occurred.
60 |

Protected Mode Exceptions

61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 |
#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MFIf there is a pending x87 FPU exception.
#UDIf the LOCK prefix is used.
71 |

Real-Address Mode Exceptions

72 |

Same exceptions as in protected mode.

73 |

Virtual-8086 Mode Exceptions

74 |

Same exceptions as in protected mode.

75 |

Compatibility Mode Exceptions

76 |

Same exceptions as in protected mode.

77 |

64-Bit Mode Exceptions

78 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/HLT.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | HLT—Halt 8 | 9 |

HLT—Halt

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-Bit ModeCompat/Leg ModeDescription
F4HLTNPValidValidHalt
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Stops instruction execution and places the processor in a HALT state. An enabled interrupt (including NMI and SMI), a debug exception, the BINIT# signal, the INIT# signal, or the RESET# signal will resume execution. If an interrupt (including NMI) is used to resume execution after a HLT instruction, the saved instruction pointer (CS:EIP) points to the instruction following the HLT instruction.

41 |

When a HLT instruction is executed on an Intel 64 or IA-32 processor supporting Intel Hyper-Threading Technology, only the logical processor that executes the instruction is halted. The other logical processors in the physical processor remain active, unless they are each individually halted by executing a HLT instruction.

42 |

The HLT instruction is a privileged instruction. When the processor is running in protected or virtual-8086 mode, the privilege level of a program or procedure must be 0 to execute the HLT instruction.

43 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

44 |

Operation

45 | 
Enter Halt state;
46 |

Flags Affected

47 |

None

48 |

Protected Mode Exceptions

49 | 50 | 51 | 52 | 53 | 54 | 55 |
#GP(0)If the current privilege level is not 0.
#UDIf the LOCK prefix is used.
56 |

Real-Address Mode Exceptions

57 |

None.

58 |

Virtual-8086 Mode Exceptions

59 |

Same exceptions as in protected mode.

60 |

Compatibility Mode Exceptions

61 |

Same exceptions as in protected mode.

62 |

64-Bit Mode Exceptions

63 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/KADDW_KADDB_KADDQ_KADDD.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | KADDW/KADDB/KADDQ/KADDD—ADD Two Masks 8 | 9 |

KADDW/KADDB/KADDQ/KADDD—ADD Two Masks

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
VEX.L1.0F.W0 4A /r KADDW k1, k2, k3RVRV/VAVX512DQAdd 16 bits masks in k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 4A /r KADDB k1, k2, k3RVRV/VAVX512DQAdd 8 bits masks in k2 and k3 and place result in k1.
VEX.L1.0F.W1 4A /r KADDQ k1, k2, k3RVRV/VAVX512BWAdd 64 bits masks in k2 and k3 and place result in k1.
VEX.L1.66.0F.W1 4A /r KADDD k1, k2, k3RVRV/VAVX512BWAdd 32 bits masks in k2 and k3 and place result in k1.
41 |

Instruction Operand Encoding

42 |

Op/En

43 |

Operand 1

44 |

Operand 2

45 |

Operand 3

46 |

RVR

47 |

ModRM:reg (w)

48 |

VEX.1vvv (r)

49 |

ModRM:r/m (r, ModRM:[7:6] must be 11b)

50 |

Description

51 |

Adds the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.

52 |

Operation

53 |

KADDW

54 | 
DEST[15:0] (cid:197) SRC1[15:0] + SRC2[15:0]
55 | DEST[MAX_KL-1:16] (cid:197) 0
56 |

KADDB

57 | 
DEST[7:0] (cid:197) SRC1[7:0] + SRC2[7:0]
58 | DEST[MAX_KL-1:8] (cid:197) 0
59 |

KADDQ

60 | 
DEST[63:0] (cid:197) SRC1[63:0] + SRC2[63:0]
61 | DEST[MAX_KL-1:64] (cid:197) 0
62 |

KADDD

63 | 
DEST[31:0] (cid:197) SRC1[31:0] + SRC2[31:0]
64 | DEST[MAX_KL-1:32] (cid:197) 0
65 |

Intel C/C++ Compiler Intrinsic Equivalent

66 |

SIMD Floating-Point Exceptions

67 |

None

68 |

Other Exceptions

69 |

See Exceptions Type K20.

-------------------------------------------------------------------------------- /html/KANDNW_KANDNB_KANDNQ_KANDND.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | KANDNW/KANDNB/KANDNQ/KANDND—Bitwise Logical AND NOT Masks 8 | 9 |

KANDNW/KANDNB/KANDNQ/KANDND—Bitwise Logical AND NOT Masks

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
VEX.NDS.L1.0F.W0 42 /r KANDNW k1, k2, k3RVRV/VAVX512FBitwise AND NOT 16 bits masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 42 /r KANDNB k1, k2, k3RVRV/VAVX512DQBitwise AND NOT 8 bits masks k1 and k2 and place result in k1.
VEX.L1.0F.W1 42 /r KANDNQ k1, k2, k3RVRV/VAVX512BWBitwise AND NOT 64 bits masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W1 42 /r KANDND k1, k2, k3RVRV/VAVX512BWBitwise AND NOT 32 bits masks k2 and k3 and place result in k1.
41 |

Instruction Operand Encoding

42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 |
Op/EnOperand 1Operand 2Operand 3
RVRModRM:reg (w)VEX.1vvv (r)ModRM:r/m (r, ModRM:[7:6] must be 11b)
53 |

Description

54 |

Performs a bitwise AND NOT between the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.

55 |

Operation

56 |

KANDNW

57 | 
DEST[15:0] (cid:197) (BITWISE NOT SRC1[15:0]) BITWISE AND SRC2[15:0]
58 | DEST[MAX_KL-1:16] (cid:197) 0
59 |

KANDNB

60 | 
DEST[7:0] (cid:197) (BITWISE NOT SRC1[7:0]) BITWISE AND SRC2[7:0]
61 | DEST[MAX_KL-1:8] (cid:197) 0
62 |

KANDNQ

63 | 
DEST[63:0] (cid:197) (BITWISE NOT SRC1[63:0]) BITWISE AND SRC2[63:0]
64 | DEST[MAX_KL-1:64] (cid:197) 0
65 |

KANDND

66 | 
DEST[31:0] (cid:197) (BITWISE NOT SRC1[31:0]) BITWISE AND SRC2[31:0]
67 | DEST[MAX_KL-1:32] (cid:197) 0
68 |

Intel C/C++ Compiler Intrinsic Equivalent

69 |

KANDNW __mmask16 _mm512_kandn(__mmask16 a, __mmask16 b);

70 |

Flags Affected

71 |

None

72 |

SIMD Floating-Point Exceptions

73 |

None

74 |

Other Exceptions

75 |

See Exceptions Type K20.

-------------------------------------------------------------------------------- /html/KANDW_KANDB_KANDQ_KANDD.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | KANDW/KANDB/KANDQ/KANDD—Bitwise Logical AND Masks 8 | 9 |

KANDW/KANDB/KANDQ/KANDD—Bitwise Logical AND Masks

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
VEX.NDS.L1.0F.W0 41 /r KANDW k1, k2, k3RVRV/VAVX512FBitwise AND 16 bits masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 41 /r KANDB k1, k2, k3RVRV/VAVX512DQBitwise AND 8 bits masks k2 and k3 and place result in k1.
VEX.L1.0F.W1 41 /r KANDQ k1, k2, k3RVRV/VAVX512BWBitwise AND 64 bits masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W1 41 /r KANDD k1, k2, k3RVRV/VAVX512BWBitwise AND 32 bits masks k2 and k3 and place result in k1.
41 |

Instruction Operand Encoding

42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 |
Op/EnOperand 1Operand 2Operand 3
RVRModRM:reg (w)VEX.1vvv (r)ModRM:r/m (r, ModRM:[7:6] must be 11b)
53 |

Description

54 |

Performs a bitwise AND between the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.

55 |

Operation

56 |

KANDW

57 | 
DEST[15:0] (cid:197) SRC1[15:0] BITWISE AND SRC2[15:0]
58 | DEST[MAX_KL-1:16] (cid:197) 0
59 |

KANDB

60 | 
DEST[7:0] (cid:197) SRC1[7:0] BITWISE AND SRC2[7:0]
61 | DEST[MAX_KL-1:8] (cid:197) 0
62 |

KANDQ

63 | 
DEST[63:0] (cid:197) SRC1[63:0] BITWISE AND SRC2[63:0]
64 | DEST[MAX_KL-1:64] (cid:197) 0
65 |

KANDD

66 | 
DEST[31:0] (cid:197) SRC1[31:0] BITWISE AND SRC2[31:0]
67 | DEST[MAX_KL-1:32] (cid:197) 0
68 |

Intel C/C++ Compiler Intrinsic Equivalent

69 |

KANDW __mmask16 _mm512_kand(__mmask16 a, __mmask16 b);

70 |

Flags Affected

71 |

None

72 |

SIMD Floating-Point Exceptions

73 |

None

74 |

Other Exceptions

75 |

See Exceptions Type K20.

-------------------------------------------------------------------------------- /html/KNOTW_KNOTB_KNOTQ_KNOTD.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | KNOTW/KNOTB/KNOTQ/KNOTD—NOT Mask Register 8 | 9 |

KNOTW/KNOTB/KNOTQ/KNOTD—NOT Mask Register

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
VEX.L0.0F.W0 44 /r KNOTW k1, k2RRV/VAVX512FBitwise NOT of 16 bits mask k2.
VEX.L0.66.0F.W0 44 /r KNOTB k1, k2RRV/VAVX512DQBitwise NOT of 8 bits mask k2.
VEX.L0.0F.W1 44 /r KNOTQ k1, k2RRV/VAVX512BWBitwise NOT of 64 bits mask k2.
VEX.L0.66.0F.W1 44 /r KNOTD k1, k2RRV/VAVX512BWBitwise NOT of 32 bits mask k2.
41 |

Instruction Operand Encoding

42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 |
Op/EnOperand 1Operand 2
RRModRM:reg (w)ModRM:r/m (r, ModRM:[7:6] must be 11b)
51 |

Description

52 |

Performs a bitwise NOT of vector mask k2 and writes the result into vector mask k1.

53 |

Operation

54 |

KNOTW

55 | 
DEST[15:0] (cid:197) BITWISE NOT SRC[15:0]
56 | DEST[MAX_KL-1:16] (cid:197) 0
57 |

KNOTB

58 | 
DEST[7:0] (cid:197) BITWISE NOT SRC[7:0]
59 | DEST[MAX_KL-1:8] (cid:197) 0
60 |

KNOTQ

61 | 
DEST[63:0] (cid:197) BITWISE NOT SRC[63:0]
62 | DEST[MAX_KL-1:64] (cid:197) 0
63 |

KNOTD

64 | 
DEST[31:0] (cid:197) BITWISE NOT SRC[31:0]
65 | DEST[MAX_KL-1:32] (cid:197) 0
66 |

Intel C/C++ Compiler Intrinsic Equivalent

67 |

KNOTW __mmask16 _mm512_knot(__mmask16 a);

68 |

Flags Affected

69 |

None

70 |

SIMD Floating-Point Exceptions

71 |

None

72 |

Other Exceptions

73 |

See Exceptions Type K20.

-------------------------------------------------------------------------------- /html/KORW_KORB_KORQ_KORD.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | KORW/KORB/KORQ/KORD—Bitwise Logical OR Masks 8 | 9 |

KORW/KORB/KORQ/KORD—Bitwise Logical OR Masks

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
VEX.NDS.L1.0F.W0 45 /r KORW k1, k2, k3RVRV/VAVX512FBitwise OR 16 bits masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 45 /r KORB k1, k2, k3RVRV/VAVX512DQBitwise OR 8 bits masks k2 and k3 and place result in k1.
VEX.L1.0F.W1 45 /r KORQ k1, k2, k3RVRV/VAVX512BWBitwise OR 64 bits masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W1 45 /r KORD k1, k2, k3RVRV/VAVX512BWBitwise OR 32 bits masks k2 and k3 and place result in k1.
41 |

Instruction Operand Encoding

42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 |
Op/EnOperand 1Operand 2Operand 3
RVRModRM:reg (w)VEX.1vvv (r)ModRM:r/m (r, ModRM:[7:6] must be 11b)
53 |

Description

54 |

Performs a bitwise OR between the vector mask k2 and the vector mask k3, and writes the result into vector mask k1 (three-operand form).

55 |

Operation

56 |

KORW

57 | 
DEST[15:0] (cid:197) SRC1[15:0] BITWISE OR SRC2[15:0]
58 | DEST[MAX_KL-1:16] (cid:197) 0
59 |

KORB

60 | 
DEST[7:0] (cid:197) SRC1[7:0] BITWISE OR SRC2[7:0]
61 | DEST[MAX_KL-1:8] (cid:197) 0
62 |

KORQ

63 | 
DEST[63:0] (cid:197) SRC1[63:0] BITWISE OR SRC2[63:0]
64 | DEST[MAX_KL-1:64] (cid:197) 0
65 |

KORD

66 | 
DEST[31:0] (cid:197) SRC1[31:0] BITWISE OR SRC2[31:0]
67 | DEST[MAX_KL-1:32] (cid:197) 0
68 |

Intel C/C++ Compiler Intrinsic Equivalent

69 |

KORW __mmask16 _mm512_kor(__mmask16 a, __mmask16 b);

70 |

Flags Affected

71 |

None

72 |

SIMD Floating-Point Exceptions

73 |

None

74 |

Other Exceptions

75 |

See Exceptions Type K20.

-------------------------------------------------------------------------------- /html/KSHIFTLW_KSHIFTLB_KSHIFTLQ_KSHIFTLD.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD—Shift Left Mask Registers 8 | 9 |

KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD—Shift Left Mask Registers

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
VEX.L0.66.0F3A.W1 32 /r KSHIFTLW k1, k2, imm8RRIV/VAVX512FShift left 16 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 32 /r KSHIFTLB k1, k2, imm8RRIV/VAVX512DQShift left 8 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W1 33 /r KSHIFTLQ k1, k2, imm8RRIV/VAVX512BWShift left 64 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 33 /r KSHIFTLD k1, k2, imm8RRIV/VAVX512BWShift left 32 bits in k2 by immediate and write result in k1.
41 |

Instruction Operand Encoding

42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 |
Op/EnOperand 1Operand 2Operand 3
RRIModRM:reg (w)ModRM:r/m (r, ModRM:[7:6] must be 11b)Imm8
53 |

Description

54 |

Shifts 8/16/32/64 bits in the second operand (source operand) left by the count specified in immediate byte and place the least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destination are zero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for word shift), 31 (for doubleword shift) or 63 (for quadword shift).

55 |

Operation

56 |

KSHIFTLW

57 | 
COUNT (cid:197) imm8[7:0]
58 | DEST[MAX_KL-1:0] (cid:197) 0
59 | IF COUNT <=15
60 |     THEN DEST[15:0] (cid:197) SRC1[15:0] << COUNT;
61 | FI;
62 |

KSHIFTLB

63 | 
COUNT (cid:197) imm8[7:0]
64 | DEST[MAX_KL-1:0] (cid:197) 0
65 | IF COUNT <=7
66 |           THEN
67 |                      DEST[7:0] (cid:197) SRC1[7:0] << COUNT;
68 | FI;
69 |

KSHIFTLQ

70 | 
COUNT (cid:197) imm8[7:0]
71 | DEST[MAX_KL-1:0] (cid:197) 0
72 | IF COUNT <=63
73 |           THEN
74 |                      DEST[63:0] (cid:197) SRC1[63:0] << COUNT;
75 | FI;
76 |

KSHIFTLD

77 | 
COUNT (cid:197) imm8[7:0]
78 | DEST[MAX_KL-1:0] (cid:197) 0
79 | IF COUNT <=31
80 |           THEN
81 |                      DEST[31:0] (cid:197) SRC1[31:0] << COUNT;
82 | FI;
83 |

Intel C/C++ Compiler Intrinsic Equivalent

84 |

Compiler auto generates KSHIFTLW when needed.

85 |

Flags Affected

86 |

None

87 |

SIMD Floating-Point Exceptions

88 |

None

89 |

Other Exceptions

90 |

See Exceptions Type K20.

-------------------------------------------------------------------------------- /html/KSHIFTRW_KSHIFTRB_KSHIFTRQ_KSHIFTRD.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD—Shift Right Mask Registers 8 | 9 |

KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD—Shift Right Mask Registers

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
VEX.L0.66.0F3A.W1 30 /r KSHIFTRW k1, k2, imm8RRIV/VAVX512FShift right 16 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 30 /r KSHIFTRB k1, k2, imm8RRIV/VAVX512DQShift right 8 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W1 31 /r KSHIFTRQ k1, k2, imm8RRIV/VAVX512BWShift right 64 bits in k2 by immediate and write result in k1.
VEX.L0.66.0F3A.W0 31 /r KSHIFTRD k1, k2, imm8RRIV/VAVX512BWShift right 32 bits in k2 by immediate and write result in k1.
41 |

Instruction Operand Encoding

42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 |
Op/EnOperand 1Operand 2Operand 3
RRIModRM:reg (w)ModRM:r/m (r, ModRM:[7:6] must be 11b)Imm8
53 |

Description

54 |

Shifts 8/16/32/64 bits in the second operand (source operand) right by the count specified in immediate and place the least significant 8/16/32/64 bits of the result in the destination operand. The higher bits of the destination are zero-extended. The destination is set to zero if the count value is greater than 7 (for byte shift), 15 (for word shift), 31 (for doubleword shift) or 63 (for quadword shift).

55 |

Operation

56 |

KSHIFTRW

57 | 
COUNT (cid:197) imm8[7:0]
58 | DEST[MAX_KL-1:0] (cid:197) 0
59 | IF COUNT <=15
60 |     THEN DEST[15:0] (cid:197) SRC1[15:0] >> COUNT;
61 | FI;
62 |

KSHIFTRB

63 | 
COUNT (cid:197) imm8[7:0]
64 | DEST[MAX_KL-1:0] (cid:197) 0
65 | IF COUNT <=7
66 |           THEN
67 |                      DEST[7:0] (cid:197) SRC1[7:0] >> COUNT;
68 | FI;
69 |

KSHIFTRQ

70 | 
COUNT (cid:197) imm8[7:0]
71 | DEST[MAX_KL-1:0] (cid:197) 0
72 | IF COUNT <=63
73 |           THEN
74 |                      DEST[63:0] (cid:197) SRC1[63:0] >> COUNT;
75 | FI;
76 |

KSHIFTRD

77 | 
COUNT (cid:197) imm8[7:0]
78 | DEST[MAX_KL-1:0] (cid:197) 0
79 | IF COUNT <=31
80 |           THEN
81 |                      DEST[31:0] (cid:197) SRC1[31:0] >> COUNT;
82 | FI;
83 |

Intel C/C++ Compiler Intrinsic Equivalent

84 |

Compiler auto generates KSHIFTRW when needed.

85 |

Flags Affected

86 |

None

87 |

SIMD Floating-Point Exceptions

88 |

None

89 |

Other Exceptions

90 |

See Exceptions Type K20.

-------------------------------------------------------------------------------- /html/KUNPCKBW_KUNPCKWD_KUNPCKDQ.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | KUNPCKBW/KUNPCKWD/KUNPCKDQ—Unpack for Mask Registers 8 | 9 |

KUNPCKBW/KUNPCKWD/KUNPCKDQ—Unpack for Mask Registers

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
VEX.NDS.L1.66.0F.W0 4B /r KUNPCKBW k1, k2, k3RVRV/VAVX512FUnpack and interleave 8 bits masks in k2 and k3 and write word result in k1.
VEX.NDS.L1.0F.W0 4B /r KUNPCKWD k1, k2, k3RVRV/VAVX512BWUnpack and interleave 16 bits in k2 and k3 and write double-word result in k1.
VEX.NDS.L1.0F.W1 4B /r KUNPCKDQ k1, k2, k3RVRV/VAVX512BWUnpack and interleave 32 bits masks in k2 and k3 and write quadword result in k1.
35 |

Instruction Operand Encoding

36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 |
Op/EnOperand 1Operand 2Operand 3
RVRModRM:reg (w)VEX.1vvv (r)ModRM:r/m (r, ModRM:[7:6] must be 11b)
47 |

Description

48 |

Unpacks the lower 8/16/32 bits of the second and third operands (source operands) into the low part of the first operand (destination operand), starting from the low bytes. The result is zero-extended in the destination.

49 |

Operation

50 |

KUNPCKBW

51 | 
DEST[7:0] (cid:197) SRC2[7:0]
52 | DEST[15:8] (cid:197) SRC1[7:0]
53 | DEST[MAX_KL-1:16] (cid:197) 0
54 |

KUNPCKWD

55 | 
DEST[15:0] (cid:197) SRC2[15:0]
56 | DEST[31:16] (cid:197) SRC1[15:0] DEST[MAX_KL-1:32] (cid:197) 0
57 |

KUNPCKDQ

58 | 
DEST[31:0] (cid:197) SRC2[31:0]
59 | DEST[63:32] (cid:197) SRC1[31:0] DEST[MAX_KL-1:64] (cid:197) 0
60 |

Intel C/C++ Compiler Intrinsic Equivalent

61 |

KUNPCKBW __mmask16 _mm512_kunpackb(__mmask16 a, __mmask16 b);

62 |

KUNPCKDQ __mmask64 _mm512_kunpackd(__mmask64 a, __mmask64 b);

63 |

KUNPCKWD __mmask32 _mm512_kunpackw(__mmask32 a, __mmask32 b);

64 |

Flags Affected

65 |

None

66 |

SIMD Floating-Point Exceptions

67 |

None

68 |

Other Exceptions

69 |

See Exceptions Type K20.

-------------------------------------------------------------------------------- /html/KXNORW_KXNORB_KXNORQ_KXNORD.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | KXNORW/KXNORB/KXNORQ/KXNORD—Bitwise Logical XNOR Masks 8 | 9 |

KXNORW/KXNORB/KXNORQ/KXNORD—Bitwise Logical XNOR Masks

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
VEX.NDS.L1.0F.W0 46 /r KXNORW k1, k2, k3RVRV/VAVX512FBitwise XNOR 16 bits masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 46 /r KXNORB k1, k2, k3RVRV/VAVX512DQBitwise XNOR 8 bits masks k2 and k3 and place result in k1.
VEX.L1.0F.W1 46 /r KXNORQ k1, k2, k3RVRV/VAVX512BWBitwise XNOR 64 bits masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W1 46 /r KXNORD k1, k2, k3RVRV/VAVX512BWBitwise XNOR 32 bits masks k2 and k3 and place result in k1.
41 |

Instruction Operand Encoding

42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 |
Op/EnOperand 1Operand 2Operand 3
RVRModRM:reg (w)VEX.1vvv (r)ModRM:r/m (r, ModRM:[7:6] must be 11b)
53 |

Description

54 |

Performs a bitwise XNOR between the vector mask k2 and the vector mask k3, and writes the result into vector mask k1 (three-operand form).

55 |

Operation

56 |

KXNORW

57 | 
DEST[15:0] (cid:197) NOT (SRC1[15:0] BITWISE XOR SRC2[15:0])
58 | DEST[MAX_KL-1:16] (cid:197) 0
59 |

KXNORB

60 | 
DEST[7:0] (cid:197) NOT (SRC1[7:0] BITWISE XOR SRC2[7:0])
61 | DEST[MAX_KL-1:8] (cid:197) 0
62 |

KXNORQ

63 | 
DEST[63:0] (cid:197) NOT (SRC1[63:0] BITWISE XOR SRC2[63:0])
64 | DEST[MAX_KL-1:64] (cid:197) 0
65 |

KXNORD

66 | 
DEST[31:0] (cid:197) NOT (SRC1[31:0] BITWISE XOR SRC2[31:0])
67 | DEST[MAX_KL-1:32] (cid:197) 0
68 |

Intel C/C++ Compiler Intrinsic Equivalent

69 |

KXNORW __mmask16 _mm512_kxnor(__mmask16 a, __mmask16 b);

70 |

Flags Affected

71 |

None

72 |

SIMD Floating-Point Exceptions

73 |

None

74 |

Other Exceptions

75 |

See Exceptions Type K20.

-------------------------------------------------------------------------------- /html/KXORW_KXORB_KXORQ_KXORD.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | KXORW/KXORB/KXORQ/KXORD—Bitwise Logical XOR Masks 8 | 9 |

KXORW/KXORB/KXORQ/KXORD—Bitwise Logical XOR Masks

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
VEX.NDS.L1.0F.W0 47 /r KXORW k1, k2, k3RVRV/VAVX512FBitwise XOR 16 bits masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W0 47 /r KXORB k1, k2, k3RVRV/VAVX512DQBitwise XOR 8 bits masks k2 and k3 and place result in k1.
VEX.L1.0F.W1 47 /r KXORQ k1, k2, k3RVRV/VAVX512BWBitwise XOR 64 bits masks k2 and k3 and place result in k1.
VEX.L1.66.0F.W1 47 /r KXORD k1, k2, k3RVRV/VAVX512BWBitwise XOR 32 bits masks k2 and k3 and place result in k1.
41 |

Instruction Operand Encoding

42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 |
Op/EnOperand 1Operand 2Operand 3
RVRModRM:reg (w)VEX.1vvv (r)ModRM:r/m (r, ModRM:[7:6] must be 11b)
53 |

Description

54 |

Performs a bitwise XOR between the vector mask k2 and the vector mask k3, and writes the result into vector mask k1 (three-operand form).

55 |

Operation

56 |

KXORW

57 | 
DEST[15:0] (cid:197) SRC1[15:0] BITWISE XOR SRC2[15:0]
58 | DEST[MAX_KL-1:16] (cid:197) 0
59 |

KXORB

60 | 
DEST[7:0] (cid:197) SRC1[7:0] BITWISE XOR SRC2[7:0]
61 | DEST[MAX_KL-1:8] (cid:197) 0
62 |

KXORQ

63 | 
DEST[63:0] (cid:197) SRC1[63:0] BITWISE XOR SRC2[63:0]
64 | DEST[MAX_KL-1:64] (cid:197) 0
65 |

KXORD

66 | 
DEST[31:0] (cid:197) SRC1[31:0] BITWISE XOR SRC2[31:0]
67 | DEST[MAX_KL-1:32] (cid:197) 0
68 |

Intel C/C++ Compiler Intrinsic Equivalent

69 |

KXORW __mmask16 _mm512_kxor(__mmask16 a, __mmask16 b);

70 |

Flags Affected

71 |

None

72 |

SIMD Floating-Point Exceptions

73 |

None

74 |

Other Exceptions

75 |

See Exceptions Type K20.

-------------------------------------------------------------------------------- /html/LAHF.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | LAHF—Load Status Flags into AH Register 8 | 9 |

LAHF—Load Status Flags into AH Register

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-Bit ModeCompat/Leg ModeDescription
9FLAHFNPInvalid*ValidLoad: AH ← EFLAGS(SF:ZF:0:AF:0:PF:1:CF).
25 |

NOTES: *Valid in specific steppings. See Description section.

26 |

Instruction Operand Encoding

27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
40 |

Description

41 |

This instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.

42 |

Operation

43 | 
IF 64-Bit Mode
44 |     THEN
45 |          IF CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1;
46 |               THEN AH ← RFLAGS(SF:ZF:0:AF:0:PF:1:CF); ELSE #UD;
47 |          FI;
48 |     ELSE
49 |          AH ← EFLAGS(SF:ZF:0:AF:0:PF:1:CF);
50 | FI;
51 |

Flags Affected

52 |

None. The state of the flags in the EFLAGS register is not affected.

53 |

Protected Mode Exceptions

54 | 55 | 56 | 57 |
#UDIf the LOCK prefix is used.
58 |

Real-Address Mode Exceptions

59 |

Same exceptions as in protected mode.

60 |

Virtual-8086 Mode Exceptions

61 |

Same exceptions as in protected mode.

62 |

Compatibility Mode Exceptions

63 |

Same exceptions as in protected mode.

64 |

64-Bit Mode Exceptions

65 | 66 | 67 | 68 |
#UD 69 |

If CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 0.

70 |

If the LOCK prefix is used.

-------------------------------------------------------------------------------- /html/LDDQU.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | LDDQU—Load Unaligned Integer 128 Bits 8 | 9 |

LDDQU—Load Unaligned Integer 128 Bits

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 | 25 | 26 | 29 | 30 | 31 | 32 | 33 | 34 | 37 | 38 | 39 | 40 |
Opcode/InstructionOp/En64/32-bit ModeCPUID Feature FlagDescription
19 |

F2 0F F0 /r

20 |

LDDQU xmm1, mem

RMV/VSSE3Load unaligned data from mem and return double quadword in xmm1.
27 |

VEX.128.F2.0F.WIG F0 /r

28 |

VLDDQU xmm1, m128

RMV/VAVXLoad unaligned packed integer values from mem to xmm1.
35 |

VEX.256.F2.0F.WIG F0 /r

36 |

VLDDQU ymm1, m256

RMV/VAVXLoad unaligned packed integer values from mem to ymm1.
41 |

Instruction Operand Encoding

42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RMModRM:reg (w)ModRM:r/m (r)NANA
55 |

Description

56 |

The instruction is functionally similar to (V)MOVDQU ymm/xmm, m256/m128 for loading from memory. That is: 32/16 bytes of data starting at an address specified by the source memory operand (second operand) are fetched from memory and placed in a destination register (first operand). The source operand need not be aligned on a 32/16-byte boundary. Up to 64/32 bytes may be loaded from memory; this is implementation dependent.

57 |

This instruction may improve performance relative to (V)MOVDQU if the source operand crosses a cache line boundary. In situations that require the data loaded by (V)LDDQU be modified and stored to the same location, use (V)MOVDQU or (V)MOVDQA instead of (V)LDDQU. To move a double quadword to or from memory locations that are known to be aligned on 16-byte boundaries, use the (V)MOVDQA instruction.

58 |

Implementation Notes

59 |

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

60 |

Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

61 |

Operation

62 |

LDDQU (128-bit Legacy SSE version)

63 | 
DEST[127:0] (cid:197) SRC[127:0]
64 | DEST[VLMAX-1:128] (Unmodified)
65 |

VLDDQU (VEX.128 encoded version)

66 | 
DEST[127:0] (cid:197) SRC[127:0]
67 | DEST[VLMAX-1:128] (cid:197) 0
68 |

VLDDQU (VEX.256 encoded version)

69 | 
DEST[255:0] (cid:197) SRC[255:0]
70 |

Intel C/C++ Compiler Intrinsic Equivalent

71 |

LDDQU:

72 |

__m128i _mm_lddqu_si128 (__m128i * p);

73 |

VLDDQU: __m256i _mm256_lddqu_si256 (__m256i * p);

74 |

Numeric Exceptions

75 |

None

76 |

Other Exceptions

77 |

See Exceptions Type 4;

78 |

Note treatment of #AC varies.

-------------------------------------------------------------------------------- /html/LDMXCSR.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | LDMXCSR—Load MXCSR Register 8 | 9 |

LDMXCSR—Load MXCSR Register

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 | 25 | 26 | 29 | 30 | 31 | 32 |
Opcode/InstructionOp/En64/32-bit ModeCPUID Feature FlagDescription
19 |

0F AE /2

20 |

LDMXCSR m32

MV/VSSELoad MXCSR register from m32.
27 |

VEX.LZ.0F.WIG AE /2

28 |

VLDMXCSR m32

MV/VAVXLoad MXCSR register from m32.
33 |

Instruction Operand Encoding

34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 |
Op/EnOperand 1Operand 2Operand 3Operand 4
MModRM:r/m (r)NANANA
47 |

Description

48 |

Loads the source operand into the MXCSR control/status register. The source operand is a 32-bit memory location. See “MXCSR Control and Status Register” in Chapter 10, of the Intel® 64 and IA-32 Architectures Software Devel-oper’s Manual, Volume 1, for a description of the MXCSR register and its contents.

49 |

The LDMXCSR instruction is typically used in conjunction with the (V)STMXCSR instruction, which stores the contents of the MXCSR register in memory.

50 |

The default MXCSR value at reset is 1F80H.

51 |

If a (V)LDMXCSR instruction clears a SIMD floating-point exception mask bit and sets the corresponding exception flag bit, a SIMD floating-point exception will not be immediately generated. The exception will be generated only upon the execution of the next instruction that meets both conditions below:

52 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

53 |

If VLDMXCSR is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an #UD exception.

54 |

Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

55 |

Operation

56 | 
MXCSR ← m32;
57 |

C/C++ Compiler Intrinsic Equivalent

58 |

_mm_setcsr(unsigned int i)

59 |

Numeric Exceptions

60 |

None

61 |

Other Exceptions

62 |

See Exceptions Type 5; additionally

63 | 64 | 65 | 66 | 67 | 68 | 69 |
#GPFor an attempt to set reserved bits in MXCSR.
#UDIf VEX.vvvv ≠ 1111B.
-------------------------------------------------------------------------------- /html/LFENCE.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | LFENCE—Load Fence 8 | 9 |

LFENCE—Load Fence

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-Bit ModeCompat/Leg ModeDescription
0F AE E8LFENCENPValidValidSerializes load operations.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Performs a serializing operation on all load-from-memory instructions that were issued prior the LFENCE instruc-tion. Specifically, LFENCE does not execute until all prior instructions have completed locally, and no later instruc-tion begins execution until LFENCE completes. In particular, an instruction that loads from memory and that precedes an LFENCE receives data from memory prior to completion of the LFENCE. (An LFENCE that follows an instruction that stores to memory might complete before the data being stored have become globally visible.) Instructions following an LFENCE may be fetched from memory before the LFENCE, but they will not execute until the LFENCE completes.

41 |

Weakly ordered memory types can be used to achieve higher processor performance through such techniques as out-of-order issue and speculative reads. The degree to which a consumer of data recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the producer of this data. The LFENCE instruction provides a performance-efficient way of ensuring load ordering between routines that produce weakly-ordered results and routines that consume that data.

42 |

Processors are free to fetch and cache data speculatively from regions of system memory that use the WB, WC, and WT memory types. This speculative fetching can occur at any time and is not tied to instruction execution. Thus, it is not ordered with respect to executions of the LFENCE instruction; data can be brought into the caches specula-tively just before, during, or after the execution of an LFENCE instruction.

43 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

44 |

Specification of the instruction's opcode above indicates a ModR/M byte of E8. For this instruction, the processor ignores the r/m field of the ModR/M byte. Thus, LFENCE is encoded by any opcode of the form 0F AE Ex, where x is in the range 8-F.

45 |

Operation

46 | 
Wait_On_Following_Instructions_Until(preceding_instructions_complete);
47 |

Intel C/C++ Compiler Intrinsic Equivalent

48 |

void _mm_lfence(void)

49 |

Exceptions (All Modes of Operation)

50 |

#UD

51 |

If CPUID.01H:EDX.SSE2[bit 26] = 0.

52 |

If the LOCK prefix is used.

-------------------------------------------------------------------------------- /html/MOVDQ2Q.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | MOVDQ2Q—Move Quadword from XMM to MMX Technology Register 8 | 9 |

MOVDQ2Q—Move Quadword from XMM to MMX Technology Register

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-Bit ModeCompat/Leg ModeDescription
F2 0F D6 /rMOVDQ2Q mm, xmmRMValidValidMove low quadword from xmm to mmx register.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RMModRM:reg (w)ModRM:r/m (r)NANA
39 |

Description

40 |

Moves the low quadword from the source operand (second operand) to the destination operand (first operand). The source operand is an XMM register and the destination operand is an MMX technology register.

41 |

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the MOVDQ2Q instruction is executed.

42 |

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

43 |

Operation

44 | 
DEST ← SRC[63:0];
45 |

Intel C/C++ Compiler Intrinsic Equivalent

46 |

MOVDQ2Q:

47 |

__m64 _mm_movepi64_pi64 ( __m128i a)

48 |

SIMD Floating-Point Exceptions

49 |

None.

50 |

Protected Mode Exceptions

51 | 52 | 53 | 54 | 55 | 56 | 57 | 62 | 63 | 64 |
#NMIf CR0.TS[bit 3] = 1.
#UD 58 |

If CR0.EM[bit 2] = 1.

59 |

If CR4.OSFXSR[bit 9] = 0.

60 |

If CPUID.01H:EDX.SSE2[bit 26] = 0.

61 |

If the LOCK prefix is used.

#MFIf there is a pending x87 FPU exception.
65 |

Real-Address Mode Exceptions

66 |

Same exceptions as in protected mode.

67 |

Virtual-8086 Mode Exceptions

68 |

Same exceptions as in protected mode.

69 |

Compatibility Mode Exceptions

70 |

Same exceptions as in protected mode.

71 |

64-Bit Mode Exceptions

72 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/MOVNTQ.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | MOVNTQ—Store of Quadword Using Non-Temporal Hint 8 | 9 |

MOVNTQ—Store of Quadword Using Non-Temporal Hint

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-Bit ModeCompat/Leg ModeDescription
0F E7 /rMOVNTQ m64, mmMRValidValidMove quadword from mm to m64 using non-temporal hint.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
MRModRM:r/m (w)ModRM:reg (r)NANA
39 |

Description

40 |

Moves the quadword in the source operand (second operand) to the destination operand (first operand) using a non-temporal hint to minimize cache pollution during the write to memory. The source operand is an MMX tech-nology register, which is assumed to contain packed integer data (packed bytes, words, or doublewords). The destination operand is a 64-bit memory location.

41 |

The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see “Caching of Temporal vs. Non-Temporal Data” in Chapter 10 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.

42 |

Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with the SFENCE or MFENCE instruction should be used in conjunction with MOVNTQ instructions if multiple processors might use different memory types to read/write the destination memory locations.

43 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

44 |

Operation

45 | 
DEST ← SRC;
46 |

Intel C/C++ Compiler Intrinsic Equivalent

47 |

MOVNTQ:

48 |

void _mm_stream_pi(__m64 * p, __m64 a)

49 |

SIMD Floating-Point Exceptions

50 |

None.

51 |

Other Exceptions

52 |

See Table 22-8, “Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

-------------------------------------------------------------------------------- /html/MOVQ2DQ.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | MOVQ2DQ—Move Quadword from MMX Technology to XMM Register 8 | 9 |

MOVQ2DQ—Move Quadword from MMX Technology to XMM Register

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-Bit ModeCompat/Leg ModeDescription
F3 0F D6 /rMOVQ2DQ xmm, mmRMValidValidMove quadword from mmx to low quadword of xmm.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RMModRM:reg (w)ModRM:r/m (r)NANA
39 |

Description

40 |

Moves the quadword from the source operand (second operand) to the low quadword of the destination operand (first operand). The source operand is an MMX technology register and the destination operand is an XMM register.

41 |

This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the MOVQ2DQ instruction is executed.

42 |

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

43 |

Operation

44 | 
DEST[63:0] ← SRC[63:0];
45 | DEST[127:64] ← 00000000000000000H;
46 |

Intel C/C++ Compiler Intrinsic Equivalent

47 |

MOVQ2DQ:

48 |

__128i _mm_movpi64_pi64 ( __m64 a)

49 |

SIMD Floating-Point Exceptions

50 |

None.

51 |

Protected Mode Exceptions

52 | 53 | 54 | 55 | 56 | 57 | 58 | 63 | 64 | 65 |
#NMIf CR0.TS[bit 3] = 1.
#UD 59 |

If CR0.EM[bit 2] = 1.

60 |

If CR4.OSFXSR[bit 9] = 0.

61 |

If CPUID.01H:EDX.SSE2[bit 26] = 0.

62 |

If the LOCK prefix is used.

#MFIf there is a pending x87 FPU exception.
66 |

Real-Address Mode Exceptions

67 |

Same exceptions as in protected mode.

68 |

Virtual-8086 Mode Exceptions

69 |

Same exceptions as in protected mode.

70 |

Compatibility Mode Exceptions

71 |

Same exceptions as in protected mode.

72 |

64-Bit Mode Exceptions

73 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/MULX.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | MULX — Unsigned Multiply Without Affecting Flags 8 | 9 |

MULX — Unsigned Multiply Without Affecting Flags

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 | 25 | 26 | 29 | 30 | 31 | 32 |
Opcode/InstructionOp/En64/32 -bit ModeCPUID Feature FlagDescription
19 |

VEX.NDD.LZ.F2.0F38.W0 F6 /r

20 |

MULX r32a, r32b, r/m32

RVMV/VBMI2Unsigned multiply of r/m32 with EDX without affecting arithmetic flags.
27 |

VEX.NDD.LZ.F2.0F38.W1 F6 /r

28 |

MULX r64a, r64b, r/m64

RVMV/N.E.BMI2Unsigned multiply of r/m64 with RDX without affecting arithmetic flags.
33 |

Instruction Operand Encoding

34 | 35 | 36 | 39 | 42 | 45 | 48 |
37 |

Op/En

38 |

RVM

 40 |

Operand 1

41 |

ModRM:reg (w)

 43 |

Operand 2

44 |

VEX.vvvv (w)

 46 |

Operand 3

47 |

ModRM:r/m (r)

 49 |

Operand 4

50 |

RDX/EDX is implied 64/32 bits

51 |

source

52 |

Description

53 |

Performs an unsigned multiplication of the implicit source operand (EDX/RDX) and the specified source operand (the third operand) and stores the low half of the result in the second destination (second operand), the high half of the result in the first destination operand (first operand), without reading or writing the arithmetic flags. This enables efficient programming where the software can interleave add with carry operations and multiplications.

54 |

If the first and second operand are identical, it will contain the high half of the multiplication result.

55 |

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

56 |

Operation

57 | 
// DEST1: ModRM:reg
58 | // DEST2: VEX.vvvv
59 | IF (OperandSize = 32)
60 |     SRC1 ← EDX;
61 |     DEST2 ← (SRC1*SRC2)[31:0];
62 |     DEST1 ← (SRC1*SRC2)[63:32];
63 | ELSE IF (OperandSize = 64)
64 |     SRC1 ← RDX;
65 |          DEST2 ← (SRC1*SRC2)[63:0];
66 |          DEST1 ← (SRC1*SRC2)[127:64];
67 | FI
68 |

Flags Affected

69 |

None

70 |

Intel C/C++ Compiler Intrinsic Equivalent

71 |

Auto-generated from high-level language when possible.

72 |

unsigned int mulx_u32(unsigned int a, unsigned int b, unsigned int * hi);

73 |

unsigned __int64 mulx_u64(unsigned __int64 a, unsigned __int64 b, unsigned __int64 * hi);

74 |

SIMD Floating-Point Exceptions

75 |

None

76 |

Other Exceptions

77 |

See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally

78 | 79 | 80 | 81 |
#UDIf VEX.W = 1.
-------------------------------------------------------------------------------- /html/PAUSE.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | PAUSE—Spin Loop Hint 8 | 9 |

PAUSE—Spin Loop Hint

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-Bit ModeCompat/Leg ModeDescription
F3 90PAUSENPValidValidGives hint to processor that improves performance of spin-wait loops.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Improves the performance of spin-wait loops. When executing a “spin-wait loop,” processors will suffer a severe performance penalty when exiting the loop because it detects a possible memory order violation. The PAUSE instruction provides a hint to the processor that the code sequence is a spin-wait loop. The processor uses this hint to avoid the memory order violation in most situations, which greatly improves processor performance. For this reason, it is recommended that a PAUSE instruction be placed in all spin-wait loops.

41 |

An additional function of the PAUSE instruction is to reduce the power consumed by a processor while executing a spin loop. A processor can execute a spin-wait loop extremely quickly, causing the processor to consume a lot of power while it waits for the resource it is spinning on to become available. Inserting a pause instruction in a spin-wait loop greatly reduces the processor’s power consumption.

42 |

This instruction was introduced in the Pentium 4 processors, but is backward compatible with all IA-32 processors. In earlier IA-32 processors, the PAUSE instruction operates like a NOP instruction. The Pentium 4 and Intel Xeon processors implement the PAUSE instruction as a delay. The delay is finite and can be zero for some processors. This instruction does not change the architectural state of the processor (that is, it performs essentially a delaying no-op operation).

43 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

44 |

Operation

45 | 
Execute_Next_Instruction(DELAY);
46 |

Numeric Exceptions

47 |

None.

48 |

Exceptions (All Operating Modes)

49 | 50 | 51 | 52 |
#UDIf the LOCK prefix is used.
-------------------------------------------------------------------------------- /html/PSHUFW.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | PSHUFW—Shuffle Packed Words 8 | 9 |

PSHUFW—Shuffle Packed Words

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64-Bit ModeCompat/Leg ModeDescription
19 |

0F 70 /r ib

20 |

PSHUFW mm1, mm2/m64, imm8

RMIValidValidShuffle the words in mm2/m64 based on the encoding in imm8 and store the result in mm1.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RMIModRM:reg (w)ModRM:r/m (r)imm8NA
39 |

Description

40 |

Copies words from the source operand (second operand) and inserts them in the destination operand (first operand) at word locations selected with the order operand (third operand). This operation is similar to the opera-tion used by the PSHUFD instruction, which is illustrated in Figure 4-16. For the PSHUFW instruction, each 2-bit field in the order operand selects the contents of one word location in the destination operand. The encodings of the order operand fields select words from the source operand to be copied to the destination operand.

41 |

The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an MMX technology register. The order operand is an 8-bit immediate. Note that this instruction permits a word in the source operand to be copied to more than one word location in the destination operand.

42 |

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

43 |

Operation

44 | 
DEST[15:0] ← (SRC >> (ORDER[1:0] * 16))[15:0];
45 | DEST[31:16] ← (SRC >> (ORDER[3:2] * 16))[15:0];
46 | DEST[47:32] ← (SRC >> (ORDER[5:4] * 16))[15:0];
47 | DEST[63:48] ← (SRC >> (ORDER[7:6] * 16))[15:0];
48 |

Intel C/C++ Compiler Intrinsic Equivalent

49 |

PSHUFW:

50 |

__m64 _mm_shuffle_pi16(__m64 a, int n)

51 |

Flags Affected

52 |

None.

53 |

Numeric Exceptions

54 |

None.

55 |

Other Exceptions

56 |

See Table 22-7, “Exception Conditions for SIMD/MMX Instructions with Memory Reference,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

-------------------------------------------------------------------------------- /html/RDPID.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | RDPID—Read Processor ID 8 | 9 |

RDPID—Read Processor ID

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 |
Opcode/InstructionOp/En64/32-bit ModeCPUID Feature FlagDescription
F3 0F C7 /7 RDPID r32MN.E./VRDPIDRead IA32_TSC_AUX into r32.
F3 0F C7 /7 RDPID r64MV/N.E.RDPIDRead IA32_TSC_AUX into r64.
29 |

Instruction Operand Encoding

30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 |
Op/EnOperand 1Operand 2Operand 3Operand 4
MModRM:r/m (w)NANANA
43 |

Description

44 |

Reads the value of the IA32_TSC_AUX MSR (address C0000103H) into the destination register. The value of CS.D and operand-size prefixes (66H and REX.W) do not affect the behavior of the RDPID instruction.

45 |

Operation

46 | 
DEST ← IA32_TSC_AUX
47 |

Flags Affected

48 |

None.

49 |

Protected Mode Exceptions

50 | 51 | 52 | 53 |
#UD 54 |

If the LOCK prefix is used.

55 |

If the F2 prefix is used.

56 |

If CPUID.7H.0:ECX.RDPID[bit 22] = 0.

57 |

Real-Address Mode Exceptions

58 |

Same exceptions as in protected mode.

59 |

Virtual-8086 Mode Exceptions

60 |

Same exceptions as in protected mode.

61 |

Compatibility Mode Exceptions

62 |

Same exceptions as in protected mode.

63 |

64-Bit Mode Exceptions

64 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/RDPKRU.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | RDPKRU—Read Protection Key Rights for User Pages 8 | 9 |

RDPKRU—Read Protection Key Rights for User Pages

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
Opcode*InstructionOp/En64/32bit Mode SupportCPUID Feature FlagDescription
0F 01 EERDPKRUNPV/VOSPKEReads PKRU into EAX.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Reads the value of PKRU into EAX and clears EDX. ECX must be 0 when RDPKRU is executed; otherwise, a general-protection exception (#GP) occurs.

41 |

RDPKRU can be executed only if CR4.PKE = 1; otherwise, an invalid-opcode exception (#UD) occurs. Software can discover the value of CR4.PKE by examining CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4].

42 |

On processors that support the Intel 64 Architecture, the high-order 32-bits of RCX are ignored and the high-order 32-bits of RDX and RAX are cleared.

43 |

Operation

44 | 
IF (ECX = 0)
45 |     THEN
46 |          EAX ← PKRU;
47 |          EDX ← 0;
48 |     ELSE #GP(0);
49 | FI;
50 |

Flags Affected

51 |

None.

52 |

C/C++ Compiler Intrinsic Equivalent

53 |

RDPKRU:

54 |

uint32_t _rdpkru_u32(void);

55 |

Protected Mode Exceptions

56 | 57 | 58 | 59 | 60 | 61 | 62 |
#GP(0)If ECX ≠ 0
#UD 63 |

If the LOCK prefix is used.

64 |

If CR4.PKE = 0.

65 |

Real-Address Mode Exceptions

66 |

Same exceptions as in protected mode.

67 |

Virtual-8086 Mode Exceptions

68 |

Same exceptions as in protected mode.

69 |

Compatibility Mode Exceptions

70 |

Same exceptions as in protected mode.

71 |

64-Bit Mode Exceptions

72 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/RORX.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | RORX — Rotate Right Logical Without Affecting Flags 8 | 9 |

RORX — Rotate Right Logical Without Affecting Flags

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 | 25 | 26 | 29 | 30 | 31 | 32 |
Opcode/InstructionOp/En64/32 -bit ModeCPUID Feature FlagDescription
19 |

VEX.LZ.F2.0F3A.W0 F0 /r ib

20 |

RORX r32, r/m32, imm8

RMIV/VBMI2Rotate 32-bit r/m32 right imm8 times without affecting arithmetic flags.
27 |

VEX.LZ.F2.0F3A.W1 F0 /r ib

28 |

RORX r64, r/m64, imm8

RMIV/N.E.BMI2Rotate 64-bit r/m64 right imm8 times without affecting arithmetic flags.
33 |

Instruction Operand Encoding

34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RMIModRM:reg (w)ModRM:r/m (r)Imm8NA
47 |

Description

48 |

Rotates the bits of second operand right by the count value specified in imm8 without affecting arithmetic flags. The RORX instruction does not read or write the arithmetic flags.

49 |

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

50 |

Operation

51 | 
IF (OperandSize = 32)
52 |     y ← imm8 AND 1FH;
53 |     DEST ← (SRC >> y) | (SRC << (32-y));
54 | ELSEIF (OperandSize = 64 )
55 |     y ← imm8 AND 3FH;
56 |     DEST ← (SRC >> y) | (SRC << (64-y));
57 | ENDIF
58 |

Flags Affected

59 |

None

60 |

Intel C/C++ Compiler Intrinsic Equivalent

61 |

Auto-generated from high-level language.

62 |

SIMD Floating-Point Exceptions

63 |

None

64 |

Other Exceptions

65 |

See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally

66 | 67 | 68 | 69 |
#UDIf VEX.W = 1.
-------------------------------------------------------------------------------- /html/RSM.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | RSM—Resume from System Management Mode 8 | 9 |

RSM—Resume from System Management Mode

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
Opcode*InstructionOp/En64-Bit ModeCompat/Leg ModeDescription
0F AARSMNPValidValidResume operation of interrupted program.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Returns program control from system management mode (SMM) to the application program or operating-system procedure that was interrupted when the processor received an SMM interrupt. The processor’s state is restored from the dump created upon entering SMM. If the processor detects invalid state information during state restora-tion, it enters the shutdown state. The following invalid information can cause a shutdown:

41 |

The contents of the model-specific registers are not affected by a return from SMM.

42 |

The SMM state map used by RSM supports resuming processor context for non-64-bit modes and 64-bit mode.

43 |

See Chapter 34, “System Management Mode,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, for more information about SMM and the behavior of the RSM instruction.

44 |

Operation

45 | 
ReturnFromSMM;
46 | IF (IA-32e mode supported) or (CPUID DisplayFamily_DisplayModel = 06H_0CH )
47 |     THEN
48 |          ProcessorState ← Restore(SMMDump(IA-32e SMM STATE MAP));
49 |     Else
50 |          ProcessorState ← Restore(SMMDump(Non-32-Bit-Mode SMM STATE MAP));
51 | FI
52 |

Flags Affected

53 |

All.

54 |

Protected Mode Exceptions

55 | 56 | 57 | 58 |
#UD 59 |

If an attempt is made to execute this instruction when the processor is not in SMM.

60 |

If the LOCK prefix is used.

61 |

Real-Address Mode Exceptions

62 |

Same exceptions as in protected mode.

63 |

Virtual-8086 Mode Exceptions

64 |

Same exceptions as in protected mode.

65 |

Compatibility Mode Exceptions

66 |

Same exceptions as in protected mode.

67 |

64-Bit Mode Exceptions

68 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/SAHF.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | SAHF—Store AH into Flags 8 | 9 |

SAHF—Store AH into Flags

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
Opcode*InstructionOp/En64-Bit ModeCompat/Leg ModeDescription
9ESAHFNPInvalid*ValidLoads SF, ZF, AF, PF, and CF from AH into EFLAGS register.
25 |

NOTES: * Valid in specific steppings. See Description section.

26 |

Instruction Operand Encoding

27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
40 |

Description

41 |

Loads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values from the corresponding bits in the AH register (bits 7, 6, 4, 2, and 0, respectively). Bits 1, 3, and 5 of register AH are ignored; the corresponding reserved bits (1, 3, and 5) in the EFLAGS register remain as shown in the “Operation” section below.

42 |

This instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.

43 |

Operation

44 | 
IF IA-64 Mode
45 |     THEN
46 |          IF CPUID.80000001H.ECX[0] = 1;
47 |               THEN
48 |                     RFLAGS(SF:ZF:0:AF:0:PF:1:CF) ← AH;
49 |               ELSE
50 |                     #UD;
51 |          FI
52 |     ELSE
53 |          EFLAGS(SF:ZF:0:AF:0:PF:1:CF) ← AH;
54 | FI;
55 |

Flags Affected

56 |

The SF, ZF, AF, PF, and CF flags are loaded with values from the AH register. Bits 1, 3, and 5 of the EFLAGS register are unaffected, with the values remaining 1, 0, and 0, respectively.

57 |

Protected Mode Exceptions

58 |

None.

59 |

Real-Address Mode Exceptions

60 |

None.

61 |

Virtual-8086 Mode Exceptions

62 |

None.

63 |

Compatibility Mode Exceptions

64 |

None.

65 |

64-Bit Mode Exceptions

66 | 67 | 68 | 69 |
#UD 70 |

If CPUID.80000001H.ECX[0] = 0.

71 |

If the LOCK prefix is used.

-------------------------------------------------------------------------------- /html/SFENCE.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | SFENCE—Store Fence 8 | 9 |

SFENCE—Store Fence

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
Opcode*InstructionOp/En64-Bit ModeCompat/Leg ModeDescription
0F AE F8SFENCENPValidValidSerializes store operations.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Performs a serializing operation on all store-to-memory instructions that were issued prior the SFENCE instruction. This serializing operation guarantees that every store instruction that precedes the SFENCE instruction in program order becomes globally visible before any store instruction that follows the SFENCE instruction. The SFENCE instruction is ordered with respect to store instructions, other SFENCE instructions, any LFENCE and MFENCE instructions, and any serializing instructions (such as the CPUID instruction). It is not ordered with respect to load instructions.

41 |

Weakly ordered memory types can be used to achieve higher processor performance through such techniques as out-of-order issue, write-combining, and write-collapsing. The degree to which a consumer of data recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the producer of this data. The SFENCE instruction provides a performance-efficient way of ensuring store ordering between routines that produce weakly-ordered results and routines that consume this data.

42 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

43 |

Specification of the instruction's opcode above indicates a ModR/M byte of F8. For this instruction, the processor ignores the r/m field of the ModR/M byte. Thus, SFENCE is encoded by any opcode of the form 0F AE Fx, where x is in the range 8-F.

44 |

Operation

45 | 
Wait_On_Following_Stores_Until(preceding_stores_globally_visible);
46 |

Intel C/C++ Compiler Intrinsic Equivalent

47 |

void _mm_sfence(void)

48 |

Exceptions (All Operating Modes)

49 |

#UD

50 |

If CPUID.01H:EDX.SSE[bit 25] = 0.

51 |

If the LOCK prefix is used.

-------------------------------------------------------------------------------- /html/SHA1MSG1.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | SHA1MSG1—Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords 8 | 9 |

SHA1MSG1—Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
19 |

0F 38 C9 /r

20 |

SHA1MSG1 xmm1, xmm2/m128

RMV/VSHAPerforms an intermediate calculation for the next four SHA1 message dwords using previous message dwords from xmm1 and xmm2/m128, storing the result in xmm1.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 |
Op/EnOperand 1Operand 2Operand 3
RMModRM:reg (r, w)ModRM:r/m (r)NA
37 |

Description

38 |

The SHA1MSG1 instruction is one of two SHA1 message scheduling instructions. The instruction performs an inter-mediate calculation for the next four SHA1 message dwords.

39 |

Operation

40 |

SHA1MSG1

41 |

W0 (cid:197) SRC1[127:96] ;

42 |

W1 (cid:197) SRC1[95:64] ;

43 |

W2 (cid:197) SRC1[63: 32] ;

44 |

W3 (cid:197) SRC1[31: 0] ;

45 |

W4 (cid:197) SRC2[127:96] ;

46 |

W5 (cid:197) SRC2[95:64] ;

47 |

DEST[127:96] (cid:197) W2 XOR W0;

48 |

DEST[95:64] (cid:197) W3 XOR W1;

49 |

DEST[63:32] (cid:197) W4 XOR W2;

50 |

DEST[31:0] (cid:197) W5 XOR W3;

51 |

Intel C/C++ Compiler Intrinsic Equivalent

52 |

SHA1MSG1: __m128i _mm_sha1msg1_epu32(__m128i, __m128i);

53 |

Flags Affected

54 |

None

55 |

SIMD Floating-Point Exceptions

56 |

None

57 |

Other Exceptions

58 |

See Exceptions Type 4.

-------------------------------------------------------------------------------- /html/SHA1MSG2.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | SHA1MSG2—Perform a Final Calculation for the Next Four SHA1 Message Dwords 8 | 9 |

SHA1MSG2—Perform a Final Calculation for the Next Four SHA1 Message Dwords

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
19 |

0F 38 CA /r

20 |

SHA1MSG2 xmm1, xmm2/m128

RMV/VSHAPerforms the final calculation for the next four SHA1 message dwords using intermediate results from xmm1 and the previous message dwords from xmm2/m128, storing the result in xmm1.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 |
Op/EnOperand 1Operand 2Operand 3
RMModRM:reg (r, w)ModRM:r/m (r)NA
37 |

Description

38 |

The SHA1MSG2 instruction is one of two SHA1 message scheduling instructions. The instruction performs the final calculation to derive the next four SHA1 message dwords.

39 |

Operation

40 |

SHA1MSG2

41 |

W13 (cid:197) SRC2[95:64] ;

42 |

W14 (cid:197) SRC2[63: 32] ;

43 |

W15 (cid:197) SRC2[31: 0] ;

44 |

W16 (cid:197) (SRC1[127:96] XOR W13 ) ROL 1;

45 |

W17 (cid:197) (SRC1[95:64] XOR W14) ROL 1;

46 |

W18 (cid:197) (SRC1[63: 32] XOR W15) ROL 1;

47 |

W19 (cid:197) (SRC1[31: 0] XOR W16) ROL 1;

48 |

DEST[127:96] (cid:197) W16;

49 |

DEST[95:64] (cid:197) W17;

50 |

DEST[63:32] (cid:197) W18;

51 |

DEST[31:0] (cid:197) W19;

52 |

Intel C/C++ Compiler Intrinsic Equivalent

53 |

SHA1MSG2: __m128i _mm_sha1msg2_epu32(__m128i, __m128i);

54 |

Flags Affected

55 |

None

56 |

SIMD Floating-Point Exceptions

57 |

None

58 |

Other Exceptions

59 |

See Exceptions Type 4.

-------------------------------------------------------------------------------- /html/SHA1NEXTE.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | SHA1NEXTE—Calculate SHA1 State Variable E after Four Rounds 8 | 9 |

SHA1NEXTE—Calculate SHA1 State Variable E after Four Rounds

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
19 |

0F 38 C8 /r

20 |

SHA1NEXTE xmm1, xmm2/m128

RMV/VSHACalculates SHA1 state variable E after four rounds of operation from the current SHA1 state variable A in xmm1. The calculated value of the SHA1 state variable E is added to the scheduled dwords in xmm2/m128, and stored with some of the scheduled dwords in xmm1.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 |
Op/EnOperand 1Operand 2Operand 3
RMModRM:reg (r, w)ModRM:r/m (r)NA
37 |

Description

38 |

The SHA1NEXTE calculates the SHA1 state variable E after four rounds of operation from the current SHA1 state variable A in the destination operand. The calculated value of the SHA1 state variable E is added to the source operand, which contains the scheduled dwords.

39 |

Operation

40 |

SHA1NEXTE

41 |

TMP (cid:197) (SRC1[127:96] ROL 30);

42 |

DEST[127:96] (cid:197) SRC2[127:96] + TMP;

43 |

DEST[95:64] (cid:197) SRC2[95:64];

44 |

DEST[63:32] (cid:197) SRC2[63:32];

45 |

DEST[31:0] (cid:197) SRC2[31:0];

46 |

Intel C/C++ Compiler Intrinsic Equivalent

47 |

SHA1NEXTE: __m128i _mm_sha1nexte_epu32(__m128i, __m128i);

48 |

Flags Affected

49 |

None

50 |

SIMD Floating-Point Exceptions

51 |

None

52 |

Other Exceptions

53 |

See Exceptions Type 4.

-------------------------------------------------------------------------------- /html/SHA256MSG1.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | SHA256MSG1—Perform an Intermediate Calculation for the Next Four SHA256 Message Dwords 8 | 9 |

SHA256MSG1—Perform an Intermediate Calculation for the Next Four SHA256 Message Dwords

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
19 |

0F 38 CC /r

20 |

SHA256MSG1 xmm1, xmm2/m128

RMV/VSHAPerforms an intermediate calculation for the next four SHA256 message dwords using previous message dwords from xmm1 and xmm2/m128, storing the result in xmm1.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 |
Op/EnOperand 1Operand 2Operand 3
RMModRM:reg (r, w)ModRM:r/m (r)NA
37 |

Description

38 |

The SHA256MSG1 instruction is one of two SHA256 message scheduling instructions. The instruction performs an intermediate calculation for the next four SHA256 message dwords.

39 |

Operation

40 |

SHA256MSG1

41 |

W4 (cid:197) SRC2[31: 0] ;

42 |

W3 (cid:197) SRC1[127:96] ;

43 |

W2 (cid:197) SRC1[95:64] ;

44 |

W1 (cid:197) SRC1[63: 32] ;

45 |

W0 (cid:197) SRC1[31: 0] ;

46 |

DEST[127:96] (cid:197) W3 + σ0( W4);

47 |

DEST[95:64] (cid:197) W2 + σ0( W3);

48 |

DEST[63:32] (cid:197) W1 + σ0( W2);

49 |

DEST[31:0] (cid:197) W0 + σ0( W1);

50 |

Intel C/C++ Compiler Intrinsic Equivalent

51 |

SHA256MSG1: __m128i _mm_sha256msg1_epu32(__m128i, __m128i);

52 |

Flags Affected

53 |

None

54 |

SIMD Floating-Point Exceptions

55 |

None

56 |

Other Exceptions

57 |

See Exceptions Type 4.

-------------------------------------------------------------------------------- /html/SHA256MSG2.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | SHA256MSG2—Perform a Final Calculation for the Next Four SHA256 Message Dwords 8 | 9 |

SHA256MSG2—Perform a Final Calculation for the Next Four SHA256 Message Dwords

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
19 |

0F 38 CD /r

20 |

SHA256MSG2 xmm1, xmm2/m128

RMV/VSHAPerforms the final calculation for the next four SHA256 message dwords using previous message dwords from xmm1 and xmm2/m128, storing the result in xmm1.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 |
Op/EnOperand 1Operand 2Operand 3
RMModRM:reg (r, w)ModRM:r/m (r)NA
37 |

Description

38 |

The SHA256MSG2 instruction is one of two SHA2 message scheduling instructions. The instruction performs the final calculation for the next four SHA256 message dwords.

39 |

Operation

40 |

SHA256MSG2

41 |

W14 (cid:197) SRC2[95:64] ;

42 |

W15 (cid:197) SRC2[127:96] ;

43 |

W16 (cid:197) SRC1[31: 0] + σ1( W14) ;

44 |

W17 (cid:197) SRC1[63: 32] + σ1( W15) ;

45 |

W18 (cid:197) SRC1[95: 64] + σ1( W16) ;

46 |

W19 (cid:197) SRC1[127: 96] + σ1( W17) ;

47 |

DEST[127:96] (cid:197) W19 ;

48 |

DEST[95:64] (cid:197) W18 ;

49 |

DEST[63:32] (cid:197) W17 ;

50 |

DEST[31:0] (cid:197) W16;

51 |

Intel C/C++ Compiler Intrinsic Equivalent

52 |

SHA256MSG2 : __m128i _mm_sha256msg2_epu32(__m128i, __m128i);

53 |

Flags Affected

54 |

None

55 |

SIMD Floating-Point Exceptions

56 |

None

57 |

Other Exceptions

58 |

See Exceptions Type 4.

-------------------------------------------------------------------------------- /html/SHA256RNDS2.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | SHA256RNDS2—Perform Two Rounds of SHA256 Operation 8 | 9 |

SHA256RNDS2—Perform Two Rounds of SHA256 Operation

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
19 |

0F 38 CB /r

20 |

SHA256RNDS2 xmm1, xmm2/m128, <XMM0>

RM0V/VSHAPerform 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H) from xmm1, an initial SHA256 state (A,B,E,F) from xmm2/m128, and a pre-computed sum of the next 2 round mes-sage dwords and the corresponding round constants from the implicit operand XMM0, storing the updated SHA256 state (A,B,E,F) result in xmm1.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 |
Op/EnOperand 1Operand 2Operand 3
RMIModRM:reg (r, w)ModRM:r/m (r)Implicit XMM0 (r)
37 |

Description

38 |

The SHA256RNDS2 instruction performs 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H) from the first operand, an initial SHA256 state (A,B,E,F) from the second operand, and a pre-computed sum of the next 2 round message dwords and the corresponding round constants from the implicit operand xmm0. Note that only the two lower dwords of XMM0 are used by the instruction.

39 |

The updated SHA256 state (A,B,E,F) is written to the first operand, and the second operand can be used as the updated state (C,D,G,H) in later rounds.

40 |

Operation

41 |

SHA256RNDS2

42 |

A_0 (cid:197) SRC2[127:96];

43 |

B_0 (cid:197) SRC2[95:64];

44 |

C_0 (cid:197) SRC1[127:96];

45 |

D_0 (cid:197) SRC1[95:64];

46 |

E_0 (cid:197) SRC2[63:32];

47 |

F_0 (cid:197) SRC2[31:0];

48 |

G_0 (cid:197) SRC1[63:32];

49 |

H_0 (cid:197) SRC1[31:0];

50 |

WK0 (cid:197) XMM0[31: 0];

51 |

WK1 (cid:197) XMM0[63: 32];

52 |

FOR i = 0 to 1

53 |

A_(i +1) (cid:197) Ch (E_i, F_i, G_i) +Σ1( E_i) +WKi+ H_i + Maj(A_i , B_i, C_i) +Σ0( A_i);

54 |

B_(i +1) (cid:197) A_i;

55 |

C_(i +1) (cid:197) B_i ;

56 |

D_(i +1) (cid:197) C_i;

57 |

E_(i +1) (cid:197) Ch (E_i, F_i, G_i) +Σ1( E_i) +WKi+ H_i + D_i;

58 |

F_(i +1) (cid:197) E_i ;

59 |

G_(i +1) (cid:197) F_i;

60 |

H_(i +1) (cid:197) G_i;

61 |

ENDFOR

62 |

DEST[127:96] (cid:197) A_2;

63 |

DEST[95:64] (cid:197) B_2;

64 |

DEST[63:32] (cid:197) E_2;

65 |

DEST[31:0] (cid:197) F_2;

66 |

Intel C/C++ Compiler Intrinsic Equivalent

67 |

SHA256RNDS2: __m128i _mm_sha256rnds2_epu32(__m128i, __m128i, __m128i);

68 |

Flags Affected

69 |

None

70 |

SIMD Floating-Point Exceptions

71 |

None

72 |

Other Exceptions

73 |

See Exceptions Type 4.

-------------------------------------------------------------------------------- /html/STAC.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | STAC—Set AC Flag in EFLAGS Register 8 | 9 |

STAC—Set AC Flag in EFLAGS Register

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-bit ModeCompat/Leg ModeDescription
0F 01 CBSTACNPValidValidSet the AC flag in the EFLAGS register.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Sets the AC flag bit in EFLAGS register. This may enable alignment checking of user-mode data accesses. This allows explicit supervisor-mode data accesses to user-mode pages even if the SMAP bit is set in the CR4 register.

41 |

This instruction's operation is the same in non-64-bit modes and 64-bit mode. Attempts to execute STAC when CPL > 0 cause #UD.

42 |

Operation

43 | 
EFLAGS.AC ← 1;
44 |

Flags Affected

45 |

AC set. Other flags are unaffected.

46 |

Protected Mode Exceptions

47 | 48 | 49 | 50 |
#UD 51 |

If the LOCK prefix is used.

52 |

If the CPL > 0.

53 |

If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

54 |

Real-Address Mode Exceptions

55 | 56 | 57 | 58 |
#UD 59 |

If the LOCK prefix is used.

60 |

If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

61 |

Virtual-8086 Mode Exceptions

62 | 63 | 64 | 65 |
#UDThe STAC instruction is not recognized in virtual-8086 mode.
66 |

Compatibility Mode Exceptions

67 | 68 | 69 | 70 |
#UD 71 |

If the LOCK prefix is used.

72 |

If the CPL > 0.

73 |

If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

74 |

64-Bit Mode Exceptions

75 | 76 | 77 | 78 |
#UD 79 |

If the LOCK prefix is used.

80 |

If the CPL > 0.

81 |

If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

-------------------------------------------------------------------------------- /html/STC.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | STC—Set Carry Flag 8 | 9 |

STC—Set Carry Flag

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-Bit ModeCompat/Leg ModeDescription
F9STCNPValidValidSet CF flag.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Sets the CF flag in the EFLAGS register. Operation is the same in all modes.

41 |

Operation

42 | 
CF ← 1;
43 |

Flags Affected

44 |

The CF flag is set. The OF, ZF, SF, AF, and PF flags are unaffected.

45 |

Exceptions (All Operating Modes)

46 |

#UD

47 |

If the LOCK prefix is used.

-------------------------------------------------------------------------------- /html/STD.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | STD—Set Direction Flag 8 | 9 |

STD—Set Direction Flag

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-bit ModeCompat/Leg ModeDescription
FDSTDNPValidValidSet DF flag.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Sets the DF flag in the EFLAGS register. When the DF flag is set to 1, string operations decrement the index regis-ters (ESI and/or EDI). Operation is the same in all modes.

41 |

Operation

42 | 
DF ← 1;
43 |

Flags Affected

44 |

The DF flag is set. The CF, OF, ZF, SF, AF, and PF flags are unaffected.

45 |

Exceptions (All Operating Modes)

46 |

#UD

47 |

If the LOCK prefix is used.

-------------------------------------------------------------------------------- /html/STMXCSR.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | STMXCSR—Store MXCSR Register State 8 | 9 |

STMXCSR—Store MXCSR Register State

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 | 25 | 26 | 29 | 30 | 31 | 32 |
Opcode*/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
19 |

0F AE /3

20 |

STMXCSR m32

MV/VSSEStore contents of MXCSR register to m32.
27 |

VEX.LZ.0F.WIG AE /3

28 |

VSTMXCSR m32

MV/VAVXStore contents of MXCSR register to m32.
33 |

Instruction Operand Encoding

34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 |
Op/EnOperand 1Operand 2Operand 3Operand 4
MModRM:r/m (w)NANANA
47 |

Description

48 |

Stores the contents of the MXCSR control and status register to the destination operand. The destination operand is a 32-bit memory location. The reserved bits in the MXCSR register are stored as 0s.

49 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

50 |

VEX.L must be 0, otherwise instructions will #UD.

51 |

Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

52 |

Operation

53 | 
m32 ← MXCSR;
54 |

Intel C/C++ Compiler Intrinsic Equivalent

55 |

_mm_getcsr(void)

56 |

SIMD Floating-Point Exceptions

57 |

None.

58 |

Other Exceptions

59 |

See Exceptions Type 5; additionally

60 | 61 | 62 | 63 |
#UD 64 |

If VEX.L= 1,

65 |

If VEX.vvvv ≠ 1111B.

-------------------------------------------------------------------------------- /html/UD2.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | UD2—Undefined Instruction 8 | 9 |

UD2—Undefined Instruction

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
OpcodeInstructionOp/En64-Bit ModeCompat/Leg ModeDescription
0F 0BUD2NPValidValidRaise invalid opcode exception.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Generates an invalid opcode exception. This instruction is provided for software testing to explicitly generate an invalid opcode exception. The opcode for this instruction is reserved for this purpose.

41 |

Other than raising the invalid opcode exception, this instruction has no effect on processor state or memory.

42 |

Even though it is the execution of the UD2 instruction that causes the invalid opcode exception, the instruction pointer saved by delivery of the exception references the UD2 instruction (and not the following instruction).

43 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

44 |

Operation

45 | 
#UD (* Generates invalid opcode exception *);
46 |

Flags Affected

47 |

None.

48 |

Exceptions (All Operating Modes)

49 |

#UD

50 |

Raises an invalid opcode exception in all operating modes.

-------------------------------------------------------------------------------- /html/VPERM2F128.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | VPERM2F128 — Permute Floating-Point Values 8 | 9 |

VPERM2F128 — Permute Floating-Point Values

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
VEX.NDS.256.66.0F3A.W0 06 /r ib VPERM2F128 ymm1, ymm2, ymm3/m256, imm8RVMIV/VAVXPermute 128-bit floating-point fields in ymm2 and ymm3/mem using controls from imm8 and store result in ymm1.
23 |

Instruction Operand Encoding

24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RVMIModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)imm8
37 |

Description

38 |

Permute 128 bit floating-point-containing fields from the first source operand (second operand) and second source operand (third operand) using bits in the 8-bit immediate and store results in the destination operand (first operand). The first source operand is a YMM register, the second source operand is a YMM register or a 256-bit memory location, and the destination operand is a YMM register.

39 |

Y1

40 |

Y0

41 |

SRC2

42 |

X1

43 |

X0

44 |

SRC1

45 |

X0, X1, Y0, or Y1

46 |

DEST

47 |

X0, X1, Y0, or Y1

48 |

Figure 5-21. VPERM2F128 Operation

49 |

Imm8[1:0] select the source for the first destination 128-bit field, imm8[5:4] select the source for the second destination field. If imm8[3] is set, the low 128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed.

50 |

VEX.L must be 1, otherwise the instruction will #UD.

51 |

Operation

52 |

VPERM2F128

53 | 
CASE IMM8[1:0] of
54 | 0: DEST[127:0] (cid:197) SRC1[127:0]
55 | 1: DEST[127:0] (cid:197) SRC1[255:128]
56 | 2: DEST[127:0] (cid:197) SRC2[127:0]
57 | 3: DEST[127:0] (cid:197) SRC2[255:128]
58 | ESAC
59 | CASE IMM8[5:4] of
60 | 0: DEST[255:128] (cid:197) SRC1[127:0]
61 | 1: DEST[255:128] (cid:197) SRC1[255:128]
62 | 2: DEST[255:128] (cid:197) SRC2[127:0]
63 | 3: DEST[255:128] (cid:197) SRC2[255:128]
64 | ESAC
65 | IF (imm8[3])
66 | DEST[127:0] (cid:197) 0
67 | FI
68 | IF (imm8[7])
69 | DEST[VLMAX-1:128] (cid:197) 0
70 | FI
71 |

Intel C/C++ Compiler Intrinsic Equivalent

72 |

VPERM2F128:

73 |

__m256 _mm256_permute2f128_ps (__m256 a, __m256 b, int control)

74 |

VPERM2F128:

75 |

__m256d _mm256_permute2f128_pd (__m256d a, __m256d b, int control)

76 |

VPERM2F128:

77 |

__m256i _mm256_permute2f128_si256 (__m256i a, __m256i b, int control)

78 |

SIMD Floating-Point Exceptions

79 |

None.

80 |

Other Exceptions

81 |

See Exceptions Type 6; additionally

82 | 83 | 84 | 85 |
#UD 86 |

If VEX.L = 0

87 |

If VEX.W = 1.

-------------------------------------------------------------------------------- /html/VPERM2I128.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | VPERM2I128 — Permute Integer Values 8 | 9 |

VPERM2I128 — Permute Integer Values

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64/32 -bit ModeCPUID Feature FlagDescription
19 |

VEX.NDS.256.66.0F3A.W0 46 /r ib

20 |

VPERM2I128 ymm1, ymm2, ymm3/m256, imm8

RVMIV/VAVX2Permute 128-bit integer data in ymm2 and ymm3/mem using controls from imm8 and store result in ymm1.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
RVMIModRM:reg (w)VEX.vvvvModRM:r/m (r)Imm8
39 |

Description

40 |

Permute 128 bit integer data from the first source operand (second operand) and second source operand (third operand) using bits in the 8-bit immediate and store results in the destination operand (first operand). The first source operand is a YMM register, the second source operand is a YMM register or a 256-bit memory location, and the destination operand is a YMM register.

41 |

Y1

42 |

Y0

43 |

SRC2

44 |

X1

45 |

X0

46 |

SRC1

47 |

X0, X1, Y0, or Y1

48 |

DEST

49 |

X0, X1, Y0, or Y1

50 |

Figure 5-22. VPERM2I128 Operation

51 |

Imm8[1:0] select the source for the first destination 128-bit field, imm8[5:4] select the source for the second destination field. If imm8[3] is set, the low 128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed.

52 |

VEX.L must be 1, otherwise the instruction will #UD.

53 |

Operation

54 |

VPERM2I128

55 | 
CASE IMM8[1:0] of
56 | 0: DEST[127:0] (cid:197) SRC1[127:0]
57 | 1: DEST[127:0] (cid:197) SRC1[255:128]
58 | 2: DEST[127:0] (cid:197) SRC2[127:0]
59 | 3: DEST[127:0] (cid:197) SRC2[255:128]
60 | ESAC
61 | CASE IMM8[5:4] of
62 | 0: DEST[255:128] (cid:197) SRC1[127:0]
63 | 1: DEST[255:128] (cid:197) SRC1[255:128]
64 | 2: DEST[255:128] (cid:197) SRC2[127:0]
65 | 3: DEST[255:128] (cid:197) SRC2[255:128]
66 | ESAC
67 | IF (imm8[3])
68 | DEST[127:0] (cid:197) 0
69 | FI
70 | IF (imm8[7])
71 | DEST[255:128] (cid:197) 0
72 | FI
73 |

Intel C/C++ Compiler Intrinsic Equivalent

74 |

VPERM2I128: __m256i _mm256_permute2x128_si256 (__m256i a, __m256i b, int control)

75 |

SIMD Floating-Point Exceptions

76 |

None

77 |

Other Exceptions

78 |

See Exceptions Type 6; additionally

79 | 80 | 81 | 82 |
#UD 83 |

If VEX.L = 0,

84 |

If VEX.W = 1.

-------------------------------------------------------------------------------- /html/VZEROALL.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | VZEROALL—Zero All YMM Registers 8 | 9 |

VZEROALL—Zero All YMM Registers

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
19 |

VEX.256.0F.WIG 77

20 |

VZEROALL

NPV/VAVXZero all YMM registers.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

The instruction zeros contents of all XMM or YMM registers.

41 |

Note: VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD. In Compatibility and legacy 32-bit mode only the lower 8 registers are modified.

42 |

Operation

43 |

VZEROALL (VEX.256 encoded version)

44 | 
IF (64-bit mode)
45 |     YMM0[VLMAX-1:0] (cid:197) 0
46 |     YMM1[VLMAX-1:0] (cid:197) 0
47 |     YMM2[VLMAX-1:0] (cid:197) 0
48 |     YMM3[VLMAX-1:0] (cid:197) 0
49 |     YMM4[VLMAX-1:0] (cid:197) 0
50 |     YMM5[VLMAX-1:0] (cid:197) 0
51 |     YMM6[VLMAX-1:0] (cid:197) 0
52 |     YMM7[VLMAX-1:0] (cid:197) 0
53 |     YMM8[VLMAX-1:0] (cid:197) 0
54 |     YMM9[VLMAX-1:0] (cid:197) 0
55 |     YMM10[VLMAX-1:0] (cid:197) 0
56 |     YMM11[VLMAX-1:0] (cid:197) 0
57 |     YMM12[VLMAX-1:0] (cid:197) 0
58 |     YMM13[VLMAX-1:0] (cid:197) 0
59 |     YMM14[VLMAX-1:0] (cid:197) 0
60 |     YMM15[VLMAX-1:0] (cid:197) 0
61 | ELSE
62 |     YMM0[VLMAX-1:0] (cid:197) 0
63 |     YMM1[VLMAX-1:0] (cid:197) 0
64 |     YMM2[VLMAX-1:0] (cid:197) 0
65 |     YMM3[VLMAX-1:0] (cid:197) 0
66 |     YMM4[VLMAX-1:0] (cid:197) 0
67 |     YMM5[VLMAX-1:0] (cid:197) 0
68 |     YMM6[VLMAX-1:0] (cid:197) 0
69 |     YMM7[VLMAX-1:0] (cid:197) 0
70 |     YMM8-15: Unmodified
71 | FI
72 |

Intel C/C++ Compiler Intrinsic Equivalent

73 |

VZEROALL:

74 |

_mm256_zeroall()

75 |

SIMD Floating-Point Exceptions

76 |

None.

77 |

Other Exceptions

78 |

See Exceptions Type 8.

-------------------------------------------------------------------------------- /html/VZEROUPPER.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | VZEROUPPER—Zero Upper Bits of YMM Registers 8 | 9 |

VZEROUPPER—Zero Upper Bits of YMM Registers

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescription
19 |

VEX.128.0F.WIG 77

20 |

VZEROUPPER

NPV/VAVXZero upper 128 bits of all YMM registers.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

The instruction zeros the bits in position 128 and higher of all YMM registers. The lower 128-bits of the registers (the corresponding XMM registers) are unmodified.

41 |

This instruction is recommended when transitioning between AVX and legacy SSE code - it will eliminate perfor-mance penalties caused by false dependencies.

42 |

Note: VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. In Compatibility and legacy 32-bit mode only the lower 8 registers are modified.

43 |

Operation

44 |

VZEROUPPER

45 | 
IF (64-bit mode)
46 |     YMM0[VLMAX-1:128] (cid:197) 0
47 |     YMM1[VLMAX-1:128] (cid:197) 0
48 |     YMM2[VLMAX-1:128] (cid:197) 0
49 |     YMM3[VLMAX-1:128] (cid:197) 0
50 |     YMM4[VLMAX-1:128] (cid:197) 0
51 |     YMM5[VLMAX-1:128] (cid:197) 0
52 |     YMM6[VLMAX-1:128] (cid:197) 0
53 |     YMM7[VLMAX-1:128] (cid:197) 0
54 |     YMM8[VLMAX-1:128] (cid:197) 0
55 |     YMM9[VLMAX-1:128] (cid:197) 0
56 |     YMM10[VLMAX-1:128] (cid:197) 0
57 |     YMM11[VLMAX-1:128] (cid:197) 0
58 |     YMM12[VLMAX-1:128] (cid:197) 0
59 |     YMM13[VLMAX-1:128] (cid:197) 0
60 |     YMM14[VLMAX-1:128] (cid:197) 0
61 |     YMM15[VLMAX-1:128] (cid:197) 0
62 | ELSE
63 |     YMM0[VLMAX-1:128] (cid:197) 0
64 |     YMM1[VLMAX-1:128] (cid:197) 0
65 |     YMM2[VLMAX-1:128] (cid:197) 0
66 |     YMM3[VLMAX-1:128] (cid:197) 0
67 |     YMM4[VLMAX-1:128] (cid:197) 0
68 |     YMM5[VLMAX-1:128] (cid:197) 0
69 |     YMM6[VLMAX-1:128] (cid:197) 0
70 |     YMM7[VLMAX-1:128] (cid:197) 0
71 |     YMM8-15: unmodified
72 | FI
73 |

Intel C/C++ Compiler Intrinsic Equivalent

74 |

VZEROUPPER:

75 |

_mm256_zeroupper()

76 |

SIMD Floating-Point Exceptions

77 |

None.

78 |

Other Exceptions

79 |

See Exceptions Type 8.

-------------------------------------------------------------------------------- /html/WAIT_FWAIT.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | WAIT/FWAIT—Wait 8 | 9 |

WAIT/FWAIT—Wait

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 |
OpcodeInstructionOp/En64-Bit ModeCompat/Leg ModeDescription
9BWAITNPValidValidCheck pending unmasked floating-point exceptions.
9BFWAITNPValidValidCheck pending unmasked floating-point exceptions.
32 |

Instruction Operand Encoding

33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
46 |

Description

47 |

Causes the processor to check for and handle pending, unmasked, floating-point exceptions before proceeding. (FWAIT is an alternate mnemonic for WAIT.)

48 |

This instruction is useful for synchronizing exceptions in critical sections of code. Coding a WAIT instruction after a floating-point instruction ensures that any unmasked floating-point exceptions the instruction may raise are handled before the processor can modify the instruction’s results. See the section titled “Floating-Point Exception Synchronization” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more information on using the WAIT/FWAIT instruction.

49 |

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

50 |

Operation

51 | 
CheckForPendingUnmaskedFloatingPointExceptions;
52 |

FPU Flags Affected

53 |

The C0, C1, C2, and C3 flags are undefined.

54 |

Floating-Point Exceptions

55 |

None.

56 |

Protected Mode Exceptions

57 | 58 | 59 | 60 | 61 | 62 | 63 |
#NMIf CR0.MP[bit 1] = 1 and CR0.TS[bit 3] = 1.
#UDIf the LOCK prefix is used.
64 |

Real-Address Mode Exceptions

65 |

Same exceptions as in protected mode.

66 |

Virtual-8086 Mode Exceptions

67 |

Same exceptions as in protected mode.

68 |

Compatibility Mode Exceptions

69 |

Same exceptions as in protected mode.

70 |

64-Bit Mode Exceptions

71 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/WRPKRU.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | WRPKRU—Write Data to User Page Key Register 8 | 9 |

WRPKRU—Write Data to User Page Key Register

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
Opcode*InstructionOp/En64/32bit Mode SupportCPUID Feature FlagDescription
0F 01 EFWRPKRUNPV/VOSPKEWrites EAX into PKRU.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand 2Operand 3Operand 4
NPNANANANA
39 |

Description

40 |

Writes the value of EAX into PKRU. ECX and EDX must be 0 when WRPKRU is executed; otherwise, a general-protection exception (#GP) occurs.

41 |

WRPKRU can be executed only if CR4.PKE = 1; otherwise, an invalid-opcode exception (#UD) occurs. Software can discover the value of CR4.PKE by examining CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4].

42 |

On processors that support the Intel 64 Architecture, the high-order 32-bits of RCX, RDX and RAX are ignored.

43 |

Operation

44 | 
IF (ECX = 0 AND EDX = 0)
45 |     THEN PKRU ← EAX;
46 |     ELSE #GP(0);
47 | FI;
48 |

Flags Affected

49 |

None.

50 |

C/C++ Compiler Intrinsic Equivalent

51 |

WRPKRU:

52 |

void _wrpkru(uint32_t);

53 |

Protected Mode Exceptions

54 | 55 | 56 | 57 | 60 | 61 | 62 |
#GP(0) 58 |

If ECX ≠ 0.

59 |

If EDX ≠ 0.

#UD 63 |

If the LOCK prefix is used.

64 |

If CR4.PKE = 0.

65 |

Real-Address Mode Exceptions

66 |

Same exceptions as in protected mode.

67 |

Virtual-8086 Mode Exceptions

68 |

Same exceptions as in protected mode.

69 |

Compatibility Mode Exceptions

70 |

Same exceptions as in protected mode.

71 |

64-Bit Mode Exceptions

72 |

Same exceptions as in protected mode.

-------------------------------------------------------------------------------- /html/XABORT.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | XABORT — Transactional Abort 8 | 9 |

XABORT — Transactional Abort

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64/32bit Mode SupportCPUID Feature FlagDescription
19 |

C6 F8 ib

20 |

XABORT imm8

AV/VRTMCauses an RTM abort if in RTM execution
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand2Operand3Operand4
Aimm8NANANA
39 |

Description

40 |

XABORT forces an RTM abort. Following an RTM abort, the logical processor resumes execution at the fallback address computed through the outermost XBEGIN instruction. The EAX register is updated to reflect an XABORT instruction caused the abort, and the imm8 argument will be provided in bits 31:24 of EAX.

41 |

Operation

42 |

XABORT

43 | 
IF RTM_ACTIVE = 0
44 |     THEN
45 |          Treat as NOP;
46 |     ELSE
47 |          GOTO RTM_ABORT_PROCESSING;
48 | FI;
49 | (* For any RTM abort condition encountered during RTM execution *)
50 | RTM_ABORT_PROCESSING:
51 |     Restore architectural register state;
52 |     Discard memory updates performed in transaction;
53 |     Update EAX with status and XABORT argument;
54 |     RTM_NEST_COUNT ← 0;
55 |     RTM_ACTIVE ← 0;
56 |     IF 64-bit Mode
57 |          THEN
58 |               RIP ← fallbackRIP;
59 |          ELSE
60 |               EIP ← fallbackEIP;
61 |     FI;
62 | END
63 |

Flags Affected

64 |

None

65 |

Intel C/C++ Compiler Intrinsic Equivalent

66 |

XABORT:

67 |

void _xabort( unsigned int);

68 |

SIMD Floating-Point Exceptions

69 |

None

70 |

Other Exceptions

71 | 72 | 73 | 74 |
#UD 75 |

CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.

76 |

If LOCK prefix is used.

-------------------------------------------------------------------------------- /html/XEND.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | XEND — Transactional End 8 | 9 |

XEND — Transactional End

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64/32bit Mode SupportCPUID Feature FlagDescription
19 |

0F 01 D5

20 |

XEND

AV/VRTMSpecifies the end of an RTM code region.
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand2Operand3Operand4
ANANANANA
39 |

Description

40 |

The instruction marks the end of an RTM code region. If this corresponds to the outermost scope (that is, including this XEND instruction, the number of XBEGIN instructions is the same as number of XEND instructions), the logical processor will attempt to commit the logical processor state atomically. If the commit fails, the logical processor will rollback all architectural register and memory updates performed during the RTM execution. The logical processor will resume execution at the fallback address computed from the outermost XBEGIN instruction. The EAX register is updated to reflect RTM abort information.

41 |

XEND executed outside a transactional region will cause a #GP (General Protection Fault).

42 |

Operation

43 |

XEND

44 | 
IF (RTM_ACTIVE = 0) THEN
45 |     SIGNAL #GP
46 | ELSE
47 |     RTM_NEST_COUNT--
48 |     IF (RTM_NEST_COUNT = 0) THEN
49 |          Try to commit transaction
50 |          IF fail to commit transactional execution
51 |               THEN
52 |                     GOTO RTM_ABORT_PROCESSING;
53 |               ELSE (* commit success *)
54 |                     RTM_ACTIVE ← 0
55 |          FI;
56 |     FI;
57 | FI;
58 | (* For any RTM abort condition encountered during RTM execution *)
59 | RTM_ABORT_PROCESSING:
60 |     Restore architectural register state
61 |     Discard memory updates performed in transaction
62 |     Update EAX with status
63 |     RTM_NEST_COUNT ← 0
64 |     RTM_ACTIVE ← 0
65 |     IF 64-bit Mode
66 |          THEN
67 |               RIP ← fallbackRIP
68 |          ELSE
69 |               EIP ← fallbackEIP
70 |     FI;
71 | END
72 |

Flags Affected

73 |

None

74 |

Intel C/C++ Compiler Intrinsic Equivalent

75 |

XEND:

76 |

void _xend( void );

77 |

SIMD Floating-Point Exceptions

78 |

None

79 |

Other Exceptions

80 | 81 | 82 | 83 | 86 | 87 | 88 |
#UD 84 |

CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.

85 |

If LOCK or 66H or F2H or F3H prefix is used.

#GP(0)If RTM_ACTIVE = 0.
-------------------------------------------------------------------------------- /html/XTEST.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | XTEST — Test If In Transactional Execution 8 | 9 |

XTEST — Test If In Transactional Execution

10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 21 | 22 | 23 | 24 |
Opcode/InstructionOp/En64/32bit Mode SupportCPUID Feature FlagDescription
19 |

0F 01 D6

20 |

XTEST

AV/VHLE or RTMTest if executing in a transactional region
25 |

Instruction Operand Encoding

26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 |
Op/EnOperand 1Operand2Operand3Operand4
ANANANANA
39 |

Description

40 |

The XTEST instruction queries the transactional execution status. If the instruction executes inside a transaction-ally executing RTM region or a transactionally executing HLE region, then the ZF flag is cleared, else it is set.

41 |

Operation

42 |

XTEST

43 | 
IF (RTM_ACTIVE = 1 OR HLE_ACTIVE = 1)
44 |     THEN
45 |          ZF ← 0
46 |     ELSE
47 |          ZF ← 1
48 | FI;
49 |

Flags Affected

50 |

The ZF flag is cleared if the instruction is executed transactionally; otherwise it is set to 1. The CF, OF, SF, PF, and AF, flags are cleared.

51 |

Intel C/C++ Compiler Intrinsic Equivalent

52 |

XTEST:

53 |

int _xtest( void );

54 |

SIMD Floating-Point Exceptions

55 |

None

56 |

Other Exceptions

57 | 58 | 59 | 60 |
#UD 61 |

CPUID.(EAX=7, ECX=0):HLE[bit 4] = 0 and CPUID.(EAX=7, ECX=0):RTM[bit 11] = 0.

62 |

If LOCK or 66H or F2H or F3H prefix is used.

-------------------------------------------------------------------------------- /html/style.css: -------------------------------------------------------------------------------- 1 | table { border-collapse: collapse } 2 | th, td { padding: 0px 10px; border: 1px #ddd solid; vertical-align: top } 3 | svg { display: block; margin: 0px auto } 4 | svg + h3 { text-align: center; } 5 | 6 | table.opcodes { font: 10pt "Courier New", monospace; } 7 | 8 | .notes { font-size: 9pt; } 9 | -------------------------------------------------------------------------------- /parsejson.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | # -*- coding: UTF-8 -*- 3 | 4 | import sys 5 | try: 6 | import ujson as json 7 | except ImportError: 8 | import json 9 | from htmltext import * 10 | 11 | def main(argv): 12 | for arg in argv[1:]: 13 | with open(arg, "rb") as f: 14 | 15 | opcodes = json.loads(f.read()) 16 | 17 | title = u"x86" 18 | result = [""] 19 | text = HtmlText() 20 | text.append(OpenTag("html")) 21 | text.append(OpenTag("head")) 22 | text.append(OpenTag("meta", attributes={"charset": "UTF-8"}, self_closes=True)) 23 | text.append(OpenTag("link", attributes={"rel": "stylesheet", "type": "text/css", "href": "style.css"}, self_closes=True)) 24 | text.append(OpenTag("title")) 25 | text.append(title) 26 | text.append(CloseTag("title")) 27 | text.append(CloseTag("head")) 28 | text.append(OpenTag("body")) 29 | 30 | text.append(OpenTag("table", attributes={"class": "opcodes"})) 31 | 32 | columns = ["Opcode", "Instruction", "Description"] 33 | 34 | text.append(OpenTag("tr")) 35 | for column in columns: 36 | text.append(OpenTag("th")) 37 | text.append(column) 38 | text.append(CloseTag("th")) 39 | text.append(CloseTag("tr")) 40 | 41 | for opcode in opcodes: 42 | text.append(OpenTag("tr")) 43 | for column in columns: 44 | value = opcode[column] 45 | text.append(OpenTag("td")) 46 | text.append(value) 47 | text.append(CloseTag("td")) 48 | text.append(CloseTag("tr")) 49 | 50 | text.append(CloseTag("table")) 51 | 52 | with open("html/_opcodes.html", "wb") as g: 53 | g.write("\n" + text.to_html().encode('ascii', 'xmlcharrefreplace')) 54 | 55 | 56 | if __name__ == "__main__": 57 | result = main(sys.argv) 58 | sys.exit(result) 59 | --------------------------------------------------------------------------------