├── .gitignore ├── .gitmodules └── README.md /.gitignore: -------------------------------------------------------------------------------- 1 | archive 2 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "chipyard"] 2 | path = RISCV/chipyard 3 | url = https://github.com/ucb-bar/chipyard.git 4 | [submodule "CircuitNet"] 5 | path = MISC/CircuitNet 6 | url = https://github.com/circuitnet/CircuitNet.git 7 | [submodule "MNISQ-quantum-circuit-dataset"] 8 | path = MISC/MNISQ-quantum-circuit-dataset 9 | url = https://github.com/FujiiLabCollaboration/MNISQ-quantum-circuit-dataset.git 10 | [submodule "GNN-RE"] 11 | path = MISC/GNN-RE 12 | url = https://github.com/DfX-NYUAD/GNN-RE.git 13 | [submodule "accelerators/ML4Accel-Dataset"] 14 | path = accelerators/ML4Accel-Dataset 15 | url = https://github.com/UT-LCA/ML4Accel-Dataset.git 16 | [submodule "accelerators/Lenet_arch"] 17 | path = accelerators/Lenet_arch 18 | url = https://github.com/vishpbharadwaj/Lenet_arch.git 19 | [submodule "accelerators/SGen"] 20 | path = accelerators/SGen 21 | url = https://github.com/fserre/SGen.git 22 | [submodule "Components/verilog-ethernet"] 23 | path = Components/verilog-ethernet 24 | url = https://github.com/alexforencich/verilog-ethernet.git 25 | [submodule "Components/verilog"] 26 | path = Components/verilog 27 | url = https://github.com/seldridge/verilog.git 28 | [submodule "Components/verilog-axi"] 29 | path = Components/verilog-axi 30 | url = https://github.com/alexforencich/verilog-axi.git 31 | [submodule "Components/verilog-pcie"] 32 | path = Components/verilog-pcie 33 | url = https://github.com/alexforencich/verilog-pcie.git 34 | [submodule "SoCs/VerilogBoy"] 35 | path = SoCs/VerilogBoy 36 | url = https://github.com/zephray/VerilogBoy.git 37 | [submodule "Components/verilog-uart"] 38 | path = Components/verilog-uart 39 | url = https://github.com/alexforencich/verilog-uart.git 40 | [submodule "FPGA/open-fpga-verilog-tutorial"] 41 | path = FPGA/open-fpga-verilog-tutorial 42 | url = https://github.com/Obijuan/open-fpga-verilog-tutorial.git 43 | [submodule "SoCs/mips-cpu"] 44 | path = SoCs/mips-cpu 45 | url = https://github.com/jmahler/mips-cpu.git 46 | [submodule "Components/cores"] 47 | path = Components/cores 48 | url = https://github.com/ultraembedded/cores.git 49 | [submodule "Components/verilog-i2c"] 50 | path = Components/verilog-i2c 51 | url = https://github.com/alexforencich/verilog-i2c.git 52 | [submodule "Components/oh"] 53 | path = Components/oh 54 | url = https://github.com/aolofsson/oh.git 55 | [submodule "Components/sdram-controller"] 56 | path = Components/sdram-controller 57 | url = https://github.com/stffrdhrn/sdram-controller.git 58 | [submodule "SoCs/e203_hbirdv2"] 59 | path = RISCV/e203_hbirdv2 60 | url = https://github.com/riscv-mcu/e203_hbirdv2.git 61 | [submodule "SoCs/darkriscv"] 62 | path = RISCV/darkriscv 63 | url = https://github.com/darklife/darkriscv.git 64 | [submodule "SoCs/serv"] 65 | path = SoCs/serv 66 | url = https://github.com/olofk/serv.git 67 | [submodule "SoCs/zipcpu"] 68 | path = SoCs/zipcpu 69 | url = https://github.com/ZipCPU/zipcpu.git 70 | [submodule "SoCs/amiga2000-gfxcard"] 71 | path = SoCs/amiga2000-gfxcard 72 | url = https://github.com/mntmn/amiga2000-gfxcard.git 73 | [submodule "SoCs/biriscv"] 74 | path = RISCV/biriscv 75 | url = https://github.com/ultraembedded/biriscv.git 76 | [submodule "FPGA/USB_C_Industrial_Camera_FPGA_USB3"] 77 | path = FPGA/USB_C_Industrial_Camera_FPGA_USB3 78 | url = https://github.com/circuitvalley/USB_C_Industrial_Camera_FPGA_USB3.git 79 | [submodule "SoCs/step_into_mips"] 80 | path = SoCs/step_into_mips 81 | url = https://github.com/lvyufeng/step_into_mips.git 82 | [submodule "Components/openwifi-hw"] 83 | path = Components/openwifi-hw 84 | url = https://github.com/open-sdr/openwifi-hw.git 85 | [submodule "Components/openofdm"] 86 | path = Components/openofdm 87 | url = https://github.com/jhshi/openofdm.git 88 | [submodule "SoCs/mor1kx"] 89 | path = SoCs/mor1kx 90 | url = https://github.com/openrisc/mor1kx.git 91 | [submodule "Components/fpu"] 92 | path = Components/fpu 93 | url = https://github.com/dawsonjon/fpu.git 94 | [submodule "FPGA/CNN-FPGA"] 95 | path = FPGA/CNN-FPGA 96 | url = https://github.com/QShen3/CNN-FPGA.git 97 | [submodule "Components/32-Verilog-Mini-Projects"] 98 | path = Components/32-Verilog-Mini-Projects 99 | url = https://github.com/sudhamshu091/32-Verilog-Mini-Projects.git 100 | [submodule "FPGA/FPGA-USB-Device"] 101 | path = FPGA/FPGA-USB-Device 102 | url = https://github.com/WangXuan95/FPGA-USB-Device.git 103 | [submodule "FPGA/convolution_network_on_FPGA"] 104 | path = FPGA/convolution_network_on_FPGA 105 | url = https://github.com/hunterlew/convolution_network_on_FPGA.git 106 | [submodule "FPGA/FPGA-FOC"] 107 | path = FPGA/FPGA-FOC 108 | url = https://github.com/WangXuan95/FPGA-FOC.git 109 | [submodule "accelerators/AccDNN"] 110 | path = accelerators/AccDNN 111 | url = https://github.com/IBM/AccDNN.git 112 | [submodule "FPGA/tillitis-key1"] 113 | path = FPGA/tillitis-key1 114 | url = https://github.com/tillitis/tillitis-key1.git 115 | [submodule "Components/aes"] 116 | path = Components/aes 117 | url = https://github.com/secworks/aes.git 118 | [submodule "SoCs/ridecore"] 119 | path = SoCs/ridecore 120 | url = https://github.com/ridecore/ridecore.git 121 | [submodule "FPGA/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA"] 122 | path = FPGA/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA 123 | url = https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA.git 124 | [submodule "SoCs/Nuked-MD-FPGA"] 125 | path = SoCs/Nuked-MD-FPGA 126 | url = https://github.com/nukeykt/Nuked-MD-FPGA.git 127 | [submodule "Components/core_ddr3_controller"] 128 | path = Components/core_ddr3_controller 129 | url = https://github.com/ultraembedded/core_ddr3_controller.git 130 | [submodule "accelerators/CNN-FPGA"] 131 | path = accelerators/CNN-FPGA 132 | url = https://github.com/omarelhedaby/CNN-FPGA.git 133 | [submodule "Components/wbuart32"] 134 | path = Components/wbuart32 135 | url = https://github.com/ZipCPU/wbuart32.git 136 | [submodule "accelerators/ZYNQ-NVDLA"] 137 | path = accelerators/ZYNQ-NVDLA 138 | url = https://github.com/LeiWang1999/ZYNQ-NVDLA.git 139 | [submodule "Components/DisplayPort_Verilog"] 140 | path = Components/DisplayPort_Verilog 141 | url = https://github.com/hamsternz/DisplayPort_Verilog.git 142 | [submodule "FPGA/ice40_ultraplus_examples"] 143 | path = FPGA/ice40_ultraplus_examples 144 | url = https://github.com/damdoy/ice40_ultraplus_examples.git 145 | [submodule "Components/FPGA-ftdi245fifo"] 146 | path = Components/FPGA-ftdi245fifo 147 | url = https://github.com/WangXuan95/FPGA-ftdi245fifo.git 148 | [submodule "Components/usbcorev"] 149 | path = Components/usbcorev 150 | url = https://github.com/avakar/usbcorev.git 151 | [submodule "SoCs/fpga-chip8"] 152 | path = SoCs/fpga-chip8 153 | url = https://github.com/pwmarcz/fpga-chip8.git 154 | [submodule "SoCs/fpg1"] 155 | path = SoCs/fpg1 156 | url = https://github.com/hrvach/fpg1.git 157 | [submodule "FPGA/fpganes"] 158 | path = FPGA/fpganes 159 | url = https://github.com/strigeus/fpganes.git 160 | [submodule "Components/async_fifo"] 161 | path = Components/async_fifo 162 | url = https://github.com/dpretet/async_fifo.git 163 | [submodule "Components/core_jpeg"] 164 | path = Components/core_jpeg 165 | url = https://github.com/ultraembedded/core_jpeg.git 166 | [submodule "SoCs/fedar-f1-rv64im"] 167 | path = SoCs/fedar-f1-rv64im 168 | url = https://github.com/eminfedar/fedar-f1-rv64im.git 169 | [submodule "FPGA/FPGA-SDcard-Reader"] 170 | path = FPGA/FPGA-SDcard-Reader 171 | url = https://github.com/WangXuan95/FPGA-SDcard-Reader.git 172 | [submodule "FPGA/FPGA-peripherals"] 173 | path = FPGA/FPGA-peripherals 174 | url = https://github.com/FPGAwars/FPGA-peripherals.git 175 | [submodule "FPGA/FPGA_Based_CNN"] 176 | path = FPGA/FPGA_Based_CNN 177 | url = https://github.com/mtmd/FPGA_Based_CNN.git 178 | [submodule "SoCs/RISC-V-CPU"] 179 | path = RISCV/RISC-V-CPU 180 | url = https://github.com/Evensgn/RISC-V-CPU.git 181 | [submodule "FPGA/fomu-workshop"] 182 | path = FPGA/fomu-workshop 183 | url = https://github.com/im-tomu/fomu-workshop.git 184 | [submodule "FPGA/FPGA-JPEG-LS-encoder"] 185 | path = FPGA/FPGA-JPEG-LS-encoder 186 | url = https://github.com/WangXuan95/FPGA-JPEG-LS-encoder.git 187 | [submodule "SoCs/vm80a"] 188 | path = SoCs/vm80a 189 | url = https://github.com/1801BM1/vm80a.git 190 | [submodule "SoCs/icestation-32"] 191 | path = SoCs/icestation-32 192 | url = https://github.com/dan-rodrigues/icestation-32.git 193 | [submodule "Components/FPGA-CAN"] 194 | path = Components/FPGA-CAN 195 | url = https://github.com/WangXuan95/FPGA-CAN.git 196 | [submodule "accelerators/Hardware-CNN"] 197 | path = accelerators/Hardware-CNN 198 | url = https://github.com/alan4186/Hardware-CNN.git 199 | [submodule "FPGA/fft-dit-fpga"] 200 | path = FPGA/fft-dit-fpga 201 | url = https://github.com/benreynwar/fft-dit-fpga.git 202 | [submodule "FPGA/iob-cache"] 203 | path = FPGA/iob-cache 204 | url = https://github.com/IObundle/iob-cache.git 205 | [submodule "accelerators/Convolutional-Neural-Network"] 206 | path = accelerators/Convolutional-Neural-Network 207 | url = https://github.com/AniketBadhan/Convolutional-Neural-Network.git 208 | [submodule "accelerators/MobileNet-in-FPGA"] 209 | path = accelerators/MobileNet-in-FPGA 210 | url = https://github.com/ZFTurbo/MobileNet-in-FPGA.git 211 | [submodule "SoCs/R8051"] 212 | path = SoCs/R8051 213 | url = https://github.com/risclite/R8051.git 214 | [submodule "FPGA/usb_cdc"] 215 | path = FPGA/usb_cdc 216 | url = https://github.com/ulixxe/usb_cdc.git 217 | [submodule "accelerators/cnn_hardware_acclerator_for_fpga"] 218 | path = accelerators/cnn_hardware_acclerator_for_fpga 219 | url = https://github.com/sumanth-kalluri/cnn_hardware_acclerator_for_fpga.git 220 | [submodule "accelerators/MIPS-pipeline-processor"] 221 | path = accelerators/MIPS-pipeline-processor 222 | url = https://github.com/mhyousefi/MIPS-pipeline-processor.git 223 | [submodule "SoCs/riskow"] 224 | path = RISCV/riskow 225 | url = https://github.com/racerxdl/riskow.git 226 | [submodule "Components/spi-slave"] 227 | path = Components/spi-slave 228 | url = https://github.com/nandland/spi-slave.git 229 | [submodule "SoCs/apple-one"] 230 | path = SoCs/apple-one 231 | url = https://github.com/alangarf/apple-one.git 232 | [submodule "FPGA/dspfilters"] 233 | path = FPGA/dspfilters 234 | url = https://github.com/ZipCPU/dspfilters.git 235 | [submodule "Components/jt12"] 236 | path = Components/jt12 237 | url = https://github.com/jotego/jt12.git 238 | [submodule "Components/NaiveMIPS-HDL"] 239 | path = Components/NaiveMIPS-HDL 240 | url = https://github.com/z4yx/NaiveMIPS-HDL.git 241 | [submodule "SoCs/agc_simulation"] 242 | path = SoCs/agc_simulation 243 | url = https://github.com/virtualagc/agc_simulation.git 244 | [submodule "MISC/Haasoscope"] 245 | path = MISC/Haasoscope 246 | url = https://github.com/drandyhaas/Haasoscope.git 247 | [submodule "Components/uart"] 248 | path = Components/uart 249 | url = https://github.com/jamieiles/uart.git 250 | [submodule "Components/NeoGeoHDMI"] 251 | path = Components/NeoGeoHDMI 252 | url = https://github.com/charcole/NeoGeoHDMI.git 253 | [submodule "Components/verilog_fixed_point_math_library"] 254 | path = Components/verilog_fixed_point_math_library 255 | url = https://github.com/freecores/verilog_fixed_point_math_library.git 256 | [submodule "Components/sdspi"] 257 | path = Components/sdspi 258 | url = https://github.com/ZipCPU/sdspi.git 259 | [submodule "SoCs/MIPS-Processor"] 260 | path = SoCs/MIPS-Processor 261 | url = https://github.com/neelkshah/MIPS-Processor.git 262 | [submodule "Components/FPGA-DDR-SDRAM"] 263 | path = Components/FPGA-DDR-SDRAM 264 | url = https://github.com/WangXuan95/FPGA-DDR-SDRAM.git 265 | [submodule "SoCs/PASC"] 266 | path = SoCs/PASC 267 | url = https://github.com/jbush001/PASC.git 268 | [submodule "Components/FPGA-FixedPoint"] 269 | path = Components/FPGA-FixedPoint 270 | url = https://github.com/WangXuan95/FPGA-FixedPoint.git 271 | [submodule "Components/FPU"] 272 | path = Components/FPU 273 | url = https://github.com/danshanley/FPU.git 274 | [submodule "Components/i3c-slave-design"] 275 | path = Components/i3c-slave-design 276 | url = https://github.com/NXP/i3c-slave-design.git 277 | [submodule "SoCs/Basic-SIMD-Processor-Verilog-Tutorial"] 278 | path = SoCs/Basic-SIMD-Processor-Verilog-Tutorial 279 | url = https://github.com/zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial.git 280 | [submodule "SoCs/mc6809"] 281 | path = SoCs/mc6809 282 | url = https://github.com/cavnex/mc6809.git 283 | [submodule "Components/xcrypto"] 284 | path = Components/xcrypto 285 | url = https://github.com/scarv/xcrypto.git 286 | [submodule "Components/verilog-cam"] 287 | path = Components/verilog-cam 288 | url = https://github.com/alexforencich/verilog-cam.git 289 | [submodule "FPGA/FPGA-NFC"] 290 | path = FPGA/FPGA-NFC 291 | url = https://github.com/WangXuan95/FPGA-NFC.git 292 | [submodule "Components/dpll"] 293 | path = Components/dpll 294 | url = https://github.com/ZipCPU/dpll.git 295 | [submodule "FPGA/CNN_for_SLR"] 296 | path = FPGA/CNN_for_SLR 297 | url = https://github.com/ilaydayaman/CNN_for_SLR.git 298 | [submodule "FPGA/Image-Classification-using-CNN-on-FPGA"] 299 | path = FPGA/Image-Classification-using-CNN-on-FPGA 300 | url = https://github.com/padhi499/Image-Classification-using-CNN-on-FPGA.git 301 | [submodule "FPGA/FPGA-SDfake"] 302 | path = FPGA/FPGA-SDfake 303 | url = https://github.com/WangXuan95/FPGA-SDfake.git 304 | [submodule "FPGA/ARM_AMBA_Design"] 305 | path = FPGA/ARM_AMBA_Design 306 | url = https://github.com/lucky-wfw/ARM_AMBA_Design.git 307 | [submodule "FPGA/Systolic-array-implementation-in-RTL-for-TPU"] 308 | path = FPGA/Systolic-array-implementation-in-RTL-for-TPU 309 | url = https://github.com/abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU.git 310 | [submodule "FPGA/FPGA-MPEG2-encoder"] 311 | path = FPGA/FPGA-MPEG2-encoder 312 | url = https://github.com/WangXuan95/FPGA-MPEG2-encoder.git 313 | [submodule "SoCs/ARM7"] 314 | path = SoCs/ARM7 315 | url = https://github.com/chsasank/ARM7.git 316 | [submodule "Components/verilog-math"] 317 | path = Components/verilog-math 318 | url = https://github.com/dawsonjon/verilog-math.git 319 | [submodule "Components/DSP-RTL-Lib"] 320 | path = Components/DSP-RTL-Lib 321 | url = https://github.com/ahmedshahein/DSP-RTL-Lib.git 322 | [submodule "Components/H264"] 323 | path = Components/H264 324 | url = https://github.com/aiminickwong/H264.git 325 | [submodule "FPGA/FPGA-PNG-decoder"] 326 | path = FPGA/FPGA-PNG-decoder 327 | url = https://github.com/WangXuan95/FPGA-PNG-decoder.git 328 | [submodule "FPGA/wbscope"] 329 | path = FPGA/wbscope 330 | url = https://github.com/ZipCPU/wbscope.git 331 | [submodule "SoCs/airisc_core_complex"] 332 | path = RISCV/airisc_core_complex 333 | url = https://github.com/Fraunhofer-IMS/airisc_core_complex.git 334 | [submodule "Generators/HDLGen"] 335 | path = Generators/HDLGen 336 | url = https://github.com/WilsonChen003/HDLGen.git 337 | [submodule "Components/core_dvi_framebuffer"] 338 | path = Components/core_dvi_framebuffer 339 | url = https://github.com/ultraembedded/core_dvi_framebuffer.git 340 | [submodule "FPGA/FPGA-Gzip-compressor"] 341 | path = FPGA/FPGA-Gzip-compressor 342 | url = https://github.com/WangXuan95/FPGA-Gzip-compressor.git 343 | [submodule "Components/core_audio"] 344 | path = Components/core_audio 345 | url = https://github.com/ultraembedded/core_audio.git 346 | [submodule "FPGA/XilinxUnisimLibrary"] 347 | path = FPGA/XilinxUnisimLibrary 348 | url = https://github.com/Xilinx/XilinxUnisimLibrary.git 349 | [submodule "FPGA/fpga-sdft"] 350 | path = FPGA/fpga-sdft 351 | url = https://github.com/mattvenn/fpga-sdft.git 352 | [submodule "Components/core_usb_cdc"] 353 | path = Components/core_usb_cdc 354 | url = https://github.com/ultraembedded/core_usb_cdc.git 355 | [submodule "Components/DDR2_Controller"] 356 | path = Components/DDR2_Controller 357 | url = https://github.com/adibis/DDR2_Controller.git 358 | [submodule "FPGA/FPGA-SDcard-Reader-SPI"] 359 | path = FPGA/FPGA-SDcard-Reader-SPI 360 | url = https://github.com/WangXuan95/FPGA-SDcard-Reader-SPI.git 361 | [submodule "SoCs/ARM9-compatible-soft-CPU-core"] 362 | path = SoCs/ARM9-compatible-soft-CPU-core 363 | url = https://github.com/risclite/ARM9-compatible-soft-CPU-core.git 364 | [submodule "Components/cordic"] 365 | path = Components/cordic 366 | url = https://github.com/cebarnes/cordic.git 367 | [submodule "SoCs/picorv32_Xilinx"] 368 | path = RISCV/picorv32_Xilinx 369 | url = https://github.com/cjhonlyone/picorv32_Xilinx.git 370 | [submodule "FPGA/FPGA-LZMA-compressor"] 371 | path = FPGA/FPGA-LZMA-compressor 372 | url = https://github.com/WangXuan95/FPGA-LZMA-compressor.git 373 | [submodule "Components/Ethernet-design-verilog"] 374 | path = Components/Ethernet-design-verilog 375 | url = https://github.com/maxs-well/Ethernet-design-verilog.git 376 | [submodule "Components/sha1"] 377 | path = Components/sha1 378 | url = https://github.com/secworks/sha1.git 379 | [submodule "FPGA/polyphony"] 380 | path = FPGA/polyphony 381 | url = https://github.com/Kenji-Ishimaru/polyphony.git 382 | [submodule "FPGA/AES-FPGA"] 383 | path = FPGA/AES-FPGA 384 | url = https://github.com/mematrix/AES-FPGA.git 385 | [submodule "SoCs/Superscalar-HIT-Core-NSCSCC2020"] 386 | path = SoCs/Superscalar-HIT-Core-NSCSCC2020 387 | url = https://github.com/Superscalar-HIT-Core/Superscalar-HIT-Core-NSCSCC2020.git 388 | [submodule "Generators/hw"] 389 | path = Generators/hw 390 | url = https://github.com/nvdla/hw.git 391 | [submodule "Generators/OpenSoCFabric"] 392 | path = Generators/OpenSoCFabric 393 | url = https://github.com/LBL-CoDEx/OpenSoCFabric.git 394 | [submodule "MISC/tnoc"] 395 | path = MISC/tnoc 396 | url = https://github.com/taichi-ishitani/tnoc.git 397 | [submodule "MISC/Open-Source-Network-on-Chip-Router-RTL"] 398 | path = MISC/Open-Source-Network-on-Chip-Router-RTL 399 | url = https://github.com/anan-cn/Open-Source-Network-on-Chip-Router-RTL.git 400 | [submodule "Generators/constellation"] 401 | path = Generators/constellation 402 | url = https://github.com/ucb-bar/constellation.git 403 | [submodule "Generators/XiangShan"] 404 | path = RISCV/XiangShan 405 | url = https://github.com/OpenXiangShan/XiangShan.git 406 | [submodule "SoCs/tinyriscv"] 407 | path = RISCV/tinyriscv 408 | url = https://gitee.com/liangkangnan/tinyriscv.git 409 | [submodule "SoCs/SparrowRV"] 410 | path = RISCV/SparrowRV 411 | url = https://gitee.com/xiaowuzxc/SparrowRV.git 412 | [submodule "SoCs/yuheng-riscv-soc"] 413 | path = RISCV/yuheng-riscv-soc 414 | url = https://gitee.com/dengchow/yuheng-riscv-soc.git 415 | [submodule "FPGA/Book_VIP"] 416 | path = FPGA/Book_VIP 417 | url = https://gitee.com/crazybingo/Book_VIP.git 418 | [submodule "SoCs/CK_Riscv"] 419 | path = RISCV/CK_Riscv 420 | url = https://gitee.com/Core_Kingdom/CK_Riscv.git 421 | [submodule "Analog/evolutionary-circuits"] 422 | path = Analog/evolutionary-circuits 423 | url = https://github.com/Ttl/evolutionary-circuits.git 424 | [submodule "Analog/GANA_circuit_data"] 425 | path = Analog/GANA_circuit_data 426 | url = https://github.com/kkunal1408/GANA_circuit_data.git 427 | [submodule "Analog/CktGNN"] 428 | path = Analog/CktGNN 429 | url = https://github.com/zehao-dong/CktGNN.git 430 | [submodule "Analog/avsdpll_1v8"] 431 | path = Analog/avsdpll_1v8 432 | url = https://github.com/lakshmi-sathi/avsdpll_1v8.git 433 | [submodule "Analog/RF-design-of-1.9-GHz-Rx-frontend"] 434 | path = Analog/RF-design-of-1.9-GHz-Rx-frontend 435 | url = https://github.com/muhammadaldacher/RF-design-of-1.9-GHz-Rx-frontend.git 436 | [submodule "Analog/butterworth-filter"] 437 | path = Analog/butterworth-filter 438 | url = https://github.com/arasgungore/butterworth-filter.git 439 | [submodule "Analog/ADS124S08"] 440 | path = Analog/ADS124S08 441 | url = https://github.com/shridattdudhat/ADS124S08.git 442 | [submodule "Analog/circuit-fewshot-code"] 443 | path = Analog/circuit-fewshot-code 444 | url = https://github.com/kouroshHakha/circuit-fewshot-code.git 445 | [submodule "Analog/3320VCF"] 446 | path = Analog/3320VCF 447 | url = https://github.com/hermflink/3320VCF.git 448 | [submodule "Analog/3310ADSR"] 449 | path = Analog/3310ADSR 450 | url = https://github.com/hermflink/3310ADSR.git 451 | [submodule "Analog/3330VCA"] 452 | path = Analog/3330VCA 453 | url = https://github.com/hermflink/3330VCA.git 454 | [submodule "Analog/VCO"] 455 | path = Analog/VCO 456 | url = https://github.com/Dhairya2908/VCO.git 457 | [submodule "Analog/Defuzzifier-Circuit"] 458 | path = Analog/Defuzzifier-Circuit 459 | url = https://github.com/pouryahoseini/Defuzzifier-Circuit.git 460 | [submodule "accelerators/fpga_accelerator_yolov3tiny"] 461 | path = accelerators/fpga_accelerator_yolov3tiny 462 | url = https://github.com/adamgallas/fpga_accelerator_yolov3tiny.git 463 | [submodule "accelerators/SpinalDLA"] 464 | path = accelerators/SpinalDLA 465 | url = https://github.com/adamgallas/SpinalDLA.git 466 | [submodule "Generators/litex"] 467 | path = Generators/litex 468 | url = https://github.com/enjoy-digital/litex.git 469 | [submodule "FPGA/openfpga-pong"] 470 | path = FPGA/openfpga-pong 471 | url = https://github.com/enjoy-digital/openfpga-pong.git 472 | [submodule "FPGA/verilog-i2c"] 473 | path = FPGA/verilog-i2c 474 | url = https://github.com/alexforencich/verilog-i2c.git 475 | [submodule "FPGA/verilog-pcie"] 476 | path = FPGA/verilog-pcie 477 | url = https://github.com/alexforencich/verilog-pcie.git 478 | [submodule "FPGA/verilog-axi"] 479 | path = FPGA/verilog-axi 480 | url = https://github.com/alexforencich/verilog-axi.git 481 | [submodule "FPGA/verilog-axis"] 482 | path = FPGA/verilog-axis 483 | url = https://github.com/alexforencich/verilog-axis.git 484 | [submodule "FPGA/verilog-ethernet"] 485 | path = FPGA/verilog-ethernet 486 | url = https://github.com/alexforencich/verilog-ethernet.git 487 | [submodule "FPGA/corundum"] 488 | path = FPGA/corundum 489 | url = https://github.com/corundum/corundum.git 490 | [submodule "FPGA/xfcp"] 491 | path = FPGA/xfcp 492 | url = https://github.com/alexforencich/xfcp.git 493 | [submodule "FPGA/verilog-uart"] 494 | path = FPGA/verilog-uart 495 | url = https://github.com/alexforencich/verilog-uart.git 496 | [submodule "FPGA/verilog-cam"] 497 | path = FPGA/verilog-cam 498 | url = https://github.com/alexforencich/verilog-cam.git 499 | [submodule "FPGA/vcu118_fmcp_qsfp"] 500 | path = FPGA/vcu118_fmcp_qsfp 501 | url = https://github.com/lastweek/vcu118_fmcp_qsfp.git 502 | [submodule "RISCV/VexRiscv"] 503 | path = RISCV/VexRiscv 504 | url = https://github.com/SpinalHDL/VexRiscv.git 505 | [submodule "RISCV/NaxRiscv"] 506 | path = RISCV/NaxRiscv 507 | url = https://github.com/SpinalHDL/NaxRiscv.git 508 | [submodule "RISCV/VexiiRiscv"] 509 | path = RISCV/VexiiRiscv 510 | url = https://github.com/SpinalHDL/VexiiRiscv.git 511 | [submodule "RISCV/SaxonSoc"] 512 | path = RISCV/SaxonSoc 513 | url = https://github.com/SpinalHDL/SaxonSoc.git 514 | [submodule "Analog/circuit-fewshot-data"] 515 | path = Analog/circuit-fewshot-data 516 | url = https://github.com/kouroshHakha/circuit-fewshot-data.git 517 | [submodule "RISCV/x-heep"] 518 | path = RISCV/x-heep 519 | url = https://github.com/esl-epfl/x-heep.git 520 | [submodule "accelerators/FireFly-v1"] 521 | path = accelerators/FireFly-v1 522 | url = https://github.com/adamgallas/FireFly-v1.git 523 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Design-Dataset 2 | This is a repo to store circuit design datasets 3 | 4 | 5 | # Release Notes: 6 | 2023-12-16: Add verilog projects in Github with more than 50 stars and categorize them. 7 | 8 | 2023-12-19: Add four repos of spinal RISCV cores and create a folder for RISCV deisgns as per issue 1. 9 | --------------------------------------------------------------------------------