├── .gitignore ├── .gitmodules ├── Doc ├── MMU_Cache_Note_2019-11-14.txt └── Microarchitecture │ ├── Figures │ ├── Fig_100_Top_HW_Side.png │ ├── Fig_100_Top_HW_Side.svg │ ├── Fig_200_SoC_Top.png │ ├── Fig_200_SoC_Top.svg │ ├── Fig_300_mkCore.png │ ├── Fig_300_mkCore.svg │ ├── Fig_310_mkCore_v2.png │ ├── Fig_310_mkCore_v2.svg │ ├── Fig_320_mkCore_Resets.png │ ├── Fig_320_mkCore_Resets.svg │ ├── Fig_500_mkCPU_Flute.png │ ├── Fig_500_mkCPU_Flute.svg │ ├── Fig_600_Near_Mem_VM_WB_L1.png │ ├── Fig_600_Near_Mem_VM_WB_L1.svg │ ├── Fig_600_Near_Mem_VM_WB_L1_L2.png │ ├── Fig_600_Near_Mem_VM_WB_L1_L2.svg │ └── Makefile │ ├── Makefile │ ├── Microarchitecture.pdf │ └── Microarchitecture.tex ├── LICENSE ├── README.md ├── Tests ├── Makefile ├── README.txt ├── Run_regression.py ├── elf_to_hex │ ├── Makefile │ ├── README.txt │ └── elf_to_hex.c └── isa │ ├── rv32mi-p-breakpoint │ ├── rv32mi-p-breakpoint.dump │ ├── rv32mi-p-csr │ ├── rv32mi-p-csr.dump │ ├── rv32mi-p-illegal │ ├── rv32mi-p-illegal.dump │ ├── rv32mi-p-ma_addr │ ├── rv32mi-p-ma_addr.dump │ ├── rv32mi-p-ma_fetch │ ├── rv32mi-p-ma_fetch.dump │ ├── rv32mi-p-mcsr │ ├── rv32mi-p-mcsr.dump │ ├── rv32mi-p-sbreak │ ├── rv32mi-p-sbreak.dump │ ├── rv32mi-p-scall │ ├── rv32mi-p-scall.dump │ ├── rv32mi-p-shamt │ ├── rv32mi-p-shamt.dump │ ├── rv32si-p-csr │ ├── rv32si-p-csr.dump │ ├── rv32si-p-dirty │ ├── rv32si-p-dirty.dump │ ├── rv32si-p-ma_fetch │ ├── rv32si-p-ma_fetch.dump │ ├── rv32si-p-sbreak │ ├── rv32si-p-sbreak.dump │ ├── rv32si-p-scall │ ├── rv32si-p-scall.dump │ ├── rv32si-p-wfi │ ├── rv32si-p-wfi.dump │ ├── rv32ua-p-amoadd_w │ ├── rv32ua-p-amoadd_w.dump │ ├── rv32ua-p-amoand_w │ ├── rv32ua-p-amoand_w.dump │ ├── rv32ua-p-amomax_w │ ├── rv32ua-p-amomax_w.dump │ ├── rv32ua-p-amomaxu_w │ ├── rv32ua-p-amomaxu_w.dump │ ├── rv32ua-p-amomin_w │ ├── rv32ua-p-amomin_w.dump │ ├── rv32ua-p-amominu_w │ ├── rv32ua-p-amominu_w.dump │ ├── rv32ua-p-amoor_w │ ├── rv32ua-p-amoor_w.dump │ ├── rv32ua-p-amoswap_w │ ├── rv32ua-p-amoswap_w.dump │ ├── rv32ua-p-amoxor_w │ ├── rv32ua-p-amoxor_w.dump │ ├── rv32ua-p-lrsc │ ├── rv32ua-p-lrsc.dump │ ├── rv32ua-v-amoadd_w │ ├── rv32ua-v-amoadd_w.dump │ ├── rv32ua-v-amoand_w │ ├── rv32ua-v-amoand_w.dump │ ├── rv32ua-v-amomax_w │ ├── rv32ua-v-amomax_w.dump │ ├── rv32ua-v-amomaxu_w │ ├── rv32ua-v-amomaxu_w.dump │ ├── rv32ua-v-amomin_w │ ├── rv32ua-v-amomin_w.dump │ ├── rv32ua-v-amominu_w │ ├── rv32ua-v-amominu_w.dump │ ├── rv32ua-v-amoor_w │ ├── rv32ua-v-amoor_w.dump │ ├── rv32ua-v-amoswap_w │ ├── rv32ua-v-amoswap_w.dump │ ├── rv32ua-v-amoxor_w │ ├── rv32ua-v-amoxor_w.dump │ ├── rv32ua-v-lrsc │ ├── rv32ua-v-lrsc.dump │ ├── rv32uc-p-rvc │ ├── rv32uc-p-rvc.dump │ ├── rv32uc-v-rvc │ ├── rv32uc-v-rvc.dump │ ├── rv32ud-p-fadd │ ├── rv32ud-p-fadd.dump │ ├── rv32ud-p-fclass │ ├── rv32ud-p-fclass.dump │ ├── rv32ud-p-fcmp │ ├── rv32ud-p-fcmp.dump │ ├── rv32ud-p-fcvt │ ├── rv32ud-p-fcvt.dump │ ├── rv32ud-p-fcvt_w │ ├── rv32ud-p-fcvt_w.dump │ ├── rv32ud-p-fdiv │ ├── rv32ud-p-fdiv.dump │ ├── rv32ud-p-fmadd │ ├── rv32ud-p-fmadd.dump │ ├── rv32ud-p-fmin │ ├── rv32ud-p-fmin.dump │ ├── rv32ud-p-ldst │ ├── rv32ud-p-ldst.dump │ ├── rv32ud-p-recoding │ ├── rv32ud-p-recoding.dump │ ├── rv32ud-v-fadd │ ├── rv32ud-v-fadd.dump │ ├── rv32ud-v-fclass │ ├── rv32ud-v-fclass.dump │ ├── rv32ud-v-fcmp │ ├── rv32ud-v-fcmp.dump │ ├── rv32ud-v-fcvt │ ├── rv32ud-v-fcvt.dump │ ├── rv32ud-v-fcvt_w │ ├── rv32ud-v-fcvt_w.dump │ ├── rv32ud-v-fdiv │ ├── rv32ud-v-fdiv.dump │ ├── rv32ud-v-fmadd │ ├── rv32ud-v-fmadd.dump │ ├── rv32ud-v-fmin │ ├── rv32ud-v-fmin.dump │ ├── rv32ud-v-ldst │ ├── rv32ud-v-ldst.dump │ ├── rv32ud-v-recoding │ ├── rv32ud-v-recoding.dump │ ├── rv32uf-p-fadd │ ├── rv32uf-p-fadd.dump │ ├── rv32uf-p-fclass │ ├── rv32uf-p-fclass.dump │ ├── rv32uf-p-fcmp │ ├── rv32uf-p-fcmp.dump │ ├── rv32uf-p-fcvt │ ├── rv32uf-p-fcvt.dump │ ├── rv32uf-p-fcvt_w │ ├── rv32uf-p-fcvt_w.dump │ ├── rv32uf-p-fdiv │ ├── rv32uf-p-fdiv.dump │ ├── rv32uf-p-fmadd │ ├── rv32uf-p-fmadd.dump │ ├── rv32uf-p-fmin │ ├── rv32uf-p-fmin.dump │ ├── rv32uf-p-ldst │ ├── rv32uf-p-ldst.dump │ ├── rv32uf-p-move │ ├── rv32uf-p-move.dump │ ├── rv32uf-p-posits │ ├── rv32uf-p-posits.dump │ ├── rv32uf-p-recoding │ ├── rv32uf-p-recoding.dump │ ├── rv32uf-v-fadd │ ├── rv32uf-v-fadd.dump │ ├── rv32uf-v-fclass │ ├── rv32uf-v-fclass.dump │ ├── rv32uf-v-fcmp │ ├── rv32uf-v-fcmp.dump │ ├── rv32uf-v-fcvt │ ├── rv32uf-v-fcvt.dump │ ├── rv32uf-v-fcvt_w │ ├── rv32uf-v-fcvt_w.dump │ ├── rv32uf-v-fdiv │ ├── rv32uf-v-fdiv.dump │ ├── rv32uf-v-fmadd │ ├── rv32uf-v-fmadd.dump │ ├── rv32uf-v-fmin │ ├── rv32uf-v-fmin.dump │ ├── rv32uf-v-ldst │ ├── rv32uf-v-ldst.dump │ ├── rv32uf-v-move │ ├── rv32uf-v-move.dump │ ├── rv32uf-v-recoding │ ├── rv32uf-v-recoding.dump │ ├── rv32ui-p-add │ ├── rv32ui-p-add.dump │ ├── rv32ui-p-addi │ ├── rv32ui-p-addi.dump │ ├── rv32ui-p-and │ ├── rv32ui-p-and.dump │ ├── rv32ui-p-andi │ ├── rv32ui-p-andi.dump │ ├── rv32ui-p-auipc │ ├── rv32ui-p-auipc.dump │ ├── rv32ui-p-beq │ ├── rv32ui-p-beq.dump │ ├── rv32ui-p-bge │ ├── rv32ui-p-bge.dump │ ├── rv32ui-p-bgeu │ ├── rv32ui-p-bgeu.dump │ ├── rv32ui-p-blt │ ├── rv32ui-p-blt.dump │ ├── rv32ui-p-bltu │ ├── rv32ui-p-bltu.dump │ ├── rv32ui-p-bne │ ├── rv32ui-p-bne.dump │ ├── rv32ui-p-fence_i │ ├── rv32ui-p-fence_i.dump │ ├── rv32ui-p-jal │ ├── rv32ui-p-jal.dump │ ├── rv32ui-p-jalr │ ├── rv32ui-p-jalr.dump │ ├── rv32ui-p-lb │ ├── rv32ui-p-lb.dump │ ├── rv32ui-p-lbu │ ├── rv32ui-p-lbu.dump │ ├── rv32ui-p-lh │ ├── rv32ui-p-lh.dump │ ├── rv32ui-p-lhu │ ├── rv32ui-p-lhu.dump │ ├── rv32ui-p-lui │ ├── rv32ui-p-lui.dump │ ├── rv32ui-p-lw │ ├── rv32ui-p-lw.dump │ ├── rv32ui-p-or │ ├── rv32ui-p-or.dump │ ├── rv32ui-p-ori │ ├── rv32ui-p-ori.dump │ ├── rv32ui-p-sb │ ├── rv32ui-p-sb.dump │ ├── rv32ui-p-sh │ ├── rv32ui-p-sh.dump │ ├── rv32ui-p-simple │ ├── rv32ui-p-simple.dump │ ├── rv32ui-p-sll │ ├── rv32ui-p-sll.dump │ ├── rv32ui-p-slli │ ├── rv32ui-p-slli.dump │ ├── rv32ui-p-slt │ ├── rv32ui-p-slt.dump │ ├── rv32ui-p-slti │ ├── rv32ui-p-slti.dump │ ├── rv32ui-p-sltiu │ ├── rv32ui-p-sltiu.dump │ ├── rv32ui-p-sltu │ ├── rv32ui-p-sltu.dump │ ├── rv32ui-p-sra │ ├── rv32ui-p-sra.dump │ ├── rv32ui-p-srai │ ├── rv32ui-p-srai.dump │ ├── rv32ui-p-srl │ ├── rv32ui-p-srl.dump │ ├── rv32ui-p-srli │ ├── rv32ui-p-srli.dump │ ├── rv32ui-p-sub │ ├── rv32ui-p-sub.dump │ ├── rv32ui-p-sw │ ├── rv32ui-p-sw.dump │ ├── rv32ui-p-xor │ ├── rv32ui-p-xor.dump │ ├── rv32ui-p-xori │ ├── rv32ui-p-xori.dump │ ├── rv32ui-v-add │ ├── rv32ui-v-add.dump │ ├── rv32ui-v-addi │ ├── rv32ui-v-addi.dump │ ├── rv32ui-v-and │ ├── rv32ui-v-and.dump │ ├── rv32ui-v-andi │ ├── rv32ui-v-andi.dump │ ├── rv32ui-v-auipc │ ├── rv32ui-v-auipc.dump │ ├── rv32ui-v-beq │ ├── rv32ui-v-beq.dump │ ├── rv32ui-v-bge │ ├── rv32ui-v-bge.dump │ ├── rv32ui-v-bgeu │ ├── rv32ui-v-bgeu.dump │ ├── rv32ui-v-blt │ ├── rv32ui-v-blt.dump │ ├── rv32ui-v-bltu │ ├── rv32ui-v-bltu.dump │ ├── rv32ui-v-bne │ ├── rv32ui-v-bne.dump │ ├── rv32ui-v-fence_i │ ├── rv32ui-v-fence_i.dump │ ├── rv32ui-v-jal │ ├── rv32ui-v-jal.dump │ ├── rv32ui-v-jalr │ ├── rv32ui-v-jalr.dump │ ├── rv32ui-v-lb │ ├── rv32ui-v-lb.dump │ ├── rv32ui-v-lbu │ ├── rv32ui-v-lbu.dump │ ├── rv32ui-v-lh │ ├── rv32ui-v-lh.dump │ ├── rv32ui-v-lhu │ ├── rv32ui-v-lhu.dump │ ├── rv32ui-v-lui │ ├── rv32ui-v-lui.dump │ ├── rv32ui-v-lw │ ├── rv32ui-v-lw.dump │ ├── rv32ui-v-or │ ├── rv32ui-v-or.dump │ ├── rv32ui-v-ori │ ├── rv32ui-v-ori.dump │ ├── rv32ui-v-sb │ ├── rv32ui-v-sb.dump │ ├── rv32ui-v-sh │ ├── rv32ui-v-sh.dump │ ├── rv32ui-v-simple │ ├── rv32ui-v-simple.dump │ ├── rv32ui-v-sll │ ├── rv32ui-v-sll.dump │ ├── rv32ui-v-slli │ ├── rv32ui-v-slli.dump │ ├── rv32ui-v-slt │ ├── rv32ui-v-slt.dump │ ├── rv32ui-v-slti │ ├── rv32ui-v-slti.dump │ ├── rv32ui-v-sltiu │ ├── rv32ui-v-sltiu.dump │ ├── rv32ui-v-sltu │ ├── rv32ui-v-sltu.dump │ ├── rv32ui-v-sra │ ├── rv32ui-v-sra.dump │ ├── rv32ui-v-srai │ ├── rv32ui-v-srai.dump │ ├── rv32ui-v-srl │ ├── rv32ui-v-srl.dump │ ├── rv32ui-v-srli │ ├── rv32ui-v-srli.dump │ ├── rv32ui-v-sub │ ├── rv32ui-v-sub.dump │ ├── rv32ui-v-sw │ ├── rv32ui-v-sw.dump │ ├── rv32ui-v-xor │ ├── rv32ui-v-xor.dump │ ├── rv32ui-v-xori │ ├── rv32ui-v-xori.dump │ ├── rv32um-p-div │ ├── rv32um-p-div.dump │ ├── rv32um-p-divu │ ├── rv32um-p-divu.dump │ ├── rv32um-p-mul │ ├── rv32um-p-mul.dump │ ├── rv32um-p-mulh │ ├── rv32um-p-mulh.dump │ ├── rv32um-p-mulhsu │ ├── rv32um-p-mulhsu.dump │ ├── rv32um-p-mulhu │ ├── rv32um-p-mulhu.dump │ ├── rv32um-p-rem │ ├── rv32um-p-rem.dump │ ├── rv32um-p-remu │ ├── rv32um-p-remu.dump │ ├── rv32um-v-div │ ├── rv32um-v-div.dump │ ├── rv32um-v-divu │ ├── rv32um-v-divu.dump │ ├── rv32um-v-mul │ ├── rv32um-v-mul.dump │ ├── rv32um-v-mulh │ ├── rv32um-v-mulh.dump │ ├── rv32um-v-mulhsu │ ├── rv32um-v-mulhsu.dump │ ├── rv32um-v-mulhu │ ├── rv32um-v-mulhu.dump │ ├── rv32um-v-rem │ ├── rv32um-v-rem.dump │ ├── rv32um-v-remu │ ├── rv32um-v-remu.dump │ ├── rv64mi-p-access │ ├── rv64mi-p-access.dump │ ├── rv64mi-p-breakpoint │ ├── rv64mi-p-breakpoint.dump │ ├── rv64mi-p-csr │ ├── rv64mi-p-csr.dump │ ├── rv64mi-p-illegal │ ├── rv64mi-p-illegal.dump │ ├── rv64mi-p-ma_addr │ ├── rv64mi-p-ma_addr.dump │ ├── rv64mi-p-ma_fetch │ ├── rv64mi-p-ma_fetch.dump │ ├── rv64mi-p-mcsr │ ├── rv64mi-p-mcsr.dump │ ├── rv64mi-p-sbreak │ ├── rv64mi-p-sbreak.dump │ ├── rv64mi-p-scall │ ├── rv64mi-p-scall.dump │ ├── rv64si-p-csr │ ├── rv64si-p-csr.dump │ ├── rv64si-p-dirty │ ├── rv64si-p-dirty.dump │ ├── rv64si-p-ma_fetch │ ├── rv64si-p-ma_fetch.dump │ ├── rv64si-p-sbreak │ ├── rv64si-p-sbreak.dump │ ├── rv64si-p-scall │ ├── rv64si-p-scall.dump │ ├── rv64si-p-wfi │ ├── rv64si-p-wfi.dump │ ├── rv64ua-p-amoadd_d │ ├── rv64ua-p-amoadd_d.dump │ ├── rv64ua-p-amoadd_w │ ├── rv64ua-p-amoadd_w.dump │ ├── rv64ua-p-amoand_d │ ├── rv64ua-p-amoand_d.dump │ ├── rv64ua-p-amoand_w │ ├── rv64ua-p-amoand_w.dump │ ├── rv64ua-p-amomax_d │ ├── rv64ua-p-amomax_d.dump │ ├── rv64ua-p-amomax_w │ ├── rv64ua-p-amomax_w.dump │ ├── rv64ua-p-amomaxu_d │ ├── rv64ua-p-amomaxu_d.dump │ ├── rv64ua-p-amomaxu_w │ ├── rv64ua-p-amomaxu_w.dump │ ├── rv64ua-p-amomin_d │ ├── rv64ua-p-amomin_d.dump │ ├── rv64ua-p-amomin_w │ ├── rv64ua-p-amomin_w.dump │ ├── rv64ua-p-amominu_d │ ├── rv64ua-p-amominu_d.dump │ ├── rv64ua-p-amominu_w │ ├── rv64ua-p-amominu_w.dump │ ├── rv64ua-p-amoor_d │ ├── rv64ua-p-amoor_d.dump │ ├── rv64ua-p-amoor_w │ ├── rv64ua-p-amoor_w.dump │ ├── rv64ua-p-amoswap_d │ ├── rv64ua-p-amoswap_d.dump │ ├── rv64ua-p-amoswap_w │ ├── rv64ua-p-amoswap_w.dump │ ├── rv64ua-p-amoxor_d │ ├── rv64ua-p-amoxor_d.dump │ ├── rv64ua-p-amoxor_w │ ├── rv64ua-p-amoxor_w.dump │ ├── rv64ua-p-lrsc │ ├── rv64ua-p-lrsc.dump │ ├── rv64ua-v-amoadd_d │ ├── rv64ua-v-amoadd_d.dump │ ├── rv64ua-v-amoadd_w │ ├── rv64ua-v-amoadd_w.dump │ ├── rv64ua-v-amoand_d │ ├── rv64ua-v-amoand_d.dump │ ├── rv64ua-v-amoand_w │ ├── rv64ua-v-amoand_w.dump │ ├── rv64ua-v-amomax_d │ ├── rv64ua-v-amomax_d.dump │ ├── rv64ua-v-amomax_w │ ├── rv64ua-v-amomax_w.dump │ ├── rv64ua-v-amomaxu_d │ ├── rv64ua-v-amomaxu_d.dump │ ├── rv64ua-v-amomaxu_w │ ├── rv64ua-v-amomaxu_w.dump │ ├── rv64ua-v-amomin_d │ ├── rv64ua-v-amomin_d.dump │ ├── rv64ua-v-amomin_w │ ├── rv64ua-v-amomin_w.dump │ ├── rv64ua-v-amominu_d │ ├── rv64ua-v-amominu_d.dump │ ├── rv64ua-v-amominu_w │ ├── rv64ua-v-amominu_w.dump │ ├── rv64ua-v-amoor_d │ ├── rv64ua-v-amoor_d.dump │ ├── rv64ua-v-amoor_w │ ├── rv64ua-v-amoor_w.dump │ ├── rv64ua-v-amoswap_d │ ├── rv64ua-v-amoswap_d.dump │ ├── rv64ua-v-amoswap_w │ ├── rv64ua-v-amoswap_w.dump │ ├── rv64ua-v-amoxor_d │ ├── rv64ua-v-amoxor_d.dump │ ├── rv64ua-v-amoxor_w │ ├── rv64ua-v-amoxor_w.dump │ ├── rv64ua-v-lrsc │ ├── rv64ua-v-lrsc.dump │ ├── rv64uc-p-rvc │ ├── rv64uc-p-rvc.dump │ ├── rv64uc-v-rvc │ ├── rv64uc-v-rvc.dump │ ├── rv64ud-p-fadd │ ├── rv64ud-p-fadd.dump │ ├── rv64ud-p-fclass │ ├── rv64ud-p-fclass.dump │ ├── rv64ud-p-fcmp │ ├── rv64ud-p-fcmp.dump │ ├── rv64ud-p-fcvt │ ├── rv64ud-p-fcvt.dump │ ├── rv64ud-p-fcvt_w │ ├── rv64ud-p-fcvt_w.dump │ ├── rv64ud-p-fdiv │ ├── rv64ud-p-fdiv.dump │ ├── rv64ud-p-fmadd │ ├── rv64ud-p-fmadd.dump │ ├── rv64ud-p-fmin │ ├── rv64ud-p-fmin.dump │ ├── rv64ud-p-ldst │ ├── rv64ud-p-ldst.dump │ ├── rv64ud-p-move │ ├── rv64ud-p-move.dump │ ├── rv64ud-p-recoding │ ├── rv64ud-p-recoding.dump │ ├── rv64ud-p-structural │ ├── rv64ud-p-structural.dump │ ├── rv64ud-v-fadd │ ├── rv64ud-v-fadd.dump │ ├── rv64ud-v-fclass │ ├── rv64ud-v-fclass.dump │ ├── rv64ud-v-fcmp │ ├── rv64ud-v-fcmp.dump │ ├── rv64ud-v-fcvt │ ├── rv64ud-v-fcvt.dump │ ├── rv64ud-v-fcvt_w │ ├── rv64ud-v-fcvt_w.dump │ ├── rv64ud-v-fdiv │ ├── rv64ud-v-fdiv.dump │ ├── rv64ud-v-fmadd │ ├── rv64ud-v-fmadd.dump │ ├── rv64ud-v-fmin │ ├── rv64ud-v-fmin.dump │ ├── rv64ud-v-ldst │ ├── rv64ud-v-ldst.dump │ ├── rv64ud-v-move │ ├── rv64ud-v-move.dump │ ├── rv64ud-v-recoding │ ├── rv64ud-v-recoding.dump │ ├── rv64ud-v-structural │ ├── rv64ud-v-structural.dump │ ├── rv64uf-p-fadd │ ├── rv64uf-p-fadd.dump │ ├── rv64uf-p-fclass │ ├── rv64uf-p-fclass.dump │ ├── rv64uf-p-fcmp │ ├── rv64uf-p-fcmp.dump │ ├── rv64uf-p-fcvt │ ├── rv64uf-p-fcvt.dump │ ├── rv64uf-p-fcvt_w │ ├── rv64uf-p-fcvt_w.dump │ ├── rv64uf-p-fdiv │ ├── rv64uf-p-fdiv.dump │ ├── rv64uf-p-fmadd │ ├── rv64uf-p-fmadd.dump │ ├── rv64uf-p-fmin │ ├── rv64uf-p-fmin.dump │ ├── rv64uf-p-ldst │ ├── rv64uf-p-ldst.dump │ ├── rv64uf-p-move │ ├── rv64uf-p-move.dump │ ├── rv64uf-p-recoding │ ├── rv64uf-p-recoding.dump │ ├── rv64uf-v-fadd │ ├── rv64uf-v-fadd.dump │ ├── rv64uf-v-fclass │ ├── rv64uf-v-fclass.dump │ ├── rv64uf-v-fcmp │ ├── rv64uf-v-fcmp.dump │ ├── rv64uf-v-fcvt │ ├── rv64uf-v-fcvt.dump │ ├── rv64uf-v-fcvt_w │ ├── rv64uf-v-fcvt_w.dump │ ├── rv64uf-v-fdiv │ ├── rv64uf-v-fdiv.dump │ ├── rv64uf-v-fmadd │ ├── rv64uf-v-fmadd.dump │ ├── rv64uf-v-fmin │ ├── rv64uf-v-fmin.dump │ ├── rv64uf-v-ldst │ ├── rv64uf-v-ldst.dump │ ├── rv64uf-v-move │ ├── rv64uf-v-move.dump │ ├── rv64uf-v-recoding │ ├── rv64uf-v-recoding.dump │ ├── rv64ui-p-add │ ├── rv64ui-p-add.dump │ ├── rv64ui-p-addi │ ├── rv64ui-p-addi.dump │ ├── rv64ui-p-addiw │ ├── rv64ui-p-addiw.dump │ ├── rv64ui-p-addw │ ├── rv64ui-p-addw.dump │ ├── rv64ui-p-and │ ├── rv64ui-p-and.dump │ ├── rv64ui-p-andi │ ├── rv64ui-p-andi.dump │ ├── rv64ui-p-auipc │ ├── rv64ui-p-auipc.dump │ ├── rv64ui-p-beq │ ├── rv64ui-p-beq.dump │ ├── rv64ui-p-bge │ ├── rv64ui-p-bge.dump │ ├── rv64ui-p-bgeu │ ├── rv64ui-p-bgeu.dump │ ├── rv64ui-p-blt │ ├── rv64ui-p-blt.dump │ ├── rv64ui-p-bltu │ ├── rv64ui-p-bltu.dump │ ├── rv64ui-p-bne │ ├── rv64ui-p-bne.dump │ ├── rv64ui-p-fence_i │ ├── rv64ui-p-fence_i.dump │ ├── rv64ui-p-jal │ ├── rv64ui-p-jal.dump │ ├── rv64ui-p-jalr │ ├── rv64ui-p-jalr.dump │ ├── rv64ui-p-lb │ ├── rv64ui-p-lb.dump │ ├── rv64ui-p-lbu │ ├── rv64ui-p-lbu.dump │ ├── rv64ui-p-ld │ ├── rv64ui-p-ld.dump │ ├── rv64ui-p-lh │ ├── rv64ui-p-lh.dump │ ├── rv64ui-p-lhu │ ├── rv64ui-p-lhu.dump │ ├── rv64ui-p-lui │ ├── rv64ui-p-lui.dump │ ├── rv64ui-p-lw │ ├── rv64ui-p-lw.dump │ ├── rv64ui-p-lwu │ ├── rv64ui-p-lwu.dump │ ├── rv64ui-p-or │ ├── rv64ui-p-or.dump │ ├── rv64ui-p-ori │ ├── rv64ui-p-ori.dump │ ├── rv64ui-p-sb │ ├── rv64ui-p-sb.dump │ ├── rv64ui-p-sd │ ├── rv64ui-p-sd.dump │ ├── rv64ui-p-sh │ ├── rv64ui-p-sh.dump │ ├── rv64ui-p-simple │ ├── rv64ui-p-simple.dump │ ├── rv64ui-p-sll │ ├── rv64ui-p-sll.dump │ ├── rv64ui-p-slli │ ├── rv64ui-p-slli.dump │ ├── rv64ui-p-slliw │ ├── rv64ui-p-slliw.dump │ ├── rv64ui-p-sllw │ ├── rv64ui-p-sllw.dump │ ├── rv64ui-p-slt │ ├── rv64ui-p-slt.dump │ ├── rv64ui-p-slti │ ├── rv64ui-p-slti.dump │ ├── rv64ui-p-sltiu │ ├── rv64ui-p-sltiu.dump │ ├── rv64ui-p-sltu │ ├── rv64ui-p-sltu.dump │ ├── rv64ui-p-sra │ ├── rv64ui-p-sra.dump │ ├── rv64ui-p-srai │ ├── rv64ui-p-srai.dump │ ├── rv64ui-p-sraiw │ ├── rv64ui-p-sraiw.dump │ ├── rv64ui-p-sraw │ ├── rv64ui-p-sraw.dump │ ├── rv64ui-p-srl │ ├── rv64ui-p-srl.dump │ ├── rv64ui-p-srli │ ├── rv64ui-p-srli.dump │ ├── rv64ui-p-srliw │ ├── rv64ui-p-srliw.dump │ ├── rv64ui-p-srlw │ ├── rv64ui-p-srlw.dump │ ├── rv64ui-p-sub │ ├── rv64ui-p-sub.dump │ ├── rv64ui-p-subw │ ├── rv64ui-p-subw.dump │ ├── rv64ui-p-sw │ ├── rv64ui-p-sw.dump │ ├── rv64ui-p-xor │ ├── rv64ui-p-xor.dump │ ├── rv64ui-p-xori │ ├── rv64ui-p-xori.dump │ ├── rv64ui-v-add │ ├── rv64ui-v-add.dump │ ├── rv64ui-v-addi │ ├── rv64ui-v-addi.dump │ ├── rv64ui-v-addiw │ ├── rv64ui-v-addiw.dump │ ├── rv64ui-v-addw │ ├── rv64ui-v-addw.dump │ ├── rv64ui-v-and │ ├── rv64ui-v-and.dump │ ├── rv64ui-v-andi │ ├── rv64ui-v-andi.dump │ ├── rv64ui-v-auipc │ ├── rv64ui-v-auipc.dump │ ├── rv64ui-v-beq │ ├── rv64ui-v-beq.dump │ ├── rv64ui-v-bge │ ├── rv64ui-v-bge.dump │ ├── rv64ui-v-bgeu │ ├── rv64ui-v-bgeu.dump │ ├── rv64ui-v-blt │ ├── rv64ui-v-blt.dump │ ├── rv64ui-v-bltu │ ├── rv64ui-v-bltu.dump │ ├── rv64ui-v-bne │ ├── rv64ui-v-bne.dump │ ├── rv64ui-v-fence_i │ ├── rv64ui-v-fence_i.dump │ ├── rv64ui-v-jal │ ├── rv64ui-v-jal.dump │ ├── rv64ui-v-jalr │ ├── rv64ui-v-jalr.dump │ ├── rv64ui-v-lb │ ├── rv64ui-v-lb.dump │ ├── rv64ui-v-lbu │ ├── rv64ui-v-lbu.dump │ ├── rv64ui-v-ld │ ├── rv64ui-v-ld.dump │ ├── rv64ui-v-lh │ ├── rv64ui-v-lh.dump │ ├── rv64ui-v-lhu │ ├── rv64ui-v-lhu.dump │ ├── rv64ui-v-lui │ ├── rv64ui-v-lui.dump │ ├── rv64ui-v-lw │ ├── rv64ui-v-lw.dump │ ├── rv64ui-v-lwu │ ├── rv64ui-v-lwu.dump │ ├── rv64ui-v-or │ ├── rv64ui-v-or.dump │ ├── rv64ui-v-ori │ ├── rv64ui-v-ori.dump │ ├── rv64ui-v-sb │ ├── rv64ui-v-sb.dump │ ├── rv64ui-v-sd │ ├── rv64ui-v-sd.dump │ ├── rv64ui-v-sh │ ├── rv64ui-v-sh.dump │ ├── rv64ui-v-simple │ ├── rv64ui-v-simple.dump │ ├── rv64ui-v-sll │ ├── rv64ui-v-sll.dump │ ├── rv64ui-v-slli │ ├── rv64ui-v-slli.dump │ ├── rv64ui-v-slliw │ ├── rv64ui-v-slliw.dump │ ├── rv64ui-v-sllw │ ├── rv64ui-v-sllw.dump │ ├── rv64ui-v-slt │ ├── rv64ui-v-slt.dump │ ├── rv64ui-v-slti │ ├── rv64ui-v-slti.dump │ ├── rv64ui-v-sltiu │ ├── rv64ui-v-sltiu.dump │ ├── rv64ui-v-sltu │ ├── rv64ui-v-sltu.dump │ ├── rv64ui-v-sra │ ├── rv64ui-v-sra.dump │ ├── rv64ui-v-srai │ ├── rv64ui-v-srai.dump │ ├── rv64ui-v-sraiw │ ├── rv64ui-v-sraiw.dump │ ├── rv64ui-v-sraw │ ├── rv64ui-v-sraw.dump │ ├── rv64ui-v-srl │ ├── rv64ui-v-srl.dump │ ├── rv64ui-v-srli │ ├── rv64ui-v-srli.dump │ ├── rv64ui-v-srliw │ ├── rv64ui-v-srliw.dump │ ├── rv64ui-v-srlw │ ├── rv64ui-v-srlw.dump │ ├── rv64ui-v-sub │ ├── rv64ui-v-sub.dump │ ├── rv64ui-v-subw │ ├── rv64ui-v-subw.dump │ ├── rv64ui-v-sw │ ├── rv64ui-v-sw.dump │ ├── rv64ui-v-xor │ ├── rv64ui-v-xor.dump │ ├── rv64ui-v-xori │ ├── rv64ui-v-xori.dump │ ├── rv64um-p-div │ ├── rv64um-p-div.dump │ ├── rv64um-p-divu │ ├── rv64um-p-divu.dump │ ├── rv64um-p-divuw │ ├── rv64um-p-divuw.dump │ ├── rv64um-p-divw │ ├── rv64um-p-divw.dump │ ├── rv64um-p-mul │ ├── rv64um-p-mul.dump │ ├── rv64um-p-mulh │ ├── rv64um-p-mulh.dump │ ├── rv64um-p-mulhsu │ ├── rv64um-p-mulhsu.dump │ ├── rv64um-p-mulhu │ ├── rv64um-p-mulhu.dump │ ├── rv64um-p-mulw │ ├── rv64um-p-mulw.dump │ ├── rv64um-p-rem │ ├── rv64um-p-rem.dump │ ├── rv64um-p-remu │ ├── rv64um-p-remu.dump │ ├── rv64um-p-remuw │ ├── rv64um-p-remuw.dump │ ├── rv64um-p-remw │ ├── rv64um-p-remw.dump │ ├── rv64um-v-div │ ├── rv64um-v-div.dump │ ├── rv64um-v-divu │ ├── rv64um-v-divu.dump │ ├── rv64um-v-divuw │ ├── rv64um-v-divuw.dump │ ├── rv64um-v-divw │ ├── rv64um-v-divw.dump │ ├── rv64um-v-mul │ ├── rv64um-v-mul.dump │ ├── rv64um-v-mulh │ ├── rv64um-v-mulh.dump │ ├── rv64um-v-mulhsu │ ├── rv64um-v-mulhsu.dump │ ├── rv64um-v-mulhu │ ├── rv64um-v-mulhu.dump │ ├── rv64um-v-mulw │ ├── rv64um-v-mulw.dump │ ├── rv64um-v-rem │ ├── rv64um-v-rem.dump │ ├── rv64um-v-remu │ ├── rv64um-v-remu.dump │ ├── rv64um-v-remuw │ ├── rv64um-v-remuw.dump │ ├── rv64um-v-remw │ └── rv64um-v-remw.dump ├── applications ├── .gitignore ├── Makefile ├── Optical-Flow │ ├── Makefile │ ├── README │ ├── bare.lds │ ├── bare.specs │ ├── img_rubik.h │ ├── img_sphere.h │ ├── lucaskanade_f32.c │ └── lucaskanade_f32q32.c ├── gemm │ ├── Makefile │ ├── README.adoc │ ├── bare.lds │ ├── bare.specs │ ├── gemm.c │ └── instr.list ├── gemv │ ├── Makefile │ ├── README.adoc │ ├── bare.lds │ ├── bare.specs │ ├── gemv.c │ └── instr.list ├── givens │ ├── Makefile │ ├── bare.lds │ ├── bare.specs │ └── givens.c ├── lib │ ├── clarinet.c │ ├── clarinet.h │ ├── main.c │ ├── riscv_counters.c │ ├── riscv_counters.h │ ├── startup.S │ ├── syscalls.c │ └── uart.c ├── tools │ ├── README │ ├── batch-compile │ ├── gen_data │ ├── instr_cycle_counter │ └── run_all.sh └── vdp │ ├── Makefile │ ├── README.md │ ├── bare.lds │ ├── bare.specs │ ├── instr.list │ └── vdp.c ├── binutils ├── README └── opcodes ├── builds ├── Makefile.Clarinet ├── RV32ACDFIMSU_FDIV_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACDFIMSU_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_FDIV_P16_P_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_FDIV_P16_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_FDIV_P24_P_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_FDIV_P24_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_FDIV_P32_P_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_FDIV_P32_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_FDIV_P8_P_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_FDIV_P8_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_FDIV_verilator │ └── Makefile ├── RV32ACFIMSU_P16_P_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_P16_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_P24_P_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_P24_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_P32_P_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_P32_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_P8_P_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_P8_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACFIMSU_verilator │ ├── Makefile │ └── src_bsv │ │ └── Posit_Numeric_Types.bsv ├── RV32ACIMSU_verilator │ └── Makefile ├── Resources │ ├── Build_all.mk │ ├── Include_Common.mk │ ├── Include_bluesim.mk │ ├── Include_iverilog.mk │ ├── Include_verilator.mk │ ├── Verilator_resources │ │ ├── import_DPI_C_decls.v │ │ ├── sed_script.txt │ │ ├── sim_main.cpp │ │ └── verilator_config.vlt │ └── mkBuild_Dir.py ├── mkCPUWrapper.v └── release-rtl.tar.gz ├── src_Core ├── BSV_Additional_Libs │ ├── AXI4_Stream.bsv │ ├── ByteLane.bsv │ ├── CreditCounter.bsv │ ├── Cur_Cycle.bsv │ ├── EdgeFIFOFs.bsv │ ├── GetPut_Aux.bsv │ └── Semi_FIFOF.bsv ├── CPU │ ├── Branch_Predictor.bsv │ ├── CPU.bsv │ ├── CPU_Decode_C.bsv │ ├── CPU_Fetch_C.bsv │ ├── CPU_Globals.bsv │ ├── CPU_IFC.bsv │ ├── CPU_Stage1.bsv │ ├── CPU_Stage2.bsv │ ├── CPU_Stage3.bsv │ ├── CPU_StageD.bsv │ ├── CPU_StageF.bsv │ ├── EX_ALU_functions.bsv │ ├── FBox_Core.bsv │ ├── FBox_Top.bsv │ ├── FPU.bsv │ ├── FPU_Types.bsv │ ├── IntMulDiv.bsv │ ├── RISCV_MBox.bsv │ └── Shifter_Box.bsv ├── Cache_Config │ ├── Cache_Decls_RV32_4KB_1way.bsv │ ├── Cache_Decls_RV32_8KB_2way.bsv │ ├── Cache_Decls_RV32_Sv32_4KB_1way.bsv │ ├── Cache_Decls_RV32_Sv32_8KB_2way.bsv │ ├── Cache_Decls_RV64_4KB_1way.bsv │ ├── Cache_Decls_RV64_8KB_2way.bsv │ ├── Cache_Decls_RV64_Sv39_4KB_1way.bsv │ ├── Cache_Decls_RV64_Sv39_8KB_2way.bsv │ ├── Gen_BSV_Cache_Decls.py │ ├── Makefile │ ├── README.txt │ ├── RV32_4KB_1way_args.yaml │ ├── RV32_8KB_2way_args.yaml │ ├── RV32_Sv32_4KB_1way_args.yaml │ ├── RV32_Sv32_8KB_2way_args.yaml │ ├── RV64_4KB_1way_args.yaml │ ├── RV64_8KB_2way_args.yaml │ ├── RV64_Sv39_4KB_1way_args.yaml │ └── RV64_Sv39_8KB_2way_args.yaml ├── Core │ ├── Core.bsv │ ├── Core_IFC.bsv │ ├── Fabric_2x3.bsv │ ├── Fabric_Defs.bsv │ ├── TV_Encode.bsv │ └── TV_Taps.bsv ├── Core_v2 │ ├── Core.bsv │ ├── Core_IFC.bsv │ ├── Dma_Server_Mux.bsv │ ├── Fabric_1x3.bsv │ ├── Fabric_Defs.bsv │ ├── TV_Encode.bsv │ └── TV_Taps.bsv ├── Debug_Module │ ├── DM_Abstract_Commands.bsv │ ├── DM_CPU_Req_Rsp.bsv │ ├── DM_Common.bsv │ ├── DM_Run_Control.bsv │ ├── DM_System_Bus.bsv │ ├── Debug_Module.bsv │ ├── README.txt │ └── Test │ │ ├── Makefile │ │ └── Testbench.bsv ├── ISA │ ├── ISA_Decls.bsv │ ├── ISA_Decls_C.bsv │ ├── ISA_Decls_Priv_M.bsv │ ├── ISA_Decls_Priv_S.bsv │ └── TV_Info.bsv ├── Near_Mem_IO │ ├── Near_Mem_IO.bsv │ ├── Near_Mem_IO_AXI4.bsv │ └── README.txt ├── Near_Mem_VM_WB_L1 │ ├── AXI4_Lite_MMU_Cache_Adapter.bsv │ ├── Cache.bsv │ ├── Cache_Decls.bsv │ ├── D_MMU_Cache.bsv │ ├── I_MMU_Cache.bsv │ ├── MMIO.bsv │ ├── MMU_Cache_AXI4_Adapter.bsv │ ├── MMU_Cache_Arbiter.bsv │ ├── MMU_Cache_Common.bsv │ ├── Near_Mem_Caches.bsv │ ├── Near_Mem_IFC.bsv │ ├── PTW.bsv │ └── TLB.bsv ├── Near_Mem_VM_WB_L1_L2 │ ├── AXI4_Lite_MMU_Cache_Adapter.bsv │ ├── Cache.bsv │ ├── Cache_Decls.bsv │ ├── D_MMU_Cache.bsv │ ├── I_MMU_Cache.bsv │ ├── LLC_AXI4_Adapter.bsv │ ├── LLC_AXI4_Adapter_2.bsv │ ├── MMIO.bsv │ ├── MMIO_AXI4_Adapter.bsv │ ├── MMU_Cache_AXI4_Adapter.bsv │ ├── MMU_Cache_Arbiter.bsv │ ├── MMU_Cache_Common.bsv │ ├── Near_Mem_Caches.bsv │ ├── Near_Mem_IFC.bsv │ ├── PTW.bsv │ ├── README.txt │ ├── TLB.bsv │ └── src_LLCache │ │ ├── Copy_Toooba_Files.mk │ │ ├── L1LLConnect.bsv │ │ ├── LICENSE_RISCY_OOO │ │ ├── LLC_DMA_AXI4_Adapter.bsv │ │ ├── LLCache.bsv │ │ ├── LLCache_Aux.bsv │ │ ├── coherence │ │ └── src │ │ │ ├── CCPipe.bsv │ │ │ ├── CCTypes.bsv │ │ │ ├── CrossBar.bsv │ │ │ ├── IBank.bsv │ │ │ ├── ICRqMshr.bsv │ │ │ ├── IPRqMshr.bsv │ │ │ ├── LLBank.bsv │ │ │ ├── LLCRqMshr.bsv │ │ │ ├── LLPipe.bsv │ │ │ ├── MshrDeadlockChecker.bsv │ │ │ ├── RWBramCore.bsv │ │ │ └── RandomReplace.bsv │ │ └── procs │ │ ├── RV64G_OOO │ │ └── ProcConfig.bsv │ │ └── lib │ │ ├── Amo.bsv │ │ ├── CacheUtils.bsv │ │ ├── Ehr.bsv │ │ ├── Fifos.bsv │ │ ├── FullAssocTlb.bsv │ │ ├── LLCRqMshrSecureModel.bsv │ │ ├── LatencyTimer.bsv │ │ ├── MMIOAddrs.bsv │ │ ├── MemLoaderIF.bsv │ │ ├── MemoryTypes.bsv │ │ ├── MsgFifo.bsv │ │ ├── Performance.bsv │ │ ├── ProcTypes.bsv │ │ ├── SafeCounter.bsv │ │ ├── SetAssocTlb.bsv │ │ ├── TranslationCache.bsv │ │ └── Types.bsv ├── Near_Mem_VM_WT_L1 │ ├── AXI4_Lite_MMU_Cache_Adapter.bsv │ ├── Cache_Decls.bsv │ ├── MMU_Cache.bsv │ ├── MMU_Cache_Arbiter.bsv │ ├── MMU_Cache_Common.bsv │ ├── MMU_Cache_Note_2019-11-14.txt │ ├── Near_Mem_Caches.bsv │ ├── Near_Mem_IFC.bsv │ └── TLB.bsv ├── PLIC │ ├── Makefile │ ├── PLIC.bsv │ ├── PLIC_16_2_7.bsv │ ├── README_PLIC.txt │ └── Test_PLIC.bsv └── RegFiles │ ├── CSR_MIE.bsv │ ├── CSR_MIP.bsv │ ├── CSR_MSTATUS.bsv │ ├── CSR_RegFile.bsv │ ├── CSR_RegFile_MSU.bsv │ ├── CSR_RegFile_UM.bsv │ ├── FPR_RegFile.bsv │ ├── GPR_RegFile.bsv │ └── PPR_RegFile.bsv ├── src_Testbench ├── Fabrics │ ├── AXI4 │ │ ├── AXI4_Addr_Translator.bsv │ │ ├── AXI4_Deburster.bsv │ │ ├── AXI4_Fabric.bsv │ │ ├── AXI4_Mem_Model.bsv │ │ ├── AXI4_Types.bsv │ │ ├── AXI4_Widener.bsv │ │ └── Unit_Test │ │ │ ├── Makefile │ │ │ └── Unit_Test_Deburster.bsv │ ├── AXI4_Lite │ │ ├── AXI4_Lite_Fabric.bsv │ │ ├── AXI4_Lite_Types.bsv │ │ └── Unit_Test │ │ │ ├── Makefile │ │ │ └── Unit_Test_Fabric.bsv │ ├── Adapters │ │ ├── AXI4_AXI4_Lite_Adapters.bsv │ │ ├── AXI4_Slave_IFC_to_AXI4_Lite_Slave_IFC.bsv │ │ ├── AXI4_Slave_to_AXI4_Lite_Slave_Adapter.bsv │ │ └── README.txt │ └── README_Fabrics.txt ├── SoC │ ├── AXI4_Accel_IFC.bsv │ ├── Accel_Dummy │ │ └── AXI4_Accel_Dummy.bsv │ ├── Boot_ROM.bsv │ ├── Boot_ROM_Generator │ │ ├── .gitignore │ │ ├── Gen_BSV_fn_read_ROM.py │ │ ├── Makefile │ │ └── gen_bootrom.cc │ ├── External_Control.bsv │ ├── Mem_Controller.bsv │ ├── SoC_Fabric.bsv │ ├── SoC_Map.bsv │ ├── SoC_Top.bsv │ ├── Timer.bsv │ ├── UART_Model.bsv │ ├── fn_read_ROM_RV32.bsvi │ └── fn_read_ROM_RV64.bsvi └── Top │ ├── C_Imported_Functions.c │ ├── C_Imported_Functions.h │ ├── C_Imports.bsv │ ├── Makefile │ ├── Mem_Model.bsv │ └── Top_HW_Side.bsv ├── src_bsc_lib_RTL ├── BRAM2.v ├── BRAM2BELoad.v ├── FIFO1.v ├── FIFO10.v ├── FIFO2.v ├── FIFO20.v ├── FIFOL1.v ├── README.txt ├── RegFile.v ├── RegFileLoad.v ├── RevertReg.v ├── SizedFIFO.v ├── SizedFIFO0.v └── main.v └── synthesis ├── README ├── synth-tab-20200329.pdf └── synth-tab-20200329.tex /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | README.html 3 | build_dir 4 | *.o 5 | obj_dir 6 | elf_to_hex 7 | *.hex 8 | exe* 9 | *.log 10 | Tests/Logs 11 | *_edited.v 12 | *.trace_mem_load 13 | AA_* 14 | symbol_table.txt 15 | vpi_wrapper_* 16 | Aux_files 17 | worker* 18 | log_*.txt 19 | Sim_RTL 20 | CPU_RTL 21 | *jou 22 | Logs 23 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "Melodica"] 2 | path = Melodica 3 | url = https://github.com/HPC-Lab-IITB/Melodica 4 | [submodule "riscv-tests"] 5 | path = riscv-tests 6 | url = https://github.com/HPC-Lab-IITB/riscv-tests 7 | -------------------------------------------------------------------------------- /Doc/Microarchitecture/Figures/Fig_100_Top_HW_Side.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HPC-Lab-IITB/Clarinet/0bf84b2db46a1a2a0c0575f94de50aead2b5f1b6/Doc/Microarchitecture/Figures/Fig_100_Top_HW_Side.png -------------------------------------------------------------------------------- /Doc/Microarchitecture/Figures/Fig_200_SoC_Top.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HPC-Lab-IITB/Clarinet/0bf84b2db46a1a2a0c0575f94de50aead2b5f1b6/Doc/Microarchitecture/Figures/Fig_200_SoC_Top.png -------------------------------------------------------------------------------- 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$(FIGS_PNG) 17 | 18 | $(FIGS_PNG): %.png: %.svg 19 | inkscape --export-filename=$@ --export-area-drawing -d 300 -y 0.0 $< 20 | 21 | # ================================================================ 22 | 23 | .PHONY: clean 24 | clean: 25 | rm -r -f *~ 26 | 27 | .PHONY: full_clean 28 | full_clean: 29 | rm -r -f *~ $(FIGS_PNG) 30 | 31 | # ================================================================ 32 | -------------------------------------------------------------------------------- /Doc/Microarchitecture/Makefile: -------------------------------------------------------------------------------- 1 | TOP_FILE = Microarchitecture 2 | 3 | # ================================================================ 4 | 5 | .PHONY: default 6 | default: 7 | mkdir -p Aux_files 8 | pdflatex -output-directory=Aux_files $(TOP_FILE).tex 9 | cp -p Aux_files/$(TOP_FILE).pdf . 10 | 11 | .PHONY: figures 12 | figures: 13 | make -C Figures 14 | 15 | # ================================================================ 16 | 17 | .PHONY: clean 18 | clean: 19 | rm -r -f *~ Aux_files/* Figures/*~ 20 | 21 | .PHONY: full_clean 22 | full_clean: clean 23 | rm -r -f $(TOP_FILE).pdf 24 | -------------------------------------------------------------------------------- /Doc/Microarchitecture/Microarchitecture.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HPC-Lab-IITB/Clarinet/0bf84b2db46a1a2a0c0575f94de50aead2b5f1b6/Doc/Microarchitecture/Microarchitecture.pdf -------------------------------------------------------------------------------- /Tests/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # Copyright (c) 2018 Bluespec, Inc. All Rights Reserved 4 | 5 | # ================================================================ 6 | # Regression: run all ISA tests relevant for the chosen simulator 7 | 8 | # ---------------- 9 | # Choose a prefix for the simulation executable dir 10 | 11 | ARCH ?= RV32IMU 12 | # ARCH ?= RV32ACIMSU 13 | 14 | # ARCH ?= RV64IMU 15 | # ARCH ?= RV64ACIMSU 16 | 17 | # ---------------- 18 | # Choose a simulation engine 19 | 20 | SIM ?= Bluesim 21 | # SIM ?= iverilog 22 | # SIM ?= verilator 23 | 24 | # ---------------- 25 | # Optionally choose an architecture explicitly, 26 | # overriding the simulation executable path 27 | 28 | OPTARCH ?= 29 | 30 | # ---------------- 31 | SIM_DIR = ../builds/$(ARCH)_$(SIM) 32 | 33 | # ================================================================ 34 | 35 | .PHONY: test 36 | test: 37 | @echo "Running regressions; saving logs in Logs/" 38 | ./Run_regression.py \ 39 | $(SIM_DIR)/exe_HW_sim \ 40 | ./isa ./Logs $(OPTARCH) 41 | @echo "Finished running regressions; saved logs in Logs/" 42 | 43 | # ================================================================ 44 | 45 | .PHONY: clean 46 | clean: 47 | rm *~ 48 | 49 | .PHONY: full_clean 50 | full_clean: 51 | rm -r -f *~ Logs *.log 52 | -------------------------------------------------------------------------------- /Tests/elf_to_hex/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile to create an elf_to_hex executable. 2 | # The executable creates mem-hex files containing 32-Byte words 3 | 4 | CC = gcc 5 | 6 | elf_to_hex: elf_to_hex.c 7 | gcc -g -o elf_to_hex elf_to_hex.c -lelf 8 | 9 | # ================================================================ 10 | 11 | .PHONY: clean 12 | clean: 13 | rm -f *~ 14 | 15 | .PHONY: full_clean 16 | full_clean: 17 | rm -f *~ elf_to_hex 18 | -------------------------------------------------------------------------------- /Tests/elf_to_hex/README.txt: -------------------------------------------------------------------------------- 1 | Copyright (c) 2018 Bluespec, Inc. All Rights Reserved 2 | 3 | This standalone C program takes two command-line arguments, and ELF 4 | filename and a Mem Hex filename. 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https://raw.githubusercontent.com/HPC-Lab-IITB/Clarinet/0bf84b2db46a1a2a0c0575f94de50aead2b5f1b6/Tests/isa/rv64um-v-remuw -------------------------------------------------------------------------------- /Tests/isa/rv64um-v-remw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HPC-Lab-IITB/Clarinet/0bf84b2db46a1a2a0c0575f94de50aead2b5f1b6/Tests/isa/rv64um-v-remw -------------------------------------------------------------------------------- /applications/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | *.dump 3 | *.rpt 4 | *.csv 5 | logs 6 | analysis 7 | deprecated 8 | -------------------------------------------------------------------------------- /applications/Optical-Flow/Makefile: -------------------------------------------------------------------------------- 1 | # -*- makefile -*- 2 | # This is not a standalone makefile. It includes flags to control 3 | # the structure of the application in this directory 4 | # 5 | # -------- 6 | # Command line arguments 7 | # The type of computation being run (POSIT, FLOAT_POSIT, FLOAT) 8 | TYPE ?= POSIT 9 | 10 | # The width of the posit input data values. This is only relevant when TYPE = POSIT 11 | PWIDTH ?= PWIDTH_32 12 | 13 | VSZ = 16 14 | 15 | # -------- 16 | 17 | # The benchmark being run 18 | APP_FLAGS = -D$(TYPE) 19 | APP_FLAGS += -D$(PWIDTH) 20 | APP_FLAGS += -DVSZ=$(VSZ) 21 | 22 | include ../Makefile 23 | -------------------------------------------------------------------------------- /applications/Optical-Flow/README: -------------------------------------------------------------------------------- 1 | This optical flow example has been translitered based on the work at: 2 | 3 | https://github.com/scivision/Optical-Flow-LucasKanade-HornSchunck 4 | 5 | Their work was in python, but as the Clarinet bare-metal platform we are testing on does not support python, the program has been transliterated into C. 6 | -------------------------------------------------------------------------------- /applications/Optical-Flow/bare.lds: -------------------------------------------------------------------------------- 1 | SECTIONS 2 | { 3 | __startup_save = .; 4 | .startup 0x80000000: { KEEP(startup.o(.text)) } 5 | . = 0x80100000; 6 | .tohost : { *(.tohost) } 7 | . = __startup_save; 8 | } 9 | INSERT AFTER .bss; 10 | INPUT(syscalls.o) 11 | INPUT(uart.o) 12 | -------------------------------------------------------------------------------- /applications/Optical-Flow/bare.specs: -------------------------------------------------------------------------------- 1 | %rename link_gcc_c_sequence bare_link_gcc_c_sequence 2 | %rename lib bare_lib 3 | 4 | *bare_libgloss: 5 | -lnosys 6 | 7 | *bare_libc: 8 | %{!specs=nano.specs:-lc} %{specs=nano.specs:-lc_nano} 9 | 10 | *link_gcc_c_sequence: 11 | %(bare_link_gcc_c_sequence) --start-group %G %(bare_libc) %(bare_libgloss) --end-group 12 | 13 | *lib: 14 | -lnosys 15 | -------------------------------------------------------------------------------- /applications/Optical-Flow/img_rubik.h: -------------------------------------------------------------------------------- 1 | img_rubik_p8.h -------------------------------------------------------------------------------- /applications/gemm/Makefile: -------------------------------------------------------------------------------- 1 | # -*- makefile -*- 2 | # This is not a standalone makefile. It includes flags to control 3 | # the structure of the application in this directory 4 | # 5 | # -------- 6 | # Command line arguments 7 | # The type of computation being run (POSIT, FLOAT_POSIT, FLOAT) 8 | TYPE ?= POSIT 9 | 10 | # The width of the posit input data values. This is only relevant when TYPE = POSIT 11 | PWIDTH ?= PWIDTH_8 12 | 13 | # -------- 14 | 15 | # The benchmark being run 16 | APP_FLAGS = -D$(TYPE) 17 | APP_FLAGS += -D$(PWIDTH) 18 | APP_FLAGS += -DVSZ=$(VSZ) 19 | APP_FLAGS += -D$(USE_FMADD) 20 | APP_FLAGS += -D$(CACHES) 21 | 22 | include ../Makefile 23 | -------------------------------------------------------------------------------- /applications/gemm/README.adoc: -------------------------------------------------------------------------------- 1 | # GEMM - Matrix-Matrix Product 2 | Uses GEMV under the hood. 3 | 4 | The following variations are supported: 5 | 6 | . Float-GEMV 7 | . Posit-GEMV using float input data 8 | . Posit-GEMV using posit input data 9 | 10 | In the case of posit input data 8, 16, 24 and 32 bit posits are supported 11 | 12 | `VSZ` varies the dimension of the matrix and vector. The matrix is a square matrix of size 13 | `VSZ`x`VSZ`, the vector is 1x`VSZ` 14 | 15 | To generate the data, compile and simulate all variants on Clarinet run the python script: 16 | 17 | `../batch-compile --compile --sim --main gemm --level 3` 18 | -------------------------------------------------------------------------------- /applications/gemm/bare.lds: -------------------------------------------------------------------------------- 1 | SECTIONS 2 | { 3 | __startup_save = .; 4 | .startup 0x80000000: { KEEP(startup.o(.text)) } 5 | . = 0x88000000; 6 | .tohost : { *(.tohost) } 7 | . = __startup_save; 8 | } 9 | INSERT AFTER .bss; 10 | INPUT(syscalls.o) 11 | INPUT(uart.o) 12 | -------------------------------------------------------------------------------- /applications/gemm/bare.specs: -------------------------------------------------------------------------------- 1 | %rename link_gcc_c_sequence bare_link_gcc_c_sequence 2 | %rename lib bare_lib 3 | 4 | *bare_libgloss: 5 | -lnosys 6 | 7 | *bare_libc: 8 | %{!specs=nano.specs:-lc} %{specs=nano.specs:-lc_nano} 9 | 10 | *link_gcc_c_sequence: 11 | %(bare_link_gcc_c_sequence) --start-group %G %(bare_libc) %(bare_libgloss) --end-group 12 | 13 | *lib: 14 | -lnosys 15 | -------------------------------------------------------------------------------- /applications/gemm/gemm.c: -------------------------------------------------------------------------------- 1 | #include 2 | //for read_cycle 3 | #include "riscv_counters.h" 4 | // for PRIu64 5 | #include 6 | #include "data_gemm.h" 7 | #include "clarinet.h" 8 | 9 | int main (void) { 10 | 11 | #ifdef POSIT 12 | #ifdef PWIDTH_8 13 | unsigned char acc [VSZ][VSZ]; 14 | #endif 15 | #ifdef PWIDTH_16 16 | unsigned short acc [VSZ][VSZ]; 17 | #endif 18 | #ifdef PWIDTH_24 19 | unsigned int acc [VSZ][VSZ]; 20 | #endif 21 | #ifdef PWIDTH_32 22 | unsigned int acc [VSZ][VSZ]; 23 | #endif 24 | #endif 25 | 26 | #ifdef DOUBLE 27 | #else 28 | #endif 29 | 30 | uint32_t start = 0; 31 | uint32_t end = 0; 32 | uint32_t elapsed = 0; 33 | 34 | // Now lets do some cycle analysis 35 | #ifdef FLOAT 36 | float acc [VSZ][VSZ]; 37 | #ifdef WARM_CACHES 38 | fn_float_gemm (acc, VSZ, m_a, m_b); 39 | #endif 40 | start=read_cycle(); 41 | fn_float_gemm (acc, VSZ, m_a, m_b); 42 | #endif 43 | 44 | #ifdef DOUBLE 45 | double acc [VSZ][VSZ]; 46 | #ifdef WARM_CACHES 47 | fn_double_gemm (acc, VSZ, m_a, m_b); 48 | #endif 49 | start=read_cycle(); 50 | fn_double_gemm (acc, VSZ, m_a, m_b); 51 | #endif 52 | 53 | #ifdef FLOAT_POSIT 54 | float acc [VSZ][VSZ]; 55 | #ifdef WARM_CACHES 56 | fn_posit_gemm (acc, VSZ, m_a, m_b); 57 | #endif 58 | start=read_cycle(); 59 | fn_posit_gemm (acc, VSZ, m_a, m_b); 60 | #endif 61 | 62 | #ifdef POSIT 63 | #ifdef WARM_CACHES 64 | #ifdef PWIDTH_24 65 | fn_posit_p_gemm (acc, VSZ, m_aH, m_a, m_bH, m_b); 66 | #else 67 | fn_posit_p_gemm (acc, VSZ, m_a, m_b); 68 | #endif 69 | #endif 70 | start=read_cycle(); 71 | #ifdef PWIDTH_24 72 | fn_posit_p_gemm (acc, VSZ, m_aH, m_a, m_bH, m_b); 73 | #else 74 | fn_posit_p_gemm (acc, VSZ, m_a, m_b); 75 | #endif 76 | #endif 77 | 78 | end=read_cycle(); 79 | elapsed = end - start; 80 | printf ("VDP Cycle Report. Size: %d. Cycles: %d\n", VSZ, elapsed); 81 | 82 | return (0); 83 | } 84 | -------------------------------------------------------------------------------- /applications/gemm/instr.list: -------------------------------------------------------------------------------- 1 | fadd.d 2 | fmul.d 3 | fmadd.d 4 | fadd.s 5 | fmul.s 6 | fmadd.s 7 | fma.p 8 | fcvt.r.p 9 | fcvt.p.r 10 | pmv.x.w 11 | pmv.w.x 12 | fcvt.p.s 13 | fcvt.s.p 14 | fld 15 | fsd 16 | flw 17 | fsw 18 | lb 19 | lbu 20 | sb 21 | sbu 22 | lw 23 | sw 24 | lh 25 | lhu 26 | sh 27 | shu 28 | -------------------------------------------------------------------------------- /applications/gemv/Makefile: -------------------------------------------------------------------------------- 1 | # -*- makefile -*- 2 | # This is not a standalone makefile. It includes flags to control 3 | # the structure of the application in this directory 4 | # 5 | # -------- 6 | # Command line arguments 7 | # The type of computation being run (POSIT, FLOAT_POSIT, FLOAT) 8 | TYPE ?= POSIT 9 | 10 | # The width of the posit input data values. This is only relevant when TYPE = POSIT 11 | PWIDTH ?= PWIDTH_8 12 | 13 | # -------- 14 | 15 | # The benchmark being run 16 | APP_FLAGS = -D$(TYPE) 17 | APP_FLAGS += -D$(PWIDTH) 18 | APP_FLAGS += -DVSZ=$(VSZ) 19 | APP_FLAGS += -D$(USE_FMADD) 20 | APP_FLAGS += -D$(CACHES) 21 | 22 | include ../Makefile 23 | -------------------------------------------------------------------------------- /applications/gemv/README.adoc: -------------------------------------------------------------------------------- 1 | # GEMV - Matrix-Vector Product 2 | Uses vector dot product (VDP) under the hood. 3 | 4 | The following variations are supported: 5 | 6 | . Float-VDP 7 | . Posit-VDP using float input data 8 | . Posit-VDP using posit input data 9 | 10 | In the case of posit input data 8, 16, 24 and 32 bit posits are supported 11 | 12 | `VSZ` varies the dimension of the matrix and vector. The matrix is a square matrix of size 13 | `VSZ`x`VSZ`, the vector is 1x`VSZ` 14 | 15 | To generate the data, compile and simulate all variants on Clarinet run the python script: 16 | 17 | `../batch-compile --compile --sim --main gemv --level 2` 18 | -------------------------------------------------------------------------------- /applications/gemv/bare.lds: -------------------------------------------------------------------------------- 1 | SECTIONS 2 | { 3 | __startup_save = .; 4 | .startup 0x80000000: { KEEP(startup.o(.text)) } 5 | . = 0x88000000; 6 | .tohost : { *(.tohost) } 7 | . = __startup_save; 8 | } 9 | INSERT AFTER .bss; 10 | INPUT(syscalls.o) 11 | INPUT(uart.o) 12 | -------------------------------------------------------------------------------- /applications/gemv/bare.specs: -------------------------------------------------------------------------------- 1 | %rename link_gcc_c_sequence bare_link_gcc_c_sequence 2 | %rename lib bare_lib 3 | 4 | *bare_libgloss: 5 | -lnosys 6 | 7 | *bare_libc: 8 | %{!specs=nano.specs:-lc} %{specs=nano.specs:-lc_nano} 9 | 10 | *link_gcc_c_sequence: 11 | %(bare_link_gcc_c_sequence) --start-group %G %(bare_libc) %(bare_libgloss) --end-group 12 | 13 | *lib: 14 | -lnosys 15 | -------------------------------------------------------------------------------- /applications/gemv/gemv.c: -------------------------------------------------------------------------------- 1 | #include 2 | //for read_cycle 3 | #include "riscv_counters.h" 4 | // for PRIu64 5 | #include 6 | #include "data_gemv.h" 7 | #include "clarinet.h" 8 | 9 | int main (void) { 10 | 11 | #ifdef POSIT 12 | #ifdef PWIDTH_8 13 | unsigned char acc [VSZ]; 14 | #endif 15 | #ifdef PWIDTH_16 16 | unsigned short acc [VSZ]; 17 | #endif 18 | #ifdef PWIDTH_24 19 | unsigned int acc [VSZ]; 20 | #endif 21 | #ifdef PWIDTH_32 22 | unsigned int acc [VSZ]; 23 | #endif 24 | #endif 25 | 26 | uint32_t start = 0; 27 | uint32_t end = 0; 28 | uint32_t elapsed = 0; 29 | 30 | // Now lets do some cycle analysis 31 | #ifdef FLOAT 32 | float acc [VSZ]; 33 | #ifdef WARM_CACHES 34 | fn_float_gemv (acc, VSZ, m_a, v_b); 35 | #endif 36 | start=read_cycle(); 37 | fn_float_gemv (acc, VSZ, m_a, v_b); 38 | #endif 39 | 40 | #ifdef DOUBLE 41 | double acc [VSZ]; 42 | #ifdef WARM_CACHES 43 | fn_double_gemv (acc, VSZ, m_a, v_b); 44 | #endif 45 | start=read_cycle(); 46 | fn_double_gemv (acc, VSZ, m_a, v_b); 47 | #endif 48 | 49 | #ifdef FLOAT_POSIT 50 | float acc [VSZ]; 51 | #ifdef WARM_CACHES 52 | fn_posit_gemv (acc, VSZ, m_a, v_b); 53 | #endif 54 | start=read_cycle(); 55 | fn_posit_gemv (acc, VSZ, m_a, v_b); 56 | #endif 57 | 58 | #ifdef POSIT 59 | #ifdef WARM_CACHES 60 | #ifdef PWIDTH_24 61 | fn_posit_p_gemv (acc, VSZ, m_aH, m_a, v_bH, v_b); 62 | #else 63 | fn_posit_p_gemv (acc, VSZ, m_a, v_b); 64 | #endif 65 | #endif 66 | start=read_cycle(); 67 | #ifdef PWIDTH_24 68 | fn_posit_p_gemv (acc, VSZ, m_aH, m_a, v_bH, v_b); 69 | #else 70 | fn_posit_p_gemv (acc, VSZ, m_a, v_b); 71 | #endif 72 | #endif 73 | 74 | end=read_cycle(); 75 | elapsed = end - start; 76 | #ifdef WARM_CACHES 77 | printf ("GEMV Cycle Report (warm caches). Size: %d. Cycles: %d\n", VSZ, elapsed); 78 | #else 79 | printf ("GEMV Cycle Report. Size: %d. Cycles: %d\n", VSZ, elapsed); 80 | #endif 81 | 82 | return (0); 83 | } 84 | -------------------------------------------------------------------------------- /applications/gemv/instr.list: -------------------------------------------------------------------------------- 1 | fadd.d 2 | fmul.d 3 | fmadd.d 4 | fadd.s 5 | fmul.s 6 | fmadd.s 7 | fma.p 8 | fcvt.r.p 9 | fcvt.p.r 10 | pmv.x.w 11 | pmv.w.x 12 | fcvt.p.s 13 | fcvt.s.p 14 | fld 15 | fsd 16 | flw 17 | fsw 18 | lb 19 | lbu 20 | sb 21 | sbu 22 | lw 23 | sw 24 | lh 25 | lhu 26 | sh 27 | shu 28 | -------------------------------------------------------------------------------- /applications/givens/Makefile: -------------------------------------------------------------------------------- 1 | # -*- makefile -*- 2 | # This is not a standalone makefile. It includes flags to control 3 | # the structure of the application in this directory 4 | # 5 | # -------- 6 | # Command line arguments 7 | # The type of computation being run (POSIT, FLOAT_POSIT, FLOAT, DOUBLE) 8 | TYPE ?= POSIT 9 | 10 | # The width of the posit input data values. This is only relevant when TYPE = POSIT 11 | PWIDTH ?= PWIDTH_8 12 | 13 | # -------- 14 | 15 | # The benchmark being run 16 | APP_FLAGS = -D$(TYPE) 17 | APP_FLAGS += -D$(PWIDTH) 18 | APP_FLAGS += -DVSZ=$(VSZ) 19 | APP_FLAGS += -D$(USE_FMADD) 20 | APP_FLAGS += -D$(CACHES) 21 | 22 | include ../Makefile 23 | -------------------------------------------------------------------------------- /applications/givens/bare.lds: -------------------------------------------------------------------------------- 1 | SECTIONS 2 | { 3 | __startup_save = .; 4 | .startup 0x80000000: { KEEP(startup.o(.text)) } 5 | . = 0x88000000; 6 | .tohost : { *(.tohost) } 7 | . = __startup_save; 8 | } 9 | INSERT AFTER .bss; 10 | INPUT(syscalls.o) 11 | INPUT(uart.o) 12 | -------------------------------------------------------------------------------- /applications/givens/bare.specs: -------------------------------------------------------------------------------- 1 | %rename link_gcc_c_sequence bare_link_gcc_c_sequence 2 | %rename lib bare_lib 3 | 4 | *bare_libgloss: 5 | -lnosys 6 | 7 | *bare_libc: 8 | %{!specs=nano.specs:-lc} %{specs=nano.specs:-lc_nano} 9 | 10 | *link_gcc_c_sequence: 11 | %(bare_link_gcc_c_sequence) --start-group %G %(bare_libc) %(bare_libgloss) --end-group 12 | 13 | *lib: 14 | -lnosys 15 | -------------------------------------------------------------------------------- /applications/lib/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | //for read_cycle 4 | #include "riscv_counters.h" 5 | 6 | // for PRIu64 7 | #include 8 | 9 | int main (int argc, char ** argv) 10 | { 11 | uint64_t start=read_cycle(); 12 | printf("Hello World!\n"); 13 | uint64_t end=read_cycle(); 14 | printf("read_cycle: %" PRIu64 " cycles have elapsed.\n",end-start); 15 | return 0; 16 | } 17 | -------------------------------------------------------------------------------- /applications/lib/riscv_counters.c: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2013 Bluespec, Inc. All Rights Reserved 2 | 3 | #include 4 | #include 5 | #include 6 | 7 | // ---------------------------------------------------------------- 8 | // For 64-bit: 9 | // The following are interfaces to inline RISC-V assembly instructions 10 | // RDCYCLE 11 | // For all of them, the result is left in v0 (= x16) per calling convention 12 | 13 | // For 32-bit, we get cycle counter out of MCYCLE / MCYCLEH CSRs. 14 | 15 | // ---------------------------------------------------------------- 16 | // RV32 versions 17 | 18 | #ifdef RV32 19 | 20 | // We use mcycle / mcycleh instead of rdcycle / rdcycleh on 32-bit 21 | // because Rocket32 (P1) seems not to have rdcycleh 22 | uint32_t read_cycle (void) 23 | { 24 | uint32_t hi, lo, tmp; 25 | 26 | __asm__ __volatile__ ( 27 | "1:\n" 28 | "csrr %0, mcycleh\n" 29 | "csrr %1, mcycle\n" 30 | "csrr %2, mcycleh\n" 31 | "bne %0, %2, 1b" 32 | : "=&r" (hi), "=&r" (lo), "=&r" (tmp)); 33 | 34 | // return ((uint64_t)hi << 32) | lo; 35 | return (lo); 36 | } 37 | 38 | #endif 39 | 40 | // ---------------------------------------------------------------- 41 | // RV64 versions 42 | 43 | #ifdef RV64 44 | 45 | uint64_t read_cycle (void) 46 | { 47 | uint64_t result; 48 | 49 | asm volatile ("RDCYCLE %0" : "=r" (result)); 50 | 51 | return result; 52 | } 53 | 54 | #endif 55 | 56 | // ---------------------------------------------------------------- 57 | -------------------------------------------------------------------------------- /applications/lib/riscv_counters.h: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2013 Bluespec, Inc. All Rights Reserved 2 | 3 | #pragma once 4 | 5 | // ---------------------------------------------------------------- 6 | // For 64-bit: 7 | // The following are interfaces to inline RISC-V assembly instructions 8 | // RDCYCLE 9 | // For all of them, the result is left in v0 (= x16) per calling convention 10 | 11 | // For 32-bit, we get cycle counter out of MCYCLE / MCYCLEH CSRs, 12 | // because some processors, e.g., Rocket32p, do not implement 13 | // RDCYCLEH. 14 | 15 | #ifdef RV32 16 | extern uint32_t read_cycle (void); // RDCYCLE 17 | #endif 18 | #ifdef RV64 19 | extern uint64_t read_cycle (void); // RDCYCLE 20 | #endif 21 | -------------------------------------------------------------------------------- /applications/lib/startup.S: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | .globl _reset 4 | 5 | _reset: 6 | // set stack pointer 7 | la t0, _reset 8 | li t1, 0xf0000 9 | add sp, t0, t1 10 | 11 | #if defined(__riscv_float_abi_double) || defined(__riscv_float_abi_single) 12 | // set mstatus.fs to initial 13 | li t0, 0x2000 14 | csrs mstatus, t0 15 | #endif 16 | 17 | j _start 18 | 19 | .pushsection .tohost,"aw",@progbits 20 | .align 6; .global tohost; tohost: .dword 0 21 | .popsection 22 | -------------------------------------------------------------------------------- /applications/lib/syscalls.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | #ifndef __linux__ 7 | 8 | __attribute__ ((weak)) 9 | int _read(int file, char *ptr, int len) { 10 | errno = ENOSYS; 11 | return -1; 12 | } 13 | 14 | __attribute__ ((weak)) 15 | int _write(int file, char *ptr, int len) { 16 | errno = ENOSYS; 17 | return -1; 18 | } 19 | 20 | 21 | #define CLOCK_PERIOD (100000000) 22 | 23 | int gettimeofday(struct timeval *ptimeval, void *ptimezone) { 24 | 25 | if (ptimeval) { 26 | long long tv; 27 | #if __riscv_xlen == 64 28 | asm ("rdtime %0" : "=r" (tv)); 29 | #else 30 | unsigned int tvh; 31 | unsigned int tvl; 32 | asm ("rdtime %0;" 33 | "rdtimeh %1 " : "=r" (tvl), "=r" (tvh)); 34 | tv = ((long long)tvh) << 32 | tvl; 35 | #endif 36 | ptimeval->tv_sec = tv / CLOCK_PERIOD; 37 | ptimeval->tv_usec = tv % CLOCK_PERIOD / (CLOCK_PERIOD / 1000000); 38 | } 39 | 40 | return 0; 41 | } 42 | 43 | unsigned int sleep(unsigned int seconds) { 44 | struct timeval tv; 45 | gettimeofday(&tv, NULL); 46 | seconds += tv.tv_sec; 47 | 48 | while (tv.tv_sec < seconds) 49 | gettimeofday(&tv, NULL); 50 | 51 | return 0; 52 | } 53 | 54 | void *_sbrk (int nbytes) { 55 | errno = ENOMEM; 56 | return (void *)-1; 57 | } 58 | 59 | int _close(int fd) { 60 | errno = ENOSYS; 61 | return -1; 62 | } 63 | 64 | long _lseek(int fd, long offset, int origin ) { 65 | errno = ENOSYS; 66 | return -1; 67 | } 68 | 69 | int _fstat(int fd, struct stat *buffer) { 70 | errno = ENOSYS; 71 | return -1; 72 | } 73 | 74 | int _isatty(int fd) { 75 | errno = ENOSYS; 76 | return 0; 77 | } 78 | 79 | /* Use the "tohost" test-exit signal to end the program */ 80 | void exit_via_tohost(void) __attribute__ ((destructor)); 81 | void exit_via_tohost(void) 82 | { 83 | asm volatile ("li a0, 0x1;" 84 | "sw a0, tohost, t0"); 85 | } 86 | 87 | #endif 88 | -------------------------------------------------------------------------------- /applications/tools/README: -------------------------------------------------------------------------------- 1 | Contains helper scripts to run BLAS applications in batch mode for analysis. 2 | -------------------------------------------------------------------------------- /applications/tools/run_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -f 2 | 3 | # A helper script to run an application across all float and posit configurations 4 | # To be run from the individual application directory 5 | # Cmd line: ./run_all.sh 6 | app=$1 7 | sz=$2 8 | level=$3 9 | 10 | mkdir -p logs/itrace.${sz} 11 | echo "--------" 12 | echo "****** RUNNING WITH VERBOSITY = 0 (WARM) (FMADD) ******" 13 | ../tools/batch-compile --sim --compile --level ${level} --vszs ${sz} --main ${app} --warm-caches --use-fmadd --pwidths 8 --pwidths 16 --pwidths 32 14 | 15 | for t in f32 16 | do 17 | mv logs/$t.${sz}.log logs/itrace.${sz}/${t}.v0.fmadd.${sz}.log 18 | done 19 | 20 | for f in f32-p8 f32-p16 f32-p32 p8 p16 p32 21 | do 22 | mv logs/${f}.${sz}.log logs/itrace.${sz}/${f}.v0.${sz}.log 23 | done 24 | 25 | echo "" 26 | echo "--------" 27 | echo "****** RUNNING WITH VERBOSITY = 1 (WARM) (FMADD) ******" 28 | ../tools/batch-compile --sim --compile --level ${level} --vszs ${sz} --main ${app} --warm-caches --use-fmadd --pwidths 8 --pwidths 16 --pwidths 32 --verbosity +v1 29 | 30 | for t in f32 31 | do 32 | mv logs/$t.${sz}.log logs/itrace.${sz}/$t.fmadd.${sz}.log 33 | mv $t.${sz}.${app}.dump $t.${sz}.${app}-fmadd.dump 34 | done 35 | 36 | for f in f32-p8 f32-p16 f32-p32 p8 p16 p32 37 | do 38 | mv logs/${f}.${sz}.log logs/itrace.${sz}/${f}.${sz}.log 39 | done 40 | 41 | #echo "" 42 | #echo "--------" 43 | #echo "****** RUNNING WITH VERBOSITY = 0 (WARM) ******" 44 | #../batch-compile --sim --compile --vszs ${sz} --main ${app} --warm-caches --data-types FLOAT --data-types DOUBLE 45 | #../tools/batch-compile --sim --compile --level ${level} --vszs ${sz} --main ${app} --warm-caches --data-types FLOAT 46 | 47 | #echo "" 48 | #echo "--------" 49 | #echo "****** RUNNING WITH VERBOSITY = 1 (WARM) ******" 50 | #../tools/batch-compile --sim --compile --vszs ${sz} --main ${app} --warm-caches --data-types FLOAT --data-types DOUBLE --verbosity +v1 51 | #../tools/batch-compile --sim --compile --level ${level} --vszs ${sz} --main ${app} --warm-caches --data-types FLOAT --verbosity +v1 52 | 53 | # for t in f32 f64 54 | #for t in f32 55 | #do 56 | # mv logs/$t.${sz}.log logs/itrace.${sz}/$t.${sz}.log 57 | #done 58 | -------------------------------------------------------------------------------- /applications/vdp/Makefile: -------------------------------------------------------------------------------- 1 | # -*- makefile -*- 2 | # This is not a standalone makefile. It includes flags to control 3 | # the structure of the application in this directory 4 | # 5 | # -------- 6 | # Command line arguments 7 | # The type of computation being run (POSIT, FLOAT_POSIT, FLOAT) 8 | TYPE ?= POSIT 9 | 10 | # The width of the posit input data values. This is only relevant when TYPE = POSIT 11 | PWIDTH ?= PWIDTH_8 12 | 13 | # -------- 14 | 15 | # The benchmark being run 16 | APP_FLAGS = -D$(TYPE) 17 | APP_FLAGS += -D$(PWIDTH) 18 | APP_FLAGS += -DVSZ=$(VSZ) 19 | APP_FLAGS += -D$(USE_FMADD) 20 | APP_FLAGS += -D$(CACHES) 21 | 22 | include ../Makefile 23 | -------------------------------------------------------------------------------- /applications/vdp/README.md: -------------------------------------------------------------------------------- 1 | The "Hello World" of applications - Vector Dot Product of two arrays. 2 | 3 | The following variations are supported: 4 | 5 | 1. Float-VDP 6 | 2. Posit-VDP using float input data 7 | 3. Posit-VDP using posit input data 8 | 9 | In the case of posit input data 8, 16, 24 and 32 bit posits are supported 10 | 11 | In order to vary the length of the VDP computation, the REP macro is used. 12 | 13 | To compile and simulate all variants on Clarinet run the python script: 14 | 15 | `../batch-compile --help` 16 | -------------------------------------------------------------------------------- /applications/vdp/bare.lds: -------------------------------------------------------------------------------- 1 | SECTIONS 2 | { 3 | __startup_save = .; 4 | .startup 0x80000000: { KEEP(startup.o(.text)) } 5 | . = 0x88000000; 6 | .tohost : { *(.tohost) } 7 | . = __startup_save; 8 | } 9 | INSERT AFTER .bss; 10 | INPUT(syscalls.o) 11 | INPUT(uart.o) 12 | -------------------------------------------------------------------------------- /applications/vdp/bare.specs: -------------------------------------------------------------------------------- 1 | %rename link_gcc_c_sequence bare_link_gcc_c_sequence 2 | %rename lib bare_lib 3 | 4 | *bare_libgloss: 5 | -lnosys 6 | 7 | *bare_libc: 8 | %{!specs=nano.specs:-lc} %{specs=nano.specs:-lc_nano} 9 | 10 | *link_gcc_c_sequence: 11 | %(bare_link_gcc_c_sequence) --start-group %G %(bare_libc) %(bare_libgloss) --end-group 12 | 13 | *lib: 14 | -lnosys 15 | -------------------------------------------------------------------------------- /applications/vdp/instr.list: -------------------------------------------------------------------------------- 1 | fadd.d 2 | fmul.d 3 | fmadd.d 4 | fadd.s 5 | fmul.s 6 | fmadd.s 7 | fma.p 8 | fcvt.r.p 9 | fcvt.p.r 10 | pmv.x.w 11 | pmv.w.x 12 | fcvt.p.s 13 | fcvt.s.p 14 | fld 15 | fsd 16 | flw 17 | fsw 18 | lb 19 | lbu 20 | sb 21 | sbu 22 | lw 23 | sw 24 | lh 25 | lhu 26 | sh 27 | shu 28 | -------------------------------------------------------------------------------- /applications/vdp/vdp.c: -------------------------------------------------------------------------------- 1 | #include 2 | //for read_cycle 3 | #include "riscv_counters.h" 4 | // for PRIu64 5 | #include 6 | #include "clarinet.h" 7 | #include "data_vdp.h" 8 | 9 | int main (void) { 10 | 11 | #ifdef POSIT 12 | #ifdef PWIDTH_8 13 | unsigned char acc; 14 | #endif 15 | #ifdef PWIDTH_16 16 | unsigned short acc; 17 | #endif 18 | #ifdef PWIDTH_24 19 | unsigned int acc; 20 | #endif 21 | #ifdef PWIDTH_32 22 | unsigned int acc; 23 | #endif 24 | #endif 25 | 26 | uint32_t start = 0; 27 | uint32_t end = 0; 28 | uint32_t elapsed = 0; 29 | 30 | // Basic VDPs are working 31 | // Now lets do some cycle analysis 32 | #ifdef FLOAT 33 | float acc; 34 | #ifdef WARM_CACHES 35 | acc = fn_float_vdp (VSZ, v_a, v_b); 36 | #endif 37 | 38 | start=read_cycle(); 39 | acc = fn_float_vdp (VSZ, v_a, v_b); 40 | end=read_cycle(); 41 | #endif 42 | 43 | #ifdef FLOAT_POSIT 44 | float acc; 45 | #ifdef WARM_CACHES // run once to warm up caches 46 | acc = fn_posit_vdp (VSZ, v_a, v_b); 47 | #endif 48 | start=read_cycle(); 49 | acc = fn_posit_vdp (VSZ, v_a, v_b); 50 | end=read_cycle(); 51 | #endif 52 | 53 | #ifdef DOUBLE 54 | double acc; 55 | #ifdef WARM_CACHES // run once to warm up caches 56 | acc = fn_double_vdp (VSZ, v_a, v_b); 57 | #endif 58 | 59 | start=read_cycle(); 60 | acc = fn_double_vdp (VSZ, v_a, v_b); 61 | end=read_cycle(); 62 | #endif 63 | 64 | #ifdef POSIT 65 | #ifdef WARM_CACHES 66 | // run once to warm up caches 67 | #ifdef PWIDTH_24 68 | acc = fn_posit_p_vdp (VSZ, v_aH, v_a, v_bH, v_b); 69 | #else 70 | acc = fn_posit_p_vdp (VSZ, v_a, v_b); 71 | #endif 72 | #endif 73 | start=read_cycle(); 74 | #ifdef PWIDTH_24 75 | acc = fn_posit_p_vdp (VSZ, v_aH, v_a, v_bH, v_b); 76 | #else 77 | acc = fn_posit_p_vdp (VSZ, v_a, v_b); 78 | #endif 79 | end=read_cycle(); 80 | #endif 81 | 82 | elapsed = end - start; 83 | #ifdef WARM_CACHES 84 | printf ("VDP Cycle Report (warm caches). Size: %d. Cycles: %d\n", VSZ, elapsed); 85 | #else 86 | printf ("VDP Cycle Report. Size: %d. Cycles: %d\n", VSZ, elapsed); 87 | #endif 88 | 89 | return (0); 90 | } 91 | -------------------------------------------------------------------------------- /builds/Makefile.Clarinet: -------------------------------------------------------------------------------- 1 | # This makefile builds all the different Clarinet flavours 2 | # 3 | # Invocation: make -f Makefile.Clarinet 4 | # Tool Dependencies: bsc, verilator 5 | # 6 | 7 | configs_all = RV32ACIMSU RV32ACFIMSU RV32ACDFIMSU RV32ACDFIMSU_FDIV RV32ACFIMSU_FDIV_P32 RV32ACFIMSU_FDIV_P24 RV32ACFIMSU_FDIV_P16 RV32ACFIMSU_FDIV_P8 RV32ACFIMSU_FDIV_P32_P RV32ACFIMSU_FDIV_P24_P RV32ACFIMSU_FDIV_P16_P RV32ACFIMSU_FDIV_P8_P RV32ACFIMSU_P8 RV32ACFIMSU_P16 RV32ACFIMSU_P24 RV32ACFIMSU_P32 RV32ACFIMSU_P8_P RV32ACFIMSU_P16_P RV32ACFIMSU_P24_P RV32ACFIMSU_P32_P 8 | 9 | configs_no_div = RV32ACIMSU RV32ACFIMSU RV32ACDFIMSU RV32ACFIMSU_P8 RV32ACFIMSU_P16 RV32ACFIMSU_P24 RV32ACFIMSU_P32 RV32ACFIMSU_P8_P RV32ACFIMSU_P16_P RV32ACFIMSU_P24_P RV32ACFIMSU_P32_P 10 | 11 | configs_div = RV32ACDFIMSU_FDIV RV32ACFIMSU_FDIV_P32 RV32ACFIMSU_FDIV_P16 RV32ACFIMSU_FDIV_P8 RV32ACFIMSU_FDIV_P32_P RV32ACFIMSU_FDIV_P16_P RV32ACFIMSU_FDIV_P8_P 12 | 13 | all : $(configs_div) 14 | 15 | $(configs_div) : 16 | $(MAKE) -C $@_verilator full_clean 17 | $(MAKE) -C $@_verilator all 18 | -------------------------------------------------------------------------------- /builds/RV32ACDFIMSU_FDIV_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACDFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_D -D ISA_C \ 18 | -D INCLUDE_FDIV \ 19 | -D INCLUDE_FSQRT \ 20 | -D SHIFT_BARREL \ 21 | -D MULT_SYNTH \ 22 | -D Near_Mem_Caches \ 23 | -D FABRIC64 \ 24 | -D WATCH_TOHOST \ 25 | 26 | # Default ISA test 27 | 28 | TEST ?= rv32ui-p-add 29 | 30 | #================================================================ 31 | # Common boilerplate rules 32 | 33 | include $(REPO)/builds/Resources/Include_Common.mk 34 | 35 | #================================================================ 36 | # Makefile rules for building for specific simulator: bluesim 37 | 38 | include $(REPO)/builds/Resources/Include_verilator.mk 39 | 40 | -------------------------------------------------------------------------------- /builds/RV32ACDFIMSU_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACDFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_D -D ISA_C \ 18 | -D SHIFT_BARREL \ 19 | -D MULT_SYNTH \ 20 | -D Near_Mem_Caches \ 21 | -D FABRIC64 \ 22 | -D WATCH_TOHOST \ 23 | 24 | # Default ISA test 25 | 26 | TEST ?= rv32ui-p-add 27 | 28 | #================================================================ 29 | # Common boilerplate rules 30 | 31 | include $(REPO)/builds/Resources/Include_Common.mk 32 | 33 | #================================================================ 34 | # Makefile rules for building for specific simulator: bluesim 35 | 36 | include $(REPO)/builds/Resources/Include_verilator.mk 37 | 38 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_FDIV_P16_P_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D SHIFT_BARREL \ 19 | -D MULT_SYNTH \ 20 | -D Near_Mem_Caches \ 21 | -D FABRIC64 \ 22 | -D WATCH_TOHOST \ 23 | 24 | # Compilation flags and paths for Melodica 25 | BSC_COMPILATION_FLAGS += \ 26 | -D POSIT \ 27 | -D QUILLS \ 28 | -D INCLUDE_PDIV \ 29 | -D ONLY_POSITS \ 30 | 31 | # For Melodica debug statements 32 | # BSC_COMPILATION_FLAGS += -D RANDOM -D RANDOM_PRINT \ 33 | 34 | # paths to melodica bsv code 35 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF:$(REPO)/Melodica/src_bsv/PtoQ:$(REPO)/Melodica/src_bsv/QtoP 36 | 37 | # Default ISA test 38 | 39 | TEST ?= rv32ui-p-add 40 | 41 | #================================================================ 42 | # Common boilerplate rules 43 | 44 | include $(REPO)/builds/Resources/Include_Common.mk 45 | 46 | #================================================================ 47 | # Makefile rules for building for specific simulator: bluesim 48 | 49 | include $(REPO)/builds/Resources/Include_verilator.mk 50 | 51 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_FDIV_P16_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D INCLUDE_FDIV \ 19 | -D INCLUDE_FSQRT \ 20 | -D SHIFT_BARREL \ 21 | -D MULT_SYNTH \ 22 | -D Near_Mem_Caches \ 23 | -D FABRIC64 \ 24 | -D WATCH_TOHOST \ 25 | 26 | # Compilation flags and paths for Melodica 27 | BSC_COMPILATION_FLAGS += \ 28 | -D POSIT \ 29 | -D QUILLS \ 30 | -D INCLUDE_PDIV \ 31 | 32 | # For Melodica debug statements 33 | # BSC_COMPILATION_FLAGS += -D RANDOM -D RANDOM_PRINT \ 34 | 35 | # paths to melodica bsv code 36 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF:$(REPO)/Melodica/src_bsv/PtoQ:$(REPO)/Melodica/src_bsv/QtoP 37 | 38 | # Default ISA test 39 | 40 | TEST ?= rv32ui-p-add 41 | 42 | #================================================================ 43 | # Common boilerplate rules 44 | 45 | include $(REPO)/builds/Resources/Include_Common.mk 46 | 47 | #================================================================ 48 | # Makefile rules for building for specific simulator: bluesim 49 | 50 | include $(REPO)/builds/Resources/Include_verilator.mk 51 | 52 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_FDIV_P24_P_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D SHIFT_BARREL \ 19 | -D MULT_SYNTH \ 20 | -D Near_Mem_Caches \ 21 | -D FABRIC64 \ 22 | -D WATCH_TOHOST \ 23 | 24 | # Compilation flags and paths for Melodica 25 | BSC_COMPILATION_FLAGS += \ 26 | -D POSIT \ 27 | -D QUILLS \ 28 | -D INCLUDE_PDIV \ 29 | -D ONLY_POSITS \ 30 | 31 | # For Melodica debug statements 32 | # BSC_COMPILATION_FLAGS += -D RANDOM -D RANDOM_PRINT \ 33 | 34 | # paths to melodica bsv code 35 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF:$(REPO)/Melodica/src_bsv/PtoQ:$(REPO)/Melodica/src_bsv/QtoP 36 | 37 | # Default ISA test 38 | 39 | TEST ?= rv32ui-p-add 40 | 41 | #================================================================ 42 | # Common boilerplate rules 43 | 44 | include $(REPO)/builds/Resources/Include_Common.mk 45 | 46 | #================================================================ 47 | # Makefile rules for building for specific simulator: bluesim 48 | 49 | include $(REPO)/builds/Resources/Include_verilator.mk 50 | 51 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_FDIV_P24_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D INCLUDE_FDIV \ 19 | -D INCLUDE_FSQRT \ 20 | -D SHIFT_BARREL \ 21 | -D MULT_SYNTH \ 22 | -D Near_Mem_Caches \ 23 | -D FABRIC64 \ 24 | -D WATCH_TOHOST \ 25 | 26 | # Compilation flags and paths for Melodica 27 | BSC_COMPILATION_FLAGS += \ 28 | -D POSIT \ 29 | -D QUILLS \ 30 | -D INCLUDE_PDIV \ 31 | 32 | # For Melodica debug statements 33 | # BSC_COMPILATION_FLAGS += -D RANDOM -D RANDOM_PRINT \ 34 | 35 | # paths to melodica bsv code 36 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF:$(REPO)/Melodica/src_bsv/PtoQ:$(REPO)/Melodica/src_bsv/QtoP 37 | 38 | # Default ISA test 39 | 40 | TEST ?= rv32ui-p-add 41 | 42 | #================================================================ 43 | # Common boilerplate rules 44 | 45 | include $(REPO)/builds/Resources/Include_Common.mk 46 | 47 | #================================================================ 48 | # Makefile rules for building for specific simulator: bluesim 49 | 50 | include $(REPO)/builds/Resources/Include_verilator.mk 51 | 52 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_FDIV_P32_P_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D SHIFT_BARREL \ 19 | -D MULT_SYNTH \ 20 | -D Near_Mem_Caches \ 21 | -D FABRIC64 \ 22 | -D WATCH_TOHOST \ 23 | 24 | # Compilation flags and paths for Melodica 25 | BSC_COMPILATION_FLAGS += \ 26 | -D POSIT \ 27 | -D QUILLS \ 28 | -D INCLUDE_PDIV \ 29 | -D ONLY_POSITS \ 30 | 31 | # For Melodica debug statements 32 | # BSC_COMPILATION_FLAGS += -D RANDOM -D RANDOM_PRINT \ 33 | 34 | # paths to melodica bsv code 35 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF:$(REPO)/Melodica/src_bsv/PtoQ:$(REPO)/Melodica/src_bsv/QtoP 36 | 37 | # Default ISA test 38 | 39 | TEST ?= rv32ui-p-add 40 | 41 | #================================================================ 42 | # Common boilerplate rules 43 | 44 | include $(REPO)/builds/Resources/Include_Common.mk 45 | 46 | #================================================================ 47 | # Makefile rules for building for specific simulator: bluesim 48 | 49 | include $(REPO)/builds/Resources/Include_verilator.mk 50 | 51 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_FDIV_P32_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D INCLUDE_FDIV \ 19 | -D INCLUDE_FSQRT \ 20 | -D SHIFT_BARREL \ 21 | -D MULT_SYNTH \ 22 | -D Near_Mem_Caches \ 23 | -D FABRIC64 \ 24 | -D WATCH_TOHOST \ 25 | 26 | # Compilation flags and paths for Melodica 27 | BSC_COMPILATION_FLAGS += \ 28 | -D POSIT \ 29 | -D INCLUDE_PDIV \ 30 | 31 | # paths to melodica bsv code 32 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF 33 | 34 | # Default ISA test 35 | 36 | TEST ?= rv32ui-p-add 37 | 38 | #================================================================ 39 | # Common boilerplate rules 40 | 41 | include $(REPO)/builds/Resources/Include_Common.mk 42 | 43 | #================================================================ 44 | # Makefile rules for building for specific simulator: bluesim 45 | 46 | include $(REPO)/builds/Resources/Include_verilator.mk 47 | 48 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_FDIV_P8_P_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D SHIFT_BARREL \ 19 | -D MULT_SYNTH \ 20 | -D Near_Mem_Caches \ 21 | -D FABRIC64 \ 22 | -D WATCH_TOHOST \ 23 | 24 | # Compilation flags and paths for Melodica 25 | BSC_COMPILATION_FLAGS += \ 26 | -D POSIT \ 27 | -D QUILLS \ 28 | -D INCLUDE_PDIV \ 29 | -D ONLY_POSITS \ 30 | -D PWIDTH_8 \ 31 | 32 | # For Melodica debug statements 33 | # BSC_COMPILATION_FLAGS += -D RANDOM -D RANDOM_PRINT \ 34 | 35 | # paths to melodica bsv code 36 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF:$(REPO)/Melodica/src_bsv/PtoQ:$(REPO)/Melodica/src_bsv/QtoP 37 | 38 | # Default ISA test 39 | 40 | TEST ?= rv32ui-p-add 41 | 42 | #================================================================ 43 | # Common boilerplate rules 44 | 45 | include $(REPO)/builds/Resources/Include_Common.mk 46 | 47 | #================================================================ 48 | # Makefile rules for building for specific simulator: bluesim 49 | 50 | include $(REPO)/builds/Resources/Include_verilator.mk 51 | 52 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_FDIV_P8_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D INCLUDE_FDIV \ 19 | -D INCLUDE_FSQRT \ 20 | -D SHIFT_BARREL \ 21 | -D MULT_SYNTH \ 22 | -D Near_Mem_Caches \ 23 | -D FABRIC64 \ 24 | -D WATCH_TOHOST \ 25 | 26 | # Compilation flags and paths for Melodica 27 | BSC_COMPILATION_FLAGS += \ 28 | -D POSIT \ 29 | -D QUILLS \ 30 | -D INCLUDE_PDIV \ 31 | -D PWIDTH_8 \ 32 | 33 | # For Melodica debug statements 34 | # BSC_COMPILATION_FLAGS += -D RANDOM -D RANDOM_PRINT \ 35 | 36 | # paths to melodica bsv code 37 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF:$(REPO)/Melodica/src_bsv/PtoQ:$(REPO)/Melodica/src_bsv/QtoP 38 | 39 | # Default ISA test 40 | 41 | TEST ?= rv32ui-p-add 42 | 43 | #================================================================ 44 | # Common boilerplate rules 45 | 46 | include $(REPO)/builds/Resources/Include_Common.mk 47 | 48 | #================================================================ 49 | # Makefile rules for building for specific simulator: bluesim 50 | 51 | include $(REPO)/builds/Resources/Include_verilator.mk 52 | 53 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_FDIV_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D INCLUDE_FDIV \ 19 | -D INCLUDE_FSQRT \ 20 | -D SHIFT_BARREL \ 21 | -D MULT_SYNTH \ 22 | -D Near_Mem_Caches \ 23 | -D FABRIC64 \ 24 | -D WATCH_TOHOST \ 25 | 26 | # Default ISA test 27 | 28 | TEST ?= rv32ui-p-add 29 | 30 | #================================================================ 31 | # Common boilerplate rules 32 | 33 | include $(REPO)/builds/Resources/Include_Common.mk 34 | 35 | #================================================================ 36 | # Makefile rules for building for specific simulator: bluesim 37 | 38 | include $(REPO)/builds/Resources/Include_verilator.mk 39 | 40 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_P16_P_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D SHIFT_BARREL \ 19 | -D MULT_SYNTH \ 20 | -D Near_Mem_Caches \ 21 | -D FABRIC64 \ 22 | -D WATCH_TOHOST \ 23 | 24 | # Compilation flags and paths for Melodica 25 | BSC_COMPILATION_FLAGS += \ 26 | -D POSIT \ 27 | -D QUILLS \ 28 | -D ONLY_POSITS \ 29 | 30 | # For Melodica debug statements 31 | # BSC_COMPILATION_FLAGS += -D RANDOM -D RANDOM_PRINT \ 32 | 33 | # paths to melodica bsv code 34 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF:$(REPO)/Melodica/src_bsv/PtoQ:$(REPO)/Melodica/src_bsv/QtoP 35 | 36 | # Default ISA test 37 | 38 | TEST ?= rv32ui-p-add 39 | 40 | #================================================================ 41 | # Common boilerplate rules 42 | 43 | include $(REPO)/builds/Resources/Include_Common.mk 44 | 45 | #================================================================ 46 | # Makefile rules for building for specific simulator: bluesim 47 | 48 | include $(REPO)/builds/Resources/Include_verilator.mk 49 | 50 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_P16_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D SHIFT_BARREL \ 19 | -D MULT_SYNTH \ 20 | -D Near_Mem_Caches \ 21 | -D FABRIC64 \ 22 | -D WATCH_TOHOST \ 23 | 24 | # Compilation flags and paths for Melodica 25 | BSC_COMPILATION_FLAGS += \ 26 | -D POSIT \ 27 | -D QUILLS \ 28 | 29 | # For Melodica debug statements 30 | # BSC_COMPILATION_FLAGS += -D RANDOM -D RANDOM_PRINT \ 31 | 32 | # paths to melodica bsv code 33 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF:$(REPO)/Melodica/src_bsv/PtoQ:$(REPO)/Melodica/src_bsv/QtoP 34 | 35 | # Default ISA test 36 | 37 | TEST ?= rv32ui-p-add 38 | 39 | #================================================================ 40 | # Common boilerplate rules 41 | 42 | include $(REPO)/builds/Resources/Include_Common.mk 43 | 44 | #================================================================ 45 | # Makefile rules for building for specific simulator: bluesim 46 | 47 | include $(REPO)/builds/Resources/Include_verilator.mk 48 | 49 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_P24_P_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # Alternative cache organizations: 11 | # Default (no definition for CACHES) L1 only, write-through policy 12 | # Define CACHES=WB_L1 L1 only, with write-back policy 13 | 14 | # ================================================================ 15 | # RISC-V config macros passed into Bluespec 'bsc' compiler 16 | 17 | BSC_COMPILATION_FLAGS += \ 18 | -D RV32 \ 19 | -D ISA_PRIV_M -D ISA_PRIV_U \ 20 | -D SV32 \ 21 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 22 | -D SHIFT_BARREL \ 23 | -D MULT_SYNTH \ 24 | -D Near_Mem_Caches \ 25 | -D FABRIC64 \ 26 | -D WATCH_TOHOST \ 27 | 28 | # Compilation flags and paths for Melodica 29 | BSC_COMPILATION_FLAGS += \ 30 | -D POSIT \ 31 | -D QUILLS \ 32 | -D ONLY_POSITS \ 33 | 34 | # For Melodica debug statements 35 | # BSC_COMPILATION_FLAGS += -D RANDOM -D RANDOM_PRINT \ 36 | 37 | # paths to melodica bsv code 38 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF:$(REPO)/Melodica/src_bsv/PtoQ:$(REPO)/Melodica/src_bsv/QtoP 39 | 40 | # Default ISA test 41 | 42 | TEST ?= rv32ui-p-add 43 | 44 | #================================================================ 45 | # Common boilerplate rules 46 | 47 | include $(REPO)/builds/Resources/Include_Common.mk 48 | 49 | #================================================================ 50 | # Makefile rules for building for specific simulator: bluesim 51 | 52 | include $(REPO)/builds/Resources/Include_verilator.mk 53 | 54 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_P24_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # Alternative cache organizations: 11 | # Default (no definition for CACHES) L1 only, write-through policy 12 | # Define CACHES=WB_L1 L1 only, with write-back policy 13 | 14 | # ================================================================ 15 | # RISC-V config macros passed into Bluespec 'bsc' compiler 16 | 17 | BSC_COMPILATION_FLAGS += \ 18 | -D RV32 \ 19 | -D ISA_PRIV_M -D ISA_PRIV_U \ 20 | -D SV32 \ 21 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 22 | -D SHIFT_BARREL \ 23 | -D MULT_SYNTH \ 24 | -D Near_Mem_Caches \ 25 | -D FABRIC64 \ 26 | -D WATCH_TOHOST \ 27 | 28 | # Compilation flags and paths for Melodica 29 | BSC_COMPILATION_FLAGS += \ 30 | -D POSIT \ 31 | -D QUILLS \ 32 | 33 | # For Melodica debug statements 34 | # BSC_COMPILATION_FLAGS += -D RANDOM -D RANDOM_PRINT \ 35 | 36 | # paths to melodica bsv code 37 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF:$(REPO)/Melodica/src_bsv/PtoQ:$(REPO)/Melodica/src_bsv/QtoP 38 | 39 | # Default ISA test 40 | 41 | TEST ?= rv32ui-p-add 42 | 43 | #================================================================ 44 | # Common boilerplate rules 45 | 46 | include $(REPO)/builds/Resources/Include_Common.mk 47 | 48 | #================================================================ 49 | # Makefile rules for building for specific simulator: bluesim 50 | 51 | include $(REPO)/builds/Resources/Include_verilator.mk 52 | 53 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_P32_P_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D SHIFT_BARREL \ 19 | -D MULT_SYNTH \ 20 | -D Near_Mem_Caches \ 21 | -D FABRIC64 \ 22 | -D WATCH_TOHOST \ 23 | 24 | # Compilation flags and paths for Melodica 25 | BSC_COMPILATION_FLAGS += \ 26 | -D POSIT \ 27 | -D QUILLS \ 28 | -D ONLY_POSITS \ 29 | 30 | # For Melodica debug statements 31 | # BSC_COMPILATION_FLAGS += -D RANDOM -D RANDOM_PRINT \ 32 | 33 | # paths to melodica bsv code 34 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF:$(REPO)/Melodica/src_bsv/PtoQ:$(REPO)/Melodica/src_bsv/QtoP 35 | 36 | # Default ISA test 37 | 38 | TEST ?= rv32ui-p-add 39 | 40 | #================================================================ 41 | # Common boilerplate rules 42 | 43 | include $(REPO)/builds/Resources/Include_Common.mk 44 | 45 | #================================================================ 46 | # Makefile rules for building for specific simulator: bluesim 47 | 48 | include $(REPO)/builds/Resources/Include_verilator.mk 49 | 50 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_P32_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D SHIFT_BARREL \ 19 | -D MULT_SYNTH \ 20 | -D Near_Mem_Caches \ 21 | -D FABRIC64 \ 22 | -D WATCH_TOHOST \ 23 | 24 | # Compilation flags and paths for Melodica 25 | BSC_COMPILATION_FLAGS += \ 26 | -D POSIT \ 27 | 28 | # paths to melodica bsv code 29 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF 30 | 31 | # Default ISA test 32 | 33 | TEST ?= rv32ui-p-add 34 | 35 | #================================================================ 36 | # Common boilerplate rules 37 | 38 | include $(REPO)/builds/Resources/Include_Common.mk 39 | 40 | #================================================================ 41 | # Makefile rules for building for specific simulator: bluesim 42 | 43 | include $(REPO)/builds/Resources/Include_verilator.mk 44 | 45 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_P8_P_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D SHIFT_BARREL \ 19 | -D MULT_SYNTH \ 20 | -D Near_Mem_Caches \ 21 | -D FABRIC64 \ 22 | -D WATCH_TOHOST \ 23 | 24 | # Compilation flags and paths for Melodica 25 | BSC_COMPILATION_FLAGS += \ 26 | -D POSIT \ 27 | -D QUILLS \ 28 | -D ONLY_POSITS \ 29 | -D PWIDTH_8 \ 30 | 31 | # For Melodica debug statements 32 | # BSC_COMPILATION_FLAGS += -D RANDOM -D RANDOM_PRINT \ 33 | 34 | # paths to melodica bsv code 35 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF:$(REPO)/Melodica/src_bsv/PtoQ:$(REPO)/Melodica/src_bsv/QtoP 36 | 37 | # Default ISA test 38 | 39 | TEST ?= rv32ui-p-add 40 | 41 | #================================================================ 42 | # Common boilerplate rules 43 | 44 | include $(REPO)/builds/Resources/Include_Common.mk 45 | 46 | #================================================================ 47 | # Makefile rules for building for specific simulator: bluesim 48 | 49 | include $(REPO)/builds/Resources/Include_verilator.mk 50 | 51 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_P8_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D SHIFT_BARREL \ 19 | -D MULT_SYNTH \ 20 | -D Near_Mem_Caches \ 21 | -D FABRIC64 \ 22 | -D WATCH_TOHOST \ 23 | 24 | # Compilation flags and paths for Melodica 25 | BSC_COMPILATION_FLAGS += \ 26 | -D POSIT \ 27 | -D QUILLS \ 28 | -D PWIDTH_8 \ 29 | 30 | # For Melodica debug statements 31 | # BSC_COMPILATION_FLAGS += -D RANDOM -D RANDOM_PRINT \ 32 | 33 | # paths to melodica bsv code 34 | CUSTOM_DIRS = ./src_bsv:$(REPO)/Melodica/src_bsv:$(REPO)/Melodica/src_bsv/common:$(REPO)/Melodica/src_bsv/lib:$(REPO)/Melodica/src_bsv/FtoP:$(REPO)/Melodica/src_bsv/Fused_Op:$(REPO)/Melodica/src_bsv/PtoF:$(REPO)/Melodica/src_bsv/PtoQ:$(REPO)/Melodica/src_bsv/QtoP 35 | 36 | # Default ISA test 37 | 38 | TEST ?= rv32ui-p-add 39 | 40 | #================================================================ 41 | # Common boilerplate rules 42 | 43 | include $(REPO)/builds/Resources/Include_Common.mk 44 | 45 | #================================================================ 46 | # Makefile rules for building for specific simulator: bluesim 47 | 48 | include $(REPO)/builds/Resources/Include_verilator.mk 49 | 50 | -------------------------------------------------------------------------------- /builds/RV32ACFIMSU_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACFIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_C \ 18 | -D SHIFT_BARREL \ 19 | -D MULT_SYNTH \ 20 | -D Near_Mem_Caches \ 21 | -D FABRIC64 \ 22 | -D WATCH_TOHOST \ 23 | 24 | # Default ISA test 25 | 26 | TEST ?= rv32ui-p-add 27 | 28 | #================================================================ 29 | # Common boilerplate rules 30 | 31 | include $(REPO)/builds/Resources/Include_Common.mk 32 | 33 | #================================================================ 34 | # Makefile rules for building for specific simulator: bluesim 35 | 36 | include $(REPO)/builds/Resources/Include_verilator.mk 37 | 38 | -------------------------------------------------------------------------------- /builds/RV32ACIMSU_verilator/Makefile: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # *** DO NOT EDIT! *** 4 | # *** This file is program-generated, not hand-written. *** 5 | # ================================================================ 6 | 7 | REPO ?= ../.. 8 | ARCH ?= RV32ACIMSU 9 | 10 | # ================================================================ 11 | # RISC-V config macros passed into Bluespec 'bsc' compiler 12 | 13 | BSC_COMPILATION_FLAGS += \ 14 | -D RV32 \ 15 | -D ISA_PRIV_M -D ISA_PRIV_U -D ISA_PRIV_S \ 16 | -D SV32 \ 17 | -D ISA_I -D ISA_M -D ISA_A -D ISA_C \ 18 | -D SHIFT_BARREL \ 19 | -D MULT_SYNTH \ 20 | -D Near_Mem_Caches \ 21 | -D FABRIC64 \ 22 | -D WATCH_TOHOST \ 23 | 24 | # Default ISA test 25 | 26 | TEST ?= rv32ui-p-add 27 | 28 | #================================================================ 29 | # Common boilerplate rules 30 | 31 | include $(REPO)/builds/Resources/Include_Common.mk 32 | 33 | #================================================================ 34 | # Makefile rules for building for specific simulator: bluesim 35 | 36 | include $(REPO)/builds/Resources/Include_verilator.mk 37 | 38 | -------------------------------------------------------------------------------- /builds/Resources/Include_bluesim.mk: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved 4 | 5 | # This file is not a standalone Makefile, but 'include'd by other Makefiles 6 | 7 | # ================================================================ 8 | # Compile Bluesim intermediate files from BSV sources (needs Bluespec 'bsc' compiler) 9 | 10 | TMP_DIRS = -bdir build_dir -simdir build_dir -info-dir build_dir 11 | 12 | build_dir: 13 | mkdir -p $@ 14 | 15 | .PHONY: compile 16 | compile: build_dir 17 | @echo "INFO: Re-compiling Core (CPU, Caches)" 18 | bsc -u -elab -sim $(TMP_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $(TOPFILE) 19 | @echo "INFO: Re-compiled Core (CPU, Caches)" 20 | 21 | # ================================================================ 22 | # Compile and link Bluesim intermediate files into a Bluesim executable 23 | 24 | SIM_EXE_FILE = exe_HW_sim 25 | 26 | BSC_C_FLAGS += \ 27 | -Xl -v \ 28 | -Xc -O3 -Xc++ -O3 \ 29 | 30 | # You may have to remove this line above 31 | # for Bluespec_2019.05.beta2-debian9stretch-amd64 32 | # -Xc++ -D_GLIBCXX_USE_CXX11_ABI=0 \ 33 | 34 | .PHONY: simulator 35 | simulator: 36 | @echo "INFO: linking bsc-compiled objects into Bluesim executable" 37 | bsc -sim -parallel-sim-link 8 \ 38 | $(TMP_DIRS) \ 39 | -e $(TOPMODULE) -o ./$(SIM_EXE_FILE) \ 40 | $(BSC_C_FLAGS) \ 41 | $(REPO)/src_Testbench/Top/C_Imported_Functions.c 42 | @echo "INFO: linked bsc-compiled objects into Bluesim executable" 43 | 44 | # ================================================================ 45 | -------------------------------------------------------------------------------- /builds/Resources/Include_iverilog.mk: -------------------------------------------------------------------------------- 1 | ### -*-Makefile-*- 2 | 3 | # Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved 4 | 5 | # This file is not a standalone Makefile, but 'include'd by other Makefiles 6 | 7 | # ================================================================ 8 | # Generate Verilog RTL from BSV sources (needs Bluespec 'bsc' compiler) 9 | 10 | RTL_GEN_DIRS = -vdir Sim_RTL -bdir build_dir -info-dir build_dir 11 | 12 | build_dir: 13 | mkdir -p $@ 14 | 15 | Sim_RTL: 16 | mkdir -p $@ 17 | 18 | .PHONY: compile 19 | compile: build_dir Sim_RTL 20 | @echo "INFO: Verilog RTL generation ..." 21 | bsc -u -elab -verilog $(RTL_GEN_DIRS) -D IVERILOG $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $(TOPFILE) 22 | @echo "INFO: Verilog RTL generation finished" 23 | 24 | # ================================================================ 25 | # Compile and link Verilog RTL sources into an iverilog executable 26 | 27 | VSIM ?= iverilog 28 | SIM_EXE_FILE = exe_HW_sim 29 | 30 | .PHONY: simulator 31 | simulator: 32 | @echo INFO: iVerilog linking start ... 33 | bsc -verilog -vsim $(VSIM) -keep-fires \ 34 | $(RTL_GEN_DIRS) \ 35 | -p $(BSC_PATH) \ 36 | -e $(TOPMODULE) -o $(SIM_EXE_FILE) \ 37 | $(BSC_C_FLAGS) \ 38 | $(REPO)/src_Testbench/Top/C_Imported_Functions.c 39 | @echo INFO: iVerilog linking finished 40 | 41 | # iverilog -o ./$(SIM_EXE_FILE) \ 42 | # -y Sim_RTL \ 43 | # -y $(REPO)/src_bsc_lib_RTL \ 44 | # -DTOP=$(TOPMODULE) \ 45 | # $(REPO)/src_bsc_lib_RTL/main.v 46 | 47 | # ================================================================ 48 | -------------------------------------------------------------------------------- /builds/Resources/Verilator_resources/sed_script.txt: -------------------------------------------------------------------------------- 1 | s/\$imported_// 2 | -------------------------------------------------------------------------------- /builds/Resources/Verilator_resources/verilator_config.vlt: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved 2 | 3 | // Flags for verilator 4 | 5 | `verilator_config 6 | lint_off -msg WIDTH 7 | lint_off -msg CASEINCOMPLETE 8 | lint_off -msg STMTDLY 9 | lint_off -msg INITIALDLY 10 | lint_off -msg UNSIGNED 11 | lint_off -msg CMPCONST 12 | `verilog 13 | -------------------------------------------------------------------------------- /builds/release-rtl.tar.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HPC-Lab-IITB/Clarinet/0bf84b2db46a1a2a0c0575f94de50aead2b5f1b6/builds/release-rtl.tar.gz -------------------------------------------------------------------------------- /src_Core/BSV_Additional_Libs/CreditCounter.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2015-2019 Bluespec, Inc., All Rights Reserved 2 | // Author: Rishiyur S. Nikhil 3 | 4 | // A "credit counter" which can be incremented and decremented concurrently. 5 | 6 | package CreditCounter; 7 | 8 | // ================================================================ 9 | // BSV library imports 10 | 11 | import Cur_Cycle :: *; 12 | 13 | // ================================================================ 14 | // Interface 15 | 16 | interface CreditCounter_IFC #(numeric type w); 17 | // Current value of internal count 18 | method UInt #(w) value; 19 | 20 | // Increment internal count 21 | method Action incr; 22 | 23 | // Decrement internal count 24 | method Action decr; 25 | 26 | // Clear internal count to 0 27 | method Action clear; 28 | endinterface 29 | 30 | // ================================================================ 31 | // Module implementation 32 | // Scheduling: value < incr < decr < clear 33 | 34 | module mkCreditCounter (CreditCounter_IFC #(w)); 35 | 36 | Reg #(UInt #(w)) crg [3] <- mkCReg (3, 0); 37 | 38 | method UInt #(w) value = crg [1]; 39 | 40 | method Action incr if (crg [0] != maxBound); 41 | if (crg [0] == maxBound) begin 42 | $display ("%0d: ERROR: CreditCounter: overflow", cur_cycle); 43 | $finish (1); // Assertion failure 44 | end 45 | crg [0] <= crg [0] + 1; 46 | endmethod 47 | 48 | method Action decr () if (crg [1] != 0); 49 | if (crg [1] == 0) begin 50 | $display ("%0d: ERROR: CreditCounter: underflow", cur_cycle); 51 | $finish (1); // Assertion failure 52 | end 53 | crg [1] <= crg [1] - 1; 54 | endmethod 55 | 56 | method Action clear; 57 | crg [2] <= 0; 58 | endmethod 59 | endmodule 60 | 61 | // ================================================================ 62 | 63 | endpackage 64 | -------------------------------------------------------------------------------- /src_Core/BSV_Additional_Libs/Cur_Cycle.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2013-2019 Bluespec, Inc. All Rights Reserved. 2 | 3 | package Cur_Cycle; 4 | 5 | // ================================================================ 6 | // A convenience function to return the current cycle number during BSV simulations 7 | 8 | ActionValue #(Bit #(32)) cur_cycle = actionvalue 9 | Bit #(32) t <- $stime; 10 | return t / 10; 11 | endactionvalue; 12 | 13 | // ================================================================ 14 | 15 | endpackage 16 | -------------------------------------------------------------------------------- /src_Core/CPU/FPU_Types.bsv: -------------------------------------------------------------------------------- 1 | // New types definition file created to capture common definitions 2 | // used by a FPU and a posit compute unit. Moved from FPU.bsv 3 | 4 | package FPU_Types; 5 | 6 | import FShow :: *; 7 | import ISA_Decls :: *; 8 | import FloatingPoint :: *; 9 | `ifdef POSIT 10 | import Posit_Numeric_Types :: *; 11 | `endif 12 | 13 | typedef FloatingPoint#(11,52) FDouble; 14 | typedef FloatingPoint#(8,23) FSingle; 15 | 16 | typedef union tagged { 17 | FDouble D; 18 | FSingle S; 19 | `ifdef POSIT 20 | WordPL P; 21 | `endif 22 | } FloatU deriving(Bits,Eq,FShow); 23 | 24 | typedef Tuple5#( FloatU,FloatU,FloatU,RoundMode,FpuOp) Fpu_Req; 25 | typedef Tuple2#( FloatU, FloatingPoint::Exception ) Fpu_Rsp; 26 | 27 | `ifdef ISA_D 28 | typedef Tuple2#( FDouble, FloatingPoint::Exception ) FpuR; 29 | `else 30 | typedef Tuple2#( FSingle, FloatingPoint::Exception ) FpuR; 31 | `endif 32 | 33 | endpackage : FPU_Types 34 | -------------------------------------------------------------------------------- /src_Core/Cache_Config/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: help 2 | help: 3 | @echo "Running an individual 'make ' will generate a BSV file" 4 | @echo "containing cache type, constant and function declarations" 5 | @echo "using config info specified in _args.yaml file" 6 | @echo "(generated BSV package/file name, cache size, associativity," 7 | @echo " basic cache word size, line size, phys addr size in bits)." 8 | @echo "" 9 | @echo "The generated BSV files are imported by BSV cache codes." 10 | @echo "" 11 | @echo "Running 'make all' will do it for each of the standard targets in this dir." 12 | @echo "" 13 | @echo "For other configs, create your own yaml files similar to" 14 | @echo "the yaml files in this directory," 15 | @echo "then run the Python program Gen_BSV_Cache_Decls.py on them." 16 | 17 | .PHONY: all 18 | all: RV32_4KB_1way RV32_8KB_2way RV32_Sv32_4KB_1way RV32_Sv32_8KB_2way \ 19 | RV64_4KB_1way RV64_8KB_2way RV64_Sv39_4KB_1way RV64_Sv39_8KB_2way 20 | 21 | # ================================================================ 22 | # For RV32 23 | 24 | .PHONY: RV32_4KB_1way 25 | RV32_4KB_1way: 26 | ./Gen_BSV_Cache_Decls.py --yaml_file RV32_4KB_1way_args.yaml 27 | 28 | .PHONY: RV32_Sv32_4KB_1way 29 | RV32_Sv32_4KB_1way: 30 | ./Gen_BSV_Cache_Decls.py --yaml_file RV32_Sv32_4KB_1way_args.yaml 31 | 32 | .PHONY: RV32_8KB_2way 33 | RV32_8KB_2way: 34 | ./Gen_BSV_Cache_Decls.py --yaml_file RV32_8KB_2way_args.yaml 35 | 36 | .PHONY: RV32_Sv32_8KB_2way 37 | RV32_Sv32_8KB_2way: 38 | ./Gen_BSV_Cache_Decls.py --yaml_file RV32_Sv32_8KB_2way_args.yaml 39 | 40 | # ================================================================ 41 | # For RV64 42 | 43 | .PHONY: RV64_4KB_1way 44 | RV64_4KB_1way: 45 | ./Gen_BSV_Cache_Decls.py --yaml_file RV64_4KB_1way_args.yaml 46 | 47 | .PHONY: RV64_Sv39_4KB_1way 48 | RV64_Sv39_4KB_1way: 49 | ./Gen_BSV_Cache_Decls.py --yaml_file RV64_Sv39_4KB_1way_args.yaml 50 | 51 | .PHONY: RV64_8KB_2way 52 | RV64_8KB_2way: 53 | ./Gen_BSV_Cache_Decls.py --yaml_file RV64_8KB_2way_args.yaml 54 | 55 | .PHONY: RV64_Sv39_8KB_2way 56 | RV64_Sv39_8KB_2way: 57 | ./Gen_BSV_Cache_Decls.py --yaml_file RV64_Sv39_8KB_2way_args.yaml 58 | 59 | # ================================================================ 60 | 61 | clean: 62 | rm -r -f *~ *.bsv 63 | -------------------------------------------------------------------------------- /src_Core/Cache_Config/README.txt: -------------------------------------------------------------------------------- 1 | This directory contains a Python program 'Gen_BSV_Cache_Decls.py' 2 | 3 | Inputs: 4 | Top-level specs for a cache, such as size, associativity etc. 5 | Inputs are givein in a YAML file, and can be over-ridden on the command-line. 6 | Run '$ Gen_BSV_Cache_Decls.py --help' for all options. 7 | 8 | Output: 9 | 10 | Generates a BSV package with numerous type, value and function 11 | declarations derived from the top-level specs, and imported into 12 | BSV code for the cache implementations. 13 | -------------------------------------------------------------------------------- /src_Core/Cache_Config/RV32_4KB_1way_args.yaml: -------------------------------------------------------------------------------- 1 | bsv_package_name: Cache_Decls_RV32_4KB_1way 2 | Bits_per_PA: 32 3 | KB_per_Cache: 4 4 | Bits_per_CWord: 64 5 | CWords_per_CLine: 8 6 | Ways_per_CSet: 1 7 | -------------------------------------------------------------------------------- /src_Core/Cache_Config/RV32_8KB_2way_args.yaml: -------------------------------------------------------------------------------- 1 | # Arguments for Gen_BSV_Cache_Decls.py for RV32 (no Supervisor mode, i.e., no Sv32) 2 | bsv_package_name: Cache_Decls_RV32_8KB_2way 3 | Bits_per_PA: 32 4 | KB_per_Cache: 8 5 | Bits_per_CWord: 64 6 | CWords_per_CLine: 8 7 | Ways_per_CSet: 2 8 | -------------------------------------------------------------------------------- /src_Core/Cache_Config/RV32_Sv32_4KB_1way_args.yaml: -------------------------------------------------------------------------------- 1 | # Arguments for Gen_BSV_Cache_Decls.py for RV32.sv32 2 | bsv_package_name: Cache_Decls_RV32_Sv32_4KB_1way 3 | Bits_per_PA: 34 4 | KB_per_Cache: 4 5 | Bits_per_CWord: 64 6 | CWords_per_CLine: 8 7 | Ways_per_CSet: 1 8 | -------------------------------------------------------------------------------- /src_Core/Cache_Config/RV32_Sv32_8KB_2way_args.yaml: -------------------------------------------------------------------------------- 1 | # Arguments for Gen_BSV_Cache_Decls.py for RV32.sv32 2 | bsv_package_name: Cache_Decls_RV32_Sv32_8KB_2way 3 | Bits_per_PA: 34 4 | KB_per_Cache: 8 5 | Bits_per_CWord: 64 6 | CWords_per_CLine: 8 7 | Ways_per_CSet: 2 8 | -------------------------------------------------------------------------------- /src_Core/Cache_Config/RV64_4KB_1way_args.yaml: -------------------------------------------------------------------------------- 1 | # Arguments for Gen_BSV_Cache_Decls.py for RV64 2 | bsv_package_name: Cache_Decls_RV64_4KB_1way 3 | Bits_per_PA: 64 4 | KB_per_Cache: 4 5 | Bits_per_CWord: 64 6 | CWords_per_CLine: 8 7 | Ways_per_CSet: 1 8 | -------------------------------------------------------------------------------- /src_Core/Cache_Config/RV64_8KB_2way_args.yaml: -------------------------------------------------------------------------------- 1 | # Arguments for Gen_BSV_Cache_Decls.py for RV64 2 | bsv_package_name: Cache_Decls_RV64_8KB_2way 3 | Bits_per_PA: 64 4 | KB_per_Cache: 8 5 | Bits_per_CWord: 64 6 | CWords_per_CLine: 8 7 | Ways_per_CSet: 2 8 | -------------------------------------------------------------------------------- /src_Core/Cache_Config/RV64_Sv39_4KB_1way_args.yaml: -------------------------------------------------------------------------------- 1 | # Arguments for Gen_BSV_Cache_Decls.py for RV64.sv39 2 | bsv_package_name: Cache_Decls_RV64_Sv39_4KB_1way 3 | Bits_per_PA: 64 4 | KB_per_Cache: 4 5 | Bits_per_CWord: 64 6 | CWords_per_CLine: 8 7 | Ways_per_CSet: 1 8 | -------------------------------------------------------------------------------- /src_Core/Cache_Config/RV64_Sv39_8KB_2way_args.yaml: -------------------------------------------------------------------------------- 1 | # Arguments for Gen_BSV_Cache_Decls.py for RV64.sv39 2 | bsv_package_name: Cache_Decls_RV64_Sv39_8KB_2way 3 | Bits_per_PA: 64 4 | KB_per_Cache: 8 5 | Bits_per_CWord: 64 6 | CWords_per_CLine: 8 7 | Ways_per_CSet: 2 8 | -------------------------------------------------------------------------------- /src_Core/Debug_Module/DM_CPU_Req_Rsp.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved. 2 | 3 | package DM_CPU_Req_Rsp; 4 | 5 | // ================================================================ 6 | // This package defines types for register access request and response 7 | 8 | // ================================================================ 9 | // BSV library imports 10 | 11 | // None 12 | 13 | // ================================================================ 14 | // Project imports 15 | 16 | // None 17 | 18 | // ================================================================ 19 | // Requests and responses 20 | 21 | typedef struct { 22 | Bool write; 23 | Bit #(a) address; 24 | Bit #(d) data; 25 | } DM_CPU_Req #(numeric type a, numeric type d) 26 | deriving (Bits, Eq, FShow); 27 | 28 | typedef struct { 29 | Bool ok; 30 | Bit #(d) data; 31 | } DM_CPU_Rsp #(numeric type d) 32 | deriving (Bits, Eq, FShow); 33 | 34 | // ================================================================ 35 | 36 | endpackage 37 | -------------------------------------------------------------------------------- /src_Core/Near_Mem_IO/README.txt: -------------------------------------------------------------------------------- 1 | Notes: 2 | 3 | - 'Near_Mem_IO' is for memory-mapped IO near the CPU. It includes: 4 | - CLINT (Core Local Interruptor): 5 | - MSIP: for software interrupts 6 | - MTIME and MTIMECMP locations: to read TIME, and to generate timer interrupts 7 | - Other: 8 | - Example: configs for caches, alternate FPUs, ... 9 | 10 | - Near_Mem_IO_AXI4.bsv: current version, using AXI4 interfaces, and 11 | sitting as a slave on the core-local AXI4 interconnect. 12 | 13 | - Near_Mem_IO.bsv: older version that used to be hooked directly into 14 | MMU_Cache, using it's own Req/Rsp packet data type. 15 | Now obsolete; not used. 16 | -------------------------------------------------------------------------------- /src_Core/Near_Mem_VM_WB_L1/Cache_Decls.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved. 2 | 3 | package Cache_Decls; 4 | 5 | // ================================================================ 6 | // This is just a convenience package, encapsulating the selection of 7 | // a specific set of cache declarations corresponding to a particular 8 | // cache config. 9 | 10 | // ================================================================ 11 | 12 | `ifdef RV32 13 | `ifdef SV32 14 | import Cache_Decls_RV32_Sv32_8KB_2way :: *; 15 | export Cache_Decls_RV32_Sv32_8KB_2way :: *; 16 | `else 17 | import Cache_Decls_RV32_8KB_2way :: *; 18 | export Cache_Decls_RV32_8KB_2way :: *; 19 | `endif 20 | `endif 21 | 22 | `ifdef RV64 23 | `ifdef SV39 24 | import Cache_Decls_RV64_Sv39_8KB_2way :: *; 25 | export Cache_Decls_RV64_Sv39_8KB_2way :: *; 26 | `else 27 | import Cache_Decls_RV64_8KB_2way :: *; 28 | export Cache_Decls_RV64_8KB_2way :: *; 29 | `endif 30 | `endif 31 | 32 | endpackage 33 | -------------------------------------------------------------------------------- /src_Core/Near_Mem_VM_WB_L1_L2/Cache_Decls.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved. 2 | 3 | package Cache_Decls; 4 | 5 | // ================================================================ 6 | // This is just a convenience package, encapsulating the selection of 7 | // a specific set of cache declarations corresponding to a particular 8 | // cache config. 9 | 10 | // ================================================================ 11 | 12 | `ifdef RV32 13 | `ifdef SV32 14 | import Cache_Decls_RV32_Sv32_8KB_2way :: *; 15 | export Cache_Decls_RV32_Sv32_8KB_2way :: *; 16 | `else 17 | import Cache_Decls_RV32_8KB_2way :: *; 18 | export Cache_Decls_RV32_8KB_2way :: *; 19 | `endif 20 | `endif 21 | 22 | `ifdef RV64 23 | `ifdef SV39 24 | import Cache_Decls_RV64_Sv39_8KB_2way :: *; 25 | export Cache_Decls_RV64_Sv39_8KB_2way :: *; 26 | `else 27 | import Cache_Decls_RV64_8KB_2way :: *; 28 | export Cache_Decls_RV64_8KB_2way :: *; 29 | `endif 30 | `endif 31 | 32 | endpackage 33 | -------------------------------------------------------------------------------- /src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/LICENSE_RISCY_OOO: -------------------------------------------------------------------------------- 1 | Copyright (c) 2017, 2018 Massachusetts Institute of Technology 2 | 3 | Permission is hereby granted, free of charge, to any person 4 | obtaining a copy of this software and associated documentation 5 | files (the "Software"), to deal in the Software without 6 | restriction, including without limitation the rights to use, copy, 7 | modify, merge, publish, distribute, sublicense, and/or sell copies 8 | of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be 12 | included in all copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 15 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 16 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 17 | NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 18 | BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 19 | ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/LLCache_Aux.bsv: -------------------------------------------------------------------------------- 1 | // These are some minimal excerpts of code from certain files (noted 2 | // below) of Toooba/RISCY-OOO needed for LLCache.bsv. 3 | 4 | // The files named here themselves import other files which, in turn, 5 | // import more files, with a large transitive closure. These excerpts 6 | // are the minimum defs actually needed by LLCache, and avoid 7 | // importing all those otherwise unnecessary files. 8 | 9 | package LLCache_Aux; 10 | 11 | `include "ProcConfig.bsv" 12 | 13 | // ---------------- 14 | // From RISCY-OOO 15 | 16 | import Types::*; 17 | import ProcTypes::*; 18 | import CCTypes::*; 19 | 20 | // ---------------- 21 | // From Piccolo/Flute 22 | 23 | import Near_Mem_IFC :: *; // For Wd_Id_Dma 24 | 25 | // ================================================================ 26 | // From L1CoCache.bsv 27 | 28 | typedef TMul#(CoreNum, 2) L1Num; 29 | typedef `LOG_L1_WAYS LgL1WayNum; 30 | typedef Bit#(LgL1WayNum) L1Way; 31 | 32 | // ================================================================ 33 | // Id for LLC's coherent cache port 34 | // This is simply the AXI4 awid/arid 35 | 36 | typedef Bit #(Wd_Id_Dma) LLCDmaReqId; 37 | 38 | // ================================================================ 39 | 40 | endpackage 41 | -------------------------------------------------------------------------------- /src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/procs/lib/MemoryTypes.bsv: -------------------------------------------------------------------------------- 1 | 2 | // Copyright (c) 2017 Massachusetts Institute of Technology 3 | // 4 | // Permission is hereby granted, free of charge, to any person 5 | // obtaining a copy of this software and associated documentation 6 | // files (the "Software"), to deal in the Software without 7 | // restriction, including without limitation the rights to use, copy, 8 | // modify, merge, publish, distribute, sublicense, and/or sell copies 9 | // of the Software, and to permit persons to whom the Software is 10 | // furnished to do so, subject to the following conditions: 11 | // 12 | // The above copyright notice and this permission notice shall be 13 | // included in all copies or substantial portions of the Software. 14 | // 15 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 | // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 | // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 18 | // NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 19 | // BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 20 | // ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 | // CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | // SOFTWARE. 23 | 24 | `include "ProcConfig.bsv" 25 | import Types::*; 26 | import Vector::*; 27 | import ClientServer::*; 28 | 29 | // typedefs for mem access performed by processor 30 | // cache line is defined in CacheUtils.bsv 31 | 32 | typedef Data MemResp; 33 | 34 | typedef enum{Ld, St, Lr, Sc, Amo} MemOp deriving(Eq,Bits,FShow); // add more ops 35 | 36 | Bit#(3) memB = 3'b000; 37 | Bit#(3) memH = 3'b001; 38 | Bit#(3) memW = 3'b010; 39 | Bit#(3) memD = 3'b011; 40 | Bit#(3) memBU = 3'b100; 41 | Bit#(3) memHU = 3'b101; 42 | Bit#(3) memWU = 3'b110; 43 | 44 | -------------------------------------------------------------------------------- /src_Core/Near_Mem_VM_WT_L1/Cache_Decls.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved. 2 | 3 | package Cache_Decls; 4 | 5 | // ================================================================ 6 | // This is just a convenience package, encapsulating the selection of 7 | // a specific set of cache declarations corresponding to a particular 8 | // cache config. 9 | 10 | // ================================================================ 11 | 12 | `ifdef RV32 13 | `ifdef SV32 14 | import Cache_Decls_RV32_Sv32_8KB_2way :: *; 15 | export Cache_Decls_RV32_Sv32_8KB_2way :: *; 16 | `else 17 | import Cache_Decls_RV32_8KB_2way :: *; 18 | export Cache_Decls_RV32_8KB_2way :: *; 19 | `endif 20 | `endif 21 | 22 | `ifdef RV64 23 | `ifdef SV39 24 | import Cache_Decls_RV64_Sv39_8KB_2way :: *; 25 | export Cache_Decls_RV64_Sv39_8KB_2way :: *; 26 | `else 27 | import Cache_Decls_RV64_8KB_2way :: *; 28 | export Cache_Decls_RV64_8KB_2way :: *; 29 | `endif 30 | `endif 31 | 32 | endpackage 33 | -------------------------------------------------------------------------------- /src_Core/Near_Mem_VM_WT_L1/MMU_Cache_Common.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved. 2 | 3 | package MMU_Cache_Common; 4 | 5 | // ================================================================ 6 | // Types etc. shared by multiple modules in MMU_Cache complex. 7 | 8 | // ================================================================ 9 | // Project imports 10 | 11 | import ISA_Decls :: *; 12 | import Fabric_Defs :: *; 13 | 14 | // ================================================================ 15 | // Near_Mem opcodes 16 | 17 | typedef enum { CACHE_LD 18 | , CACHE_ST 19 | `ifdef ISA_A 20 | , CACHE_AMO 21 | `endif 22 | } CacheOp 23 | deriving (Bits, Eq, FShow); 24 | 25 | // ================================================================ 26 | // Check if addr is aligned 27 | 28 | function Bool fn_is_aligned (Bit #(3) f3, Bit #(n) addr); 29 | return ( (f3 [1:0] == 2'b00) // B, BU 30 | || ((f3 [1:0] == 2'b01) && (addr [0] == 1'b0)) // H, HU 31 | || ((f3 [1:0] == 2'b10) && (addr [1:0] == 2'b00)) // W, WU 32 | || ((f3 [1:0] == 2'b11) && (addr [2:0] == 3'b000)) // D 33 | ); 34 | endfunction 35 | 36 | // ================================================================ 37 | // Convert width of an address from PA to Fabric_Addr 38 | 39 | function Fabric_Addr fn_PA_to_Fabric_Addr (PA pa); 40 | Bit #(TAdd #(Wd_Addr, PA_sz)) fa = zeroExtend (pa); 41 | Integer hi = valueOf (Wd_Addr) - 1; 42 | return fa [hi:0]; 43 | endfunction 44 | 45 | // ================================================================ 46 | 47 | endpackage 48 | -------------------------------------------------------------------------------- /src_Core/PLIC/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2019 Bluespec, Inc. All Rights Reserved 2 | 3 | # Makefile to create Test_PLIC and PLIC into a standalone unit-test executable. 4 | 5 | # Edit the StmtFSM in Test_PLIC to create different tests. 6 | 7 | # ---------------- 8 | 9 | REPO = $(HOME)/GitHub/Flute 10 | 11 | # ---------------- 12 | # Top-level file and module 13 | 14 | TOPFILE ?= $(REPO)/src_Core/PLIC/Test_PLIC.bsv 15 | TOPMODULE ?= mkTest_PLIC 16 | 17 | # ================================================================ 18 | # RISC-V config macros passed into Bluespec 'bsc' compiler 19 | 20 | BSC_COMPILATION_FLAGS += \ 21 | -D RV64 \ 22 | -D ISA_PRIV_M -D ISA_PRIV_U -D ISA_PRIV_S \ 23 | -D SV39 \ 24 | -D ISA_I -D ISA_M -D ISA_A \ 25 | -D SHIFT_BARREL \ 26 | -D MULT_SYNTH \ 27 | -D Near_Mem_Caches \ 28 | -D FABRIC64 \ 29 | 30 | 31 | # ================================================================ 32 | # Common boilerplate rules 33 | 34 | include $(REPO)/builds/Resources/Include_Common.mk 35 | 36 | # ================================================================ 37 | # Makefile rules for building for specific simulator: bluesim 38 | 39 | include $(REPO)/builds/Resources/Include_bluesim.mk 40 | 41 | # ================================================================ 42 | -------------------------------------------------------------------------------- /src_Core/PLIC/PLIC_16_2_7.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2019 Bluespec, Inc. All Rights Reserved 2 | 3 | package PLIC_16_2_7; 4 | 5 | // ================================================================ 6 | // Instantiation of parameterized PLIC to specific parameter values. 7 | // 8 | // ================================================================ 9 | // Bluespec lib imports 10 | 11 | // None 12 | 13 | // ---------------- 14 | // BSV additional libs 15 | 16 | // None 17 | 18 | // ================================================================ 19 | // Project imports 20 | 21 | import SoC_Map :: *; // For N_External_Interrupt_Sources 22 | import PLIC :: *; // For PLIC_IFC, mkPLIC 23 | 24 | // ================================================================ 25 | // PLIC for this core 26 | 27 | typedef 2 PLIC_N_Targets; 28 | typedef 7 PLIC_Max_Priority; 29 | 30 | typedef PLIC_IFC #(N_External_Interrupt_Sources, 31 | PLIC_N_Targets, 32 | PLIC_Max_Priority) PLIC_IFC_16_2_7; 33 | 34 | (* synthesize *) 35 | module mkPLIC_16_2_7 (PLIC_IFC_16_2_7); 36 | let m <- mkPLIC; 37 | return m; 38 | endmodule 39 | 40 | // ================================================================ 41 | 42 | endpackage 43 | -------------------------------------------------------------------------------- /src_Core/RegFiles/CSR_RegFile.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved 2 | 3 | package CSR_RegFile; 4 | 5 | 6 | // ================================================================ 7 | `ifdef CSR_REGFILE_MIN 8 | 9 | // Minimal CSR RegFile: User-mode CSRs, plus just enough M-mode CSRs 10 | // to support traps/interrupts. 11 | 12 | import CSR_RegFile_Min :: *; 13 | export CSR_RegFile_Min :: *; 14 | 15 | // ================================================================ 16 | `else 17 | 18 | // Machine-mode, Supervisor-mode and User-mode CSRs 19 | 20 | import CSR_RegFile_MSU :: *; 21 | export CSR_RegFile_MSU :: *; 22 | 23 | // ================================================================ 24 | `endif 25 | 26 | endpackage 27 | -------------------------------------------------------------------------------- /src_Testbench/Fabrics/Adapters/README.txt: -------------------------------------------------------------------------------- 1 | CAVEAT 2020-07-14: 2 | 3 | These adapters between AXI4 and AXI4_Lite are checked in here for 4 | the record; they may be in working or near-working state, but they 5 | have not been used for some time. They were each developed for some 6 | specific need that seems to have gone away. They are not used in 7 | the standard Piccolo/Flute/Toooba builds. 8 | -------------------------------------------------------------------------------- /src_Testbench/SoC/AXI4_Accel_IFC.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All Rights Reserved. 2 | // Author: Rishiyur S. Nikhil 3 | 4 | package AXI4_Accel_IFC; 5 | 6 | // ================================================================ 7 | // Canonical interface for a accelerator: 8 | // 'init' method to: 9 | // - intialize the accelerator 10 | // - set its place in the address map 11 | // - set an AXI4 TID to be used by the master interface 12 | // 'slave' interface that is used to program the accelerator 13 | // 'master' interface used by the accelerator to read/write memory 14 | 15 | // ================================================================ 16 | // Bluespec library imports 17 | 18 | import RegFile :: *; 19 | import FIFOF :: *; 20 | import GetPut :: *; 21 | import ClientServer :: *; 22 | 23 | // ---------------- 24 | // BSV additional libs 25 | 26 | import Cur_Cycle :: *; 27 | import GetPut_Aux :: *; 28 | import Semi_FIFOF :: *; 29 | 30 | // ================================================================ 31 | // Project imports 32 | 33 | import AXI4_Types :: *; 34 | import Fabric_Defs :: *; 35 | 36 | // ================================================================ 37 | // Interface 38 | 39 | interface AXI4_Accel_IFC; 40 | method Action init (Bit# (Wd_Id) axi4_id, Bit #(Wd_Addr) addr_base, Bit #(Wd_Addr) addr_lim); 41 | 42 | interface AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave; 43 | 44 | method Bool interrupt_req; 45 | 46 | interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master; 47 | endinterface 48 | 49 | // ================================================================ 50 | 51 | endpackage 52 | -------------------------------------------------------------------------------- /src_Testbench/SoC/Accel_Dummy/AXI4_Accel_Dummy.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2019 Bluespec, Inc. All Rights Reserved. 2 | // Author: Rishiyur S. Nikhil 3 | 4 | package AXI4_Accel_Dummy; 5 | 6 | // ================================================================ 7 | // A dummy 'accelerator' for testing that software can read/write 8 | // accelerator registers. 9 | 10 | // The slave interface just implements a memory model. 11 | // The master interface is a dummy. 12 | 13 | // ================================================================ 14 | // Bluespec library imports 15 | 16 | import RegFile :: *; 17 | import FIFOF :: *; 18 | import GetPut :: *; 19 | import ClientServer :: *; 20 | 21 | // ---------------- 22 | // BSV additional libs 23 | 24 | import Cur_Cycle :: *; 25 | import GetPut_Aux :: *; 26 | import Semi_FIFOF :: *; 27 | 28 | // ================================================================ 29 | // Project imports 30 | 31 | import AXI4_Types :: *; 32 | import AXI4_Mem_Model :: *; 33 | import Fabric_Defs :: *; 34 | import AXI4_Accel_IFC :: *; 35 | 36 | // ================================================================ 37 | 38 | (* synthesize *) 39 | module mkAXI4_Accel_Dummy (AXI4_Accel_IFC); 40 | 41 | AXI4_Mem_Model_IFC #(Wd_Id, 42 | Wd_Addr, 43 | Wd_Data, 44 | Wd_User) mem_model <- mkAXI4_Mem_Model; 45 | 46 | method Action init (Bit# (Wd_Id) axi4_id, Bit #(Wd_Addr) addr_base, Bit #(Wd_Addr) addr_lim); 47 | mem_model.init (addr_base, addr_lim); 48 | endmethod 49 | 50 | interface slave = mem_model.slave; 51 | interface master = dummy_AXI4_Master_ifc; 52 | endmodule 53 | 54 | // ================================================================ 55 | 56 | endpackage 57 | -------------------------------------------------------------------------------- /src_Testbench/SoC/Boot_ROM_Generator/.gitignore: -------------------------------------------------------------------------------- 1 | *.exe 2 | -------------------------------------------------------------------------------- /src_Testbench/SoC/Boot_ROM_Generator/Makefile: -------------------------------------------------------------------------------- 1 | # Generates fn_read_ROM_RV32.bsvi and fn_read_ROM_RV64.bsvi 2 | # in a temporary directory 'tmpdir/'. 3 | # Manually copy these to .., if ok. 4 | 5 | default: tmpdir/fn_read_ROM_RV32.bsvi tmpdir/fn_read_ROM_RV64.bsvi 6 | 7 | tmpdir/fn_read_ROM_RV64.bsvi: tmpdir gen_bootrom.exe 8 | ./gen_bootrom.exe RV64 imaus > tmpdir/boot_ROM_RV64.memhex 9 | ./Gen_BSV_fn_read_ROM.py tmpdir/boot_ROM_RV64.memhex tmpdir/fn_read_ROM_RV64.bsvi 10 | 11 | tmpdir/fn_read_ROM_RV32.bsvi: tmpdir gen_bootrom.exe 12 | ./gen_bootrom.exe RV32 imaus > tmpdir/boot_ROM_RV32.memhex 13 | ./Gen_BSV_fn_read_ROM.py tmpdir/boot_ROM_RV32.memhex tmpdir/fn_read_ROM_RV32.bsvi 14 | 15 | gen_bootrom.exe: tmpdir gen_bootrom.cc 16 | $(CXX) -o $@ -std=c++11 gen_bootrom.cc 17 | 18 | tmpdir: 19 | mkdir -p tmpdir 20 | 21 | .PHONY: full_clean 22 | full_clean: 23 | rm -r -f *~ tmpdir gen_bootrom.exe 24 | -------------------------------------------------------------------------------- /src_Testbench/SoC/External_Control.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved 2 | 3 | package External_Control; 4 | 5 | // ================================================================ 6 | // This package defines control request and response types from an 7 | // external agent (usually GDB) to the SoC. 8 | 9 | // ================================================================ 10 | // BSV library imports 11 | 12 | // None 13 | 14 | // ================================================================ 15 | // External control requests 16 | 17 | typedef struct { 18 | Bit #(8) op; 19 | Bit #(64) arg1; 20 | Bit #(64) arg2; 21 | } Control_Req 22 | deriving (Bits, FShow); 23 | 24 | // ---------------- 25 | // Reads and writes to the Debug Module 26 | 27 | Bit #(8) external_control_req_op_read_control_fabric = 10; // arg1: fabric_addr 28 | Bit #(8) external_control_req_op_write_control_fabric = 11; // arg1: fabric_addr, arg2: data 29 | 30 | // ================================================================ 31 | // External control responses 32 | 33 | typedef struct { 34 | Bit #(8) status; 35 | Bit #(64) result; 36 | } Control_Rsp 37 | deriving (Bits, FShow); 38 | 39 | Bit #(8) external_control_rsp_status_ok = 0; 40 | Bit #(8) external_control_rsp_status_err = 1; 41 | 42 | // ================================================================ 43 | 44 | endpackage 45 | -------------------------------------------------------------------------------- /src_Testbench/Top/Makefile: -------------------------------------------------------------------------------- 1 | # This Makefile is for standalone testing of various groups of 2 | # functions in C_Imported_Functions.c 3 | 4 | # ================================================================ 5 | 6 | C_Imported_Functions.o: C_Imported_Functions.h C_Imported_Functions.c 7 | $(CC) -c C_Imported_Functions.c 8 | 9 | # ================================================================ 10 | # Standalone testing 11 | 12 | # Uncomment one of the following 13 | 14 | TEST ?= PLEASE_CHOOSE_TEST 15 | 16 | # TEST = TEST_TRYGETCHAR 17 | # TEST = TEST_GET_SYMBOL_VAL 18 | TEST = TEST_COMMS 19 | 20 | test_exe: C_Imported_Functions.c 21 | $(CC) -o test_exe -D$(TEST) C_Imported_Functions.c 22 | 23 | .PHONY: start 24 | start: test_exe 25 | ./test_exe 26 | 27 | # ================================================================ 28 | 29 | .PHONY: clean 30 | clean: 31 | rm -f *~ *.o 32 | 33 | .PHONY: full_clean 34 | full_clean: 35 | rm -f *~ *.o test_exe 36 | 37 | # ================================================================ 38 | -------------------------------------------------------------------------------- /src_bsc_lib_RTL/README.txt: -------------------------------------------------------------------------------- 1 | These are copies of a few of the Verilog files that are found in any 2 | standard Bluespec bsc distribution at $(BLUESPECDIR)/Verilog 3 | -------------------------------------------------------------------------------- /src_bsc_lib_RTL/RevertReg.v: -------------------------------------------------------------------------------- 1 | 2 | // Copyright (c) 2000-2009 Bluespec, Inc. 3 | 4 | // Permission is hereby granted, free of charge, to any person obtaining a copy 5 | // of this software and associated documentation files (the "Software"), to deal 6 | // in the Software without restriction, including without limitation the rights 7 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | // copies of the Software, and to permit persons to whom the Software is 9 | // furnished to do so, subject to the following conditions: 10 | 11 | // The above copyright notice and this permission notice shall be included in 12 | // all copies or substantial portions of the Software. 13 | 14 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 | // THE SOFTWARE. 21 | // 22 | // $Revision$ 23 | // $Date$ 24 | 25 | `ifdef BSV_ASSIGNMENT_DELAY 26 | `else 27 | `define BSV_ASSIGNMENT_DELAY 28 | `endif 29 | 30 | module RevertReg(CLK, Q_OUT, D_IN, EN); 31 | 32 | parameter width = 1; 33 | parameter init = { width {1'b0} } ; 34 | 35 | input CLK; 36 | input EN; 37 | input [width - 1 : 0] D_IN; 38 | output [width - 1 : 0] Q_OUT; 39 | 40 | assign Q_OUT = init; 41 | endmodule 42 | -------------------------------------------------------------------------------- /synthesis/README: -------------------------------------------------------------------------------- 1 | TOP_MODULE = mkCPU 2 | Versions: 3 | 4 | RV32ACFIMSU 5 | Base version 6 | 7 | RV32ACDFIMSU 8 | To determine the cost of double precision 9 | 10 | RV32ACFIMSUP_32 11 | Cost of 32 bit posit wrt baseline 12 | 13 | RV32ACFIMSUP_24 14 | Cost of 24 bit posit wrt baseline 15 | 16 | RV32ACFIMSUP_16 17 | Cost of 16 bit posit wrt baseline 18 | -------------------------------------------------------------------------------- /synthesis/synth-tab-20200329.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HPC-Lab-IITB/Clarinet/0bf84b2db46a1a2a0c0575f94de50aead2b5f1b6/synthesis/synth-tab-20200329.pdf --------------------------------------------------------------------------------