├── Project_1 ├── Project_1.cr.mti ├── Project_1.mpf ├── code.txt ├── control │ ├── ALUctrl.v │ └── ctrl.v ├── datapath │ ├── alu.v │ ├── dm.v │ ├── ext.v │ ├── im.v │ ├── mux.v │ ├── pc.v │ └── regheap.v ├── mips.v ├── testbench.v ├── vsim.wlf └── work │ ├── _info │ ├── _lib.qdb │ ├── _lib1_0.qdb │ ├── _lib1_0.qpg │ ├── _lib1_0.qtl │ └── _vmake ├── Project_2 ├── Project_2.cr.mti ├── Project_2.mpf ├── code.txt ├── control │ ├── ALUctrl.v │ ├── ctrl.v │ ├── forwardingUnit.v │ └── hazardDetectionUnit.v ├── datapath │ ├── alu.v │ ├── dm.v │ ├── ext.v │ ├── im.v │ ├── mux.v │ ├── pc.v │ └── regheap.v ├── midreg │ ├── EX_MEM.v │ ├── ID_EX.v │ ├── IF_ID.v │ └── MEM_WB.v ├── mips.v ├── testbench.v ├── testcode.asm ├── vsim.wlf └── work │ ├── _info │ ├── _lib.qdb │ ├── _lib1_1.qdb │ ├── _lib1_1.qpg │ ├── _lib1_1.qtl │ ├── _lib1_24.qdb │ ├── _lib1_24.qpg │ ├── _lib1_24.qtl │ └── _vmake ├── Project_3 ├── code.txt ├── control │ ├── ALUctrl.v │ ├── ctrl.v │ ├── forwardingUnit.v │ └── hazardDetectionUnit.v ├── datapath │ ├── alu.v │ ├── dm.v │ ├── ext.v │ ├── im.v │ ├── mux.v │ ├── pc.v │ ├── regheap.v │ └── register.v ├── midreg │ ├── EX_MEM.v │ ├── ID_EX.v │ ├── IF_ID.v │ └── MEM_WB.v ├── mips.v ├── testbench.v └── testcode.asm └── README.md /Project_1/Project_1.cr.mti: -------------------------------------------------------------------------------- 1 | D:/Code/Repos/mips/Project_1/control/ALUctrl.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_1/control/ALUctrl.v 2 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 3 | -- Compiling module ALUctrl 4 | 5 | Top level modules: 6 | ALUctrl 7 | 8 | } {} {}} D:/Code/Repos/mips/Project_1/datapath/dm.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_1/datapath/dm.v 9 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 10 | -- Compiling module dm_4k 11 | 12 | Top level modules: 13 | dm_4k 14 | 15 | } {} {}} D:/Code/Repos/mips/Project_1/datapath/ext.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_1/datapath/ext.v 16 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 17 | -- Compiling module ext 18 | 19 | Top level modules: 20 | ext 21 | 22 | } {} {}} D:/Code/Repos/mips/Project_1/testbench.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_1/testbench.v 23 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 24 | -- Compiling module testbench 25 | 26 | Top level modules: 27 | testbench 28 | 29 | } {} {}} D:/Code/Repos/mips/Project_1/datapath/alu.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_1/datapath/alu.v 30 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 31 | -- Compiling module alu 32 | 33 | Top level modules: 34 | alu 35 | 36 | } {} {}} D:/Code/Repos/mips/Project_1/datapath/im.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_1/datapath/im.v 37 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 38 | -- Compiling module im_4k 39 | 40 | Top level modules: 41 | im_4k 42 | 43 | } {} {}} D:/Code/Repos/mips/Project_1/datapath/mux.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_1/datapath/mux.v 44 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 45 | -- Compiling module mux2 46 | 47 | Top level modules: 48 | mux2 49 | 50 | } {} {}} D:/Code/Repos/mips/Project_1/mips.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_1/mips.v 51 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 52 | -- Compiling module mips 53 | 54 | Top level modules: 55 | mips 56 | 57 | } {} {}} D:/Code/Repos/mips/Project_1/control/ctrl.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_1/control/ctrl.v 58 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 59 | -- Compiling module ctrl 60 | 61 | Top level modules: 62 | ctrl 63 | 64 | } {} {}} D:/Code/Repos/mips/Project_1/datapath/pc.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_1/datapath/pc.v 65 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 66 | -- Compiling module pc 67 | 68 | Top level modules: 69 | pc 70 | 71 | } {} {}} D:/Code/Repos/mips/Project_1/datapath/regheap.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_1/datapath/regheap.v 72 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 73 | -- Compiling module regheap 74 | 75 | Top level modules: 76 | regheap 77 | 78 | } {} {}} 79 | -------------------------------------------------------------------------------- /Project_1/Project_1.mpf: -------------------------------------------------------------------------------- 1 | ; vsim modelsim.ini file, version 10.4 2 | [Version] 3 | INIVersion = "10.4a" 4 | 5 | ; Copyright 1991-2015 Mentor Graphics Corporation 6 | ; 7 | ; All Rights Reserved. 8 | ; 9 | ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 10 | ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. 11 | ; 12 | 13 | [Library] 14 | std = $MODEL_TECH/../std 15 | ieee = $MODEL_TECH/../ieee 16 | vital2000 = $MODEL_TECH/../vital2000 17 | ; 18 | ; VITAL concerns: 19 | ; 20 | ; The library ieee contains (among other packages) the packages of the 21 | ; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use 22 | ; the physical library ieee (recommended), or use the physical library 23 | ; vital2000, but not both. The design can use logical library ieee and/or 24 | ; vital2000 as long as each of these maps to the same physical library, either 25 | ; ieee or vital2000. 26 | ; 27 | ; A design using the 1995 version of the VITAL packages, whether or not 28 | ; it also uses the 2000 version of the VITAL packages, must have logical library 29 | ; name ieee mapped to physical library vital1995. (A design cannot use library 30 | ; vital1995 directly because some packages in this library use logical name ieee 31 | ; when referring to the other packages in the library.) The design source 32 | ; should use logical name ieee when referring to any packages there except the 33 | ; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical 34 | ; name vital2000 (mapped to physical library vital2000) to refer to those 35 | ; packages. 36 | ; ieee = $MODEL_TECH/../vital1995 37 | ; 38 | ; For compatiblity with previous releases, logical library name vital2000 maps 39 | ; to library vital2000 (a different library than library ieee, containing the 40 | ; same packages). 41 | ; A design should not reference VITAL from both the ieee library and the 42 | ; vital2000 library because the vital packages are effectively different. 43 | ; A design that references both the ieee and vital2000 libraries must have 44 | ; both logical names ieee and vital2000 mapped to the same library, either of 45 | ; these: 46 | ; $MODEL_TECH/../ieee 47 | ; $MODEL_TECH/../vital2000 48 | ; 49 | verilog = $MODEL_TECH/../verilog 50 | std_developerskit = $MODEL_TECH/../std_developerskit 51 | synopsys = $MODEL_TECH/../synopsys 52 | modelsim_lib = $MODEL_TECH/../modelsim_lib 53 | sv_std = $MODEL_TECH/../sv_std 54 | mtiAvm = $MODEL_TECH/../avm 55 | mtiRnm = $MODEL_TECH/../rnm 56 | mtiOvm = $MODEL_TECH/../ovm-2.1.2 57 | mtiUvm = $MODEL_TECH/../uvm-1.1d 58 | mtiUPF = $MODEL_TECH/../upf_lib 59 | mtiPA = $MODEL_TECH/../pa_lib 60 | floatfixlib = $MODEL_TECH/../floatfixlib 61 | mc2_lib = $MODEL_TECH/../mc2_lib 62 | osvvm = $MODEL_TECH/../osvvm 63 | 64 | ; added mapping for ADMS 65 | mgc_ams = $MODEL_TECH/../mgc_ams 66 | ieee_env = $MODEL_TECH/../ieee_env 67 | 68 | ;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release 69 | ;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release 70 | ;mvc_lib = $MODEL_TECH/../mvc_lib 71 | infact = $MODEL_TECH/../infact 72 | 73 | 74 | vhdlopt_lib = $MODEL_TECH/../vhdlopt_lib 75 | work = work 76 | [DefineOptionset] 77 | ; Define optionset entries for the various compilers, vmake, and vsim. 78 | ; These option sets can be used with the "-optionset " syntax. 79 | ; i.e. 80 | ; vlog -optionset COMPILEDEBUG top.sv 81 | ; vsim -optionset UVMDEBUG my_top 82 | ; 83 | ; Following are some useful examples. 84 | 85 | ; define a vsim optionset for uvm debugging 86 | UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop 87 | 88 | ; define a vopt optionset for debugging 89 | VOPTDEBUG = +acc -debugdb 90 | 91 | 92 | [vcom] 93 | ; VHDL93 variable selects language version as the default. 94 | ; Default is VHDL-2002. 95 | ; Value of 0 or 1987 for VHDL-1987. 96 | ; Value of 1 or 1993 for VHDL-1993. 97 | ; Default or value of 2 or 2002 for VHDL-2002. 98 | ; Value of 3 or 2008 for VHDL-2008 99 | ; Value of 4 or ams99 for VHDL-AMS-1999 100 | ; Value of 5 or ams07 for VHDL-AMS-2007 101 | VHDL93 = 2002 102 | 103 | ; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. 104 | ; ignoreStandardRealVector = 1 105 | 106 | ; Show source line containing error. Default is off. 107 | ; Show_source = 1 108 | 109 | ; Turn off unbound-component warnings. Default is on. 110 | ; Show_Warning1 = 0 111 | 112 | ; Turn off process-without-a-wait-statement warnings. Default is on. 113 | ; Show_Warning2 = 0 114 | 115 | ; Turn off null-range warnings. Default is on. 116 | ; Show_Warning3 = 0 117 | 118 | ; Turn off no-space-in-time-literal warnings. Default is on. 119 | ; Show_Warning4 = 0 120 | 121 | ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. 122 | ; Show_Warning5 = 0 123 | 124 | ; Turn off optimization for IEEE std_logic_1164 package. Default is on. 125 | ; Optimize_1164 = 0 126 | 127 | ; Enable compiler statistics. Specify one or more arguments: 128 | ; [all,none,time,cmd,msg,perf,verbose,list] 129 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 130 | ; Stats = time,cmd,msg 131 | 132 | ; Turn on resolving of ambiguous function overloading in favor of the 133 | ; "explicit" function declaration (not the one automatically created by 134 | ; the compiler for each type declaration). Default is off. 135 | ; The .ini file has Explicit enabled so that std_logic_signed/unsigned 136 | ; will match the behavior of synthesis tools. 137 | Explicit = 1 138 | 139 | ; Turn off acceleration of the VITAL packages. Default is to accelerate. 140 | ; NoVital = 1 141 | 142 | ; Turn off VITAL compliance checking. Default is checking on. 143 | ; NoVitalCheck = 1 144 | 145 | ; Ignore VITAL compliance checking errors. Default is to not ignore. 146 | ; IgnoreVitalErrors = 1 147 | 148 | ; Turn off VITAL compliance checking warnings. Default is to show warnings. 149 | ; Show_VitalChecksWarnings = 0 150 | 151 | ; Turn off PSL assertion warning messages. Default is to show warnings. 152 | ; Show_PslChecksWarnings = 0 153 | 154 | ; Enable parsing of embedded PSL assertions. Default is enabled. 155 | ; EmbeddedPsl = 0 156 | 157 | ; Keep silent about case statement static warnings. 158 | ; Default is to give a warning. 159 | ; NoCaseStaticError = 1 160 | 161 | ; Keep silent about warnings caused by aggregates that are not locally static. 162 | ; Default is to give a warning. 163 | ; NoOthersStaticError = 1 164 | 165 | ; Treat as errors: 166 | ; case statement static warnings 167 | ; warnings caused by aggregates that are not locally static 168 | ; Overrides NoCaseStaticError, NoOthersStaticError settings. 169 | ; PedanticErrors = 1 170 | 171 | ; Turn off inclusion of debugging info within design units. 172 | ; Default is to include debugging info. 173 | ; NoDebug = 1 174 | 175 | ; Turn off "Loading..." messages. Default is messages on. 176 | ; Quiet = 1 177 | 178 | ; Turn on some limited synthesis rule compliance checking. Checks only: 179 | ; -- signals used (read) by a process must be in the sensitivity list 180 | ; CheckSynthesis = 1 181 | 182 | ; Activate optimizations on expressions that do not involve signals, 183 | ; waits, or function/procedure/task invocations. Default is off. 184 | ; ScalarOpts = 1 185 | 186 | ; Turns on lint-style checking. 187 | ; Show_Lint = 1 188 | 189 | ; Require the user to specify a configuration for all bindings, 190 | ; and do not generate a compile time default binding for the 191 | ; component. This will result in an elaboration error of 192 | ; 'component not bound' if the user fails to do so. Avoids the rare 193 | ; issue of a false dependency upon the unused default binding. 194 | ; RequireConfigForAllDefaultBinding = 1 195 | 196 | ; Perform default binding at compile time. 197 | ; Default is to do default binding at load time. 198 | ; BindAtCompile = 1; 199 | 200 | ; Inhibit range checking on subscripts of arrays. Range checking on 201 | ; scalars defined with subtypes is inhibited by default. 202 | ; NoIndexCheck = 1 203 | 204 | ; Inhibit range checks on all (implicit and explicit) assignments to 205 | ; scalar objects defined with subtypes. 206 | ; NoRangeCheck = 1 207 | 208 | ; Set the prefix to be honored for synthesis/coverage pragma recognition. 209 | ; Default is "". 210 | ; AddPragmaPrefix = "" 211 | 212 | ; Ignore synthesis and coverage pragmas with this prefix. 213 | ; Default is "". 214 | ; IgnorePragmaPrefix = "" 215 | 216 | ; Turn on code coverage in VHDL design units. Default is off. 217 | ; Coverage = sbceft 218 | 219 | ; Turn off code coverage in VHDL subprograms. Default is on. 220 | ; CoverSub = 0 221 | 222 | ; Automatically exclude VHDL case statement OTHERS choice branches. 223 | ; This includes OTHERS choices in selected signal assigment statements. 224 | ; Default is to not exclude. 225 | ; CoverExcludeDefault = 1 226 | 227 | ; Control compiler and VOPT optimizations that are allowed when 228 | ; code coverage is on. Refer to the comment for this in the [vlog] area. 229 | ; CoverOpt = 3 230 | 231 | ; Turn on or off clkOpt optimization for code coverage. Default is on. 232 | ; CoverClkOpt = 1 233 | 234 | ; Turn on or off clkOpt optimization builtins for code coverage. Default is on. 235 | ; CoverClkOptBuiltins = 0 236 | 237 | ; Inform code coverage optimizations to respect VHDL 'H' and 'L' 238 | ; values on signals in conditions and expressions, and to not automatically 239 | ; convert them to '1' and '0'. Default is to not convert. 240 | ; CoverRespectHandL = 0 241 | 242 | ; Increase or decrease the maximum number of rows allowed in a UDP table 243 | ; implementing a VHDL condition coverage or expression coverage expression. 244 | ; More rows leads to a longer compile time, but more expressions covered. 245 | ; CoverMaxUDPRows = 192 246 | 247 | ; Increase or decrease the maximum number of input patterns that are present 248 | ; in FEC table. This leads to a longer compile time with more expressions 249 | ; covered with FEC metric. 250 | ; CoverMaxFECRows = 192 251 | 252 | ; Increase or decrease the limit on the size of expressions and conditions 253 | ; considered for expression and condition coverages. Higher FecUdpEffort leads 254 | ; to higher compile, optimize and simulation time, but more expressions and 255 | ; conditions are considered for coverage in the design. FecUdpEffort can 256 | ; be set to a number ranging from 1 (low) to 3 (high), defined as: 257 | ; 1 - (low) Only small expressions and conditions considered for coverage. 258 | ; 2 - (medium) Bigger expressions and conditions considered for coverage. 259 | ; 3 - (high) Very large expressions and conditions considered for coverage. 260 | ; The default setting is 1 (low). 261 | ; FecUdpEffort = 1 262 | 263 | ; Enable or disable Focused Expression Coverage analysis for conditions and 264 | ; expressions. Focused Expression Coverage data is provided by default when 265 | ; expression and/or condition coverage is active. 266 | ; CoverFEC = 0 267 | 268 | ; Enable or disable UDP Coverage analysis for conditions and expressions. 269 | ; UDP Coverage data is disabled by default when expression and/or condition 270 | ; coverage is active. 271 | ; CoverUDP = 1 272 | 273 | ; Enable or disable Rapid Expression Coverage mode for conditions and expressions. 274 | ; Disabling this would convert non-masking conditions in FEC tables to matching 275 | ; input patterns. 276 | ; CoverREC = 1 277 | 278 | ; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions 279 | ; for expression/condition coverage. 280 | ; NOTE: Enabling this may have a negative impact on simulation performance. 281 | ; CoverExpandReductionPrefix = 0 282 | 283 | ; Enable or disable short circuit evaluation of conditions and expressions when 284 | ; condition or expression coverage is active. Short circuit evaluation is enabled 285 | ; by default. 286 | ; CoverShortCircuit = 0 287 | 288 | ; Enable code coverage reporting of code that has been optimized away. 289 | ; The default is not to report. 290 | ; CoverReportCancelled = 1 291 | 292 | ; Enable deglitching of code coverage in combinatorial, non-clocked, processes. 293 | ; Default is no deglitching. 294 | ; CoverDeglitchOn = 1 295 | 296 | ; Control the code coverage deglitching period. A period of 0, eliminates delta 297 | ; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a 298 | ; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 299 | ; CoverDeglitchPeriod = 0 300 | 301 | ; Use this directory for compiler temporary files instead of "work/_temp" 302 | ; CompilerTempDir = /tmp 303 | 304 | ; Set this to cause the compilers to force data to be committed to disk 305 | ; when the files are closed. 306 | ; SyncCompilerFiles = 1 307 | 308 | ; Add VHDL-AMS declarations to package STANDARD 309 | ; Default is not to add 310 | ; AmsStandard = 1 311 | 312 | ; Range and length checking will be performed on array indices and discrete 313 | ; ranges, and when violations are found within subprograms, errors will be 314 | ; reported. Default is to issue warnings for violations, because subprograms 315 | ; may not be invoked. 316 | ; NoDeferSubpgmCheck = 0 317 | 318 | ; Turn ON detection of FSMs having single bit current state variable. 319 | ; FsmSingle = 1 320 | 321 | ; Turn off reset state transitions in FSM. 322 | ; FsmResetTrans = 0 323 | 324 | ; Turn ON detection of FSM Implicit Transitions. 325 | ; FsmImplicitTrans = 1 326 | 327 | ; Controls whether or not to show immediate assertions with constant expressions 328 | ; in GUI/report/UCDB etc. By default, immediate assertions with constant 329 | ; expressions are shown in GUI/report/UCDB etc. This does not affect 330 | ; evaluation of immediate assertions. 331 | ; ShowConstantImmediateAsserts = 0 332 | 333 | ; Controls how VHDL basic identifiers are stored with the design unit. 334 | ; Does not make the language case-sensitive, affects only how declarations 335 | ; declared with basic identifiers have their names stored and printed 336 | ; (in the GUI, examine, etc.). 337 | ; Default is to preserve the case as originally depicted in the VHDL source. 338 | ; Value of 0 indicates to change all basic identifiers to lower case. 339 | ; PreserveCase = 0 340 | 341 | ; For Configuration Declarations, controls the effect that USE clauses have 342 | ; on visibility inside the configuration items being configured. If 1 343 | ; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, 344 | ; extend the visibility of objects made visible through USE clauses into nested 345 | ; component configurations. 346 | ; OldVHDLConfigurationVisibility = 0 347 | 348 | ; Allows VHDL configuration declarations to be in a different library from 349 | ; the corresponding configured entity. Default is to not allow this for 350 | ; stricter LRM-compliance. 351 | ; SeparateConfigLibrary = 1; 352 | 353 | ; Determine how mode OUT subprogram parameters of type array and record are treated. 354 | ; If 0 (the default), then only VHDL 2008 will do this initialization. 355 | ; If 1, always initialize the mode OUT parameter to its default value. 356 | ; If 2, do not initialize the mode OUT out parameter. 357 | ; Note that prior to release 10.1, all language versions did not initialize mode 358 | ; OUT array and record type parameters, unless overridden here via this mechanism. 359 | ; In release 10.1 and later, only files compiled with VHDL 2008 will cause this 360 | ; initialization, unless overridden here. 361 | ; InitOutCompositeParam = 0 362 | 363 | ; Generate symbols debugging database in only some special cases to save on 364 | ; the number of files in the library. For other design-units, this database is 365 | ; generated on-demand in vsim. 366 | ; Default is to to generate debugging database for all design-units. 367 | ; SmartDbgSym = 1 368 | 369 | ; Enable or disable automatic creation of missing libraries. 370 | ; Default is 1 (enabled) 371 | ; CreateLib = 1 372 | 373 | [vlog] 374 | ; Turn off inclusion of debugging info within design units. 375 | ; Default is to include debugging info. 376 | ; NoDebug = 1 377 | 378 | ; Turn on `protect compiler directive processing. 379 | ; Default is to ignore `protect directives. 380 | ; Protect = 1 381 | 382 | ; Turn off "Loading..." messages. Default is messages on. 383 | ; Quiet = 1 384 | 385 | ; Turn on Verilog hazard checking (order-dependent accessing of global vars). 386 | ; Default is off. 387 | ; Hazard = 1 388 | 389 | ; Turn on converting regular Verilog identifiers to uppercase. Allows case 390 | ; insensitivity for module names. Default is no conversion. 391 | ; UpCase = 1 392 | 393 | ; Activate optimizations on expressions that do not involve signals, 394 | ; waits, or function/procedure/task invocations. Default is off. 395 | ; ScalarOpts = 1 396 | 397 | ; Turns on lint-style checking. 398 | ; Show_Lint = 1 399 | 400 | ; Show source line containing error. Default is off. 401 | ; Show_source = 1 402 | 403 | ; Turn on bad option warning. Default is off. 404 | ; Show_BadOptionWarning = 1 405 | 406 | ; Revert back to IEEE 1364-1995 syntax, default is 0 (off). 407 | ; vlog95compat = 1 408 | 409 | ; Turn off PSL warning messages. Default is to show warnings. 410 | ; Show_PslChecksWarnings = 0 411 | 412 | ; Enable parsing of embedded PSL assertions. Default is enabled. 413 | ; EmbeddedPsl = 0 414 | 415 | ; Enable compiler statistics. Specify one or more arguments: 416 | ; [all,none,time,cmd,msg,perf,verbose,list,kb] 417 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 418 | ; Stats = time,cmd,msg 419 | 420 | ; Set the threshold for automatically identifying sparse Verilog memories. 421 | ; A memory with depth equal to or more than the sparse memory threshold gets 422 | ; marked as sparse automatically, unless specified otherwise in source code 423 | ; or by +nosparse commandline option of vlog or vopt. 424 | ; The default is 1M. (i.e. memories with depth equal 425 | ; to or greater than 1M are marked as sparse) 426 | ; SparseMemThreshold = 1048576 427 | 428 | ; Set the prefix to be honored for synthesis and coverage pragma recognition. 429 | ; Default is "". 430 | ; AddPragmaPrefix = "" 431 | 432 | ; Ignore synthesis and coverage pragmas with this prefix. 433 | ; Default is "". 434 | ; IgnorePragmaPrefix = "" 435 | 436 | ; Set the option to treat all files specified in a vlog invocation as a 437 | ; single compilation unit. The default value is set to 0 which will treat 438 | ; each file as a separate compilation unit as specified in the P1800 draft standard. 439 | ; MultiFileCompilationUnit = 1 440 | 441 | ; Turn on code coverage in Verilog design units. Default is off. 442 | ; Coverage = sbceft 443 | 444 | ; Automatically exclude Verilog case statement default branches. 445 | ; Default is to not automatically exclude defaults. 446 | ; CoverExcludeDefault = 1 447 | 448 | ; Increase or decrease the maximum number of rows allowed in a UDP table 449 | ; implementing a VHDL condition coverage or expression coverage expression. 450 | ; More rows leads to a longer compile time, but more expressions covered. 451 | ; CoverMaxUDPRows = 192 452 | 453 | ; Increase or decrease the maximum number of input patterns that are present 454 | ; in FEC table. This leads to a longer compile time with more expressions 455 | ; covered with FEC metric. 456 | ; CoverMaxFECRows = 192 457 | 458 | ; Increase or decrease the limit on the size of expressions and conditions 459 | ; considered for expression and condition coverages. Higher FecUdpEffort leads 460 | ; to higher compile, optimize and simulation time, but more expressions and 461 | ; conditions are considered for coverage in the design. FecUdpEffort can 462 | ; be set to a number ranging from 1 (low) to 3 (high), defined as: 463 | ; 1 - (low) Only small expressions and conditions considered for coverage. 464 | ; 2 - (medium) Bigger expressions and conditions considered for coverage. 465 | ; 3 - (high) Very large expressions and conditions considered for coverage. 466 | ; The default setting is 1 (low). 467 | ; FecUdpEffort = 1 468 | 469 | ; Enable or disable Focused Expression Coverage analysis for conditions and 470 | ; expressions. Focused Expression Coverage data is provided by default when 471 | ; expression and/or condition coverage is active. 472 | ; CoverFEC = 0 473 | 474 | ; Enable or disable UDP Coverage analysis for conditions and expressions. 475 | ; UDP Coverage data is disabled by default when expression and/or condition 476 | ; coverage is active. 477 | ; CoverUDP = 1 478 | 479 | ; Enable or disable Rapid Expression Coverage mode for conditions and expressions. 480 | ; Disabling this would convert non-masking conditions in FEC tables to matching 481 | ; input patterns. 482 | ; CoverREC = 1 483 | 484 | ; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions 485 | ; for expression/condition coverage. 486 | ; NOTE: Enabling this may have a negative impact on simulation performance. 487 | ; CoverExpandReductionPrefix = 0 488 | 489 | ; Enable or disable short circuit evaluation of conditions and expressions when 490 | ; condition or expression coverage is active. Short circuit evaluation is enabled 491 | ; by default. 492 | ; CoverShortCircuit = 0 493 | 494 | ; Enable deglitching of code coverage in combinatorial, non-clocked, processes. 495 | ; Default is no deglitching. 496 | ; CoverDeglitchOn = 1 497 | 498 | ; Control the code coverage deglitching period. A period of 0, eliminates delta 499 | ; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a 500 | ; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 501 | ; CoverDeglitchPeriod = 0 502 | 503 | ; Turn on code coverage in VLOG `celldefine modules, modules containing 504 | ; specify blocks, and modules included using vlog -v and -y. Default is off. 505 | ; CoverCells = 1 506 | 507 | ; Enable code coverage reporting of code that has been optimized away. 508 | ; The default is not to report. 509 | ; CoverReportCancelled = 1 510 | 511 | ; Control compiler and VOPT optimizations that are allowed when 512 | ; code coverage is on. This is a number from 0 to 5, with the following 513 | ; meanings (the default is 3): 514 | ; 5 -- All allowable optimizations are on. 515 | ; 4 -- Turn off removing unreferenced code. 516 | ; 3 -- Turn off process, always block and if statement merging. 517 | ; 2 -- Turn off expression optimization, converting primitives 518 | ; to continuous assignments, VHDL subprogram inlining. 519 | ; and VHDL clkOpt (converting FF's to builtins). 520 | ; 1 -- Turn off continuous assignment optimizations and clock suppression. 521 | ; 0 -- Turn off Verilog module inlining and VHDL arch inlining. 522 | ; HOWEVER, if fsm coverage is turned on, optimizations will be forced to 523 | ; level 3, with also turning off converting primitives to continuous assigns. 524 | ; CoverOpt = 3 525 | 526 | ; Specify the override for the default value of "cross_num_print_missing" 527 | ; option for the Cross in Covergroups. If not specified then LRM default 528 | ; value of 0 (zero) is used. This is a compile time option. 529 | ; SVCrossNumPrintMissingDefault = 0 530 | 531 | ; Setting following to 1 would cause creation of variables which 532 | ; would represent the value of Coverpoint expressions. This is used 533 | ; in conjunction with "SVCoverpointExprVariablePrefix" option 534 | ; in the modelsim.ini 535 | ; EnableSVCoverpointExprVariable = 0 536 | 537 | ; Specify the override for the prefix used in forming the variable names 538 | ; which represent the Coverpoint expressions. This is used in conjunction with 539 | ; "EnableSVCoverpointExprVariable" option of the modelsim.ini 540 | ; The default prefix is "expr". 541 | ; The variable name is 542 | ; variable name => _ 543 | ; SVCoverpointExprVariablePrefix = expr 544 | 545 | ; Override for the default value of the SystemVerilog covergroup, 546 | ; coverpoint, and cross option.goal (defined to be 100 in the LRM). 547 | ; NOTE: It does not override specific assignments in SystemVerilog 548 | ; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" 549 | ; in the [vsim] section can override this value. 550 | ; SVCovergroupGoalDefault = 100 551 | 552 | ; Override for the default value of the SystemVerilog covergroup, 553 | ; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) 554 | ; NOTE: It does not override specific assignments in SystemVerilog 555 | ; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" 556 | ; in the [vsim] section can override this value. 557 | ; SVCovergroupTypeGoalDefault = 100 558 | 559 | ; Specify the override for the default value of "strobe" option for the 560 | ; Covergroup Type. This is a compile time option which forces "strobe" to 561 | ; a user specified default value and supersedes SystemVerilog specified 562 | ; default value of '0'(zero). NOTE: This can be overriden by a runtime 563 | ; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. 564 | ; SVCovergroupStrobeDefault = 0 565 | 566 | ; Specify the override for the default value of "per_instance" option for the 567 | ; Covergroup variables. This is a compile time option which forces "per_instance" 568 | ; to a user specified default value and supersedes SystemVerilog specified 569 | ; default value of '0'(zero). 570 | ; SVCovergroupPerInstanceDefault = 0 571 | 572 | ; Specify the override for the default value of "get_inst_coverage" option for the 573 | ; Covergroup variables. This is a compile time option which forces 574 | ; "get_inst_coverage" to a user specified default value and supersedes 575 | ; SystemVerilog specified default value of '0'(zero). 576 | ; SVCovergroupGetInstCoverageDefault = 0 577 | 578 | ; 579 | ; A space separated list of resource libraries that contain precompiled 580 | ; packages. The behavior is identical to using the "-L" switch. 581 | ; 582 | ; LibrarySearchPath = [ ...] 583 | LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact 584 | 585 | ; The behavior is identical to the "-mixedansiports" switch. Default is off. 586 | ; MixedAnsiPorts = 1 587 | 588 | ; Enable SystemVerilog 3.1a $typeof() function. Default is off. 589 | ; EnableTypeOf = 1 590 | 591 | ; Only allow lower case pragmas. Default is disabled. 592 | ; AcceptLowerCasePragmaOnly = 1 593 | 594 | ; Set the maximum depth permitted for a recursive include file nesting. 595 | ; IncludeRecursionDepthMax = 5 596 | 597 | ; Turn ON detection of FSMs having single bit current state variable. 598 | ; FsmSingle = 1 599 | 600 | ; Turn off reset state transitions in FSM. 601 | ; FsmResetTrans = 0 602 | 603 | ; Turn off detections of FSMs having x-assignment. 604 | ; FsmXAssign = 0 605 | 606 | ; Turn ON detection of FSM Implicit Transitions. 607 | ; FsmImplicitTrans = 1 608 | 609 | ; List of file suffixes which will be read as SystemVerilog. White space 610 | ; in extensions can be specified with a back-slash: "\ ". Back-slashes 611 | ; can be specified with two consecutive back-slashes: "\\"; 612 | ; SvFileSuffixes = sv svp svh 613 | 614 | ; This setting is the same as the vlog -sv command line switch. 615 | ; Enables SystemVerilog features and keywords when true (1). 616 | ; When false (0), the rules of IEEE Std 1364-2001 are followed and 617 | ; SystemVerilog keywords are ignored. 618 | ; Svlog = 0 619 | 620 | ; Prints attribute placed upon SV packages during package import 621 | ; when true (1). The attribute will be ignored when this 622 | ; entry is false (0). The attribute name is "package_load_message". 623 | ; The value of this attribute is a string literal. 624 | ; Default is true (1). 625 | ; PrintSVPackageLoadingAttribute = 1 626 | 627 | ; Do not show immediate assertions with constant expressions in 628 | ; GUI/reports/UCDB etc. By default immediate assertions with constant 629 | ; expressions are shown in GUI/reports/UCDB etc. This does not affect 630 | ; evaluation of immediate assertions. 631 | ; ShowConstantImmediateAsserts = 0 632 | 633 | ; Controls if untyped parameters that are initialized with values greater 634 | ; than 2147483647 are mapped to generics of type INTEGER or ignored. 635 | ; If mapped to VHDL Integers, values greater than 2147483647 636 | ; are mapped to negative values. 637 | ; Default is to map these parameter to generic of type INTEGER 638 | ; ForceUnsignedToVHDLInteger = 1 639 | 640 | ; Enable AMS wreal (wired real) extensions. Default is 0. 641 | ; WrealType = 1 642 | 643 | ; Controls SystemVerilog Language Extensions. These options enable 644 | ; some non-LRM compliant behavior. Valid extensions are: 645 | ; "acum", "atpi", "catx", "daoa", "feci", "fin0", "idcl", 646 | ; "iddp", "pae", "sccts", "spsl", "stop0", "udm0", and "uslt". 647 | ; SvExtensions = uslt,spsl,sccts 648 | 649 | ; Generate symbols debugging database in only some special cases to save on 650 | ; the number of files in the library. For other design-units, this database is 651 | ; generated on-demand in vsim. 652 | ; Default is to to generate debugging database for all design-units. 653 | ; SmartDbgSym = 1 654 | 655 | ; Controls how $unit library entries are named. Valid options are: 656 | ; "file" (generate name based on the first file on the command line) 657 | ; "du" (generate name based on first design unit following an item 658 | ; found in $unit scope) 659 | ; CUAutoName = file 660 | 661 | ; Enable or disable automatic creation of missing libraries. 662 | ; Default is 1 (enabled) 663 | ; CreateLib = 1 664 | 665 | [sccom] 666 | ; Enable use of SCV include files and library. Default is off. 667 | ; UseScv = 1 668 | 669 | ; Add C++ compiler options to the sccom command line by using this variable. 670 | ; CppOptions = -g 671 | 672 | ; Use custom C++ compiler located at this path rather than the default path. 673 | ; The path should point directly at a compiler executable. 674 | ; CppPath = /usr/bin/g++ 675 | 676 | ; Specify the compiler version from the list of support GNU compilers. 677 | ; examples 4.3.3, 4.5.0 678 | ; CppInstall = 4.5.0 679 | 680 | ; Enable verbose messages from sccom. Default is off. 681 | ; SccomVerbose = 1 682 | 683 | ; sccom logfile. Default is no logfile. 684 | ; SccomLogfile = sccom.log 685 | 686 | ; Enable use of SC_MS include files and library. Default is off. 687 | ; UseScMs = 1 688 | 689 | ; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. 690 | ; Sc22Mode = 1 691 | 692 | ; Enable compiler statistics. Specify one or more arguments: 693 | ; [all,none,time,cmd,msg,perf,verbose,list,kb] 694 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 695 | ; Stats = time,cmd,msg 696 | 697 | ; Enable or disable automatic creation of missing libraries. 698 | ; Default is 1 (enabled) 699 | ; CreateLib = 1 700 | 701 | [vopt] 702 | ; Turn on code coverage in vopt. Default is off. 703 | ; Coverage = sbceft 704 | 705 | ; Control compiler optimizations that are allowed when 706 | ; code coverage is on. Refer to the comment for this in the [vlog] area. 707 | ; CoverOpt = 3 708 | 709 | ; Increase or decrease the maximum number of rows allowed in a UDP table 710 | ; implementing a VHDL condition coverage or expression coverage expression. 711 | ; More rows leads to a longer compile time, but more expressions covered. 712 | ; CoverMaxUDPRows = 192 713 | 714 | ; Increase or decrease the maximum number of input patterns that are present 715 | ; in FEC table. This leads to a longer compile time with more expressions 716 | ; covered with FEC metric. 717 | ; CoverMaxFECRows = 192 718 | 719 | ; Increase or decrease the limit on the size of expressions and conditions 720 | ; considered for expression and condition coverages. Higher FecUdpEffort leads 721 | ; to higher compile, optimize and simulation time, but more expressions and 722 | ; conditions are considered for coverage in the design. FecUdpEffort can 723 | ; be set to a number ranging from 1 (low) to 3 (high), defined as: 724 | ; 1 - (low) Only small expressions and conditions considered for coverage. 725 | ; 2 - (medium) Bigger expressions and conditions considered for coverage. 726 | ; 3 - (high) Very large expressions and conditions considered for coverage. 727 | ; The default setting is 1 (low). 728 | ; FecUdpEffort = 1 729 | 730 | ; Enable code coverage reporting of code that has been optimized away. 731 | ; The default is not to report. 732 | ; CoverReportCancelled = 1 733 | 734 | ; Enable deglitching of code coverage in combinatorial, non-clocked, processes. 735 | ; Default is no deglitching. 736 | ; CoverDeglitchOn = 1 737 | 738 | ; Enable compiler statistics. Specify one or more arguments: 739 | ; [all,none,time,cmd,msg,perf,verbose,list,kb] 740 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 741 | ; Stats = time,cmd,msg 742 | 743 | ; Control the code coverage deglitching period. A period of 0, eliminates delta 744 | ; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a 745 | ; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 746 | ; CoverDeglitchPeriod = 0 747 | 748 | ; Do not show immediate assertions with constant expressions in 749 | ; GUI/reports/UCDB etc. By default immediate assertions with constant 750 | ; expressions are shown in GUI/reports/UCDB etc. This does not affect 751 | ; evaluation of immediate assertions. 752 | ; ShowConstantImmediateAsserts = 0 753 | 754 | ; Set the maximum number of iterations permitted for a generate loop. 755 | ; Restricting this permits the implementation to recognize infinite 756 | ; generate loops. 757 | ; GenerateLoopIterationMax = 100000 758 | 759 | ; Set the maximum depth permitted for a recursive generate instantiation. 760 | ; Restricting this permits the implementation to recognize infinite 761 | ; recursions. 762 | ; GenerateRecursionDepthMax = 200 763 | 764 | ; Set the number of processes created during the code generation phase. 765 | ; By default a heuristic is used to set this value. This may be set to 0 766 | ; to disable this feature completely. 767 | ; ParallelJobs = 0 768 | 769 | ; Controls SystemVerilog Language Extensions. These options enable 770 | ; some non-LRM compliant behavior. Valid extensions are "feci", 771 | ; "pae", "uslt", "spsl", "fin0" and "sccts". 772 | ; SvExtensions = uslt,spsl,sccts 773 | 774 | ; Load the specified shared objects with the RTLD_GLOBAL flag. 775 | ; This gives global visibility to all symbols in the shared objects, 776 | ; meaning that subsequently loaded shared objects can bind to symbols 777 | ; in the global shared objects. The list of shared objects should 778 | ; be whitespace delimited. This option is not supported on the 779 | ; Windows or AIX platforms. 780 | ; GlobalSharedObjectList = example1.so example2.so example3.so 781 | 782 | ; Disable SystemVerilog elaboration system task messages 783 | ; IgnoreSVAInfo = 1 784 | ; IgnoreSVAWarning = 1 785 | ; IgnoreSVAError = 1 786 | ; IgnoreSVAFatal = 1 787 | 788 | ; Enable or disable automatic creation of missing libraries. 789 | ; Default is 1 (enabled) 790 | ; CreateLib = 1 791 | 792 | 793 | [vsim] 794 | ; vopt flow 795 | ; Set to turn on automatic optimization of a design. 796 | ; Default is on 797 | VoptFlow = 1 798 | 799 | ; Simulator resolution 800 | ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. 801 | Resolution = ns 802 | 803 | ; Disable certain code coverage exclusions automatically. 804 | ; Assertions and FSM are exluded from the code coverage by default 805 | ; Set AutoExclusionsDisable = fsm to enable code coverage for fsm 806 | ; Set AutoExclusionsDisable = assertions to enable code coverage for assertions 807 | ; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions 808 | ; Or specify comma or space separated list 809 | ;AutoExclusionsDisable = fsm,assertions 810 | 811 | ; User time unit for run commands 812 | ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the 813 | ; unit specified for Resolution. For example, if Resolution is 100ps, 814 | ; then UserTimeUnit defaults to ps. 815 | ; Should generally be set to default. 816 | UserTimeUnit = default 817 | 818 | ; Default run length 819 | RunLength = 100 ns 820 | 821 | ; Maximum iterations that can be run without advancing simulation time 822 | IterationLimit = 10000000 823 | 824 | ; Specify libraries to be searched for precompiled modules 825 | ; LibrarySearchPath = [ ...] 826 | 827 | ; Set XPROP assertion fail limit. Default is 5. 828 | ; Any positive integer, -1 for infinity. 829 | ; XpropAssertionLimit = 5 830 | 831 | ; Control PSL and Verilog Assume directives during simulation 832 | ; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts 833 | ; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts 834 | ; SimulateAssumeDirectives = 1 835 | 836 | ; Control the simulation of PSL and SVA 837 | ; These switches can be overridden by the vsim command line switches: 838 | ; -psl, -nopsl, -sva, -nosva. 839 | ; Set SimulatePSL = 0 to disable PSL simulation 840 | ; Set SimulatePSL = 1 to enable PSL simulation (default) 841 | ; SimulatePSL = 1 842 | ; Set SimulateSVA = 0 to disable SVA simulation 843 | ; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) 844 | ; SimulateSVA = 1 845 | 846 | ; Control SVA and VHDL immediate assertion directives during simulation 847 | ; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts 848 | ; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts 849 | ; SimulateImmedAsserts = 1 850 | 851 | ; License feature mappings for Verilog and VHDL 852 | ; qhsimvh Single language VHDL license 853 | ; qhsimvl Single language Verilog license 854 | ; msimhdlsim Language neutral license for either Verilog or VHDL 855 | ; msimhdlmix Second language only, language neutral license for either 856 | ; Verilog or VHDL 857 | ; 858 | ; Directives to license manager can be set either as single value or as 859 | ; space separated multi-values: 860 | ; vhdl Immediately checkout and hold a VHDL license (i.e., one of 861 | ; qhsimvh, msimhdlsim, or msimhdlmix) 862 | ; vlog Immediately checkout and hold a Verilog license (i.e., one of 863 | ; qhsimvl, msimhdlsim, or msimhdlmix) 864 | ; plus Immediately checkout and hold a VHDL license and a Verilog license 865 | ; noqueue Do not wait in the license queue when a license is not available 866 | ; viewsim Try for viewer license but accept simulator license(s) instead 867 | ; of queuing for viewer license (PE ONLY) 868 | ; noviewer Disable checkout of msimviewer license feature (PE ONLY) 869 | ; noslvhdl Disable checkout of qhsimvh license feature 870 | ; noslvlog Disable checkout of qhsimvl license feature 871 | ; nomix Disable checkout of msimhdlmix license feature 872 | ; nolnl Disable checkout of msimhdlsim license feature 873 | ; mixedonly Disable checkout of qhsimvh and qhsimvl license features 874 | ; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features 875 | ; 876 | ; Examples (remove ";" comment character to activate licensing directives): 877 | ; Single directive: 878 | ; License = plus 879 | ; Multi-directive (Note: space delimited directives): 880 | ; License = noqueue plus 881 | 882 | ; Severity level of a VHDL assertion message or of a SystemVerilog severity system task 883 | ; which will cause a running simulation to stop. 884 | ; VHDL assertions and SystemVerilog severity system task that occur with the 885 | ; given severity or higher will cause a running simulation to stop. 886 | ; This value is ignored during elaboration. 887 | ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal 888 | BreakOnAssertion = 3 889 | 890 | ; Severity level of a tool message which will cause a running simulation to 891 | ; stop. This value is ignored during elaboration. Default is to not break. 892 | ; 0 = Note 1 = Warning 2 = Error 3 = Fatal 893 | ;BreakOnMessage = 2 894 | 895 | ; The class debug feature enables more visibility and tracking of class instances 896 | ; during simulation. By default this feature is disabled (0). To enable this 897 | ; feature set ClassDebug to 1. 898 | ; ClassDebug = 1 899 | 900 | ; Message Format conversion specifications: 901 | ; %S - Severity Level of message/assertion 902 | ; %R - Text of message 903 | ; %T - Time of message 904 | ; %D - Delta value (iteration number) of Time 905 | ; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected 906 | ; %i - Instance/Region/Signal pathname with Process name (if available) 907 | ; %I - shorthand for one of these: 908 | ; " %K: %i" 909 | ; " %K: %i File: %F" (when path is not Process or Signal) 910 | ; except that the %i in this case does not report the Process name 911 | ; %O - Process name 912 | ; %P - Instance/Region path without leaf process 913 | ; %F - File name 914 | ; %L - Line number; if assertion message, then line number of assertion or, if 915 | ; assertion is in a subprogram, line from which the call is made 916 | ; %u - Design unit name in form library.primary 917 | ; %U - Design unit name in form library.primary(secondary) 918 | ; %% - The '%' character itself 919 | ; 920 | ; If specific format for Severity Level is defined, use that format. 921 | ; Else, for a message that occurs during elaboration: 922 | ; -- Failure/Fatal message in VHDL region that is not a Process, and in 923 | ; certain non-VHDL regions, uses MessageFormatBreakLine; 924 | ; -- Failure/Fatal message otherwise uses MessageFormatBreak; 925 | ; -- Note/Warning/Error message uses MessageFormat. 926 | ; Else, for a message that occurs during runtime and triggers a breakpoint because 927 | ; of the BreakOnAssertion setting: 928 | ; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; 929 | ; -- otherwise uses MessageFormatBreak. 930 | ; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. 931 | ; 932 | ; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" 933 | ; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" 934 | ; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 935 | ; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 936 | ; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 937 | ; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" 938 | ; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 939 | ; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" 940 | 941 | ; Error File - alternate file for storing error messages 942 | ; ErrorFile = error.log 943 | 944 | ; Simulation Breakpoint messages 945 | ; This flag controls the display of function names when reporting the location 946 | ; where the simulator stops because of a breakpoint or fatal error. 947 | ; Example with function name: # Break in Process ctr at counter.vhd line 44 948 | ; Example without function name: # Break at counter.vhd line 44 949 | ; Default value is 1. 950 | ShowFunctions = 1 951 | 952 | ; Default radix for all windows and commands. 953 | ; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned 954 | ; Flags may be one of: enumnumeric, showbase 955 | DefaultRadix = hexadecimal 956 | DefaultRadixFlags = showbase 957 | ; Set to 1 for make the signal_force VHDL and Verilog functions use the 958 | ; default radix when processing the force value. Prior to 10.2 signal_force 959 | ; used the default radix, now it always uses symbolic unless value explicitly indicates base 960 | ;SignalForceFunctionUseDefaultRadix = 0 961 | 962 | ; VSIM Startup command 963 | ; Startup = do startup.do 964 | 965 | ; VSIM Shutdown file 966 | ; Filename to save u/i formats and configurations. 967 | ; ShutdownFile = restart.do 968 | ; To explicitly disable auto save: 969 | ; ShutdownFile = --disable-auto-save 970 | 971 | ; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. 972 | ; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. 973 | ; BatchMode = 1 974 | 975 | ; File for saving command transcript when -batch option used 976 | ; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero 977 | ; default is unset so command transcript only goes to stdout for better performance 978 | ; BatchTranscriptFile = transcript 979 | 980 | ; File for saving command transcript, this option is ignored when -batch option is used 981 | TranscriptFile = transcript 982 | 983 | ; File for saving command history 984 | ; CommandHistory = cmdhist.log 985 | 986 | ; Specify whether paths in simulator commands should be described 987 | ; in VHDL or Verilog format. 988 | ; For VHDL, PathSeparator = / 989 | ; For Verilog, PathSeparator = . 990 | ; Must not be the same character as DatasetSeparator. 991 | PathSeparator = / 992 | 993 | ; Specify the dataset separator for fully rooted contexts. 994 | ; The default is ':'. For example: sim:/top 995 | ; Must not be the same character as PathSeparator. 996 | DatasetSeparator = : 997 | 998 | ; Specify a unique path separator for the Signal Spy set of functions. 999 | ; The default will be to use the PathSeparator variable. 1000 | ; Must not be the same character as DatasetSeparator. 1001 | ; SignalSpyPathSeparator = / 1002 | 1003 | ; Used to control parsing of HDL identifiers input to the tool. 1004 | ; This includes CLI commands, vsim/vopt/vlog/vcom options, 1005 | ; string arguments to FLI/VPI/DPI calls, etc. 1006 | ; If set to 1, accept either Verilog escaped Id syntax or 1007 | ; VHDL extended id syntax, regardless of source language. 1008 | ; If set to 0, the syntax of the source language must be used. 1009 | ; Each identifier in a hierarchical name may need different syntax, 1010 | ; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or 1011 | ; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" 1012 | ; GenerousIdentifierParsing = 1 1013 | 1014 | ; Disable VHDL assertion messages 1015 | ; IgnoreNote = 1 1016 | ; IgnoreWarning = 1 1017 | ; IgnoreError = 1 1018 | ; IgnoreFailure = 1 1019 | 1020 | ; Disable SystemVerilog assertion messages 1021 | ; IgnoreSVAInfo = 1 1022 | ; IgnoreSVAWarning = 1 1023 | ; IgnoreSVAError = 1 1024 | ; IgnoreSVAFatal = 1 1025 | 1026 | ; Do not print any additional information from Severity System tasks. 1027 | ; Only the message provided by the user is printed along with severity 1028 | ; information. 1029 | ; SVAPrintOnlyUserMessage = 1; 1030 | 1031 | ; Default force kind. May be freeze, drive, deposit, or default 1032 | ; or in other terms, fixed, wired, or charged. 1033 | ; A value of "default" will use the signal kind to determine the 1034 | ; force kind, drive for resolved signals, freeze for unresolved signals 1035 | ; DefaultForceKind = freeze 1036 | 1037 | ; Control the iteration of events when a VHDL signal is forced to a value 1038 | ; This flag can be set to honour the signal update event in next iteration, 1039 | ; the default is to update and propagate in the same iteration. 1040 | ; ForceSigNextIter = 1 1041 | 1042 | ; Enable simulation statistics. Specify one or more arguments: 1043 | ; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] 1044 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 1045 | ; Stats = time,cmd,msg 1046 | 1047 | ; If zero, open files when elaborated; otherwise, open files on 1048 | ; first read or write. Default is 0. 1049 | ; DelayFileOpen = 1 1050 | 1051 | ; Control VHDL files opened for write. 1052 | ; 0 = Buffered, 1 = Unbuffered 1053 | UnbufferedOutput = 0 1054 | 1055 | ; Control the number of VHDL files open concurrently. 1056 | ; This number should always be less than the current ulimit 1057 | ; setting for max file descriptors. 1058 | ; 0 = unlimited 1059 | ConcurrentFileLimit = 40 1060 | 1061 | ; If nonzero, close files as soon as there is either an explicit call to 1062 | ; file_close, or when the file variable's scope is closed. When zero, a 1063 | ; file opened in append mode is not closed in case it is immediately 1064 | ; reopened in append mode; otherwise, the file will be closed at the 1065 | ; point it is reopened. 1066 | ; AppendClose = 1 1067 | 1068 | ; Control the number of hierarchical regions displayed as 1069 | ; part of a signal name shown in the Wave window. 1070 | ; A value of zero tells VSIM to display the full name. 1071 | ; The default is 0. 1072 | ; WaveSignalNameWidth = 0 1073 | 1074 | ; Turn off warnings when changing VHDL constants and generics 1075 | ; Default is 1 to generate warning messages 1076 | ; WarnConstantChange = 0 1077 | 1078 | ; Turn off warnings from accelerated versions of the std_logic_arith, 1079 | ; std_logic_unsigned, and std_logic_signed packages. 1080 | ; StdArithNoWarnings = 1 1081 | 1082 | ; Turn off warnings from accelerated versions of the IEEE numeric_std 1083 | ; and numeric_bit packages. 1084 | ; NumericStdNoWarnings = 1 1085 | 1086 | ; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names 1087 | ; in the design hierarchy. 1088 | ; This style is controlled by the value of the GenerateFormat 1089 | ; value described next. Default is to use new-style names, which 1090 | ; comprise the generate statement label, '(', the value of the generate 1091 | ; parameter, and a closing ')'. 1092 | ; Set this to 1 to use old-style names. 1093 | ; OldVhdlForGenNames = 1 1094 | 1095 | ; Control the format of the old-style VHDL FOR generate statement region 1096 | ; name for each iteration. Do not quote the value. 1097 | ; The format string here must contain the conversion codes %s and %d, 1098 | ; in that order, and no other conversion codes. The %s represents 1099 | ; the generate statement label; the %d represents the generate parameter value 1100 | ; at a particular iteration (this is the position number if the generate parameter 1101 | ; is of an enumeration type). Embedded whitespace is allowed (but discouraged); 1102 | ; leading and trailing whitespace is ignored. 1103 | ; Application of the format must result in a unique region name over all 1104 | ; loop iterations for a particular immediately enclosing scope so that name 1105 | ; lookup can function properly. The default is %s__%d. 1106 | ; GenerateFormat = %s__%d 1107 | 1108 | ; Enable more efficient logging of VHDL Variables. 1109 | ; Logging VHDL variables without this enabled, while possible, is very 1110 | ; inefficient. Enabling this will provide a more efficient logging methodology 1111 | ; at the expense of more memory usage. By default this feature is disabled (0). 1112 | ; To enabled this feature, set this variable to 1. 1113 | ; VhdlVariableLogging = 1 1114 | 1115 | ; Enable logging of VHDL access type variables and their designated objects. 1116 | ; This setting will allow both variables of an access type ("access variables") 1117 | ; and their designated objects ("access objects") to be logged. Logging a 1118 | ; variable of an access type will automatically also cause the designated 1119 | ; object(s) of that variable to be logged as the simulation progresses. 1120 | ; Further, enabling this allows access objects to be logged by name. By default 1121 | ; this feature is disabled (0). To enable this feature, set this variable to 1. 1122 | ; Enabling this will automatically enable the VhdlVariableLogging feature also. 1123 | ; AccessObjDebug = 1 1124 | 1125 | ; Make each VHDL package in a PDU has its own separate copy of the package instead 1126 | ; of sharing the package between PDUs. The default is to share packages. 1127 | ; To ensure that each PDU has its own set of packages, set this variable to 1. 1128 | ; VhdlSeparatePduPackage = 1 1129 | 1130 | ; Specify whether checkpoint files should be compressed. 1131 | ; The default is 1 (compressed). 1132 | ; CheckpointCompressMode = 0 1133 | 1134 | ; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. 1135 | ; Use custom gcc compiler located at this path rather than the default path. 1136 | ; The path should point directly at a compiler executable. 1137 | ; DpiCppPath = /bin/gcc 1138 | 1139 | ; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. 1140 | ; The term "out-of-the-blue" refers to SystemVerilog export function calls 1141 | ; made from C functions that don't have the proper context setup 1142 | ; (as is the case when running under "DPI-C" import functions). 1143 | ; When this is enabled, one can call a DPI export function 1144 | ; (but not task) from any C code. 1145 | ; the setting of this variable can be one of the following values: 1146 | ; 0 : dpioutoftheblue call is disabled (default) 1147 | ; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. 1148 | ; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. 1149 | ; DpiOutOfTheBlue = 1 1150 | 1151 | ; Specify whether continuous assignments are run before other normal priority 1152 | ; processes scheduled in the same iteration. This event ordering minimizes race 1153 | ; differences between optimized and non-optimized designs, and is the default 1154 | ; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set 1155 | ; ImmediateContinuousAssign to 0. 1156 | ; The default is 1 (enabled). 1157 | ; ImmediateContinuousAssign = 0 1158 | 1159 | ; List of dynamically loaded objects for Verilog PLI applications 1160 | ; Veriuser = veriuser.sl 1161 | 1162 | ; Which default VPI object model should the tool conform to? 1163 | ; The 1364 modes are Verilog-only, for backwards compatibility with older 1164 | ; libraries, and SystemVerilog objects are not available in these modes. 1165 | ; 1166 | ; In the absence of a user-specified default, the tool default is the 1167 | ; latest available LRM behavior. 1168 | ; Options for PliCompatDefault are: 1169 | ; VPI_COMPATIBILITY_VERSION_1364v1995 1170 | ; VPI_COMPATIBILITY_VERSION_1364v2001 1171 | ; VPI_COMPATIBILITY_VERSION_1364v2005 1172 | ; VPI_COMPATIBILITY_VERSION_1800v2005 1173 | ; VPI_COMPATIBILITY_VERSION_1800v2008 1174 | ; 1175 | ; Synonyms for each string are also recognized: 1176 | ; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) 1177 | ; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) 1178 | ; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) 1179 | ; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) 1180 | ; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) 1181 | 1182 | 1183 | ; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 1184 | 1185 | ; Specify whether the Verilog system task $fopen or vpi_mcd_open() 1186 | ; will create directories that do not exist when opening the file 1187 | ; in "a" or "w" mode. 1188 | ; The default is 0 (do not create non-existent directories) 1189 | ; CreateDirForFileAccess = 1 1190 | 1191 | ; Specify default options for the restart command. Options can be one 1192 | ; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions 1193 | ; DefaultRestartOptions = -force 1194 | 1195 | 1196 | ; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. 1197 | ; Valid options include: all, none, verbose, disable, struct, msglog, trlog, certe. 1198 | ; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". 1199 | ; The list of options must be delimited by commas, without spaces or tabs. 1200 | ; The default is UVMControl = struct 1201 | 1202 | ; Some examples 1203 | ; To turn on all available UVM-aware debug features: 1204 | ; UVMControl = all 1205 | ; To turn on the struct window, mesage logging, and transaction logging: 1206 | ; UVMControl = struct,msglog,trlog 1207 | ; To turn on all options except certe: 1208 | ; UVMControl = all,-certe 1209 | ; To completely disable all UVM-aware debug functionality: 1210 | ; UVMControl = disable 1211 | 1212 | ; Specify the WildcardFilter setting. 1213 | ; A space separated list of object types to be excluded when performing 1214 | ; wildcard matches with log, wave, etc commands. The default value for this variable is: 1215 | ; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" 1216 | ; See "Using the WildcardFilter Preference Variable" in the documentation for 1217 | ; details on how to use this variable and for descriptions of the filter types. 1218 | WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile 1219 | 1220 | ; Specify the WildcardSizeThreshold setting. 1221 | ; This integer setting specifies the size at which objects will be excluded when 1222 | ; performing wildcard matches with log, wave, etc commands. Objects of size equal 1223 | ; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard 1224 | ; matches. The size is a simple calculation of number of bits or items in the object. 1225 | ; The default value is 8k (8192). Setting this value to 0 will disable the checking 1226 | ; of object size against this threshold and allow all objects of any size to be logged. 1227 | WildcardSizeThreshold = 8192 1228 | 1229 | ; Specify whether warning messages are output when objects are filtered out due to the 1230 | ; WildcardSizeThreshold. The default is 0 (no messages generated). 1231 | WildcardSizeThresholdVerbose = 0 1232 | 1233 | ; Turn on (1) or off (0) WLF file compression. 1234 | ; The default is 1 (compress WLF file). 1235 | ; WLFCompress = 0 1236 | 1237 | ; Specify whether to save all design hierarchy (1) in the WLF file 1238 | ; or only regions containing logged signals (0). 1239 | ; The default is 0 (save only regions with logged signals). 1240 | ; WLFSaveAllRegions = 1 1241 | 1242 | ; WLF file time limit. Limit WLF file by time, as closely as possible, 1243 | ; to the specified amount of simulation time. When the limit is exceeded 1244 | ; the earliest times get truncated from the file. 1245 | ; If both time and size limits are specified the most restrictive is used. 1246 | ; UserTimeUnits are used if time units are not specified. 1247 | ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} 1248 | ; WLFTimeLimit = 0 1249 | 1250 | ; WLF file size limit. Limit WLF file size, as closely as possible, 1251 | ; to the specified number of megabytes. If both time and size limits 1252 | ; are specified then the most restrictive is used. 1253 | ; The default is 0 (no limit). 1254 | ; WLFSizeLimit = 1000 1255 | 1256 | ; Specify whether or not a WLF file should be deleted when the 1257 | ; simulation ends. A value of 1 will cause the WLF file to be deleted. 1258 | ; The default is 0 (do not delete WLF file when simulation ends). 1259 | ; WLFDeleteOnQuit = 1 1260 | 1261 | ; Specify whether or not a WLF file should be optimized during 1262 | ; simulation. If set to 0, the WLF file will not be optimized. 1263 | ; The default is 1, optimize the WLF file. 1264 | ; WLFOptimize = 0 1265 | 1266 | ; Specify the name of the WLF file. 1267 | ; The default is vsim.wlf 1268 | ; WLFFilename = vsim.wlf 1269 | 1270 | ; Specify whether to lock the WLF file. 1271 | ; Locking the file prevents other invocations of ModelSim/Questa tools from 1272 | ; inadvertently overwriting the WLF file. 1273 | ; The default is 1, lock the WLF file. 1274 | ; WLFFileLock = 0 1275 | 1276 | ; Specify the update interval for the WLF file in live simulation. 1277 | ; The interval is given in seconds. 1278 | ; The value is the smallest interval between WLF file updates. The WLF file 1279 | ; will be flushed (updated) after (at least) the interval has elapsed, ensuring 1280 | ; that the data is correct when viewed from a separate viewer. 1281 | ; A value of 0 means that no updating will occur. 1282 | ; The default value is 10 seconds. 1283 | ; WLFUpdateInterval = 10 1284 | 1285 | ; Specify the WLF cache size limit for WLF files. 1286 | ; The value is given in megabytes. A value of 0 turns off the cache. 1287 | ; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). 1288 | ; On Windows, the default value is 1000 (megabytes) to help to avoid filling 1289 | ; process memory. 1290 | ; WLFSimCacheSize allows a different cache size to be set for a live simulation 1291 | ; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize 1292 | ; is not set, it defaults to the WLFCacheSize value. 1293 | ; WLFCacheSize = 2000 1294 | ; WLFSimCacheSize = 500 1295 | 1296 | ; Specify the WLF file event collapse mode. 1297 | ; 0 = Preserve all events and event order. (same as -wlfnocollapse) 1298 | ; 1 = Only record values of logged objects at the end of a simulator iteration. 1299 | ; (same as -wlfcollapsedelta) 1300 | ; 2 = Only record values of logged objects at the end of a simulator time step. 1301 | ; (same as -wlfcollapsetime) 1302 | ; The default is 1. 1303 | ; WLFCollapseMode = 0 1304 | 1305 | ; Specify whether WLF file logging can use threads on multi-processor machines. 1306 | ; If 0, no threads will be used; if 1, threads will be used if the system has 1307 | ; more than one processor. 1308 | ; WLFUseThreads = 1 1309 | 1310 | ; Specify the size of objects that will trigger "large object" messages 1311 | ; at log/wave/list time. The size calculation of the object is the same as that 1312 | ; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. 1313 | ; Setting LargeObjectSize to 0 will disable these messages. 1314 | ; LargeObjectSize = 500000 1315 | 1316 | ; Specify the depth of stack frames returned by $stacktrace([level]). 1317 | ; This depth will be picked up when the optional 'level' argument 1318 | ; is not specified or its value is not a positive integer. 1319 | ; StackTraceDepth = 100 1320 | 1321 | ; Turn on/off undebuggable SystemC type warnings. Default is on. 1322 | ; ShowUndebuggableScTypeWarning = 0 1323 | 1324 | ; Turn on/off unassociated SystemC name warnings. Default is off. 1325 | ; ShowUnassociatedScNameWarning = 1 1326 | 1327 | ; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. 1328 | ; ScShowIeeeDeprecationWarnings = 1 1329 | 1330 | ; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. 1331 | ; ScEnableScSignalWriteCheck = 1 1332 | 1333 | ; Set SystemC default time unit. 1334 | ; Set to fs, ps, ns, us, ms, or sec with optional 1335 | ; prefix of 1, 10, or 100. The default is 1 ns. 1336 | ; The ScTimeUnit value is honored if it is coarser than Resolution. 1337 | ; If ScTimeUnit is finer than Resolution, it is set to the value 1338 | ; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, 1339 | ; then the default time unit will be 1 ns. However if Resolution 1340 | ; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. 1341 | ScTimeUnit = ns 1342 | 1343 | ; Set SystemC sc_main stack size. The stack size is set as an integer 1344 | ; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or 1345 | ; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends 1346 | ; on the amount of data on the sc_main() stack and the memory required 1347 | ; to succesfully execute the longest function call chain of sc_main(). 1348 | ScMainStackSize = 10 Mb 1349 | 1350 | ; Set SystemC thread stack size. The stack size is set as an integer 1351 | ; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or 1352 | ; Gb(Giga-byte). The stack size for sc_thread depends 1353 | ; on the amount of data on the sc_thread stack and the memory required 1354 | ; to succesfully execute the thread. 1355 | ; ScStackSize = 1 Mb 1356 | 1357 | ; Turn on/off execution of remainder of sc_main upon quitting the current 1358 | ; simulation session. If the cumulative length of sc_main() in terms of 1359 | ; simulation time units is less than the length of the current simulation 1360 | ; run upon quit or restart, sc_main() will be in the middle of execution. 1361 | ; This switch gives the option to execute the remainder of sc_main upon 1362 | ; quitting simulation. The drawback of not running sc_main till the end 1363 | ; is memory leaks for objects created by sc_main. If on, the remainder of 1364 | ; sc_main will be executed ignoring all delays. This may cause the simulator 1365 | ; to crash if the code in sc_main is dependent on some simulation state. 1366 | ; Default is on. 1367 | ScMainFinishOnQuit = 1 1368 | 1369 | ; Set the SCV relationship name that will be used to identify phase 1370 | ; relations. If the name given to a transactor relation matches this 1371 | ; name, the transactions involved will be treated as phase transactions 1372 | ScvPhaseRelationName = mti_phase 1373 | 1374 | ; Customize the vsim kernel shutdown behavior at the end of the simulation. 1375 | ; Some common causes of the end of simulation are $finish (implicit or explicit), 1376 | ; sc_stop(), tf_dofinish(), and assertion failures. 1377 | ; This should be set to "ask", "exit", or "stop". The default is "ask". 1378 | ; "ask" -- In batch mode, the vsim kernel will abruptly exit. 1379 | ; In GUI mode, a dialog box will pop up and ask for user confirmation 1380 | ; whether or not to quit the simulation. 1381 | ; "stop" -- Cause the simulation to stay loaded in memory. This can make some 1382 | ; post-simulation tasks easier. 1383 | ; "exit" -- The simulation will abruptly exit without asking for any confirmation. 1384 | ; "final" -- Run SystemVerilog final blocks then behave as "stop". 1385 | ; Note: This variable can be overridden with the vsim "-onfinish" command line switch. 1386 | OnFinish = ask 1387 | 1388 | ; Print pending deferred assertion messages. 1389 | ; Deferred assertion messages may be scheduled after the $finish in the same 1390 | ; time step. Deferred assertions scheduled to print after the $finish are 1391 | ; printed before exiting with severity level NOTE since it's not known whether 1392 | ; the assertion is still valid due to being printed in the active region 1393 | ; instead of the reactive region where they are normally printed. 1394 | ; OnFinishPendingAssert = 1; 1395 | 1396 | ; Print "simstats" result. Default is 0. 1397 | ; 0 == do not print simstats 1398 | ; 1 == print at end of simulation 1399 | ; 2 == print at end of each run command and end of simulation 1400 | ; PrintSimStats = 1 1401 | 1402 | ; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages 1403 | ; AssertFile = assert.log 1404 | 1405 | ; Enable assertion counts. Default is off. 1406 | ; AssertionCover = 1 1407 | 1408 | ; Run simulator in assertion debug mode. Default is off. 1409 | ; AssertionDebug = 1 1410 | 1411 | ; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. 1412 | ; AssertionEnable = 0 1413 | 1414 | ; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. 1415 | ; Any positive integer, -1 for infinity. 1416 | ; AssertionLimit = 1 1417 | 1418 | ; Turn on/off concurrent assertion pass log. Default is off. 1419 | ; Assertion pass logging is only enabled when assertion is browseable 1420 | ; and assertion debug is enabled. 1421 | ; AssertionPassLog = 1 1422 | 1423 | ; Turn on/off PSL concurrent assertion fail log. Default is on. 1424 | ; The flag does not affect SVA 1425 | ; AssertionFailLog = 0 1426 | 1427 | ; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. 1428 | ; AssertionFailLocalVarLog = 0 1429 | 1430 | ; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. 1431 | ; 0 = Continue 1 = Break 2 = Exit 1432 | ; AssertionFailAction = 1 1433 | 1434 | ; Enable the active thread monitor in the waveform display when assertion debug is enabled. 1435 | ; AssertionActiveThreadMonitor = 1 1436 | 1437 | ; Control how many waveform rows will be used for displaying the active threads. Default is 5. 1438 | ; AssertionActiveThreadMonitorLimit = 5 1439 | 1440 | ; Assertion thread limit after which assertion would be killed/switched off. 1441 | ; The default is -1 (unlimited). If the number of threads for an assertion go 1442 | ; beyond this limit, the assertion would be either switched off or killed. This 1443 | ; limit applies to only assert directives. 1444 | ;AssertionThreadLimit = -1 1445 | 1446 | ; Action to be taken once the assertion thread limit is reached. Default 1447 | ; is kill. It can have a value of off or kill. In case of kill, all the existing 1448 | ; threads are terminated and no new attempts are started. In case of off, the 1449 | ; existing attempts keep on evaluating but no new attempts are started. This 1450 | ; variable applies to only assert directives. 1451 | ;AssertionThreadLimitAction = kill 1452 | 1453 | ; Cover thread limit after which cover would be killed/switched off. 1454 | ; The default is -1 (unlimited). If the number of threads for a cover go 1455 | ; beyond this limit, the cover would be either switched off or killed. This 1456 | ; limit applies to only cover directives. 1457 | ;CoverThreadLimit = -1 1458 | 1459 | ; Action to be taken once the cover thread limit is reached. Default 1460 | ; is kill. It can have a value of off or kill. In case of kill, all the existing 1461 | ; threads are terminated and no new attempts are started. In case of off, the 1462 | ; existing attempts keep on evaluating but no new attempts are started. This 1463 | ; variable applies to only cover directives. 1464 | ;CoverThreadLimitAction = kill 1465 | 1466 | 1467 | ; By default immediate assertions do not participate in Assertion Coverage calculations 1468 | ; unless they are executed. This switch causes all immediate assertions in the design 1469 | ; to participate in Assertion Coverage calculations, whether attempted or not. 1470 | ; UnattemptedImmediateAssertions = 0 1471 | 1472 | ; By default immediate covers participate in Coverage calculations 1473 | ; whether they are attempted or not. This switch causes all unattempted 1474 | ; immediate covers in the design to stop participating in Coverage 1475 | ; calculations. 1476 | ; UnattemptedImmediateCovers = 0 1477 | 1478 | ; By default pass action block is not executed for assertions on vacuous 1479 | ; success. The following variable is provided to enable execution of 1480 | ; pass action block on vacuous success. The following variable is only effective 1481 | ; if the user does not disable pass action block execution by using either 1482 | ; system tasks or CLI. Also there is a performance penalty for enabling 1483 | ; the following variable. 1484 | ;AssertionEnableVacuousPassActionBlock = 1 1485 | 1486 | ; As per strict 1850-2005 PSL LRM, an always property can either pass 1487 | ; or fail. However, by default, Questa reports multiple passes and 1488 | ; multiple fails on top always/never property (always/never operator 1489 | ; is the top operator under Verification Directive). The reason 1490 | ; being that Questa reports passes and fails on per attempt of the 1491 | ; top always/never property. Use the following flag to instruct 1492 | ; Questa to strictly follow LRM. With this flag, all assert/never 1493 | ; directives will start an attempt once at start of simulation. 1494 | ; The attempt can either fail, match or match vacuously. 1495 | ; For e.g. if always is the top operator under assert, the always will 1496 | ; keep on checking the property at every clock. If the property under 1497 | ; always fails, the directive will be considered failed and no more 1498 | ; checking will be done for that directive. A top always property, 1499 | ; if it does not fail, will show a pass at end of simulation. 1500 | ; The default value is '0' (i.e. zero is off). For example: 1501 | ; PslOneAttempt = 1 1502 | 1503 | ; Specify the number of clock ticks to represent infinite clock ticks. 1504 | ; This affects eventually!, until! and until_!. If at End of Simulation 1505 | ; (EOS) an active strong-property has not clocked this number of 1506 | ; clock ticks then neither pass or fail (vacuous match) is returned 1507 | ; else respective fail/pass is returned. The default value is '0' (zero) 1508 | ; which effectively does not check for clock tick condition. For example: 1509 | ; PslInfinityThreshold = 5000 1510 | 1511 | ; Control how many thread start times will be preserved for ATV viewing for a given assertion 1512 | ; instance. Default is -1 (ALL). 1513 | ; ATVStartTimeKeepCount = -1 1514 | 1515 | ; Turn on/off code coverage 1516 | ; CodeCoverage = 0 1517 | 1518 | ; This option applies to condition and expression coverage UDP tables. It 1519 | ; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. 1520 | ; If this option is used and a match occurs in more than one row in the UDP table, 1521 | ; none of the counts for all matching rows is incremented. By default, counts are 1522 | ; incremented for all matching rows. 1523 | ; CoverCountAll = 1 1524 | 1525 | ; Turn off automatic inclusion of VHDL integers in toggle coverage. Default 1526 | ; is to include them. 1527 | ; ToggleNoIntegers = 1 1528 | 1529 | ; Set the maximum number of values that are collected for toggle coverage of 1530 | ; VHDL integers. Default is 100; 1531 | ; ToggleMaxIntValues = 100 1532 | 1533 | ; Set the maximum number of values that are collected for toggle coverage of 1534 | ; Verilog real. Default is 100; 1535 | ; ToggleMaxRealValues = 100 1536 | 1537 | ; Turn on automatic inclusion of Verilog integers in toggle coverage, except 1538 | ; for enumeration types. Default is to include them. 1539 | ; ToggleVlogIntegers = 0 1540 | 1541 | ; Turn on automatic inclusion of Verilog real type in toggle coverage, except 1542 | ; for shortreal types. Default is to not include them. 1543 | ; ToggleVlogReal = 1 1544 | 1545 | ; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays 1546 | ; and VHDL arrays-of-arrays in toggle coverage. 1547 | ; Default is to not include them. 1548 | ; ToggleFixedSizeArray = 1 1549 | 1550 | ; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, 1551 | ; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. 1552 | ; This leads to a longer simulation time with bigger arrays covered with toggle coverage. 1553 | ; Default is 1024. 1554 | ; ToggleMaxFixedSizeArray = 1024 1555 | 1556 | ; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized 1557 | ; one-dimensional packed vectors for toggle coverage. Default is 0. 1558 | ; TogglePackedAsVec = 0 1559 | 1560 | ; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for 1561 | ; toggle coverage. Default is 0. 1562 | ; ToggleVlogEnumBits = 0 1563 | 1564 | ; Turn off automatic inclusion of VHDL records in toggle coverage. 1565 | ; Default is to include them. 1566 | ; ToggleVHDLRecords = 0 1567 | 1568 | ; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. 1569 | ; For unlimited width, set to 0. 1570 | ; ToggleWidthLimit = 128 1571 | 1572 | ; Limit the counts that are tracked for toggle coverage. When all edges for a bit have 1573 | ; reached this count, further activity on the bit is ignored. Default is 1. 1574 | ; For unlimited counts, set to 0. 1575 | ; ToggleCountLimit = 1 1576 | 1577 | ; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. 1578 | ; Following is the toggle coverage calculation criteria based on extended toggle mode: 1579 | ; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). 1580 | ; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. 1581 | ; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. 1582 | ; ExtendedToggleMode = 3 1583 | 1584 | ; Enable toggle statistics collection only for ports. Default is 0. 1585 | ; TogglePortsOnly = 1 1586 | 1587 | ; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has 1588 | ; reached this count, further tracking of the input patterns linked to it is ignored. 1589 | ; Default is 1. For unlimited counts, set to 0. 1590 | ; NOTE: Changing this value from its default value may affect simulation performance. 1591 | ; FecCountLimit = 1 1592 | 1593 | ; Limit the counts that are tracked for UDP Coverage. When a bin has 1594 | ; reached this count, further tracking of the input patterns linked to it is ignored. 1595 | ; Default is 1. For unlimited counts, set to 0. 1596 | ; NOTE: Changing this value from its default value may affect simulation performance. 1597 | ; UdpCountLimit = 1 1598 | 1599 | ; Control toggle coverage deglitching period. A period of 0, eliminates delta 1600 | ; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either 1601 | ; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 1602 | ; ToggleDeglitchPeriod = 10.0ps 1603 | 1604 | ; Turn on/off all PSL/SVA cover directive enables. Default is on. 1605 | ; CoverEnable = 0 1606 | 1607 | ; Turn on/off PSL/SVA cover log. Default is off "0". 1608 | ; CoverLog = 1 1609 | 1610 | ; Set "at_least" value for all PSL/SVA cover directives. Default is 1. 1611 | ; CoverAtLeast = 2 1612 | 1613 | ; Set "limit" value for all PSL/SVA cover directives. Default is -1. 1614 | ; Any positive integer, -1 for infinity. 1615 | ; CoverLimit = 1 1616 | 1617 | ; Specify the coverage database filename. 1618 | ; Default is "" (i.e. database is NOT automatically saved on close). 1619 | ; UCDBFilename = vsim.ucdb 1620 | 1621 | ; Specify the maximum limit for the number of Cross (bin) products reported 1622 | ; in XML and UCDB report against a Cross. A warning is issued if the limit 1623 | ; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this 1624 | ; setting. 1625 | ; MaxReportRhsSVCrossProducts = 1000 1626 | 1627 | ; Specify the override for the "auto_bin_max" option for the Covergroups. 1628 | ; If not specified then value from Covergroup "option" is used. 1629 | ; SVCoverpointAutoBinMax = 64 1630 | 1631 | ; Specify the override for the value of "cross_num_print_missing" 1632 | ; option for the Cross in Covergroups. If not specified then value 1633 | ; specified in the "option.cross_num_print_missing" is used. This 1634 | ; is a runtime option. NOTE: This overrides any "cross_num_print_missing" 1635 | ; value specified by user in source file and any SVCrossNumPrintMissingDefault 1636 | ; specified in modelsim.ini. 1637 | ; SVCrossNumPrintMissing = 0 1638 | 1639 | ; Specify whether to use the value of "cross_num_print_missing" 1640 | ; option in report and GUI for the Cross in Covergroups. If not specified then 1641 | ; cross_num_print_missing is ignored for creating reports and displaying 1642 | ; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". 1643 | ; UseSVCrossNumPrintMissing = 0 1644 | 1645 | ; Specify the threshold of Coverpoint wildcard bin value range size, above which 1646 | ; a warning will be triggered. The default is 4K -- 12 wildcard bits. 1647 | ; SVCoverpointWildCardBinValueSizeWarn = 4096 1648 | 1649 | ; Specify the override for the value of "strobe" option for the 1650 | ; Covergroup Type. If not specified then value in "type_option.strobe" 1651 | ; will be used. This is runtime option which forces "strobe" to 1652 | ; user specified value and supersedes user specified values in the 1653 | ; SystemVerilog Code. NOTE: This also overrides the compile time 1654 | ; default value override specified using "SVCovergroupStrobeDefault" 1655 | ; SVCovergroupStrobe = 0 1656 | 1657 | ; Override for explicit assignments in source code to "option.goal" of 1658 | ; SystemVerilog covergroup, coverpoint, and cross. It also overrides the 1659 | ; default value of "option.goal" (defined to be 100 in the SystemVerilog 1660 | ; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". 1661 | ; SVCovergroupGoal = 100 1662 | 1663 | ; Override for explicit assignments in source code to "type_option.goal" of 1664 | ; SystemVerilog covergroup, coverpoint, and cross. It also overrides the 1665 | ; default value of "type_option.goal" (defined to be 100 in the SystemVerilog 1666 | ; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". 1667 | ; SVCovergroupTypeGoal = 100 1668 | 1669 | ; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() 1670 | ; builtin functions, and report. This setting changes the default values of 1671 | ; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 1672 | ; behavior if explicit assignments are not made on option.get_inst_coverage and 1673 | ; type_option.merge_instances by the user. There are two vsim command line 1674 | ; options, -cvg63 and -nocvg63 to override this setting from vsim command line. 1675 | ; The default value of this variable from release 6.6 onwards is 0. This default 1676 | ; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. 1677 | ; SVCovergroup63Compatibility = 0 1678 | 1679 | ; Enforce the default behavior of covergroup get_coverage() builtin function, GUI 1680 | ; and report. This variable sets the default value of type_option.merge_instances. 1681 | ; There are two vsim command line options, -cvgmergeinstances and 1682 | ; -nocvgmergeinstances to override this setting from vsim command line. 1683 | ; The default value of this variable is 0. This default 1684 | ; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. 1685 | ; SVCovergroupMergeInstancesDefault = 0 1686 | 1687 | ; Enable or disable generation of more detailed information about the sampling 1688 | ; of covergroup, cross, and coverpoints. It provides the details of the number 1689 | ; of times the covergroup instance and type were sampled, as well as details 1690 | ; about why covergroup, cross and coverpoint were not covered. A non-zero value 1691 | ; is to enable this feature. 0 is to disable this feature. Default is 0 1692 | ; SVCovergroupSampleInfo = 0 1693 | 1694 | ; Specify the maximum number of Coverpoint bins in whole design for 1695 | ; all Covergroups. 1696 | ; MaxSVCoverpointBinsDesign = 2147483648 1697 | 1698 | ; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins 1699 | ; MaxSVCoverpointBinsInst = 1048576 1700 | 1701 | ; Specify the maximum number of Cross bins in whole design for 1702 | ; all Covergroups. 1703 | ; MaxSVCrossBinsDesign = 2147483648 1704 | 1705 | ; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins 1706 | ; MaxSVCrossBinsInst = 67108864 1707 | 1708 | ; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. 1709 | ; By default, this variable is set 0, in which case option.no_collect setting will take effect. 1710 | ; If this variable is set to 1, all zero-weight coverage items will not be saved. 1711 | ; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting 1712 | ; of this variable. 1713 | ; CvgZWNoCollect = 1 1714 | 1715 | ; Specify a space delimited list of double quoted TCL style 1716 | ; regular expressions which will be matched against the text of all messages. 1717 | ; If any regular expression is found to be contained within any message, the 1718 | ; status for that message will not be propagated to the UCDB TESTSTATUS. 1719 | ; If no match is detected, then the status will be propagated to the 1720 | ; UCDB TESTSTATUS. More than one such regular expression text is allowed, 1721 | ; and each message text is compared for each regular expression in the list. 1722 | ; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" 1723 | 1724 | ; Set weight for all PSL/SVA cover directives. Default is 1. 1725 | ; CoverWeight = 2 1726 | 1727 | ; Check vsim plusargs. Default is 0 (off). 1728 | ; 0 = Don't check plusargs 1729 | ; 1 = Warning on unrecognized plusarg 1730 | ; 2 = Error and exit on unrecognized plusarg 1731 | ; CheckPlusargs = 1 1732 | 1733 | ; Load the specified shared objects with the RTLD_GLOBAL flag. 1734 | ; This gives global visibility to all symbols in the shared objects, 1735 | ; meaning that subsequently loaded shared objects can bind to symbols 1736 | ; in the global shared objects. The list of shared objects should 1737 | ; be whitespace delimited. This option is not supported on the 1738 | ; Windows or AIX platforms. 1739 | ; GlobalSharedObjectList = example1.so example2.so example3.so 1740 | 1741 | ; Generate the stub definitions for the undefined symbols in the shared libraries being 1742 | ; loaded in the simulation. When this flow is turned on, the undefined symbols will not 1743 | ; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. 1744 | ; The valid arguments are: on, off, verbose. 1745 | ; on : turn on the automatic generation of stub definitions. 1746 | ; off: turn off the flow. The undefined symbols will trigger an immediate load failure. 1747 | ; verbose: Turn on the flow and report the undefined symbols for each shared library. 1748 | ; NOTE: This variable can be overriden with vsim switch "-undefsyms". 1749 | ; The default is off. 1750 | ; 1751 | ; UndefSyms = on 1752 | 1753 | ; Initial seed for the random number generator of the root thread (SystemVerilog). 1754 | ; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. 1755 | ; The default value is 0. 1756 | ; Sv_Seed = 0 1757 | 1758 | ; Specify the solver "engine" that vsim will select for constrained random 1759 | ; generation. 1760 | ; Valid values are: 1761 | ; "auto" - automatically select the best engine for the current 1762 | ; constraint scenario 1763 | ; "bdd" - evaluate all constraint scenarios using the BDD solver engine 1764 | ; "act" - evaluate all constraint scenarios using the ACT solver engine 1765 | ; While the BDD solver engine is generally efficient with constraint scenarios 1766 | ; involving bitwise logical relationships, the ACT solver engine can exhibit 1767 | ; superior performance with constraint scenarios involving large numbers of 1768 | ; random variables related via arithmetic operators (+, *, etc). 1769 | ; NOTE: This variable can be overridden with the vsim "-solveengine" command 1770 | ; line switch. 1771 | ; The default value is "auto". 1772 | ; SolveEngine = auto 1773 | 1774 | ; Specify if the solver should attempt to ignore overflow/underflow semantics 1775 | ; for arithmetic constraints (multiply, addition, subtraction) in order to 1776 | ; improve performance. The "solveignoreoverflow" attribute can be specified on 1777 | ; a per-call basis to randomize() to override this setting. 1778 | ; The default value is 0 (overflow/underflow is not ignored). Set to 1 to 1779 | ; ignore overflow/underflow. 1780 | ; SolveIgnoreOverflow = 0 1781 | 1782 | ; Specifies the maximum size that a dynamic array may be resized to by the 1783 | ; solver. If the solver attempts to resize a dynamic array to a size greater 1784 | ; than the specified limit, the solver will abort with an error. 1785 | ; The default value is 10000. A value of 0 indicates no limit. 1786 | ; SolveArrayResizeMax = 10000 1787 | 1788 | ; Error message severity when randomize() failure is detected (SystemVerilog). 1789 | ; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal 1790 | ; The default is 0 (no error). 1791 | ; SolveFailSeverity = 0 1792 | 1793 | ; Error message severity for suppressible errors that are detected in a 1794 | ; solve/before constraint. 1795 | ; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" 1796 | ; command line switch. 1797 | ; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal 1798 | ; The default is 3 (failure). 1799 | ; SolveBeforeErrorSeverity = 3 1800 | 1801 | ; Enable/disable debug information for randomize() failures. 1802 | ; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command 1803 | ; line switch. 1804 | ; The default is 0 (disabled). Set to 1 to enable basic debug (with no 1805 | ; performance penalty). Set to 2 for enhanced debug (will result in slower 1806 | ; runtime performance). 1807 | ; SolveFailDebug = 0 1808 | 1809 | ; Upon encountering a randomize() failure, generate a simplified testcase that 1810 | ; will reproduce the failure. Optionally output the testcase to a file. 1811 | ; Testcases for 'no-solution' failures will only be produced if SolveFailDebug 1812 | ; is enabled (see above). 1813 | ; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" 1814 | ; command line switch. 1815 | ; The default is OFF (do not generate a testcase). To enable testcase 1816 | ; generation, uncomment this variable. To redirect testcase generation to a 1817 | ; file, specify the name of the output file. 1818 | ; SolveFailTestcase = 1819 | 1820 | ; Specify solver timeout threshold (in seconds). randomize() will fail if the 1821 | ; CPU time required to evaluate any randset exceeds the specified timeout. 1822 | ; The default value is 500. A value of 0 will disable timeout failures. 1823 | ; SolveTimeout = 500 1824 | 1825 | ; Specify the maximum size of the solution graph generated by the BDD solver. 1826 | ; This value can be used to force the BDD solver to abort the evaluation of a 1827 | ; complex constraint scenario that cannot be evaluated with finite memory. 1828 | ; This value is specified in 1000s of nodes. 1829 | ; The default value is 10000. A value of 0 indicates no limit. 1830 | ; SolveGraphMaxSize = 10000 1831 | 1832 | ; Specify the maximum number of evaluations that may be performed on the 1833 | ; solution graph by the BDD solver. This value can be used to force the BDD 1834 | ; solver to abort the evaluation of a complex constraint scenario that cannot 1835 | ; be evaluated in finite time. This value is specified in 10000s of evaluations. 1836 | ; The default value is 10000. A value of 0 indicates no limit. 1837 | ; SolveGraphMaxEval = 10000 1838 | 1839 | ; Specify the maximum number of tests that the ACT solver may evaluate before 1840 | ; abandoning an attempt to solve a particular constraint scenario. 1841 | ; The default value is 2000000. A value of 0 indicates no limit. 1842 | ; SolveACTMaxTests = 2000000 1843 | 1844 | ; Specify the maximum number of operations that the ACT solver may perform 1845 | ; before abandoning an attempt to solve a particular constraint scenario. The 1846 | ; value is specified in 1000000s of operations. 1847 | ; The default value is 10000. A value of 0 indicates no limit. 1848 | ; SolveACTMaxOps = 10000 1849 | 1850 | ; Specify the number of times the ACT solver will retry to evaluate a constraint 1851 | ; scenario that fails due to the SolveACTMax[Tests|Ops] threshold. 1852 | ; The default value is 0 (no retry). 1853 | ; SolveACTRetryCount = 0 1854 | 1855 | ; Specify random sequence compatiblity with a prior letter release. This 1856 | ; option is used to get the same random sequences during simulation as 1857 | ; as a prior letter release. Only prior letter releases (of the current 1858 | ; number release) are allowed. 1859 | ; NOTE: Only those random sequence changes due to solver optimizations are 1860 | ; reverted by this variable. Random sequence changes due to solver bugfixes 1861 | ; cannot be un-done. 1862 | ; NOTE: This variable can be overridden with the vsim "-solverev" command 1863 | ; line switch. 1864 | ; Default value set to "" (no compatibility). 1865 | ; SolveRev = 1866 | 1867 | ; Environment variable expansion of command line arguments has been depricated 1868 | ; in favor shell level expansion. Universal environment variable expansion 1869 | ; inside -f files is support and continued support for MGC Location Maps provide 1870 | ; alternative methods for handling flexible pathnames. 1871 | ; The following line may be uncommented and the value set to 1 to re-enable this 1872 | ; deprecated behavior. The default value is 0. 1873 | ; DeprecatedEnvironmentVariableExpansion = 0 1874 | 1875 | ; Specify the memory threshold for the System Verilog garbage collector. 1876 | ; The value is the number of megabytes of class objects that must accumulate 1877 | ; before the garbage collector is run. 1878 | ; The GCThreshold setting is used when class debug mode is disabled to allow 1879 | ; less frequent garbage collection and better simulation performance. 1880 | ; The GCThresholdClassDebug setting is used when class debug mode is enabled 1881 | ; to allow for more frequent garbage collection. 1882 | ; GCThreshold = 100 1883 | ; GCThresholdClassDebug = 5 1884 | 1885 | ; Turn on/off collapsing of bus ports in VCD dumpports output 1886 | DumpportsCollapse = 1 1887 | 1888 | ; Location of Multi-Level Verification Component (MVC) installation. 1889 | ; The default location is the product installation directory. 1890 | MvcHome = $MODEL_TECH/.. 1891 | 1892 | ; Location of InFact installation. The default is $MODEL_TECH/../../infact 1893 | ; 1894 | ; InFactHome = $MODEL_TECH/../../infact 1895 | 1896 | ; Initialize SystemVerilog enums using the base type's default value 1897 | ; instead of the leftmost value. 1898 | ; EnumBaseInit = 1 1899 | 1900 | ; Suppress file type registration. 1901 | ; SuppressFileTypeReg = 1 1902 | 1903 | ; Controls SystemVerilog Language Extensions. These options enable 1904 | ; some non-LRM compliant behavior. Valid extensions are "cfce", 1905 | ; SvExtensions = cfce 1906 | 1907 | ; Controls the formatting of '%p' and '%P' conversion specification, used in $display 1908 | ; and similar system tasks. 1909 | ; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. 1910 | ; The 'I' flag when present causes relevant data types to be expanded and indented into 1911 | ; a more readable format. 1912 | ; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). 1913 | ; 2. SVPrettyPrintFlags=L limits the output to lines. 1914 | ; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). 1915 | ; 3. SVPrettyPrintFlags=C limits the output to characters. 1916 | ; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). 1917 | ; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes 1918 | ; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). 1919 | ; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes 1920 | ; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). 1921 | ; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . 1922 | ; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). 1923 | ; 7. Items 1-6 above can be combined as a comma separated list. 1924 | ; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5) 1925 | ; SVPrettyPrintFlags=I4S 1926 | 1927 | [lmc] 1928 | ; The simulator's interface to Logic Modeling's SmartModel SWIFT software 1929 | libsm = $MODEL_TECH/libsm.sl 1930 | ; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) 1931 | ; libsm = $MODEL_TECH/libsm.dll 1932 | ; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) 1933 | ; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl 1934 | ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) 1935 | ; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o 1936 | ; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) 1937 | ; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so 1938 | ; Logic Modeling's SmartModel SWIFT software (Windows NT) 1939 | ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll 1940 | ; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) 1941 | ; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so 1942 | ; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) 1943 | ; libswift = $LMC_HOME/lib/linux.lib/libswift.so 1944 | 1945 | ; The simulator's interface to Logic Modeling's hardware modeler SFI software 1946 | libhm = $MODEL_TECH/libhm.sl 1947 | ; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) 1948 | ; libhm = $MODEL_TECH/libhm.dll 1949 | ; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) 1950 | ; libsfi = /lib/hp700/libsfi.sl 1951 | ; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) 1952 | ; libsfi = /lib/rs6000/libsfi.a 1953 | ; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) 1954 | ; libsfi = /lib/sun4.solaris/libsfi.so 1955 | ; Logic Modeling's hardware modeler SFI software (Windows NT) 1956 | ; libsfi = /lib/pcnt/lm_sfi.dll 1957 | ; Logic Modeling's hardware modeler SFI software (Linux) 1958 | ; libsfi = /lib/linux/libsfi.so 1959 | 1960 | [msg_system] 1961 | ; Change a message severity or suppress a message. 1962 | ; The format is: = [,...] 1963 | ; suppress can be used to achieve +nowarn functionality 1964 | ; The format is: suppress = ,,[,,...] 1965 | ; Examples: 1966 | suppress = 8780 ;an explanation can be had by running: verror 8780 1967 | ; note = 3009 1968 | ; warning = 3033 1969 | ; error = 3010,3016 1970 | ; fatal = 3016,3033 1971 | ; suppress = 3009,3016,3601 1972 | ; suppress = 3009,CNNODP,3601,TFMPC 1973 | ; suppress = 8683,8684 1974 | ; The command verror can be used to get the complete 1975 | ; description of a message. 1976 | 1977 | ; Control transcripting of Verilog display system task messages and 1978 | ; PLI/FLI print function call messages. The system tasks include 1979 | ; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They 1980 | ; also include the analogous file I/O tasks that write to STDOUT 1981 | ; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, 1982 | ; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default 1983 | ; is to have messages appear only in the transcript. The other 1984 | ; settings are to send messages to the wlf file only (messages that 1985 | ; are recorded in the wlf file can be viewed in the MsgViewer) or 1986 | ; to both the transcript and the wlf file. The valid values are 1987 | ; tran {transcript only (default)} 1988 | ; wlf {wlf file only} 1989 | ; both {transcript and wlf file} 1990 | ; displaymsgmode = tran 1991 | 1992 | ; Control transcripting of elaboration/runtime messages not 1993 | ; addressed by the displaymsgmode setting. The default is to 1994 | ; have messages appear only in the transcript. The other settings 1995 | ; are to send messages to the wlf file only (messages that are 1996 | ; recorded in the wlf file can be viewed in the MsgViewer) or to both 1997 | ; the transcript and the wlf file. The valid values are 1998 | ; tran {transcript only (default)} 1999 | ; wlf {wlf file only} 2000 | ; both {transcript and wlf file} 2001 | ; msgmode = tran 2002 | 2003 | ; Controls number of displays of a particluar message 2004 | ; default value is 5 2005 | ; MsgLimitCount = 5 2006 | 2007 | [utils] 2008 | ; Default Library Type (while creating a library with "vlib") 2009 | ; 0 - legacy library using subdirectories for design units 2010 | ; 2 - flat library 2011 | ; DefaultLibType = 2 2012 | 2013 | ; Flat Library Page Size (while creating a library with "vlib") 2014 | ; Set the size in bytes for flat library file pages. Libraries containing 2015 | ; very large files may benefit from a larger value. 2016 | ; FlatLibPageSize = 8192 2017 | 2018 | ; Flat Library Page Cleanup Percentage (while creating a library with "vlib") 2019 | ; Set the percentage of total pages deleted before library cleanup can occur. 2020 | ; This setting is applied together with FlatLibPageDeleteThreshold. 2021 | ; FlatLibPageDeletePercentage = 50 2022 | 2023 | ; Flat Library Page Cleanup Threshold (while creating a library with "vlib") 2024 | ; Set the number of pages deleted before library cleanup can occur. 2025 | ; This setting is applied together with FlatLibPageDeletePercentage. 2026 | ; FlatLibPageDeleteThreshold = 1000 2027 | 2028 | [Project] 2029 | ; Warning -- Do not edit the project properties directly. 2030 | ; Property names are dynamic in nature and property 2031 | ; values have special syntax. Changing property data directly 2032 | ; can result in a corrupt MPF file. All project properties 2033 | ; can be modified through project window dialogs. 2034 | Project_Version = 6 2035 | Project_DefaultLib = work 2036 | Project_SortMethod = unused 2037 | Project_Files_Count = 11 2038 | Project_File_0 = D:/Code/Repos/mips/Project_1/control/ALUctrl.v 2039 | Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder control last_compile 1463141985 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0 2040 | Project_File_1 = D:/Code/Repos/mips/Project_1/datapath/dm.v 2041 | Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1463560265 folder datapath cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0 2042 | Project_File_2 = D:/Code/Repos/mips/Project_1/datapath/ext.v 2043 | Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1463244921 folder datapath cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0 2044 | Project_File_3 = D:/Code/Repos/mips/Project_1/testbench.v 2045 | Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1463133920 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 2046 | Project_File_4 = D:/Code/Repos/mips/Project_1/datapath/alu.v 2047 | Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1463143954 folder datapath cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 2048 | Project_File_5 = D:/Code/Repos/mips/Project_1/datapath/im.v 2049 | Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1463553177 folder datapath cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0 2050 | Project_File_6 = D:/Code/Repos/mips/Project_1/datapath/mux.v 2051 | Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1463034043 folder datapath cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0 2052 | Project_File_7 = D:/Code/Repos/mips/Project_1/mips.v 2053 | Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1463536186 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 2054 | Project_File_8 = D:/Code/Repos/mips/Project_1/control/ctrl.v 2055 | Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder control last_compile 1463562406 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0 2056 | Project_File_9 = D:/Code/Repos/mips/Project_1/datapath/pc.v 2057 | Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1463128473 folder datapath cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0 2058 | Project_File_10 = D:/Code/Repos/mips/Project_1/datapath/regheap.v 2059 | Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1463559338 folder datapath cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0 2060 | Project_Sim_Count = 0 2061 | Project_Folder_Count = 2 2062 | Project_Folder_0 = control 2063 | Project_Folder_P_0 = folder {Top Level} 2064 | Project_Folder_1 = datapath 2065 | Project_Folder_P_1 = folder {Top Level} 2066 | Echo_Compile_Output = 0 2067 | Save_Compile_Report = 1 2068 | Project_Opt_Count = 0 2069 | ForceSoftPaths = 0 2070 | ProjectStatusDelay = 5000 2071 | VERILOG_DoubleClick = Edit 2072 | VERILOG_CustomDoubleClick = 2073 | SYSTEMVERILOG_DoubleClick = Edit 2074 | SYSTEMVERILOG_CustomDoubleClick = 2075 | VHDL_DoubleClick = Edit 2076 | VHDL_CustomDoubleClick = 2077 | PSL_DoubleClick = Edit 2078 | PSL_CustomDoubleClick = 2079 | TEXT_DoubleClick = Edit 2080 | TEXT_CustomDoubleClick = 2081 | SYSTEMC_DoubleClick = Edit 2082 | SYSTEMC_CustomDoubleClick = 2083 | TCL_DoubleClick = Edit 2084 | TCL_CustomDoubleClick = 2085 | MACRO_DoubleClick = Edit 2086 | MACRO_CustomDoubleClick = 2087 | VCD_DoubleClick = Edit 2088 | VCD_CustomDoubleClick = 2089 | SDF_DoubleClick = Edit 2090 | SDF_CustomDoubleClick = 2091 | XML_DoubleClick = Edit 2092 | XML_CustomDoubleClick = 2093 | LOGFILE_DoubleClick = Edit 2094 | LOGFILE_CustomDoubleClick = 2095 | UCDB_DoubleClick = Edit 2096 | UCDB_CustomDoubleClick = 2097 | TDB_DoubleClick = Edit 2098 | TDB_CustomDoubleClick = 2099 | UPF_DoubleClick = Edit 2100 | UPF_CustomDoubleClick = 2101 | PCF_DoubleClick = Edit 2102 | PCF_CustomDoubleClick = 2103 | PROJECT_DoubleClick = Edit 2104 | PROJECT_CustomDoubleClick = 2105 | VRM_DoubleClick = Edit 2106 | VRM_CustomDoubleClick = 2107 | DEBUGDATABASE_DoubleClick = Edit 2108 | DEBUGDATABASE_CustomDoubleClick = 2109 | DEBUGARCHIVE_DoubleClick = Edit 2110 | DEBUGARCHIVE_CustomDoubleClick = 2111 | Project_Major_Version = 10 2112 | Project_Minor_Version = 4 2113 | -------------------------------------------------------------------------------- /Project_1/code.txt: -------------------------------------------------------------------------------- 1 | 01095020 2 | ac0a0064 3 | 8c0c0064 4 | 018d5822 5 | 01f07024 6 | 02538825 7 | 02b6a02a 8 | 1109fff8 9 | 08000c00 10 | -------------------------------------------------------------------------------- /Project_1/control/ALUctrl.v: -------------------------------------------------------------------------------- 1 | module ALUctrl(ALUOp, funct, op); 2 | input [1:0] ALUOp; 3 | input [5:0] funct; 4 | output reg [3:0] op; 5 | 6 | parameter ADD = 6'b100000, 7 | SUB = 6'b100010, 8 | AND = 6'b100100, 9 | OR = 6'b100101, 10 | SLT = 6'b101010; 11 | 12 | always @(*) begin 13 | case (ALUOp) 14 | 2'b00 : begin 15 | op <= 4'b0010; 16 | end 17 | 2'b01 : begin 18 | op <= 4'b0110; 19 | end 20 | 2'b10 : begin 21 | case (funct) 22 | ADD : begin 23 | op <= 4'b0010; 24 | end 25 | SUB : begin 26 | op <= 4'b0110; 27 | end 28 | AND : begin 29 | op <= 4'b0000; 30 | end 31 | OR : begin 32 | op <= 4'b0001; 33 | end 34 | SLT : begin 35 | op <= 4'b0111; 36 | end 37 | endcase 38 | end 39 | endcase 40 | end 41 | endmodule -------------------------------------------------------------------------------- /Project_1/control/ctrl.v: -------------------------------------------------------------------------------- 1 | module ctrl(op, RegDst, RegWrite, ALUSrc, MemRead, MemWrite, MemtoReg, Jump, Branch, ALUOp); 2 | input [5:0] op; 3 | output reg RegDst; 4 | output reg RegWrite; 5 | output reg ALUSrc; 6 | output reg MemRead; 7 | output reg MemWrite; 8 | output reg MemtoReg; 9 | output reg Jump; 10 | output reg Branch; 11 | output reg [1:0] ALUOp; 12 | 13 | parameter R = 6'b000000, 14 | LW = 6'b100011, 15 | SW = 6'b101011, 16 | BEQ = 6'b000100, 17 | J = 6'b000010; 18 | 19 | always @(*) begin 20 | case (op) 21 | R: begin 22 | RegDst = 1; 23 | ALUSrc = 0; 24 | MemtoReg = 0; 25 | RegWrite = 1; 26 | MemRead = 0; 27 | MemWrite = 0; 28 | Jump = 1; 29 | Branch = 0; 30 | ALUOp = 2'b10; 31 | end 32 | 33 | LW: begin 34 | RegDst = 0; 35 | ALUSrc = 1; 36 | MemtoReg = 1; 37 | RegWrite = 1; 38 | MemRead = 1; 39 | MemWrite = 0; 40 | Jump = 1; 41 | Branch = 0; 42 | ALUOp = 2'b00; 43 | end 44 | 45 | SW: begin 46 | ALUSrc = 1; 47 | RegWrite = 0; 48 | MemRead = 0; 49 | MemWrite = 1; 50 | Jump = 1; 51 | Branch = 0; 52 | ALUOp = 2'b00; 53 | end 54 | 55 | BEQ: begin 56 | ALUSrc = 0; 57 | RegWrite = 0; 58 | MemRead = 0; 59 | MemWrite = 0; 60 | Jump = 1; 61 | Branch = 1; 62 | ALUOp = 2'b01; 63 | end 64 | 65 | J: begin 66 | ALUSrc = 0; 67 | RegWrite = 0; 68 | MemRead = 0; 69 | MemWrite = 0; 70 | Jump = 0; 71 | Branch = 0; 72 | end 73 | endcase 74 | end 75 | 76 | endmodule -------------------------------------------------------------------------------- /Project_1/datapath/alu.v: -------------------------------------------------------------------------------- 1 | module alu(op, a, b, zero, dout); 2 | input [3:0] op; 3 | input [31:0] a; 4 | input [31:0] b; 5 | output zero; 6 | output reg [31:0] dout; 7 | 8 | assign zero = dout == 0 ? 1 : 0; 9 | always @(op or a or b) begin 10 | case(op) 11 | 4'b0010 : dout = a + b; 12 | 4'b0110 : dout = a - b; 13 | 4'b0001 : dout = a | b; 14 | 4'b0000 : dout = a & b; 15 | 4'b0111 : begin 16 | dout = a < b ? 1 : 0; 17 | end 18 | endcase 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /Project_1/datapath/dm.v: -------------------------------------------------------------------------------- 1 | module dm_4k(addr, din, we, re, clk, dout); 2 | input [11:2] addr ; // address bus 3 | input [31:0] din ; // 32-bit input data 4 | input we ; // memory write enable 5 | input re ; // memory read enable 6 | input clk ; // clock 7 | output reg [31:0] dout ; // 32-bit memory output 8 | 9 | reg [31:0] dm[1023:0] ; 10 | 11 | always @(posedge clk) begin 12 | if (we) begin 13 | dm[addr[11:2]][31:0] <= din[31:0]; 14 | end 15 | end 16 | 17 | always @(addr or re) begin 18 | if (re) begin 19 | dout[31:0] <= dm[addr[11:2]][31:0]; 20 | end 21 | end 22 | endmodule -------------------------------------------------------------------------------- /Project_1/datapath/ext.v: -------------------------------------------------------------------------------- 1 | module ext #(parameter W = 16) (din, dout); 2 | input [W-1:0] din; 3 | output [31:0] dout; 4 | 5 | assign dout = {{32-W{din[W-1]}}, din}; 6 | endmodule -------------------------------------------------------------------------------- /Project_1/datapath/im.v: -------------------------------------------------------------------------------- 1 | module im_4k( addr, dout ) ; 2 | input [11:2] addr ; // address bus 3 | output [31:0] dout ; // 32-bit memory output 4 | 5 | reg [31:0] im[1023:0] ; 6 | 7 | initial 8 | begin 9 | $readmemh("code.txt", im); 10 | end 11 | 12 | assign dout = im[addr[11:2]][31:0]; 13 | endmodule -------------------------------------------------------------------------------- /Project_1/datapath/mux.v: -------------------------------------------------------------------------------- 1 | module mux2 #(parameter W = 32) (a, b, s, dout); 2 | input [W-1:0] a; 3 | input [W-1:0] b; 4 | input s; 5 | output [W-1:0] dout; 6 | 7 | assign dout = s ? b : a; 8 | endmodule -------------------------------------------------------------------------------- /Project_1/datapath/pc.v: -------------------------------------------------------------------------------- 1 | module pc (clk, rst, data, dout); 2 | input clk; 3 | input rst; 4 | input [31:0] data; 5 | output reg [31:0] dout; 6 | 7 | always @(posedge clk) 8 | begin 9 | if(rst) 10 | dout[31:0] <= {32'h0000_3000}; 11 | else 12 | dout <= data; 13 | end 14 | endmodule 15 | -------------------------------------------------------------------------------- /Project_1/datapath/regheap.v: -------------------------------------------------------------------------------- 1 | module regheap(clk, we, rreg1, rreg2, wreg, wdata, rdata1, rdata2); 2 | input clk; 3 | input we; 4 | input [4:0] rreg1, rreg2, wreg; 5 | input [31:0] wdata; 6 | output [31:0] rdata1, rdata2; 7 | 8 | reg [31:0] rh[31:0]; 9 | 10 | initial begin 11 | rh[8] = 32'b0000_0000_0000_0000_0000_0000_0000_0001; 12 | rh[9] = 32'b0000_0000_0000_0000_0000_0000_0000_0010; 13 | 14 | rh[13] = 32'b0000_0000_0000_0000_0000_0000_0010_0000; 15 | 16 | rh[15] = 32'b0000_0000_0000_0000_0011_0000_0000_0001; 17 | rh[16] = 32'b0000_0000_0000_0000_0110_0000_0000_0010; 18 | 19 | rh[18] = 32'b0000_0000_0000_1010_0000_0000_0000_0001; 20 | rh[19] = 32'b0000_0000_0000_1001_0000_0000_0000_0010; 21 | 22 | rh[21] = 32'b0000_0000_0010_0000_0000_0000_0000_0001; 23 | rh[22] = 32'b0000_0000_0100_0000_0000_0000_0000_0010; 24 | end 25 | 26 | always @(posedge clk) begin 27 | if (we) begin 28 | rh[wreg] <= wdata; 29 | $display(rh[10]); 30 | end 31 | end 32 | 33 | assign rdata1 = (rreg1 != 0)? rh[rreg1]:0; 34 | assign rdata2 = (rreg2 != 0)? rh[rreg2]:0; 35 | endmodule -------------------------------------------------------------------------------- /Project_1/mips.v: -------------------------------------------------------------------------------- 1 | module mips(clk, rst) ; 2 | input clk ; // clock 3 | input rst ; // reset 4 | 5 | wire [31:0] pc_now; 6 | wire [31:0] pc_tmp; 7 | wire [31:0] pc_next; 8 | wire [31:0] pc_plus_4; 9 | wire [31:0] pc_br; 10 | wire [31:0] ins; 11 | wire [4:0] wreg; 12 | wire [31:0] rdata1; 13 | wire [31:0] rdata2; 14 | wire [31:0] const_or_addr; 15 | wire [31:0] ALUSrc_data1; 16 | wire [31:0] ALUSrc_data2; 17 | wire zero; 18 | wire [31:0] ALU_res; 19 | wire [31:0] rdata; 20 | wire [31:0] wdata; 21 | wire [3:0] op; 22 | 23 | 24 | wire RegDst; 25 | wire RegWrite; 26 | wire ALUSrc; 27 | wire MemRead; 28 | wire MemWrite; 29 | wire MemtoReg; 30 | wire Jump; 31 | wire Branch; 32 | wire [1:0] ALUOp; 33 | 34 | pc pc(.clk(clk), .rst(rst), .data(pc_next), .dout(pc_now)); 35 | assign pc_plus_4 = pc_now + 4; 36 | 37 | 38 | alu pc_alu(.op(4'b0010), .a(pc_plus_4), .b({const_or_addr[29:0], 2'b00}), .dout(pc_br)); 39 | mux2 #(32) br_mux(.a(pc_plus_4), .b(pc_br), .s(Branch & zero), .dout(pc_tmp)); 40 | mux2 #(32) j_mux(.a({pc_plus_4[31:28],ins[25:0],2'b00}), .b(pc_tmp), .s(Jump), .dout(pc_next)); 41 | im_4k im(.addr(pc_now[11:2]), .dout(ins)); 42 | 43 | ctrl ctrl( .op(ins[31:26]), .RegDst(RegDst), .RegWrite(RegWrite), .ALUSrc(ALUSrc), 44 | .MemRead(MemRead), .MemWrite(MemWrite), .MemtoReg(MemtoReg), 45 | .Jump(Jump), .Branch(Branch), .ALUOp(ALUOp)); 46 | 47 | mux2 #(5) wreg_mux(.a(ins[20:16]), .b(ins[15:11]), .s(RegDst), .dout(wreg)); 48 | regheap regheap(.clk(clk), .we(RegWrite), .rreg1(ins[25:21]), .rreg2(ins[20:16]), 49 | .wreg(wreg), .wdata(wdata), .rdata1(rdata1), .rdata2(rdata2)); 50 | ext #(16) ext(.din(ins[15:0]), .dout(const_or_addr)); 51 | assign ALUSrc_data1 = rdata1; 52 | mux2 #(32) ALUSrc_mux(.a(rdata2), .b(const_or_addr), .s(ALUSrc), .dout(ALUSrc_data2)); 53 | ALUctrl ALUctrl(.ALUOp(ALUOp), .funct(ins[5:0]), .op(op)); 54 | alu alu(.op(op), .a(ALUSrc_data1), .b(ALUSrc_data2), .zero(zero), .dout(ALU_res)); 55 | dm_4k dm(.addr(ALU_res), .din(rdata2), .we(MemWrite), .re(MemRead), .clk(clk), .dout(rdata)); 56 | mux2 #(32) RegSrc_mux(.a(ALU_res), .b(rdata), .s(MemtoReg), .dout(wdata)); 57 | 58 | 59 | endmodule -------------------------------------------------------------------------------- /Project_1/testbench.v: -------------------------------------------------------------------------------- 1 | module testbench(); 2 | reg clk, rst; 3 | 4 | initial begin 5 | clk = 0; 6 | rst = 1; 7 | #12 rst = 0; 8 | end 9 | 10 | always #10 clk = ~clk; 11 | 12 | mips mips(clk, rst); 13 | endmodule -------------------------------------------------------------------------------- /Project_1/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HaleLu/mips/309193bf0c709cfe71abf270c26272fc4b3410f2/Project_1/vsim.wlf -------------------------------------------------------------------------------- /Project_1/work/_info: -------------------------------------------------------------------------------- 1 | m255 2 | K4 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/Project_1/work/_lib1_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HaleLu/mips/309193bf0c709cfe71abf270c26272fc4b3410f2/Project_1/work/_lib1_0.qpg -------------------------------------------------------------------------------- /Project_1/work/_lib1_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HaleLu/mips/309193bf0c709cfe71abf270c26272fc4b3410f2/Project_1/work/_lib1_0.qtl -------------------------------------------------------------------------------- /Project_1/work/_vmake: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z0 4 | cModel Technology 5 | -------------------------------------------------------------------------------- /Project_2/Project_2.cr.mti: -------------------------------------------------------------------------------- 1 | D:/Code/Repos/mips/Project_2/midreg/MEM_WB.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/midreg/MEM_WB.v 2 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 3 | -- Compiling module MEM_WB 4 | 5 | Top level modules: 6 | MEM_WB 7 | 8 | } {} {}} D:/Code/Repos/mips/Project_2/control/ALUctrl.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/control/ALUctrl.v 9 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 10 | -- Compiling module ALUctrl 11 | 12 | Top level modules: 13 | ALUctrl 14 | 15 | } {} {}} D:/Code/Repos/mips/Project_2/testbench.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/testbench.v 16 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 17 | -- Compiling module testbench 18 | 19 | Top level modules: 20 | testbench 21 | 22 | } {} {}} D:/Code/Repos/mips/Project_2/control/hazardDetectionUnit.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/control/hazardDetectionUnit.v 23 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 24 | -- Compiling module hdu 25 | -- Compiling module br_hdu 26 | 27 | Top level modules: 28 | hdu 29 | br_hdu 30 | 31 | } {} {}} D:/Code/Repos/mips/Project_2/datapath/regheap.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/datapath/regheap.v 32 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 33 | -- Compiling module regheap 34 | 35 | Top level modules: 36 | regheap 37 | 38 | } {} {}} D:/Code/Repos/mips/Project_2/midreg/EX_MEM.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/midreg/EX_MEM.v 39 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 40 | -- Compiling module EX_MEM 41 | 42 | Top level modules: 43 | EX_MEM 44 | 45 | } {} {}} D:/Code/Repos/mips/Project_2/datapath/im.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/datapath/im.v 46 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 47 | -- Compiling module im_4k 48 | 49 | Top level modules: 50 | im_4k 51 | 52 | } {} {}} D:/Code/Repos/mips/Project_2/datapath/dm.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/datapath/dm.v 53 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 54 | -- Compiling module dm_4k 55 | 56 | Top level modules: 57 | dm_4k 58 | 59 | } {} {}} D:/Code/Repos/mips/Project_2/datapath/ext.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/datapath/ext.v 60 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 61 | -- Compiling module ext 62 | 63 | Top level modules: 64 | ext 65 | 66 | } {} {}} D:/Code/Repos/mips/Project_2/midreg/ID_EX.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/midreg/ID_EX.v 67 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 68 | -- Compiling module ID_EX 69 | 70 | Top level modules: 71 | ID_EX 72 | 73 | } {} {}} D:/Code/Repos/mips/Project_2/datapath/mux.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/datapath/mux.v 74 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 75 | -- Compiling module mux2 76 | -- Compiling module mux3 77 | 78 | Top level modules: 79 | mux2 80 | mux3 81 | 82 | } {} {}} D:/Code/Repos/mips/Project_2/datapath/alu.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/datapath/alu.v 83 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 84 | -- Compiling module alu 85 | 86 | Top level modules: 87 | alu 88 | 89 | } {} {}} D:/Code/Repos/mips/Project_2/mips.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/mips.v 90 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 91 | -- Compiling module mips 92 | 93 | Top level modules: 94 | mips 95 | 96 | } {} {}} D:/Code/Repos/mips/Project_2/datapath/pc.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/datapath/pc.v 97 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 98 | -- Compiling module pc 99 | 100 | Top level modules: 101 | pc 102 | 103 | } {} {}} D:/Code/Repos/mips/Project_2/midreg/IF_ID.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/midreg/IF_ID.v 104 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 105 | -- Compiling module IF_ID 106 | 107 | Top level modules: 108 | IF_ID 109 | 110 | } {} {}} D:/Code/Repos/mips/Project_2/control/forwardingUnit.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/control/forwardingUnit.v 111 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 112 | -- Compiling module fu 113 | 114 | Top level modules: 115 | fu 116 | 117 | } {} {}} D:/Code/Repos/mips/Project_2/control/ctrl.v {1 {vlog -work work -stats=none D:/Code/Repos/mips/Project_2/control/ctrl.v 118 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 119 | -- Compiling module ctrl 120 | 121 | Top level modules: 122 | ctrl 123 | 124 | } {} {}} 125 | -------------------------------------------------------------------------------- /Project_2/code.txt: -------------------------------------------------------------------------------- 1 | 20080001 2 | 20090002 3 | 200d0010 4 | 200f0051 5 | 21f00021 6 | 201200c1 7 | 00005020 8 | 010a4020 9 | 0109502a 10 | 11400005 11 | 01095820 12 | ac0b0064 13 | 8c0c0064 14 | 018d5822 15 | 08000c07 16 | 01f07024 17 | 01d28825 18 | ac110064 19 | 8c130064 20 | 1233fffb 21 | -------------------------------------------------------------------------------- /Project_2/control/ALUctrl.v: -------------------------------------------------------------------------------- 1 | module ALUctrl(ALUOp, funct, op); 2 | input [1:0] ALUOp; 3 | input [5:0] funct; 4 | output reg [3:0] op; 5 | 6 | parameter ADD = 6'b100000, 7 | SUB = 6'b100010, 8 | AND = 6'b100100, 9 | OR = 6'b100101, 10 | SLT = 6'b101010; 11 | 12 | always @(*) begin 13 | case (ALUOp) 14 | 2'b00 : begin 15 | op <= 4'b0010; 16 | end 17 | 2'b01 : begin 18 | op <= 4'b0110; 19 | end 20 | 2'b10 : begin 21 | case (funct) 22 | ADD : begin 23 | op <= 4'b0010; 24 | end 25 | SUB : begin 26 | op <= 4'b0110; 27 | end 28 | AND : begin 29 | op <= 4'b0000; 30 | end 31 | OR : begin 32 | op <= 4'b0001; 33 | end 34 | SLT : begin 35 | op <= 4'b0111; 36 | end 37 | endcase 38 | end 39 | endcase 40 | end 41 | endmodule -------------------------------------------------------------------------------- /Project_2/control/ctrl.v: -------------------------------------------------------------------------------- 1 | module ctrl(op, RegDst, RegWrite, ALUSrc, MemRead, MemWrite, MemtoReg, Jump, Branch, ALUOp); 2 | input [5:0] op; 3 | output reg RegDst; 4 | output reg RegWrite; 5 | output reg ALUSrc; 6 | output reg MemRead; 7 | output reg MemWrite; 8 | output reg MemtoReg; 9 | output reg Jump; 10 | output reg Branch; 11 | output reg [1:0] ALUOp; 12 | 13 | parameter R = 6'b000000, 14 | LW = 6'b100011, 15 | SW = 6'b101011, 16 | BEQ = 6'b000100, 17 | J = 6'b000010, 18 | ADDI = 6'b001000; 19 | 20 | initial begin 21 | RegDst = 0; 22 | ALUSrc = 0; 23 | MemtoReg = 0; 24 | RegWrite = 0; 25 | MemRead = 0; 26 | MemWrite = 0; 27 | Jump = 0; 28 | Branch = 0; 29 | ALUOp = 2'b00; 30 | end 31 | 32 | always @(*) begin 33 | case (op) 34 | R: begin 35 | RegDst = 1; 36 | ALUSrc = 0; 37 | MemtoReg = 0; 38 | RegWrite = 1; 39 | MemRead = 0; 40 | MemWrite = 0; 41 | Jump = 0; 42 | Branch = 0; 43 | ALUOp = 2'b10; 44 | end 45 | 46 | LW: begin 47 | RegDst = 0; 48 | ALUSrc = 1; 49 | MemtoReg = 1; 50 | RegWrite = 1; 51 | MemRead = 1; 52 | MemWrite = 0; 53 | Jump = 0; 54 | Branch = 0; 55 | ALUOp = 2'b00; 56 | end 57 | 58 | SW: begin 59 | ALUSrc = 1; 60 | RegWrite = 0; 61 | MemRead = 0; 62 | MemWrite = 1; 63 | Jump = 0; 64 | Branch = 0; 65 | ALUOp = 2'b00; 66 | end 67 | 68 | BEQ: begin 69 | ALUSrc = 0; 70 | RegWrite = 0; 71 | MemRead = 0; 72 | MemWrite = 0; 73 | Jump = 0; 74 | Branch = 1; 75 | ALUOp = 2'b01; 76 | end 77 | 78 | J: begin 79 | ALUSrc = 0; 80 | RegWrite = 0; 81 | MemRead = 0; 82 | MemWrite = 0; 83 | Jump = 1; 84 | Branch = 0; 85 | end 86 | 87 | ADDI: begin 88 | RegDst = 0; 89 | ALUSrc = 1; 90 | MemtoReg = 0; 91 | RegWrite = 1; 92 | MemRead = 0; 93 | MemWrite = 0; 94 | Jump = 0; 95 | Branch = 0; 96 | ALUOp = 2'b00; 97 | end 98 | 99 | default: begin 100 | RegDst = 0; 101 | ALUSrc = 0; 102 | MemtoReg = 0; 103 | RegWrite = 0; 104 | MemRead = 0; 105 | MemWrite = 0; 106 | Jump = 0; 107 | Branch = 0; 108 | ALUOp = 2'b00; 109 | end 110 | endcase 111 | end 112 | 113 | endmodule -------------------------------------------------------------------------------- /Project_2/control/forwardingUnit.v: -------------------------------------------------------------------------------- 1 | module fu(EX_rs, EX_rt, MEM_RegWrite, MEM_rd, WB_RegWrite, WB_rd, ForwardA, ForwardB); 2 | input [4:0] EX_rs; 3 | input [4:0] EX_rt; 4 | input MEM_RegWrite; 5 | input [4:0] MEM_rd; 6 | input WB_RegWrite; 7 | input [4:0] WB_rd; 8 | 9 | output reg [1:0] ForwardA; 10 | output reg [1:0] ForwardB; 11 | 12 | always @(*) begin 13 | if (MEM_RegWrite && MEM_rd != 0 && MEM_rd == EX_rs) begin 14 | ForwardA <= 2'b10; 15 | end 16 | else if (WB_RegWrite && WB_rd != 0 && WB_rd == EX_rs) begin 17 | ForwardA <= 2'b01; 18 | end 19 | else begin 20 | ForwardA <= 2'b00; 21 | end 22 | 23 | if (MEM_RegWrite && MEM_rd != 0 && MEM_rd == EX_rt) begin 24 | ForwardB <= 2'b10; 25 | end 26 | else if (WB_RegWrite && WB_rd != 0 && WB_rd == EX_rt) begin 27 | ForwardB <= 2'b01; 28 | end 29 | else begin 30 | ForwardB <= 2'b00; 31 | end 32 | end 33 | 34 | endmodule -------------------------------------------------------------------------------- /Project_2/control/hazardDetectionUnit.v: -------------------------------------------------------------------------------- 1 | module hdu(EX_MemRead, EX_rt, ID_rs, ID_rt, stall); 2 | input EX_MemRead; 3 | input [4:0] EX_rt; 4 | input [4:0] ID_rs; 5 | input [4:0] ID_rt; 6 | 7 | output stall; 8 | 9 | assign stall = (EX_MemRead && ((EX_rt == ID_rs) || (EX_rt == ID_rt)))? 1 : 0; 10 | endmodule 11 | 12 | module br_hdu(Branch, EX_RegWrite, EX_wreg, MEM_MemRead, MEM_wreg, ID_rs, ID_rt, stall); 13 | input Branch; 14 | input EX_RegWrite; 15 | input MEM_MemRead; 16 | input [4:0] EX_wreg; 17 | input [4:0] MEM_wreg; 18 | input [4:0] ID_rs; 19 | input [4:0] ID_rt; 20 | 21 | output stall; 22 | 23 | assign stall = Branch && ( (EX_RegWrite && ((EX_wreg == ID_rs) || (EX_wreg == ID_rt))) || 24 | (MEM_MemRead && ((MEM_wreg == ID_rs) || (MEM_wreg == ID_rt))) ) ? 1 : 0; 25 | endmodule -------------------------------------------------------------------------------- /Project_2/datapath/alu.v: -------------------------------------------------------------------------------- 1 | module alu(op, a, b, zero, dout); 2 | input [3:0] op; 3 | input [31:0] a; 4 | input [31:0] b; 5 | output zero; 6 | output reg [31:0] dout; 7 | 8 | assign zero = dout == 0 ? 1 : 0; 9 | always @(op or a or b) begin 10 | case(op) 11 | 4'b0010 : dout = a + b; 12 | 4'b0110 : dout = a - b; 13 | 4'b0001 : dout = a | b; 14 | 4'b0000 : dout = a & b; 15 | 4'b0111 : begin 16 | dout = a < b ? 1 : 0; 17 | end 18 | endcase 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /Project_2/datapath/dm.v: -------------------------------------------------------------------------------- 1 | module dm_4k(addr, din, we, re, clk, dout); 2 | input [11:2] addr ; // address bus 3 | input [31:0] din ; // 32-bit input data 4 | input we ; // memory write enable 5 | input re ; // memory read enable 6 | input clk ; // clock 7 | output reg [31:0] dout ; // 32-bit memory output 8 | 9 | reg [31:0] dm[1023:0] ; 10 | 11 | always @(posedge clk) begin 12 | if (we) begin 13 | dm[addr[11:2]][31:0] <= din[31:0]; 14 | end 15 | end 16 | 17 | always @(addr or re) begin 18 | if (re) begin 19 | dout[31:0] <= dm[addr[11:2]][31:0]; 20 | end 21 | end 22 | endmodule -------------------------------------------------------------------------------- /Project_2/datapath/ext.v: -------------------------------------------------------------------------------- 1 | module ext #(parameter W = 16) (din, dout); 2 | input [W-1:0] din; 3 | output [31:0] dout; 4 | 5 | assign dout = {{32-W{din[W-1]}}, din}; 6 | endmodule -------------------------------------------------------------------------------- /Project_2/datapath/im.v: -------------------------------------------------------------------------------- 1 | module im_4k( addr, dout ) ; 2 | input [11:2] addr ; // address bus 3 | output [31:0] dout ; // 32-bit memory output 4 | 5 | reg [31:0] im[1023:0] ; 6 | 7 | initial 8 | begin 9 | $readmemh("code.txt", im); 10 | end 11 | 12 | assign dout = im[addr[11:2]][31:0]; 13 | endmodule -------------------------------------------------------------------------------- /Project_2/datapath/mux.v: -------------------------------------------------------------------------------- 1 | module mux2 #(parameter W = 32) (a, b, s, dout); 2 | input [W-1:0] a; 3 | input [W-1:0] b; 4 | input s; 5 | output [W-1:0] dout; 6 | 7 | assign dout = s ? b : a; 8 | endmodule 9 | 10 | module mux3 #(parameter W = 32) (a, b, c, s, dout); 11 | input [W-1:0] a; 12 | input [W-1:0] b; 13 | input [W-1:0] c; 14 | input [1:0] s; 15 | output [W-1:0] dout; 16 | 17 | assign dout = (s==2'b00) ? a : (s==2'b01) ? b : c; 18 | endmodule -------------------------------------------------------------------------------- /Project_2/datapath/pc.v: -------------------------------------------------------------------------------- 1 | module pc (clk, rst, en, data, dout); 2 | input clk; 3 | input rst; 4 | input en; 5 | input [31:0] data; 6 | output reg [31:0] dout; 7 | 8 | always @(posedge clk) 9 | begin 10 | if(rst) 11 | dout[31:0] <= {32'h0000_3000}; 12 | else 13 | if (en) begin 14 | dout <= data; 15 | end 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /Project_2/datapath/regheap.v: -------------------------------------------------------------------------------- 1 | module regheap(clk, we, rreg1, rreg2, wreg, wdata, rdata1, rdata2); 2 | input clk; 3 | input we; 4 | input [4:0] rreg1, rreg2, wreg; 5 | input [31:0] wdata; 6 | output [31:0] rdata1, rdata2; 7 | 8 | reg [31:0] rh[31:0]; 9 | 10 | initial begin 11 | // Set all registers to 0 12 | rh[0] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 13 | rh[1] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 14 | rh[2] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 15 | rh[3] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 16 | rh[4] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 17 | rh[5] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 18 | rh[6] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 19 | rh[7] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 20 | rh[8] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 21 | rh[9] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 22 | rh[10] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 23 | rh[11] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 24 | rh[12] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 25 | rh[13] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 26 | rh[14] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 27 | rh[15] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 28 | rh[16] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 29 | rh[17] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 30 | rh[18] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 31 | rh[19] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 32 | rh[20] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 33 | rh[21] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 34 | rh[22] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 35 | rh[23] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 36 | rh[24] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 37 | rh[25] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 38 | rh[26] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 39 | rh[27] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 40 | rh[28] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 41 | rh[29] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 42 | rh[30] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 43 | rh[31] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 44 | end 45 | 46 | always @(posedge clk) begin 47 | if (we) begin 48 | rh[wreg] <= (wreg != 0)? wdata:0; 49 | end 50 | end 51 | 52 | assign rdata1 = (rreg1 != 0)? rh[rreg1]:0; 53 | assign rdata2 = (rreg2 != 0)? rh[rreg2]:0; 54 | endmodule -------------------------------------------------------------------------------- /Project_2/midreg/EX_MEM.v: -------------------------------------------------------------------------------- 1 | module EX_MEM(clk, EX_MemtoReg , EX_RegWrite , EX_MemRead , EX_MemWrite , EX_ALU_res , EX_rdata2 , EX_wreg, 2 | MEM_MemtoReg, MEM_RegWrite, MEM_MemRead, MEM_MemWrite, MEM_ALU_res, MEM_rdata2, MEM_wreg); 3 | input clk; 4 | 5 | input EX_MemtoReg; 6 | input EX_RegWrite; 7 | input EX_MemRead; 8 | input EX_MemWrite; 9 | input [31:0] EX_ALU_res; 10 | input [31:0] EX_rdata2; 11 | input [4:0] EX_wreg; 12 | 13 | output MEM_MemtoReg; 14 | output MEM_RegWrite; 15 | output MEM_MemRead; 16 | output MEM_MemWrite; 17 | output [31:0] MEM_ALU_res; 18 | output [31:0] MEM_rdata2; 19 | output [4:0] MEM_wreg; 20 | 21 | reg MemtoReg; 22 | reg RegWrite; 23 | reg MemRead; 24 | reg MemWrite; 25 | reg [31:0] ALU_res; 26 | reg [31:0] rdata2; 27 | reg [4:0] wreg; 28 | 29 | initial begin 30 | MemtoReg = 0; 31 | RegWrite = 0; 32 | MemRead = 0; 33 | MemWrite = 0; 34 | ALU_res = 0; 35 | rdata2 = 0; 36 | wreg = 0; 37 | end 38 | 39 | always @(posedge clk) begin 40 | MemtoReg <= EX_MemtoReg; 41 | RegWrite <= EX_RegWrite; 42 | MemRead <= EX_MemRead; 43 | MemWrite <= EX_MemWrite; 44 | ALU_res <= EX_ALU_res; 45 | rdata2 <= EX_rdata2; 46 | wreg <= EX_wreg; 47 | end 48 | 49 | assign MEM_MemtoReg = MemtoReg; 50 | assign MEM_RegWrite = RegWrite; 51 | assign MEM_MemRead = MemRead; 52 | assign MEM_MemWrite = MemWrite; 53 | assign MEM_ALU_res = ALU_res; 54 | assign MEM_rdata2 = rdata2; 55 | assign MEM_wreg = wreg; 56 | endmodule -------------------------------------------------------------------------------- /Project_2/midreg/ID_EX.v: -------------------------------------------------------------------------------- 1 | module ID_EX(clk, ID_RegDst, ID_RegWrite, ID_MemRead, ID_MemWrite, ID_ALUSrc, ID_MemtoReg, ID_ALUOp, ID_rdata1, ID_rdata2, ID_const_or_addr, ID_rs, ID_rt, ID_rd, 2 | EX_RegDst, EX_RegWrite, EX_MemRead, EX_MemWrite, EX_ALUSrc, EX_MemtoReg, EX_ALUOp, EX_rdata1, EX_rdata2, EX_const_or_addr, EX_rs, EX_rt, EX_rd); 3 | input clk; 4 | 5 | input ID_RegDst; 6 | input ID_RegWrite; 7 | input ID_MemRead; 8 | input ID_MemWrite; 9 | input ID_ALUSrc; 10 | input ID_MemtoReg; 11 | input [1:0] ID_ALUOp; 12 | input [31:0] ID_rdata1; 13 | input [31:0] ID_rdata2; 14 | input [31:0] ID_const_or_addr; 15 | input [4:0] ID_rs; 16 | input [4:0] ID_rt; 17 | input [4:0] ID_rd; 18 | 19 | output EX_RegDst; 20 | output EX_RegWrite; 21 | output EX_MemRead; 22 | output EX_MemWrite; 23 | output EX_ALUSrc; 24 | output EX_MemtoReg; 25 | output [1:0] EX_ALUOp; 26 | output [31:0] EX_rdata1; 27 | output [31:0] EX_rdata2; 28 | output [31:0] EX_const_or_addr; 29 | output [4:0] EX_rs; 30 | output [4:0] EX_rt; 31 | output [4:0] EX_rd; 32 | 33 | reg RegDst; 34 | reg RegWrite; 35 | reg MemRead; 36 | reg MemWrite; 37 | reg ALUSrc; 38 | reg MemtoReg; 39 | reg [1:0] ALUOp; 40 | reg [31:0] rdata1; 41 | reg [31:0] rdata2; 42 | reg [31:0] const_or_addr; 43 | reg [4:0] rs; 44 | reg [4:0] rt; 45 | reg [4:0] rd; 46 | 47 | initial begin 48 | RegDst = 0; 49 | RegWrite = 0; 50 | MemRead = 0; 51 | MemWrite = 0; 52 | ALUSrc = 0; 53 | MemtoReg = 0; 54 | ALUOp = 0; 55 | rdata1 = 0; 56 | rdata2 = 0; 57 | const_or_addr = 0; 58 | rs = 0; 59 | rt = 0; 60 | rd = 0; 61 | end 62 | 63 | always @(posedge clk) begin 64 | RegDst <= ID_RegDst; 65 | RegWrite <= ID_RegWrite; 66 | MemRead <= ID_MemRead; 67 | MemWrite <= ID_MemWrite; 68 | ALUSrc <= ID_ALUSrc; 69 | MemtoReg <= ID_MemtoReg; 70 | ALUOp <= ID_ALUOp; 71 | rdata1 <= ID_rdata1; 72 | rdata2 <= ID_rdata2; 73 | const_or_addr <= ID_const_or_addr; 74 | rs <= ID_rs; 75 | rt <= ID_rt; 76 | rd <= ID_rd; 77 | end 78 | 79 | assign EX_RegDst = RegDst; 80 | assign EX_RegWrite = RegWrite; 81 | assign EX_MemRead = MemRead; 82 | assign EX_MemWrite = MemWrite; 83 | assign EX_ALUSrc = ALUSrc; 84 | assign EX_MemtoReg = MemtoReg; 85 | assign EX_ALUOp = ALUOp; 86 | assign EX_rdata1 = rdata1; 87 | assign EX_rdata2 = rdata2; 88 | assign EX_const_or_addr = const_or_addr; 89 | assign EX_rs = rs; 90 | assign EX_rt = rt; 91 | assign EX_rd = rd; 92 | endmodule -------------------------------------------------------------------------------- /Project_2/midreg/IF_ID.v: -------------------------------------------------------------------------------- 1 | module IF_ID(clk, en, rst, IF_pc_plus_4, IF_ins, 2 | ID_pc_plus_4, ID_ins); 3 | input clk; 4 | input en; 5 | input rst; 6 | input [31:0] IF_pc_plus_4; 7 | input [31:0] IF_ins; 8 | 9 | output [31:0] ID_pc_plus_4; 10 | output [31:0] ID_ins; 11 | 12 | reg [31:0] pc_plus_4; 13 | reg [31:0] ins; 14 | 15 | initial begin 16 | pc_plus_4 = 0; 17 | ins = 0; 18 | end 19 | 20 | always @(posedge clk) begin 21 | if (rst) begin 22 | pc_plus_4 = 0; 23 | ins = 0; 24 | end 25 | else if (en) begin 26 | pc_plus_4 <= IF_pc_plus_4; 27 | ins <= IF_ins; 28 | end 29 | end 30 | 31 | assign ID_pc_plus_4 = pc_plus_4; 32 | assign ID_ins = ins; 33 | endmodule -------------------------------------------------------------------------------- /Project_2/midreg/MEM_WB.v: -------------------------------------------------------------------------------- 1 | module MEM_WB(clk, MEM_MemtoReg, MEM_RegWrite, MEM_rdata, MEM_ALU_res, MEM_wreg, 2 | WB_MemtoReg, WB_RegWrite, WB_rdata , WB_ALU_res, WB_wreg); 3 | input clk; 4 | input MEM_MemtoReg; 5 | input MEM_RegWrite; 6 | input [31:0] MEM_rdata; 7 | input [31:0] MEM_ALU_res; 8 | input [4:0] MEM_wreg; 9 | 10 | output WB_MemtoReg; 11 | output WB_RegWrite; 12 | output [31:0] WB_rdata; 13 | output [31:0] WB_ALU_res; 14 | output [4:0] WB_wreg; 15 | 16 | reg MemtoReg; 17 | reg RegWrite; 18 | reg [31:0] rdata; 19 | reg [31:0] ALU_res; 20 | reg [4:0] wreg; 21 | 22 | initial begin 23 | MemtoReg = 0; 24 | RegWrite = 0; 25 | rdata = 0; 26 | ALU_res = 0; 27 | wreg = 0; 28 | end 29 | 30 | always @(posedge clk) begin 31 | MemtoReg <= MEM_MemtoReg; 32 | RegWrite <= MEM_RegWrite; 33 | rdata <= MEM_rdata; 34 | ALU_res <= MEM_ALU_res; 35 | wreg <= MEM_wreg; 36 | end 37 | 38 | assign WB_MemtoReg = MemtoReg; 39 | assign WB_RegWrite = RegWrite; 40 | assign WB_rdata = rdata; 41 | assign WB_ALU_res = ALU_res; 42 | assign WB_wreg = wreg; 43 | endmodule -------------------------------------------------------------------------------- /Project_2/mips.v: -------------------------------------------------------------------------------- 1 | module mips(clk, rst) ; 2 | input clk ; // clock 3 | input rst ; // reset 4 | 5 | wire [31:0] pc_now; 6 | wire [31:0] pc_next; 7 | wire [31:0] IF_pc_plus_4; 8 | wire [31:0] ID_pc_plus_4; 9 | wire [31:0] ID_pc_br; 10 | wire [31:0] IF_ins; 11 | wire [31:0] ID_ins; 12 | wire [4:0] EX_rs; 13 | wire [4:0] EX_rt; 14 | wire [4:0] EX_rd; 15 | wire [4:0] EX_wreg; 16 | wire [4:0] MEM_wreg; 17 | wire [4:0] WB_wreg; 18 | wire [31:0] ID_rdata1; 19 | wire [31:0] ID_rdata2; 20 | wire [31:0] EX_rtemp1; 21 | wire [31:0] EX_rdata1; 22 | wire [31:0] EX_rtemp2; 23 | wire [31:0] EX_rdata2; 24 | wire [31:0] MEM_rdata2; 25 | wire [31:0] ID_const_or_addr; 26 | wire [31:0] EX_const_or_addr; 27 | wire [31:0] ALUSrc_data1; 28 | wire [31:0] ALUSrc_data2; 29 | wire [31:0] EX_ALU_res; 30 | wire [31:0] WB_ALU_res; 31 | wire [31:0] MEM_ALU_res; 32 | wire [31:0] MEM_rdata; 33 | wire [31:0] WB_rdata; 34 | wire [31:0] wdata; 35 | wire [3:0] op; 36 | wire Jump; 37 | 38 | wire RegDst; 39 | wire RegWrite; 40 | wire ALUSrc; 41 | wire MemRead; 42 | wire MemWrite; 43 | wire MemtoReg; 44 | wire Branch; 45 | wire [1:0] ALUOp; 46 | 47 | // WB_Reg 48 | wire ID_MemtoReg; 49 | wire ID_RegWrite; 50 | wire EX_MemtoReg; 51 | wire EX_RegWrite; 52 | wire MEM_MemtoReg; 53 | wire MEM_RegWrite; 54 | wire WB_MemtoReg; 55 | wire WB_RegWrite; 56 | 57 | // M_Reg 58 | wire ID_MemRead; 59 | wire ID_MemWrite; 60 | wire EX_MemRead; 61 | wire EX_MemWrite; 62 | wire MEM_MemRead; 63 | wire MEM_MemWrite; 64 | 65 | // EX_Reg 66 | wire ID_ALUSrc; 67 | wire ID_RegDst; 68 | wire [1:0] ID_ALUOp; 69 | wire EX_ALUSrc; 70 | wire EX_RegDst; 71 | wire [1:0] EX_ALUOp; 72 | 73 | wire [1:0] ForwardA; 74 | wire [1:0] ForwardB; 75 | 76 | wire ls_Stall; 77 | wire rdata_equal; 78 | wire IF_Flush; 79 | wire Stall; 80 | 81 | 82 | wire [31:0] br_ID_rdata1; 83 | wire [31:0] br_ID_rdata2; 84 | wire [1:0] br_ForwardA; 85 | wire [1:0] br_ForwardB; 86 | wire br_Stall; 87 | 88 | // IF 89 | pc pc(.clk(clk), .rst(rst), .en(~Stall), .data(pc_next), .dout(pc_now)); 90 | assign IF_pc_plus_4 = pc_now + 4; 91 | assign IF_Flush = ~br_Stall & rdata_equal & Branch; 92 | mux3 #(32) pc_mux(.a(IF_pc_plus_4), .b(ID_pc_br), .c({ID_pc_plus_4[31:28],ID_ins[25:0],2'b00}), .s({Jump, IF_Flush}), .dout(pc_next)); 93 | im_4k im(.addr(pc_now[11:2]), .dout(IF_ins)); 94 | 95 | // IF/ID 96 | IF_ID IF_ID(.clk(clk), .en(~Stall), .rst(IF_Flush | Jump), .IF_pc_plus_4(IF_pc_plus_4), .IF_ins(IF_ins), .ID_pc_plus_4(ID_pc_plus_4), .ID_ins(ID_ins)); 97 | 98 | // ID 99 | assign ID_pc_br = ID_pc_plus_4 + {ID_const_or_addr[29:0], 2'b00}; 100 | ctrl ctrl( .op(ID_ins[31:26]), .RegDst(RegDst), .RegWrite(RegWrite), .ALUSrc(ALUSrc), 101 | .MemRead(MemRead), .MemWrite(MemWrite), .MemtoReg(MemtoReg), 102 | .Jump(Jump), .Branch(Branch), .ALUOp(ALUOp)); 103 | regheap regheap(.clk(clk), .we(WB_RegWrite), .rreg1(ID_ins[25:21]), .rreg2(ID_ins[20:16]), 104 | .wreg(WB_wreg), .wdata(wdata), .rdata1(ID_rdata1), .rdata2(ID_rdata2)); 105 | ext #(16) ext(.din(ID_ins[15:0]), .dout(ID_const_or_addr)); 106 | mux3 br_rdata1_mux(.a(ID_rdata1), .b(wdata), .c(MEM_ALU_res), .s(br_ForwardA), .dout(br_ID_rdata1)); 107 | mux3 br_rdata2_mux(.a(ID_rdata2), .b(wdata), .c(MEM_ALU_res), .s(br_ForwardB), .dout(br_ID_rdata2)); 108 | assign rdata_equal = br_ID_rdata1 == br_ID_rdata2 ? 1 : 0; 109 | 110 | 111 | // Hazard Detection Unit 112 | hdu hdu(.EX_MemRead(EX_MemRead), .EX_rt(EX_rt), .ID_rs(ID_ins[25:21]), .ID_rt(ID_ins[20:16]), .stall(ls_Stall)); 113 | br_hdu br_hdu(.Branch(Branch), .EX_RegWrite(EX_RegWrite), .EX_wreg(EX_wreg), 114 | .MEM_MemRead(MEM_MemRead), .MEM_wreg(MEM_wreg), 115 | .ID_rs(ID_ins[25:21]), .ID_rt(ID_ins[20:16]), .stall(br_Stall)); 116 | assign Stall = br_Stall | ls_Stall; 117 | 118 | mux2 #(8) stall_mux(.a({RegDst,RegWrite,ALUSrc,MemRead,MemWrite,MemtoReg,ALUOp}), .b(8'b0000_0000), .s(Stall), 119 | .dout({ID_RegDst,ID_RegWrite,ID_ALUSrc,ID_MemRead,ID_MemWrite,ID_MemtoReg,ID_ALUOp})); 120 | // ID/EX 121 | ID_EX ID_EX(.clk(clk), .ID_RegDst(ID_RegDst), .ID_RegWrite(ID_RegWrite), 122 | .ID_MemRead(ID_MemRead), .ID_MemWrite(ID_MemWrite), 123 | .ID_ALUSrc(ID_ALUSrc), .ID_MemtoReg(ID_MemtoReg), .ID_ALUOp(ID_ALUOp), 124 | .ID_rdata1(ID_rdata1), .ID_rdata2(ID_rdata2), 125 | .ID_const_or_addr(ID_const_or_addr), .ID_rs(ID_ins[25:21]), .ID_rt(ID_ins[20:16]), .ID_rd(ID_ins[15:11]), 126 | .EX_RegDst(EX_RegDst), .EX_RegWrite(EX_RegWrite), 127 | .EX_MemRead(EX_MemRead), .EX_MemWrite(EX_MemWrite), 128 | .EX_ALUSrc(EX_ALUSrc), .EX_MemtoReg(EX_MemtoReg), .EX_ALUOp(EX_ALUOp), 129 | .EX_rdata1(EX_rtemp1), .EX_rdata2(EX_rtemp2), 130 | .EX_const_or_addr(EX_const_or_addr), .EX_rs(EX_rs), .EX_rt(EX_rt), .EX_rd(EX_rd)); 131 | 132 | // EX 133 | mux3 #(32) ALUSrc1_mux(.a(EX_rtemp1), .b(wdata), .c(MEM_ALU_res), .s(ForwardA), .dout(EX_rdata1)); 134 | mux3 #(32) ALUSrc2_mux(.a(EX_rtemp2), .b(wdata), .c(MEM_ALU_res), .s(ForwardB), .dout(EX_rdata2)); 135 | ALUctrl ALUctrl(.ALUOp(EX_ALUOp), .funct(EX_const_or_addr[5:0]), .op(op)); 136 | assign ALUSrc_data1 = EX_rdata1; 137 | mux2 #(32) ALUSrc_mux(.a(EX_rdata2), .b(EX_const_or_addr), .s(EX_ALUSrc), .dout(ALUSrc_data2)); 138 | alu alu(.op(op), .a(ALUSrc_data1), .b(ALUSrc_data2), .dout(EX_ALU_res)); 139 | mux2 #(5) wreg_mux(.a(EX_rt), .b(EX_rd), .s(EX_RegDst), .dout(EX_wreg)); 140 | 141 | // Forwarding Unit 142 | fu forwardingUnit(.EX_rs(EX_rs), .EX_rt(EX_rt), .MEM_RegWrite(MEM_RegWrite), .MEM_rd(MEM_wreg), 143 | .WB_RegWrite(WB_RegWrite), .WB_rd(WB_wreg), .ForwardA(ForwardA), .ForwardB(ForwardB)); 144 | fu br_forwardingUnit(.EX_rs(ID_ins[25:21]), .EX_rt(ID_ins[20:16]), .MEM_RegWrite(MEM_RegWrite), .MEM_rd(MEM_wreg), 145 | .WB_RegWrite(WB_RegWrite), .WB_rd(WB_wreg), .ForwardA(br_ForwardA), .ForwardB(br_ForwardB)); 146 | 147 | // EX/MEM 148 | EX_MEM EX_MEM(.clk(clk), .EX_MemtoReg(EX_MemtoReg), .EX_RegWrite(EX_RegWrite), 149 | .EX_MemRead(EX_MemRead), .EX_MemWrite(EX_MemWrite), 150 | .EX_ALU_res(EX_ALU_res), .EX_rdata2(EX_rdata2), .EX_wreg(EX_wreg), 151 | .MEM_MemtoReg(MEM_MemtoReg), .MEM_RegWrite(MEM_RegWrite), 152 | .MEM_MemRead(MEM_MemRead), .MEM_MemWrite(MEM_MemWrite), 153 | .MEM_ALU_res(MEM_ALU_res), .MEM_rdata2(MEM_rdata2), .MEM_wreg(MEM_wreg)); 154 | 155 | // MEM 156 | dm_4k dm(.addr(MEM_ALU_res), .din(MEM_rdata2), .we(MEM_MemWrite), .re(MEM_MemRead), .clk(clk), .dout(MEM_rdata)); 157 | 158 | // MEM/WB 159 | MEM_WB MEM_WB(.clk(clk), .MEM_MemtoReg(MEM_MemtoReg), .MEM_RegWrite(MEM_RegWrite), 160 | .MEM_rdata(MEM_rdata), .MEM_ALU_res(MEM_ALU_res), .MEM_wreg(MEM_wreg), 161 | .WB_MemtoReg(WB_MemtoReg), .WB_RegWrite(WB_RegWrite), 162 | .WB_rdata(WB_rdata), .WB_ALU_res(WB_ALU_res), .WB_wreg(WB_wreg)); 163 | 164 | // WB 165 | mux2 #(32) RegSrc_mux(.a(WB_ALU_res), .b(WB_rdata), .s(WB_MemtoReg), .dout(wdata)); 166 | 167 | endmodule -------------------------------------------------------------------------------- /Project_2/testbench.v: -------------------------------------------------------------------------------- 1 | module testbench(); 2 | reg clk, rst; 3 | 4 | initial begin 5 | clk = 0; 6 | rst = 1; 7 | #12 rst = 0; 8 | end 9 | 10 | always #10 clk = ~clk; 11 | 12 | mips mips(clk, rst); 13 | endmodule -------------------------------------------------------------------------------- /Project_2/testcode.asm: -------------------------------------------------------------------------------- 1 | addi $8,$0,1 # set $8 = 0000_0001 2 | addi $9,$0,2 # set $9 = 0000_0010 3 | addi $13,$0,16 # set $13 = 0000_1000 4 | addi $15,$0,81 # set $15 = 0101_0001 5 | addi $16,$15,33 # set $16 = 0111_0010 6 | addi $18,$0,193 # set $18 = 1100_0001 7 | add $10,$0,$0 # set $10 = 0 8 | 9 | l1: 10 | add $8,$8,$10 # First: $8 = 1 + 0 = 1 Second: $8 = 1 + 1 = 2 11 | slt $10,$8,$9 # forwarding First: $10 = 1 < 2 ? 1 : 0 = 1 Second: $10 = 2 < 2 ? 1 : 0 = 0 12 | beq $10,$0,l2 # branch if ($10 == 0) branch : l2 13 | add $11,$8,$9 # $11 = 1 + 2 = 3 14 | sw $11, 100 15 | lw $12, 100 16 | sub $11,$12,$13 # load-use $11 = 3 - 16 = -13 = FFFF_FFF3? 17 | j l1 18 | l2: 19 | and $14,$15,$16 # $14 = 0101_0001 & 0111_0010 = 0101_0000 20 | or $17,$14,$18 # forwarding $17 = 0101_0000 | 1100_0001 = 1101_0001 21 | sw $17, 100 22 | lw $19, 100 23 | beq $17,$19,l2 # load-branch 24 | -------------------------------------------------------------------------------- /Project_2/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HaleLu/mips/309193bf0c709cfe71abf270c26272fc4b3410f2/Project_2/vsim.wlf -------------------------------------------------------------------------------- /Project_2/work/_info: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z2 4 | 13 5 | !s112 1.1 6 | !i10d 8192 7 | !i10e 25 8 | !i10f 100 9 | cModel Technology 10 | dD:/Code/Repos/mips/Project_1 11 | valu 12 | Z0 !s110 1464767476 13 | !i10b 1 14 | !s100 i2g6S2eQY958M=[_QR@`I2 15 | Ie?X[4bP`A5ITEd6?RgKkf1 16 | Z1 VDg1SIo80bB@j0V0VzS_@n1 17 | Z2 dD:/Code/Repos/mips/Project_2 18 | w1463143954 19 | 8D:/Code/Repos/mips/Project_2/datapath/alu.v 20 | FD:/Code/Repos/mips/Project_2/datapath/alu.v 21 | L0 1 22 | Z3 OP;L;10.4a;61 23 | r1 24 | !s85 0 25 | 31 26 | Z4 !s108 1464767476.000000 27 | !s107 D:/Code/Repos/mips/Project_2/datapath/alu.v| 28 | !s90 -reportprogress|300|-work|work|-stats=none|D:/Code/Repos/mips/Project_2/datapath/alu.v| 29 | !s101 -O0 30 | !i113 1 31 | Z5 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0 32 | vALUctrl 33 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| R17 341 | L0 10 342 | R3 343 | r1 344 | !s85 0 345 | 31 346 | R4 347 | R18 348 | R19 349 | !s101 -O0 350 | !i113 1 351 | R5 352 | vpc 353 | R0 354 | !i10b 1 355 | !s100 mUc6g0Nfa:;Q6d[=Mg2I02 356 | IEHDm3Nk5IA7LlQ^NidL?91 357 | R1 358 | R2 359 | w1464627336 360 | 8D:/Code/Repos/mips/Project_2/datapath/pc.v 361 | FD:/Code/Repos/mips/Project_2/datapath/pc.v 362 | L0 1 363 | R3 364 | r1 365 | !s85 0 366 | 31 367 | R4 368 | !s107 D:/Code/Repos/mips/Project_2/datapath/pc.v| 369 | !s90 -reportprogress|300|-work|work|-stats=none|D:/Code/Repos/mips/Project_2/datapath/pc.v| 370 | !s101 -O0 371 | !i113 1 372 | R5 373 | vregheap 374 | R0 375 | !i10b 1 376 | !s100 A>AV]K9bi7YB47NT8XzDn1 377 | Ic_41O3:zkWmdTa@bW9V=n2 378 | R1 379 | R2 380 | w1464767429 381 | 8D:/Code/Repos/mips/Project_2/datapath/regheap.v 382 | FD:/Code/Repos/mips/Project_2/datapath/regheap.v 383 | L0 1 384 | R3 385 | r1 386 | !s85 0 387 | 31 388 | R4 389 | !s107 D:/Code/Repos/mips/Project_2/datapath/regheap.v| 390 | !s90 -reportprogress|300|-work|work|-stats=none|D:/Code/Repos/mips/Project_2/datapath/regheap.v| 391 | !s101 -O0 392 | !i113 1 393 | R5 394 | vtestbench 395 | R6 396 | !i10b 1 397 | !s100 0XODATekgjQ4o3i3k^fWF0 398 | I8LQ2?nY?^68z@F>KY=DP[2 399 | R1 400 | R2 401 | w1463133920 402 | 8D:/Code/Repos/mips/Project_2/testbench.v 403 | FD:/Code/Repos/mips/Project_2/testbench.v 404 | L0 1 405 | R3 406 | r1 407 | !s85 0 408 | 31 409 | R7 410 | !s107 D:/Code/Repos/mips/Project_2/testbench.v| 411 | !s90 -reportprogress|300|-work|work|-stats=none|D:/Code/Repos/mips/Project_2/testbench.v| 412 | !s101 -O0 413 | !i113 1 414 | R5 415 | -------------------------------------------------------------------------------- /Project_2/work/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HaleLu/mips/309193bf0c709cfe71abf270c26272fc4b3410f2/Project_2/work/_lib.qdb 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-------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z0 4 | cModel Technology 5 | -------------------------------------------------------------------------------- /Project_3/code.txt: -------------------------------------------------------------------------------- 1 | 20080001 2 | 20090002 3 | 200d0010 4 | 200f0051 5 | 21f00021 6 | 201200c1 7 | 00005020 8 | 010a4020 9 | 0109502a 10 | 11400005 11 | 01095820 12 | ac0b0064 13 | 8c0c0064 14 | 018d5822 15 | 08000c07 16 | 01f07024 17 | 01d28825 18 | ac110064 19 | 8c130064 20 | 0293a820 21 | 1233fffa 22 | -------------------------------------------------------------------------------- /Project_3/control/ALUctrl.v: -------------------------------------------------------------------------------- 1 | module ALUctrl(ALUOp, funct, op, e); 2 | input [1:0] ALUOp; 3 | input [5:0] funct; 4 | output reg [3:0] op; 5 | output reg e; 6 | 7 | parameter ADD = 6'b100000, 8 | SUB = 6'b100010, 9 | AND = 6'b100100, 10 | OR = 6'b100101, 11 | SLT = 6'b101010; 12 | 13 | always @(*) begin 14 | case (ALUOp) 15 | 2'b00 : begin 16 | op <= 4'b0010; 17 | e <= 0; 18 | end 19 | 2'b01 : begin 20 | op <= 4'b0110; 21 | e <= 0; 22 | end 23 | 2'b10 : begin 24 | case (funct) 25 | ADD : begin 26 | op <= 4'b0010; 27 | e <= 0; 28 | end 29 | SUB : begin 30 | op <= 4'b0110; 31 | e <= 0; 32 | end 33 | AND : begin 34 | op <= 4'b0000; 35 | e <= 0; 36 | end 37 | OR : begin 38 | op <= 4'b0001; 39 | e <= 0; 40 | end 41 | SLT : begin 42 | op <= 4'b0111; 43 | e <= 0; 44 | end 45 | default : begin 46 | e <= 1; 47 | end 48 | endcase 49 | end 50 | endcase 51 | end 52 | endmodule -------------------------------------------------------------------------------- /Project_3/control/ctrl.v: -------------------------------------------------------------------------------- 1 | module ctrl(op, RegDst, RegWrite, ALUSrc, MemRead, MemWrite, MemtoReg, Jump, Branch, ALUOp, e); 2 | input [5:0] op; 3 | output reg RegDst; 4 | output reg RegWrite; 5 | output reg ALUSrc; 6 | output reg MemRead; 7 | output reg MemWrite; 8 | output reg MemtoReg; 9 | output reg Jump; 10 | output reg Branch; 11 | output reg [1:0] ALUOp; 12 | output reg e; 13 | 14 | parameter R = 6'b000000, 15 | LW = 6'b100011, 16 | SW = 6'b101011, 17 | BEQ = 6'b000100, 18 | J = 6'b000010, 19 | ADDI = 6'b001000; 20 | 21 | initial begin 22 | RegDst = 0; 23 | ALUSrc = 0; 24 | MemtoReg = 0; 25 | RegWrite = 0; 26 | MemRead = 0; 27 | MemWrite = 0; 28 | Jump = 0; 29 | Branch = 0; 30 | ALUOp = 2'b00; 31 | e = 0; 32 | end 33 | 34 | always @(*) begin 35 | case (op) 36 | R: begin 37 | RegDst = 1; 38 | ALUSrc = 0; 39 | MemtoReg = 0; 40 | RegWrite = 1; 41 | MemRead = 0; 42 | MemWrite = 0; 43 | Jump = 0; 44 | Branch = 0; 45 | ALUOp = 2'b10; 46 | e = 0; 47 | end 48 | 49 | LW: begin 50 | RegDst = 0; 51 | ALUSrc = 1; 52 | MemtoReg = 1; 53 | RegWrite = 1; 54 | MemRead = 1; 55 | MemWrite = 0; 56 | Jump = 0; 57 | Branch = 0; 58 | ALUOp = 2'b00; 59 | e = 0; 60 | end 61 | 62 | SW: begin 63 | ALUSrc = 1; 64 | RegWrite = 0; 65 | MemRead = 0; 66 | MemWrite = 1; 67 | Jump = 0; 68 | Branch = 0; 69 | ALUOp = 2'b00; 70 | e = 0; 71 | end 72 | 73 | BEQ: begin 74 | ALUSrc = 0; 75 | RegWrite = 0; 76 | MemRead = 0; 77 | MemWrite = 0; 78 | Jump = 0; 79 | Branch = 1; 80 | ALUOp = 2'b01; 81 | e = 0; 82 | end 83 | 84 | J: begin 85 | ALUSrc = 0; 86 | RegWrite = 0; 87 | MemRead = 0; 88 | MemWrite = 0; 89 | Jump = 1; 90 | Branch = 0; 91 | ALUOp = 2'b00; 92 | e = 0; 93 | end 94 | 95 | ADDI: begin 96 | RegDst = 0; 97 | ALUSrc = 1; 98 | MemtoReg = 0; 99 | RegWrite = 1; 100 | MemRead = 0; 101 | MemWrite = 0; 102 | Jump = 0; 103 | Branch = 0; 104 | ALUOp = 2'b00; 105 | e = 0; 106 | end 107 | 108 | default: begin 109 | RegDst = 0; 110 | ALUSrc = 0; 111 | MemtoReg = 0; 112 | RegWrite = 0; 113 | MemRead = 0; 114 | MemWrite = 0; 115 | Jump = 0; 116 | Branch = 0; 117 | ALUOp = 2'b00; 118 | e = 1; 119 | end 120 | endcase 121 | end 122 | 123 | endmodule -------------------------------------------------------------------------------- /Project_3/control/forwardingUnit.v: -------------------------------------------------------------------------------- 1 | module fu(EX_rs, EX_rt, MEM_RegWrite, MEM_rd, WB_RegWrite, WB_rd, ForwardA, ForwardB); 2 | input [4:0] EX_rs; 3 | input [4:0] EX_rt; 4 | input MEM_RegWrite; 5 | input [4:0] MEM_rd; 6 | input WB_RegWrite; 7 | input [4:0] WB_rd; 8 | 9 | output reg [1:0] ForwardA; 10 | output reg [1:0] ForwardB; 11 | 12 | always @(*) begin 13 | if (MEM_RegWrite && MEM_rd != 0 && MEM_rd == EX_rs) begin 14 | ForwardA <= 2'b10; 15 | end 16 | else if (WB_RegWrite && WB_rd != 0 && WB_rd == EX_rs) begin 17 | ForwardA <= 2'b01; 18 | end 19 | else begin 20 | ForwardA <= 2'b00; 21 | end 22 | 23 | if (MEM_RegWrite && MEM_rd != 0 && MEM_rd == EX_rt) begin 24 | ForwardB <= 2'b10; 25 | end 26 | else if (WB_RegWrite && WB_rd != 0 && WB_rd == EX_rt) begin 27 | ForwardB <= 2'b01; 28 | end 29 | else begin 30 | ForwardB <= 2'b00; 31 | end 32 | end 33 | 34 | endmodule -------------------------------------------------------------------------------- /Project_3/control/hazardDetectionUnit.v: -------------------------------------------------------------------------------- 1 | module hdu(EX_MemRead, EX_rt, ID_rs, ID_rt, stall); 2 | input EX_MemRead; 3 | input [4:0] EX_rt; 4 | input [4:0] ID_rs; 5 | input [4:0] ID_rt; 6 | 7 | output stall; 8 | 9 | assign stall = (EX_MemRead && ((EX_rt == ID_rs) || (EX_rt == ID_rt)))? 1 : 0; 10 | endmodule 11 | 12 | module br_hdu(Branch, EX_RegWrite, EX_wreg, MEM_MemRead, MEM_wreg, ID_rs, ID_rt, stall); 13 | input Branch; 14 | input EX_RegWrite; 15 | input MEM_MemRead; 16 | input [4:0] EX_wreg; 17 | input [4:0] MEM_wreg; 18 | input [4:0] ID_rs; 19 | input [4:0] ID_rt; 20 | 21 | output stall; 22 | 23 | assign stall = Branch && ( (EX_RegWrite && ((EX_wreg == ID_rs) || (EX_wreg == ID_rt))) || 24 | (MEM_MemRead && ((MEM_wreg == ID_rs) || (MEM_wreg == ID_rt))) ) ? 1 : 0; 25 | endmodule -------------------------------------------------------------------------------- /Project_3/datapath/alu.v: -------------------------------------------------------------------------------- 1 | module alu(op, a, b, zero, dout, e); 2 | input [3:0] op; 3 | input [31:0] a; 4 | input [31:0] b; 5 | output zero; 6 | output reg [31:0] dout; 7 | output reg [1:0] e; 8 | 9 | assign zero = dout == 0 ? 1 : 0; 10 | always @(op or a or b) begin 11 | case(op) 12 | 4'b0010 : begin 13 | dout = a + b; 14 | e = (a[31] == 0 && b[31] == 0 && dout[31] == 1) || (a[31] == 1 && b[31] == 1 && dout[31] == 0) ? 1 : 0; 15 | end 16 | 4'b0110 : begin 17 | dout = a - b; 18 | e = (a[31] == 0 && b[31] == 1 && dout[31] == 1) || (a[31] == 1 && b[31] == 0 && dout[31] == 0) ? 2 : 0; 19 | end 20 | 4'b0001 : begin 21 | dout = a | b; 22 | e = 0; 23 | end 24 | 4'b0000 : begin 25 | dout = a & b; 26 | e = 0; 27 | end 28 | 4'b0111 : begin 29 | dout = a < b ? 1 : 0; 30 | e = 0; 31 | end 32 | endcase 33 | end 34 | endmodule 35 | -------------------------------------------------------------------------------- /Project_3/datapath/dm.v: -------------------------------------------------------------------------------- 1 | module dm_4k(addr, din, we, re, clk, dout); 2 | input [11:2] addr ; // address bus 3 | input [31:0] din ; // 32-bit input data 4 | input we ; // memory write enable 5 | input re ; // memory read enable 6 | input clk ; // clock 7 | output reg [31:0] dout ; // 32-bit memory output 8 | 9 | reg [31:0] dm[1023:0] ; 10 | 11 | always @(posedge clk) begin 12 | if (we) begin 13 | dm[addr[11:2]][31:0] <= din[31:0]; 14 | end 15 | end 16 | 17 | always @(addr or re) begin 18 | if (re) begin 19 | dout[31:0] <= dm[addr[11:2]][31:0]; 20 | end 21 | end 22 | endmodule -------------------------------------------------------------------------------- /Project_3/datapath/ext.v: -------------------------------------------------------------------------------- 1 | module ext #(parameter W = 16) (din, dout); 2 | input [W-1:0] din; 3 | output [31:0] dout; 4 | 5 | assign dout = {{32-W{din[W-1]}}, din}; 6 | endmodule -------------------------------------------------------------------------------- /Project_3/datapath/im.v: -------------------------------------------------------------------------------- 1 | module im_4k( addr, dout ) ; 2 | input [11:2] addr ; // address bus 3 | output [31:0] dout ; // 32-bit memory output 4 | 5 | reg [31:0] im[1023:0] ; 6 | 7 | initial 8 | begin 9 | $readmemh("code.txt", im); 10 | end 11 | 12 | assign dout = im[addr[11:2]][31:0]; 13 | endmodule -------------------------------------------------------------------------------- /Project_3/datapath/mux.v: -------------------------------------------------------------------------------- 1 | module mux2 #(parameter W = 32) (a, b, s, dout); 2 | input [W-1:0] a; 3 | input [W-1:0] b; 4 | input s; 5 | output [W-1:0] dout; 6 | 7 | assign dout = s ? b : a; 8 | endmodule 9 | 10 | module mux3 #(parameter W = 32) (a, b, c, s, dout); 11 | input [W-1:0] a; 12 | input [W-1:0] b; 13 | input [W-1:0] c; 14 | input [1:0] s; 15 | output [W-1:0] dout; 16 | 17 | assign dout = (s==2'b00) ? a : (s==2'b01) ? b : c; 18 | endmodule -------------------------------------------------------------------------------- /Project_3/datapath/pc.v: -------------------------------------------------------------------------------- 1 | module pc (clk, rst, en, data, dout); 2 | input clk; 3 | input rst; 4 | input en; 5 | input [31:0] data; 6 | output reg [31:0] dout; 7 | 8 | always @(posedge clk) 9 | begin 10 | if(rst) 11 | dout[31:0] <= {32'h0000_3000}; 12 | else 13 | if (en) begin 14 | dout <= data; 15 | end 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /Project_3/datapath/regheap.v: -------------------------------------------------------------------------------- 1 | module regheap(clk, we, rreg1, rreg2, wreg, wdata, rdata1, rdata2); 2 | input clk; 3 | input we; 4 | input [4:0] rreg1, rreg2, wreg; 5 | input [31:0] wdata; 6 | output [31:0] rdata1, rdata2; 7 | 8 | reg [31:0] rh[31:0]; 9 | 10 | initial begin 11 | // Set all registers to 0 12 | rh[0] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 13 | rh[1] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 14 | rh[2] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 15 | rh[3] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 16 | rh[4] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 17 | rh[5] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 18 | rh[6] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 19 | rh[7] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 20 | rh[8] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 21 | rh[9] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 22 | rh[10] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 23 | rh[11] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 24 | rh[12] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 25 | rh[13] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 26 | rh[14] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 27 | rh[15] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 28 | rh[16] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 29 | rh[17] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 30 | rh[18] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 31 | rh[19] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 32 | rh[20] = 32'b0111_1111_1111_1111_1111_1111_1111_0000; 33 | rh[21] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 34 | rh[22] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 35 | rh[23] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 36 | rh[24] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 37 | rh[25] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 38 | rh[26] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 39 | rh[27] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 40 | rh[28] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 41 | rh[29] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 42 | rh[30] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 43 | rh[31] = 32'b0000_0000_0000_0000_0000_0000_0000_0000; 44 | end 45 | 46 | always @(posedge clk) begin 47 | if (we) begin 48 | rh[wreg] <= (wreg != 0)? wdata:0; 49 | end 50 | end 51 | 52 | assign rdata1 = (rreg1 != 0)? rh[rreg1]:0; 53 | assign rdata2 = (rreg2 != 0)? rh[rreg2]:0; 54 | endmodule -------------------------------------------------------------------------------- /Project_3/datapath/register.v: -------------------------------------------------------------------------------- 1 | module register(clk, wdata, rdata); 2 | input clk; 3 | input [31:0] wdata; 4 | output reg [31:0] rdata; 5 | 6 | initial begin 7 | rdata <= 0; 8 | end 9 | 10 | always @(posedge clk) begin 11 | rdata <= wdata; 12 | end 13 | endmodule -------------------------------------------------------------------------------- /Project_3/midreg/EX_MEM.v: -------------------------------------------------------------------------------- 1 | module EX_MEM(clk, rst, EX_MemtoReg , EX_RegWrite , EX_MemRead , EX_MemWrite , EX_ALU_res , EX_rdata2 , EX_wreg, 2 | MEM_MemtoReg, MEM_RegWrite, MEM_MemRead, MEM_MemWrite, MEM_ALU_res, MEM_rdata2, MEM_wreg); 3 | input clk; 4 | input rst; 5 | 6 | input EX_MemtoReg; 7 | input EX_RegWrite; 8 | input EX_MemRead; 9 | input EX_MemWrite; 10 | input [31:0] EX_ALU_res; 11 | input [31:0] EX_rdata2; 12 | input [4:0] EX_wreg; 13 | 14 | output MEM_MemtoReg; 15 | output MEM_RegWrite; 16 | output MEM_MemRead; 17 | output MEM_MemWrite; 18 | output [31:0] MEM_ALU_res; 19 | output [31:0] MEM_rdata2; 20 | output [4:0] MEM_wreg; 21 | 22 | reg MemtoReg; 23 | reg RegWrite; 24 | reg MemRead; 25 | reg MemWrite; 26 | reg [31:0] ALU_res; 27 | reg [31:0] rdata2; 28 | reg [4:0] wreg; 29 | 30 | initial begin 31 | MemtoReg = 0; 32 | RegWrite = 0; 33 | MemRead = 0; 34 | MemWrite = 0; 35 | ALU_res = 0; 36 | rdata2 = 0; 37 | wreg = 0; 38 | end 39 | 40 | always @(posedge clk) begin 41 | if (rst) begin 42 | MemtoReg = 0; 43 | RegWrite = 0; 44 | MemRead = 0; 45 | MemWrite = 0; 46 | ALU_res = 0; 47 | rdata2 = 0; 48 | wreg = 0; 49 | end 50 | else begin 51 | MemtoReg <= EX_MemtoReg; 52 | RegWrite <= EX_RegWrite; 53 | MemRead <= EX_MemRead; 54 | MemWrite <= EX_MemWrite; 55 | ALU_res <= EX_ALU_res; 56 | rdata2 <= EX_rdata2; 57 | wreg <= EX_wreg; 58 | end 59 | 60 | end 61 | 62 | assign MEM_MemtoReg = MemtoReg; 63 | assign MEM_RegWrite = RegWrite; 64 | assign MEM_MemRead = MemRead; 65 | assign MEM_MemWrite = MemWrite; 66 | assign MEM_ALU_res = ALU_res; 67 | assign MEM_rdata2 = rdata2; 68 | assign MEM_wreg = wreg; 69 | endmodule -------------------------------------------------------------------------------- /Project_3/midreg/ID_EX.v: -------------------------------------------------------------------------------- 1 | module ID_EX(clk, rst, ID_RegDst, ID_RegWrite, ID_MemRead, ID_MemWrite, ID_ALUSrc, ID_MemtoReg, ID_ALUOp, ID_pc_plus_4, ID_rdata1, ID_rdata2, ID_const_or_addr, ID_rs, ID_rt, ID_rd, 2 | EX_RegDst, EX_RegWrite, EX_MemRead, EX_MemWrite, EX_ALUSrc, EX_MemtoReg, EX_ALUOp, EX_pc_plus_4, EX_rdata1, EX_rdata2, EX_const_or_addr, EX_rs, EX_rt, EX_rd); 3 | input clk; 4 | input rst; 5 | 6 | input ID_RegDst; 7 | input ID_RegWrite; 8 | input ID_MemRead; 9 | input ID_MemWrite; 10 | input ID_ALUSrc; 11 | input ID_MemtoReg; 12 | input [1:0] ID_ALUOp; 13 | input [31:0] ID_pc_plus_4; 14 | input [31:0] ID_rdata1; 15 | input [31:0] ID_rdata2; 16 | input [31:0] ID_const_or_addr; 17 | input [4:0] ID_rs; 18 | input [4:0] ID_rt; 19 | input [4:0] ID_rd; 20 | 21 | output EX_RegDst; 22 | output EX_RegWrite; 23 | output EX_MemRead; 24 | output EX_MemWrite; 25 | output EX_ALUSrc; 26 | output EX_MemtoReg; 27 | output [1:0] EX_ALUOp; 28 | output [31:0] EX_pc_plus_4; 29 | output [31:0] EX_rdata1; 30 | output [31:0] EX_rdata2; 31 | output [31:0] EX_const_or_addr; 32 | output [4:0] EX_rs; 33 | output [4:0] EX_rt; 34 | output [4:0] EX_rd; 35 | 36 | reg RegDst; 37 | reg RegWrite; 38 | reg MemRead; 39 | reg MemWrite; 40 | reg ALUSrc; 41 | reg MemtoReg; 42 | reg [1:0] ALUOp; 43 | reg [31:0] pc_plus_4; 44 | reg [31:0] rdata1; 45 | reg [31:0] rdata2; 46 | reg [31:0] const_or_addr; 47 | reg [4:0] rs; 48 | reg [4:0] rt; 49 | reg [4:0] rd; 50 | 51 | initial begin 52 | RegDst = 0; 53 | RegWrite = 0; 54 | MemRead = 0; 55 | MemWrite = 0; 56 | ALUSrc = 0; 57 | MemtoReg = 0; 58 | ALUOp = 0; 59 | pc_plus_4 = 0; 60 | rdata1 = 0; 61 | rdata2 = 0; 62 | const_or_addr = 0; 63 | rs = 0; 64 | rt = 0; 65 | rd = 0; 66 | end 67 | 68 | always @(posedge clk) begin 69 | if (rst) begin 70 | RegDst = 0; 71 | RegWrite = 0; 72 | MemRead = 0; 73 | MemWrite = 0; 74 | ALUSrc = 0; 75 | MemtoReg = 0; 76 | ALUOp = 0; 77 | pc_plus_4 = 0; 78 | rdata1 = 0; 79 | rdata2 = 0; 80 | const_or_addr = 0; 81 | rs = 0; 82 | rt = 0; 83 | rd = 0; 84 | end 85 | else begin 86 | RegDst <= ID_RegDst; 87 | RegWrite <= ID_RegWrite; 88 | MemRead <= ID_MemRead; 89 | MemWrite <= ID_MemWrite; 90 | ALUSrc <= ID_ALUSrc; 91 | MemtoReg <= ID_MemtoReg; 92 | ALUOp <= ID_ALUOp; 93 | pc_plus_4 <= ID_pc_plus_4; 94 | rdata1 <= ID_rdata1; 95 | rdata2 <= ID_rdata2; 96 | const_or_addr <= ID_const_or_addr; 97 | rs <= ID_rs; 98 | rt <= ID_rt; 99 | rd <= ID_rd; 100 | end 101 | end 102 | 103 | assign EX_RegDst = RegDst; 104 | assign EX_RegWrite = RegWrite; 105 | assign EX_MemRead = MemRead; 106 | assign EX_MemWrite = MemWrite; 107 | assign EX_ALUSrc = ALUSrc; 108 | assign EX_MemtoReg = MemtoReg; 109 | assign EX_ALUOp = ALUOp; 110 | assign EX_pc_plus_4 = pc_plus_4; 111 | assign EX_rdata1 = rdata1; 112 | assign EX_rdata2 = rdata2; 113 | assign EX_const_or_addr = const_or_addr; 114 | assign EX_rs = rs; 115 | assign EX_rt = rt; 116 | assign EX_rd = rd; 117 | endmodule -------------------------------------------------------------------------------- /Project_3/midreg/IF_ID.v: -------------------------------------------------------------------------------- 1 | module IF_ID(clk, en, rst, IF_pc_plus_4, IF_ins, 2 | ID_pc_plus_4, ID_ins); 3 | input clk; 4 | input en; 5 | input rst; 6 | input [31:0] IF_pc_plus_4; 7 | input [31:0] IF_ins; 8 | 9 | output [31:0] ID_pc_plus_4; 10 | output [31:0] ID_ins; 11 | 12 | reg [31:0] pc_plus_4; 13 | reg [31:0] ins; 14 | 15 | initial begin 16 | pc_plus_4 = 0; 17 | ins = 32'h2000_0000; 18 | end 19 | 20 | always @(posedge clk) begin 21 | if (rst) begin 22 | pc_plus_4 = 0; 23 | ins = 32'h2000_0000; 24 | end 25 | else if (en) begin 26 | pc_plus_4 <= IF_pc_plus_4; 27 | ins <= IF_ins; 28 | end 29 | end 30 | 31 | assign ID_pc_plus_4 = pc_plus_4; 32 | assign ID_ins = ins; 33 | endmodule -------------------------------------------------------------------------------- /Project_3/midreg/MEM_WB.v: -------------------------------------------------------------------------------- 1 | module MEM_WB(clk, rst, MEM_MemtoReg, MEM_RegWrite, MEM_rdata, MEM_ALU_res, MEM_wreg, 2 | WB_MemtoReg , WB_RegWrite , WB_rdata , WB_ALU_res , WB_wreg); 3 | input clk; 4 | input rst; 5 | 6 | input MEM_MemtoReg; 7 | input MEM_RegWrite; 8 | input [31:0] MEM_rdata; 9 | input [31:0] MEM_ALU_res; 10 | input [4:0] MEM_wreg; 11 | 12 | output WB_MemtoReg; 13 | output WB_RegWrite; 14 | output [31:0] WB_rdata; 15 | output [31:0] WB_ALU_res; 16 | output [4:0] WB_wreg; 17 | 18 | reg MemtoReg; 19 | reg RegWrite; 20 | reg [31:0] rdata; 21 | reg [31:0] ALU_res; 22 | reg [4:0] wreg; 23 | 24 | initial begin 25 | MemtoReg = 0; 26 | RegWrite = 0; 27 | rdata = 0; 28 | ALU_res = 0; 29 | wreg = 0; 30 | end 31 | 32 | always @(posedge clk) begin 33 | if (rst) begin 34 | MemtoReg = 0; 35 | RegWrite = 0; 36 | rdata = 0; 37 | ALU_res = 0; 38 | wreg = 0; 39 | end 40 | else begin 41 | MemtoReg <= MEM_MemtoReg; 42 | RegWrite <= MEM_RegWrite; 43 | rdata <= MEM_rdata; 44 | ALU_res <= MEM_ALU_res; 45 | wreg <= MEM_wreg; 46 | end 47 | end 48 | 49 | assign WB_MemtoReg = MemtoReg; 50 | assign WB_RegWrite = RegWrite; 51 | assign WB_rdata = rdata; 52 | assign WB_ALU_res = ALU_res; 53 | assign WB_wreg = wreg; 54 | endmodule -------------------------------------------------------------------------------- /Project_3/mips.v: -------------------------------------------------------------------------------- 1 | module mips(clk, rst) ; 2 | input clk ; // clock 3 | input rst ; // reset 4 | 5 | wire [31:0] pc_now; 6 | wire [31:0] pc_next; 7 | wire [31:0] IF_pc_plus_4; 8 | wire [31:0] ID_pc_plus_4; 9 | wire [31:0] EX_pc_plus_4; 10 | wire [31:0] EPC; 11 | wire [31:0] ID_pc_br; 12 | wire [31:0] IF_ins; 13 | wire [31:0] ID_ins; 14 | wire [4:0] EX_rs; 15 | wire [4:0] EX_rt; 16 | wire [4:0] EX_rd; 17 | wire [4:0] EX_wreg; 18 | wire [4:0] MEM_wreg; 19 | wire [4:0] WB_wreg; 20 | wire [31:0] ID_rdata1; 21 | wire [31:0] ID_rdata2; 22 | wire [31:0] EX_rtemp1; 23 | wire [31:0] EX_rdata1; 24 | wire [31:0] EX_rtemp2; 25 | wire [31:0] EX_rdata2; 26 | wire [31:0] MEM_rdata2; 27 | wire [31:0] ID_const_or_addr; 28 | wire [31:0] EX_const_or_addr; 29 | wire [31:0] ALUSrc_data1; 30 | wire [31:0] ALUSrc_data2; 31 | wire [31:0] EX_ALU_res; 32 | wire [31:0] WB_ALU_res; 33 | wire [31:0] MEM_ALU_res; 34 | wire [31:0] MEM_rdata; 35 | wire [31:0] WB_rdata; 36 | wire [31:0] wdata; 37 | wire [3:0] op; 38 | wire Jump; 39 | 40 | wire RegDst; 41 | wire RegWrite; 42 | wire ALUSrc; 43 | wire MemRead; 44 | wire MemWrite; 45 | wire MemtoReg; 46 | wire Branch; 47 | wire [1:0] ALUOp; 48 | 49 | // WB_Reg 50 | wire ID_MemtoReg; 51 | wire ID_RegWrite; 52 | wire EX_MemtoReg; 53 | wire EX_RegWrite; 54 | wire MEM_MemtoReg; 55 | wire MEM_RegWrite; 56 | wire WB_MemtoReg; 57 | wire WB_RegWrite; 58 | 59 | // M_Reg 60 | wire ID_MemRead; 61 | wire ID_MemWrite; 62 | wire EX_MemRead; 63 | wire EX_MemWrite; 64 | wire MEM_MemRead; 65 | wire MEM_MemWrite; 66 | 67 | // EX_Reg 68 | wire ID_ALUSrc; 69 | wire ID_RegDst; 70 | wire [1:0] ID_ALUOp; 71 | wire EX_ALUSrc; 72 | wire EX_RegDst; 73 | wire [1:0] EX_ALUOp; 74 | 75 | wire [1:0] ForwardA; 76 | wire [1:0] ForwardB; 77 | 78 | wire ls_Stall; 79 | wire rdata_equal; 80 | wire IF_Flush; 81 | wire Stall; 82 | 83 | 84 | wire [31:0] br_ID_rdata1; 85 | wire [31:0] br_ID_rdata2; 86 | wire [1:0] br_ForwardA; 87 | wire [1:0] br_ForwardB; 88 | wire br_Stall; 89 | 90 | wire [2:0] Cause; 91 | wire [1:0] ALU_e; 92 | 93 | parameter Undefined_e = 3'b001, 94 | Add_e = 3'b010, 95 | Sub_e = 3'b011, 96 | pc_e = 32'h8000_0180; 97 | 98 | 99 | // IF 100 | pc pc(.clk(clk), .rst(rst), .en(~Stall), .data(Cause ? pc_e : pc_next), .dout(pc_now)); 101 | assign IF_pc_plus_4 = pc_now + 4; 102 | assign IF_Flush = ~br_Stall & rdata_equal & Branch; 103 | mux3 #(32) pc_mux(.a(IF_pc_plus_4), .b(ID_pc_br), .c({ID_pc_plus_4[31:28],ID_ins[25:0],2'b00}), .s({Jump, IF_Flush}), .dout(pc_next)); 104 | im_4k im(.addr(pc_now[11:2]), .dout(IF_ins)); 105 | 106 | // IF/ID 107 | IF_ID IF_ID(.clk(clk), .en(~Stall), .rst(rst || Cause || (IF_Flush | Jump) ? 1 : 0), .IF_pc_plus_4(IF_pc_plus_4), .IF_ins(IF_ins), .ID_pc_plus_4(ID_pc_plus_4), .ID_ins(ID_ins)); 108 | 109 | // ID 110 | assign ID_pc_br = ID_pc_plus_4 + {ID_const_or_addr[29:0], 2'b00}; 111 | ctrl ctrl( .op(ID_ins[31:26]), .RegDst(RegDst), .RegWrite(RegWrite), .ALUSrc(ALUSrc), 112 | .MemRead(MemRead), .MemWrite(MemWrite), .MemtoReg(MemtoReg), 113 | .Jump(Jump), .Branch(Branch), .ALUOp(ALUOp), .e(ctrl_e)); 114 | regheap regheap(.clk(clk), .we(WB_RegWrite), .rreg1(ID_ins[25:21]), .rreg2(ID_ins[20:16]), 115 | .wreg(WB_wreg), .wdata(wdata), .rdata1(ID_rdata1), .rdata2(ID_rdata2)); 116 | ext #(16) ext(.din(ID_ins[15:0]), .dout(ID_const_or_addr)); 117 | mux3 br_rdata1_mux(.a(ID_rdata1), .b(wdata), .c(MEM_ALU_res), .s(br_ForwardA), .dout(br_ID_rdata1)); 118 | mux3 br_rdata2_mux(.a(ID_rdata2), .b(wdata), .c(MEM_ALU_res), .s(br_ForwardB), .dout(br_ID_rdata2)); 119 | assign rdata_equal = br_ID_rdata1 == br_ID_rdata2 ? 1 : 0; 120 | 121 | 122 | // Hazard Detection Unit 123 | hdu hdu(.EX_MemRead(EX_MemRead), .EX_rt(EX_rt), .ID_rs(ID_ins[25:21]), .ID_rt(ID_ins[20:16]), .stall(ls_Stall)); 124 | br_hdu br_hdu(.Branch(Branch), .EX_RegWrite(EX_RegWrite), .EX_wreg(EX_wreg), 125 | .MEM_MemRead(MEM_MemRead), .MEM_wreg(MEM_wreg), 126 | .ID_rs(ID_ins[25:21]), .ID_rt(ID_ins[20:16]), .stall(br_Stall)); 127 | assign Stall = br_Stall | ls_Stall; 128 | 129 | mux2 #(8) stall_mux(.a({RegDst,RegWrite,ALUSrc,MemRead,MemWrite,MemtoReg,ALUOp}), .b(8'b0000_0000), .s(Stall || Cause ? 1 : 0), 130 | .dout({ID_RegDst,ID_RegWrite,ID_ALUSrc,ID_MemRead,ID_MemWrite,ID_MemtoReg,ID_ALUOp})); 131 | // ID/EX 132 | ID_EX ID_EX(.clk(clk), .rst(rst), .ID_pc_plus_4(ID_pc_plus_4), .ID_RegDst(ID_RegDst), .ID_RegWrite(ID_RegWrite), 133 | .ID_MemRead(ID_MemRead), .ID_MemWrite(ID_MemWrite), 134 | .ID_ALUSrc(ID_ALUSrc), .ID_MemtoReg(ID_MemtoReg), .ID_ALUOp(ID_ALUOp), 135 | .ID_rdata1(ID_rdata1), .ID_rdata2(ID_rdata2), 136 | .ID_const_or_addr(ID_const_or_addr), .ID_rs(ID_ins[25:21]), .ID_rt(ID_ins[20:16]), .ID_rd(ID_ins[15:11]), 137 | .EX_pc_plus_4(EX_pc_plus_4), .EX_RegDst(EX_RegDst), .EX_RegWrite(EX_RegWrite), 138 | .EX_MemRead(EX_MemRead), .EX_MemWrite(EX_MemWrite), 139 | .EX_ALUSrc(EX_ALUSrc), .EX_MemtoReg(EX_MemtoReg), .EX_ALUOp(EX_ALUOp), 140 | .EX_rdata1(EX_rtemp1), .EX_rdata2(EX_rtemp2), 141 | .EX_const_or_addr(EX_const_or_addr), .EX_rs(EX_rs), .EX_rt(EX_rt), .EX_rd(EX_rd)); 142 | register ID_EX_e(.clk(clk), .wdata(ctrl_e), .rdata(EX_ctrl_e)); 143 | 144 | // EX 145 | mux3 #(32) ALUSrc1_mux(.a(EX_rtemp1), .b(wdata), .c(MEM_ALU_res), .s(ForwardA), .dout(EX_rdata1)); 146 | mux3 #(32) ALUSrc2_mux(.a(EX_rtemp2), .b(wdata), .c(MEM_ALU_res), .s(ForwardB), .dout(EX_rdata2)); 147 | ALUctrl ALUctrl(.ALUOp(EX_ALUOp), .funct(EX_const_or_addr[5:0]), .op(op), .e(ALUctrl_e)); 148 | assign ALUSrc_data1 = EX_rdata1; 149 | mux2 #(32) ALUSrc_mux(.a(EX_rdata2), .b(EX_const_or_addr), .s(EX_ALUSrc), .dout(ALUSrc_data2)); 150 | alu alu(.op(op), .a(ALUSrc_data1), .b(ALUSrc_data2), .dout(EX_ALU_res), .e(ALU_e)); 151 | mux2 #(5) wreg_mux(.a(EX_rt), .b(EX_rd), .s(EX_RegDst), .dout(EX_wreg)); 152 | 153 | // Exception Registers 154 | assign EPC = EX_pc_plus_4 - 4; 155 | assign Cause = EX_ctrl_e || ALUctrl_e ? Undefined_e : ALU_e[0] ? Add_e : ALU_e[1] ? Sub_e : 0; 156 | 157 | 158 | // Forwarding Unit 159 | fu forwardingUnit(.EX_rs(EX_rs), .EX_rt(EX_rt), .MEM_RegWrite(MEM_RegWrite), .MEM_rd(MEM_wreg), 160 | .WB_RegWrite(WB_RegWrite), .WB_rd(WB_wreg), .ForwardA(ForwardA), .ForwardB(ForwardB)); 161 | fu br_forwardingUnit(.EX_rs(ID_ins[25:21]), .EX_rt(ID_ins[20:16]), .MEM_RegWrite(MEM_RegWrite), .MEM_rd(MEM_wreg), 162 | .WB_RegWrite(WB_RegWrite), .WB_rd(WB_wreg), .ForwardA(br_ForwardA), .ForwardB(br_ForwardB)); 163 | 164 | mux2 #(4) EX_flush_mux(.a({EX_MemtoReg,EX_RegWrite,EX_MemRead,EX_MemWrite}), .b(4'b0000), .s(Cause ? 1 : 0), 165 | .dout({EX_MemtoReg_m,EX_RegWrite_m,EX_MemRead_m,EX_MemWrite_m})); 166 | 167 | // EX/MEM 168 | EX_MEM EX_MEM(.clk(clk), .rst(rst), .EX_MemtoReg(EX_MemtoReg_m), .EX_RegWrite(EX_RegWrite_m), 169 | .EX_MemRead(EX_MemRead_m), .EX_MemWrite(EX_MemWrite_m), 170 | .EX_ALU_res(EX_ALU_res), .EX_rdata2(EX_rdata2), .EX_wreg(EX_wreg), 171 | .MEM_MemtoReg(MEM_MemtoReg), .MEM_RegWrite(MEM_RegWrite), 172 | .MEM_MemRead(MEM_MemRead), .MEM_MemWrite(MEM_MemWrite), 173 | .MEM_ALU_res(MEM_ALU_res), .MEM_rdata2(MEM_rdata2), .MEM_wreg(MEM_wreg)); 174 | 175 | // MEM 176 | dm_4k dm(.addr(MEM_ALU_res), .din(MEM_rdata2), .we(MEM_MemWrite), .re(MEM_MemRead), .clk(clk), .dout(MEM_rdata)); 177 | 178 | // MEM/WB 179 | MEM_WB MEM_WB(.clk(clk), .rst(rst), .MEM_MemtoReg(MEM_MemtoReg), .MEM_RegWrite(MEM_RegWrite), 180 | .MEM_rdata(MEM_rdata), .MEM_ALU_res(MEM_ALU_res), .MEM_wreg(MEM_wreg), 181 | .WB_MemtoReg(WB_MemtoReg), .WB_RegWrite(WB_RegWrite), 182 | .WB_rdata(WB_rdata), .WB_ALU_res(WB_ALU_res), .WB_wreg(WB_wreg)); 183 | 184 | // WB 185 | mux2 #(32) RegSrc_mux(.a(WB_ALU_res), .b(WB_rdata), .s(WB_MemtoReg), .dout(wdata)); 186 | 187 | endmodule -------------------------------------------------------------------------------- /Project_3/testbench.v: -------------------------------------------------------------------------------- 1 | module testbench(); 2 | reg clk, rst; 3 | 4 | initial begin 5 | clk = 0; 6 | rst = 1; 7 | #12 rst = 0; 8 | end 9 | 10 | always #10 clk = ~clk; 11 | 12 | mips mips(clk, rst); 13 | endmodule -------------------------------------------------------------------------------- /Project_3/testcode.asm: -------------------------------------------------------------------------------- 1 | addi $8,$0,1 # set $8 = 0000_0001 2 | addi $9,$0,2 # set $9 = 0000_0010 3 | addi $13,$0,16 # set $13 = 0000_1000 4 | addi $15,$0,81 # set $15 = 0101_0001 5 | addi $16,$15,33 # set $16 = 0111_0010 6 | addi $18,$0,193 # set $18 = 1100_0001 7 | add $10,$0,$0 # set $10 = 0 8 | 9 | l1: 10 | add $8,$8,$10 # First: $8 = 1 + 0 = 1 Second: $8 = 1 + 1 = 2 11 | slt $10,$8,$9 # forwarding First: $10 = 1 < 2 ? 1 : 0 = 1 Second: $10 = 2 < 2 ? 1 : 0 = 0 12 | beq $10,$0,l2 # branch if ($10 == 0) branch : l2 13 | add $11,$8,$9 # $11 = 1 + 2 = 3 14 | sw $11, 100 15 | lw $12, 100 16 | sub $11,$12,$13 # load-use $11 = 3 - 16 = -13 = FFFF_FFF3? 17 | j l1 18 | l2: 19 | and $14,$15,$16 # $14 = 0101_0001 & 0111_0010 = 0101_0000 20 | or $17,$14,$18 # forwarding $17 = 0101_0000 | 1100_0001 = 1101_0001 21 | sw $17, 100 22 | lw $19, 100 23 | add $21,$20,$19 24 | beq $17,$19,l2 # load-branch 25 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # mips 2 | Mips 处理器仿真设计 3 | 4 | ## 开发语言、工具和环境 5 | 采用 Verilog 语言开发 6 | Window 10 环境下 7 | 使用了 Sublime Text + ModelSim 的方式进行开发（ModelSim 自带的编辑器真的难用一个tab竟然是8个空格啊啊啊啊啊） 8 | 9 | ## 开发进度 10 | Project 1 已完成支持9条指令的单周期。 11 | Project 2 目前已完成支持9条指令的流水，暂不支持转发、阻塞和异常。 12 | 13 | ## Project_1 14 | 单周期的 MIPS 处理器 15 | 只支持 add、sub、and、or、lw、sw、slt、beq、j 这9条指令 16 | 17 | 具体分为两大部分和处理器部分 18 | ### datapath（数据通路） 19 | 定义了各种元部件 20 | #### alu.v 21 | 模块名：alu 22 | 说明：算逻部件 23 | 输入接口：op（4位，运算符编码）, a, b（32位，运算数） 24 | 输出接口：zero（结果是否为0）, dout（32位，运算结果） 25 | op的说明： 26 | 　　0010： dout = a + b 27 | 　　0110： dout = a - b 28 | 　　0001： dout = a | b 29 | 　　0000： dout = a & b 30 | 　　0111： dout = a < b ? 1 : 0 31 | 32 | #### dm.v 33 | 模块名：dm_4k 34 | 说明：数据寄存器，大小为4k（时钟上升沿触发） 35 | 输入接口：addr（10位，数据地址）, din（32位，写数据时的数据端）, we（写数据使能端）, re（读数据使能端）, clk（时钟端） 36 | 输出接口：dout（32位，读数据时的数据输出端） 37 | 38 | #### ext.v 39 | 模块名：ext 40 | 说明：符号扩展部件（W 表示输入数据宽度） 41 | 输入接口：din（W 位） 42 | 输出接口：dout（32位） 43 | 44 | #### im.v 45 | 模块名：im_4k 46 | 说明：指令存储器，大小为4k 47 | 输入接口：addr（10位，运算符编码） 48 | 输出接口：dout（32位，对应指令） 49 | 50 | #### mux.v 51 | 模块名：mux2 52 | 说明：二路选择器（W 表示输入数据宽度） 53 | 输入接口：a, b（W 位，表示0和1对应的数据源）, s（选择信号） 54 | 输出接口：dout（W 位，选择结果） 55 | 56 | #### pc.v 57 | 模块名：pc 58 | 说明：程序计数器（时钟上升沿触发） 59 | 输入接口：clk（时钟端）, rst（重置信号）, data（32位，下一指令地址） 60 | 输出接口：dout（32位，当前指令地址） 61 | 62 | #### regheap.v 63 | 模块名：regheap 64 | 说明：寄存器堆（时钟上升沿触发） 65 | 输入接口：clk（时钟端）, we（写寄存器使能端）, rreg1（5位，读寄存器1地址）, rreg2（5位，读寄存器2地址）, wreg（5位，写寄存器的地址）, wdata（写入寄存器的数据） 66 | 输出接口：rdata1（32位，读寄存器1的数据）, rdata2（32位，读寄存器2的数据） 67 | 另：有部分为方便测试而添加的初始化寄存器的值的代码。 68 | 69 | ### control（控制信号） 70 | 71 | 解析指令，生成对应的控制信号 72 | 73 | #### ALUctrl.v 74 | 模块名：ALUctrl 75 | 说明：算逻部件控制器 76 | 输入接口：ALUOp（2位）, funct（6位，指令的5-0位） 77 | 输出接口：op（4位，对应的 alu 运算符编码） 78 | 79 | #### ctrl.v 80 | 模块名：ctrl 81 | 说明：算逻部件控制器 82 | 输入接口：op（6位，指令的31-26位） 83 | 输出接口：RegDst, RegWrite, ALUSrc, MemRead, MemWrite, MemtoReg, Jump, Branch, ALUOp（各种控制信号，其中 ALUOp 为2位） 84 | 85 | 控制信号名|无效时的含义|有效时的含义 86 | :--|:--:|--: 87 | RegDst|写寄存器的目标寄存器号来自 rt 字段（位 20 : 16 ）|写寄存器的目标寄存器号来自 rd 字段（位 15 : 11 ） 88 | RegWrite|无|寄存器堆写使能有效 89 | ALUSrc|第二个 ALU 操作数来自寄存器堆的第二个输出（读数据2）|第二个 ALU 操作数为指令低16位的符号扩展 90 | MemRead|无|数据存储器读使能有效 91 | MemWrite|无|数据存储器写使能有效 92 | MemroReg|写入存储器的数据来自 ALU|写入寄存器的数据来自数据存储器 93 | Jump|无|PC 跳转至指定地址 94 | Branch|无|PC 在分支条件成立时跳转 95 | 96 | ### mips.v（处理器部分） 97 | 模块名：mips 98 | 说明：单周期处理器（时钟上升沿触发） 99 | 输入接口：clk（时钟端）, rst（重置信号） 100 | 101 | ### testbench.v（测试代码） 102 | 模块名：testbench 103 | 说明：生成时钟信号测试部件可行性 104 | 105 | ## Project_2 106 | 流水级 MIPS 处理器 107 | 暂时支持 add、sub、and、or、lw、sw、slt、beq、j、addi 这10条指令 108 | 支持转发、阻塞，暂不支持异常 109 | 110 | 和 Project_1 相比，差别在于添加了中间寄存器和转发、阻塞机制 111 | 112 | ### midreg（中间寄存器） 113 | 114 | #### IF_ID.v 115 | 模块名：IF_ID 116 | 说明：IF/ID（时钟上升沿触发） 117 | 输入接口：clk（时钟端）, en（修改使能端）, rst（重置信号）, IF_pc_plus_4（32位，pc + 4）, IF_ins（32位，IF取出的指令） 118 | 输出接口：ID_pc_plus_4（32位）, ID_ins（32位） 119 | 120 | #### ID_EX.v 121 | 模块名：ID_EX 122 | 说明：ID/EX（时钟上升沿触发） 123 | 输入接口：clk（时钟端）, 124 | 　　　　　ID_RegDst, ID_RegWrite, ID_MemRead, ID_MemWrite, ID_ALUSrc, ID_MemtoReg, ID_ALUOp（除 ID_ALUOp 为2位外其余均为1位，表示对应的控制信号）, 125 | 　　　　　ID_rdata1（32位，rs 寄存器的数据）, ID_rdata2（32位，rt 寄存器的数据）, ID_const_or_addr（32位，I 指令中的地址/立即数）, 126 | 　　　　　ID_rs（5位， 表示 rs 寄存器）, ID_rt（5位， 表示 rt 寄存器）, ID_rd（5位， 表示 rd 寄存器） 127 | 输出接口：EX_RegDst, EX_RegWrite, EX_MemRead, EX_MemWrite, EX_ALUSrc, EX_MemtoReg, EX_ALUOp, 128 | 　　　　　EX_rdata1, EX_rdata2, EX_const_or_addr, 129 | 　　　　　EX_rs, EX_rt, EX_rd（分别表示对应的数据位） 130 | 131 | #### EX_MEM.v 132 | 模块名：EX_MEM 133 | 说明：EX/MEM（时钟上升沿触发） 134 | 输入接口：clk（时钟端）, 135 | 　　　　　EX_MemtoReg , EX_RegWrite , EX_MemRead , EX_MemWrite（表示对应的控制信号）, 136 | 　　　　　EX_ALU_res（32位，ALU 运算结果）, EX_rdata2（32位，rt 寄存器的数据）, EX_wreg（5位，写入的寄存器地址） 137 | 输出接口：MEM_MemtoReg, MEM_RegWrite, MEM_MemRead, MEM_MemWrite, 138 | 　　　　　MEM_ALU_res, MEM_rdata2, MEM_wreg（分别表示对应的数据位） 139 | 140 | #### MEM_WB.v 141 | 模块名：MEM_WB 142 | 说明：MEM/WB（时钟上升沿触发） 143 | 输入接口：clk（时钟端）, 144 | 　　　　　MEM_MemtoReg, MEM_RegWrite（表示对应的控制信号）, 145 | 　　　　　MEM_rdata（32位，从 dm 中读取的数据）, MEM_ALU_res（ALU 运算结果）, MEM_wreg（5位，写入的寄存器地址） 146 | 输出接口：WB_MemtoReg, WB_RegWrite, 147 | 　　　　　WB_rdata, WB_ALU_res, WB_wreg（分别表示对应的数据位） 148 | 149 | ### *control 150 | #### *ctrl.v 151 | \*模块名：ctrl 152 | \*说明：新增对 addi 指令的支持 153 | 154 | #### forwardingUnit.v 155 | 模块名：fu 156 | 说明：转发单元 157 | 输入接口：EX_rs, EX_rt, MEM_RegWrite, MEM_rd, WB_RegWrite, WB_rd 158 | 输出接口：ForwardA, ForwardB 159 | 160 | 多选器控制|源|解释 161 | :--|:--:|--: 162 | ForwardA = 00|ID/EX|第一个 ALU 操作数来自寄存器堆 163 | ForwardA = 10|EX/MEM|第一个 ALU 操作数由上一个 ALU 运算结果转发获得 164 | ForwardA = 01|MEM/WB|第一个 ALU 操作数从数据存储器或者前面的 ALU 结果中转发获得 165 | ForwardB = 00|ID/EX|第二个 ALU 操作数来自寄存器堆 166 | ForwardB = 10|EX/MEM|第二个 ALU 操作数由上一个 ALU 运算结果转发获得 167 | ForwardB = 01|MEM/WB|第二个 ALU 操作数从数据存储器或者前面的 ALU 结果中转发获得 168 | 169 | #### hazardDetectionUnit.v 170 | 模块名：hdu 171 | 说明：load-use 数据冒险检测单元 172 | 输入接口：EX_MemRead, EX_rt, ID_rs, ID_rt 173 | 输出接口：stall（阻塞信号） 174 | 175 | 模块名：br_hdu 176 | 说明：分支冒险检测单元 177 | 输入接口：Branch, EX_RegWrite, EX_wreg, MEM_MemRead, MEM_wreg, ID_rs, ID_rt 178 | 输出接口：stall（阻塞信号） 179 | 180 | ### *datapath 181 | #### *mux.v 182 | 模块名：mux3 183 | 说明：三路选择器（W 表示输入数据宽度） 184 | 输入接口：a, b, c（W 位，表示0和1对应的数据源）, s（2位，选择信号） 185 | 输出接口：dout（W 位，选择结果） 186 | 187 | #### *pc.v 188 | \*模块名：pc 189 | \*说明：新增写入使能端 190 | \*新增输入接口：en（写入使能端） 191 | 192 | #### *regheap 193 | \*模块名：regheap 194 | \*说明：移除初始数据，全部初始化为0 195 | 196 | *注：星号表示有新增或修改* --------------------------------------------------------------------------------