├── .gitignore ├── IP ├── BISS_C │ ├── CRC6.v │ ├── axi_lite.v │ ├── biss_c.v │ ├── biss_c_top.v │ ├── clk_div.v │ ├── component.xml │ ├── drivers_demo │ │ ├── Xilinx.spec │ │ ├── axi_lite_rw.c │ │ ├── axi_lite_rw.h │ │ ├── biss-c.c │ │ ├── biss-c.h │ │ ├── hello-biss.c │ │ ├── lscript.ld │ │ ├── platform.c │ │ ├── platform.h │ │ └── platform_config.h │ ├── line_delay_cal.v │ ├── signal_delay.v │ ├── tb_CRC_Unit.sv │ ├── tb_biss_c.sv │ └── xgui │ │ ├── BISS_C_v1_0.tcl │ │ └── biss_c_top_v1_0.tcl ├── IPRepo │ ├── IPlib │ │ └── ClkDivider_1.0 │ │ │ ├── component.xml │ │ │ ├── doc │ │ │ ├── ClkDivider.assets │ │ │ │ ├── image-20200106164500017.png │ │ │ │ └── image-20200106165228944.png │ │ │ ├── ClkDivider.md │ │ │ └── ClkDivider.pdf │ │ │ ├── gui │ │ │ ├── ClkDivider_v1_0.gtcl │ │ │ └── clk_div_top_v1_0.gtcl │ │ │ ├── sim │ │ │ └── clk_div_tb.sv │ │ │ ├── src │ │ │ ├── ClkDivider.v │ │ │ ├── clk_div.v │ │ │ └── trigger_sync.sv │ │ │ └── xgui │ │ │ └── ClkDivider_v1_0.tcl │ └── Interface │ │ ├── group_port.xml │ │ ├── group_port_rtl.xml │ │ └── readme.txt ├── axi_dma_s2mm_filter │ ├── ReadMe.assets │ │ └── image-20231103093201470.png │ ├── ReadMe.md │ ├── component.xml │ ├── s2mm_filter.v │ ├── tb_s2mm_filter.sv │ └── xgui │ │ └── s2mm_filter_v1_0.tcl └── interface │ ├── biss_c.xml │ └── biss_c_rtl.xml ├── README.assets └── image-20231027163109709.png ├── README.md ├── constraints └── io.xdc ├── doc ├── BISS-C IP User Manual.docx ├── BISS-C IP User Manual.pdf ├── BISS_EB-SCH.pdf ├── BiSS_C_protocol.pdf ├── L-9709-9005-03-F_Data_sheet_BiSS_(unidirectional)_RESOLUTE_en(1).pdf ├── SSI&BISS绝对值编码器用户手册 V2.0.pdf └── ZYNQ 7020&7010 Core.pdf └── scripts ├── bd_biss.tcl ├── build.bat ├── build_project.tcl └── prj_biss.tcl /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/.gitignore -------------------------------------------------------------------------------- /IP/BISS_C/CRC6.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/CRC6.v -------------------------------------------------------------------------------- /IP/BISS_C/axi_lite.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/axi_lite.v -------------------------------------------------------------------------------- /IP/BISS_C/biss_c.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/biss_c.v -------------------------------------------------------------------------------- /IP/BISS_C/biss_c_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/biss_c_top.v -------------------------------------------------------------------------------- /IP/BISS_C/clk_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/clk_div.v -------------------------------------------------------------------------------- /IP/BISS_C/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/component.xml -------------------------------------------------------------------------------- /IP/BISS_C/drivers_demo/Xilinx.spec: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/drivers_demo/Xilinx.spec -------------------------------------------------------------------------------- /IP/BISS_C/drivers_demo/axi_lite_rw.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/drivers_demo/axi_lite_rw.c -------------------------------------------------------------------------------- /IP/BISS_C/drivers_demo/axi_lite_rw.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/drivers_demo/axi_lite_rw.h -------------------------------------------------------------------------------- /IP/BISS_C/drivers_demo/biss-c.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/drivers_demo/biss-c.c -------------------------------------------------------------------------------- /IP/BISS_C/drivers_demo/biss-c.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/drivers_demo/biss-c.h -------------------------------------------------------------------------------- /IP/BISS_C/drivers_demo/hello-biss.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/drivers_demo/hello-biss.c -------------------------------------------------------------------------------- /IP/BISS_C/drivers_demo/lscript.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/drivers_demo/lscript.ld -------------------------------------------------------------------------------- /IP/BISS_C/drivers_demo/platform.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/drivers_demo/platform.c -------------------------------------------------------------------------------- /IP/BISS_C/drivers_demo/platform.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/drivers_demo/platform.h -------------------------------------------------------------------------------- /IP/BISS_C/drivers_demo/platform_config.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/drivers_demo/platform_config.h -------------------------------------------------------------------------------- /IP/BISS_C/line_delay_cal.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/line_delay_cal.v -------------------------------------------------------------------------------- /IP/BISS_C/signal_delay.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/signal_delay.v -------------------------------------------------------------------------------- /IP/BISS_C/tb_CRC_Unit.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/tb_CRC_Unit.sv -------------------------------------------------------------------------------- /IP/BISS_C/tb_biss_c.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/tb_biss_c.sv -------------------------------------------------------------------------------- /IP/BISS_C/xgui/BISS_C_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/xgui/BISS_C_v1_0.tcl -------------------------------------------------------------------------------- /IP/BISS_C/xgui/biss_c_top_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/BISS_C/xgui/biss_c_top_v1_0.tcl -------------------------------------------------------------------------------- /IP/IPRepo/IPlib/ClkDivider_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/IPlib/ClkDivider_1.0/component.xml -------------------------------------------------------------------------------- /IP/IPRepo/IPlib/ClkDivider_1.0/doc/ClkDivider.assets/image-20200106164500017.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/IPlib/ClkDivider_1.0/doc/ClkDivider.assets/image-20200106164500017.png -------------------------------------------------------------------------------- /IP/IPRepo/IPlib/ClkDivider_1.0/doc/ClkDivider.assets/image-20200106165228944.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/IPlib/ClkDivider_1.0/doc/ClkDivider.assets/image-20200106165228944.png -------------------------------------------------------------------------------- /IP/IPRepo/IPlib/ClkDivider_1.0/doc/ClkDivider.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/IPlib/ClkDivider_1.0/doc/ClkDivider.md -------------------------------------------------------------------------------- /IP/IPRepo/IPlib/ClkDivider_1.0/doc/ClkDivider.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/IPlib/ClkDivider_1.0/doc/ClkDivider.pdf -------------------------------------------------------------------------------- /IP/IPRepo/IPlib/ClkDivider_1.0/gui/ClkDivider_v1_0.gtcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/IPlib/ClkDivider_1.0/gui/ClkDivider_v1_0.gtcl -------------------------------------------------------------------------------- /IP/IPRepo/IPlib/ClkDivider_1.0/gui/clk_div_top_v1_0.gtcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/IPlib/ClkDivider_1.0/gui/clk_div_top_v1_0.gtcl -------------------------------------------------------------------------------- /IP/IPRepo/IPlib/ClkDivider_1.0/sim/clk_div_tb.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/IPlib/ClkDivider_1.0/sim/clk_div_tb.sv -------------------------------------------------------------------------------- /IP/IPRepo/IPlib/ClkDivider_1.0/src/ClkDivider.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/IPlib/ClkDivider_1.0/src/ClkDivider.v -------------------------------------------------------------------------------- /IP/IPRepo/IPlib/ClkDivider_1.0/src/clk_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/IPlib/ClkDivider_1.0/src/clk_div.v -------------------------------------------------------------------------------- /IP/IPRepo/IPlib/ClkDivider_1.0/src/trigger_sync.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/IPlib/ClkDivider_1.0/src/trigger_sync.sv -------------------------------------------------------------------------------- /IP/IPRepo/IPlib/ClkDivider_1.0/xgui/ClkDivider_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/IPlib/ClkDivider_1.0/xgui/ClkDivider_v1_0.tcl -------------------------------------------------------------------------------- /IP/IPRepo/Interface/group_port.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/Interface/group_port.xml -------------------------------------------------------------------------------- /IP/IPRepo/Interface/group_port_rtl.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/Interface/group_port_rtl.xml -------------------------------------------------------------------------------- /IP/IPRepo/Interface/readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/IPRepo/Interface/readme.txt -------------------------------------------------------------------------------- /IP/axi_dma_s2mm_filter/ReadMe.assets/image-20231103093201470.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/axi_dma_s2mm_filter/ReadMe.assets/image-20231103093201470.png -------------------------------------------------------------------------------- /IP/axi_dma_s2mm_filter/ReadMe.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/axi_dma_s2mm_filter/ReadMe.md -------------------------------------------------------------------------------- /IP/axi_dma_s2mm_filter/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/axi_dma_s2mm_filter/component.xml -------------------------------------------------------------------------------- /IP/axi_dma_s2mm_filter/s2mm_filter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/axi_dma_s2mm_filter/s2mm_filter.v -------------------------------------------------------------------------------- /IP/axi_dma_s2mm_filter/tb_s2mm_filter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/axi_dma_s2mm_filter/tb_s2mm_filter.sv -------------------------------------------------------------------------------- /IP/axi_dma_s2mm_filter/xgui/s2mm_filter_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/axi_dma_s2mm_filter/xgui/s2mm_filter_v1_0.tcl -------------------------------------------------------------------------------- /IP/interface/biss_c.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/interface/biss_c.xml -------------------------------------------------------------------------------- /IP/interface/biss_c_rtl.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/IP/interface/biss_c_rtl.xml -------------------------------------------------------------------------------- /README.assets/image-20231027163109709.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/README.assets/image-20231027163109709.png -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/README.md -------------------------------------------------------------------------------- /constraints/io.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/constraints/io.xdc -------------------------------------------------------------------------------- /doc/BISS-C IP User Manual.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/doc/BISS-C IP User Manual.docx -------------------------------------------------------------------------------- /doc/BISS-C IP User Manual.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/doc/BISS-C IP User Manual.pdf -------------------------------------------------------------------------------- /doc/BISS_EB-SCH.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/doc/BISS_EB-SCH.pdf -------------------------------------------------------------------------------- /doc/BiSS_C_protocol.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/doc/BiSS_C_protocol.pdf -------------------------------------------------------------------------------- /doc/L-9709-9005-03-F_Data_sheet_BiSS_(unidirectional)_RESOLUTE_en(1).pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/doc/L-9709-9005-03-F_Data_sheet_BiSS_(unidirectional)_RESOLUTE_en(1).pdf -------------------------------------------------------------------------------- /doc/SSI&BISS绝对值编码器用户手册 V2.0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/doc/SSI&BISS绝对值编码器用户手册 V2.0.pdf -------------------------------------------------------------------------------- /doc/ZYNQ 7020&7010 Core.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/doc/ZYNQ 7020&7010 Core.pdf -------------------------------------------------------------------------------- /scripts/bd_biss.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/scripts/bd_biss.tcl -------------------------------------------------------------------------------- /scripts/build.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/scripts/build.bat -------------------------------------------------------------------------------- /scripts/build_project.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/scripts/build_project.tcl -------------------------------------------------------------------------------- /scripts/prj_biss.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hello-FPGA/BISS-C/HEAD/scripts/prj_biss.tcl --------------------------------------------------------------------------------