├── .dockerignore ├── Dockerfile ├── LICENSE.txt ├── README.md ├── driver ├── cifx0daemon.c ├── includes │ ├── TLR_Types.h │ ├── cifXEndianess.h │ ├── cifXErrors.h │ ├── cifXUser.h │ ├── cifxlinux.h │ ├── netx_tap.h │ ├── rcX_Public.h │ └── rcX_User.h └── netx-docker-pi-drv-2.0.1-r0.deb ├── firmware └── netx-docker-pi-pns-eth-3.12.0.8.deb ├── hooks ├── build ├── post_push └── pre_build └── init.d └── entrypoint.sh /.dockerignore: -------------------------------------------------------------------------------- 1 | Dockerfile 2 | LICENSE.txt 3 | README.md 4 | -------------------------------------------------------------------------------- /Dockerfile: -------------------------------------------------------------------------------- 1 | #use armv7hf compatible base image 2 | FROM balenalib/armv7hf-debian:buster-20191223 3 | 4 | #dynamic build arguments coming from the /hook/build file 5 | ARG BUILD_DATE 6 | ARG VCS_REF 7 | 8 | #metadata labels 9 | LABEL org.label-schema.build-date=$BUILD_DATE \ 10 | org.label-schema.vcs-url="https://github.com/HilscherAutomation/netPI-codesys-basis" \ 11 | org.label-schema.vcs-ref=$VCS_REF 12 | 13 | #version 14 | ENV HILSCHERNETPI_CODESYS_BASIS_VERSION 1.3.5 15 | 16 | #execute all commands as root 17 | USER root 18 | 19 | #labeling 20 | LABEL maintainer="netpi@hilscher.com" \ 21 | version=$HILSCHERNETPI_CODESYS_BASIS_VERSION \ 22 | description="CODESYS Control" 23 | 24 | #environment variables 25 | ENV USER=pi 26 | ENV PASSWD=raspberry 27 | 28 | COPY "./driver/*" "./driver/includes/" "./firmware/*" /tmp/ 29 | 30 | #install ssh, create user "pi" and make him sudo 31 | RUN apt-get update \ 32 | && apt-get install -y openssh-server net-tools psmisc build-essential ifupdown isc-dhcp-client \ 33 | && mkdir /var/run/sshd \ 34 | && useradd --create-home --shell /bin/bash pi \ 35 | && echo $USER:$PASSWD | chpasswd \ 36 | && adduser $USER sudo \ 37 | && echo $USER " ALL=(ALL) NOPASSWD: ALL" > /etc/sudoers.d/010_pi-nopasswd \ 38 | # create some necessary files for CODESYS 39 | && touch /usr/bin/modprobe \ 40 | && chmod +x /usr/bin/modprobe \ 41 | && mkdir /etc/modprobe.d \ 42 | && touch /etc/modprobe.d/blacklist.conf \ 43 | && touch /etc/modules \ 44 | #install netX driver and netX ethernet supporting firmware 45 | && dpkg -i /tmp/netx-docker-pi-drv-2.0.1-r0.deb \ 46 | && dpkg -i /tmp/netx-docker-pi-pns-eth-3.12.0.8.deb \ 47 | #compile netX network daemon that creates the cifx0 ethernet interface 48 | && echo "Irq=/sys/class/gpio/gpio24/value" >> /opt/cifx/plugins/netx-spm/config0 \ 49 | && cp /tmp/*.h /usr/include/cifx \ 50 | && cp /tmp/cifx0daemon.c /opt/cifx/cifx0daemon.c \ 51 | && gcc /opt/cifx/cifx0daemon.c -o /opt/cifx/cifx0daemon -I/usr/include/cifx -Iincludes/ -lcifx -pthread \ 52 | #clean up 53 | && rm -rf /tmp/* \ 54 | && apt-get remove build-essential \ 55 | && apt-get -yqq autoremove \ 56 | && apt-get -y clean \ 57 | && rm -rf /var/lib/apt/lists/* 58 | 59 | #do ports 60 | EXPOSE 22 1217 61 | 62 | #do entrypoint 63 | COPY "./init.d/*" /etc/init.d/ 64 | ENTRYPOINT ["/etc/init.d/entrypoint.sh"] 65 | 66 | #set STOPSGINAL 67 | STOPSIGNAL SIGTERM 68 | 69 | -------------------------------------------------------------------------------- /LICENSE.txt: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2017 - Hilscher Gesellschaft fuer Systemautomation mbH 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | 23 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## CODESYS Control 2 | 3 | Made for Raspberry Pi 3B architecture based devices and compatibles 4 | 5 | ### Docker repository 6 | 7 | https://hub.docker.com/r/hilschernetpi/netpi-codesys-basis/ 8 | 9 | ### Container features 10 | 11 | The image provided hereunder deploys a container with a basic setup of Linux tools, utilities and default user `pi` as needed for a flawless installation of the CODESYS Control for Raspberry Pi (SL and MC SL) packages with the Windows® based [CODESYS Development System V3](https://store.codesys.com/codesys.html)(free). 12 | 13 | Base of this image builds [debian](https://www.balena.io/docs/reference/base-images/base-images/) with enabled [SSH](https://en.wikipedia.org/wiki/Secure_Shell) and created default user 'pi'(sudo). This setup is equivalent to a stripped down Raspbian OS with least capabilities. 14 | 15 | Once the container is deployed it needs an upgrade with the following packages you can download from the CODESYS store 16 | 17 | * [CODESYS Control for Raspberry Pi SL](https://store.codesys.com/codesys-control-for-raspberry-pi-sl.html) or [CODESYS Control for Raspberry Pi MC SL](https://store.codesys.com/codesys-control-for-raspberry-pi-mc-sl.html) 18 | * [CODESYS Edge Gateway](https://store.codesys.com/codesys-edge-gateway.html) (needed at later versions of CODESYS runtime) 19 | 20 | ### Container hosts 21 | 22 | The container has been successfully tested on the following Docker hosts 23 | 24 | * netPI, model RTE 3, product name NIOT-E-NPI3-51-EN-RE 25 | * netPI, model CORE 3, product name NIOT-E-NPI3-EN 26 | * netIOT Connect, product name NIOT-E-TPI51-EN-RE 27 | * netFIELD Connect, product name NIOT-E-TPI51-EN-RE/NFLD 28 | * Raspberry Pi, model 3B 29 | 30 | netPI devices specifically feature a restricted Docker protecting the Docker host system software's integrity by maximum. The restrictions are 31 | 32 | * privileged mode is not automatically adding all host devices `/dev/` to a container 33 | * volume bind mounts to rootfs is not supported 34 | * the devices `/dev`,`/dev/mem`,`/dev/sd*`,`/dev/dm*`,`/dev/mapper`,`/dev/mmcblk*` cannot be added to a container 35 | 36 | ### Container licensing 37 | 38 | If not licensed the "CODESYS Control for Raspberry Pi" SoftPLC runtime operates 1 hour and then stops. A [Licensing](https://www.codesys.com/the-system/licensing.html) is needed to make it run an unlimited time. 39 | 40 | A license purchase follows an email with a ticket number (e.g A78HY-TBVMD-8SVC7-P8BHX-4LED6) granting you the license. The `Tools->License Manager` in the CODESYS Development System (internet needed) transforms the ticket number in a deployed license. The ticket number can be used only one time and gets invalid during the licensing procedure. 41 | 42 | It is possible to deploy a license to either a CODESYS Runtime Key (USB dongle) or to a software container. 43 | 44 | **IMPORTANT NOTE**: A software container needs special care cause the license is stored in container. If this container is lost or destroyed by any reason or is deleted your license copy is **gone forever!!!**. This is why a license backup is obligatory in this case. 45 | 46 | To backup the license file "3SLicenseInfo.tar" follow this [FAQ information](https://forum.codesys.com/viewtopic.php?f=22&t=5641&start=15#p10689). 47 | To restore the license file "3SLicenseInfo.tar" follow this [FAQ information](https://forum.codesys.com/viewtopic.php?f=22&t=5641&p=10690#p10690). 48 | 49 | ### Container setup 50 | 51 | #### Environment variable (optional) 52 | 53 | The container binds the SSH server port to `22` by default. 54 | 55 | For an alternative port use the variable **SSHPORT** with the desired port number as value. 56 | 57 | #### Host network 58 | 59 | The container needs to run in `host` network mode. 60 | 61 | Using this mode makes port mapping unnecessary since all the used container ports (like 22) are exposed to the host automatically. 62 | 63 | #### Privileged mode 64 | 65 | The privileged mode option needs to be activated to lift the standard Docker enforced container limitations. With this setting the container and the applications inside are the getting (almost) all capabilities as if running on the Host directly 66 | 67 | #### Host devices 68 | 69 | The CODESYS runtime perfoms a license check across the Docker host VideoCore GPU when started. To grant access to the GPU chip the `/dev/vcio` Docker host device is mandatory to add to the container. 70 | 71 | In case an external USB CODESYS Runtime Key Dongle is used for licensing the Docker host device `/dev/hidraw0` needs to be added to the container. The device `/dev/hidraw0` is only available on the Docker host if such a USB dongle physically has been connected to one of the USB sockets. 72 | 73 | ##### Additional Ethernet ports on netPI RTE 3 or netFIELD/netIOT connect (optional) 74 | 75 | The container configures the double RJ45 socket driven by netX controller to operate as standard LAN interface (single MAC address, switched always) with a device name `cifx0` if the following devices found added to the container 76 | 77 | * Docker host device `/dev/spidev0.0` granting access to the network controller netX driving the RTE ports 78 | * Docker host device `/dev/net/tun` granting access to network interface registering logic 79 | 80 | Cause the container runs in `host` network mode the interface is instantiated on the Docker host as a standard LAN interface. This is why the `cifx0` IP settings have to be configured in the Docker host's web UI network setup dialog (as "eth0" interface) and not in the container. Any change on the IP settings needs a container restart to accept the new IP parameters. 81 | 82 | The netX controller was designed to support all kind of Industrial Networks as device in the first place. Its performance is high when exchanging IO data with a network master across IO buffers. It was not designed to support high performance message oriented exchange of data as used in Ethernet communications. This is why the provided `cifx0` interface is a low to mid-range performer but is still a good compromise if another Ethernet interface is needed. 83 | 84 | Measurements have shown that around 700 to 800KByte/s throughput can be reached across `cifx0` only whereas with netPI's primary Ethernet port `eth0` 10MByte/s can be reached. The reasons are: 85 | 86 | * 25MHz SPI clock frequency between netX and Raspberry Pi CPU only 87 | * User space driver instead of a kernel driver 88 | * 8 messages deep message receive queue only for incoming Ethernet frames 89 | * SPI handshake protocol with additional overhead between netX and Raspberry Pi during message based communications 90 | 91 | The `cifx0` LAN interface will drop Ethernet frames in case its message queue is being overun at high LAN network traffic. The TCP/IP network protocol embeds a recovery procedure for packet loss due to retransmissions. This is why you usually do not recognize a problem when this happens. Single frame communications using non TCP/IP based traffic like the ping command may recognize lost frames. 92 | 93 | The `cifx0` LAN interface DOES NOT support Ethernet package reception of type multicast. 94 | 95 | ### Container deployment 96 | 97 | Pulling the image may take 10 minutes. 98 | 99 | #### netPI example 100 | 101 | STEP 1. Open netPI's web UI in your browser (https). 102 | 103 | STEP 2. Click the Docker tile to open the [Portainer.io](http://portainer.io/) Docker management user interface. 104 | 105 | STEP 3. Enter the following parameters under *Containers > + Add Container* 106 | 107 | Parameter | Value | Remark 108 | :---------|:------ |:------ 109 | *Image* | **hilschernetpi/netpi-codesys-basis** | a :tag may be added as well 110 | *Network > Network* | **host** | 111 | *Restart policy* | **always** | 112 | *Adv.con.set. > Env > +add env.var.* | *name* **SSHPORT** -> *value* **any number value** | optional for different SSH port 113 | *Adv.con.set. > Devices > +add device* | *Host path* **/dev/vcio** -> *Container path* **/dev/vcio** | 114 | *Adv.con.set. > Devices > +add device* | *Host path* **/dev/hidraw0** -> *Container path* **/dev/hidraw0** | for CODESYS Runtime Key Dongle 115 | *Adv.con.set. > Devices > +add device* | *Host path* **/dev/spidev0.0** -> *Container path* **/dev/spidev0.0** | for `cifx0` LAN 116 | *Adv.con.set. > Devices > +add device* | *Host path* **/dev/net/tun** -> *Container path* **/dev/net/tun** | for `cifx0` LAN 117 | *Adv.con.set. > Privileged mode* | **On** | 118 | 119 | STEP 4. Press the button *Actions > Start/Deploy container* 120 | 121 | #### Docker command line example 122 | 123 | `docker run -d --privileged --network=host --restart=always -e SSHPORT=22 --device=/dev/vcio0:/dev/vcio --device=/dev/hidraw0:/dev/hidraw0 --device=/dev/spidev0.0:/dev/spidev0.0 --device=/dev/net/tun:/dev/net-tun -p 22:22/tcp hilschernetpi/netpi-codesys-basis` 124 | 125 | #### Docker compose example 126 | 127 | A `docker-compose.yml` file could look like this 128 | 129 | version: "2" 130 | 131 | services: 132 | nodered: 133 | image: hilschernetpi/netpi-codesys-basis 134 | restart: always 135 | privileged: true 136 | network_mode: host 137 | ports: 138 | - 22:22 139 | devices: 140 | - "/dev/vcio:/dev/vcio" 141 | - "/dev/hidraw0:/dev/hidraw0" 142 | - "/dev/spidev0.0:/dev/spidev0.0" 143 | - "/dev/net/tun:/dev/net/tun" 144 | environment: 145 | - SSHPORT=22 146 | 147 | ### Container access 148 | 149 | The container starts the SSH server automatically when deployed. 150 | 151 | For an SSH terminal session as used by the CODESYS development system to communicate with a target hardware use the Docker host IP address with the port number `22` or the configured **SSHPORT**. 152 | 153 | A fresh container can immediately be upgraded with your downloaded packages from the CODESYS store. Here is how to proceed 154 | 155 | STEP 1: Upgrade your Windows CODESYS development system first with support for Raspberry Pi/Linux compatible platforms using the function `Tools->Package Manager->Install`. Choose your packages "CODESYS Control for Raspberry Pi 3.5.xx.xx.package" and "CODESYS Edge Gateway for Linux 3.5.x.x.package" and click `Install`. 156 | 157 | STEP 2: Restart the development system to activate the installed packages extending the top menu bar `Tools` by two new functions. 158 | 159 | STEP 3: Use the new function `Tools->Update Raspberry Pi` to deploy your "CODESYS Control for Raspberry Pi" package to the container. Enter the user `pi` and the password `raspberry` as `Login credentials`. Enter your Docker host IP address in `Select target->IP address` with the :port as extension , choose the version under `Package` you want to install and press `Install`. The installation may take up to 1 minute. Choose `Standard` or `Multicore` runtime mode during installation. 160 | 161 | STEP 4: Use the new function `Tools->Update Edge Gateway` to deploy your "CODESYS Edge Gateway for Linux" package to the container. Enter the user `pi` and the password `raspberry` as `Login credentials`. Enter your Dcoker host IP address in `Select target->IP address` with the :port as extension, choose the version `V3.5.x.x.(armhf)` under `Package` you want to install and press `Install`. The installation may take up to 1 minute. The container is now well prepared and ready to receive a project. 162 | 163 | STEP 5: Create a CODESYS new project. Choose `Standard Project` and as `Device` "CODESYS Control for Raspberry Pi xx" and then `ok`. After project creation double click the topmost `Device(CODESYS Control for Raspberry Pi)` in the project tree. 164 | 165 | STEP 6: Setup a communication from the CODESYS development system to the container Edge Gateway. Use the function `Gateway->Add New Gateway` in the dialog `Device`. As gateway `IP-address` use the Docker host IP address at port 1217 and click `ok`. Use the option `Device->Scan Network...` option and click the found device found. e.g. NTB827EBEA02D0 [0000.0539] and `ok`. 166 | 167 | ### Container test 168 | 169 | The container has been successfully tested against the [CODESYS Development System V3](https://store.codesys.com/codesys.html) in the version V3.5.15.40(64Bit) and the [CODESYS Control for Raspberry Pi SL](https://store.codesys.com/codesys-control-for-raspberry-pi-sl.html) and [CODESYS Control for Raspberry Pi MC SL](https://store.codesys.com/codesys-control-for-raspberry-pi-mc-sl.html) both in the version V3.5.16.0 170 | 171 | ### License 172 | 173 | Copyright (c) Hilscher Gesellschaft fuer Systemautomation mbH. All rights reserved. 174 | Licensed under the LISENSE.txt file information stored in the project's source code repository. 175 | 176 | As with all Docker images, these likely also contain other software which may be under other licenses (such as Bash, etc from the base distribution, along with any direct or indirect dependencies of the primary software being contained). 177 | As for any pre-built image usage, it is the image user's responsibility to ensure that any use of this image complies with any relevant licenses for all software contained within. 178 | 179 | [![N|Solid](http://www.hilscher.com/fileadmin/templates/doctima_2013/resources/Images/logo_hilscher.png)](http://www.hilscher.com) Hilscher Gesellschaft fuer Systemautomation mbH www.hilscher.com 180 | -------------------------------------------------------------------------------- /driver/cifx0daemon.c: -------------------------------------------------------------------------------- 1 | /* 2 | # 3 | # MIT License 4 | # 5 | # Copyright (c) 2017 Hilscher Systemautomation 6 | # 7 | # Permission is hereby granted, free of charge, to any person obtaining a copy 8 | # of this software and associated documentation files (the "Software"), to deal 9 | # in the Software without restriction, including without limitation the rights 10 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 | # copies of the Software, and to permit persons to whom the Software is 12 | # furnished to do so, subject to the following conditions: 13 | # 14 | # The above copyright notice and this permission notice shall be included in all 15 | # copies or substantial portions of the Software. 16 | # 17 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 | # SOFTWARE. 24 | # 25 | */ 26 | 27 | /*************************************************************************************************/ 28 | /* cifx0daemon creates a network interface named 'cifx0' from netPI's netx controller. */ 29 | /* */ 30 | /* Phyiscally this interface sends/receives data through the switched two-ported netx RJ45 ports */ 31 | /* */ 32 | /* Treat the interface in the same manner as interface such as 'eth0', 'wan0' etc. */ 33 | /*************************************************************************************************/ 34 | 35 | 36 | #include "cifxlinux.h" 37 | #include "cifXEndianess.h" 38 | #include "rcX_Public.h" 39 | 40 | #include 41 | #include 42 | #include 43 | 44 | #include 45 | #include 46 | #include 47 | #include 48 | 49 | #include 50 | #include 51 | 52 | #define CIFX_DEV "cifX0" 53 | #define NL_MAX_PAYLOAD 8192 54 | #define MAX_WAIT_FOR_CIFX0_IN_SEC 30 55 | 56 | CIFXHANDLE hDriver = NULL; 57 | CIFXHANDLE hSysdevice = NULL; 58 | SYSTEM_CHANNEL_SYSTEM_INFO_BLOCK tSystemInfoBlock; 59 | 60 | 61 | /*****************************************************************************/ 62 | /*! Main entry function 63 | * \return 0 */ 64 | /*****************************************************************************/ 65 | int main(int argc, char* argv[]) 66 | { 67 | int err; 68 | 69 | // fork the process 70 | pid_t pid = fork(); 71 | 72 | if( pid == 0 ) { // child process 73 | 74 | // starting the netx "cifx0" network interface 75 | 76 | // sempahore needed to sync signal events of child process 77 | static sem_t sem; 78 | 79 | // handler called on exceptional signals 80 | void semhandler(int sig) { 81 | // unlock semaphore 82 | sem_post(&sem); 83 | } 84 | 85 | struct CIFX_LINUX_INIT init = 86 | { 87 | .init_options = CIFX_DRIVER_INIT_AUTOSCAN, 88 | .iCardNumber = 0, 89 | .fEnableCardLocking = 0, 90 | .base_dir = NULL, 91 | .poll_interval = 0, 92 | .poll_StackSize = 0, 93 | .trace_level = 255, 94 | .user_card_cnt = 0, 95 | .user_cards = NULL, 96 | }; 97 | 98 | // initialize semaphore and lock it by default 99 | sem_init(&sem,0,0); 100 | 101 | // define signals that could kill the process 102 | signal(SIGKILL, semhandler); 103 | signal(SIGTERM, semhandler); 104 | signal(SIGINT, semhandler); 105 | signal(SIGQUIT, semhandler); 106 | 107 | int32_t lRet = cifXDriverInit(&init); 108 | 109 | if(CIFX_NO_ERROR == lRet) { 110 | 111 | // driver sucessfully initialized 112 | 113 | lRet = xDriverOpen(&hDriver); 114 | 115 | if(CIFX_NO_ERROR == lRet) { 116 | 117 | // driver successfully opened, SPI bus and netX found 118 | 119 | lRet = xSysdeviceOpen(hDriver, CIFX_DEV ,&hSysdevice); 120 | 121 | // System channel successfully opened 122 | 123 | if(CIFX_NO_ERROR == lRet) { 124 | 125 | // query system information block 126 | 127 | if( CIFX_NO_ERROR == (lRet = xSysdeviceInfo(hSysdevice, CIFX_INFO_CMD_SYSTEM_INFO_BLOCK, sizeof(SYSTEM_CHANNEL_SYSTEM_INFO_BLOCK), &tSystemInfoBlock ))) { 128 | 129 | if( (long unsigned int)tSystemInfoBlock.ulDeviceNumber / 100 == 76601) { 130 | 131 | // netPI device detected, suspend until signal 132 | 133 | sem_wait(&sem); 134 | 135 | } 136 | 137 | } 138 | 139 | // close the system channel 140 | 141 | xSysdeviceClose(hSysdevice); 142 | 143 | } 144 | 145 | // close the driver 146 | 147 | xDriverClose(hDriver); 148 | 149 | } 150 | 151 | } 152 | 153 | cifXDriverDeinit(); 154 | 155 | sem_destroy(&sem); 156 | 157 | exit(0); 158 | 159 | } else { // parent process 160 | 161 | // listing to kernel events via netlink socket to wait for "cifx0" network interface been created 162 | 163 | int nl_socket; 164 | struct sockaddr_nl src_addr; 165 | char msg[NL_MAX_PAYLOAD]; 166 | int32_t lRet; 167 | char eventstr[] = "add@/devices/virtual/net/cifx0"; 168 | int timeout = 0; 169 | 170 | // handler called on alarm 171 | void alrmhandler(int sig) { 172 | timeout = 1; 173 | } 174 | 175 | memset(&src_addr, 0, sizeof(src_addr)); 176 | src_addr.nl_family = AF_NETLINK; 177 | src_addr.nl_pid = getpid(); 178 | src_addr.nl_groups = -1; 179 | 180 | nl_socket = socket(AF_NETLINK, (SOCK_DGRAM | SOCK_CLOEXEC), NETLINK_KOBJECT_UEVENT); 181 | if (nl_socket < 0) { 182 | printf("Failed to create socket for DeviceFinder"); 183 | exit(1); 184 | } 185 | 186 | lRet = bind(nl_socket, (struct sockaddr*) &src_addr, sizeof(src_addr)); 187 | if (lRet) { 188 | printf("Failed to bind netlink socket.."); 189 | close(nl_socket); 190 | return 1; 191 | } 192 | 193 | printf("Waiting for added 'cifx0' network interface ... \n"); 194 | 195 | // define alarm signal and handler 196 | signal(SIGALRM, alrmhandler); 197 | 198 | // wait for max tim to "cifx0" becoming ready 199 | alarm(MAX_WAIT_FOR_CIFX0_IN_SEC); 200 | 201 | while (1) { 202 | 203 | if( timeout ) { 204 | 205 | // alarm timeout received 206 | 207 | printf("'cifx0' network interface not ready in time\n"); 208 | 209 | // kill child process also 210 | kill( pid, SIGTERM); 211 | 212 | break; 213 | } 214 | 215 | int r = recv(nl_socket, msg, sizeof(msg), MSG_DONTWAIT); 216 | 217 | if (r == -1) // nothing 218 | continue; 219 | 220 | if (r < 0) { // error 221 | continue; 222 | } 223 | 224 | if( memcmp((const void*)&msg,(const void*)&eventstr,sizeof(eventstr)) == 0) { 225 | 226 | // event matches, interface is ready 227 | 228 | printf("'cifx0' network interface is now ready\n"); 229 | 230 | break; 231 | } 232 | 233 | } 234 | 235 | exit(0); 236 | 237 | } 238 | } 239 | 240 | -------------------------------------------------------------------------------- /driver/includes/TLR_Types.h: -------------------------------------------------------------------------------- 1 | /************************************************************************************** 2 | 3 | Copyright (c) Hilscher Gesellschaft fuer Systemautomation mbH. All Rights Reserved. 4 | 5 | *************************************************************************************** 6 | 7 | $Id: TLR_Types.h 6827 2015-03-31 15:23:50Z Robert $: 8 | 9 | Description: 10 | TLR type definitions 11 | 12 | Changes: 13 | Date Description 14 | ----------------------------------------------------------------------------------- 15 | 2015-03-31 Added guard for _MSC_VER to allow compilation using -wundef 16 | 2015-01-15 Undo packing of TLR_PACKET_HEADER_T/TLR_UUID_T to avoid alignment issues 17 | 2014-07-07 Added support for IAR C/C++ Compiler (ARM Cores only) 18 | 2014-04-28 Added support for armcc compiler, 19 | packed TLR_PACKET_HEADER_T and TLR_UUID_T to handle 20 | strict packing rules of armcc compiler 21 | 2010-06-14 Added __PACKED_PRE / POST macros (as old header 22 | files might illegally contain them. Theses files 23 | should be changed to use __TLR_PACKED_PRE / POST) 24 | 2010-04-27 Re-added all TLR_TASK_UID_xx from TLR_Common.h 25 | Re-added TLR_TASK_UID_T from TLR_Common.h 26 | 2010-04-14 Added Logical Queue defines TLR_PACKET_DEST_xx 27 | 2010-04-07 Added TLR_TBF_BUFFERPOOL_T, TLR_TBF_CALLBACK 28 | 2010-03-23 File created. 29 | 30 | **************************************************************************************/ 31 | 32 | 33 | #ifndef __TLR_TYPES_H 34 | #define __TLR_TYPES_H 35 | 36 | #ifdef __cplusplus 37 | extern "C" { 38 | #endif /* __cplusplus */ 39 | 40 | 41 | 42 | /*****************************************************************************/ 43 | /* Include Files Required */ 44 | /*****************************************************************************/ 45 | 46 | #if defined( __RX_INCLUDES_H ) 47 | #error Problem with include order. Please include TLR_Includes.h before rX_Includes.h. 48 | #endif 49 | 50 | #if defined (__TLR_USE_CUSTOM_TYPES__) 51 | #include "TLR_CustomTypes.h" 52 | #else 53 | #include /* ISO/IEC 9899:1999 fixed width data types */ 54 | #endif 55 | 56 | 57 | 58 | /*****************************************************************************/ 59 | /* Symbol Definitions */ 60 | /*****************************************************************************/ 61 | 62 | 63 | /************************ General Symbol Definitions *************************/ 64 | 65 | /* boolean evaluation */ 66 | #define TLR_FALSE (0) 67 | #define TLR_TRUE (1) 68 | 69 | /* pointer types */ 70 | #ifndef FAR 71 | #define FAR 72 | #endif /* FAR */ 73 | 74 | /* storage classes */ 75 | #ifndef CONST 76 | #define CONST const 77 | #endif /* CONST */ 78 | 79 | #ifndef EXTERN 80 | #define EXTERN extern 81 | #endif /* EXTERN */ 82 | 83 | #ifndef STATIC 84 | #define STATIC static 85 | #endif /* STATIC */ 86 | 87 | 88 | /******************* Compiler Specific Symbol Definitions ********************/ 89 | 90 | /* MSVC defines a version rather than a key symbol. Prepare standard key symbol handling. */ 91 | #if defined(_MSC_VER) 92 | #if _MSC_VER >= 1000 93 | #define __MSVC__ 94 | #endif /* _MSC_VER >= 1000 */ 95 | #endif /* _MSC_VER */ 96 | 97 | 98 | /* check for known compilers using the key symbols of which one should be defined */ 99 | #if !defined (__GNUC__) && !defined (__MSVC__) && !defined (__ADS__) && !defined (__REALVIEW__) && !defined (__CC_ARM) && !defined (__ICCARM__) && !defined(__TLR_USE_CUSTOM_COMPILER__) 100 | #error Unknown compiler type. (Check definitions in TLR_Types.h.) 101 | #endif /* __MSVC__, __GNUC__, __ADS__, __REALVIEW__ */ 102 | 103 | 104 | /* specific definitions for GNU C compiler */ 105 | #if defined (__GNUC__) 106 | /* tight packing of structure members */ 107 | #define __TLR_PACKED_PRE 108 | #define __TLR_PACKED_POST __attribute__ ((packed)) 109 | /* redefinition for inline */ 110 | #ifndef INLINE 111 | #define INLINE static inline 112 | #endif /* INLINE */ 113 | #endif /* __GNUC__ */ 114 | 115 | 116 | /* specific definitions for Microsoft C compiler */ 117 | #if defined (__MSVC__) 118 | /* tight packing of structure members */ 119 | #define __TLR_PACKED_PRE 120 | #define __TLR_PACKED_POST 121 | #define PRAGMA_PACK_ENABLE 122 | #define PRAGMA_PACK_1(label) pack(push, label, 1) 123 | #define PRAGMA_UNPACK_1(label) pack(pop, label) 124 | /* redefinition for inline */ 125 | #ifndef INLINE 126 | #define INLINE static 127 | #endif /* INLINE */ 128 | /* strict data type checking */ 129 | #ifndef STRICT 130 | #define STRICT 131 | #endif 132 | #endif /* _MSC_VER >= 1000 */ 133 | 134 | 135 | /* specific definitions for REALVIEW ARM and IAR compiler (ARM cores only) */ 136 | #if defined (__ADS__) || defined (__REALVIEW__) || defined (__CC_ARM) || defined (__ICCARM__) 137 | /* tight packing of structure members */ 138 | #define __TLR_PACKED_PRE __packed 139 | #define __TLR_PACKED_POST 140 | /* redefinition for inline */ 141 | #ifndef INLINE 142 | #define INLINE static 143 | #endif /* INLINE */ 144 | #endif /* __ADS__, __REALVIEW__ */ 145 | 146 | #if defined(__TLR_USE_CUSTOM_COMPILER__) 147 | #include 148 | #endif /* __TLR_USE_CUSTOM_COMPILER__ */ 149 | 150 | #ifndef __RCX__ 151 | #ifndef __PACKED_PRE 152 | #define __PACKED_PRE __TLR_PACKED_PRE 153 | #endif 154 | 155 | #ifndef __PACKED_POST 156 | #define __PACKED_POST __TLR_PACKED_POST 157 | #endif 158 | #endif 159 | 160 | /************************ General Packet Definitions *************************/ 161 | 162 | /* total packet size definition */ 163 | #define TLR_MAX_PACKET_SIZE (1596) 164 | 165 | 166 | /* Logical Queue defines */ 167 | #define TLR_PACKET_DEST_MID_SYS (0) 168 | #define TLR_PACKET_DEST_CHANNEL_0 (1) 169 | #define TLR_PACKET_DEST_CHANNEL_1 (2) 170 | #define TLR_PACKET_DEST_CHANNEL_2 (3) 171 | #define TLR_PACKET_DEST_CHANNEL_3 (4) 172 | 173 | #define TLR_PACKET_DEST_DEFAULT_CHANNEL (32) 174 | 175 | 176 | /*** Definitions for the Packet Extension Field ***/ 177 | 178 | /* mask for sequence number and sequence control portions */ 179 | #define TLR_PACKET_SEQ_NR_MASK (0x0000003F) /* used for filtering the sequence number */ 180 | #define TLR_PACKET_SEQ_MASK (0x000000C0) /* used for filtering the sequence control code */ 181 | 182 | /* sequence control codes */ 183 | #define TLR_PACKET_SEQ_NONE (0x00000000) /* packet is not part of a packet sequence */ 184 | #define TLR_PACKET_SEQ_LAST (0x00000040) /* last packet of a packet sequence */ 185 | #define TLR_PACKET_SEQ_FIRST (0x00000080) /* first packet of a packet sequence */ 186 | #define TLR_PACKET_SEQ_MIDDLE (0x000000C0) /* packet in the middle of a packet sequence */ 187 | 188 | /* packet handling flags */ 189 | #define TLR_PACKET_NOT_DELETE (0x00000100) /* packet must not be returned to a packet pool */ 190 | #define TLR_PACKET_RETRY (0x00000200) /* packet will be resent based on a predefined retry mechanism */ 191 | 192 | /* router flags */ 193 | #define TLR_PACKET_NO_CNF_THRU_ROUTER (0x00000400) /* router must not send response/confirmation packet back */ 194 | 195 | 196 | /*********************** Task Types for TLR_TASK_UID_T ***********************/ 197 | 198 | /* task type not set */ 199 | #define TLR_TASK_UID_TASK_TYPE_INVALID (0x0000) 200 | /* user application task */ 201 | #define TLR_TASK_UID_TASK_TYPE_USER (0x0001) 202 | /* task belonging to a communication protocol stack */ 203 | #define TLR_TASK_UID_TASK_TYPE_PROTOCOL_STACK (0x0002) 204 | /* task belonging to the rcX operating system */ 205 | #define TLR_TASK_UID_TASK_TYPE_RCX (0x0003) 206 | /* task belonging to the Windows CE operating system */ 207 | #define TLR_TASK_UID_TASK_TYPE_WINCE (0x0004) 208 | /* XPEC channel that has not yet been allocated by a protocol stack */ 209 | #define TLR_TASK_UID_TASK_TYPE_XPEC (0x0005) 210 | 211 | 212 | /********************* Protocol Types for TLR_TASK_UID_T *********************/ 213 | 214 | /* protocol type IDs for TLR_TASK_UID_TASK_TYPE_PROTOCOL_STACK */ 215 | #define TLR_TASK_UID_STACK_PROFINET_SLAVE (0x00000001) 216 | #define TLR_TASK_UID_STACK_PROFINET_MASTER (0x00000002) 217 | #define TLR_TASK_UID_STACK_PROFIBUS_SLAVE (0x00000003) 218 | #define TLR_TASK_UID_STACK_PROFIBUS_MASTER (0x00000004) 219 | #define TLR_TASK_UID_STACK_POWERLINK_SLAVE (0x00000005) 220 | #define TLR_TASK_UID_STACK_ETHERNETIP_MASTER (0x00000006) 221 | #define TLR_TASK_UID_STACK_ETHERNETIP_SLAVE (0x00000007) 222 | #define TLR_TASK_UID_STACK_ETHERCAT_SLAVE (0x00000008) 223 | #define TLR_TASK_UID_STACK_TCPIP (0x00000009) 224 | #define TLR_TASK_UID_STACK_ASI_MASTER (0x0000000A) 225 | #define TLR_TASK_UID_STACK_PROFIBUS (0x0000000B) 226 | #define TLR_TASK_UID_STACK_SERCOSIII_SLAVE (0x0000000C) 227 | #define TLR_TASK_UID_STACK_ETHERCAT_MASTER (0x0000000D) 228 | 229 | /* protocol type IDs for TLR_TASK_UID_TASK_TYPE_RCX */ 230 | #define TLR_TASK_UID_RCX_MID_SYS (0x00000001) 231 | #define TLR_TASK_UID_RCX_MID_DBG (0x00000002) 232 | 233 | 234 | 235 | /*****************************************************************************/ 236 | /* Class, Type, and Structure Definitions */ 237 | /*****************************************************************************/ 238 | 239 | #if !defined (__TLR_USE_CUSTOM_TYPES__) 240 | /* signed integers with defined length */ 241 | typedef int8_t TLR_INT8; 242 | typedef int16_t TLR_INT16; 243 | typedef int32_t TLR_INT32; 244 | typedef int64_t TLR_INT64; 245 | /* unsigned integers with defined length */ 246 | typedef uint8_t TLR_UINT8; 247 | typedef uint16_t TLR_UINT16; 248 | typedef uint32_t TLR_UINT32; 249 | typedef uint64_t TLR_UINT64; 250 | /* 8-bit ANSI characters */ 251 | typedef char TLR_CHAR; 252 | typedef char TLR_STR; 253 | /* data types with machine word length (avoid use in structures) */ 254 | typedef int TLR_INT; 255 | typedef unsigned int TLR_UINT; 256 | typedef unsigned int TLR_BOOLEAN; 257 | #endif 258 | 259 | /* simply nothing */ 260 | typedef void TLR_VOID; 261 | 262 | /* boolean values with defined length */ 263 | typedef TLR_UINT8 TLR_BOOLEAN8; 264 | typedef TLR_UINT32 TLR_BOOLEAN32; 265 | 266 | /* context specific data types */ 267 | typedef TLR_UINT32 TLR_RESULT; 268 | typedef TLR_UINT32 TLR_STATUS; 269 | typedef void* TLR_HANDLE; 270 | 271 | 272 | /******************** Other Basic Structure Definitions **********************/ 273 | 274 | /* UUID */ 275 | typedef struct 276 | { 277 | TLR_UINT32 ulData1; 278 | TLR_UINT16 usData2; 279 | TLR_UINT16 usData3; 280 | TLR_UINT8 abData4[8]; 281 | } TLR_UUID_T; 282 | 283 | 284 | /* task UUID with special meaning of the elements */ 285 | typedef __TLR_PACKED_PRE struct 286 | { 287 | TLR_UINT32 ulProtocolType; /* see TLR_TASK_UID_STACK_xxx */ 288 | TLR_UINT16 usMajorVersion; /* major number of the task (or stack) version */ 289 | TLR_UINT16 usTaskType; /* see TLR_TASK_UID_TASK_TYPE_xxx */ 290 | TLR_UINT32 ulLayerLevel; /* layer number (per the OSI model) */ 291 | TLR_UINT32 ulLayerSubTask; /* subtask number, e.g. in case of multiple channels */ 292 | } __TLR_PACKED_POST TLR_TASK_UID_T; 293 | 294 | 295 | /* destination queue link (used for routing support) */ 296 | typedef struct 297 | { 298 | TLR_HANDLE hQue; /* handle of the queue to send the packets to */ 299 | TLR_UINT32 ulDest; /* ulDest value for the packets to send */ 300 | TLR_UINT32 ulDestId; /* ulDestId value for the packets to send */ 301 | TLR_UINT32 ulMTU; /* maximum transfer unit to be sent unfragmented */ 302 | } TLR_QUE_LINK_T; 303 | 304 | 305 | /* source queue link (used for routing support) */ 306 | typedef struct 307 | { 308 | TLR_UINT32 ulSrc; /* ulSrc value for the packets to send back */ 309 | TLR_UINT32 ulSrcId; /* ulSrcId value for the packets to send back */ 310 | } TLR_QUE_LINK_SOURCE_T; 311 | 312 | 313 | /* packed access */ 314 | __TLR_PACKED_PRE struct TLR_PACKED_UINT16_Ttag { 315 | TLR_UINT16 usData; 316 | } __TLR_PACKED_POST; 317 | typedef struct TLR_PACKED_UINT16_Ttag TLR_PACKED_UINT16_T; 318 | 319 | 320 | __TLR_PACKED_PRE struct TLR_PACKED_UINT32_Ttag { 321 | TLR_UINT32 ulData; 322 | } __TLR_PACKED_POST; 323 | typedef struct TLR_PACKED_UINT32_Ttag TLR_PACKED_UINT32_T; 324 | 325 | 326 | /* buffer pointer set (Triple buffer - TBF) */ 327 | typedef struct 328 | { 329 | TLR_UINT8* pabBufA; 330 | TLR_UINT8* pabBufB; 331 | TLR_UINT8* pabBufC; 332 | } TLR_BUFFERPOOL_T; 333 | 334 | typedef TLR_BUFFERPOOL_T TLR_TBF_BUFFERPOOL_T; 335 | typedef TLR_VOID (*TLR_TBF_CALLBACK)(TLR_HANDLE hTripleBuffer, TLR_VOID* pvParam); 336 | 337 | 338 | /*********************** Packet Structure Definitions ************************/ 339 | 340 | /* packet header definition */ 341 | typedef struct 342 | { 343 | TLR_UINT32 ulDest; /* destination of the packet (task message queue reference) */ 344 | TLR_UINT32 ulSrc; /* source of the packet (task message queue reference) */ 345 | TLR_UINT32 ulDestId; /* destination reference (internal use for message routing) */ 346 | TLR_UINT32 ulSrcId; /* source reference (internal use for message routing) */ 347 | TLR_UINT32 ulLen; /* length of packet data (starting from the end of the header) */ 348 | TLR_UINT32 ulId; /* identification reference (internal use by the sender) */ 349 | TLR_UINT32 ulSta; /* operation status code (error code, initialize with 0) */ 350 | TLR_UINT32 ulCmd; /* operation command code */ 351 | TLR_UINT32 ulExt; /* extension count (nonzero in multi-packet transfers) */ 352 | TLR_UINT32 ulRout; /* router reference (internal use for message routing) */ 353 | } TLR_PACKET_HEADER_T; 354 | 355 | 356 | /* definition of a packet with maximum size */ 357 | typedef struct 358 | { 359 | TLR_PACKET_HEADER_T tHead; 360 | TLR_UINT8 abData[TLR_MAX_PACKET_SIZE - sizeof (TLR_PACKET_HEADER_T)]; 361 | } TLR_PACKET_T; 362 | 363 | 364 | /* definition of a packet with minimum size */ 365 | typedef struct 366 | { 367 | TLR_PACKET_HEADER_T tHead; 368 | } TLR_EMPTY_PACKET_T; 369 | 370 | 371 | 372 | /*****************************************************************************/ 373 | /* Global Variables */ 374 | /*****************************************************************************/ 375 | 376 | 377 | /* none */ 378 | 379 | 380 | 381 | /*****************************************************************************/ 382 | /* Macros */ 383 | /*****************************************************************************/ 384 | 385 | 386 | /* none */ 387 | 388 | 389 | 390 | /*****************************************************************************/ 391 | /* Functions */ 392 | /*****************************************************************************/ 393 | 394 | 395 | /* none */ 396 | 397 | 398 | 399 | #ifdef __cplusplus 400 | } 401 | #endif /* __cplusplus */ 402 | 403 | #endif /* __TLR_TYPES_H */ 404 | -------------------------------------------------------------------------------- /driver/includes/cifXEndianess.h: -------------------------------------------------------------------------------- 1 | /************************************************************************************** 2 | 3 | Copyright (c) Hilscher Gesellschaft fuer Systemautomation mbH. All Rights Reserved. 4 | 5 | *************************************************************************************** 6 | 7 | $Id: cifXEndianess.h 6598 2014-10-02 08:57:18Z stephans $: 8 | 9 | Description: 10 | Little/Big Endian conversion 11 | 12 | Changes: 13 | Date Description 14 | ----------------------------------------------------------------------------------- 15 | 2010-01-25 added additional braces to the macros 16 | 2009-01-20 initial version 17 | 18 | **************************************************************************************/ 19 | 20 | /*****************************************************************************/ 21 | /*! \file cifXEndianess.h 22 | * Little/Big Endian conversion */ 23 | /*****************************************************************************/ 24 | 25 | #ifndef __CIFX_ENDIANESS__H 26 | #define __CIFX_ENDIANESS__H 27 | 28 | /* Give the user the possibility to use own macros for 29 | endianess conversion */ 30 | #ifndef BIGENDIAN_MACROS_PROVIDED 31 | #ifndef CIFX_TOOLKIT_BIGENDIAN 32 | /* Little endian, so we don't need a conversion */ 33 | #define LE16_TO_HOST(a) (a) 34 | #define LE32_TO_HOST(a) (a) 35 | #define LE64_TO_HOST(a) (a) 36 | #define HOST_TO_LE16(a) (a) 37 | #define HOST_TO_LE32(a) (a) 38 | #define HOST_TO_LE64(a) (a) 39 | #else 40 | /* BIG endian, so we DO need a conversion */ 41 | #define LE16_TO_HOST(a) ( (((a) & 0x00FF) << 8) | \ 42 | (((a) & 0xFF00) >> 8) ) 43 | 44 | #define LE32_TO_HOST(a) ( (((a) & 0x000000FFUL) << 24) | \ 45 | (((a) & 0x0000FF00UL) << 8) | \ 46 | (((a) & 0x00FF0000UL) >> 8) | \ 47 | (((a) & 0xFF000000UL) >> 24) ) 48 | 49 | #define LE64_TO_HOST(a) ( (((a) & 0x00000000000000FFULL) << 56) | \ 50 | (((a) & 0x000000000000FF00ULL) << 40) | \ 51 | (((a) & 0x0000000000FF0000ULL) << 24) | \ 52 | (((a) & 0x00000000FF000000ULL) << 8) | \ 53 | (((a) & 0x000000FF00000000ULL) >> 8) | \ 54 | (((a) & 0x0000FF0000000000ULL) >> 24) | \ 55 | (((a) & 0x00FF000000000000ULL) >> 40) | \ 56 | (((a) & 0xFF00000000000000ULL) >> 56) ) 57 | 58 | #define HOST_TO_LE16(a) LE16_TO_HOST(a) 59 | #define HOST_TO_LE32(a) LE32_TO_HOST(a) 60 | #define HOST_TO_LE64(a) LE64_TO_HOST(a) 61 | #endif 62 | #endif 63 | 64 | typedef enum 65 | { 66 | eCIFX_ENDIANESS_WIDTH_8BIT, 67 | eCIFX_ENDIANESS_WIDTH_16BIT, 68 | eCIFX_ENDIANESS_WIDTH_32BIT, 69 | eCIFX_ENDIANESS_WIDTH_64BIT 70 | 71 | } CIFX_ENDIANESS_WIDTH; 72 | 73 | /*****************************************************************************/ 74 | /*! Structure definition for endianess conversion function. An array of this 75 | * this structure is used for automatically transforming a structure (which 76 | * is described by this structure) from/to host endianess */ 77 | /*****************************************************************************/ 78 | typedef struct CIFX_ENDIANESS_ENTRY_Ttag 79 | { 80 | int iOffset; /*!< Offset inside the buffer */ 81 | CIFX_ENDIANESS_WIDTH eWidth; /*!< Data width of structure */ 82 | int iElementCnt; /*!< Number of elements to convert */ 83 | 84 | } CIFX_ENDIANESS_ENTRY_T, *PCIFX_ENDIANESS_ENTRY_T; 85 | 86 | void cifXConvertEndianess(void* pvBuffer, int iBufferLen, 87 | const CIFX_ENDIANESS_ENTRY_T* atConv, int iConvLen); 88 | 89 | #endif /* __CIFX_ENDIANESS__H */ 90 | -------------------------------------------------------------------------------- /driver/includes/cifXErrors.h: -------------------------------------------------------------------------------- 1 | #ifndef __CIFXERRORS_H__ 2 | #define __CIFXERRORS_H__ 3 | 4 | /******************************************************************************* 5 | * CIF Device Driver Errors 6 | *******************************************************************************/ 7 | /* */ 8 | /* Values are 32 bit values laid out as follows: */ 9 | /* */ 10 | /* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 */ 11 | /* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 */ 12 | /* +---+-+-+-----------------------+-------------------------------+ */ 13 | /* |Sev|C|R| Facility | Code | */ 14 | /* +---+-+-+-----------------------+-------------------------------+ */ 15 | /* */ 16 | /* where */ 17 | /* */ 18 | /* Sev - is the severity code */ 19 | /* */ 20 | /* 00 - Success */ 21 | /* 01 - Informational */ 22 | /* 10 - Warning */ 23 | /* 11 - Error */ 24 | /* */ 25 | /* C - is the Customer code flag */ 26 | /* */ 27 | /* R - is a reserved bit */ 28 | /* */ 29 | /* Facility - is the facility code */ 30 | /* */ 31 | /* Code - is the facility's status code */ 32 | /* */ 33 | /* */ 34 | /* Define the facility codes */ 35 | /* */ 36 | 37 | 38 | /* */ 39 | /* Define the severity codes */ 40 | /* */ 41 | 42 | 43 | /* */ 44 | /* MessageId: CIFX_NO_ERROR */ 45 | /* */ 46 | /* MessageText: */ 47 | /* */ 48 | /* No Error */ 49 | /* */ 50 | #define CIFX_NO_ERROR ((int32_t)0x00000000L) 51 | 52 | /******************************************************************************* 53 | * Generic Errors 54 | *******************************************************************************/ 55 | /* */ 56 | /* MessageId: CIFX_INVALID_POINTER */ 57 | /* */ 58 | /* MessageText: */ 59 | /* */ 60 | /* Invalid pointer (e.g. NULL) passed to driver */ 61 | /* */ 62 | #define CIFX_INVALID_POINTER ((int32_t)0x800A0001L) 63 | 64 | /* */ 65 | /* MessageId: CIFX_INVALID_BOARD */ 66 | /* */ 67 | /* MessageText: */ 68 | /* */ 69 | /* No board with the given name / index available */ 70 | /* */ 71 | #define CIFX_INVALID_BOARD ((int32_t)0x800A0002L) 72 | 73 | /* */ 74 | /* MessageId: CIFX_INVALID_CHANNEL */ 75 | /* */ 76 | /* MessageText: */ 77 | /* */ 78 | /* No channel with the given index available */ 79 | /* */ 80 | #define CIFX_INVALID_CHANNEL ((int32_t)0x800A0003L) 81 | 82 | /* */ 83 | /* MessageId: CIFX_INVALID_HANDLE */ 84 | /* */ 85 | /* MessageText: */ 86 | /* */ 87 | /* Invalid handle passed to driver */ 88 | /* */ 89 | #define CIFX_INVALID_HANDLE ((int32_t)0x800A0004L) 90 | 91 | /* */ 92 | /* MessageId: CIFX_INVALID_PARAMETER */ 93 | /* */ 94 | /* MessageText: */ 95 | /* */ 96 | /* Invalid parameter */ 97 | /* */ 98 | #define CIFX_INVALID_PARAMETER ((int32_t)0x800A0005L) 99 | 100 | /* */ 101 | /* MessageId: CIFX_INVALID_COMMAND */ 102 | /* */ 103 | /* MessageText: */ 104 | /* */ 105 | /* Invalid command */ 106 | /* */ 107 | #define CIFX_INVALID_COMMAND ((int32_t)0x800A0006L) 108 | 109 | /* */ 110 | /* MessageId: CIFX_INVALID_BUFFERSIZE */ 111 | /* */ 112 | /* MessageText: */ 113 | /* */ 114 | /* Invalid buffer size */ 115 | /* */ 116 | #define CIFX_INVALID_BUFFERSIZE ((int32_t)0x800A0007L) 117 | 118 | /* */ 119 | /* MessageId: CIFX_INVALID_ACCESS_SIZE */ 120 | /* */ 121 | /* MessageText: */ 122 | /* */ 123 | /* Invalid access size */ 124 | /* */ 125 | #define CIFX_INVALID_ACCESS_SIZE ((int32_t)0x800A0008L) 126 | 127 | /* */ 128 | /* MessageId: CIFX_FUNCTION_FAILED */ 129 | /* */ 130 | /* MessageText: */ 131 | /* */ 132 | /* Function failed */ 133 | /* */ 134 | #define CIFX_FUNCTION_FAILED ((int32_t)0x800A0009L) 135 | 136 | /* */ 137 | /* MessageId: CIFX_FILE_OPEN_FAILED */ 138 | /* */ 139 | /* MessageText: */ 140 | /* */ 141 | /* File could not be opened */ 142 | /* */ 143 | #define CIFX_FILE_OPEN_FAILED ((int32_t)0x800A000AL) 144 | 145 | /* */ 146 | /* MessageId: CIFX_FILE_SIZE_ZERO */ 147 | /* */ 148 | /* MessageText: */ 149 | /* */ 150 | /* File size is zero */ 151 | /* */ 152 | #define CIFX_FILE_SIZE_ZERO ((int32_t)0x800A000BL) 153 | 154 | /* */ 155 | /* MessageId: CIFX_FILE_LOAD_INSUFF_MEM */ 156 | /* */ 157 | /* MessageText: */ 158 | /* */ 159 | /* Insufficient memory to load file */ 160 | /* */ 161 | #define CIFX_FILE_LOAD_INSUFF_MEM ((int32_t)0x800A000CL) 162 | 163 | /* */ 164 | /* MessageId: CIFX_FILE_CHECKSUM_ERROR */ 165 | /* */ 166 | /* MessageText: */ 167 | /* */ 168 | /* File checksum compare failed */ 169 | /* */ 170 | #define CIFX_FILE_CHECKSUM_ERROR ((int32_t)0x800A000DL) 171 | 172 | /* */ 173 | /* MessageId: CIFX_FILE_READ_ERROR */ 174 | /* */ 175 | /* MessageText: */ 176 | /* */ 177 | /* Error reading from file */ 178 | /* */ 179 | #define CIFX_FILE_READ_ERROR ((int32_t)0x800A000EL) 180 | 181 | /* */ 182 | /* MessageId: CIFX_FILE_TYPE_INVALID */ 183 | /* */ 184 | /* MessageText: */ 185 | /* */ 186 | /* Invalid file type */ 187 | /* */ 188 | #define CIFX_FILE_TYPE_INVALID ((int32_t)0x800A000FL) 189 | 190 | /* */ 191 | /* MessageId: CIFX_FILE_NAME_INVALID */ 192 | /* */ 193 | /* MessageText: */ 194 | /* */ 195 | /* Invalid file name */ 196 | /* */ 197 | #define CIFX_FILE_NAME_INVALID ((int32_t)0x800A0010L) 198 | 199 | /* */ 200 | /* MessageId: CIFX_FUNCTION_NOT_AVAILABLE */ 201 | /* */ 202 | /* MessageText: */ 203 | /* */ 204 | /* Driver function not available */ 205 | /* */ 206 | #define CIFX_FUNCTION_NOT_AVAILABLE ((int32_t)0x800A0011L) 207 | 208 | /* */ 209 | /* MessageId: CIFX_BUFFER_TOO_SHORT */ 210 | /* */ 211 | /* MessageText: */ 212 | /* */ 213 | /* Given buffer is too short */ 214 | /* */ 215 | #define CIFX_BUFFER_TOO_SHORT ((int32_t)0x800A0012L) 216 | 217 | /* */ 218 | /* MessageId: CIFX_MEMORY_MAPPING_FAILED */ 219 | /* */ 220 | /* MessageText: */ 221 | /* */ 222 | /* Failed to map the memory */ 223 | /* */ 224 | #define CIFX_MEMORY_MAPPING_FAILED ((int32_t)0x800A0013L) 225 | 226 | /* */ 227 | /* MessageId: CIFX_NO_MORE_ENTRIES */ 228 | /* */ 229 | /* MessageText: */ 230 | /* */ 231 | /* No more entries available */ 232 | /* */ 233 | #define CIFX_NO_MORE_ENTRIES ((int32_t)0x800A0014L) 234 | 235 | /* */ 236 | /* MessageId: CIFX_CALLBACK_MODE_UNKNOWN */ 237 | /* */ 238 | /* MessageText: */ 239 | /* */ 240 | /* Unkown callback handling mode */ 241 | /* */ 242 | #define CIFX_CALLBACK_MODE_UNKNOWN ((int32_t)0x800A0015L) 243 | 244 | /* */ 245 | /* MessageId: CIFX_CALLBACK_CREATE_EVENT_FAILED */ 246 | /* */ 247 | /* MessageText: */ 248 | /* */ 249 | /* Failed to create callback events */ 250 | /* */ 251 | #define CIFX_CALLBACK_CREATE_EVENT_FAILED ((int32_t)0x800A0016L) 252 | 253 | /* */ 254 | /* MessageId: CIFX_CALLBACK_CREATE_RECV_BUFFER */ 255 | /* */ 256 | /* MessageText: */ 257 | /* */ 258 | /* Failed to create callback receive buffer */ 259 | /* */ 260 | #define CIFX_CALLBACK_CREATE_RECV_BUFFER ((int32_t)0x800A0017L) 261 | 262 | /* */ 263 | /* MessageId: CIFX_CALLBACK_ALREADY_USED */ 264 | /* */ 265 | /* MessageText: */ 266 | /* */ 267 | /* Callback already used */ 268 | /* */ 269 | #define CIFX_CALLBACK_ALREADY_USED ((int32_t)0x800A0018L) 270 | 271 | /* */ 272 | /* MessageId: CIFX_CALLBACK_NOT_REGISTERED */ 273 | /* */ 274 | /* MessageText: */ 275 | /* */ 276 | /* Callback was not registerd before */ 277 | /* */ 278 | #define CIFX_CALLBACK_NOT_REGISTERED ((int32_t)0x800A0019L) 279 | 280 | /* */ 281 | /* MessageId: CIFX_INTERRUPT_DISABLED */ 282 | /* */ 283 | /* MessageText: */ 284 | /* */ 285 | /* Interrupt is disabled */ 286 | /* */ 287 | #define CIFX_INTERRUPT_DISABLED ((int32_t)0x800A001AL) 288 | 289 | /******************************************************************************* 290 | * Generic Driver Errors 291 | *******************************************************************************/ 292 | /* */ 293 | /* MessageId: CIFX_DRV_NOT_INITIALIZED */ 294 | /* */ 295 | /* MessageText: */ 296 | /* */ 297 | /* Driver not initialized */ 298 | /* */ 299 | #define CIFX_DRV_NOT_INITIALIZED ((int32_t)0x800B0001L) 300 | 301 | /* */ 302 | /* MessageId: CIFX_DRV_INIT_STATE_ERROR */ 303 | /* */ 304 | /* MessageText: */ 305 | /* */ 306 | /* Driver init state error */ 307 | /* */ 308 | #define CIFX_DRV_INIT_STATE_ERROR ((int32_t)0x800B0002L) 309 | 310 | /* */ 311 | /* MessageId: CIFX_DRV_READ_STATE_ERROR */ 312 | /* */ 313 | /* MessageText: */ 314 | /* */ 315 | /* Driver read state error */ 316 | /* */ 317 | #define CIFX_DRV_READ_STATE_ERROR ((int32_t)0x800B0003L) 318 | 319 | /* */ 320 | /* MessageId: CIFX_DRV_CMD_ACTIVE */ 321 | /* */ 322 | /* MessageText: */ 323 | /* */ 324 | /* Command is active on device */ 325 | /* */ 326 | #define CIFX_DRV_CMD_ACTIVE ((int32_t)0x800B0004L) 327 | 328 | /* */ 329 | /* MessageId: CIFX_DRV_DOWNLOAD_FAILED */ 330 | /* */ 331 | /* MessageText: */ 332 | /* */ 333 | /* General error during download */ 334 | /* */ 335 | #define CIFX_DRV_DOWNLOAD_FAILED ((int32_t)0x800B0005L) 336 | 337 | /* */ 338 | /* MessageId: CIFX_DRV_WRONG_DRIVER_VERSION */ 339 | /* */ 340 | /* MessageText: */ 341 | /* */ 342 | /* Wrong driver version */ 343 | /* */ 344 | #define CIFX_DRV_WRONG_DRIVER_VERSION ((int32_t)0x800B0006L) 345 | 346 | /* */ 347 | /* MessageId: CIFX_DRV_DRIVER_NOT_LOADED */ 348 | /* */ 349 | /* MessageText: */ 350 | /* */ 351 | /* CIFx driver is not running */ 352 | /* */ 353 | #define CIFX_DRV_DRIVER_NOT_LOADED ((int32_t)0x800B0030L) 354 | 355 | /* */ 356 | /* MessageId: CIFX_DRV_INIT_ERROR */ 357 | /* */ 358 | /* MessageText: */ 359 | /* */ 360 | /* Failed to initialize the device */ 361 | /* */ 362 | #define CIFX_DRV_INIT_ERROR ((int32_t)0x800B0031L) 363 | 364 | /* */ 365 | /* MessageId: CIFX_DRV_CHANNEL_NOT_INITIALIZED */ 366 | /* */ 367 | /* MessageText: */ 368 | /* */ 369 | /* Channel not initialized (xOpenChannel not called) */ 370 | /* */ 371 | #define CIFX_DRV_CHANNEL_NOT_INITIALIZED ((int32_t)0x800B0032L) 372 | 373 | /* */ 374 | /* MessageId: CIFX_DRV_IO_CONTROL_FAILED */ 375 | /* */ 376 | /* MessageText: */ 377 | /* */ 378 | /* IOControl call failed */ 379 | /* */ 380 | #define CIFX_DRV_IO_CONTROL_FAILED ((int32_t)0x800B0033L) 381 | 382 | /* */ 383 | /* MessageId: CIFX_DRV_NOT_OPENED */ 384 | /* */ 385 | /* MessageText: */ 386 | /* */ 387 | /* Driver was not opened */ 388 | /* */ 389 | #define CIFX_DRV_NOT_OPENED ((int32_t)0x800B0034L) 390 | 391 | /* */ 392 | /* MessageId: CIFX_DRV_DOWNLOAD_STORAGE_UNKNOWN */ 393 | /* */ 394 | /* MessageText: */ 395 | /* */ 396 | /* Unknown download storage type (RAM/FLASH based) found */ 397 | /* */ 398 | #define CIFX_DRV_DOWNLOAD_STORAGE_UNKNOWN ((int32_t)0x800B0040L) 399 | 400 | /* */ 401 | /* MessageId: CIFX_DRV_DOWNLOAD_FW_WRONG_CHANNEL */ 402 | /* */ 403 | /* MessageText: */ 404 | /* */ 405 | /* Channel number for a firmware download not supported */ 406 | /* */ 407 | #define CIFX_DRV_DOWNLOAD_FW_WRONG_CHANNEL ((int32_t)0x800B0041L) 408 | 409 | /* */ 410 | /* MessageId: CIFX_DRV_DOWNLOAD_MODULE_NO_BASEOS */ 411 | /* */ 412 | /* MessageText: */ 413 | /* */ 414 | /* Modules are not allowed without a Base OS firmware */ 415 | /* */ 416 | #define CIFX_DRV_DOWNLOAD_MODULE_NO_BASEOS ((int32_t)0x800B0042L) 417 | 418 | /******************************************************************************* 419 | * Generic Device Errors 420 | *******************************************************************************/ 421 | /* */ 422 | /* MessageId: CIFX_DEV_DPM_ACCESS_ERROR */ 423 | /* */ 424 | /* MessageText: */ 425 | /* */ 426 | /* Dual port memory not accessable (board not found) */ 427 | /* */ 428 | #define CIFX_DEV_DPM_ACCESS_ERROR ((int32_t)0x800C0010L) 429 | 430 | /* */ 431 | /* MessageId: CIFX_DEV_NOT_READY */ 432 | /* */ 433 | /* MessageText: */ 434 | /* */ 435 | /* Device not ready (ready flag failed) */ 436 | /* */ 437 | #define CIFX_DEV_NOT_READY ((int32_t)0x800C0011L) 438 | 439 | /* */ 440 | /* MessageId: CIFX_DEV_NOT_RUNNING */ 441 | /* */ 442 | /* MessageText: */ 443 | /* */ 444 | /* Device not running (running flag failed) */ 445 | /* */ 446 | #define CIFX_DEV_NOT_RUNNING ((int32_t)0x800C0012L) 447 | 448 | /* */ 449 | /* MessageId: CIFX_DEV_WATCHDOG_FAILED */ 450 | /* */ 451 | /* MessageText: */ 452 | /* */ 453 | /* Watchdog test failed */ 454 | /* */ 455 | #define CIFX_DEV_WATCHDOG_FAILED ((int32_t)0x800C0013L) 456 | 457 | /* */ 458 | /* MessageId: CIFX_DEV_SYSERR */ 459 | /* */ 460 | /* MessageText: */ 461 | /* */ 462 | /* Error in handshake flags */ 463 | /* */ 464 | #define CIFX_DEV_SYSERR ((int32_t)0x800C0015L) 465 | 466 | /* */ 467 | /* MessageId: CIFX_DEV_MAILBOX_FULL */ 468 | /* */ 469 | /* MessageText: */ 470 | /* */ 471 | /* Send mailbox is full */ 472 | /* */ 473 | #define CIFX_DEV_MAILBOX_FULL ((int32_t)0x800C0016L) 474 | 475 | /* */ 476 | /* MessageId: CIFX_DEV_PUT_TIMEOUT */ 477 | /* */ 478 | /* MessageText: */ 479 | /* */ 480 | /* Send packet timeout */ 481 | /* */ 482 | #define CIFX_DEV_PUT_TIMEOUT ((int32_t)0x800C0017L) 483 | 484 | /* */ 485 | /* MessageId: CIFX_DEV_GET_TIMEOUT */ 486 | /* */ 487 | /* MessageText: */ 488 | /* */ 489 | /* Receive packet timeout */ 490 | /* */ 491 | #define CIFX_DEV_GET_TIMEOUT ((int32_t)0x800C0018L) 492 | 493 | /* */ 494 | /* MessageId: CIFX_DEV_GET_NO_PACKET */ 495 | /* */ 496 | /* MessageText: */ 497 | /* */ 498 | /* No packet available */ 499 | /* */ 500 | #define CIFX_DEV_GET_NO_PACKET ((int32_t)0x800C0019L) 501 | 502 | /* */ 503 | /* MessageId: CIFX_DEV_MAILBOX_TOO_SHORT */ 504 | /* */ 505 | /* MessageText: */ 506 | /* */ 507 | /* Mailbox too short */ 508 | /* */ 509 | #define CIFX_DEV_MAILBOX_TOO_SHORT ((int32_t)0x800C001AL) 510 | 511 | /* */ 512 | /* MessageId: CIFX_DEV_RESET_TIMEOUT */ 513 | /* */ 514 | /* MessageText: */ 515 | /* */ 516 | /* Reset command timeout */ 517 | /* */ 518 | #define CIFX_DEV_RESET_TIMEOUT ((int32_t)0x800C0020L) 519 | 520 | /* */ 521 | /* MessageId: CIFX_DEV_NO_COM_FLAG */ 522 | /* */ 523 | /* MessageText: */ 524 | /* */ 525 | /* COM-flag not set */ 526 | /* */ 527 | #define CIFX_DEV_NO_COM_FLAG ((int32_t)0x800C0021L) 528 | 529 | /* */ 530 | /* MessageId: CIFX_DEV_EXCHANGE_FAILED */ 531 | /* */ 532 | /* MessageText: */ 533 | /* */ 534 | /* I/O data exchange failed */ 535 | /* */ 536 | #define CIFX_DEV_EXCHANGE_FAILED ((int32_t)0x800C0022L) 537 | 538 | /* */ 539 | /* MessageId: CIFX_DEV_EXCHANGE_TIMEOUT */ 540 | /* */ 541 | /* MessageText: */ 542 | /* */ 543 | /* I/O data exchange timeout */ 544 | /* */ 545 | #define CIFX_DEV_EXCHANGE_TIMEOUT ((int32_t)0x800C0023L) 546 | 547 | /* */ 548 | /* MessageId: CIFX_DEV_COM_MODE_UNKNOWN */ 549 | /* */ 550 | /* MessageText: */ 551 | /* */ 552 | /* Unknown I/O exchange mode */ 553 | /* */ 554 | #define CIFX_DEV_COM_MODE_UNKNOWN ((int32_t)0x800C0024L) 555 | 556 | /* */ 557 | /* MessageId: CIFX_DEV_FUNCTION_FAILED */ 558 | /* */ 559 | /* MessageText: */ 560 | /* */ 561 | /* Device function failed */ 562 | /* */ 563 | #define CIFX_DEV_FUNCTION_FAILED ((int32_t)0x800C0025L) 564 | 565 | /* */ 566 | /* MessageId: CIFX_DEV_DPMSIZE_MISMATCH */ 567 | /* */ 568 | /* MessageText: */ 569 | /* */ 570 | /* DPM size differs from configuration */ 571 | /* */ 572 | #define CIFX_DEV_DPMSIZE_MISMATCH ((int32_t)0x800C0026L) 573 | 574 | /* */ 575 | /* MessageId: CIFX_DEV_STATE_MODE_UNKNOWN */ 576 | /* */ 577 | /* MessageText: */ 578 | /* */ 579 | /* Unknown state mode */ 580 | /* */ 581 | #define CIFX_DEV_STATE_MODE_UNKNOWN ((int32_t)0x800C0027L) 582 | 583 | /* */ 584 | /* MessageId: CIFX_DEV_HW_PORT_IS_USED */ 585 | /* */ 586 | /* MessageText: */ 587 | /* */ 588 | /* Device is still accessed */ 589 | /* */ 590 | #define CIFX_DEV_HW_PORT_IS_USED ((int32_t)0x800C0028L) 591 | 592 | /* */ 593 | /* MessageId: CIFX_DEV_CONFIG_LOCK_TIMEOUT */ 594 | /* */ 595 | /* MessageText: */ 596 | /* */ 597 | /* Configuration locking timeout */ 598 | /* */ 599 | #define CIFX_DEV_CONFIG_LOCK_TIMEOUT ((int32_t)0x800C0029L) 600 | 601 | /* */ 602 | /* MessageId: CIFX_DEV_CONFIG_UNLOCK_TIMEOUT */ 603 | /* */ 604 | /* MessageText: */ 605 | /* */ 606 | /* Configuration unlocking timeout */ 607 | /* */ 608 | #define CIFX_DEV_CONFIG_UNLOCK_TIMEOUT ((int32_t)0x800C002AL) 609 | 610 | /* */ 611 | /* MessageId: CIFX_DEV_HOST_STATE_SET_TIMEOUT */ 612 | /* */ 613 | /* MessageText: */ 614 | /* */ 615 | /* Set HOST state timeout */ 616 | /* */ 617 | #define CIFX_DEV_HOST_STATE_SET_TIMEOUT ((int32_t)0x800C002BL) 618 | 619 | /* */ 620 | /* MessageId: CIFX_DEV_HOST_STATE_CLEAR_TIMEOUT */ 621 | /* */ 622 | /* MessageText: */ 623 | /* */ 624 | /* Clear HOST state timeout */ 625 | /* */ 626 | #define CIFX_DEV_HOST_STATE_CLEAR_TIMEOUT ((int32_t)0x800C002CL) 627 | 628 | /* */ 629 | /* MessageId: CIFX_DEV_INITIALIZATION_TIMEOUT */ 630 | /* */ 631 | /* MessageText: */ 632 | /* */ 633 | /* Timeout during channel initialization */ 634 | /* */ 635 | #define CIFX_DEV_INITIALIZATION_TIMEOUT ((int32_t)0x800C002DL) 636 | 637 | /* */ 638 | /* MessageId: CIFX_DEV_BUS_STATE_ON_TIMEOUT */ 639 | /* */ 640 | /* MessageText: */ 641 | /* */ 642 | /* Set Bus ON Timeout */ 643 | /* */ 644 | #define CIFX_DEV_BUS_STATE_ON_TIMEOUT ((int32_t)0x800C002EL) 645 | 646 | /* */ 647 | /* MessageId: CIFX_DEV_BUS_STATE_OFF_TIMEOUT */ 648 | /* */ 649 | /* MessageText: */ 650 | /* */ 651 | /* Set Bus OFF Timeout */ 652 | /* */ 653 | #define CIFX_DEV_BUS_STATE_OFF_TIMEOUT ((int32_t)0x800C002FL) 654 | 655 | /* */ 656 | /* MessageId: CIFX_DEV_MODULE_ALREADY_RUNNING */ 657 | /* */ 658 | /* MessageText: */ 659 | /* */ 660 | /* Module already running */ 661 | /* */ 662 | #define CIFX_DEV_MODULE_ALREADY_RUNNING ((int32_t)0x800C0040L) 663 | 664 | /* */ 665 | /* MessageId: CIFX_DEV_MODULE_ALREADY_EXISTS */ 666 | /* */ 667 | /* MessageText: */ 668 | /* */ 669 | /* Module already exists */ 670 | /* */ 671 | #define CIFX_DEV_MODULE_ALREADY_EXISTS ((int32_t)0x800C0041L) 672 | 673 | /* */ 674 | /* MessageId: CIFX_DEV_DMA_INSUFF_BUFFER_COUNT */ 675 | /* */ 676 | /* MessageText: */ 677 | /* */ 678 | /* Number of configured DMA buffers insufficient */ 679 | /* */ 680 | #define CIFX_DEV_DMA_INSUFF_BUFFER_COUNT ((int32_t)0x800C0050L) 681 | 682 | /* */ 683 | /* MessageId: CIFX_DEV_DMA_BUFFER_TOO_SMALL */ 684 | /* */ 685 | /* MessageText: */ 686 | /* */ 687 | /* DMA buffers size too small (min size 256Byte) */ 688 | /* */ 689 | #define CIFX_DEV_DMA_BUFFER_TOO_SMALL ((int32_t)0x800C0051L) 690 | 691 | /* */ 692 | /* MessageId: CIFX_DEV_DMA_BUFFER_TOO_BIG */ 693 | /* */ 694 | /* MessageText: */ 695 | /* */ 696 | /* DMA buffers size too big (max size 63,75KByte) */ 697 | /* */ 698 | #define CIFX_DEV_DMA_BUFFER_TOO_BIG ((int32_t)0x800C0052L) 699 | 700 | /* */ 701 | /* MessageId: CIFX_DEV_DMA_BUFFER_NOT_ALIGNED */ 702 | /* */ 703 | /* MessageText: */ 704 | /* */ 705 | /* DMA buffer alignment failed (must be 256Byte) */ 706 | /* */ 707 | #define CIFX_DEV_DMA_BUFFER_NOT_ALIGNED ((int32_t)0x800C0053L) 708 | 709 | /* */ 710 | /* MessageId: CIFX_DEV_DMA_HANSHAKEMODE_NOT_SUPPORTED */ 711 | /* */ 712 | /* MessageText: */ 713 | /* */ 714 | /* I/O data uncontrolled handshake mode not supported */ 715 | /* */ 716 | #define CIFX_DEV_DMA_HANSHAKEMODE_NOT_SUPPORTED ((int32_t)0x800C0054L) 717 | 718 | /* */ 719 | /* MessageId: CIFX_DEV_DMA_IO_AREA_NOT_SUPPORTED */ 720 | /* */ 721 | /* MessageText: */ 722 | /* */ 723 | /* I/O area in DMA mode not supported (only area 0 possible) */ 724 | /* */ 725 | #define CIFX_DEV_DMA_IO_AREA_NOT_SUPPORTED ((int32_t)0x800C0055L) 726 | 727 | /* */ 728 | /* MessageId: CIFX_DEV_DMA_STATE_ON_TIMEOUT */ 729 | /* */ 730 | /* MessageText: */ 731 | /* */ 732 | /* Set DMA ON Timeout */ 733 | /* */ 734 | #define CIFX_DEV_DMA_STATE_ON_TIMEOUT ((int32_t)0x800C0056L) 735 | 736 | /* */ 737 | /* MessageId: CIFX_DEV_DMA_STATE_OFF_TIMEOUT */ 738 | /* */ 739 | /* MessageText: */ 740 | /* */ 741 | /* Set DMA OFF Timeout */ 742 | /* */ 743 | #define CIFX_DEV_DMA_STATE_OFF_TIMEOUT ((int32_t)0x800C0057L) 744 | 745 | /* */ 746 | /* MessageId: CIFX_DEV_SYNC_STATE_INVALID_MODE */ 747 | /* */ 748 | /* MessageText: */ 749 | /* */ 750 | /* Device is in invalid mode for this operation */ 751 | /* */ 752 | #define CIFX_DEV_SYNC_STATE_INVALID_MODE ((int32_t)0x800C0058L) 753 | 754 | /* */ 755 | /* MessageId: CIFX_DEV_SYNC_STATE_TIMEOUT */ 756 | /* */ 757 | /* MessageText: */ 758 | /* */ 759 | /* Waiting for synchronization event bits timed out */ 760 | /* */ 761 | #define CIFX_DEV_SYNC_STATE_TIMEOUT ((int32_t)0x800C0059L) 762 | 763 | /******************************************************************************* 764 | * CIFX API Transport Errors 765 | *******************************************************************************/ 766 | /* */ 767 | /* MessageId: CIFX_TRANSPORT_SEND_TIMEOUT */ 768 | /* */ 769 | /* MessageText: */ 770 | /* */ 771 | /* Time out while sending data */ 772 | /* */ 773 | #define CIFX_TRANSPORT_SEND_TIMEOUT ((int32_t)0x800D0001L) 774 | 775 | /* */ 776 | /* MessageId: CIFX_TRANSPORT_RECV_TIMEOUT */ 777 | /* */ 778 | /* MessageText: */ 779 | /* */ 780 | /* Time out waiting for incoming data */ 781 | /* */ 782 | #define CIFX_TRANSPORT_RECV_TIMEOUT ((int32_t)0x800D0002L) 783 | 784 | /* */ 785 | /* MessageId: CIFX_TRANSPORT_CONNECT */ 786 | /* */ 787 | /* MessageText: */ 788 | /* */ 789 | /* Unable to communicate to the device / no answer */ 790 | /* */ 791 | #define CIFX_TRANSPORT_CONNECT ((int32_t)0x800D0003L) 792 | 793 | /* */ 794 | /* MessageId: CIFX_TRANSPORT_ABORTED */ 795 | /* */ 796 | /* MessageText: */ 797 | /* */ 798 | /* Transfer has been aborted due to keep alive timeout or interface detachment */ 799 | /* */ 800 | #define CIFX_TRANSPORT_ABORTED ((long)0x800D0004L) 801 | 802 | /* */ 803 | /* MessageId: CIFX_TRANSPORT_INVALID_RESPONSE */ 804 | /* */ 805 | /* MessageText: */ 806 | /* */ 807 | /* The packet response was rejected due to invalid packet data */ 808 | /* */ 809 | #define CIFX_TRANSPORT_INVALID_RESPONSE ((long)0x800D0005L) 810 | 811 | /* */ 812 | /* MessageId: CIFX_TRANSPORT_UNKNOWN_DATALAYER */ 813 | /* */ 814 | /* MessageText: */ 815 | /* */ 816 | /* The data layer provided by the device is not supported */ 817 | /* */ 818 | #define CIFX_TRANSPORT_UNKNOWN_DATALAYER ((long)0x800D0006L) 819 | 820 | /* */ 821 | /* MessageId: CIFX_CONNECTOR_FUNCTIONS_READ_ERROR */ 822 | /* */ 823 | /* MessageText: */ 824 | /* */ 825 | /* Error reading the connector functions from the DLL */ 826 | /* */ 827 | #define CIFX_CONNECTOR_FUNCTIONS_READ_ERROR ((long)0x800D0010L) 828 | 829 | /* */ 830 | /* MessageId: CIFX_CONNECTOR_IDENTIFIER_TOO_LONG */ 831 | /* */ 832 | /* MessageText: */ 833 | /* */ 834 | /* Connector delivers an identifier longer than 6 characters */ 835 | /* */ 836 | #define CIFX_CONNECTOR_IDENTIFIER_TOO_LONG ((long)0x800D0011L) 837 | 838 | /* */ 839 | /* MessageId: CIFX_CONNECTOR_IDENTIFIER_EMPTY */ 840 | /* */ 841 | /* MessageText: */ 842 | /* */ 843 | /* Connector delivers an empty dentifier */ 844 | /* */ 845 | #define CIFX_CONNECTOR_IDENTIFIER_EMPTY ((long)0x800D0012L) 846 | 847 | /* */ 848 | /* MessageId: CIFX_CONNECTOR_DUPLICATE_IDENTIFIER */ 849 | /* */ 850 | /* MessageText: */ 851 | /* */ 852 | /* Connector identifier already used */ 853 | /* */ 854 | #define CIFX_CONNECTOR_DUPLICATE_IDENTIFIER ((long)0x800D0013L) 855 | 856 | /******************************************************************************* 857 | * CIFX API Transport Header State Errors 858 | *******************************************************************************/ 859 | /* */ 860 | /* MessageId: CIFX_TRANSPORT_ERROR_UNKNOWN */ 861 | /* */ 862 | /* MessageText: */ 863 | /* */ 864 | /* Unknown error code in transport header */ 865 | /* */ 866 | #define CIFX_TRANSPORT_ERROR_UNKNOWN ((int32_t)0x800E0001L) 867 | 868 | /* */ 869 | /* MessageId: CIFX_TRANSPORT_CHECKSUM_ERROR */ 870 | /* */ 871 | /* MessageText: */ 872 | /* */ 873 | /* CRC16 checksum failed */ 874 | /* */ 875 | #define CIFX_TRANSPORT_CHECKSUM_ERROR ((int32_t)0x800E0002L) 876 | 877 | /* */ 878 | /* MessageId: CIFX_TRANSPORT_LENGTH_INCOMPLETE */ 879 | /* */ 880 | /* MessageText: */ 881 | /* */ 882 | /* Transaction with inclomplete length detected */ 883 | /* */ 884 | #define CIFX_TRANSPORT_LENGTH_INCOMPLETE ((int32_t)0x800E0003L) 885 | 886 | /* */ 887 | /* MessageId: CIFX_TRANSPORT_DATA_TYPE_UNKOWN */ 888 | /* */ 889 | /* MessageText: */ 890 | /* */ 891 | /* Device does not support requested data type */ 892 | /* */ 893 | #define CIFX_TRANSPORT_DATA_TYPE_UNKOWN ((int32_t)0x800E0004L) 894 | 895 | /* */ 896 | /* MessageId: CIFX_TRANSPORT_DEVICE_UNKNOWN */ 897 | /* */ 898 | /* MessageText: */ 899 | /* */ 900 | /* Device not available/unknown */ 901 | /* */ 902 | #define CIFX_TRANSPORT_DEVICE_UNKNOWN ((int32_t)0x800E0005L) 903 | 904 | /* */ 905 | /* MessageId: CIFX_TRANSPORT_CHANNEL_UNKNOWN */ 906 | /* */ 907 | /* MessageText: */ 908 | /* */ 909 | /* Channel not available/unknown */ 910 | /* */ 911 | #define CIFX_TRANSPORT_CHANNEL_UNKNOWN ((int32_t)0x800E0006L) 912 | 913 | /* */ 914 | /* MessageId: CIFX_TRANSPORT_SEQUENCE */ 915 | /* */ 916 | /* MessageText: */ 917 | /* */ 918 | /* Sequence error detected */ 919 | /* */ 920 | #define CIFX_TRANSPORT_SEQUENCE ((int32_t)0x800E0007L) 921 | 922 | /* */ 923 | /* MessageId: CIFX_TRANSPORT_BUFFEROVERFLOW */ 924 | /* */ 925 | /* MessageText: */ 926 | /* */ 927 | /* Buffer overflow detected */ 928 | /* */ 929 | #define CIFX_TRANSPORT_BUFFEROVERFLOW ((int32_t)0x800E0008L) 930 | 931 | /* */ 932 | /* MessageId: CIFX_TRANSPORT_RESOURCE */ 933 | /* */ 934 | /* MessageText: */ 935 | /* */ 936 | /* Device signals out of resources */ 937 | /* */ 938 | #define CIFX_TRANSPORT_RESOURCE ((int32_t)0x800E0009L) 939 | 940 | /* */ 941 | /* MessageId: CIFX_TRANSPORT_KEEPALIVE */ 942 | /* */ 943 | /* MessageText: */ 944 | /* */ 945 | /* Device connection monitoring error (Keep alive) */ 946 | /* */ 947 | #define CIFX_TRANSPORT_KEEPALIVE ((int32_t)0x800E000AL) 948 | 949 | /* */ 950 | /* MessageId: CIFX_TRANSPORT_DATA_TOO_SHORT */ 951 | /* */ 952 | /* MessageText: */ 953 | /* */ 954 | /* Received transaction data too short */ 955 | /* */ 956 | #define CIFX_TRANSPORT_DATA_TOO_SHORT ((int32_t)0x800E000BL) 957 | 958 | /*******************************************************************************/ 959 | 960 | #endif /*__CIFXERRORS_H__ */ 961 | -------------------------------------------------------------------------------- /driver/includes/cifXUser.h: -------------------------------------------------------------------------------- 1 | /************************************************************************************** 2 | 3 | Copyright (c) Hilscher Gesellschaft fuer Systemautomation mbH. All Rights Reserved. 4 | 5 | *************************************************************************************** 6 | 7 | $Id: cifXUser.h 7155 2015-07-23 11:12:18Z Robert $: 8 | 9 | Description: 10 | CIFx driver API definition file 11 | 12 | Changes: 13 | Date Description 14 | ----------------------------------------------------------------------------------- 15 | 2015-07-23 Added API function pointer definitions usable in a pointer table 16 | 2015-03-31 Added guard for _MSC_VER to allow compilation using -wundef 17 | 2014-07-07 Added support for IAR C/C++ Compiler (ARM Cores only) 18 | 2014-04-28 Added support for armcc compiler 19 | 2012-01-31 Added COM-State notification structure 20 | 2011-12-12 SYSTEM_CHANNEL_SYSTEM_STATUS_BLOCK structure extended by ulHWFeatures 21 | 2011-11-29 Added xSysdeviceExtendedMemory() 22 | 2011-09-13 - CIFX_MAX_PACKET_SIZE changed from 1600 to 1596 bytes because of mailbox counter 23 | - xSysdeviceBoostart() function added 24 | 2010-04-22 Added ulBootError to SYSTEM_CHANNEL_SYSTEM_STATUS_BLOCK 25 | 2010-04-15 - Added timeout to xChannelSyncState function 26 | - Added CIFX_SYNC_WAIT_CMD to be able to wait for sync signalling by firmware 27 | 2010-04-01 Data types update 28 | 2010-03-23 - Data types changed for 32/64Bit usage 29 | - Event functions include 30 | 2009-10-29 DMA state function and states included 31 | 2009-10-01 CIFX_TO_WAIT_COS_CMD/ACK changed to 20ms 32 | 2009-06-08 SYSTEM_CHANNEL_SYSTEM_INFO_BLOCK structure extended by bDevIdNumber 33 | 2009-04-28 New download mode for modules included 34 | 2009-01-23 netX DPM signature included 35 | 2008-11-25 NETX_SYSTEM_STATUS block structure updated 36 | - removed LEDs 37 | - added CPU load and system start time values 38 | 2008-06-19 xDriverRestartDevice() function parameters changed 39 | 2008-05-27 APIENTRY now set empty, if not defined outside the file 40 | 2008-04-29 DOWNLOAD_MODE_LICENSECODE added 41 | 2008-03-17 xDriverRestartDevice() included 42 | 2008-02-22 Firmware version changed from Major,Minor,Revision,Build to 43 | Major,Minor,Build,Revision, as decided on 19.11.2007 44 | 2007-07-26 Added DOWNLOAD_MODE_BOOTLOADER 45 | 2007-04-17 Parameters for the following functions changed 46 | - xSysdeviceDownload/Upload 47 | - xSysdeviceFindFirstFile/NextFile 48 | - xChannelDownload/Upload 49 | - xChannelFindFirstFile/NextFile 50 | 2007-04-13 CALLBACK state definition included 51 | 2007-04-10 - PFN_TRANSFER_PACKET moved to toolkit headers 52 | - CIFX_COLDSTART and CIFX_WARMSTART changed to 53 | CIFX_SYSTEMSTART and CIFX_CHANNELINIT 54 | 2007-04-04 xChannelBusState() included 55 | 2007-03-28 typedef for PFN_TRANSFER_PACKET included 56 | 2007-03-21 Added: 57 | - xChannelIOInfo 58 | - xSysdeviceReset 59 | - CIFX_WARMSTART/CIFX_COLDSTART 60 | 2007-03-20 Added: 61 | - xChannelFindFirstFile 62 | - xChannelFindNextFile 63 | - xChannelUpload 64 | - xSysdeviceFindFirstFile 65 | - xSysdeviceFindNextFile 66 | - xSysdeviceUpload 67 | 2007-03-16 Removed CIFX_DRIVER define around API functions, 68 | as it is not needed anymore (since V0.920 of driver) 69 | 2006-12-04 PACKED_POST moved to closing curly brace after type definition 70 | 2006-10-18 Changed HANDLE to CIFXHANDLE which is a void*, to be 71 | usable on VxWorks without compiler warnings 72 | 2006-03-17 created 73 | 74 | **************************************************************************************/ 75 | 76 | /*****************************************************************************/ 77 | /*! \addtogroup CIFX_DRIVER_API cifX Driver API implementation */ 78 | /*! \{ */ 79 | /*****************************************************************************/ 80 | 81 | /* prevent multiple inclusion */ 82 | #ifndef __CIFxUSER_H 83 | #define __CIFxUSER_H 84 | 85 | #if defined(_MSC_VER) 86 | #if _MSC_VER >= 1000 87 | #define __CIFx_PACKED_PRE 88 | #define __CIFx_PACKED_POST 89 | #pragma once 90 | #pragma pack(1) /* Always align structures to 1Byte boundery */ 91 | #ifndef STRICT /* Check Typedefinition */ 92 | #define STRICT 93 | #endif 94 | #endif /* _MSC_VER >= 1000 */ 95 | #endif /* _MSC_VER */ 96 | 97 | /* support for GNU compiler */ 98 | #ifdef __GNUC__ 99 | #define __CIFx_PACKED_PRE 100 | #define __CIFx_PACKED_POST __attribute__((packed)) 101 | #endif 102 | 103 | /* support for ARMCC and IAR compiler (ARM cores only) */ 104 | #if defined (__ADS__) || defined (__REALVIEW__) || defined (__CC_ARM) || defined (__ICCARM__) 105 | /* tight packing of structure members */ 106 | #define __CIFx_PACKED_PRE __packed 107 | #define __CIFx_PACKED_POST 108 | #endif /* __ADS__, __REALVIEW__, __CC_ARM */ 109 | 110 | #ifdef __cplusplus 111 | extern "C" { 112 | #endif /* _cplusplus */ 113 | 114 | #include 115 | 116 | #ifndef APIENTRY 117 | #define APIENTRY 118 | #endif 119 | 120 | /* ------------------------------------------------------------------------------------ */ 121 | /* global definitions */ 122 | /* ------------------------------------------------------------------------------------ */ 123 | typedef void* CIFXHANDLE; 124 | 125 | /* DPM memory validation */ 126 | #define CIFX_DPM_NO_MEMORY_ASSIGNED 0x0BAD0BADUL 127 | #define CIFX_DPM_INVALID_CONTENT 0xFFFFFFFFUL 128 | 129 | #define CIFX_DPMSIGNATURE_BSL_STR "BOOT" 130 | #define CIFX_DPMSIGNATURE_BSL_VAL 0x544F4F42UL 131 | #define CIFX_DPMSIGNATURE_FW_STR "netX" 132 | #define CIFX_DPMSIGNATURE_FW_VAL 0x5874656EUL 133 | 134 | /* CIFx global timeouts in milliseconds */ 135 | #define CIFX_TO_WAIT_HW_RESET_ACTIVE 2000UL 136 | #define CIFX_TO_WAIT_HW 2000UL 137 | #define CIFX_TO_WAIT_COS_CMD 20UL 138 | #define CIFX_TO_WAIT_COS_ACK 20UL 139 | #define CIFX_TO_SEND_PACKET 5000UL 140 | #define CIFX_TO_1ST_PACKET 1000UL 141 | #define CIFX_TO_CONT_PACKET 1000UL 142 | #define CIFX_TO_LAST_PACKET 1000UL 143 | #define CIFX_TO_FIRMWARE_START 10000UL 144 | 145 | /* Maximum channel number */ 146 | #define CIFX_MAX_NUMBER_OF_CHANNEL_DEFINITION 8 147 | #define CIFX_MAX_NUMBER_OF_CHANNELS 6 148 | #define CIFX_NO_CHANNEL 0xFFFFFFFF 149 | 150 | /* Maximum file name length */ 151 | #define CIFX_MAX_FILE_NAME_LENGTH 260 152 | #define CIFX_MIN_FILE_NAME_LENGTH 5 153 | 154 | /* The system device port number */ 155 | #define CIFX_SYSTEM_DEVICE 0xFFFFFFFF 156 | 157 | /* Information commands */ 158 | #define CIFX_INFO_CMD_SYSTEM_INFORMATION 1 159 | #define CIFX_INFO_CMD_SYSTEM_INFO_BLOCK 2 160 | #define CIFX_INFO_CMD_SYSTEM_CHANNEL_BLOCK 3 161 | #define CIFX_INFO_CMD_SYSTEM_CONTROL_BLOCK 4 162 | #define CIFX_INFO_CMD_SYSTEM_STATUS_BLOCK 5 163 | 164 | /* General commands */ 165 | #define CIFX_CMD_READ_DATA 1 166 | #define CIFX_CMD_WRITE_DATA 2 167 | 168 | /* HOST mode definition */ 169 | #define CIFX_HOST_STATE_NOT_READY 0 170 | #define CIFX_HOST_STATE_READY 1 171 | #define CIFX_HOST_STATE_READ 2 172 | 173 | /* WATCHDOG commands*/ 174 | #define CIFX_WATCHDOG_STOP 0 175 | #define CIFX_WATCHDOG_START 1 176 | 177 | /* Configuration Lock commands*/ 178 | #define CIFX_CONFIGURATION_UNLOCK 0 179 | #define CIFX_CONFIGURATION_LOCK 1 180 | #define CIFX_CONFIGURATION_GETLOCKSTATE 2 181 | 182 | /* BUS state commands*/ 183 | #define CIFX_BUS_STATE_OFF 0 184 | #define CIFX_BUS_STATE_ON 1 185 | #define CIFX_BUS_STATE_GETSTATE 2 186 | 187 | /* DMA state commands*/ 188 | #define CIFX_DMA_STATE_OFF 0 189 | #define CIFX_DMA_STATE_ON 1 190 | #define CIFX_DMA_STATE_GETSTATE 2 191 | 192 | /* Memory pointer commands*/ 193 | #define CIFX_MEM_PTR_OPEN 1 194 | #define CIFX_MEM_PTR_OPEN_USR 2 195 | #define CIFX_MEM_PTR_CLOSE 3 196 | 197 | /* I/O area definition */ 198 | #define CIFX_IO_INPUT_AREA 1 199 | #define CIFX_IO_OUTPUT_AREA 2 200 | 201 | /* Reset definitions */ 202 | #define CIFX_SYSTEMSTART 1 203 | #define CIFX_CHANNELINIT 2 204 | #define CIFX_BOOTSTART 3 205 | 206 | /* Sync command definitions */ 207 | #define CIFX_SYNC_SIGNAL_CMD 1 208 | #define CIFX_SYNC_ACKNOWLEDGE_CMD 2 209 | #define CIFX_SYNC_WAIT_CMD 3 210 | 211 | typedef struct CIFX_NOTIFY_RX_MBX_FULL_DATA_Ttag 212 | { 213 | uint32_t ulRecvCount; 214 | } CIFX_NOTIFY_RX_MBX_FULL_DATA_T; 215 | 216 | typedef struct CIFX_NOTIFY_TX_MBX_EMPTY_DATA_Ttag 217 | { 218 | uint32_t ulMaxSendCount; 219 | } CIFX_NOTIFY_TX_MBX_EMPTY_DATA_T; 220 | 221 | typedef struct CIFX_NOTIFY_COM_STATE_Ttag 222 | { 223 | uint32_t ulComState; 224 | } CIFX_NOTIFY_COM_STATE_T; 225 | 226 | /* Notifications */ 227 | #define CIFX_NOTIFY_RX_MBX_FULL 1 228 | #define CIFX_NOTIFY_TX_MBX_EMPTY 2 229 | #define CIFX_NOTIFY_PD0_IN 3 230 | #define CIFX_NOTIFY_PD1_IN 4 231 | #define CIFX_NOTIFY_PD0_OUT 5 232 | #define CIFX_NOTIFY_PD1_OUT 6 233 | #define CIFX_NOTIFY_SYNC 7 234 | #define CIFX_NOTIFY_COM_STATE 8 235 | 236 | /* Extended memory commands */ 237 | #define CIFX_GET_EXTENDED_MEMORY_INFO 1 238 | #define CIFX_GET_EXTENDED_MEMORY_POINTER 2 239 | #define CIFX_FREE_EXTENDED_MEMORY_POINTER 3 240 | 241 | /*****************************************************************************/ 242 | /*! Structure definitions */ 243 | /*****************************************************************************/ 244 | typedef __CIFx_PACKED_PRE struct DRIVER_INFORMATIONtag 245 | { 246 | char abDriverVersion[32]; /*!< Driver version */ 247 | uint32_t ulBoardCnt; /*!< Number of available Boards */ 248 | } __CIFx_PACKED_POST DRIVER_INFORMATION; 249 | 250 | #define CIFx_MAX_INFO_NAME_LENTH 16 251 | 252 | /*****************************************************************************/ 253 | /*! Directory Information structure for enumerating directories */ 254 | /*****************************************************************************/ 255 | typedef __CIFx_PACKED_PRE struct CIFX_DIRECTORYENTRYtag 256 | { 257 | CIFXHANDLE hList; /*!< Handle from Enumeration function, do not touch */ 258 | char szFilename[CIFx_MAX_INFO_NAME_LENTH]; /*!< Returned file name. */ 259 | uint8_t bFiletype; /*!< Returned file type. */ 260 | uint32_t ulFilesize; /*!< Returned file size. */ 261 | 262 | } __CIFx_PACKED_POST CIFX_DIRECTORYENTRY; 263 | 264 | /*****************************************************************************/ 265 | /*! Extended memory information structure */ 266 | /*****************************************************************************/ 267 | typedef __CIFx_PACKED_PRE struct CIFX_EXTENDED_MEMORY_INFORMATIONtag 268 | { 269 | void* pvMemoryID; /*!< Identification of the memory area */ 270 | void* pvMemoryPtr; /*!< Memory pointer */ 271 | uint32_t ulMemorySize; /*!< Memory size of the Extended memory area */ 272 | uint32_t ulMemoryType; /*!< Memory type information */ 273 | 274 | } __CIFx_PACKED_POST CIFX_EXTENDED_MEMORY_INFORMATION; 275 | 276 | /*****************************************************************************/ 277 | /*! System Channel Information structure */ 278 | /*****************************************************************************/ 279 | typedef __CIFx_PACKED_PRE struct SYSTEM_CHANNEL_SYSTEM_INFORMATIONtag 280 | { 281 | uint32_t ulSystemError; /*!< Global system error */ 282 | uint32_t ulDpmTotalSize; /*!< Total size dual-port memory in bytes */ 283 | uint32_t ulMBXSize; /*!< System mailbox data size [Byte]*/ 284 | uint32_t ulDeviceNumber; /*!< Global device number */ 285 | uint32_t ulSerialNumber; /*!< Global serial number */ 286 | uint32_t ulOpenCnt; /*!< Channel open counter */ 287 | } __CIFx_PACKED_POST SYSTEM_CHANNEL_SYSTEM_INFORMATION; 288 | 289 | /* System Channel: System Information Block */ 290 | typedef __CIFx_PACKED_PRE struct SYSTEM_CHANNEL_SYSTEM_INFO_BLOCKtag 291 | { 292 | uint8_t abCookie[4]; /*!< 0x00 "netX" cookie */ 293 | uint32_t ulDpmTotalSize; /*!< 0x04 Total Size of the whole dual-port memory in bytes */ 294 | uint32_t ulDeviceNumber; /*!< 0x08 Device number */ 295 | uint32_t ulSerialNumber; /*!< 0x0C Serial number */ 296 | uint16_t ausHwOptions[4]; /*!< 0x10 Hardware options, xC port 0..3 */ 297 | uint16_t usManufacturer; /*!< 0x18 Manufacturer Location */ 298 | uint16_t usProductionDate; /*!< 0x1A Date of production */ 299 | uint32_t ulLicenseFlags1; /*!< 0x1C License code flags 1 */ 300 | uint32_t ulLicenseFlags2; /*!< 0x20 License code flags 2 */ 301 | uint16_t usNetxLicenseID; /*!< 0x24 netX license identification */ 302 | uint16_t usNetxLicenseFlags; /*!< 0x26 netX license flags */ 303 | uint16_t usDeviceClass; /*!< 0x28 netX device class */ 304 | uint8_t bHwRevision; /*!< 0x2A Hardware revision index */ 305 | uint8_t bHwCompatibility; /*!< 0x2B Hardware compatibility index */ 306 | uint8_t bDevIdNumber; /*!< 0x2C Device identification number (rotary switch) */ 307 | uint8_t bReserved; /*!< 0x2D Reserved byte */ 308 | uint16_t usReserved; /*!< 0x2E:0x2F Reserved */ 309 | } __CIFx_PACKED_POST SYSTEM_CHANNEL_SYSTEM_INFO_BLOCK; 310 | 311 | /* System Channel: Channel Information Block */ 312 | #define CIFX_SYSTEM_CHANNEL_DEFAULT_INFO_BLOCK_SIZE 16 313 | typedef __CIFx_PACKED_PRE struct SYSTEM_CHANNEL_CHANNEL_INFO_BLOCKtag 314 | { 315 | uint8_t abInfoBlock[CIFX_MAX_NUMBER_OF_CHANNEL_DEFINITION][CIFX_SYSTEM_CHANNEL_DEFAULT_INFO_BLOCK_SIZE]; 316 | } __CIFx_PACKED_POST SYSTEM_CHANNEL_CHANNEL_INFO_BLOCK; 317 | 318 | /* System Channel: System Control Block */ 319 | typedef __CIFx_PACKED_PRE struct SYSTEM_CHANNEL_SYSTEM_CONTROL_BLOCKtag 320 | { 321 | uint32_t ulSystemCommandCOS; /*!< 0x00 System channel change of state command */ 322 | uint32_t ulReserved; /*!< 0x04 Reserved */ 323 | } __CIFx_PACKED_POST SYSTEM_CHANNEL_SYSTEM_CONTROL_BLOCK; 324 | 325 | /* System Channel: System Status Block */ 326 | typedef __CIFx_PACKED_PRE struct SYSTEM_CHANNEL_SYSTEM_STATUS_BLOCKtag 327 | { 328 | uint32_t ulSystemCOS; /*!< 0x00 System channel change of state acknowledge */ 329 | uint32_t ulSystemStatus; /*!< 0x04 Actual system state */ 330 | uint32_t ulSystemError; /*!< 0x08 Actual system error */ 331 | uint32_t ulBootError; /*!< 0x0C Bootup error code (only valid if Cookie="BOOT") */ 332 | uint32_t ulTimeSinceStart; /*!< 0x10 time since start in seconds */ 333 | uint16_t usCpuLoad; /*!< 0x14 cpu load in 0,01% units (10000 => 100%) */ 334 | uint16_t usReserved; /*!< 0x16 Reserved */ 335 | uint32_t ulHWFeatures; /*!< 0x18 Hardware features */ 336 | uint8_t abReserved[36]; /*!< 0x1C:3F Reserved */ 337 | } __CIFx_PACKED_POST SYSTEM_CHANNEL_SYSTEM_STATUS_BLOCK; 338 | 339 | /*****************************************************************************/ 340 | /*! Board Information structure */ 341 | /*****************************************************************************/ 342 | typedef __CIFx_PACKED_PRE struct BOARD_INFORMATIONtag 343 | { 344 | int32_t lBoardError; /*!< Global Board error. Set when device specific data must not be used */ 345 | char abBoardName[CIFx_MAX_INFO_NAME_LENTH]; /*!< Global board name */ 346 | char abBoardAlias[CIFx_MAX_INFO_NAME_LENTH]; /*!< Global board alias name */ 347 | uint32_t ulBoardID; /*!< Unique board ID, driver created*/ 348 | uint32_t ulSystemError; /*!< System error */ 349 | uint32_t ulPhysicalAddress; /*!< Physical memory address */ 350 | uint32_t ulIrqNumber; /*!< Hardware interrupt number */ 351 | uint8_t bIrqEnabled; /*!< Hardware interrupt enable flag */ 352 | uint32_t ulChannelCnt; /*!< Number of available channels */ 353 | uint32_t ulDpmTotalSize; /*!< Dual-Port memory size in bytes */ 354 | SYSTEM_CHANNEL_SYSTEM_INFO_BLOCK tSystemInfo; /*!< System information */ 355 | } __CIFx_PACKED_POST BOARD_INFORMATION; 356 | 357 | /*****************************************************************************/ 358 | /*! Channel Information structure */ 359 | /*****************************************************************************/ 360 | typedef __CIFx_PACKED_PRE struct CHANNEL_INFORMATIONtag 361 | { 362 | char abBoardName[CIFx_MAX_INFO_NAME_LENTH]; /*!< Global board name */ 363 | char abBoardAlias[CIFx_MAX_INFO_NAME_LENTH]; /*!< Global board alias name */ 364 | uint32_t ulDeviceNumber; /*!< Global board device number */ 365 | uint32_t ulSerialNumber; /*!< Global board serial number */ 366 | 367 | uint16_t usFWMajor; /*!< Major Version of Channel Firmware */ 368 | uint16_t usFWMinor; /*!< Minor Version of Channel Firmware */ 369 | uint16_t usFWBuild; /*!< Build number of Channel Firmware */ 370 | uint16_t usFWRevision; /*!< Revision of Channel Firmware */ 371 | uint8_t bFWNameLength; /*!< Length of FW Name */ 372 | uint8_t abFWName[63]; /*!< Firmware Name */ 373 | uint16_t usFWYear; /*!< Build Year of Firmware */ 374 | uint8_t bFWMonth; /*!< Build Month of Firmware (1..12) */ 375 | uint8_t bFWDay; /*!< Build Day of Firmware (1..31) */ 376 | 377 | uint32_t ulChannelError; /*!< Channel error */ 378 | uint32_t ulOpenCnt; /*!< Channel open counter */ 379 | uint32_t ulPutPacketCnt; /*!< Number of put packet commands */ 380 | uint32_t ulGetPacketCnt; /*!< Number of get packet commands */ 381 | uint32_t ulMailboxSize; /*!< Mailbox packet size in bytes */ 382 | uint32_t ulIOInAreaCnt; /*!< Number of IO IN areas */ 383 | uint32_t ulIOOutAreaCnt; /*!< Number of IO OUT areas */ 384 | uint32_t ulHskSize; /*!< Size of the handshake cells */ 385 | uint32_t ulNetxFlags; /*!< Actual netX state flags */ 386 | uint32_t ulHostFlags; /*!< Actual Host flags */ 387 | uint32_t ulHostCOSFlags; /*!< Actual Host COS flags */ 388 | uint32_t ulDeviceCOSFlags; /*!< Actual Device COS flags */ 389 | 390 | } __CIFx_PACKED_POST CHANNEL_INFORMATION; 391 | 392 | /*****************************************************************************/ 393 | /*! IO Area Information structure */ 394 | /*****************************************************************************/ 395 | typedef __CIFx_PACKED_PRE struct CHANNEL_IO_INFORMATIONtag 396 | { 397 | uint32_t ulTotalSize; /*!< Total IO area size in byte */ 398 | uint32_t ulReserved; /*!< reserved for further use */ 399 | uint32_t ulIOMode; /*!< Exchange mode */ 400 | } __CIFx_PACKED_POST CHANNEL_IO_INFORMATION; 401 | 402 | /*****************************************************************************/ 403 | /*! Memory Information structure */ 404 | /*****************************************************************************/ 405 | typedef __CIFx_PACKED_PRE struct MEMORY_INFORMATIONtag 406 | { 407 | void* pvMemoryID; /*!< Identification of the memory area */ 408 | void** ppvMemoryPtr; /*!< Memory pointer */ 409 | uint32_t* pulMemorySize; /*!< Complete size of the mapped memory */ 410 | uint32_t ulChannel; /*!< Requested channel number */ 411 | uint32_t* pulChannelStartOffset;/*!< Start offset of the requested channel */ 412 | uint32_t* pulChannelSize; /*!< Memory size of the requested channel */ 413 | } __CIFx_PACKED_POST MEMORY_INFORMATION; 414 | 415 | /*****************************************************************************/ 416 | /*! PLC Memory Information structure */ 417 | /*****************************************************************************/ 418 | typedef __CIFx_PACKED_PRE struct PLC_MEMORY_INFORMATIONtag 419 | { 420 | void* pvMemoryID; /*!< Identification of the memory area */ 421 | void** ppvMemoryPtr; /*!< Memory pointer */ 422 | uint32_t ulAreaDefinition; /*!< Input/output area */ 423 | uint32_t ulAreaNumber; /*!< Area number */ 424 | uint32_t* pulIOAreaStartOffset; /*!< Start offset */ 425 | uint32_t* pulIOAreaSize; /*!< Memory size */ 426 | } __CIFx_PACKED_POST PLC_MEMORY_INFORMATION; 427 | 428 | 429 | /***************************************************************************/ 430 | /* Driver dependent information */ 431 | 432 | #define CIFX_MAX_PACKET_SIZE 1596 /*!< Maximum size of the RCX packet in bytes */ 433 | #define CIFX_PACKET_HEADER_SIZE 40 /*!< Maximum size of the RCX packet header in bytes */ 434 | #define CIFX_MAX_DATA_SIZE (CIFX_MAX_PACKET_SIZE - CIFX_PACKET_HEADER_SIZE) /*!< Maximum RCX packet data size */ 435 | 436 | #define CIFX_MSK_PACKET_ANSWER 0x00000001 /*!< Packet answer bit */ 437 | 438 | /*****************************************************************************/ 439 | /*! Packet header */ 440 | /*****************************************************************************/ 441 | typedef __CIFx_PACKED_PRE struct CIFX_PACKET_HEADERtag 442 | { 443 | uint32_t ulDest; /*!< destination of packet, process queue */ 444 | uint32_t ulSrc; /*!< source of packet, process queue */ 445 | uint32_t ulDestId; /*!< destination reference of packet */ 446 | uint32_t ulSrcId; /*!< source reference of packet */ 447 | uint32_t ulLen; /*!< length of packet data without header */ 448 | uint32_t ulId; /*!< identification handle of sender */ 449 | uint32_t ulState; /*!< status code of operation */ 450 | uint32_t ulCmd; /*!< packet command defined in TLR_Commands.h */ 451 | uint32_t ulExt; /*!< extension */ 452 | uint32_t ulRout; /*!< router */ 453 | } __CIFx_PACKED_POST CIFX_PACKET_HEADER; 454 | 455 | /*****************************************************************************/ 456 | /*! Definition of the rcX Packet */ 457 | /*****************************************************************************/ 458 | typedef __CIFx_PACKED_PRE struct CIFX_PACKETtag 459 | { 460 | CIFX_PACKET_HEADER tHeader; /**! */ 461 | uint8_t abData[CIFX_MAX_DATA_SIZE]; 462 | } __CIFx_PACKED_POST CIFX_PACKET; 463 | 464 | #define CIFX_CALLBACK_ACTIVE 0 465 | #define CIFX_CALLBACK_FINISHED 1 466 | typedef void(APIENTRY *PFN_PROGRESS_CALLBACK)(uint32_t ulStep, uint32_t ulMaxStep, void* pvUser, int8_t bFinished, int32_t lError); 467 | typedef void(APIENTRY *PFN_RECV_PKT_CALLBACK)(CIFX_PACKET* ptRecvPkt, void* pvUser); 468 | typedef void(APIENTRY *PFN_NOTIFY_CALLBACK) (uint32_t ulNotification, uint32_t ulDataLen, void* pvData, void* pvUser); 469 | 470 | #define DOWNLOAD_MODE_FIRMWARE 1 471 | #define DOWNLOAD_MODE_CONFIG 2 472 | #define DOWNLOAD_MODE_FILE 3 473 | #define DOWNLOAD_MODE_BOOTLOADER 4 /*!< Download bootloader update to target. */ 474 | #define DOWNLOAD_MODE_LICENSECODE 5 /*!< License update code. */ 475 | #define DOWNLOAD_MODE_MODULE 6 476 | 477 | 478 | /*************************************************************************** 479 | * API Functions 480 | ***************************************************************************/ 481 | 482 | /* Global driver functions */ 483 | int32_t APIENTRY xDriverOpen ( CIFXHANDLE* phDriver); 484 | int32_t APIENTRY xDriverClose ( CIFXHANDLE hDriver); 485 | int32_t APIENTRY xDriverGetInformation ( CIFXHANDLE hDriver, uint32_t ulSize, void* pvDriverInfo); 486 | int32_t APIENTRY xDriverGetErrorDescription ( int32_t lError, char* szBuffer, uint32_t ulBufferLen); 487 | int32_t APIENTRY xDriverEnumBoards ( CIFXHANDLE hDriver, uint32_t ulBoard, uint32_t ulSize, void* pvBoardInfo); 488 | int32_t APIENTRY xDriverEnumChannels ( CIFXHANDLE hDriver, uint32_t ulBoard, uint32_t ulChannel, uint32_t ulSize, void* pvChannelInfo); 489 | int32_t APIENTRY xDriverMemoryPointer ( CIFXHANDLE hDriver, uint32_t ulBoard, uint32_t ulCmd,void* pvMemoryInfo); 490 | int32_t APIENTRY xDriverRestartDevice ( CIFXHANDLE hDriver, char* szBoardName, void* pvData); 491 | 492 | /* System device depending functions */ 493 | int32_t APIENTRY xSysdeviceOpen ( CIFXHANDLE hDriver, char* szBoard, CIFXHANDLE* phSysdevice); 494 | int32_t APIENTRY xSysdeviceClose ( CIFXHANDLE hSysdevice); 495 | int32_t APIENTRY xSysdeviceGetMBXState ( CIFXHANDLE hSysdevice, uint32_t* pulRecvPktCount, uint32_t* pulSendPktCount); 496 | int32_t APIENTRY xSysdevicePutPacket ( CIFXHANDLE hSysdevice, CIFX_PACKET* ptSendPkt, uint32_t ulTimeout); 497 | int32_t APIENTRY xSysdeviceGetPacket ( CIFXHANDLE hSysdevice, uint32_t ulSize, CIFX_PACKET* ptRecvPkt, uint32_t ulTimeout); 498 | int32_t APIENTRY xSysdeviceInfo ( CIFXHANDLE hSysdevice, uint32_t ulCmd, uint32_t ulSize, void* pvInfo); 499 | 500 | int32_t APIENTRY xSysdeviceFindFirstFile ( CIFXHANDLE hSysdevice, uint32_t ulChannel, CIFX_DIRECTORYENTRY* ptDirectoryInfo, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 501 | int32_t APIENTRY xSysdeviceFindNextFile ( CIFXHANDLE hSysdevice, uint32_t ulChannel, CIFX_DIRECTORYENTRY* ptDirectoryInfo, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 502 | int32_t APIENTRY xSysdeviceDownload ( CIFXHANDLE hSysdevice, uint32_t ulChannel, uint32_t ulMode, char* pszFileName, uint8_t* pabFileData, uint32_t ulFileSize, 503 | PFN_PROGRESS_CALLBACK pfnCallback, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 504 | int32_t APIENTRY xSysdeviceUpload ( CIFXHANDLE hSysdevice, uint32_t ulChannel, uint32_t ulMode, char* pszFileName, uint8_t* pabFileData, uint32_t* pulFileSize, 505 | PFN_PROGRESS_CALLBACK pfnCallback, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 506 | 507 | int32_t APIENTRY xSysdeviceReset ( CIFXHANDLE hSysdevice, uint32_t ulTimeout); 508 | int32_t APIENTRY xSysdeviceBootstart ( CIFXHANDLE hSysdevice, uint32_t ulTimeout); 509 | 510 | int32_t APIENTRY xSysdeviceExtendedMemory ( CIFXHANDLE hSysdevice, uint32_t ulCmd, CIFX_EXTENDED_MEMORY_INFORMATION* ptExtMemData); 511 | 512 | /* Channel depending functions */ 513 | int32_t APIENTRY xChannelOpen ( CIFXHANDLE hDriver, char* szBoard, uint32_t ulChannel, CIFXHANDLE* phChannel); 514 | int32_t APIENTRY xChannelClose ( CIFXHANDLE hChannel); 515 | int32_t APIENTRY xChannelFindFirstFile ( CIFXHANDLE hChannel, CIFX_DIRECTORYENTRY* ptDirectoryInfo, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 516 | int32_t APIENTRY xChannelFindNextFile ( CIFXHANDLE hChannel, CIFX_DIRECTORYENTRY* ptDirectoryInfo, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 517 | 518 | int32_t APIENTRY xChannelDownload ( CIFXHANDLE hChannel, uint32_t ulMode, char* pszFileName, uint8_t* pabFileData, uint32_t ulFileSize, 519 | PFN_PROGRESS_CALLBACK pfnCallback, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 520 | int32_t APIENTRY xChannelUpload ( CIFXHANDLE hChannel, uint32_t ulMode, char* pszFileName, uint8_t* pabFileData, uint32_t* pulFileSize, 521 | PFN_PROGRESS_CALLBACK pfnCallback, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 522 | 523 | int32_t APIENTRY xChannelGetMBXState ( CIFXHANDLE hChannel, uint32_t* pulRecvPktCount, uint32_t* pulSendPktCount); 524 | int32_t APIENTRY xChannelPutPacket ( CIFXHANDLE hChannel, CIFX_PACKET* ptSendPkt, uint32_t ulTimeout); 525 | int32_t APIENTRY xChannelGetPacket ( CIFXHANDLE hChannel, uint32_t ulSize, CIFX_PACKET* ptRecvPkt, uint32_t ulTimeout); 526 | int32_t APIENTRY xChannelGetSendPacket ( CIFXHANDLE hChannel, uint32_t ulSize, CIFX_PACKET* ptRecvPkt); 527 | 528 | int32_t APIENTRY xChannelConfigLock ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t* pulState, uint32_t ulTimeout); 529 | int32_t APIENTRY xChannelReset ( CIFXHANDLE hChannel, uint32_t ulResetMode, uint32_t ulTimeout); 530 | int32_t APIENTRY xChannelInfo ( CIFXHANDLE hChannel, uint32_t ulSize, void* pvChannelInfo); 531 | int32_t APIENTRY xChannelWatchdog ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t* pulTrigger); 532 | int32_t APIENTRY xChannelHostState ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t* pulState, uint32_t ulTimeout); 533 | int32_t APIENTRY xChannelBusState ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t* pulState, uint32_t ulTimeout); 534 | int32_t APIENTRY xChannelDMAState ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t* pulState); 535 | 536 | int32_t APIENTRY xChannelIOInfo ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t ulAreaNumber, uint32_t ulSize, void* pvData); 537 | int32_t APIENTRY xChannelIORead ( CIFXHANDLE hChannel, uint32_t ulAreaNumber, uint32_t ulOffset, uint32_t ulDataLen, void* pvData, uint32_t ulTimeout); 538 | int32_t APIENTRY xChannelIOWrite ( CIFXHANDLE hChannel, uint32_t ulAreaNumber, uint32_t ulOffset, uint32_t ulDataLen, void* pvData, uint32_t ulTimeout); 539 | int32_t APIENTRY xChannelIOReadSendData ( CIFXHANDLE hChannel, uint32_t ulAreaNumber, uint32_t ulOffset, uint32_t ulDataLen, void* pvData); 540 | 541 | int32_t APIENTRY xChannelControlBlock ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t ulOffset, uint32_t ulDataLen, void* pvData); 542 | int32_t APIENTRY xChannelCommonStatusBlock ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t ulOffset, uint32_t ulDataLen, void* pvData); 543 | int32_t APIENTRY xChannelExtendedStatusBlock ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t ulOffset, uint32_t ulDataLen, void* pvData); 544 | int32_t APIENTRY xChannelUserBlock ( CIFXHANDLE hChannel, uint32_t ulAreaNumber, uint32_t ulCmd, uint32_t ulOffset, uint32_t ulDataLen, void* pvData); 545 | 546 | int32_t APIENTRY xChannelPLCMemoryPtr ( CIFXHANDLE hChannel, uint32_t ulCmd, void* pvMemoryInfo); 547 | int32_t APIENTRY xChannelPLCIsReadReady ( CIFXHANDLE hChannel, uint32_t ulAreaNumber, uint32_t* pulReadState); 548 | int32_t APIENTRY xChannelPLCIsWriteReady ( CIFXHANDLE hChannel, uint32_t ulAreaNumber, uint32_t* pulWriteState); 549 | int32_t APIENTRY xChannelPLCActivateWrite ( CIFXHANDLE hChannel, uint32_t ulAreaNumber); 550 | int32_t APIENTRY xChannelPLCActivateRead ( CIFXHANDLE hChannel, uint32_t ulAreaNumber); 551 | 552 | int32_t APIENTRY xChannelRegisterNotification ( CIFXHANDLE hChannel, uint32_t ulNotification, PFN_NOTIFY_CALLBACK pfnCallback, void* pvUser); 553 | int32_t APIENTRY xChannelUnregisterNotification( CIFXHANDLE hChannel, uint32_t ulNotification); 554 | int32_t APIENTRY xChannelSyncState ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t ulTimeout, uint32_t* pulErrorCount); 555 | /***************************************************************************/ 556 | 557 | /*************************************************************************** 558 | * API Functionpointer definitions 559 | ***************************************************************************/ 560 | 561 | /* Global driver functions */ 562 | typedef int32_t (APIENTRY *PFN_XDRIVEROPEN) ( CIFXHANDLE* phDriver); 563 | typedef int32_t (APIENTRY *PFN_XDRIVERCLOSE) ( CIFXHANDLE hDriver); 564 | typedef int32_t (APIENTRY *PFN_XDRIVERGETINFORMATION) ( CIFXHANDLE hDriver, uint32_t ulSize, void* pvDriverInfo); 565 | typedef int32_t (APIENTRY *PFN_XDRIVERGETERRORDESCRIPTION) ( int32_t lError, char* szBuffer, uint32_t ulBufferLen); 566 | typedef int32_t (APIENTRY *PFN_XDRIVERENUMBOARDS) ( CIFXHANDLE hDriver, uint32_t ulBoard, uint32_t ulSize, void* pvBoardInfo); 567 | typedef int32_t (APIENTRY *PFN_XDRIVERENUMCHANNELS) ( CIFXHANDLE hDriver, uint32_t ulBoard, uint32_t ulChannel, uint32_t ulSize, void* pvChannelInfo); 568 | typedef int32_t (APIENTRY *PFN_XDRIVERMEMORYPOINTER) ( CIFXHANDLE hDriver, uint32_t ulBoard, uint32_t ulCmd, void* pvMemoryInfo); 569 | typedef int32_t (APIENTRY *PFN_XDRIVERRESTARTDEVICE) ( CIFXHANDLE hDriver, char* szBoardName, void* pvData); 570 | 571 | /* System device depending functions */ 572 | typedef int32_t (APIENTRY *PFN_XSYSDEVICEOPEN) ( CIFXHANDLE hDriver, char* szBoard, CIFXHANDLE* phSysdevice); 573 | typedef int32_t (APIENTRY *PFN_XSYSDEVICECLOSE) ( CIFXHANDLE hSysdevice); 574 | typedef int32_t (APIENTRY *PFN_XSYSDEVICEGETMBXSTATE) ( CIFXHANDLE hSysdevice, uint32_t* pulRecvPktCount, uint32_t* pulSendPktCount); 575 | typedef int32_t (APIENTRY *PFN_XSYSDEVICEPUTPACKET) ( CIFXHANDLE hSysdevice, CIFX_PACKET* ptSendPkt, uint32_t ulTimeout); 576 | typedef int32_t (APIENTRY *PFN_XSYSDEVICEGETPACKET) ( CIFXHANDLE hSysdevice, uint32_t ulSize, CIFX_PACKET* ptRecvPkt, uint32_t ulTimeout); 577 | typedef int32_t (APIENTRY *PFN_XSYSDEVICEINFO) ( CIFXHANDLE hSysdevice, uint32_t ulCmd, uint32_t ulSize, void* pvInfo); 578 | 579 | typedef int32_t (APIENTRY *PFN_XSYSDEVICEFINDFIRSTFILE) ( CIFXHANDLE hSysdevice, uint32_t ulChannel, CIFX_DIRECTORYENTRY* ptDirectoryInfo, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 580 | typedef int32_t (APIENTRY *PFN_XSYSDEVICEFINDNEXTFILE) ( CIFXHANDLE hSysdevice, uint32_t ulChannel, CIFX_DIRECTORYENTRY* ptDirectoryInfo, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 581 | typedef int32_t (APIENTRY *PFN_XSYSDEVICEDOWNLOAD) ( CIFXHANDLE hSysdevice, uint32_t ulChannel, uint32_t ulMode, char* pszFileName, uint8_t* pabFileData, uint32_t ulFileSize, 582 | PFN_PROGRESS_CALLBACK pfnCallback, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 583 | typedef int32_t (APIENTRY *PFN_XSYSDEVICEUPLOAD) ( CIFXHANDLE hSysdevice, uint32_t ulChannel, uint32_t ulMode, char* pszFileName, uint8_t* pabFileData, uint32_t* pulFileSize, 584 | PFN_PROGRESS_CALLBACK pfnCallback, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 585 | 586 | typedef int32_t (APIENTRY *PFN_XSYSDEVICERESET) ( CIFXHANDLE hSysdevice, uint32_t ulTimeout); 587 | typedef int32_t (APIENTRY *PFN_XSYSDEVICEBOOTSTART) ( CIFXHANDLE hSysdevice, uint32_t ulTimeout); 588 | 589 | typedef int32_t (APIENTRY *PFN_XSYSDEVICEEXTENDEDMEMORY) ( CIFXHANDLE hSysdevice, uint32_t ulCmd, CIFX_EXTENDED_MEMORY_INFORMATION* ptExtMemData); 590 | 591 | /* Channel depending functions */ 592 | typedef int32_t (APIENTRY *PFN_XCHANNELOPEN) ( CIFXHANDLE hDriver, char* szBoard, uint32_t ulChannel, CIFXHANDLE* phChannel); 593 | typedef int32_t (APIENTRY *PFN_XCHANNELCLOSE) ( CIFXHANDLE hChannel); 594 | typedef int32_t (APIENTRY *PFN_XCHANNELFINDFIRSTFILE) ( CIFXHANDLE hChannel, CIFX_DIRECTORYENTRY* ptDirectoryInfo, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 595 | typedef int32_t (APIENTRY *PFN_XCHANNELFINDNEXTFILE) ( CIFXHANDLE hChannel, CIFX_DIRECTORYENTRY* ptDirectoryInfo, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 596 | 597 | typedef int32_t (APIENTRY *PFN_XCHANNELDOWNLOAD) ( CIFXHANDLE hChannel, uint32_t ulMode, char* pszFileName, uint8_t* pabFileData, uint32_t ulFileSize, 598 | PFN_PROGRESS_CALLBACK pfnCallback, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 599 | typedef int32_t (APIENTRY *PFN_XCHANNELUPLOAD) ( CIFXHANDLE hChannel, uint32_t ulMode, char* pszFileName, uint8_t* pabFileData, uint32_t* pulFileSize, 600 | PFN_PROGRESS_CALLBACK pfnCallback, PFN_RECV_PKT_CALLBACK pfnRecvPktCallback, void* pvUser); 601 | 602 | typedef int32_t (APIENTRY *PFN_XCHANNELGETMBXSTATE) ( CIFXHANDLE hChannel, uint32_t* pulRecvPktCount, uint32_t* pulSendPktCount); 603 | typedef int32_t (APIENTRY *PFN_XCHANNELPUTPACKET) ( CIFXHANDLE hChannel, CIFX_PACKET* ptSendPkt, uint32_t ulTimeout); 604 | typedef int32_t (APIENTRY *PFN_XCHANNELGETPACKET) ( CIFXHANDLE hChannel, uint32_t ulSize, CIFX_PACKET* ptRecvPkt, uint32_t ulTimeout); 605 | typedef int32_t (APIENTRY *PFN_XCHANNELGETSENDPACKET) ( CIFXHANDLE hChannel, uint32_t ulSize, CIFX_PACKET* ptRecvPkt); 606 | 607 | typedef int32_t (APIENTRY *PFN_XCHANNELCONFIGLOCK) ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t* pulState, uint32_t ulTimeout); 608 | typedef int32_t (APIENTRY *PFN_XCHANNELRESET) ( CIFXHANDLE hChannel, uint32_t ulResetMode, uint32_t ulTimeout); 609 | typedef int32_t (APIENTRY *PFN_XCHANNELINFO) ( CIFXHANDLE hChannel, uint32_t ulSize, void* pvChannelInfo); 610 | typedef int32_t (APIENTRY *PFN_XCHANNELWATCHDOG) ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t* pulTrigger); 611 | typedef int32_t (APIENTRY *PFN_XCHANNELHOSTSTATE) ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t* pulState, uint32_t ulTimeout); 612 | typedef int32_t (APIENTRY *PFN_XCHANNELBUSSTATE) ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t* pulState, uint32_t ulTimeout); 613 | typedef int32_t (APIENTRY *PFN_XCHANNELDMASTATE) ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t* pulState); 614 | 615 | typedef int32_t (APIENTRY *PFN_XCHANNELIOINFO) ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t ulAreaNumber, uint32_t ulSize, void* pvData); 616 | typedef int32_t (APIENTRY *PFN_XCHANNELIOREAD) ( CIFXHANDLE hChannel, uint32_t ulAreaNumber, uint32_t ulOffset, uint32_t ulDataLen, void* pvData, uint32_t ulTimeout); 617 | typedef int32_t (APIENTRY *PFN_XCHANNELIOWRITE) ( CIFXHANDLE hChannel, uint32_t ulAreaNumber, uint32_t ulOffset, uint32_t ulDataLen, void* pvData, uint32_t ulTimeout); 618 | typedef int32_t (APIENTRY *PFN_XCHANNELIOREADSENDDATA) ( CIFXHANDLE hChannel, uint32_t ulAreaNumber, uint32_t ulOffset, uint32_t ulDataLen, void* pvData); 619 | 620 | typedef int32_t (APIENTRY *PFN_XCHANNELCONTROLBLOCK) ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t ulOffset, uint32_t ulDataLen, void* pvData); 621 | typedef int32_t (APIENTRY *PFN_XCHANNELCOMMONSTATUSBLOCK) ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t ulOffset, uint32_t ulDataLen, void* pvData); 622 | typedef int32_t (APIENTRY *PFN_XCHANNELEXTENDEDSTATUSBLOCK)( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t ulOffset, uint32_t ulDataLen, void* pvData); 623 | typedef int32_t (APIENTRY *PFN_XCHANNELUSERBLOCK) ( CIFXHANDLE hChannel, uint32_t ulAreaNumber, uint32_t ulCmd, uint32_t ulOffset, uint32_t ulDataLen, void* pvData); 624 | 625 | typedef int32_t (APIENTRY *PFN_XCHANNELPLCMEMORYPTR) ( CIFXHANDLE hChannel, uint32_t ulCmd, void* pvMemoryInfo); 626 | typedef int32_t (APIENTRY *PFN_XCHANNELPLCISREADREADY) ( CIFXHANDLE hChannel, uint32_t ulAreaNumber, uint32_t* pulReadState); 627 | typedef int32_t (APIENTRY *PFN_XCHANNELPLCISWRITEREADY) ( CIFXHANDLE hChannel, uint32_t ulAreaNumber, uint32_t* pulWriteState); 628 | typedef int32_t (APIENTRY *PFN_XCHANNELPLCACTIVATEWRITE) ( CIFXHANDLE hChannel, uint32_t ulAreaNumber); 629 | typedef int32_t (APIENTRY *PFN_XCHANNELPLCACTIVATEREAD) ( CIFXHANDLE hChannel, uint32_t ulAreaNumber); 630 | 631 | typedef int32_t (APIENTRY *PFN_XCHANNELREGISTERNOTIFICATION) ( CIFXHANDLE hChannel, uint32_t ulNotification, PFN_NOTIFY_CALLBACK pfnCallback, void* pvUser); 632 | typedef int32_t (APIENTRY *PFN_XCHANNELUNREGISTERNOTIFICATION)( CIFXHANDLE hChannel, uint32_t ulNotification); 633 | typedef int32_t (APIENTRY *PFN_XCHANNELSYNCSTATE) ( CIFXHANDLE hChannel, uint32_t ulCmd, uint32_t ulTimeout, uint32_t* pulErrorCount); 634 | /***************************************************************************/ 635 | 636 | #ifdef __cplusplus 637 | } 638 | #endif 639 | 640 | #if defined(_MSC_VER) 641 | #if _MSC_VER >= 1000 642 | #pragma pack() /* Always align structures to default boundery */ 643 | #endif /* _MSC_VER >= 1000 */ 644 | #endif /* _MSC_VER */ 645 | 646 | #undef __CIFx_PACKED_PRE 647 | #undef __CIFx_PACKED_POST 648 | 649 | /*****************************************************************************/ 650 | /*! \} */ 651 | /*****************************************************************************/ 652 | 653 | #endif /* __CIFxUSER_H */ 654 | -------------------------------------------------------------------------------- /driver/includes/cifxlinux.h: -------------------------------------------------------------------------------- 1 | /************************************************************************************** 2 | 3 | Copyright (c) Hilscher GmbH. All Rights Reserved. 4 | 5 | ************************************************************************************** 6 | 7 | Filename: 8 | $Workfile: cifxlinux.h $ 9 | Last Modification: 10 | $Author: sebastiand $ 11 | $Modtime: 30.09.09 12:12 $ 12 | $Revision: 7797 $ 13 | 14 | Targets: 15 | Linux : yes 16 | 17 | Description: 18 | Linux specific driver / toolkit initialization 19 | 20 | Changes: 21 | 22 | Version Date Author Description 23 | ---------------------------------------------------------------------------------- 24 | 12 03.07.2014 SD Added: 25 | - CIFX_DEVICE_T 26 | added parameter for the toolkit's hw-function interface 27 | 11 16.01.2013 SD Added: 28 | - CIFX_DEVICE_T 29 | add DMA information 30 | 10 16.01.2012 SD Added: 31 | - Definition for netJACK PCI card 32 | Changed: 33 | - structure CIFX_DEVICE_T 34 | - add parameter for the extended memory 35 | - structure CIFX_LINUX_INIT 36 | - add iCardNumber (support to specify single card) 37 | - add poll_StackSize (if != 0 stack size of polling thread) 38 | 9 15.06.2010 SD Added: 39 | - DPM mapping for ISA devices 40 | 8 27.05.2010 SD Added: 41 | - Driver-version (LINUXCIFXDRV_VERSION) 42 | 7 26.05.2010 SD Added 43 | - ifdef cplusplus 44 | 6 21.04.2010 MT Added netPLC support 45 | 5 30.09.2009 MT Changed: 46 | - Allow external usage of uio access functions 47 | 4 16.02.2009 MT Added poll_priority to init parameters 48 | Changed: 49 | - Passing CIFX_POLLINTERVAL_DISABLETHREAD as 50 | poll_timeout will disable polling thread completely 51 | 3 29.01.2009 MT Added force_ram flag to allow forcing HW Reset 52 | and re-download of all files on DPM devices 53 | Added notify event for cards that need to 54 | change DPM timings after second stage loader 55 | download (or before HW reset) 56 | 2 28.11.2008 MT Structures updated 57 | 1 12.11.2008 Linutronix Initial version 58 | 59 | **************************************************************************************/ 60 | 61 | #ifndef __CIFX_LINUX__H 62 | #define __CIFX_LINUX__H 63 | 64 | #ifdef __cplusplus 65 | extern "C" 66 | { 67 | #endif 68 | 69 | 70 | #define LIBRARYNAME "LinuxCIFXDrv " 71 | #define LINUXCIFXDRV_VERSION LIBRARYNAME VERSION_INFO 72 | 73 | #define APIENTRY 74 | #ifdef CIFX_TOOLKIT_HWIF 75 | #include "cifXHWFunctions.h" 76 | #endif 77 | #include "cifXUser.h" 78 | #include "cifXErrors.h" 79 | 80 | #define CIFX_DRIVER_INIT_NOSCAN 0 /*!< Don't automatically scan and add found devices */ 81 | #define CIFX_DRIVER_INIT_AUTOSCAN 1 /*!< Scan automatically for devices and add them to toolkit control */ 82 | #define CIFX_DRIVER_INIT_CARDNUMBER 2 /*!< Initialize specific card */ 83 | 84 | #define CIFX_POLLINTERVAL_DISABLETHREAD (~0) /*!< Disable polling completely */ 85 | #define DMA_BUFFER_COUNT 8 86 | 87 | /*****************************************************************************/ 88 | /*! Driver initialization structure */ 89 | /*****************************************************************************/ 90 | struct CIFX_LINUX_INIT 91 | { 92 | int init_options; /*!< see CIFX_DRIVER_INIT_XXX defines */ 93 | 94 | const char* base_dir; /*!< base directory for device configuration */ 95 | unsigned long poll_interval; /*!< Poll interval in ms for non-irq cards */ 96 | int poll_priority; /*!< Poll thread priority */ 97 | unsigned long trace_level; /*!< see TRACE_LVL_XXX defines */ 98 | int user_card_cnt; /*!< Number of user defined cards */ 99 | struct CIFX_DEVICE_T* user_cards; /*!< Pointer to Array of user cards (must be user_card_cnt long) */ 100 | 101 | int iCardNumber; 102 | int fEnableCardLocking; 103 | int poll_StackSize; /*!< Stack size of polling thread */ 104 | int poll_schedpolicy; /*!< Schedule policy of poll thread */ 105 | }; 106 | 107 | int32_t cifXDriverInit(const struct CIFX_LINUX_INIT* init_params); 108 | void cifXDriverDeinit(); 109 | int32_t cifXGetDriverVersion(uint32_t ulSize, char* szVersion); 110 | 111 | typedef int32_t (*PFN_DRV_HWIF_INIT) ( struct CIFX_DEVICE_T* ptDevice); 112 | typedef void (*PFN_DRV_HWIF_EXIT) ( struct CIFX_DEVICE_T* ptDevice); 113 | typedef void* (*PFN_DRV_HWIF_MEMCPY) ( struct CIFX_DEVICE_T* ptDevice, void* pvAddr, void* pvData, uint32_t ulLen); 114 | 115 | /*****************************************************************************/ 116 | /*! Notification events */ 117 | /*****************************************************************************/ 118 | typedef enum CIFX_NOTIFY_Etag 119 | { 120 | eCIFX_EVENT_PRERESET = 0, /*!< Event signalled, before device is reset (HW Reset) */ 121 | eCIFX_EVENT_POSTRESET, /*!< Called after HW reset has been executed */ 122 | eCIFX_EVENT_PRE_BOOTLOADER, /*!< Called before bootloader is downloaded */ 123 | eCIFX_EVENT_POST_BOOTLOADER, /*!< Called after bootloader was downloaded and started */ 124 | 125 | } CIFX_NOTIFY_E; 126 | 127 | typedef void(*PFN_CIFX_NOTIFY_EVENT)(struct CIFX_DEVICE_T* ptDevice, CIFX_NOTIFY_E eEvent); 128 | 129 | /*****************************************************************************/ 130 | /*! Memory types */ 131 | /*****************************************************************************/ 132 | typedef enum CIFX_MEM_TYPE_Etag 133 | { 134 | eMEM_DPM, 135 | eMEM_EXTMEM, 136 | eMEM_DMA 137 | } CIFX_MEM_TYPE_E; 138 | 139 | /*****************************************************************************/ 140 | /*! DMA memory information */ 141 | /*****************************************************************************/ 142 | typedef struct DMABUFFER_Ttag 143 | { 144 | uint32_t ulSize; /*!< DMA buffer size */ 145 | uint32_t ulPhysicalAddress; /*!< Physical address of the buffer */ 146 | void* pvBuffer; /*!< Pointer to the buffer */ 147 | } DMABUFFER_T; 148 | 149 | /*****************************************************************************/ 150 | /*! Device structure for manually adding devices */ 151 | /*****************************************************************************/ 152 | struct CIFX_DEVICE_T 153 | { 154 | unsigned char* dpm; /*!< virtual pointer to DPM */ 155 | unsigned long dpmaddr; /*!< physical address to DPM, this parameter will be used for PCI cards to detect bus address */ 156 | unsigned long dpmlen; /*!< Length of DPM in bytes */ 157 | 158 | int uio_num; /*!< uio number, -1 for non-uio devices */ 159 | int uio_fd; /*!< uio file handle, -1 for non-uio devices */ 160 | 161 | int pci_card; /*!< !=0 if device is a pci card */ 162 | int force_ram; /*!< Force usage of RAM instead of flash. Card will always be reset and all 163 | files are downloaded again */ 164 | 165 | PFN_CIFX_NOTIFY_EVENT notify; /*!< Function to call, after the card has passed several stages (usually needed on RAM based 166 | devices, that change DPM configuration during initialization) */ 167 | 168 | void* userparam; /*!< User specific parameter (e.g. identifier for manual added devices */ 169 | 170 | unsigned char* extmem; /*!< virtual pointer to extended memory */ 171 | unsigned long extmemaddr; /*!< physical address to extended memory */ 172 | unsigned long extmemlen; /*!< Length of extended memory in bytes */ 173 | 174 | /* DMA Buffer Structure */ 175 | uint32_t dma_buffer_cnt; /*!< Number of available DMA buffers */ 176 | DMABUFFER_T dma_buffer[DMA_BUFFER_COUNT]; /*!< DMA buffer definition for the device */ 177 | 178 | /* function interface required when using the toolkit's hardware functions */ 179 | PFN_DRV_HWIF_INIT hwif_init; /*!< Function initializes custom hw-function interface */ 180 | PFN_DRV_HWIF_EXIT hwif_deinit; /*!< Function de-initializes custom hw-function interface */ 181 | PFN_DRV_HWIF_MEMCPY hwif_read; /*!< Function provides read access to the DPM via custom hardware interface */ 182 | PFN_DRV_HWIF_MEMCPY hwif_write; /*!< Function provides write access to the DPM via custom hardware interface */ 183 | }; 184 | 185 | int cifXGetDeviceCount(void); 186 | struct CIFX_DEVICE_T* cifXFindDevice(int iNum, int fForceOpenDevice); 187 | void cifXDeleteDevice(struct CIFX_DEVICE_T* device); 188 | 189 | #define CIFX_UIO_MAP_NO_FOR_DPM 0 /*!< Offset of uio driver to mmap */ 190 | 191 | #define CIFX_UIO_PLX_CARD_NAME "netx_plx" /*!< uio name of a NXSB-PCA or NXPCA-PCI card */ 192 | #define CIFX_UIO_CARD_NAME "netx" /*!< uio name of a cifX PCI card */ 193 | #define CIFX_UIO_NETPLC_CARD_NAME "netplc" /*!< uio name of a netPLC PCI card */ 194 | #define CIFX_UIO_NETJACK_CARD_NAME "netjack" /*!< uio name of a netJACK PCI card */ 195 | #define CIFX_UIO_CUSTOM_CARD_NAME "netx_custom" /*!< name of user defined cards */ 196 | 197 | #define UIO_NETX_START_TYPE_AUTO "auto" 198 | #define UIO_NETX_START_TYPE_RAM "ram" 199 | #define UIO_NETX_START_TYPE_FLASH "flash" 200 | #define UIO_NETX_START_TYPE_DONTTOUCH "donttouch" 201 | 202 | /* UIO helper functions to allow users, to find own uio devices, without the need to reimplement the uio access functions */ 203 | int cifx_uio_open(int uio_num, int fForceOpenDevice); 204 | int cifx_ISA_open(void); 205 | void cifx_ISA_close(int isa_fd); 206 | unsigned long cifx_uio_get_mem_size(int uio_num, int bar); 207 | unsigned long cifx_uio_get_mem_addr(int uio_num, int bar); 208 | int cifx_uio_validate_name(int uio_num, const char* name); 209 | int cifx_uio_map_dpm(int uio_fd, int uio_num, void** dpmbase, unsigned long* dpmaddr, unsigned long* dpmlen); 210 | int cifx_ISA_map_dpm(int fd, void** dpmbase, int dpmaddr, int dpmlen); 211 | void cifx_ISA_unmap_dpm(void* dpmbase, int dpmlen); 212 | 213 | #define CIFX_PLUGIN_GET_DEVICE_COUNT "cifx_device_count" 214 | typedef uint32_t(*PFN_CIFX_PLUGIN_GET_DEVICE_COUNT)(void); 215 | #define CIFX_PLUGIN_ALLOC_DEVICE "cifx_alloc_device" 216 | typedef struct CIFX_DEVICE_T*(*PFN_CIFX_PLUGIN_ALLOC_DEVICE)(uint32_t num); 217 | #define CIFX_PLUGIN_FREE_DEVICE "cifx_free_device" 218 | typedef void(*PFN_CIFX_PLUGIN_FREE_DEVICE)(struct CIFX_DEVICE_T*); 219 | 220 | #ifdef __cplusplus 221 | } 222 | #endif 223 | 224 | #endif /* __CIFX_LINUX__H */ 225 | -------------------------------------------------------------------------------- /driver/includes/netx_tap.h: -------------------------------------------------------------------------------- 1 | #ifndef __NETX_TAP__H 2 | #define __NETX_TAP__H 3 | 4 | #ifdef CIFXETHERNET 5 | 6 | #include 7 | #include 8 | #include 9 | #include 10 | 11 | #include 12 | 13 | #define DEFAULT_POLL_TIMEOUT 10 /* polling interval of receiver thread in ms */ 14 | 15 | /* symbols used when requesting information of the extended status block (->cifXEthGetExentedStatusInformation()) */ 16 | #define EXT_INFO_INTF_CONFIG 1 /* request for interface configuration (returns EXT_INFO_MACADDR, EXT_INFO_IPADDR, EXT_INFO_NETMASK, EXT_INFO_GATEWAY) */ 17 | #define EXT_INFO_LINKSTATE 2 18 | #define EXT_INFO_MACADDR 3 19 | #define EXT_INFO_IPADDR 4 20 | #define EXT_INFO_NETMASK 5 21 | #define EXT_INFO_GATEWAY 6 22 | #define EXT_INFO_NO_RECVPKT 7 23 | #define EXT_INFO_NO_RCVPKT_DROP 8 24 | #define EXT_INFO_NO_SENDPKT 9 25 | #define EXT_INFO_NO_SENDPKT_DROP 10 26 | #define EXT_STATISTICS 11 27 | 28 | typedef struct NETX_ETH_DEV_CFG_Ttag 29 | { 30 | char cifx_name[16]; 31 | char eth_dev_name[IFNAMSIZ]; 32 | 33 | } NETX_ETH_DEV_CFG_T; 34 | 35 | #pragma pack(1) 36 | typedef struct IPCONFIG_Ttag /* configuration of the hardware, indicated by the ETH_INTF_RECV_IP_CONFIG_IND packet */ 37 | { 38 | uint32_t ulFlags; 39 | uint32_t ulIpAddr; 40 | uint32_t ulNetMask; 41 | uint32_t ulGateway; 42 | uint8_t abEthernetMACAddr[6]; 43 | 44 | } IPCONFIG_T, *PIPCONFIG_T; 45 | #pragma pack() 46 | 47 | typedef struct STATISTIC_Ttag /* ethernet statistic information structure (located in the extended information field) */ 48 | { 49 | uint64_t ullIfInPkts; /* the number of packets received */ 50 | uint64_t ullIfInDiscards; /* The number of received packets not passed to the host because of packet queue overflow */ 51 | uint64_t ullIfOutPkts; /* The number of sent ethernet frames */ 52 | uint64_t ullIfOutDiscards; /* The number of ethernet frames dropped because of no ethernet frame buffer available */ 53 | uint64_t ullIfInBytes; /* the number of bytes received */ 54 | uint64_t ullIfOutBytes; /* the number of bytes transmitted */ 55 | 56 | } STATISTIC_T, *PSTATISTIC_T; 57 | 58 | typedef struct LINK_STATE_Ttag 59 | { 60 | uint8_t bLinkState; 61 | } LINK_STATE_T, *PLINK_STATE_T; 62 | 63 | void* cifxeth_create_device( NETX_ETH_DEV_CFG_T* config); 64 | void cifxeth_remove_device( void* handle, NETX_ETH_DEV_CFG_T* config); 65 | void cifxeth_sys_cleanup(void); 66 | 67 | #endif //CIFXETHERNET 68 | 69 | #endif /* __NETX_TAP__H */ 70 | -------------------------------------------------------------------------------- /driver/includes/rcX_User.h: -------------------------------------------------------------------------------- 1 | /************************************************************************************** 2 | 3 | Copyright (c) Hilscher Gesellschaft fuer Systemautomation mbH. All Rights Reserved. 4 | 5 | *************************************************************************************** 6 | 7 | $Id: rcX_User.h 6827 2015-03-31 15:23:50Z Robert $: 8 | 9 | Description: 10 | Definition file for the rcX operating system 11 | 12 | Changes: 13 | Date Description 14 | ----------------------------------------------------------------------------------- 15 | 2014-09-17 Added RCX_HW_DEV_CLASS_NETIC_52 16 | 2014-07-07 Added support for IAR C/C++ Compiler (ARM Cores only) 17 | 2014-04-28 Added support for armcc compiler 18 | 2013-12-17 Added RCX_HW_DEV_CLASS_NETPLC_J500 19 | 2013-11-07 Added RCX_HW_DEV_CLASS_NETSMART_T51, RCX_HW_DEV_CLASS_NETSCADA_T52, 20 | RCX_HW_DEV_CLASS_NETSAFETY_51, RCX_HW_DEV_CLASS_NETSAFETY_52 21 | 2013-10-01 Added RCX_HW_DEV_CLASS_NETRAPID_52 22 | 2013-05-28 Added RCX_HW_DEV_CLASS_NETSCOPE_C100 23 | 2013-04-03 Added RCX_HW_DEV_CLASS_NETHOST_T100 24 | 2013-01-15 Added RCX_HW_DEV_CLASS_COMX_51, RCX_HW_DEV_CLASS_NETJACK_51 25 | 2012-08-03 Added RCX_HW_DEV_CLASS_CHIP_NETX_52, RCX_HW_DEV_CLASS_NETSCADA_T50, 26 | RCX_HW_DEV_CLASS_NETSMART_50, RCX_HW_DEV_CLASS_IOLINK_GW_51, 27 | RCX_HW_DEV_CLASS_NETHMI_B500 28 | 2012-07-23 Changed RCX_MAX_PACKET_SIZE to 1596 Bytes (Comm. Channel Mailbox Size) 29 | 2012-05-29 Added DPM structure NETX_8K_DPM_COMM_CHANNEL 30 | for hardware with only 8 KByte DPM (e.g. COMX10) 31 | 2012-02-29 Added RCX_HW_DEV_CLASS_GW_EU5C 32 | 2012-01-31 Added RCX_HW_DEV_CLASS_NETSCADA_T51, 33 | RCX_HW_DEV_CLASS_CHIP_NETX_51, RCX_HW_DEV_CLASS_NETRAPID_51 34 | 2011-12-12 Updated ulHWFeatures definitions for extended memory (MRAM) 35 | 2011-12-06 Added ulHWFeatures into SYSTEM_STATUS_BLOCK (RTC/MRAM) 36 | 2011-10-31 Added RCX_HW_DEV_CLASS_NETRAPID_10/50 37 | 2011-07-07 Added PROT_CLASS_3S_PLC_HANDLER 38 | 2010-12-10 Added RCX_HW_DEV_CLASS_NETJACK_10/50/100/500 and RCX_HW_DEV_CLASS_NETLINK_10_USB 39 | 2010-11-29 fixed Mantis 11689 (update rcx_user.h (sync stuff)) 40 | 2010-11-15 Added RCX_HW_DEV_CLASS_COMX_50 41 | Added RCX_PROT_CLASS_VARAN 42 | 2010-11-10 Added RCX_HW_DEV_CLASS_COMX_10 43 | Added RCX_HW_DEV_CLASS_NETIC_10 44 | Rename RCX_HW_DEV_CLASS_COMX to RCX_HW_DEV_CLASS_COMX_100 45 | Rename RCX_HW_DEV_CLASS_NETIC to RCX_HW_DEV_CLASS_NETIC_50 46 | 2010-09-02 Added RCX_HW_DEV_CLASS_CHIP_NETX_10 47 | 2010-08-03 Added RCX_E_INVALID_ALIGNMENT 48 | 2010-07-22 Added RCX_PROT_CLASS_DF1 49 | 2010-05-04 Added HW option validation start/end defines 50 | 2010-05-04 Added "System Status" defines 51 | 2010-03-23 File created. 52 | 53 | **************************************************************************************/ 54 | 55 | 56 | /* Prevent multiple inclusion */ 57 | #ifndef __RCX_USER_H 58 | #define __RCX_USER_H 59 | 60 | #include 61 | 62 | /*---------------------------------------------------------------------------*/ 63 | /* Compiler settings */ 64 | #ifdef _MSC_VER 65 | #if _MSC_VER >= 1000 66 | #define __RCX_PACKED_PRE 67 | #define __RCX_PACKED_POST 68 | #pragma once 69 | #pragma pack(1) /* Always align structures to byte boundery */ 70 | #ifndef STRICT /* Check Typdefinition */ 71 | #define STRICT 72 | #endif 73 | #endif /* _MSC_VER >= 1000 */ 74 | #endif /* _MSC_VER */ 75 | 76 | /* support for GNU compiler */ 77 | #ifdef __GNUC__ 78 | #define __RCX_PACKED_PRE 79 | #define __RCX_PACKED_POST __attribute__((__packed__)) 80 | #endif 81 | 82 | /* support for REALVIEW ARM and IAR compiler (ARM cores only) */ 83 | #if defined (__ADS__) || defined (__REALVIEW__) || defined (__CC_ARM) || defined (__ICCARM__) 84 | #define __RCX_PACKED_PRE __packed 85 | #define __RCX_PACKED_POST 86 | #endif 87 | 88 | /*===========================================================================*/ 89 | /* */ 90 | /* DEFAULT DPM structure */ 91 | /* */ 92 | /*===========================================================================*/ 93 | /* */ 94 | /* ------------------------- DPM Offset 0 */ 95 | /* | System Channel | */ 96 | /* ------------------------- */ 97 | /* | Handshake channel | */ 98 | /* ------------------------- */ 99 | /* | Communication channel 0 | */ 100 | /* ------------------------- */ 101 | /* | Communication channel 1 | */ 102 | /* ------------------------- */ 103 | /* | Communication channel 2 | */ 104 | /* ------------------------- */ 105 | /* | Communication channel 3 | */ 106 | /* ------------------------- */ 107 | /* | Application channel 0 | */ 108 | /* ------------------------- */ 109 | /* | Application channel 1 | */ 110 | /* ------------------------- DPM Offset xxxx */ 111 | /*===========================================================================*/ 112 | /*\/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ */ 113 | 114 | /* Global definitions */ 115 | #define NETX_MAX_SUPPORTED_CHANNELS 8 /*!< Maximum number of possible channels */ 116 | 117 | /* Global system channel definitions */ 118 | #define NETX_SYSTEM_HSK_CELL_OFFSET 0 /*!< Offset of the system handshake cells */ 119 | #define NETX_SYSTEM_BLOCK_VERSION 0 /*!< Version of the system block structure */ 120 | #define NETX_SYSTEM_CHANNEL_SIZE 512 /*!< Size of the system channel in bytes */ 121 | #define NETX_SYSTEM_MAILBOX_MIN_SIZE 124 /*!< Size of a system packet mailbox in bytes */ 122 | 123 | #define NETX_SYSTEM_CHANNEL_INDEX 0 /*!< Index of the system channel, always 0 */ 124 | #define NETX_HANDSHAKE_CHANNEL_INDEX 1 /*!< Index of the handshake channel, always 1 if available */ 125 | #define NETX_COM_CHANNEL_START_INDEX 2 /*!< Start index of communication channel 0 */ 126 | 127 | /* Global handshake channel size */ 128 | #define NETX_HANDSHAKE_CHANNEL_SIZE 256 /*!< Length of the handshake channel in bytes */ 129 | #define NETX_HANDSHAKE_PAIRS 16 /*!< Number of possible handshake pairs */ 130 | 131 | /* Global communication channel definitions */ 132 | #define NETX_STATUS_BLOCK_VERSION 2 /*!< version of the common status block structure */ 133 | #define NETX_EXT_STATE_SIZE 432 /*!< Default size of the extended state block */ 134 | 135 | #define NETX_CHANNEL_MAILBOX_SIZE 1596 /*!< Default size of a channel packet mailbox in bytes */ 136 | #define NETX_HP_IO_DATA_SIZE 64 /*!< Default size of the high prio I/O data */ 137 | #define NETX_IO_DATA_SIZE 5760 /*!< Default I/O data size in bytes */ 138 | #define NETX_IO_DATA_SIZE_8K_DPM 1536 /*!< I/O data size in bytes for hardware with 8KByte DPM */ 139 | 140 | /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 141 | /*XX XXXXXXXXXXXXXX*/ 142 | /*XX SYSTEM CHANNEL LAYOUT XXXXXXXXXXXXXX*/ 143 | /*XX XXXXXXXXXXXXXX*/ 144 | /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 145 | 146 | /*****************************************************************************/ 147 | /*! System channel information structure (Size always 16 Byte) */ 148 | /*****************************************************************************/ 149 | typedef __RCX_PACKED_PRE struct NETX_SYSTEM_CHANNEL_INFOtag 150 | { 151 | uint8_t bChannelType; /*!< 0x00 Type of this channel */ 152 | uint8_t bReserved; /*!< 0x01 reserved */ 153 | uint8_t bSizePositionOfHandshake; /*!< 0x02 Size and position of the handshake cells */ 154 | uint8_t bNumberOfBlocks; /*!< 0x03 Number of blocks in this channel */ 155 | uint32_t ulSizeOfChannel; /*!< 0x04 Size of channel in bytes */ 156 | uint16_t usSizeOfMailbox; /*!< 0x08 Size of the send and receive mailbox */ 157 | uint16_t usMailboxStartOffset; /*!< 0x0A Start offset of the mailbox structure (see NETX_MAILBOX) */ 158 | uint8_t abReserved[4]; /*!< 0x0C:0x0F Reserved area */ 159 | } __RCX_PACKED_POST NETX_SYSTEM_CHANNEL_INFO; 160 | 161 | /*****************************************************************************/ 162 | /*! Handshake channel information structure (Size always 16 Byte) */ 163 | /*****************************************************************************/ 164 | typedef __RCX_PACKED_PRE struct NETX_HANDSHAKE_CHANNEL_INFOtag 165 | { 166 | uint8_t bChannelType; /*!< 0x00 Type of this channel */ 167 | uint8_t bReserved[3]; /*!< 0x01 reserved */ 168 | uint32_t ulSizeOfChannel; /*!< 0x04 Size of channel in bytes */ 169 | uint8_t abReserved[8]; /*!< 0x08:0x0F Reserved area */ 170 | } __RCX_PACKED_POST NETX_HANDSHAKE_CHANNEL_INFO; 171 | 172 | /*****************************************************************************/ 173 | /*! Communication channel information structure (Size always 16 Byte) */ 174 | /*****************************************************************************/ 175 | typedef __RCX_PACKED_PRE struct NETX_COMMUNICATION_CHANNEL_INFOtag 176 | { 177 | uint8_t bChannelType; /*!< 0x00 Type of this channel */ 178 | uint8_t bChannelId; /*!< 0x01 Channel / Port ID */ 179 | uint8_t bSizePositionOfHandshake; /*!< 0x02 Size and position of the handshake cells */ 180 | uint8_t bNumberOfBlocks; /*!< 0x03 Number of blocks in this channel */ 181 | uint32_t ulSizeOfChannel; /*!< 0x04 Size of channel in bytes */ 182 | uint16_t usCommunicationClass; /*!< 0x08 Communication Class (Master, Slave...) */ 183 | uint16_t usProtocolClass; /*!< 0x0A Protocol Class (PROFIBUS, PROFINET....) */ 184 | uint16_t usProtocolConformanceClass; /*!< 0x0C Protocol Conformance Class (DPV1, DPV2...) */ 185 | uint8_t abReserved[2]; /*!< 0x0E:0x0F Reserved area */ 186 | } __RCX_PACKED_POST NETX_COMMUNICATION_CHANNEL_INFO; 187 | 188 | /*****************************************************************************/ 189 | /*! Application channel information structure (Size always 16 Byte) */ 190 | /*****************************************************************************/ 191 | typedef __RCX_PACKED_PRE struct NETX_APPLICATION_CHANNEL_INFOtag 192 | { 193 | uint8_t bChannelType; /*!< 0x00 Type of this channel */ 194 | uint8_t bChannelId; /*!< 0x01 Channel / Port ID */ 195 | uint8_t bSizePositionOfHandshake; /*!< 0x02 Size and position of the handshake cells */ 196 | uint8_t bNumberOfBlocks; /*!< 0x03 Number of blocks in this channel */ 197 | uint32_t ulSizeOfChannel; /*!< 0x04 Size of channel in bytes */ 198 | uint8_t abReserved[8]; /*!< 0x0C:0x0F Reserved area */ 199 | } __RCX_PACKED_POST NETX_APPLICATION_CHANNEL_INFO; 200 | 201 | /*****************************************************************************/ 202 | /*! System information block (Size = 48 Byte) */ 203 | /*****************************************************************************/ 204 | typedef __RCX_PACKED_PRE struct NETX_SYSTEM_INFO_BLOCKtag 205 | { 206 | uint8_t abCookie[4]; /*!< 0x00 "netX" cookie */ 207 | uint32_t ulDpmTotalSize; /*!< 0x04 Total Size of the whole dual-port memory in bytes */ 208 | uint32_t ulDeviceNumber; /*!< 0x08 Device number */ 209 | uint32_t ulSerialNumber; /*!< 0x0C Serial number */ 210 | uint16_t ausHwOptions[4]; /*!< 0x10 Hardware options, xC port 0..3 */ 211 | uint16_t usManufacturer; /*!< 0x18 Manufacturer Location */ 212 | uint16_t usProductionDate; /*!< 0x1A Date of production */ 213 | uint32_t ulLicenseFlags1; /*!< 0x1C License code flags 1 */ 214 | uint32_t ulLicenseFlags2; /*!< 0x20 License code flags 2 */ 215 | uint16_t usNetxLicenseID; /*!< 0x24 netX license identification */ 216 | uint16_t usNetxLicenseFlags; /*!< 0x26 netX license flags */ 217 | uint16_t usDeviceClass; /*!< 0x28 netX device class */ 218 | uint8_t bHwRevision; /*!< 0x2A Hardware revision index */ 219 | uint8_t bHwCompatibility; /*!< 0x2B Hardware compatibility index */ 220 | uint8_t bDevIdNumber; /*!< 0x2C Device identification number (rotary switch) */ 221 | uint8_t bReserved; /*!< 0x2D Reserved byte */ 222 | uint16_t usReserved; /*!< 0x2E:0x2F Reserved */ 223 | } __RCX_PACKED_POST NETX_SYSTEM_INFO_BLOCK; 224 | 225 | /*****************************************************************************/ 226 | /*! Channel information block (Size always 16 Byte) */ 227 | /*****************************************************************************/ 228 | typedef __RCX_PACKED_PRE union NETX_CHANNEL_INFO_BLOCKtag 229 | { 230 | NETX_SYSTEM_CHANNEL_INFO tSystem; 231 | NETX_HANDSHAKE_CHANNEL_INFO tHandshake; 232 | NETX_COMMUNICATION_CHANNEL_INFO tCom; 233 | NETX_APPLICATION_CHANNEL_INFO tApp; 234 | } __RCX_PACKED_POST NETX_CHANNEL_INFO_BLOCK; 235 | 236 | /*****************************************************************************/ 237 | /*! System information block (Size = 8 Byte) */ 238 | /*****************************************************************************/ 239 | typedef __RCX_PACKED_PRE struct NETX_SYSTEM_CONTROL_BLOCKtag 240 | { 241 | uint32_t ulSystemCommandCOS; /*!< 0x00 System channel change of state command */ 242 | uint32_t ulReserved; /*!< 0x04 Reserved */ 243 | } __RCX_PACKED_POST NETX_SYSTEM_CONTROL_BLOCK; 244 | 245 | /*****************************************************************************/ 246 | /*! System status block (Size = 64 Byte) */ 247 | /*****************************************************************************/ 248 | typedef __RCX_PACKED_PRE struct NETX_SYSTEM_STATUS_BLOCKtag 249 | { 250 | uint32_t ulSystemCOS; /*!< 0x00 System channel change of state acknowledge */ 251 | uint32_t ulSystemStatus; /*!< 0x04 Actual system state */ 252 | uint32_t ulSystemError; /*!< 0x08 Actual system error */ 253 | uint32_t ulBootError; /*!< 0x0C Bootup error (only set by 2nd Stage Bootloader) */ 254 | uint32_t ulTimeSinceStart; /*!< 0x10 time since start in seconds */ 255 | uint16_t usCpuLoad; /*!< 0x14 cpu load in 0,01% units (10000 => 100%) */ 256 | uint16_t usReserved; /*!< 0x16 Reserved */ 257 | uint32_t ulHWFeatures; /*!< 0x18 Hardware features */ 258 | uint8_t abReserved[36]; /*!< 0x1C:3F Reserved */ 259 | } __RCX_PACKED_POST NETX_SYSTEM_STATUS_BLOCK; 260 | 261 | /*****************************************************************************/ 262 | /*! System send packet mailbox (Size 128 Byte) */ 263 | /*****************************************************************************/ 264 | typedef __RCX_PACKED_PRE struct NETX_SYSTEM_SEND_MAILBOXtag 265 | { 266 | uint16_t usPackagesAccepted; /*!< Number of packages that can be accepted */ 267 | uint16_t usReserved; /*!< Reserved */ 268 | uint8_t abSendMbx[NETX_SYSTEM_MAILBOX_MIN_SIZE]; /*!< Send mailbox packet buffer */ 269 | } __RCX_PACKED_POST NETX_SYSTEM_SEND_MAILBOX; 270 | 271 | /*****************************************************************************/ 272 | /*! System receive packet mailbox (Size 128 Byte) */ 273 | /*****************************************************************************/ 274 | typedef __RCX_PACKED_PRE struct NETX_SYSTEM_RECV_MAILBOXtag 275 | { 276 | uint16_t usWaitingPackages; /*!< Number of packages waiting to be processed */ 277 | uint16_t usReserved; /*!< Reserved */ 278 | uint8_t abRecvMbx[NETX_SYSTEM_MAILBOX_MIN_SIZE]; /*!< Receive mailbox packet buffer */ 279 | } __RCX_PACKED_POST NETX_SYSTEM_RECV_MAILBOX; 280 | 281 | /*****************************************************************************/ 282 | /*! Handshake cell definition */ 283 | /*****************************************************************************/ 284 | typedef __RCX_PACKED_PRE union NETX_HANDSHAKE_CELLtag 285 | { 286 | __RCX_PACKED_PRE struct 287 | { 288 | volatile uint8_t abData[2]; /*!< Data value, not belonging to handshake */ 289 | volatile uint8_t bNetxFlags; /*!< Device status flags (8Bit Mode) */ 290 | volatile uint8_t bHostFlags; /*!< Device command flags (8Bit Mode) */ 291 | } __RCX_PACKED_POST t8Bit; 292 | 293 | __RCX_PACKED_PRE struct 294 | { 295 | volatile uint16_t usNetxFlags; /*!< Device status flags (16Bit Mode) */ 296 | volatile uint16_t usHostFlags; /*!< Device command flags (16Bit Mode)*/ 297 | } __RCX_PACKED_POST t16Bit; 298 | volatile uint32_t ulValue; /*!< Handshake cell value */ 299 | } __RCX_PACKED_POST NETX_HANDSHAKE_CELL; 300 | 301 | /*****************************************************************************/ 302 | /*! Structure of the whole system channel (DPM) (Size 512 Byte) */ 303 | /*****************************************************************************/ 304 | typedef __RCX_PACKED_PRE struct NETX_SYSTEM_CHANNELtag 305 | { 306 | NETX_SYSTEM_INFO_BLOCK tSystemInfo; /*!< 0x000:0x02F System information block */ 307 | NETX_CHANNEL_INFO_BLOCK atChannelInfo[NETX_MAX_SUPPORTED_CHANNELS]; /*!< 0x030:0x0AF Channel information block */ 308 | NETX_HANDSHAKE_CELL tSysHandshake; /*!< 0x0B0:0x0B3 Handshake cells used, if not in Handshake block */ 309 | uint8_t abReserved[4]; /*!< 0x0B4:0x0B7 unused/reserved */ 310 | NETX_SYSTEM_CONTROL_BLOCK tSystemControl; /*!< 0x0B8:0x0BF System control block */ 311 | NETX_SYSTEM_STATUS_BLOCK tSystemState; /*!< 0x0C0:0x0FF System state block */ 312 | NETX_SYSTEM_SEND_MAILBOX tSystemSendMailbox; /*!< 0x100:0x17F Send mailbox */ 313 | NETX_SYSTEM_RECV_MAILBOX tSystemRecvMailbox; /*!< 0x180:0x1FF Receive mailbox */ 314 | } __RCX_PACKED_POST NETX_SYSTEM_CHANNEL; 315 | 316 | /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 317 | /*XX XXXXXXXXXXXXXX*/ 318 | /*XX HANDSHAKE CHANNEL LAYOUT XXXXXXXXXXXXXX*/ 319 | /*XX XXXXXXXXXXXXXX*/ 320 | /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 321 | 322 | /*****************************************************************************/ 323 | /*! Handshake array definition */ 324 | /*****************************************************************************/ 325 | typedef __RCX_PACKED_PRE struct NETX_HANDSHAKE_ARRAYtag 326 | { 327 | NETX_HANDSHAKE_CELL atHsk[NETX_HANDSHAKE_PAIRS]; /*!< Handshake cell block definition */ 328 | } __RCX_PACKED_POST NETX_HANDSHAKE_ARRAY; 329 | 330 | /*****************************************************************************/ 331 | /*! Handshake channel definition */ 332 | /*****************************************************************************/ 333 | typedef struct NETX_HANDSHAKE_CHANNELtag 334 | { 335 | NETX_HANDSHAKE_CELL tSysFlags; /*!< 0x00 System handshake flags */ 336 | NETX_HANDSHAKE_CELL tHskFlags; /*!< 0x04 not used */ 337 | NETX_HANDSHAKE_CELL tCommFlags0; /*!< 0x08 channel 0 handshake flags */ 338 | NETX_HANDSHAKE_CELL tCommFlags1; /*!< 0x0C channel 1 handshake flags */ 339 | NETX_HANDSHAKE_CELL tCommFlags2; /*!< 0x10 channel 2 handshake flags */ 340 | NETX_HANDSHAKE_CELL tCommFlags3; /*!< 0x14 channel 3 handshake flags */ 341 | NETX_HANDSHAKE_CELL tAppFlags0; /*!< 0x18 not supported yet */ 342 | NETX_HANDSHAKE_CELL tAppFlags1; /*!< 0x1C not supported yet */ 343 | uint32_t aulReserved[ 56 ]; /*!< 0x20 - 0xFF */ 344 | } NETX_HANDSHAKE_CHANNEL; 345 | 346 | /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 347 | /*XX XXXXXXXXXXXXXX*/ 348 | /*XX COMMUNICATION CHANNEL LAYOUT XXXXXXXXXXXXXX*/ 349 | /*XX XXXXXXXXXXXXXX*/ 350 | /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 351 | 352 | /*****************************************************************************/ 353 | /*! Default master status structure */ 354 | /*****************************************************************************/ 355 | typedef __RCX_PACKED_PRE struct NETX_MASTER_STATUStag 356 | { 357 | uint32_t ulSlaveState; /*!< Slave status */ 358 | uint32_t ulSlaveErrLogInd; /*!< Slave error indication */ 359 | uint32_t ulNumOfConfigSlaves; /*!< Number of configured slaves */ 360 | uint32_t ulNumOfActiveSlaves; /*!< Number of active slaves */ 361 | uint32_t ulNumOfDiagSlaves; /*!< Number of slaves in diag mode */ 362 | uint32_t ulReserved; /*!< unused/reserved */ 363 | } __RCX_PACKED_POST NETX_MASTER_STATUS; 364 | 365 | /* Master Status definitions */ 366 | #define RCX_SLAVE_STATE_UNDEFINED 0x00000000 367 | #define RCX_SLAVE_STATE_OK 0x00000001 368 | #define RCX_SLAVE_STATE_FAILED 0x00000002 369 | 370 | /*****************************************************************************/ 371 | /*! Channel handshake block (Size always 8 Byte) */ 372 | /*****************************************************************************/ 373 | typedef __RCX_PACKED_PRE struct NETX_HANDSHAKE_BLOCKtag 374 | { 375 | uint8_t abReserved[8]; /*!< unused/reserved */ 376 | } __RCX_PACKED_POST NETX_HANDSHAKE_BLOCK; 377 | 378 | /*****************************************************************************/ 379 | /*! Channel control block (Size 8 Byte) */ 380 | /*****************************************************************************/ 381 | typedef __RCX_PACKED_PRE struct NETX_CONTROL_BLOCKtag 382 | { 383 | uint32_t ulApplicationCOS; /*!< 0x00 Application "Change Of State" flags */ 384 | uint32_t ulDeviceWatchdog; /*!< 0x04 Watchdog cell written by the Host */ 385 | } __RCX_PACKED_POST NETX_CONTROL_BLOCK; 386 | 387 | /*****************************************************************************/ 388 | /*! Channel common status block (Size 64 Byte) */ 389 | /*****************************************************************************/ 390 | typedef __RCX_PACKED_PRE struct NETX_COMMON_STATUS_BLOCKtag 391 | { 392 | uint32_t ulCommunicationCOS; /*!< 0x00 Communication channel "Change Of State" */ 393 | uint32_t ulCommunicationState; /*!< 0x04 Actual communication state */ 394 | uint32_t ulCommunicationError; /*!< 0x08 Actual communication error */ 395 | uint16_t usVersion; /*!< 0x0C Version of the diagnostic structure */ 396 | uint16_t usWatchdogTime; /*!< 0x0E Configured watchdog time */ 397 | uint8_t bPDInHskMode; /*!< 0x10 Input area handshake mode. */ 398 | uint8_t bPDInSource; /*!< 0x11 Reserved. Set to zero.*/ 399 | uint8_t bPDOutHskMode; /*!< 0x12 Output area handshake mode. */ 400 | uint8_t bPDOutSource; /*!< 0x13 Reserved. Set to zero.*/ 401 | uint32_t ulHostWatchdog; /*!< 0x14 Host watchdog */ 402 | uint32_t ulErrorCount; /*!< 0x18 Number of erros since power-up */ 403 | uint8_t bErrorLogInd; /*!< 0x1C Counter of available Log Entries (not supported yet) */ 404 | uint8_t bErrorPDInCnt; /*!< 0x1D Counter of input process data handshake handling errors */ 405 | uint8_t bErrorPDOutCnt; /*!< 0x1E Counter of output process data handshake handling errors */ 406 | uint8_t bErrorSyncCnt; /*!< 0x1F Counter of synchronization handshake handling errors */ 407 | uint8_t bSyncHskMode; /*!< 0x20 Synchronization Handshake mode. */ 408 | uint8_t bSyncSource; /*!< 0x21 Synchronization source. */ 409 | uint16_t ausReserved[3]; /*!< 0x22 Reserved */ 410 | __RCX_PACKED_PRE union 411 | { 412 | NETX_MASTER_STATUS tMasterStatusBlock; /*!< For master implementations */ 413 | uint32_t aulReserved[6]; /*!< reserved */ 414 | } __RCX_PACKED_POST uStackDepended; /*!< 0x28 Stack depend status block */ 415 | } __RCX_PACKED_POST NETX_COMMON_STATUS_BLOCK; 416 | 417 | /*****************************************************************************/ 418 | /*! Channel extended status block (Size 432 Byte) */ 419 | /*****************************************************************************/ 420 | typedef __RCX_PACKED_PRE struct NETX_EXTENDED_STATUS_BLOCKtag 421 | { 422 | uint8_t abExtendedStatus[NETX_EXT_STATE_SIZE]; /*!< 0x00 Extended status buffer */ 423 | } __RCX_PACKED_POST NETX_EXTENDED_STATUS_BLOCK; 424 | 425 | /* Description of the extended status block structure */ 426 | #define RCX_EXT_STS_MAX_STRUCTURES 24 427 | /* Location definiton of the ext. state information (bStateArea) */ 428 | #define RCX_EXT_STS_STD_OUTPUT_BLK_ID 8 /* State field located in standard output area */ 429 | #define RCX_EXT_STS_HI_OUTPUT_BLK_ID 9 /* State field located in high prio. output area */ 430 | #define RCX_EXT_STS_STD_INPUT_BLK_ID 0 /* State field located in standard input area */ 431 | #define RCX_EXT_STS_HI_INPUT_BLK_ID 1 /* State field located in high prio. input area */ 432 | /* Definition of state information (bStateTypeID) */ 433 | #define RCX_EXT_STS_SLAVE_CONFIGURED 1 /* Configured slave bit field */ 434 | #define RCX_EXT_STS_SLAVE_ACTIV 2 /* Activ slave bit field */ 435 | #define RCX_EXT_STS_SLAVE_DIAGNOSTIC 3 /* Slave diagnostic bit field */ 436 | typedef __RCX_PACKED_PRE struct NETX_EXTENDED_STATE_STRUCT_Ttag 437 | { 438 | uint8_t bStateArea; /* Location of the ext. state information */ 439 | uint8_t bStateTypeID; /* Type of the state information */ 440 | uint16_t usNumOfStateEntries; /* Number of state entries of the type bStateTypeID */ 441 | uint32_t ulStateOffset; /* Byte start offset in the defined I/O area*/ 442 | } __RCX_PACKED_POST NETX_EXTENDED_STATE_STRUCT_T; 443 | 444 | typedef __RCX_PACKED_PRE struct NETX_EXTENDED_STATE_FIELD_Ttag 445 | { 446 | uint8_t bReserved[3]; /* 3 Bytes preserved. Not used. */ 447 | uint8_t bNumStateStructs; /* Number of following state structures */ 448 | NETX_EXTENDED_STATE_STRUCT_T atStateStruct[RCX_EXT_STS_MAX_STRUCTURES]; 449 | } __RCX_PACKED_POST NETX_EXTENDED_STATE_FIELD_T; 450 | typedef __RCX_PACKED_PRE struct NETX_EXTENDED_STATE_FIELD_DEFINITION_Ttag 451 | { 452 | uint8_t abReserved[172]; /* Default, protocol specific information area */ 453 | NETX_EXTENDED_STATE_FIELD_T tExtStateField; /* Extended status structures */ 454 | } __RCX_PACKED_POST NETX_EXTENDED_STATE_FIELD_DEFINITION_T; 455 | /*****************************************************************************/ 456 | /*! Channel send packet mailbox block (Size 1600 Byte) */ 457 | /*****************************************************************************/ 458 | typedef __RCX_PACKED_PRE struct NETX_SEND_MAILBOX_BLOCKtag 459 | { 460 | uint16_t usPackagesAccepted; /*!< 0x00 Number of packages that can be accepted */ 461 | uint16_t usReserved; /*!< 0x02 Reserved */ 462 | uint8_t abSendMailbox[NETX_CHANNEL_MAILBOX_SIZE]; /*!< 0x04 Send mailbox packet buffer */ 463 | } __RCX_PACKED_POST NETX_SEND_MAILBOX_BLOCK; 464 | 465 | /*****************************************************************************/ 466 | /*! Channel receive packet mailbox block (Size 1600 Byte) */ 467 | /*****************************************************************************/ 468 | typedef __RCX_PACKED_PRE struct NETX_RECV_MAILBOX_BLOCKtag 469 | { 470 | uint16_t usWaitingPackages; /*!< 0x00 Number of packages waiting to be processed */ 471 | uint16_t usReserved; /*!< 0x02 Reserved */ 472 | uint8_t abRecvMailbox[NETX_CHANNEL_MAILBOX_SIZE]; /*!< 0x04 Receive mailbox packet buffer */ 473 | } __RCX_PACKED_POST NETX_RECV_MAILBOX_BLOCK; 474 | 475 | /*****************************************************************************/ 476 | /*! Structure of the DEFAULT communication channel (Size 15616 Byte) */ 477 | /*****************************************************************************/ 478 | typedef __RCX_PACKED_PRE struct NETX_DEFAULT_COMM_CHANNELtag 479 | { 480 | NETX_HANDSHAKE_BLOCK tReserved; /*!< 0x000:0x007 Reserved for later use */ 481 | NETX_CONTROL_BLOCK tControl; /*!< 0x008:0x00F Control block */ 482 | NETX_COMMON_STATUS_BLOCK tCommonStatus; /*!< 0x010:0x04F Common status block */ 483 | NETX_EXTENDED_STATUS_BLOCK tExtendedStatus; /*!< 0x050:0x1FF Extended status block */ 484 | NETX_SEND_MAILBOX_BLOCK tSendMbx; /*!< 0x200:0x83F Send mailbox block */ 485 | NETX_RECV_MAILBOX_BLOCK tRecvMbx; /*!< 0x840:0xE7F Recveice mailbox block */ 486 | uint8_t abPd1Output[NETX_HP_IO_DATA_SIZE]; /*!< 0xE80:0xEBF Process data 1 output area */ 487 | uint8_t abPd1Input[NETX_HP_IO_DATA_SIZE]; /*!< 0xEC0:0xEFF Process data 1 input area */ 488 | uint8_t abReserved1[256]; /*!< 0xF00:0xFFF Reserved */ 489 | uint8_t abPd0Output[NETX_IO_DATA_SIZE]; /*!< 0x1000:0x267F Process data 0 output area */ 490 | uint8_t abPd0Input[NETX_IO_DATA_SIZE]; /*!< 0x2680:0x3CFF Process data 0 input area */ 491 | } __RCX_PACKED_POST NETX_DEFAULT_COMM_CHANNEL; 492 | 493 | 494 | /*****************************************************************************/ 495 | /*! Structure of the communication channel for 8K DPM hardware (e.g. COMX10) */ 496 | /*****************************************************************************/ 497 | typedef __RCX_PACKED_PRE struct NETX_8K_DPM_COMM_CHANNELtag 498 | { 499 | NETX_HANDSHAKE_BLOCK tReserved; /*!< 0x000:0x007 Reserved for later use */ 500 | NETX_CONTROL_BLOCK tControl; /*!< 0x008:0x00F Control block */ 501 | NETX_COMMON_STATUS_BLOCK tCommonStatus; /*!< 0x010:0x04F Common status block */ 502 | NETX_EXTENDED_STATUS_BLOCK tExtendedStatus; /*!< 0x050:0x1FF Extended status block */ 503 | NETX_SEND_MAILBOX_BLOCK tSendMbx; /*!< 0x200:0x83F Send mailbox block */ 504 | NETX_RECV_MAILBOX_BLOCK tRecvMbx; /*!< 0x840:0xE7F Recveice mailbox block */ 505 | uint8_t abPd1Output[NETX_HP_IO_DATA_SIZE]; /*!< 0xE80:0xEBF Process data 1 output area */ 506 | uint8_t abPd1Input[NETX_HP_IO_DATA_SIZE]; /*!< 0xEC0:0xEFF Process data 1 input area */ 507 | uint8_t abReserved1[256]; /*!< 0xF00:0xFFF Reserved */ 508 | uint8_t abPd0Output[NETX_IO_DATA_SIZE_8K_DPM]; /*!< 0x1000:0x15FF Process data 0 output area */ 509 | uint8_t abPd0Input[NETX_IO_DATA_SIZE_8K_DPM]; /*!< 0x1600:0x1BFF Process data 0 input area */ 510 | uint8_t abReserved2[256]; /*!< 0x1C00:0x1CFF Reserved */ 511 | } __RCX_PACKED_POST NETX_8K_DPM_COMM_CHANNEL; 512 | 513 | 514 | /* /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ /\ */ 515 | /* End of DPM Layout definition */ 516 | 517 | /*===========================================================================*/ 518 | /* */ 519 | /* Standardized Handshake Flags */ 520 | /* */ 521 | /*===========================================================================*/ 522 | 523 | /* --------------------------------------------*/ 524 | /* System Channel Handshake Flags */ 525 | /* --------------------------------------------*/ 526 | /* HOST Flags */ 527 | #define HSF_RESET 0x0001 /*!< Reset command bitmask */ 528 | #define HSF_BOOTSTART 0x0002 /*!< Set when device has a second stage loader, to enter bootloader mode after a system start */ 529 | #define HSF_HOST_COS_CMD 0x0004 /*!< Host "Change Of State" command bitmask */ 530 | #define HSF_NETX_COS_ACK 0x0008 /*!< NetX "Change Of State" acknowlegde bitmask */ 531 | #define HSF_SEND_MBX_CMD 0x0010 /*!< Send mailbox command bitmask */ 532 | #define HSF_RECV_MBX_ACK 0x0020 /*!< Receive mailbox acknowledge bitmask */ 533 | #define HSF_EXT_SEND_MBX_CMD 0x0040 /*!< Second stage loader extended mailbox command bitmask */ 534 | #define HSF_EXT_RECV_MBX_ACK 0x0080 /*!< Second stage loader extended mailbox ack bitmask */ 535 | 536 | /* HOST Flags as Bit number */ 537 | #define HSF_RESET_BIT_NO 0 /*!< Reset command bitnumber */ 538 | #define HSF_BOOTLOADER_BIT_NO 1 /*!< Bitnumber to be set when device has a second stage loader, to enter bootloader mode after a system start */ 539 | #define HSF_HOST_COS_CMD_BIT_NO 2 /*!< Host "Change Of State" command bitnumber */ 540 | #define HSF_NETX_COS_ACK_BIT_NO 3 /*!< NetX "Change Of State" acknowlegde bitnumber */ 541 | #define HSF_SEND_MBX_CMD_BIT_NO 4 /*!< Send mailbox command bitnumber */ 542 | #define HSF_RECV_MBX_ACK_BIT_NO 5 /*!< Receive mailbox acknowledge bitnumber */ 543 | #define HSF_EXT_SEND_MBX_CMD_BIT_NO 6 /*!< Second stage loader extended mailbox command bitnumber */ 544 | #define HSF_EXT_RECV_MBX_ACK_BIT_NO 7 /*!< Second stage loader extended mailbox ack bitnumber */ 545 | 546 | 547 | /* netX Flags */ 548 | #define NSF_READY 0x0001 /*!< netX System READY bitmask */ 549 | #define NSF_ERROR 0x0002 /*!< General system error bitmask */ 550 | #define NSF_HOST_COS_ACK 0x0004 /*!< Host "Change Of State" acknowledge bitmask */ 551 | #define NSF_NETX_COS_CMD 0x0008 /*!< NetX "Change of State command bitmask */ 552 | #define NSF_SEND_MBX_ACK 0x0010 /*!< Send mailbox acknowledge bitmask */ 553 | #define NSF_RECV_MBX_CMD 0x0020 /*!< Receive mailbox command bitmask */ 554 | #define NSF_EXT_SEND_MBX_ACK 0x0040 /*!< Second stage loader extended mailbox ack bitmask */ 555 | #define NSF_EXT_RECV_MBX_CMD 0x0080 /*!< Second stage loader extended mailbox command bitmask */ 556 | /* netX Flags as Bit number */ 557 | #define NSF_READY_BIT_NO 0 /*!< netX System READY bitnumber */ 558 | #define NSF_ERROR_BIT_NO 1 /*!< General system error bitnumber */ 559 | #define NSF_HOST_COS_ACK_BIT_NO 2 /*!< Host "Change Of State" acknowledge bitnumber */ 560 | #define NSF_NETX_COS_CMD_BIT_NO 3 /*!< NetX "Change of State command bitnumber */ 561 | #define NSF_SEND_MBX_ACK_BIT_NO 4 /*!< Send mailbox acknowledge bitnumber */ 562 | #define NSF_RECV_MBX_CMD_BIT_NO 5 /*!< Receive mailbox command bitnumber */ 563 | #define NSF_EXT_SEND_MBX_ACK_BIT_NO 6 /*!< Second stage loader extended mailbox ack bitnumber */ 564 | #define NSF_EXT_RECV_MBX_CMD_BIT_NO 7 /*!< Second stage loader extended mailbox command bitnumber */ 565 | 566 | /*--------------------------------------------*/ 567 | /* Communication Channel Handshake Flags */ 568 | /*--------------------------------------------*/ 569 | /* HOST Communication Channel Flags */ 570 | #define HCF_HOST_READY 0x0001 /*!< Host application is Ready bitmask */ 571 | #define HCF_unused 0x0002 /*!< unused */ 572 | #define HCF_HOST_COS_CMD 0x0004 /*!< Host "Change Of State" command bitmask */ 573 | #define HCF_NETX_COS_ACK 0x0008 /*!< NetX "Change Of State" acknowledge bitmask */ 574 | #define HCF_SEND_MBX_CMD 0x0010 /*!< Send mailbox command bitmask */ 575 | #define HCF_RECV_MBX_ACK 0x0020 /*!< Receive mailbox ackowledge bitmask */ 576 | #define HCF_PD0_OUT_CMD 0x0040 /*!< Process data, block 0, output command bitmask */ 577 | #define HCF_PD0_IN_ACK 0x0080 /*!< Process data, block 0, input acknowlegde bitmask */ 578 | #define HCF_PD1_OUT_CMD 0x0100 /*!< Process data, block 1, output command bitmask */ 579 | #define HCF_PD1_IN_ACK 0x0200 /*!< Process data, block 1, input acknowlegde bitmask */ 580 | /* HOST Communication Channel Flags as Bit number */ 581 | #define HCF_HOST_READY_BIT_NO 0 /*!< Host application is Ready bitnumber */ 582 | #define HCF_unused_BIT_NO 1 /*!< unused */ 583 | #define HCF_HOST_COS_CMD_BIT_NO 2 /*!< Host "Change Of State" command bitnumber */ 584 | #define HCF_NETX_COS_ACK_BIT_NO 3 /*!< NetX "Change Of State" acknowledge bitnumber */ 585 | #define HCF_SEND_MBX_CMD_BIT_NO 4 /*!< Send mailbox command bitnumber */ 586 | #define HCF_RECV_MBX_ACK_BIT_NO 5 /*!< Receive mailbox ackowledge bitnumber */ 587 | #define HCF_PD0_OUT_CMD_BIT_NO 6 /*!< Process data, block 0, output command bitnumber */ 588 | #define HCF_PD0_IN_ACK_BIT_NO 7 /*!< Process data, block 0, input acknowlegde bitnumber */ 589 | #define HCF_PD1_OUT_CMD_BIT_NO 8 /*!< Process data, block 1, output command bitnumber */ 590 | #define HCF_PD1_IN_ACK_BIT_NO 9 /*!< Process data, block 1, input acknowlegde bitnumber */ 591 | 592 | /* netX Communication Channel Flags */ 593 | #define NCF_COMMUNICATING 0x0001 /*!< Channel has an active conection bitmask */ 594 | #define NCF_ERROR 0x0002 /*!< Communication channel error bitmask */ 595 | #define NCF_HOST_COS_ACK 0x0004 /*!< Host "Change Of State" acknowledge bitmask */ 596 | #define NCF_NETX_COS_CMD 0x0008 /*!< NetX "Change Of State" command bitmask */ 597 | #define NCF_SEND_MBX_ACK 0x0010 /*!< Send mailbox acknowldege bitmask */ 598 | #define NCF_RECV_MBX_CMD 0x0020 /*!< Receive mailbox command bitmask */ 599 | #define NCF_PD0_OUT_ACK 0x0040 /*!< Process data, block 0, output acknowledge bitmask */ 600 | #define NCF_PD0_IN_CMD 0x0080 /*!< Process data, block 0, input command bitmask */ 601 | #define NCF_PD1_OUT_ACK 0x0100 /*!< Process data, block 1, output acknowlegde bitmask */ 602 | #define NCF_PD1_IN_CMD 0x0200 /*!< Process data, block 1, input command bitmask */ 603 | /* netX Communication Channel Flags as Bit number */ 604 | #define NCF_COMMUNICATING_BIT_NO 0 /*!< Channel has an active conection bitnumber */ 605 | #define NCF_ERROR_BIT_NO 1 /*!< Communication channel error bitnumber */ 606 | #define NCF_HOST_COS_ACK_BIT_NO 2 /*!< Host "Change Of State" acknowledge bitnumber */ 607 | #define NCF_NETX_COS_CMD_BIT_NO 3 /*!< NetX "Change Of State" command bitnumber */ 608 | #define NCF_SEND_MBX_ACK_BIT_NO 4 /*!< Send mailbox acknowldege bitnumber */ 609 | #define NCF_RECV_MBX_CMD_BIT_NO 5 /*!< Receive mailbox command bitnumber */ 610 | #define NCF_PD0_OUT_ACK_BIT_NO 6 /*!< Process data, block 0, output acknowledge bitnumber */ 611 | #define NCF_PD0_IN_CMD_BIT_NO 7 /*!< Process data, block 0, input command bitnumber */ 612 | #define NCF_PD1_OUT_ACK_BIT_NO 8 /*!< Process data, block 1, output acknowlegde bitnumber */ 613 | #define NCF_PD1_IN_CMD_BIT_NO 9 /*!< Process data, block 1, input command bitnumber */ 614 | 615 | /*--------------------------------------------*/ 616 | /* Handshake Flags State Definitions */ 617 | /*--------------------------------------------*/ 618 | /* Flag state definition */ 619 | #define RCX_FLAGS_EQUAL 0 620 | #define RCX_FLAGS_NOT_EQUAL 1 621 | #define RCX_FLAGS_CLEAR 2 622 | #define RCX_FLAGS_SET 3 623 | #define RCX_FLAGS_NONE 0xFF 624 | 625 | #define RCX_FLAG_CLEAR 0 626 | #define RCX_FLAG_SET 1 627 | 628 | /*===========================================================================*/ 629 | /* */ 630 | /* SYSTEM CHANNEL Configuration definitions */ 631 | /* */ 632 | /*===========================================================================*/ 633 | 634 | /*--------------------------------------------*/ 635 | /* SYSTEM STATUS BLOCK */ 636 | /*--------------------------------------------*/ 637 | /* System Change of State flags */ 638 | #define RCX_SYS_COS_UNDEFINED 0 639 | #define RCX_SYS_COS_DEFAULT_MEMORY 0x80000000 640 | /* System Change of State flags as bit number */ 641 | #define RCX_SYS_COS_DEFAULT_MEMORY_BIT_NO 31 642 | 643 | /* System Status */ 644 | #define RCX_SYS_STATUS_UNDEFINED 0x00000000 645 | #define RCX_SYS_STATUS_OK 0x00000001 646 | #define RCX_SYS_STATUS_BOOTMEDIUM_MASK 0x0F000000 647 | #define RCX_SYS_STATUS_BOOTMEDIUM_RAM 0x00000000 648 | #define RCX_SYS_STATUS_BOOTMEDIUM_SERFLASH 0x01000000 649 | #define RCX_SYS_STATUS_BOOTMEDIUM_PARFLASH 0x02000000 650 | #define RCX_SYS_STATUS_NO_SYSVOLUME 0x20000000 651 | #define RCX_SYS_STATUS_SYSVOLUME_FFS 0x40000000 /* _FFS = Flash File System */ 652 | #define RCX_SYS_STATUS_NXO_SUPPORTED 0x80000000 653 | 654 | /* System Status definition */ 655 | #define RCX_SYS_STATE_UNDEFINED 0 656 | #define RCX_SYS_STATE_OK 1 657 | 658 | /* System Error definitions */ 659 | #define RCX_SYS_ERROR_SUCCESS 0 660 | 661 | /* System Status */ 662 | #define RCX_SYS_STATE_RESET 0x000000F0 663 | #define RCX_SYS_STATE_SELF_TEST 0x000000EF 664 | #define RCX_SYS_STATE_RAM_TEST 0x000000EE 665 | #define RCX_SYS_STATE_FAULT_INIT 0x000000ED 666 | #define RCX_SYS_STATE_DEVICE_INIT 0x000000EC 667 | #define RCX_SYS_STATE_MAILBOX_INIT 0x000000EB 668 | #define RCX_SYS_STATE_SERIAL_INIT 0x000000EA 669 | #define RCX_SYS_STATE_SEMAPHORE_INIT 0x000000E9 670 | #define RCX_SYS_STATE_QUEUE_INIT 0x000000E8 671 | #define RCX_SYS_STATE_MUTEX_INIT 0x000000E7 672 | #define RCX_SYS_STATE_EVENT_INIT 0x000000E6 673 | #define RCX_SYS_STATE_SIGNAL_INIT 0x000000E5 674 | #define RCX_SYS_STATE_TIMER_INIT 0x000000E4 675 | #define RCX_SYS_STATE_BARRIER_INIT 0x000000E3 676 | #define RCX_SYS_STATE_DIAGNOSTIC_INIT 0x000000E2 677 | #define RCX_SYS_STATE_FINITE_STATE_INIT 0x000000E1 678 | #define RCX_SYS_STATE_INTERRUPT_INIT 0x000000E0 679 | #define RCX_SYS_STATE_LED_INIT 0x000000DF 680 | /*#define RCX_SYS_STATE_TIMER_INIT 0x000000DE*/ 681 | #define RCX_SYS_STATE_PAR_FLASH_INIT 0x000000DD 682 | #define RCX_SYS_STATE_XC_INIT 0x000000DC 683 | #define RCX_SYS_STATE_PHY_INIT 0x000000DB 684 | #define RCX_SYS_STATE_UART_INIT 0x000000DA 685 | #define RCX_SYS_STATE_VOL_INIT 0x000000D9 686 | #define RCX_SYS_STATE_EDD_INIT 0x000000D8 687 | #define RCX_SYS_STATE_ICM_INIT 0x000000D7 688 | #define RCX_SYS_STATE_USB_INIT 0x000000D6 689 | #define RCX_SYS_STATE_FIFO_INIT 0x000000D5 690 | #define RCX_SYS_STATE_EBUS_INIT 0x000000D4 691 | #define RCX_SYS_STATE_MMU_INIT 0x000000D3 692 | #define RCX_SYS_STATE_TCM_INIT 0x000000D2 693 | #define RCX_SYS_STATE_CCH_INIT 0x000000D1 694 | #define RCX_SYS_STATE_MID_SYS_INIT 0x000000D0 695 | #define RCX_SYS_STATE_MID_DBM_INIT 0x000000CF 696 | #define RCX_SYS_STATE_HIF_INIT 0x000000CE 697 | #define RCX_SYS_STATE_HIFPIO_INIT 0x000000CD 698 | #define RCX_SYS_STATE_SPI_INIT 0x000000CC 699 | #define RCX_SYS_STATE_FIQ_INIT 0x000000CB 700 | #define RCX_SYS_STATE_SEC_INIT 0x000000CA 701 | #define RCX_SYS_STATE_CRC_INIT 0x000000C9 702 | #define RCX_SYS_STATE_MEMORY_INIT 0x000000C8 703 | #define RCX_SYS_STATE_SER_FLASH_INIT 0x000000C7 704 | #define RCX_SYS_STATE_TASKS_INIT 0x000000C6 705 | #define RCX_SYS_STATE_MID_STA_INIT 0x000000C5 706 | #define RCX_SYS_STATE_MULTITASK_INIT 0x000000C4 707 | #define RCX_SYS_STATE_IDLE_TASK_INIT 0x000000C3 708 | #define RCX_SYS_STATE_GPIO_INIT 0x000000C2 709 | #define RCX_SYS_STATE_PIO_INIT 0x000000C1 710 | #define RCX_SYS_STATE_SUCCESS 0x00000000 711 | 712 | /* System Error */ 713 | #define RCX_SYS_SUCCESS 0x00000000 714 | #define RCX_SYS_RAM_NOT_FOUND 0x00000001 715 | #define RCX_SYS_RAM_TYPE 0x00000002 716 | #define RCX_SYS_RAM_SIZE 0x00000003 717 | #define RCX_SYS_RAM_TEST 0x00000004 718 | #define RCX_SYS_FLASH_NOT_FOUND 0x00000005 719 | #define RCX_SYS_FLASH_TYPE 0x00000006 720 | #define RCX_SYS_FLASH_SIZE 0x00000007 721 | #define RCX_SYS_FLASH_TEST 0x00000008 722 | #define RCX_SYS_EEPROM_NOT_FOUND 0x00000009 723 | #define RCX_SYS_EEPROM_TYPE 0x0000000A 724 | #define RCX_SYS_EEPROM_SIZE 0x0000000B 725 | #define RCX_SYS_EEPROM_TEST 0x0000000C 726 | #define RCX_SYS_SECURE_EEPROM 0x0000000D 727 | #define RCX_SYS_SECURE_EEPROM_NOT_INIT 0x0000000E 728 | #define RCX_SYS_FILE_SYSTEM_FAULT 0x0000000F 729 | #define RCX_SYS_VERSION_CONFLICT 0x00000010 730 | #define RCX_SYS_NOT_INITIALIZED 0x00000011 731 | #define RCX_SYS_MEM_ALLOC 0x00000012 732 | 733 | /* LED State definition */ 734 | #define RCX_LED_STATE_MASK 0x0F 735 | #define RCX_LED_STATE_OFF 0x00 736 | #define RCX_LED_STATE_SOLID_ON 0x01 737 | #define RCX_LED_STATE_FLICKER 0x02 738 | #define RCX_LED_STATE_SINGLE_FLICKER 0x03 739 | #define RCX_LED_STATE_FLASH_CYCLIC 0x04 740 | #define RCX_LED_STATE_FLASH_CYCLIC_FAST 0x05 741 | #define RCX_LED_STATE_SINGLE_FLASH 0x06 742 | #define RCX_LED_STATE_DOUBLE_FLASH 0x07 743 | #define RCX_LED_STATE_QUADRUPLE_FLASH 0x08 744 | #define RCX_LED_STATE_FLASH_NON_CYCLIC 0x09 745 | #define RCX_LED_STATE_TRIPLE_FLASH 0x0A 746 | 747 | /* LED Color State */ 748 | #define RCX_LED_COLOR_STATE_MASK 0xF0 749 | #define RCX_LED_COLOR_NOT_USED 0x00 750 | #define RCX_LED_COLOR_RED 0x10 751 | #define RCX_LED_COLOR_YELLOW 0x20 752 | #define RCX_LED_COLOR_GREEN 0x30 753 | #define RCX_LED_COLOR_BLUE 0x40 754 | #define RCX_LED_COLOR_RED_GREEN 0x50 755 | #define RCX_LED_COLOR_RED_YELLOW 0x60 756 | #define RCX_LED_COLOR_GREEN_YELLOW 0x70 757 | 758 | /* System LED definition */ 759 | #define RCX_LED_OFF 0x00 760 | #define RCX_LED_YEL_CYCLIC_FAST 0x25 761 | #define RCX_LED_YEL_CYCLIC 0x24 762 | #define RCX_LED_YEL_NONCYCLIC 0x29 763 | #define RCX_LED_GRN_SOLID 0x31 764 | #define RCX_LED_GRN_CYCLIC 0x34 765 | #define RCX_LED_GRN_NONCYCLIC 0x39 766 | 767 | /* System Hardware Features */ 768 | /* Extended Memory */ 769 | #define RCX_SYSTEM_EXTMEM_TYPE_MSK 0x0000000F 770 | #define RCX_SYSTEM_EXTMEM_TYPE_NONE 0x00000000 771 | #define RCX_SYSTEM_EXTMEM_TYPE_MRAM_128K 0x00000001 772 | 773 | #define RCX_SYSTEM_EXTMEM_ACCESS_MSK 0x000000C0 774 | #define RCX_SYSTEM_EXTMEM_ACCESS_NONE 0x00000000 775 | #define RCX_SYSTEM_EXTMEM_ACCESS_EXTERNAL 0x00000040 776 | #define RCX_SYSTEM_EXTMEM_ACCESS_INTERNAL 0x00000080 777 | #define RCX_SYSTEM_EXTMEM_ACCESS_BOTH 0x000000C0 778 | 779 | /* RTC */ 780 | #define RCX_SYSTEM_HW_RTC_MSK 0x00000700 781 | #define RCX_SYSTEM_HW_RTC_TYPE_MSK 0x00000300 782 | #define RCX_SYSTEM_HW_RTC_TYPE_NONE 0x00000000 783 | #define RCX_SYSTEM_HW_RTC_TYPE_INTERNAL 0x00000100 784 | #define RCX_SYSTEM_HW_RTC_TYPE_EXTERNAL 0x00000200 785 | #define RCX_SYSTEM_HW_RTC_TYPE_EMULATED 0x00000300 786 | #define RCX_SYSTEM_HW_RTC_STATE 0x00000400 787 | 788 | /*--------------------------------------------*/ 789 | /* SYSTEM INFORMATION BLOCK */ 790 | /*--------------------------------------------*/ 791 | /* Hardware options */ 792 | #define RCX_HW_ASSEMBLY_UNDEFINED 0x0000 793 | #define RCX_HW_ASSEMBLY_NOT_AVAILABLE 0x0001 794 | 795 | #define RCX_HW_ASSEMBLY_VALIDATION_START 0x0010 /* Start of HW option validation area */ 796 | 797 | #define RCX_HW_ASSEMBLY_SERIAL 0x0010 798 | #define RCX_HW_ASSEMBLY_ASI 0x0020 799 | #define RCX_HW_ASSEMBLY_CAN 0x0030 800 | #define RCX_HW_ASSEMBLY_DEVICENET 0x0040 801 | #define RCX_HW_ASSEMBLY_PROFIBUS 0x0050 802 | 803 | #define RCX_HW_ASSEMBLY_CCLINK 0x0070 804 | #define RCX_HW_ASSEMBLY_ETHERNET 0x0080 805 | #define RCX_HW_ASSEMBLY_ETHERNET_X_PHY 0x0081 806 | #define RCX_HW_ASSEMBLY_ETHERNET_FIBRE_OPTIC 0x0082 807 | 808 | #define RCX_HW_ASSEMBLY_SPI 0x0090 809 | #define RCX_HW_ASSEMBLY_IO_LINK 0x00A0 810 | #define RCX_HW_ASSEMBLY_COMPONET 0x00B0 811 | 812 | #define RCX_HW_ASSEMBLY_VALIDATION_END 0xFFEF /* End of HW option validation area */ 813 | 814 | #define RCX_HW_ASSEMBLY_I2C_UNKNOWN 0xFFF4 815 | #define RCX_HW_ASSEMBLY_SSI 0xFFF5 816 | #define RCX_HW_ASSEMBLY_SYNC 0xFFF6 817 | 818 | #define RCX_HW_ASSEMBLY_FIELDBUS 0xFFF8 819 | 820 | #define RCX_HW_ASSEMBLY_TOUCH_SCREEN 0xFFFA 821 | #define RCX_HW_ASSEMBLY_I2C_PIO 0xFFFB 822 | #define RCX_HW_ASSEMBLY_I2C_PIO_NT 0xFFFC 823 | #define RCX_HW_ASSEMBLY_PROPRIETARY 0xFFFD 824 | #define RCX_HW_ASSEMBLY_NOT_CONNECTED 0xFFFE 825 | #define RCX_HW_ASSEMBLY_RESERVED 0xFFFF 826 | 827 | /* Manufacturer definition */ 828 | #define RCX_MANUFACTURER_UNDEFINED 0x0000 829 | #define RCX_MANUFACTURER_HILSCHER_GMBH 0x0001 /* Hilscher GmbH */ 830 | #define RCX_MANUFACTURER_HILSCHER_GMBH_MAX 0x00FF /* Hilscher GmbH max. value*/ 831 | 832 | /* Production date definition */ 833 | #define RCX_PRODUCTION_DATE_YEAR_MASK 0xFF00 /* Year offset (0..255) starting at 2000 */ 834 | #define RCX_PRODUCTION_DATE_WEEK_MASK 0x00FF /* Week of year ( 1..52) */ 835 | 836 | /* Device class definition */ 837 | #define RCX_HW_DEV_CLASS_UNDEFINED 0x0000 838 | #define RCX_HW_DEV_CLASS_UNCLASSIFIABLE 0x0001 839 | #define RCX_HW_DEV_CLASS_CHIP_NETX_500 0x0002 840 | #define RCX_HW_DEV_CLASS_CIFX 0x0003 841 | #define RCX_HW_DEV_CLASS_COMX_100 0x0004 842 | #define RCX_HW_DEV_CLASS_COMX 0x0004 /* old definition only for compatibility reasons */ 843 | #define RCX_HW_DEV_CLASS_EVA_BOARD 0x0005 844 | #define RCX_HW_DEV_CLASS_NETDIMM 0x0006 845 | #define RCX_HW_DEV_CLASS_CHIP_NETX_100 0x0007 846 | #define RCX_HW_DEV_CLASS_NETX_HMI 0x0008 847 | 848 | #define RCX_HW_DEV_CLASS_NETIO_50 0x000A 849 | #define RCX_HW_DEV_CLASS_NETIO_100 0x000B 850 | #define RCX_HW_DEV_CLASS_CHIP_NETX_50 0x000C 851 | #define RCX_HW_DEV_CLASS_GW_NETPAC 0x000D 852 | #define RCX_HW_DEV_CLASS_GW_NETTAP 0x000E 853 | #define RCX_HW_DEV_CLASS_NETSTICK 0x000F 854 | #define RCX_HW_DEV_CLASS_NETANALYZER 0x0010 855 | #define RCX_HW_DEV_CLASS_NETSWITCH 0x0011 856 | #define RCX_HW_DEV_CLASS_NETLINK 0x0012 857 | #define RCX_HW_DEV_CLASS_NETIC_50 0x0013 858 | #define RCX_HW_DEV_CLASS_NETIC 0x0013 /* old definition only for compatibility reasons */ 859 | #define RCX_HW_DEV_CLASS_NPLC_C100 0x0014 860 | #define RCX_HW_DEV_CLASS_NPLC_M100 0x0015 861 | #define RCX_HW_DEV_CLASS_GW_NETTAP_50 0x0016 862 | #define RCX_HW_DEV_CLASS_NETBRICK 0x0017 863 | #define RCX_HW_DEV_CLASS_NPLC_T100 0x0018 864 | #define RCX_HW_DEV_CLASS_NETLINK_PROXY 0x0019 865 | #define RCX_HW_DEV_CLASS_CHIP_NETX_10 0x001A 866 | #define RCX_HW_DEV_CLASS_NETJACK_10 0x001B 867 | #define RCX_HW_DEV_CLASS_NETJACK_50 0x001C 868 | #define RCX_HW_DEV_CLASS_NETJACK_100 0x001D 869 | #define RCX_HW_DEV_CLASS_NETJACK_500 0x001E 870 | #define RCX_HW_DEV_CLASS_NETLINK_10_USB 0x001F 871 | #define RCX_HW_DEV_CLASS_COMX_10 0x0020 872 | #define RCX_HW_DEV_CLASS_NETIC_10 0x0021 873 | #define RCX_HW_DEV_CLASS_COMX_50 0x0022 874 | #define RCX_HW_DEV_CLASS_NETRAPID_10 0x0023 875 | #define RCX_HW_DEV_CLASS_NETRAPID_50 0x0024 876 | #define RCX_HW_DEV_CLASS_NETSCADA_T51 0x0025 877 | #define RCX_HW_DEV_CLASS_CHIP_NETX_51 0x0026 878 | #define RCX_HW_DEV_CLASS_NETRAPID_51 0x0027 879 | #define RCX_HW_DEV_CLASS_GW_EU5C 0x0028 880 | #define RCX_HW_DEV_CLASS_NETSCADA_T50 0x0029 881 | #define RCX_HW_DEV_CLASS_NETSMART_50 0x002A 882 | #define RCX_HW_DEV_CLASS_IOLINK_GW_51 0x002B 883 | #define RCX_HW_DEV_CLASS_NETHMI_B500 0x002C 884 | #define RCX_HW_DEV_CLASS_CHIP_NETX_52 0x002D 885 | #define RCX_HW_DEV_CLASS_COMX_51 0x002E 886 | #define RCX_HW_DEV_CLASS_NETJACK_51 0x002F 887 | #define RCX_HW_DEV_CLASS_NETHOST_T100 0x0030 888 | #define RCX_HW_DEV_CLASS_NETSCOPE_C100 0x0031 889 | #define RCX_HW_DEV_CLASS_NETRAPID_52 0x0032 890 | #define RCX_HW_DEV_CLASS_NETSMART_T51 0x0033 891 | #define RCX_HW_DEV_CLASS_NETSCADA_T52 0x0034 892 | #define RCX_HW_DEV_CLASS_NETSAFETY_51 0x0035 893 | #define RCX_HW_DEV_CLASS_NETSAFETY_52 0x0036 894 | #define RCX_HW_DEV_CLASS_NETPLC_J500 0x0037 895 | #define RCX_HW_DEV_CLASS_NETIC_52 0x0038 896 | 897 | #define RCX_HW_DEV_CLASS_HILSCHER_GMBH_MAX 0x7FFF /* Hilscher GmbH max. value*/ 898 | #define RCX_HW_DEV_CLASS_OEM_DEVICE 0xFFFE 899 | 900 | /*--------------------------------------------*/ 901 | /* CHANNEL INFORMATION BLOCK */ 902 | /*--------------------------------------------*/ 903 | /* Channel type definitions */ 904 | #define RCX_CHANNEL_TYPE_UNDEFINED 0 /*!< Type of the channel is undefined */ 905 | #define RCX_CHANNEL_TYPE_NOT_AVAILABLE 1 /*!< Type of the channel not available */ 906 | #define RCX_CHANNEL_TYPE_RESERVED 2 /*!< Reserved */ 907 | #define RCX_CHANNEL_TYPE_SYSTEM 3 /*!< System channel */ 908 | #define RCX_CHANNEL_TYPE_HANDSHAKE 4 /*!< Handshake channel */ 909 | #define RCX_CHANNEL_TYPE_COMMUNICATION 5 /*!< Communication channel */ 910 | #define RCX_CHANNEL_TYPE_APPLICATION 6 /*!< Application channnel */ 911 | #define RCX_CHANNEL_TYPE_MAX 127 /*!< Maximum used channel number */ 912 | #define RCX_CHANNEL_TYPE_USER_DEFINED_START 128 /*!< User defined channel */ 913 | 914 | /* Handshake cell, size and position */ 915 | #define RCX_HANDSHAKE_SIZE_MASK 0x0F /*!< Handshake size mask */ 916 | #define RCX_HANDSHAKE_SIZE_NOT_AVAILABLE 0x00 /*!< No handshake cells */ 917 | #define RCX_HANDSHAKE_SIZE_8BIT 0x01 /*!< Handshake cell size 8bit */ 918 | #define RCX_HANDSHAKE_SIZE_16BIT 0x02 /*!< Handshake cell size 16bit */ 919 | 920 | #define RCX_HANDSHAKE_POSITION_MASK 0xF0 /*!< Handshake position mask */ 921 | #define RCX_HANDSHAKE_POSITION_BEGINNING 0x00 /*!< Handshake cells located at the start of each channel */ 922 | #define RCX_HANDSHAKE_POSITION_CHANNEL 0x10 /*!< Handshake cells located in an own channel */ 923 | 924 | /* Communication Class information */ 925 | #define RCX_COMM_CLASS_UNDEFINED 0x0000 926 | #define RCX_COMM_CLASS_UNCLASSIFIABLE 0x0001 927 | #define RCX_COMM_CLASS_MASTER 0x0002 928 | #define RCX_COMM_CLASS_SLAVE 0x0003 929 | #define RCX_COMM_CLASS_SCANNER 0x0004 930 | #define RCX_COMM_CLASS_ADAPTER 0x0005 931 | #define RCX_COMM_CLASS_MESSAGING 0x0006 932 | #define RCX_COMM_CLASS_CLIENT 0x0007 933 | #define RCX_COMM_CLASS_SERVER 0x0008 934 | #define RCX_COMM_CLASS_IO_CONTROLLER 0x0009 935 | #define RCX_COMM_CLASS_IO_DEVICE 0x000A 936 | #define RCX_COMM_CLASS_IO_SUPERVISOR 0x000B 937 | #define RCX_COMM_CLASS_GATEWAY 0x000C 938 | #define RCX_COMM_CLASS_MONITOR 0x000D 939 | #define RCX_COMM_CLASS_PRODUCER 0x000E 940 | #define RCX_COMM_CLASS_CONSUMER 0x000F 941 | #define RCX_COMM_CLASS_SWITCH 0x0010 942 | #define RCX_COMM_CLASS_HUB 0x0011 943 | #define RCX_COMM_CLASS_COMBI 0x0012 944 | #define RCX_COMM_CLASS_MANAGING_NODE 0x0013 945 | #define RCX_COMM_CLASS_CONTROLLED_NODE 0x0014 946 | #define RCX_COMM_CLASS_PLC 0x0015 947 | #define RCX_COMM_CLASS_HMI 0x0016 948 | #define RCX_COMM_CLASS_ITEM_SERVER 0x0017 949 | 950 | /* Protocol Class information */ 951 | #define RCX_PROT_CLASS_UNDEFINED 0x0000 952 | #define RCX_PROT_CLASS_3964R 0x0001 953 | #define RCX_PROT_CLASS_ASINTERFACE 0x0002 954 | #define RCX_PROT_CLASS_ASCII 0x0003 955 | #define RCX_PROT_CLASS_CANOPEN 0x0004 956 | #define RCX_PROT_CLASS_CCLINK 0x0005 957 | #define RCX_PROT_CLASS_COMPONET 0x0006 958 | #define RCX_PROT_CLASS_CONTROLNET 0x0007 959 | #define RCX_PROT_CLASS_DEVICENET 0x0008 960 | #define RCX_PROT_CLASS_ETHERCAT 0x0009 961 | #define RCX_PROT_CLASS_ETHERNET_IP 0x000A 962 | #define RCX_PROT_CLASS_FOUNDATION_FB 0x000B 963 | #define RCX_PROT_CLASS_FL_NET 0x000C 964 | #define RCX_PROT_CLASS_INTERBUS 0x000D 965 | #define RCX_PROT_CLASS_IO_LINK 0x000E 966 | #define RCX_PROT_CLASS_LON 0x000F 967 | #define RCX_PROT_CLASS_MODBUS_PLUS 0x0010 968 | #define RCX_PROT_CLASS_MODBUS_RTU 0x0011 969 | #define RCX_PROT_CLASS_OPEN_MODBUS_TCP 0x0012 970 | #define RCX_PROT_CLASS_PROFIBUS_DP 0x0013 971 | #define RCX_PROT_CLASS_PROFIBUS_MPI 0x0014 972 | #define RCX_PROT_CLASS_PROFINET_IO 0x0015 973 | #define RCX_PROT_CLASS_RK512 0x0016 974 | #define RCX_PROT_CLASS_SERCOS_II 0x0017 975 | #define RCX_PROT_CLASS_SERCOS_III 0x0018 976 | #define RCX_PROT_CLASS_TCP_IP_UDP_IP 0x0019 977 | #define RCX_PROT_CLASS_POWERLINK 0x001A 978 | #define RCX_PROT_CLASS_HART 0x001B 979 | #define RCX_PROT_CLASS_COMBI 0x001C 980 | #define RCX_PROT_CLASS_PROG_GATEWAY 0x001D 981 | #define RCX_PROT_CLASS_PROG_SERIAL 0x001E 982 | #define RCX_PROT_CLASS_PLC_CODESYS 0x001F 983 | #define RCX_PROT_CLASS_PLC_PROCONOS 0x0020 984 | #define RCX_PROT_CLASS_PLC_IBH_S7 0x0021 985 | #define RCX_PROT_CLASS_PLC_ISAGRAF 0x0022 986 | #define RCX_PROT_CLASS_VISU_QVIS 0x0023 987 | #define RCX_PROT_CLASS_ETHERNET 0x0024 988 | #define RCX_PROT_CLASS_RFC1006 0x0025 989 | #define RCX_PROT_CLASS_DF1 0x0026 990 | #define RCX_PROT_CLASS_VARAN 0x0027 991 | #define PROT_CLASS_3S_PLC_HANDLER 0x0028 992 | #define RCX_PROT_CLASS_OEM 0xFFF0 993 | 994 | /*===========================================================================*/ 995 | /* */ 996 | /* COMMUNICATION / APPLICATION CHANNEL Configuration definitions */ 997 | /* */ 998 | /*===========================================================================*/ 999 | /*-----------------------------------*/ 1000 | /* CHANNEL CONTROL BLOCK */ 1001 | /*-----------------------------------*/ 1002 | /* Application Change of State */ 1003 | #define RCX_APP_COS_APPLICATION_READY 0x00000001 1004 | #define RCX_APP_COS_BUS_ON 0x00000002 1005 | #define RCX_APP_COS_BUS_ON_ENABLE 0x00000004 1006 | #define RCX_APP_COS_INITIALIZATION 0x00000008 1007 | #define RCX_APP_COS_INITIALIZATION_ENABLE 0x00000010 1008 | #define RCX_APP_COS_LOCK_CONFIGURATION 0x00000020 1009 | #define RCX_APP_COS_LOCK_CONFIGURATION_ENABLE 0x00000040 1010 | #define RCX_APP_COS_DMA 0x00000080 1011 | #define RCX_APP_COS_DMA_ENABLE 0x00000100 1012 | 1013 | /* Application Change of State flags as bit number */ 1014 | #define RCX_APP_COS_APPLICATION_READY_BIT_NO 0 1015 | #define RCX_APP_COS_BUS_ON_BIT_NO 1 1016 | #define RCX_APP_COS_BUS_ON_ENABLE_BIT_NO 2 1017 | #define RCX_APP_COS_INITIALIZATION_BIT_NO 3 1018 | #define RCX_APP_COS_INITIALIZATION_ENABLE_BIT_NO 4 1019 | #define RCX_APP_COS_LOCK_CONFIGURATION_BIT_NO 5 1020 | #define RCX_APP_COS_LOCK_CONFIGURATION_ENABLE_BIT_NO 6 1021 | #define RCX_APP_COS_DMA_BIT_NO 7 1022 | #define RCX_APP_COS_DMA_ENABLE_BIT_NO 8 1023 | 1024 | /*-----------------------------------*/ 1025 | /* CHANNEL COMMON STATUS BLOCK */ 1026 | /*-----------------------------------*/ 1027 | /* Channel Change Of State flags */ 1028 | #define RCX_COMM_COS_UNDEFINED 0x00000000 1029 | #define RCX_COMM_COS_READY 0x00000001 1030 | #define RCX_COMM_COS_RUN 0x00000002 1031 | #define RCX_COMM_COS_BUS_ON 0x00000004 1032 | #define RCX_COMM_COS_CONFIG_LOCKED 0x00000008 1033 | #define RCX_COMM_COS_CONFIG_NEW 0x00000010 1034 | #define RCX_COMM_COS_RESTART_REQUIRED 0x00000020 1035 | #define RCX_COMM_COS_RESTART_REQUIRED_ENABLE 0x00000040 1036 | #define RCX_COMM_COS_DMA 0x00000080 1037 | 1038 | /* Channel Change Of State flags as bit numbers */ 1039 | #define RCX_COMM_COS_READY_BIT_NO 0 1040 | #define RCX_COMM_COS_RUN_BIT_NO 1 1041 | #define RCX_COMM_COS_BUS_ON_BIT_NO 2 1042 | #define RCX_COMM_COS_CONFIG_LOCKED_BIT_NO 3 1043 | #define RCX_COMM_COS_CONFIG_NEW_BIT_NO 4 1044 | #define RCX_COMM_COS_RESTART_REQUIRED_BIT_NO 5 1045 | #define RCX_COMM_COS_RESTART_REQUIRED_ENABLE_BIT_NO 6 1046 | #define RCX_COMM_COS_DMA_BIT_NO 7 1047 | 1048 | /*===========================================================================*/ 1049 | /* */ 1050 | /* Channel block information */ 1051 | /* */ 1052 | /*===========================================================================*/ 1053 | 1054 | /*****************************************************************************/ 1055 | /*! Block configuration information */ 1056 | /*****************************************************************************/ 1057 | typedef struct NETX_BLOCK_DEFINITIONtag 1058 | { 1059 | uint8_t bChannelNumber; 1060 | uint8_t blBlockNumber; 1061 | uint8_t bBlockID; 1062 | uint8_t bPad; 1063 | uint32_t ulOffset; 1064 | uint32_t ulSize; 1065 | uint16_t usFlags; 1066 | uint16_t usHandshakeMode; 1067 | uint16_t usHandshakePosition; 1068 | uint16_t usReserved; 1069 | } NETX_BLOCK_DEFINITION; 1070 | 1071 | /* Block ID */ 1072 | #define RCX_BLOCK_MASK 0x00FFL 1073 | #define RCX_BLOCK_UNDEFINED 0x0000L 1074 | #define RCX_BLOCK_UNKNOWN 0x0001L 1075 | #define RCX_BLOCK_DATA_IMAGE 0x0002L 1076 | #define RCX_BLOCK_DATA_IMAGE_HI_PRIO 0x0003L 1077 | #define RCX_BLOCK_MAILBOX 0x0004L 1078 | #define RCX_BLOCK_CTRL_PARAM 0x0005L 1079 | #define RCX_BLOCK_COMMON_STATE 0x0006L 1080 | #define RCX_BLOCK_EXTENDED_STATE 0x0007L 1081 | #define RCX_BLOCK_USER 0x0008L 1082 | 1083 | /* Flags definition: Direction */ 1084 | #define RCX_DIRECTION_MASK 0x000F 1085 | #define RCX_DIRECTION_UNDEFINED 0x0000 1086 | #define RCX_DIRECTION_IN 0x0001 1087 | #define RCX_DIRECTION_OUT 0x0002 1088 | #define RCX_DIRECTION_INOUT 0x0003 1089 | 1090 | /* Flags definition: Transmission type */ 1091 | #define RCX_TRANSMISSION_TYPE_MASK 0x00F0 1092 | #define RCX_TRANSMISSION_TYPE_UNDEFINED 0x0000 1093 | #define RCX_TRANSMISSION_TYPE_DPM 0x0010 1094 | #define RCX_TRANSMISSION_TYPE_DMA 0x0020 1095 | 1096 | /* Block definition: I/O Mode */ 1097 | #define RCX_IO_MODE_DEFAULT 0x0000 /*!< I/O mode default, for compability reasons this value is identical to 0x4 (buffered host controlled) */ 1098 | #define RCX_IO_MODE_BUFF_DEV_CTRL 0x0002 /*!< I/O mode buffered device controlled */ 1099 | #define RCX_IO_MODE_UNCONTROLLED 0x0003 /*!< I/O mode bus synchronous device controlled */ 1100 | #define RCX_IO_MODE_BUFF_HST_CTRL 0x0004 /*!< I/O mode buffered host controlled */ 1101 | 1102 | /* Block definition: Synchronization Mode */ 1103 | #define RCX_SYNC_MODE_OFF 0x00 1104 | #define RCX_SYNC_MODE_DEV_CTRL 0x01 1105 | #define RCX_SYNC_MODE_HST_CTRL 0x02 1106 | 1107 | /* Block definition: Synchronization Sources */ 1108 | #define RCX_SYNC_SOURCE_OFF 0x00 1109 | #define RCX_SYNC_SOURCE_1 0x01 1110 | #define RCX_SYNC_SOURCE_2 0x02 1111 | 1112 | 1113 | 1114 | 1115 | /*===========================================================================*/ 1116 | /* */ 1117 | /* */ 1118 | /* */ 1119 | /*===========================================================================*/ 1120 | 1121 | /* Status Information */ 1122 | #define RCX_SI_STATE_SUCCESS 0x0000 1123 | 1124 | /* Fault State */ 1125 | #define RCX_FS_STATE_UNDEFINED 0x0000 1126 | #define RCX_FS_STATE_NO_FAULT 0x0001 1127 | #define RCX_FS_STATE_CONF_ERROR 0x0002 1128 | #define RCX_FS_STATE_RECOVERABLE 0x0003 1129 | #define RCX_FS_STATE_SEVERE 0x0004 1130 | #define RCX_FS_STATE_FATAL 0x0005 1131 | #define RCX_FS_STATE_WATCHDOG 0x0006 1132 | 1133 | /* Network State */ 1134 | #define RCX_COMM_STATE_UNKNOWN 0x0000 1135 | #define RCX_COMM_STATE_NOT_CONFIGURED 0x0001 1136 | #define RCX_COMM_STATE_STOP 0x0002 1137 | #define RCX_COMM_STATE_IDLE 0x0003 1138 | #define RCX_COMM_STATE_OPERATE 0x0004 1139 | 1140 | /* Input / Output data states */ 1141 | #define RCX_IODS_FIELDBUS_MASK 0x00F0 1142 | #define RCX_IODS_DATA_STATE_GOOD 0x0080 1143 | #define RCX_IODS_PROVIDER_RUN 0x0040 1144 | #define RCX_IODS_GENERATED_LOCALLY 0x0020 1145 | 1146 | /* System Reset cookie */ 1147 | #define RCX_SYS_RESET_COOKIE 0x55AA55AA 1148 | #define RCX_SYS_BAD_MEMORY_COOKIE 0x0BAD 1149 | 1150 | /*===========================================================================*/ 1151 | /* */ 1152 | /* RCX Packet Definition */ 1153 | /* */ 1154 | /*===========================================================================*/ 1155 | /* Structure of the RCX packet header */ 1156 | #define RCX_MAX_PACKET_SIZE 1596 /*!< Maximum size of the RCX packet in bytes */ 1157 | #define RCX_PACKET_HEADER_SIZE 40 /*!< Maximum size of the RCX packet header in bytes */ 1158 | #define RCX_MAX_DATA_SIZE (RCX_MAX_PACKET_SIZE - RCX_PACKET_HEADER_SIZE) /* Maximum RCX packet data size */ 1159 | 1160 | #define RCX_MSK_PACKET_ANSWER 0x00000001 /*!< Packet answer bit */ 1161 | 1162 | /* Packet default Destination */ 1163 | #define RCX_SYSTEM_CHANNEL 0xFFFFFFFF 1164 | 1165 | /* Packet destinations */ 1166 | #define RCX_PACKET_DEST_SYSTEM 0 1167 | #define RCX_PACKET_DEST_PORT_0 1 1168 | #define RCX_PACKET_DEST_PORT_1 2 1169 | #define RCX_PACKET_DEST_PORT_2 3 1170 | #define RCX_PACKET_DEST_PORT_3 4 1171 | #define RCX_PACKET_DEST_DEFAULT_CHANNEL 0x00000020 1172 | #define RCX_PKT_COMM_CHANNEL_TOKEN 0x00000020 1173 | 1174 | /* Flags for the packet extension field */ 1175 | /* Sequence numbering */ 1176 | #define RCX_PACKET_SEQ_NR_MASK 0x0000003f /*!< Packet sequence number mask */ 1177 | #define RCX_PACKET_SEQ_MASK 0x000000c0 /*!< Mask for the sequence bits */ 1178 | #define RCX_PACKET_SEQ_NONE 0x00000000 /*!< No packet sequence */ 1179 | #define RCX_PACKET_SEQ_FIRST 0x00000080 /*!< First packet of a sequence */ 1180 | #define RCX_PACKET_SEQ_MIDDLE 0x000000c0 /*!< Packet in a sequence */ 1181 | #define RCX_PACKET_SEQ_LAST 0x00000040 /*!< Last packet of a sequence */ 1182 | 1183 | /* Flag bits */ 1184 | #define RCX_PACKET_RETRY 0x00000200 /*!< Packet will be resent based on retry mechanism defined by e.g. stacks */ 1185 | 1186 | /* Default NO_ERROR packet state */ 1187 | #define RCX_S_OK 0 1188 | 1189 | /* Global packet state errors */ 1190 | #define RCX_E_FAIL 0xC0000001 1191 | #define RCX_E_UNEXPECTED 0xC0000002 1192 | #define RCX_E_OUTOFMEMORY 0xC0000003 1193 | #define RCX_E_UNKNOWN_COMMAND 0xC0000004 1194 | #define RCX_E_UNKNOWN_DESTINATION 0xC0000005 1195 | #define RCX_E_UNKNOWN_DESTINATION_ID 0xC0000006 1196 | #define RCX_E_INVALID_PACKET_LEN 0xC0000007 1197 | #define RCX_E_INVALID_EXTENSION 0xC0000008 1198 | #define RCX_E_INVALID_PARAMETER 0xC0000009 1199 | #define RCX_E_INVALID_ALIGNMENT 0xC000000A 1200 | #define RCX_E_WATCHDOG_TIMEOUT 0xC000000C 1201 | #define RCX_E_INVALID_LIST_TYPE 0xC000000D 1202 | #define RCX_E_UNKNOWN_HANDLE 0xC000000E 1203 | #define RCX_E_PACKET_OUT_OF_SEQ 0xC000000F 1204 | #define RCX_E_PACKET_OUT_OF_MEMORY 0xC0000010 1205 | #define RCX_E_QUE_PACKETDONE 0xC0000011 1206 | #define RCX_E_QUE_SENDPACKET 0xC0000012 1207 | #define RCX_E_POOL_PACKET_GET 0xC0000013 1208 | #define RCX_E_POOL_GET_LOAD 0xC0000015 1209 | #define RCX_E_REQUEST_RUNNING 0xC000001A 1210 | 1211 | /* Global state errors */ 1212 | #define RCX_E_INIT_FAULT 0xC0000100 1213 | #define RCX_E_DATABASE_ACCESS_FAILED 0xC0000101 1214 | #define RCX_E_NOT_CONFIGURED 0xC0000119 1215 | #define RCX_E_CONFIGURATION_FAULT 0xC0000120 1216 | #define RCX_E_INCONSISTENT_DATA_SET 0xC0000121 1217 | #define RCX_E_DATA_SET_MISMATCH 0xC0000122 1218 | #define RCX_E_INSUFFICIENT_LICENSE 0xC0000123 1219 | #define RCX_E_PARAMETER_ERROR 0xC0000124 1220 | #define RCX_E_INVALID_NETWORK_ADDRESS 0xC0000125 1221 | #define RCX_E_NO_SECURITY_MEMORY 0xC0000126 1222 | #define RCX_E_NETWORK_FAULT 0xC0000140 1223 | #define RCX_E_CONNECTION_CLOSED 0xC0000141 1224 | #define RCX_E_CONNECTION_TIMEOUT 0xC0000142 1225 | #define RCX_E_LONELY_NETWORK 0xC0000143 1226 | #define RCX_E_DUPLICATE_NODE 0xC0000144 1227 | #define RCX_E_CABLE_DISCONNECT 0xC0000145 1228 | #define RCX_E_BUS_OFF 0xC0000180 1229 | #define RCX_E_CONFIG_LOCKED 0xC0000181 1230 | #define RCX_E_APPLICATION_NOT_READY 0xC0000182 1231 | 1232 | #define RCX_E_TIMER_APPL_PACKET_SENT 0xC002000C 1233 | 1234 | /* MidSys packet state Error Codes */ 1235 | #define RCX_E_QUE_UNKNOWN 0xC02B0001 1236 | #define RCX_E_QUE_INDEX_UNKNOWN 0xC02B0002 1237 | #define RCX_E_TASK_UNKNOWN 0xC02B0003 1238 | #define RCX_E_TASK_INDEX_UNKNOWN 0xC02B0004 1239 | #define RCX_E_TASK_HANDLE_INVALID 0xC02B0005 1240 | #define RCX_E_TASK_INFO_IDX_UNKNOWN 0xC02B0006 1241 | #define RCX_E_FILE_XFR_TYPE_INVALID 0xC02B0007 1242 | #define RCX_E_FILE_REQUEST_INCORRECT 0xC02B0008 1243 | #define RCX_E_UNKNOWN_PORT_INDEX 0xC02B0009 1244 | #define RCX_E_ROUTER_TABLE_FULL 0xC02B000A 1245 | #define RCX_E_NO_SUCH_ROUTER_IN_TABLE 0xC02B000B 1246 | #define RCX_E_INSTANCE_NOT_NULL 0xC02B000C 1247 | #define RCX_E_COMMAND_INVALID 0xC02B000D 1248 | #define RCX_E_TASK_INVALID 0xC02B000E 1249 | #define RCX_E_TASK_NOT_A_USER_TASK 0xC02B000F 1250 | #define RCX_E_INVALID_FIRMWARE_SIZE 0xC02B001B 1251 | #define RCX_E_SEC_FAILED 0xC02B001D 1252 | #define RCX_E_SEC_DISABLED 0xC02B001E 1253 | #define RCX_E_BLOCK_SIZE_OUT_OF_RANGE 0xC02B0020 1254 | #define RCX_E_INVALID_CHANNEL 0xC02B0021 1255 | #define RCX_E_INVALID_FILE_LENGTH 0xC02B0022 1256 | #define RCX_E_INVALID_CHARACTER 0xC02B0023 1257 | #define RCX_E_PACKET_OUT_OF_SEQUNCE 0xC02B0024 1258 | #define RCX_E_NOT_POSSIBLE_IN_CURRENT_STATE 0xC02B0025 1259 | #define RCX_E_SECURTY_EEPROM_INVALID_ZONE 0xC02B0026 1260 | #define RCX_E_SECURTY_EEPROM_NOT_ALLOWED 0xC02B0027 1261 | #define RCX_E_SECURTY_EEPROM_NOT_AVAILABLE 0xC02B0028 1262 | #define RCX_E_SECURTY_EEPROM_INVALID_CHECKSUM 0xC02B0029 1263 | #define RCX_E_SECURTY_EEPROM_ZONE_NOT_WRITEABLE 0xC02B002A 1264 | #define RCX_E_SECURTY_EEPROM_READ_FAILED 0xC02B002B 1265 | #define RCX_E_SECURTY_EEPROM_WRITE_FAILED 0xC02B002C 1266 | #define RCX_E_SECURTY_EEPROM_ZONE_ACCESS_DENIDED 0xC02B002D 1267 | #define RCX_E_SECURTY_EEPROM_EMULATED 0xC02B002E 1268 | #define RCX_E_FILE_NAME_INVALID 0xC02B002F 1269 | #define RCX_E_FILE_SEQUENCE_ERROR 0xC02B0030 1270 | #define RCX_E_FILE_SEQUENCE_END_ERROR 0xC02B0031 1271 | #define RCX_E_FILE_SEQUENCE_BEGIN_ERROR 0xC02B0032 1272 | #define RCX_E_FILE_UNEXPECTED_BLOCK_SIZE 0xC02B0033 1273 | #define RCX_E_HIL_FILE_HEADER_CRC_ERROR 0xC02B0034 1274 | #define RCX_E_HIL_FILE_HEADER_MODULE_SIZE_DIFFERS 0xC02B0035 1275 | #define RCX_E_HIL_FILE_HEADER_MD5_CHECKSUM_ERROR 0xC02B0036 1276 | #define RCX_E_PACKET_WOULD_BE_TO_LONG_FOR_MTU 0xC02B0037 1277 | #define RCX_E_INVALID_BLOCK 0xC02B0038 1278 | #define RCX_E_INVALID_STRUCT_NUMBER 0xC02B0039 1279 | 1280 | /*****************************************************************************/ 1281 | /*! Default RCX packet header structure */ 1282 | /*****************************************************************************/ 1283 | typedef __RCX_PACKED_PRE struct RCX_PACKET_HEADERtag 1284 | { 1285 | uint32_t ulDest; /*!< 00:04, Destination of packet, process queue */ 1286 | uint32_t ulSrc; /*!< 04:04, Source of packet, process queue */ 1287 | uint32_t ulDestId; /*!< 08:04, Destination reference of packet*/ 1288 | uint32_t ulSrcId; /*!< 12:04, Source reference of packet */ 1289 | uint32_t ulLen; /*!< 16:04, Length of packet data without header */ 1290 | uint32_t ulId; /*!< 20:04, Identification handle of sender */ 1291 | uint32_t ulState; /*!< 24:04, Status code of operation */ 1292 | uint32_t ulCmd; /*!< 28:04, Packet command */ 1293 | uint32_t ulExt; /*!< 32:04, Extension */ 1294 | uint32_t ulRout; /*!< 36:04, Router (internal use only) */ 1295 | } __RCX_PACKED_POST RCX_PACKET_HEADER; 1296 | 1297 | /*****************************************************************************/ 1298 | /*! Default RCX packet structure, including user data */ 1299 | /*****************************************************************************/ 1300 | typedef __RCX_PACKED_PRE struct RCX_PACKETtag 1301 | { 1302 | RCX_PACKET_HEADER tHeader; /*!< Packet header */ 1303 | uint8_t abData[RCX_MAX_DATA_SIZE]; /*!< Packet data */ 1304 | } __RCX_PACKED_POST RCX_PACKET; 1305 | 1306 | /*****************************************************************************/ 1307 | /*! Firmware Identification */ 1308 | /*****************************************************************************/ 1309 | 1310 | typedef __RCX_PACKED_PRE struct tagNETX_FW_VERSION 1311 | { 1312 | uint16_t usMajor; 1313 | uint16_t usMinor; 1314 | uint16_t usBuild; 1315 | uint16_t usRevision; 1316 | } __RCX_PACKED_POST NETX_FW_VERSION; 1317 | 1318 | typedef __RCX_PACKED_PRE struct tagNETX_FW_NAME 1319 | { 1320 | uint8_t bNameLength; 1321 | uint8_t abName[ 63 ]; 1322 | } __RCX_PACKED_POST NETX_FW_NAME; 1323 | 1324 | typedef __RCX_PACKED_PRE struct tagNETX_FW_DATE 1325 | { 1326 | uint16_t usYear; 1327 | uint8_t bMonth; 1328 | uint8_t bDay; 1329 | } __RCX_PACKED_POST NETX_FW_DATE; 1330 | 1331 | typedef __RCX_PACKED_PRE struct tagNETX_FW_IDENTIFICATION 1332 | { 1333 | NETX_FW_VERSION tFwVersion; /* !< firmware version */ 1334 | NETX_FW_NAME tFwName; /* !< firmware name */ 1335 | NETX_FW_DATE tFwDate; /* !< firmware date */ 1336 | } __RCX_PACKED_POST NETX_FW_IDENTIFICATION; 1337 | 1338 | /*****************************************************************************/ 1339 | /*! Hardware name */ 1340 | /*****************************************************************************/ 1341 | 1342 | typedef __RCX_PACKED_PRE struct tagNETX_HW_NAME 1343 | { 1344 | uint8_t bNameLength; 1345 | uint8_t abName[ 63 ]; 1346 | } __RCX_PACKED_POST NETX_HW_NAME; 1347 | 1348 | 1349 | /*---------------------------------------------------------------------------*/ 1350 | /* Compiler settings */ 1351 | #ifdef _MSC_VER 1352 | #if _MSC_VER >= 1000 1353 | #pragma pack() /* Always allign structures to compiler settings */ 1354 | #endif /* _MSC_VER >= 1000 */ 1355 | #endif /* _MSC_VER */ 1356 | /*---------------------------------------------------------------------------*/ 1357 | 1358 | #undef __RCX_PACKED_PRE 1359 | #undef __RCX_PACKED_POST 1360 | 1361 | #endif /* __RCX_USER_H */ 1362 | -------------------------------------------------------------------------------- /driver/netx-docker-pi-drv-2.0.1-r0.deb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HilscherAutomation/netPI-codesys-basis/b5576b2f63b74eef98a6223320d531db2e01e9cd/driver/netx-docker-pi-drv-2.0.1-r0.deb -------------------------------------------------------------------------------- /firmware/netx-docker-pi-pns-eth-3.12.0.8.deb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HilscherAutomation/netPI-codesys-basis/b5576b2f63b74eef98a6223320d531db2e01e9cd/firmware/netx-docker-pi-pns-eth-3.12.0.8.deb -------------------------------------------------------------------------------- /hooks/build: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | echo "Build hook is running" 4 | docker build --build-arg BUILD_DATE=`date -u +"%Y-%m-%dT%H:%M:%SZ"` \ 5 | --build-arg VCS_REF=`git rev-parse --short HEAD` \ 6 | -t $IMAGE_NAME . 7 | 8 | -------------------------------------------------------------------------------- /hooks/post_push: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Use manifest-tool to create the manifest, given the experimental 4 | # "docker manifest" command isn't available yet on Docker Hub. 5 | 6 | curl -Lo manifest-tool https://github.com/estesp/manifest-tool/releases/download/v0.9.0/manifest-tool-linux-amd64 7 | chmod +x manifest-tool 8 | 9 | ./manifest-tool push from-args \ 10 | --platforms linux/arm \ 11 | --template "$IMAGE_NAME" \ 12 | --target "$IMAGE_NAME" 13 | 14 | -------------------------------------------------------------------------------- /hooks/pre_build: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Register qemu-*-static for all supported processors except the 4 | # current one, but also remove all registered binfmt_misc before 5 | docker run --rm --privileged multiarch/qemu-user-static:register --reset 6 | 7 | -------------------------------------------------------------------------------- /init.d/entrypoint.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash +e 2 | 3 | #check if container is running in host mode 4 | if [[ -z `grep "docker0" /proc/net/dev` ]]; then 5 | echo "Container not running in host mode. Sure you configured host network mode? Container stopped." 6 | exit 143 7 | fi 8 | 9 | #check if container is running in privileged mode 10 | ip link add dummy0 type dummy >/dev/null 2>&1 11 | if [[ -z `grep "dummy0" /proc/net/dev` ]]; then 12 | echo "Container not running in privileged mode. Sure you configured privileged mode? Container stopped." 13 | exit 143 14 | else 15 | # clean the dummy0 link 16 | ip link delete dummy0 >/dev/null 2>&1 17 | fi 18 | 19 | if [[ ! -e "/dev/vcio" ]]; then 20 | #reset BCM chip possible 21 | echo "Container access to VideCore GPU not possible. Device /dev/vcio/ is not mapped. Container stopped." 22 | exit 143 23 | fi 24 | 25 | # catch signals as PID 1 in a container 26 | 27 | # SIGNAL-handler 28 | term_handler() { 29 | 30 | #remove cifx0 interface from system if created by the container 31 | if ps -A | grep -q "cifx0daemon" ; then 32 | killall cifx0deamon 33 | ip link delete cifx0 34 | fi 35 | 36 | if [ -f /etc/init.d/edgegateway ] 37 | then 38 | echo "Terminating CODESYS Edge Gateway ..." 39 | /etc/init.d/codesysedge stop 40 | fi 41 | 42 | if [ -f /etc/init.d/codesyscontrol ] 43 | then 44 | echo "Terminating CODESYS Runtime ..." 45 | /etc/init.d/codesyscontrol stop 46 | fi 47 | 48 | 49 | echo "Terminating ssh ..." 50 | /etc/init.d/ssh stop 51 | 52 | exit 143; # 128 + 15 -- SIGTERM 53 | } 54 | 55 | # on callback, stop all started processes in term_handler 56 | trap 'kill ${!}; term_handler' SIGINT SIGKILL SIGTERM SIGQUIT SIGTSTP SIGSTOP SIGHUP 57 | 58 | #resolve HOST just in case 59 | if ! ( grep -q "127.0.0.1 localhost localhost.localdomain ${HOSTNAME}" /etc/hosts > /dev/null); 60 | then 61 | echo "127.0.0.1 localhost localhost.localdomain ${HOSTNAME}" >> /etc/hosts 62 | fi 63 | 64 | #check presence of device spi0.0 and net device register 65 | if [[ -e "/dev/spidev0.0" ]]&& [[ -e "/dev/net/tun" ]]; then 66 | 67 | #check if cifx0 interface is not running already 68 | if ! ip addr show | grep -q "cifx0" ; then 69 | 70 | echo "cifx0 hardware support (TCP/IP over RTE LAN ports) configured." 71 | 72 | #pre-configure GPIO 24 to serve as interrupt pin between netX chip and BCM CPU 73 | if [[ ! -e "/sys/class/gpio/gpio24" ]]; then 74 | echo 24 > /sys/class/gpio/export 75 | fi 76 | echo rising > /sys/class/gpio/gpio24/edge 77 | echo in > /sys/class/gpio/gpio24/direction 78 | echo 1 > /sys/class/gpio/gpio24/active_low 79 | 80 | # create netx "cifx0" ethernet network interface 81 | /opt/cifx/cifx0daemon 82 | 83 | # bring interface up first of all 84 | ip link set cifx0 up 85 | 86 | fi 87 | else 88 | echo "cifx0 hardware support (TCP/IP over RTE LAN ports) not configured." 89 | fi 90 | 91 | 92 | # run applications in the background 93 | echo "starting SSH server ..." 94 | if [ "SSHPORT" ]; then 95 | #there is an alternative SSH port configured 96 | echo "the container binds the SSH server port to the configured port $SSHPORT" 97 | sed -i -e "s;#Port 22;Port $SSHPORT;" /etc/ssh/sshd_config 98 | else 99 | echo "the container binds the SSH server port to the default port 22" 100 | fi 101 | /etc/init.d/ssh start & 102 | 103 | if [ -f /etc/init.d/codesyscontrol ] 104 | then 105 | echo "Starting CODESYS Runtime ..." 106 | /etc/init.d/codesyscontrol start & 107 | else 108 | echo "CODESYS runtime not installed. Download from here https://store.codesys.com/codesys-control-for-raspberry-pi-sl.html and install via CODESYS Development System." 109 | fi 110 | 111 | if [ -f /etc/init.d/codesysedge ] 112 | then 113 | echo "Starting CODESYS Edge Gateway ..." 114 | /etc/init.d/codesysedge start >/dev/null & 115 | else 116 | echo "CODESYS Edge Gateway not installed. Download from here https://store.codesys.com/codesys-edge-gateway.html and install via CODESYS Development System." 117 | fi 118 | 119 | # wait forever not to exit the container 120 | while true 121 | do 122 | tail -f /dev/null & wait ${!} 123 | done 124 | 125 | exit 0 126 | --------------------------------------------------------------------------------