├── InputFiles ├── fir_bin.dat └── input_mic8.dat ├── LICENSE ├── Pictures ├── Comb_Filter.png ├── FPGA_File_Structure.png ├── FPGA_TestBench_Structure.png ├── Integrator_Filter.png ├── ODAS_Matrix_Creator.gif ├── Validation_TestBench.png ├── cic_op_fsm_1.png ├── cic_sync_1.png ├── cic_sync_2.png ├── cic_sync_3.png ├── fir_pipe_fsm_1.png ├── fir_pipe_fsm_2.png ├── fir_pipe_fsm_3.png ├── fir_pipe_fsm_4.png ├── mic_fir_1.png ├── mic_fir_2.png ├── mic_fir_3.png ├── mic_fir_4.png └── mic_fir_5.png ├── Postprocessing_Python └── output_mic8.dat ├── README.md └── VerilogFiles ├── Mic_Array_TB.v ├── cic.v ├── cic_comb.v ├── cic_int.v ├── cic_op_fsm.v ├── cic_sync.v ├── fir_data.v ├── fir_pipe_fsm.v ├── mic_array_buffer.v ├── mic_fir.v └── pdm_data.v /InputFiles/fir_bin.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Hoi-Jeon/Verilog-for-Mic-in-Matrix-Creator/HEAD/InputFiles/fir_bin.dat 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