├── AMBAAXI3BUSPPT_.pdf ├── AXI_Questa ├── MasterSlaveAxiInterface.sv ├── Master_Axi3Protocol.sv ├── Simulation Result.jpg ├── Slave_Axi3Protocol.sv ├── Top_HDL.sv ├── Top_HVL.sv ├── VE.sv ├── assertions.sv ├── driver.sv ├── monitor.sv ├── run.do └── testcase.sv ├── Emulation ├── Makefile ├── MasterSlaveAxiInterface.sv ├── Master_Axi3Protocol.sv ├── Screenshot (14).png ├── Screenshot (15).png ├── Screenshot (16).png ├── Slave_Axi3Protocol.sv ├── Top_HDL.sv ├── run.do ├── veloce.config └── view.do └── README_AXI.txt /AMBAAXI3BUSPPT_.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HunterBitos/Implementation-of-AMBA-AXI3-protocol/cf3431683f6e2a583cfffcf62b15e4e2a9147b62/AMBAAXI3BUSPPT_.pdf -------------------------------------------------------------------------------- /AXI_Questa/MasterSlaveAxiInterface.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////// 2 | //Interface 'axi'- For creating modports for Slave and Master. 3 | // 4 | ////controls signals for the 5 channels -Write address channel, write data channel, write response channel, Read address channel, Read data Channel(contains response too) 5 | // 6 | ///////////////////////////////////////////////////////// 7 | // 8 | interface axi#(parameter DATAWIDTH=32, SIZE=3); 9 | 10 | // Control signals 11 | logic AWREADY, AWVALID,RLAST, WREADY,WVALID,WLAST,BVALID,BREADY,ARREADY,ARVALID,RVALID,RREADY; //handshaking signals valid, ready for all the write & read address ,data ,response channels, last signal 12 | logic [SIZE-2:0] AWBURST,BRESP,ARBURST,RRESP; // Write Burst type, Write Response, Read Burst type, Read response signals 13 | logic [(DATAWIDTH/8)-1:0] AWLEN ,AWID,WSTRB, WID,BID,ARID,ARLEN,RID; // control info for number of transfers, ids, strobe signals 14 | logic [DATAWIDTH:0] WDATA; // write data 15 | logic [DATAWIDTH-1:0] ARADDR,RDATA,AWADDR; //read address, read data, write address signals 16 | logic [SIZE-1:0] ARSIZE,AWSIZE; //transfer size for read write transactions 17 | 18 | //Slave Modport 19 | modport Slave( 20 | 21 | output WREADY, //write ready signal from slave 22 | input WVALID, //valid signal for write 23 | input WLAST, //write last signal 24 | input WSTRB, // strobe signal for writing in 25 | input WDATA, //write data 26 | input WID, //write data id 27 | output BID, //response id 28 | output BRESP, //write response signal from slave 29 | output BVALID, //write response valid signal 30 | input BREADY, //write response ready signal 31 | output AWREADY, //write address ready signal from slave 32 | input AWVALID, // write address valid signal 33 | input AWBURST, //write address channel signal for burst type 34 | input AWSIZE, //size of each transfer in bytes(encoded) 35 | input AWLEN, //burst length- number of transfers in a burst 36 | input AWADDR, //write address signal 37 | input AWID, // write address id 38 | output ARREADY, //read address ready signal from slave 39 | input ARID, //read address id 40 | input ARADDR, //read address signal 41 | input ARLEN, //length of the burst 42 | input ARSIZE, //number of bytes in a transfer 43 | input ARBURST, //burst type - fixed, incremental, wrapping 44 | input ARVALID, //address read valid signal 45 | output RID, //read data id 46 | output RDATA, //read data from slave 47 | output RRESP, //read response signal 48 | output RLAST, //read data last signal 49 | output RVALID, //read data valid signal 50 | input RREADY //read ready signal 51 | ); 52 | 53 | //Master modport 54 | modport Master( 55 | 56 | 57 | input AWREADY, ////////////////////////////////////inputs to the Master 58 | input BID, // 59 | input BRESP, // 60 | input BVALID, // 61 | input WREADY, // 62 | input ARREADY, // 63 | input RID, // ready, id , response,read data signals to the master for various channels 64 | input RDATA, // 65 | input RRESP, // 66 | input RLAST, // 67 | input RVALID, /////////////////////////////// 68 | output AWVALID, // write address valid signal from Master 69 | output AWBURST, // 70 | output AWSIZE, // 71 | output AWLEN, // 72 | output AWADDR, // signals specifying the length of a burst , size of each transfer, id, valid, last, strobe etc. for various- write & read address ,data, response channels 73 | output AWID, // 74 | output WVALID, // 75 | output WLAST, // 76 | output WSTRB, // 77 | output WDATA, // write data from Master 78 | output WID, // 79 | output BREADY, // 80 | output ARID, // 81 | output ARADDR, // 82 | output ARLEN, // 83 | output ARSIZE, // 84 | output ARBURST, // 85 | output ARVALID, // 86 | output RREADY //////////////////////// 87 | ); 88 | 89 | 90 | endinterface -------------------------------------------------------------------------------- /AXI_Questa/Master_Axi3Protocol.sv: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////// 2 | //Module for the Axi3 interconnect protocol behaviour with various response signals from Master's channels- 3 | // 1.Write address channel 2.Write Data Channel 3. Write Response channel 4. Read Address channel 5.Read Data Channel 4 | //Implementing the Axi3 protocol while interfacing with Master 5 | //Master<->AXI fsm's 6 | // 7 | /////////////////////////////////////////////////////////// 8 | module Master_Axi3Protocol #(parameter DATAWIDTH, SIZE) 9 | ( 10 | input clock, reset, 11 | axi.Master AMBA, //instantiating the Master's Modport from the Interface module 'axi' created in the file 'MasterSlaveAxiInterface.sv' 12 | 13 | 14 | input logic [DATAWIDTH-1:0] AWaddr, ///////////////////////////////// 15 | input logic [(DATAWIDTH/8)-1:0] AWlen, // 16 | input logic [DATAWIDTH-1:0] WData, // 17 | input logic [(DATAWIDTH/8)-1:0] AWid, // 18 | input logic [(DATAWIDTH/8)-1:0] WStrb, // 19 | input logic [(DATAWIDTH/8)-1:0] ARid, ///////CAMEL CASE LETTERS- indicating the Axi3 interconnecting signals to from Master 20 | input logic [(DATAWIDTH/8)-1:0] ARlen, // 21 | input logic [SIZE-1:0] AWsize, // 22 | input logic [SIZE-2:0] AWburst, // 23 | input logic [DATAWIDTH-1:0] ARaddr, // 24 | input logic [SIZE-1:0] ARsize, // 25 | input logic [SIZE-2:0] ARburst, /////////////////////////////////// 26 | output logic [4095:0] [7:0] read_memory); //creating a 2D memory array at the axi-> master side for storing the read data recieved by the master from slave . 27 | 28 | 29 | 30 | ////////////////////////////////////////////////////////Channels \\\\\\\\\\\\\\\\\\\\\\\\\\\///////////////////// 31 | // 32 | //Master -Write address channel states 33 | enum logic [1:0] { 34 | MWRITE_IDLE=2'b00, 35 | MWRITE_START, 36 | MWRITE_WAIT, 37 | MWRITE_VALID } MAWRITEState, MAWRITENext_state; 38 | 39 | // Master - Write data Channel states 40 | logic [4:0] Count, NextCount; 41 | enum logic [2:0] {MWRITE_INIT=3'b000, 42 | MWRITE_TRANSFER, 43 | MWRITE_READY, 44 | MDWRITE_VALID, 45 | MWRITE_ERROR} MWRITEState, MWRITENext_state; 46 | 47 | //Master- Write Response Channel states 48 | enum logic [1:0] { MASTERB_IDLE=2'b00, 49 | MASTERB_START, 50 | MASTERB_READY } MASTERBState, MASTERBNext_state; 51 | 52 | 53 | //Master-Read Address Channel states 54 | enum logic [2:0] {MREAD_IDLE=3'b000, 55 | MREAD_WAIT, 56 | MREAD_READY, 57 | MREAD_VALID, 58 | MREAD_EXTRA} ARMREADState,ARMREADNext_state; 59 | 60 | 61 | // Master -Read Data Channel States 62 | logic [31:0] slaveaddress, 63 | slaveaddress_r, 64 | slaveaddress_temp, 65 | ARADDR_r; 66 | 67 | enum logic [1:0] {MREAD_CLEAR=2'b00, 68 | MREAD_STARTM, 69 | MREAD_READ, 70 | MDREAD_VALID } MREADState,MREADNext_state; 71 | integer wrap_boundary,first_time1, first_time1_next; 72 | 73 | /////////////////////////////////////////////////////////////////////////////FSMs Master channels with Axi Protocol implementing\\\\\\\\\\\\\\////////////////////// 74 | ///////////Assigning each channel w.r.t Axi interconnect signals(in Camel case) to the Master's output ports. 75 | ///////////////////////////FSM for - Write Address Channel Master\\\\\\\\\\\\\\\\\\\\\/////////////// 76 | always_ff @(posedge clock or negedge reset) 77 | begin 78 | if(!reset) begin 79 | MAWRITEState <= MWRITE_IDLE; 80 | end 81 | else begin 82 | MAWRITEState <= MAWRITENext_state; 83 | end 84 | end 85 | 86 | always_comb 87 | begin 88 | case(MAWRITEState) 89 | MWRITE_IDLE:begin 90 | AMBA.AWVALID = '0; 91 | AMBA.AWBURST = '0; 92 | AMBA.AWSIZE = '0; 93 | AMBA.AWLEN = '0; 94 | AMBA.AWADDR = '0; 95 | AMBA.AWID = '0; 96 | MAWRITENext_state = MWRITE_START; 97 | end 98 | 99 | MWRITE_START:begin 100 | if(AWaddr > 32'h0) begin 101 | AMBA.AWBURST = AWburst; 102 | AMBA.AWSIZE = AWsize; 103 | AMBA.AWLEN = AWlen; 104 | AMBA.AWADDR = AWaddr; 105 | AMBA.AWID = AWid; 106 | AMBA.AWVALID = 1'b1; 107 | MAWRITENext_state = MWRITE_WAIT; 108 | end 109 | else 110 | MAWRITENext_state = MWRITE_IDLE; 111 | end 112 | 113 | MWRITE_WAIT:begin 114 | if (AMBA.AWREADY) 115 | MAWRITENext_state = MWRITE_VALID; 116 | else 117 | MAWRITENext_state = MWRITE_WAIT; 118 | end 119 | 120 | MWRITE_VALID:begin 121 | AMBA.AWVALID = '0; 122 | if(AMBA.BREADY) 123 | MAWRITENext_state = MWRITE_IDLE; 124 | else 125 | MAWRITENext_state = MWRITE_VALID; 126 | end 127 | endcase 128 | end 129 | 130 | 131 | 132 | /////////////////////////////////////////FSM for Write Data Channel of Master\\\\\\\\\\\\\///////////////////////////////////// 133 | 134 | always_ff @(posedge clock or negedge reset) 135 | begin 136 | if(!reset) 137 | begin 138 | MWRITEState <= MWRITE_INIT; 139 | Count <= 4'b0; 140 | end 141 | else 142 | begin 143 | MWRITEState <= MWRITENext_state; 144 | Count <= NextCount; 145 | end 146 | end 147 | 148 | always_comb 149 | begin 150 | case(MWRITEState) 151 | 152 | MWRITE_INIT:begin 153 | AMBA.WID = '0; 154 | AMBA.WDATA = '0; 155 | AMBA.WSTRB = '0; 156 | AMBA.WLAST = '0; 157 | AMBA.WVALID = '0; 158 | NextCount = '0; 159 | if(AMBA.AWREADY == 1) MWRITENext_state = MWRITE_TRANSFER; 160 | else MWRITENext_state = MWRITE_INIT; 161 | end 162 | 163 | MWRITE_TRANSFER:begin 164 | if(AWaddr > 32'h5ff && AWaddr <=32'hfff && AWsize <3'b100) 165 | begin 166 | AMBA.WID = AMBA.AWID; 167 | AMBA.WVALID = '1; 168 | AMBA.WSTRB = WStrb; 169 | AMBA.WDATA = WData; 170 | NextCount = Count + 4'b1; 171 | MWRITENext_state = MWRITE_READY; 172 | end 173 | else begin 174 | NextCount = Count + 4'b1; 175 | MWRITENext_state = MWRITE_ERROR; 176 | end 177 | end 178 | 179 | MWRITE_READY:begin 180 | if(AMBA.WREADY) begin 181 | if(NextCount == (AWlen+1)) AMBA.WLAST = 1'b1; 182 | else AMBA.WLAST = 1'b0; 183 | 184 | MWRITENext_state = MDWRITE_VALID; 185 | end 186 | else MWRITENext_state = MWRITE_READY; 187 | end 188 | 189 | MDWRITE_VALID:begin 190 | AMBA.WVALID = '0; 191 | 192 | if(NextCount == AWlen+1) begin 193 | MWRITENext_state = MWRITE_INIT; 194 | AMBA.WLAST='0; 195 | end 196 | else MWRITENext_state = MWRITE_TRANSFER; 197 | end 198 | 199 | MWRITE_ERROR:begin 200 | if(NextCount == (AWlen+1)) begin 201 | AMBA.WLAST = 1'b1; 202 | MWRITENext_state = MDWRITE_VALID; 203 | end 204 | else begin 205 | AMBA.WLAST = 1'b0; 206 | MWRITENext_state = MWRITE_TRANSFER; 207 | end 208 | end 209 | endcase 210 | end 211 | 212 | ///////////////////////////////////////FSM for Write Response Channel of Master\\\\\\\\\\\\\\\\\\\\\\\//////////// 213 | 214 | always_ff @(posedge clock or negedge reset) begin 215 | if(!reset) begin 216 | MASTERBState <= MASTERB_IDLE; 217 | end 218 | else 219 | MASTERBState <= MASTERBNext_state; 220 | end 221 | 222 | always_comb begin 223 | 224 | case(MASTERBState) 225 | 226 | MASTERB_IDLE:begin 227 | AMBA.BREADY = '0; 228 | MASTERBNext_state = MASTERB_START; 229 | end 230 | 231 | MASTERB_START:begin 232 | if(AMBA.BVALID) begin 233 | MASTERBNext_state = MASTERB_READY; 234 | end 235 | end 236 | 237 | MASTERB_READY:begin 238 | AMBA.BREADY = 1'b1; 239 | MASTERBNext_state = MASTERB_IDLE; 240 | end 241 | endcase 242 | end 243 | 244 | 245 | 246 | //////////////////////////////////////////////FSM for Read Address Channel of Master \\\\\\\\\\\\\\\\\\\\\\\/////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\// 247 | 248 | 249 | always_ff @(posedge clock or negedge reset) 250 | begin 251 | if (!reset) begin 252 | ARMREADState <= MREAD_IDLE; 253 | end 254 | else begin 255 | ARMREADState <= ARMREADNext_state; 256 | end 257 | 258 | end 259 | 260 | 261 | always_comb 262 | begin 263 | case (ARMREADState) 264 | MREAD_IDLE:begin 265 | AMBA.ARID = 0; 266 | AMBA.ARADDR = 0; 267 | AMBA.ARLEN = 0; 268 | AMBA.ARSIZE = 0; 269 | AMBA.ARBURST = 0; 270 | AMBA.ARVALID = 0; 271 | ARMREADNext_state = MREAD_WAIT; 272 | end 273 | 274 | MREAD_WAIT:begin 275 | if(ARaddr > 32'h0) begin 276 | AMBA.ARID = ARid; 277 | AMBA.ARADDR = ARaddr; 278 | AMBA.ARLEN = ARlen; 279 | AMBA.ARSIZE = ARsize; 280 | AMBA.ARBURST = ARburst; 281 | AMBA.ARVALID = 1'b1; 282 | ARMREADNext_state = MREAD_READY; 283 | end 284 | else 285 | ARMREADNext_state = MREAD_IDLE; 286 | end 287 | 288 | MREAD_READY:begin 289 | if (AMBA.ARREADY) 290 | ARMREADNext_state = MREAD_VALID; 291 | else 292 | ARMREADNext_state = MREAD_READY; 293 | end 294 | 295 | MREAD_VALID:begin 296 | AMBA.ARVALID = '0; 297 | if(AMBA.RLAST) 298 | ARMREADNext_state = MREAD_EXTRA; 299 | else 300 | ARMREADNext_state = MREAD_VALID; 301 | end 302 | 303 | MREAD_EXTRA:begin 304 | ARMREADNext_state = MREAD_IDLE; 305 | end 306 | endcase 307 | end 308 | 309 | 310 | ////////////////////////////////////////////////////////////////FSM for Read Data Channel of Master\\\\\\\\\\\\\\\\\\\\\\\\\\//////////////////// 311 | 312 | 313 | always_ff @(posedge clock or negedge reset) 314 | begin 315 | if(!reset) 316 | MREADState <= MREAD_CLEAR; 317 | else begin 318 | MREADState <= MREADNext_state; 319 | first_time1 <= first_time1_next; 320 | end 321 | end 322 | 323 | always_comb 324 | begin 325 | if(AMBA.ARREADY) 326 | ARADDR_r = ARaddr; 327 | 328 | case(MREADState) 329 | MREAD_CLEAR:begin 330 | MREADNext_state = MREAD_STARTM; 331 | AMBA.RREADY = '0; 332 | first_time1_next = 0; 333 | slaveaddress = '0; 334 | slaveaddress_r='0; 335 | end 336 | 337 | MREAD_STARTM:begin 338 | if(AMBA.RVALID) begin 339 | MREADNext_state = MREAD_READ; 340 | slaveaddress = slaveaddress_r; 341 | end 342 | else 343 | MREADNext_state = MREAD_STARTM; 344 | end 345 | 346 | MREAD_READ:begin 347 | MREADNext_state = MDREAD_VALID; 348 | AMBA.RREADY= '1; 349 | 350 | case(ARburst) ///Burst type - Fixed(00), Increment(01), Wrapping(10) 351 | 2'b00:begin //fixed 352 | slaveaddress = ARADDR_r; 353 | case (ARsize) 354 | 3'b000: begin 355 | read_memory[slaveaddress] = AMBA.RDATA[7:0]; 356 | end 357 | 3'b001: begin 358 | read_memory[slaveaddress] = AMBA.RDATA[7:0]; 359 | read_memory[slaveaddress+1] = AMBA.RDATA[15:8]; 360 | end 361 | 3'b010: begin 362 | read_memory[slaveaddress] = AMBA.RDATA[7:0]; 363 | read_memory[slaveaddress+1] = AMBA.RDATA[15:8]; 364 | read_memory[slaveaddress+2] = AMBA.RDATA[23:16]; 365 | read_memory[slaveaddress+3] = AMBA.RDATA[31:24]; 366 | end 367 | endcase 368 | end 369 | 370 | 2'b01:begin ///Increment 371 | if(first_time1 == 0) begin 372 | slaveaddress = ARADDR_r; 373 | first_time1_next = 1; 374 | end 375 | else 376 | first_time1_next = first_time1; 377 | 378 | if(AMBA.RLAST == 1) 379 | first_time1_next = 0; 380 | else 381 | first_time1_next = first_time1; 382 | 383 | case (ARsize) 384 | 3'b000: begin 385 | read_memory[slaveaddress] = AMBA.RDATA[7:0]; 386 | end 387 | 3'b001: begin 388 | read_memory[slaveaddress] = AMBA.RDATA[7:0]; 389 | read_memory[slaveaddress+1] = AMBA.RDATA[15:8]; 390 | slaveaddress_r = slaveaddress + 2; 391 | end 392 | 3'b010: begin 393 | read_memory[slaveaddress] = AMBA.RDATA[7:0]; 394 | read_memory[slaveaddress+1] = AMBA.RDATA[15:8]; 395 | read_memory[slaveaddress+2] = AMBA.RDATA[23:16]; 396 | read_memory[slaveaddress+3] = AMBA.RDATA[31:24]; 397 | slaveaddress_r = slaveaddress + 4; 398 | end 399 | endcase 400 | end 401 | 2'b10:begin //Wrapping type 402 | if(first_time1 == 0) begin 403 | slaveaddress = ARADDR_r; 404 | first_time1_next = 1; 405 | end 406 | else 407 | first_time1_next = first_time1; 408 | 409 | if(AMBA.RLAST == 1) 410 | first_time1_next = 0; 411 | else 412 | first_time1_next = first_time1; 413 | 414 | case(ARlen) ///////////////Calculating the Wrapping Boundary based on the Length of the Burst and size of each transfer inside a burst. 415 | 4'b0001:begin ///ARlen signal encoded as a 4bit vector each specifying a number of transfers in a burst 416 | case(ARsize) /////////////////ARsize signal specifies Size of each transfer in bytes and encoded as a 3 bit vector with maximum data width constraints (Max 4bytes used here in the design) 417 | 3'b000: begin 418 | wrap_boundary = 2 * 1; 419 | end 420 | 3'b001: begin 421 | wrap_boundary = 2 * 2; 422 | end 423 | 3'b010: begin 424 | wrap_boundary = 2 * 4; 425 | end 426 | endcase 427 | end 428 | 429 | 4'b0011: begin 430 | case(ARsize) 431 | 3'b000: begin 432 | wrap_boundary = 4 * 1; 433 | end 434 | 3'b001: begin 435 | wrap_boundary = 4 * 2; 436 | end 437 | 3'b010: begin 438 | wrap_boundary = 4 * 4; 439 | end 440 | endcase 441 | end 442 | 443 | 4'b0111:begin 444 | case(ARsize) 445 | 3'b000: begin 446 | wrap_boundary = 8 * 1; 447 | end 448 | 3'b001: begin 449 | wrap_boundary = 8 * 2; 450 | end 451 | 3'b010: begin 452 | wrap_boundary = 8 * 4; 453 | end 454 | endcase 455 | end 456 | 457 | 4'b1111: begin 458 | case(ARsize) 459 | 3'b000: begin 460 | wrap_boundary = 16 * 1; 461 | end 462 | 3'b001: begin 463 | wrap_boundary = 16 * 2; 464 | end 465 | 3'b010: begin 466 | wrap_boundary = 16 * 4; 467 | end 468 | endcase 469 | end 470 | endcase 471 | 472 | case(ARsize) 473 | 3'b000: begin 474 | read_memory[slaveaddress] = AMBA.RDATA[7:0]; 475 | slaveaddress_temp = slaveaddress + 1; 476 | 477 | if(slaveaddress_temp % wrap_boundary == 0) 478 | slaveaddress_r = slaveaddress_temp - wrap_boundary; 479 | else 480 | slaveaddress_r = slaveaddress_temp; 481 | end 482 | 483 | 3'b001: begin 484 | read_memory[slaveaddress] = AMBA.RDATA[7:0]; 485 | slaveaddress_temp = slaveaddress + 1; 486 | 487 | if(slaveaddress_temp % wrap_boundary == 0) 488 | slaveaddress_r = slaveaddress_temp - wrap_boundary; 489 | else 490 | slaveaddress_r = slaveaddress_temp; 491 | 492 | read_memory[slaveaddress_r] = AMBA.RDATA[15:8]; 493 | slaveaddress_temp = slaveaddress_r + 1; 494 | 495 | if(slaveaddress_temp % wrap_boundary == 0) 496 | slaveaddress_r = slaveaddress_temp - wrap_boundary; 497 | else 498 | slaveaddress_r = slaveaddress_temp; 499 | end 500 | 501 | 3'b010: begin 502 | read_memory[slaveaddress] = AMBA.RDATA[7:0]; 503 | slaveaddress_temp = slaveaddress + 1; 504 | 505 | if(slaveaddress_temp % wrap_boundary == 0) 506 | slaveaddress_r = slaveaddress_temp - wrap_boundary; 507 | else 508 | slaveaddress_r = slaveaddress_temp; 509 | 510 | read_memory[slaveaddress_r] = AMBA.RDATA[15:8]; 511 | slaveaddress_temp = slaveaddress_r + 1; 512 | 513 | if(slaveaddress_temp % wrap_boundary == 0) 514 | slaveaddress_r = slaveaddress_temp - wrap_boundary; 515 | else 516 | slaveaddress_r = slaveaddress_temp; 517 | 518 | read_memory[slaveaddress_r] = AMBA.RDATA[23:16]; 519 | slaveaddress_temp = slaveaddress_r + 1; 520 | 521 | if(slaveaddress_temp % wrap_boundary == 0) 522 | slaveaddress_r = slaveaddress_temp - wrap_boundary; 523 | else 524 | slaveaddress_r = slaveaddress_temp; 525 | 526 | read_memory[slaveaddress_r] = AMBA.RDATA[31:24]; 527 | slaveaddress_temp = slaveaddress_r + 1; 528 | 529 | if(slaveaddress_temp % wrap_boundary == 0) 530 | slaveaddress_r = slaveaddress_temp - wrap_boundary; 531 | else 532 | slaveaddress_r = slaveaddress_temp; 533 | end 534 | endcase 535 | end 536 | 537 | 538 | endcase 539 | end 540 | 541 | MDREAD_VALID:begin 542 | AMBA.RREADY = 1'b0; 543 | if(AMBA.RLAST) begin 544 | $display("MASTER Memory= %p",read_memory); 545 | MREADNext_state = MREAD_CLEAR; 546 | end 547 | else 548 | MREADNext_state = MREAD_STARTM; 549 | end 550 | endcase 551 | end 552 | endmodule -------------------------------------------------------------------------------- /AXI_Questa/Simulation Result.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HunterBitos/Implementation-of-AMBA-AXI3-protocol/cf3431683f6e2a583cfffcf62b15e4e2a9147b62/AXI_Questa/Simulation Result.jpg -------------------------------------------------------------------------------- /AXI_Questa/Slave_Axi3Protocol.sv: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////// 2 | //Module for the Axi3 interconnect protocol behaviour with various response signals from Slave's channels- 3 | // 1.Write address channel 2.Write Data Channel 3. Write Response channel 4. Read Address channel 5.Read Data Channel 4 | //Implementing the Axi3 protocol while interfacing with Slave 5 | //Slave<->AXI fsm's 6 | // 7 | /////////////////////////////////////////////////////////// 8 | module Slave_Axi3Protocol( 9 | input clock, reset, 10 | axi.Slave AMBAS, 11 | 12 | output logic [4095:0] [7:0] slave_memory); 13 | 14 | //////////////////////enums for the states\\\\\\\\\\\\\\// 15 | //Write address channel for Slave/// 16 | enum logic [1:0] { 17 | WSLAVE_IDLE=2'b00, 18 | WSLAVE_START, 19 | WSLAVE_READY } WRITEADDR_STATE, WRITEADDR_NEXTSTATE; 20 | 21 | 22 | ////////////Write Data Channel for slave\\\ 23 | logic [31:0] AWADDR_r; 24 | integer first_time, first_time_next2,wrap_boundary; 25 | logic [31:0] masteraddress, masteraddress_reg, masteraddress_temp; 26 | enum logic [1:0]{ 27 | WSLAVE_INIT=2'b00, 28 | WDSLAVE_START, 29 | WDSLAVE_READY, 30 | WDSLAVE_VALID} WRITED_STATE, WRITED_NEXTSTATE; 31 | 32 | /////////////////Write Response Channel for slave 33 | enum logic [2:0] { 34 | RESPONSEB_IDLE=3'b000, 35 | RESPONSEB_LAST, 36 | RESPONSEB_START, 37 | RESPONSEB_WAIT, 38 | RESPONSEB_VALID } SLAVEB_STATE, SLAVEB_NEXTSTATE; 39 | 40 | 41 | /////////////////Read Address Channel for Slave// 42 | enum logic [1:0] { 43 | RSLAVE_IDLE=2'b00, 44 | RSLAVE_WAIT, 45 | RSLAVE_READY} RSLAVE_STATE,RSLAVE_NEXTSTATE; 46 | 47 | //////////////////Read Data Channel for Slave// 48 | enum logic [2:0] { 49 | RDSLAVE_CLEAR=3'b000, 50 | RDSLAVE_START, 51 | RDSLAVE_WAIT, 52 | RDSLAVE_VALID, 53 | RDSLAVE_ERROR } RDSLAVE_STATE, RDSLAVE_NEXTSTATE; 54 | integer first_time2, first_time2_next,wrap_boundary2; 55 | logic [4:0] Counter, Next_Counter; 56 | logic [31:0] ARADDR_r1, readdata_address,readdata_address_r, readdata_address_temp; 57 | 58 | 59 | /////////////////////////////////////////////////////////////////////////////FSMs Slave channels with Axi Protocol implementing\\\\\\\\\\\\\\////////////////////// 60 | ///////////Assigning each channel w.r.t Axi interconnect signals(in Camel case) to the Slave's output ports. 61 | ///////////////////////////FSM for - Write Address Channel Slave\\\\\\\\\\\\\\\\\\\\\/////////////// 62 | 63 | always_ff @(posedge clock or negedge reset) 64 | begin 65 | if(!reset) begin 66 | WRITEADDR_STATE <= WSLAVE_IDLE; 67 | end 68 | else begin 69 | WRITEADDR_STATE <= WRITEADDR_NEXTSTATE; 70 | end 71 | end 72 | 73 | 74 | always_comb 75 | begin 76 | case(WRITEADDR_STATE) 77 | WSLAVE_IDLE:begin 78 | AMBAS.AWREADY = '0; 79 | WRITEADDR_NEXTSTATE = WSLAVE_START; 80 | end 81 | 82 | WSLAVE_START:begin 83 | if(AMBAS.AWVALID) begin 84 | WRITEADDR_NEXTSTATE = WSLAVE_READY; 85 | end 86 | else 87 | WRITEADDR_NEXTSTATE = WSLAVE_START; 88 | end 89 | 90 | WSLAVE_READY:begin 91 | AMBAS.AWREADY = 1'b1; 92 | WRITEADDR_NEXTSTATE = WSLAVE_IDLE; 93 | end 94 | endcase 95 | end 96 | 97 | 98 | /////////////////////////////////////////FSM for Write Data Channel of Slave \\\\\\\\\\\\\///////////////////////////////////// 99 | 100 | 101 | always_ff @(posedge clock or negedge reset) 102 | begin 103 | if(!reset) begin 104 | WRITED_STATE <= WSLAVE_INIT; 105 | end 106 | else begin 107 | WRITED_STATE <= WRITED_NEXTSTATE; 108 | first_time <= first_time_next2; 109 | end 110 | end 111 | 112 | always_comb 113 | begin 114 | if(AMBAS.AWVALID == 1) 115 | AWADDR_r = AMBAS.AWADDR; 116 | 117 | case(WRITED_STATE) 118 | WSLAVE_INIT:begin 119 | AMBAS.WREADY = 1'b0; 120 | WRITED_NEXTSTATE = WDSLAVE_START; 121 | first_time_next2 = 0; 122 | masteraddress_reg = '0; 123 | masteraddress = '0; 124 | end 125 | 126 | WDSLAVE_START:begin 127 | if(AMBAS.WVALID) begin 128 | WRITED_NEXTSTATE = WDSLAVE_READY; 129 | masteraddress = masteraddress_reg; 130 | end 131 | else begin 132 | WRITED_NEXTSTATE = WDSLAVE_START; 133 | end 134 | end 135 | 136 | WDSLAVE_READY:begin 137 | if(AMBAS.WLAST) begin 138 | WRITED_NEXTSTATE = WSLAVE_INIT; 139 | end 140 | else 141 | WRITED_NEXTSTATE = WDSLAVE_VALID; 142 | AMBAS.WREADY = 1'b1; 143 | 144 | unique case(AMBAS.AWBURST) 145 | 2'b00:begin 146 | masteraddress = AWADDR_r; 147 | 148 | unique case (AMBAS.WSTRB) 149 | 4'b0001:begin 150 | slave_memory[masteraddress] = AMBAS.WDATA[7:0]; 151 | end 152 | 153 | 4'b0010:begin 154 | slave_memory[masteraddress] = AMBAS.WDATA[15:8]; 155 | end 156 | 157 | 4'b0100:begin 158 | slave_memory[masteraddress] = AMBAS.WDATA[23:16]; 159 | end 160 | 161 | 4'b1000:begin 162 | slave_memory[masteraddress] = AMBAS.WDATA[31:24]; 163 | end 164 | 165 | 4'b0011:begin 166 | slave_memory[masteraddress] = AMBAS.WDATA[7:0]; 167 | slave_memory[masteraddress+1] = AMBAS.WDATA[15:8]; 168 | end 169 | 170 | 4'b0101:begin 171 | slave_memory[masteraddress] = AMBAS.WDATA[7:0]; 172 | slave_memory[masteraddress+1] = AMBAS.WDATA[23:16]; 173 | end 174 | 175 | 4'b1001:begin 176 | slave_memory[masteraddress] = AMBAS.WDATA[7:0]; 177 | slave_memory[masteraddress+1] = AMBAS.WDATA[31:24]; 178 | end 179 | 180 | 4'b0110:begin 181 | slave_memory[masteraddress] = AMBAS.WDATA[15:0]; 182 | slave_memory[masteraddress+1] = AMBAS.WDATA[23:16]; 183 | end 184 | 185 | 4'b1010:begin 186 | slave_memory[masteraddress] = AMBAS.WDATA[15:8]; 187 | slave_memory[masteraddress+1] = AMBAS.WDATA[31:24]; 188 | end 189 | 190 | 4'b1100:begin 191 | slave_memory[masteraddress] = AMBAS.WDATA[23:16]; 192 | slave_memory[masteraddress+1] = AMBAS.WDATA[31:24]; 193 | end 194 | 195 | 4'b0111:begin 196 | slave_memory[masteraddress] = AMBAS.WDATA[7:0]; 197 | slave_memory[masteraddress+1] = AMBAS.WDATA[15:8]; 198 | slave_memory[masteraddress+2] = AMBAS.WDATA[23:16]; 199 | end 200 | 201 | 4'b1110:begin 202 | slave_memory[masteraddress] = AMBAS.WDATA[15:8]; 203 | slave_memory[masteraddress+1] = AMBAS.WDATA[23:16]; 204 | slave_memory[masteraddress+2] = AMBAS.WDATA[31:24]; 205 | end 206 | 207 | 4'b1011:begin 208 | slave_memory[masteraddress] = AMBAS.WDATA[7:0]; 209 | slave_memory[masteraddress+1] = AMBAS.WDATA[15:8]; 210 | slave_memory[masteraddress+2] = AMBAS.WDATA[31:24]; 211 | end 212 | 213 | 4'b1101:begin 214 | slave_memory[masteraddress] = AMBAS.WDATA[7:0]; 215 | slave_memory[masteraddress+1] = AMBAS.WDATA[23:16]; 216 | slave_memory[masteraddress+2] = AMBAS.WDATA[31:24]; 217 | end 218 | 219 | 4'b1111:begin 220 | slave_memory[masteraddress] = AMBAS.WDATA[7:0]; 221 | slave_memory[masteraddress+1] = AMBAS.WDATA[15:8]; 222 | slave_memory[masteraddress+2] = AMBAS.WDATA [23:16]; 223 | slave_memory[masteraddress+3] = AMBAS.WDATA [31:24]; 224 | end 225 | default: begin 226 | end 227 | 228 | endcase 229 | end 230 | 231 | 2'b01:begin 232 | if(first_time == 0) 233 | begin 234 | masteraddress = AWADDR_r; 235 | first_time_next2 = 1; 236 | end 237 | else 238 | first_time_next2 = first_time; 239 | 240 | if(AMBAS.BREADY == 1) 241 | first_time_next2 = 0; 242 | else 243 | first_time_next2 = first_time; 244 | 245 | unique case (AMBAS.WSTRB) 246 | 4'b0001:begin 247 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 248 | masteraddress_reg = masteraddress + 1; 249 | end 250 | 251 | 4'b0010:begin 252 | slave_memory[masteraddress] = AMBAS.WDATA [15:8]; 253 | masteraddress_reg = masteraddress + 1; 254 | end 255 | 256 | 4'b0100:begin 257 | slave_memory[masteraddress] = AMBAS.WDATA [23:16]; 258 | masteraddress_reg = masteraddress + 1; 259 | end 260 | 261 | 4'b1000:begin 262 | slave_memory[masteraddress] = AMBAS.WDATA [31:24]; 263 | masteraddress_reg = masteraddress + 1; 264 | end 265 | 266 | 4'b0011:begin 267 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 268 | slave_memory[masteraddress+1] = AMBAS.WDATA [15:8]; 269 | masteraddress_reg = masteraddress + 2; 270 | end 271 | 272 | 4'b0101:begin 273 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 274 | slave_memory[masteraddress+1] = AMBAS.WDATA [23:16]; 275 | masteraddress_reg = masteraddress + 2; 276 | end 277 | 278 | 4'b1001:begin 279 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 280 | slave_memory[masteraddress+1] = AMBAS.WDATA [31:24]; 281 | masteraddress_reg = masteraddress + 2; 282 | end 283 | 284 | 4'b0110:begin 285 | slave_memory[masteraddress] = AMBAS.WDATA [15:0]; 286 | slave_memory[masteraddress+1] = AMBAS.WDATA [23:16]; 287 | masteraddress_reg = masteraddress + 2; 288 | end 289 | 290 | 4'b1010:begin 291 | slave_memory[masteraddress] = AMBAS.WDATA [15:8]; 292 | slave_memory[masteraddress+1] = AMBAS.WDATA [31:24]; 293 | masteraddress_reg = masteraddress + 2; 294 | end 295 | 296 | 4'b1100:begin 297 | slave_memory[masteraddress] = AMBAS.WDATA [23:16]; 298 | slave_memory[masteraddress+1] = AMBAS.WDATA [31:24]; 299 | masteraddress_reg = masteraddress + 2; 300 | end 301 | 302 | 4'b0111:begin 303 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 304 | slave_memory[masteraddress+1] = AMBAS.WDATA [15:8]; 305 | slave_memory[masteraddress+2] = AMBAS.WDATA [23:16]; 306 | masteraddress_reg = masteraddress + 3; 307 | end 308 | 309 | 4'b1110:begin 310 | slave_memory[masteraddress] = AMBAS.WDATA [15:8]; 311 | slave_memory[masteraddress+1] = AMBAS.WDATA [23:16]; 312 | slave_memory[masteraddress+2] = AMBAS.WDATA [31:24]; 313 | masteraddress_reg = masteraddress + 3; 314 | end 315 | 316 | 4'b1011:begin 317 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 318 | slave_memory[masteraddress+1] = AMBAS.WDATA [15:8]; 319 | slave_memory[masteraddress+2] = AMBAS.WDATA [31:24]; 320 | masteraddress_reg = masteraddress + 3; 321 | end 322 | 323 | 4'b1101:begin 324 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 325 | slave_memory[masteraddress+1] = AMBAS.WDATA [23:16]; 326 | slave_memory[masteraddress+2] = AMBAS.WDATA [31:24]; 327 | masteraddress_reg = masteraddress + 3; 328 | end 329 | 330 | 4'b1111:begin 331 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 332 | slave_memory[masteraddress+1] = AMBAS.WDATA [15:8]; 333 | slave_memory[masteraddress+2] = AMBAS.WDATA [23:16]; 334 | slave_memory[masteraddress+3] = AMBAS.WDATA [31:24]; 335 | masteraddress_reg = masteraddress + 4; 336 | end 337 | default: begin end 338 | endcase 339 | end 340 | 341 | 2'b10:begin 342 | if(first_time == 0) begin 343 | masteraddress = AWADDR_r; 344 | first_time_next2 = 1; 345 | end 346 | else 347 | first_time_next2 = first_time; 348 | if(AMBAS.BREADY == 1) 349 | first_time_next2 = 0; 350 | else 351 | first_time_next2 = first_time; 352 | 353 | unique case(AMBAS.AWLEN) 354 | 4'b0001:begin 355 | unique case(AMBAS.AWSIZE) 356 | 3'b000: begin 357 | wrap_boundary = 2 * 1; 358 | end 359 | 3'b001: begin 360 | wrap_boundary = 2 * 2; 361 | end 362 | 3'b010: begin 363 | wrap_boundary = 2 * 4; 364 | end 365 | default: begin end 366 | endcase 367 | end 368 | 369 | 4'b0011:begin 370 | unique case(AMBAS.AWSIZE) 371 | 3'b000: begin 372 | wrap_boundary = 4 * 1; 373 | end 374 | 3'b001: begin 375 | wrap_boundary = 4 * 2; 376 | end 377 | 3'b010: begin 378 | wrap_boundary = 4 * 4; 379 | end 380 | default: begin end 381 | endcase 382 | end 383 | 384 | 4'b0111:begin 385 | unique case(AMBAS.AWSIZE) 386 | 3'b000: begin 387 | wrap_boundary = 8 * 1; 388 | end 389 | 3'b001: begin 390 | wrap_boundary = 8 * 2; 391 | end 392 | 3'b010: begin 393 | wrap_boundary = 8 * 4; 394 | end 395 | default: begin end 396 | endcase 397 | end 398 | 399 | 4'b1111:begin 400 | unique case(AMBAS.AWSIZE) 401 | 3'b000: begin 402 | wrap_boundary = 16 * 1; 403 | 404 | end 405 | 3'b001: begin 406 | wrap_boundary = 16 * 2; 407 | end 408 | 3'b010: begin 409 | wrap_boundary = 16 * 4; 410 | end 411 | default: begin end 412 | endcase 413 | end 414 | endcase 415 | 416 | unique case(AMBAS.WSTRB) //Write strobe signal is encoded for writing different bit positions to the slave memory. 417 | 4'b0001:begin 418 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 419 | masteraddress_temp = masteraddress + 1; 420 | 421 | if(masteraddress_temp % wrap_boundary == 0) 422 | masteraddress_reg = masteraddress_temp - wrap_boundary; 423 | else 424 | masteraddress_reg = masteraddress_temp; 425 | end 426 | 427 | 4'b0010:begin 428 | slave_memory[masteraddress] = AMBAS.WDATA [15:8]; 429 | masteraddress_temp = masteraddress + 1; 430 | 431 | if(masteraddress_temp % wrap_boundary == 0) 432 | masteraddress_reg = masteraddress_temp - wrap_boundary; 433 | else 434 | masteraddress_reg = masteraddress_temp; 435 | end 436 | 437 | 4'b0100:begin 438 | slave_memory[masteraddress] = AMBAS.WDATA [23:16]; 439 | masteraddress_temp = masteraddress + 1; 440 | 441 | if(masteraddress_temp % wrap_boundary == 0) 442 | masteraddress_reg = masteraddress_temp - wrap_boundary; 443 | else 444 | masteraddress_reg = masteraddress_temp; 445 | end 446 | 447 | 4'b1000:begin 448 | slave_memory[masteraddress] = AMBAS.WDATA [31:24]; 449 | masteraddress_temp = masteraddress + 1; 450 | 451 | if(masteraddress_temp % wrap_boundary == 0) 452 | masteraddress_reg = masteraddress_temp - wrap_boundary; 453 | else 454 | masteraddress_reg = masteraddress_temp; 455 | end 456 | 457 | 4'b0011:begin 458 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 459 | masteraddress_temp = masteraddress + 1; 460 | 461 | if(masteraddress_temp % wrap_boundary == 0) 462 | masteraddress_reg = masteraddress_temp - wrap_boundary; 463 | else 464 | masteraddress_reg = masteraddress_temp; 465 | 466 | slave_memory[masteraddress_reg] = AMBAS.WDATA [15:8]; 467 | masteraddress_temp = masteraddress_reg + 1; 468 | 469 | if(masteraddress_temp % wrap_boundary == 0) 470 | masteraddress_reg = masteraddress_temp - wrap_boundary; 471 | else 472 | masteraddress_reg = masteraddress_temp; 473 | end 474 | 475 | 4'b0101:begin 476 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 477 | masteraddress_temp = masteraddress + 1; 478 | 479 | if(masteraddress_temp % wrap_boundary == 0) 480 | masteraddress_reg = masteraddress_temp - wrap_boundary; 481 | else 482 | masteraddress_reg = masteraddress_temp; 483 | slave_memory[masteraddress_reg] = AMBAS.WDATA [23:16]; 484 | masteraddress_temp = masteraddress_reg + 1; 485 | 486 | if(masteraddress_temp % wrap_boundary == 0) 487 | masteraddress_reg = masteraddress_temp - wrap_boundary; 488 | else 489 | masteraddress_reg = masteraddress_temp; 490 | end 491 | 492 | 4'b1001:begin 493 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 494 | masteraddress_temp = masteraddress + 1; 495 | 496 | if(masteraddress_temp % wrap_boundary == 0) 497 | masteraddress_reg = masteraddress_temp - wrap_boundary; 498 | else 499 | masteraddress_reg = masteraddress_temp; 500 | 501 | slave_memory[masteraddress_reg] = AMBAS.WDATA [31:24]; 502 | masteraddress_temp = masteraddress_reg + 1; 503 | 504 | if(masteraddress_temp % wrap_boundary == 0) 505 | masteraddress_reg = masteraddress_temp - wrap_boundary; 506 | else 507 | masteraddress_reg = masteraddress_temp; 508 | end 509 | 510 | 4'b0110:begin 511 | slave_memory[masteraddress] = AMBAS.WDATA [15:0]; 512 | masteraddress_temp = masteraddress + 1; 513 | 514 | if(masteraddress_temp % wrap_boundary == 0) 515 | masteraddress_reg = masteraddress_temp - wrap_boundary; 516 | else 517 | masteraddress_reg = masteraddress_temp; 518 | 519 | slave_memory[masteraddress_reg] = AMBAS.WDATA [23:16]; 520 | masteraddress_temp = masteraddress_reg + 1; 521 | 522 | if(masteraddress_temp % wrap_boundary == 0) 523 | masteraddress_reg = masteraddress_temp - wrap_boundary; 524 | else 525 | masteraddress_reg = masteraddress_temp; 526 | end 527 | 528 | 4'b1010:begin 529 | slave_memory[masteraddress] = AMBAS.WDATA [15:8]; 530 | masteraddress_temp = masteraddress + 1; 531 | 532 | if(masteraddress_temp % wrap_boundary== 0) 533 | masteraddress_reg = masteraddress_temp - wrap_boundary; 534 | else 535 | masteraddress_reg = masteraddress_temp; 536 | 537 | slave_memory[masteraddress_reg] = AMBAS.WDATA [31:24]; 538 | masteraddress_temp = masteraddress_reg + 1; 539 | 540 | if(masteraddress_temp % wrap_boundary == 0) 541 | masteraddress_reg = masteraddress_temp - wrap_boundary; 542 | else 543 | masteraddress_reg = masteraddress_temp; 544 | end 545 | 546 | 4'b1100:begin 547 | slave_memory[masteraddress] = AMBAS.WDATA [23:16]; 548 | masteraddress_temp = masteraddress + 1; 549 | 550 | if(masteraddress_temp % wrap_boundary == 0) 551 | masteraddress_reg = masteraddress_temp - wrap_boundary; 552 | else 553 | masteraddress_reg = masteraddress_temp; 554 | 555 | slave_memory[masteraddress_reg] = AMBAS.WDATA [31:24]; 556 | masteraddress_temp = masteraddress_reg + 1; 557 | 558 | if(masteraddress_temp % wrap_boundary == 0) 559 | masteraddress_reg = masteraddress_temp - wrap_boundary; 560 | else 561 | masteraddress_reg = masteraddress_temp; 562 | end 563 | 564 | 4'b0111:begin 565 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 566 | masteraddress_temp = masteraddress + 1; 567 | 568 | if(masteraddress_temp % wrap_boundary == 0) 569 | masteraddress_reg = masteraddress_temp - wrap_boundary; 570 | else 571 | masteraddress_reg = masteraddress_temp; 572 | 573 | slave_memory[masteraddress_reg] = AMBAS.WDATA [15:8]; 574 | masteraddress_temp = masteraddress_reg + 1; 575 | 576 | if(masteraddress_temp % wrap_boundary == 0) 577 | masteraddress_reg = masteraddress_temp - wrap_boundary; 578 | else 579 | masteraddress_reg = masteraddress_temp; 580 | 581 | slave_memory[masteraddress_reg] = AMBAS.WDATA [23:16]; 582 | masteraddress_temp = masteraddress_reg + 1; 583 | 584 | if(masteraddress_temp % wrap_boundary == 0) 585 | masteraddress_reg = masteraddress_temp - wrap_boundary; 586 | else 587 | masteraddress_reg = masteraddress_temp; 588 | end 589 | 590 | 4'b1110:begin 591 | slave_memory[masteraddress] = AMBAS.WDATA [15:8]; 592 | masteraddress_temp = masteraddress + 1; 593 | 594 | if(masteraddress_temp % wrap_boundary == 0) 595 | masteraddress_reg = masteraddress_temp - wrap_boundary; 596 | else 597 | masteraddress_reg = masteraddress_temp; 598 | 599 | slave_memory[masteraddress_reg] = AMBAS.WDATA [23:16]; 600 | masteraddress_temp = masteraddress_reg + 1; 601 | 602 | if(masteraddress_temp % wrap_boundary == 0) 603 | masteraddress_reg = masteraddress_temp - wrap_boundary; 604 | else 605 | masteraddress_reg = masteraddress_temp; 606 | 607 | slave_memory[masteraddress_reg] = AMBAS.WDATA [31:24]; 608 | masteraddress_temp = masteraddress_reg + 1; 609 | 610 | if(masteraddress_temp % wrap_boundary == 0) 611 | masteraddress_reg = masteraddress_temp - wrap_boundary; 612 | else 613 | masteraddress_reg = masteraddress_temp; 614 | end 615 | 616 | 4'b1011:begin 617 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 618 | masteraddress_temp = masteraddress + 1; 619 | 620 | if(masteraddress_temp % wrap_boundary == 0) 621 | masteraddress_reg = masteraddress_temp - wrap_boundary; 622 | else 623 | masteraddress_reg = masteraddress_temp; 624 | 625 | slave_memory[masteraddress_reg] = AMBAS.WDATA [15:8]; 626 | masteraddress_temp = masteraddress_reg + 1; 627 | 628 | if(masteraddress_temp % wrap_boundary == 0) 629 | masteraddress_reg = masteraddress_temp - wrap_boundary; 630 | else 631 | masteraddress_reg = masteraddress_temp; 632 | 633 | slave_memory[masteraddress_reg] = AMBAS.WDATA [31:24]; 634 | masteraddress_temp = masteraddress_reg + 1; 635 | 636 | if(masteraddress_temp % wrap_boundary == 0) 637 | masteraddress_reg = masteraddress_temp - wrap_boundary; 638 | else 639 | masteraddress_reg = masteraddress_temp; 640 | end 641 | 4'b1101:begin 642 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 643 | masteraddress_temp = masteraddress + 1; 644 | 645 | if(masteraddress_temp % wrap_boundary == 0) 646 | masteraddress_reg = masteraddress_temp - wrap_boundary; 647 | else 648 | masteraddress_reg = masteraddress_temp; 649 | 650 | slave_memory[masteraddress_reg] = AMBAS.WDATA [23:16]; 651 | masteraddress_temp = masteraddress_reg + 1; 652 | 653 | if(masteraddress_temp % wrap_boundary == 0) 654 | masteraddress_reg = masteraddress_temp - wrap_boundary; 655 | else 656 | masteraddress_reg = masteraddress_temp; 657 | 658 | slave_memory[masteraddress_reg] = AMBAS.WDATA [31:24]; 659 | masteraddress_temp = masteraddress_reg + 1; 660 | 661 | if(masteraddress_temp % wrap_boundary == 0) 662 | masteraddress_reg = masteraddress_temp - wrap_boundary; 663 | else 664 | masteraddress_reg = masteraddress_temp; 665 | end 666 | 667 | 4'b1111: begin 668 | slave_memory[masteraddress] = AMBAS.WDATA [7:0]; 669 | masteraddress_temp = masteraddress + 1; 670 | 671 | if(masteraddress_temp % wrap_boundary == 0) 672 | masteraddress_reg = masteraddress_temp - wrap_boundary; 673 | else 674 | masteraddress_reg = masteraddress_temp; 675 | 676 | slave_memory[masteraddress_reg] = AMBAS.WDATA [15:8]; 677 | masteraddress_temp = masteraddress_reg + 1; 678 | 679 | if(masteraddress_temp % wrap_boundary == 0) 680 | masteraddress_reg = masteraddress_temp - wrap_boundary; 681 | else 682 | masteraddress_reg = masteraddress_temp; 683 | 684 | slave_memory[masteraddress_reg] = AMBAS.WDATA [23:16]; 685 | masteraddress_temp = masteraddress_reg + 1; 686 | 687 | if(masteraddress_temp % wrap_boundary == 0) 688 | masteraddress_reg = masteraddress_temp - wrap_boundary; 689 | else 690 | masteraddress_reg = masteraddress_temp; 691 | 692 | slave_memory[masteraddress_reg] = AMBAS.WDATA [31:24]; 693 | masteraddress_temp = masteraddress_reg + 1; 694 | 695 | if(masteraddress_temp % wrap_boundary == 0) 696 | masteraddress_reg = masteraddress_temp - wrap_boundary; 697 | else 698 | masteraddress_reg = masteraddress_temp; 699 | end 700 | default: begin end 701 | endcase 702 | end 703 | 704 | 705 | 706 | endcase 707 | $display("each beat Meme= %p",slave_memory); 708 | end 709 | WDSLAVE_VALID:begin 710 | AMBAS.WREADY = 1'b0; 711 | WRITED_NEXTSTATE = WDSLAVE_START; 712 | end 713 | endcase 714 | end 715 | 716 | 717 | 718 | ///////////////////////////////////////FSM for Write Response Channel of Slave\\\\\\\\\\\\\\\\\\\\\\\//////////// 719 | 720 | always_ff @(posedge clock or negedge reset) 721 | begin 722 | if(!reset) begin 723 | SLAVEB_STATE <= RESPONSEB_IDLE; 724 | end 725 | else 726 | SLAVEB_STATE <= SLAVEB_NEXTSTATE; 727 | end 728 | 729 | 730 | always_comb 731 | begin 732 | case(SLAVEB_STATE) 733 | RESPONSEB_IDLE:begin 734 | AMBAS.BID = '0; 735 | AMBAS.BRESP = '0; 736 | AMBAS.BVALID = '0; 737 | SLAVEB_NEXTSTATE = RESPONSEB_LAST; 738 | end 739 | 740 | RESPONSEB_LAST:begin 741 | if(AMBAS.WLAST) 742 | SLAVEB_NEXTSTATE = RESPONSEB_START; 743 | else 744 | SLAVEB_NEXTSTATE = RESPONSEB_LAST; 745 | end 746 | 747 | RESPONSEB_START:begin 748 | AMBAS.BID = AMBAS.AWID; 749 | if ( AMBAS.AWADDR > 32'h5ff && AMBAS.AWADDR <=32'hfff && AMBAS.AWSIZE < 3'b011 ) 750 | AMBAS.BRESP = 2'b00; 751 | else if(( AMBAS.AWADDR > 32'h1ff && AMBAS.AWADDR <=32'h5ff) || AMBAS.AWSIZE > 3'b010) 752 | AMBAS.BRESP = 2'b10; 753 | else 754 | AMBAS.BRESP = 2'b11; 755 | 756 | AMBAS.BVALID = 1'b1; 757 | SLAVEB_NEXTSTATE = RESPONSEB_WAIT; 758 | end 759 | 760 | RESPONSEB_WAIT:begin 761 | if (AMBAS.BREADY) begin 762 | SLAVEB_NEXTSTATE = RESPONSEB_IDLE; 763 | end 764 | end 765 | endcase 766 | end 767 | 768 | 769 | 770 | 771 | //////////////////////////////////////////////FSM for Read Address Channel of Slave \\\\\\\\\\\\\\\\\\\\\\\/////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\// 772 | 773 | 774 | always_ff @(posedge clock or negedge reset) 775 | begin 776 | if (!reset) begin 777 | RSLAVE_STATE <= RSLAVE_IDLE; 778 | end 779 | else begin 780 | RSLAVE_STATE <= RSLAVE_NEXTSTATE; 781 | end 782 | end 783 | 784 | always_comb 785 | begin 786 | case (RSLAVE_STATE) 787 | RSLAVE_IDLE:begin 788 | AMBAS.ARREADY = '0; 789 | RSLAVE_NEXTSTATE = RSLAVE_WAIT; 790 | end 791 | 792 | RSLAVE_WAIT:begin 793 | if (AMBAS.ARVALID) 794 | RSLAVE_NEXTSTATE = RSLAVE_READY; 795 | else 796 | RSLAVE_NEXTSTATE = RSLAVE_WAIT; 797 | end 798 | 799 | RSLAVE_READY:begin 800 | RSLAVE_NEXTSTATE = RSLAVE_IDLE; 801 | AMBAS.ARREADY = 1'b1; 802 | end 803 | endcase 804 | end 805 | 806 | 807 | 808 | ////////////////////////////////////////////////////////////////FSM for Read Data Channel of Slave\\\\\\\\\\\\\\\\\\\\\\\\\\//////////////////// 809 | 810 | 811 | always_ff@(posedge clock or negedge reset) 812 | begin 813 | if(!reset) begin 814 | RDSLAVE_STATE <= RDSLAVE_CLEAR; 815 | Counter <= '0; 816 | end 817 | else begin 818 | RDSLAVE_STATE <= RDSLAVE_NEXTSTATE; 819 | Counter <= Next_Counter; 820 | first_time2 <= first_time2_next; 821 | end 822 | end 823 | 824 | always_comb 825 | begin 826 | if(AMBAS.ARVALID) 827 | ARADDR_r1 = AMBAS.ARADDR; 828 | 829 | unique case(RDSLAVE_STATE) 830 | RDSLAVE_CLEAR:begin 831 | AMBAS.RID = '0; 832 | AMBAS.RDATA = '0; 833 | AMBAS.RRESP = '0; 834 | AMBAS.RLAST = '0; 835 | AMBAS.RVALID = '0; 836 | first_time2_next = 0; 837 | Next_Counter = '0; 838 | readdata_address_r='0; 839 | readdata_address='0; 840 | if(AMBAS.ARVALID) begin 841 | RDSLAVE_NEXTSTATE = RDSLAVE_START; 842 | end 843 | else 844 | RDSLAVE_NEXTSTATE = RDSLAVE_CLEAR; 845 | end 846 | 847 | RDSLAVE_START:begin 848 | if( AMBAS.ARADDR > 32'h1ff && AMBAS.ARADDR <=32'hfff && AMBAS.ARSIZE <3'b100) begin 849 | AMBAS.RID = AMBAS.ARID; 850 | 851 | unique case(AMBAS.ARBURST) //Read Burst type- Fixed, increment, Wrapping 852 | 2'b00:begin //Fixed(00) 853 | readdata_address = ARADDR_r1; 854 | unique case (AMBAS.ARSIZE) 855 | 3'b000:begin 856 | AMBAS.RDATA[7:0] = slave_memory[readdata_address]; 857 | end 858 | 859 | 3'b001:begin 860 | AMBAS.RDATA[7:0] = slave_memory[readdata_address]; 861 | AMBAS.RDATA[15:8] = slave_memory[readdata_address+1]; 862 | end 863 | 864 | 3'b010:begin 865 | AMBAS.RDATA[7:0] = slave_memory[readdata_address]; 866 | AMBAS.RDATA[15:8] = slave_memory[readdata_address+1]; 867 | AMBAS.RDATA[23:16] = slave_memory[readdata_address+2]; 868 | AMBAS.RDATA[31:24] = slave_memory[readdata_address+3]; 869 | end 870 | endcase 871 | end 872 | 873 | 2'b01:begin //Increment(01) 874 | if(first_time2 == 0) begin 875 | readdata_address = ARADDR_r1; 876 | first_time2_next = 1; 877 | end 878 | else 879 | first_time2_next = first_time2; 880 | 881 | if(Next_Counter == AMBAS.ARLEN+4'b1) 882 | first_time2_next = 0; 883 | else 884 | first_time2_next = first_time2; 885 | 886 | unique case (AMBAS.ARSIZE) 887 | 3'b000:begin 888 | AMBAS.RDATA[7:0] = slave_memory[readdata_address]; 889 | end 890 | 891 | 3'b001: begin 892 | AMBAS.RDATA[7:0] = slave_memory[readdata_address]; 893 | AMBAS.RDATA[15:8] = slave_memory[readdata_address+1]; 894 | readdata_address_r = readdata_address + 2; 895 | end 896 | 3'b010: begin 897 | AMBAS.RDATA[7:0] = slave_memory[readdata_address]; 898 | AMBAS.RDATA[15:8] = slave_memory[readdata_address+1]; 899 | AMBAS.RDATA[23:16] = slave_memory[readdata_address+1]; 900 | AMBAS.RDATA[31:24] = slave_memory[readdata_address+1]; 901 | readdata_address_r = readdata_address + 4; 902 | end 903 | endcase 904 | end 905 | 2'b10:begin //Wrapping (10) 906 | if(first_time2 == 0) begin 907 | readdata_address = ARADDR_r1; 908 | first_time2_next = 1; 909 | end 910 | else 911 | first_time2_next = first_time2; 912 | 913 | if(Next_Counter == AMBAS.ARLEN+4'b1) 914 | first_time2_next = 0; 915 | else 916 | first_time2_next = first_time2; 917 | 918 | unique case( AMBAS.ARLEN) 919 | 4'b0001:begin 920 | unique case( AMBAS.ARSIZE) 921 | 3'b000:begin 922 | wrap_boundary2 = 2 * 1; 923 | end 924 | 925 | 3'b001:begin 926 | wrap_boundary2 = 2 * 2; 927 | end 928 | 929 | 3'b010:begin 930 | wrap_boundary2 = 2 * 4; 931 | end 932 | default: begin end 933 | endcase 934 | end 935 | 936 | 4'b0011:begin 937 | unique case(AMBAS.ARSIZE) 938 | 3'b000:begin 939 | wrap_boundary2 = 4 * 1; 940 | end 941 | 942 | 3'b001:begin 943 | wrap_boundary2 = 4 * 2; 944 | end 945 | 946 | 3'b010:begin 947 | wrap_boundary2 = 4 * 4; 948 | end 949 | default: begin end 950 | endcase 951 | end 952 | 953 | 4'b0111:begin 954 | unique case(AMBAS.ARSIZE) 955 | 3'b000:begin 956 | wrap_boundary2 = 8 * 1; 957 | end 958 | 959 | 3'b001:begin 960 | wrap_boundary2 = 8 * 2; 961 | end 962 | 963 | 3'b010:begin 964 | wrap_boundary2 = 8 * 4; 965 | end 966 | default: begin end 967 | endcase 968 | end 969 | 970 | 4'b1111:begin 971 | unique case(AMBAS.ARSIZE) 972 | 3'b000:begin 973 | wrap_boundary2 = 16 * 1; 974 | end 975 | 976 | 3'b001:begin 977 | wrap_boundary2 = 16 * 2; 978 | end 979 | 980 | 3'b010:begin 981 | wrap_boundary2 = 16 * 4; 982 | end 983 | default: begin end 984 | endcase 985 | end 986 | endcase 987 | 988 | unique case(AMBAS.ARSIZE) 989 | 3'b000:begin 990 | AMBAS.RDATA[7:0] = slave_memory[readdata_address]; 991 | readdata_address_temp = readdata_address + 1; 992 | 993 | if(readdata_address_temp % wrap_boundary2 == 0) 994 | readdata_address_r = readdata_address_temp - wrap_boundary2; 995 | else 996 | readdata_address_r = readdata_address_temp; 997 | end 998 | 999 | 3'b001:begin 1000 | AMBAS.RDATA[7:0] = slave_memory[readdata_address]; 1001 | readdata_address_temp = readdata_address + 1; 1002 | 1003 | if(readdata_address_temp % wrap_boundary2 == 0) 1004 | readdata_address_r = readdata_address_temp - wrap_boundary2; 1005 | else 1006 | readdata_address_r = readdata_address_temp; 1007 | 1008 | AMBAS.RDATA[15:8] = slave_memory[readdata_address_r]; 1009 | readdata_address_temp = readdata_address_r + 1; 1010 | 1011 | if(readdata_address_temp % wrap_boundary2 == 0) 1012 | readdata_address_r = readdata_address_temp - wrap_boundary2; 1013 | else 1014 | readdata_address_r = readdata_address_temp; 1015 | end 1016 | 1017 | 3'b010:begin 1018 | AMBAS.RDATA[7:0] = slave_memory[readdata_address]; 1019 | readdata_address_temp = readdata_address + 1; 1020 | 1021 | if(readdata_address_temp % wrap_boundary2 == 0) 1022 | readdata_address_r = readdata_address_temp - wrap_boundary2; 1023 | else 1024 | readdata_address_r = readdata_address_temp; 1025 | 1026 | AMBAS.RDATA[15:8] = slave_memory[readdata_address_r]; 1027 | readdata_address_temp = readdata_address_r + 1; 1028 | 1029 | if(readdata_address_temp % wrap_boundary2 == 0) 1030 | readdata_address_r = readdata_address_temp - wrap_boundary2; 1031 | else 1032 | readdata_address_r = readdata_address_temp; 1033 | 1034 | AMBAS.RDATA[23:16] = slave_memory[readdata_address_r]; 1035 | readdata_address_temp = readdata_address_r + 1; 1036 | 1037 | if(readdata_address_temp % wrap_boundary2 == 0) 1038 | readdata_address_r = readdata_address_temp - wrap_boundary2; 1039 | else 1040 | readdata_address_r = readdata_address_temp; 1041 | 1042 | AMBAS.RDATA[31:24] = slave_memory[readdata_address_r]; 1043 | readdata_address_temp = readdata_address_r + 1; 1044 | 1045 | if(readdata_address_temp % wrap_boundary2 == 0) 1046 | readdata_address_r = readdata_address_temp - wrap_boundary2; 1047 | else 1048 | readdata_address_r = readdata_address_temp; 1049 | end 1050 | default: begin end 1051 | endcase 1052 | end 1053 | endcase 1054 | 1055 | 1056 | 1057 | 1058 | 1059 | AMBAS.RVALID = '1; 1060 | Next_Counter=Counter+4'b1; 1061 | RDSLAVE_NEXTSTATE = RDSLAVE_WAIT; 1062 | AMBAS.RRESP = 2'b00; 1063 | end 1064 | 1065 | else begin 1066 | if (AMBAS.ARSIZE >= 3'b011) 1067 | AMBAS.RRESP = 2'b10; 1068 | else 1069 | AMBAS.RRESP = 2'b11; 1070 | 1071 | Next_Counter=Counter+4'b1; 1072 | RDSLAVE_NEXTSTATE = RDSLAVE_ERROR; 1073 | end 1074 | end 1075 | 1076 | RDSLAVE_WAIT:begin 1077 | if(AMBAS.RREADY) begin 1078 | if(Next_Counter == AMBAS.ARLEN+4'b1) begin 1079 | AMBAS.RLAST = '1; 1080 | end 1081 | else 1082 | AMBAS.RLAST = '0; 1083 | 1084 | RDSLAVE_NEXTSTATE = RDSLAVE_VALID; 1085 | end 1086 | else begin 1087 | RDSLAVE_NEXTSTATE = RDSLAVE_WAIT; 1088 | end 1089 | end 1090 | 1091 | RDSLAVE_VALID:begin 1092 | AMBAS.RVALID = '0; 1093 | 1094 | if (Next_Counter == AMBAS.ARLEN+4'b1) begin 1095 | RDSLAVE_NEXTSTATE = RDSLAVE_CLEAR; 1096 | AMBAS.RLAST = '0; 1097 | end 1098 | else begin 1099 | readdata_address = readdata_address_r; 1100 | RDSLAVE_NEXTSTATE = RDSLAVE_START; 1101 | end 1102 | end 1103 | 1104 | RDSLAVE_ERROR:begin 1105 | if (Next_Counter == AMBAS.ARLEN+4'b1) begin 1106 | AMBAS.RLAST = '1; 1107 | RDSLAVE_NEXTSTATE = RDSLAVE_VALID; 1108 | end 1109 | else begin 1110 | AMBAS.RLAST = '0; 1111 | RDSLAVE_NEXTSTATE = RDSLAVE_START; 1112 | end 1113 | end 1114 | endcase 1115 | end 1116 | 1117 | endmodule -------------------------------------------------------------------------------- /AXI_Questa/Top_HDL.sv: -------------------------------------------------------------------------------- 1 | `include "MasterSlaveAxiInterface.sv" 2 | 3 | 4 | module Top_HDL #(parameter DATAWIDTH, SIZE) 5 | ( 6 | input logic clock, 7 | input logic reset, 8 | output logic [4095:0][7:0] slave_memory, 9 | output logic [4095:0][7:0] master_memory, 10 | axi intf, 11 | 12 | 13 | ///////////////////////Inputs to the Master from Testbench 14 | 15 | input logic [DATAWIDTH-1:0] AWaddr, 16 | input logic [(DATAWIDTH/8)-1:0] AWlen, 17 | input logic [(DATAWIDTH/8)-1:0] WStrb, 18 | input logic [SIZE-1:0] AWsize, 19 | input logic [SIZE-2:0] AWburst, 20 | input logic [DATAWIDTH-1:0] WData, 21 | input logic [(DATAWIDTH/8)-1:0] AWid, 22 | 23 | input logic [DATAWIDTH-1:0] ARaddr, 24 | input logic [(DATAWIDTH/8)-1:0] ARid, 25 | input logic [(DATAWIDTH/8)-1:0] ARlen, 26 | input logic [SIZE-1:0] ARsize, 27 | input logic [SIZE-2:0] ARburst 28 | 29 | ); 30 | 31 | 32 | 33 | 34 | 35 | ///Master<-> Axi3 interconnect instantiating 36 | 37 | Master_Axi3Protocol #(.DATAWIDTH(32),.SIZE(3)) 38 | master_inst ( .clock(clock), 39 | .reset(reset), 40 | .AMBA(intf), 41 | 42 | .read_memory(master_memory), 43 | .AWaddr(AWaddr), 44 | .AWlen(AWlen), 45 | .WStrb(WStrb), 46 | .AWsize(AWsize), 47 | .AWburst(AWburst), 48 | .WData(WData), 49 | .AWid(AWid), 50 | 51 | .ARaddr(ARaddr), 52 | .ARid(ARid), 53 | .ARlen(ARlen), 54 | .ARsize(ARsize), 55 | .ARburst(ARburst) 56 | ); 57 | 58 | //Slave<->Axi3 interconnect instantiating 59 | 60 | Slave_Axi3Protocol slave_inst(.clock(clock), 61 | .reset(reset), 62 | .AMBAS(intf), 63 | .slave_memory(slave_memory) 64 | ); 65 | 66 | 67 | endmodule -------------------------------------------------------------------------------- /AXI_Questa/Top_HVL.sv: -------------------------------------------------------------------------------- 1 | `include"driver.sv" 2 | `include"MasterSlaveAxiInterface.sv" 3 | `include"VE.sv" 4 | `include"assertions.sv" 5 | `include"Top_HDL.sv" 6 | 7 | module top(); 8 | timeunit 1ns; 9 | timeprecision 100ps; 10 | 11 | environment env; 12 | 13 | logic clock; 14 | logic reset; 15 | logic [4095:0][7:0] slave_memory; 16 | logic [4095:0][7:0] master_memory; 17 | 18 | bit [31:0] AWaddr; 19 | bit [3:0] AWlen; 20 | bit [3:0] WStrb; 21 | bit [2:0] AWsize; 22 | bit [1:0] AWburst; 23 | bit [31:0] WData; 24 | bit [3:0] AWid; 25 | 26 | bit [31:0] ARaddr; 27 | bit [3:0] ARid; 28 | bit [3:0] ARlen; 29 | bit [2:0] ARsize; 30 | bit [1:0] ARburst; 31 | 32 | 33 | 34 | //Generating Clock 35 | 36 | initial begin 37 | clock ='1; 38 | forever #5 clock = ~clock; 39 | end 40 | 41 | //////////////Instantiating 42 | axi intf(); 43 | driver drvr= new(intf); 44 | testcase test(intf); 45 | Top_HDL #(.DATAWIDTH(32),.SIZE(3)) 46 | Top_inst (.clock(clock), 47 | .reset(reset), 48 | .slave_memory(slave_memory), 49 | .master_memory(master_memory), 50 | .AWaddr(AWaddr), 51 | .AWlen(AWlen), 52 | .WStrb(WStrb), 53 | .AWsize(AWsize), 54 | .AWburst(AWburst), 55 | .WData(WData), 56 | .AWid(AWid), 57 | .ARaddr(ARaddr), 58 | .ARid(ARid), 59 | .ARlen(ARlen), 60 | .ARsize(ARsize), 61 | .ARburst(ARburst), 62 | .intf(intf) 63 | 64 | ); 65 | 66 | // Binding assertions with Top_HDL 67 | bind Top_HDL assertions duta(clock,reset,intf); 68 | endmodule 69 | 70 | -------------------------------------------------------------------------------- /AXI_Questa/VE.sv: -------------------------------------------------------------------------------- 1 | `include"driver.sv" 2 | `include"MasterSlaveAxiInterface.sv" 3 | `include"monitor.sv" 4 | 5 | 6 | 7 | 8 | `timescale 1ns/1ns 9 | 10 | `ifndef env_sv 11 | `define env_sv 12 | class environment; 13 | driver drvr; 14 | 15 | monitor mntr; 16 | virtual axi intf; 17 | 18 | function new(virtual axi intf); 19 | this.intf = intf; 20 | 21 | drvr = new(intf); 22 | mntr = new(intf); 23 | endfunction 24 | 25 | 26 | 27 | endclass 28 | `endif -------------------------------------------------------------------------------- /AXI_Questa/assertions.sv: -------------------------------------------------------------------------------- 1 | `include"MasterSlaveAxiInterface.sv" 2 | 3 | module assertions( 4 | input logic clock, 5 | input logic reset, 6 | 7 | axi intf 8 | 9 | ); 10 | 11 | // *********************Write Data Channel Assertions********************************************** 12 | // WID and AWID shuld match 13 | property AXI_AWID_WID; 14 | @(posedge clock) 15 | intf.WVALID |=> (intf.WID == intf.AWID); 16 | endproperty 17 | AXI_WVALID_WID_c: assert property (AXI_AWID_WID); 18 | 19 | 20 | // The control signals WDATA, WSTRB,WLAST,WID should remain stable 21 | property AXI_WVALID_STABLE; 22 | @(posedge clock) 23 | (intf.WVALID && !intf.WREADY) |=> ($stable(intf.WDATA) && $stable(intf.WSTRB) && $stable(intf.WID)); 24 | endproperty 25 | AXI_WVALID_STABLE_c: assert property (AXI_WVALID_STABLE); 26 | 27 | // The control signals WSTRB,WLAST,WID should not have any X's or Z's 28 | 29 | property AXI_VALIDSIGNALS; 30 | @(posedge clock) 31 | ##1 (intf.WVALID) |=> (!$isunknown(intf.WDATA) && !$isunknown(intf.WSTRB) && !$isunknown(intf.WID)); 32 | endproperty 33 | AXI_VALIDSIGNALS_c: assert property (AXI_VALIDSIGNALS); 34 | 35 | //Check when WREADY goes low after 1 clock cycle 36 | property AXI_WVALID_WREADY; 37 | @(posedge clock) 38 | (intf.WVALID && !intf.WREADY) |=> (intf.WVALID &&intf.WREADY) ##1 (!intf.WVALID && !intf.WREADY); 39 | endproperty 40 | 41 | AXI_WVALID_WREADY_c: assert property (AXI_WVALID_WREADY); 42 | 43 | //**************************** Write Address Channel Assertions********************************************************* 44 | 45 | // Data width should be less than 32 bit 46 | 47 | property AXI_AWSIZE; 48 | @(posedge clock) 49 | ##1 intf.AWSIZE < 3'b011; 50 | 51 | endproperty 52 | 53 | AXI_AWSIZE_WA: assert property(AXI_AWSIZE); 54 | 55 | // AWBURST type cannot be 3 56 | 57 | property AXI_AWBURST; 58 | @(posedge clock) 59 | ##1 intf.AWBURST != 2'b11; 60 | endproperty 61 | AXI_AWBURST_WA: assert property(AXI_AWBURST); 62 | 63 | // check whether control signals are stable 64 | 65 | property AXI_MASTERSIGNAL_STABLE; 66 | @(posedge clock) 67 | (intf.AWVALID && !intf.AWREADY)|=> ($stable(intf.AWID) && $stable(intf.AWADDR) && $stable(intf.AWLEN) && $stable(intf.AWSIZE) && $stable(intf.AWBURST)); 68 | 69 | endproperty 70 | AXI_MASTERSIGNAL_STABLE_c:assert property(AXI_MASTERSIGNAL_STABLE); 71 | 72 | // Check for X's and Z's 73 | 74 | property AXI_MASTERSIGNAL_UNDEFINED; 75 | @(posedge clock) 76 | disable iff (!reset) 77 | (intf.AWVALID) |-> (!$isunknown(intf.AWID) && !$isunknown(intf.AWADDR) && !$isunknown(intf.AWLEN) && !$isunknown(intf.AWSIZE) && !$isunknown(intf.AWBURST)); 78 | endproperty 79 | AXI_MASTERSIGNAL_UNDEFINED_c:assert property(AXI_MASTERSIGNAL_UNDEFINED); 80 | 81 | //In case of wrapping burst AWLEN should have value 2, 4, 8, 16 82 | 83 | property AXI_WRAPBOUNDARY; 84 | @(posedge clock) 85 | disable iff (!reset) 86 | (intf.AWBURST == 2'b10) |-> (intf.AWLEN == 4'b0001 || intf.AWLEN == 4'b0011 || intf.AWLEN == 4'b0111 || intf.AWLEN == 4'b1111); 87 | endproperty 88 | 89 | AXI_WRAPBOUNDARY_c: assert property(AXI_WRAPBOUNDARY); 90 | 91 | // check when AWVALID is asserted, AWVALID goes high and then goes low 92 | 93 | property AXI_AWVALID_AWREADY; 94 | @(posedge clock) 95 | (intf.AWVALID && !intf.AWREADY) |=> (intf.AWVALID &&intf.AWREADY) ##1 (!intf.AWVALID && !intf.AWREADY); 96 | endproperty 97 | 98 | AXI_AWVALID_AWREADY_c: assert property(AXI_AWVALID_AWREADY); 99 | 100 | 101 | //******************* Assertions for Write Response Channel***************************************** 102 | //Check if BID and AWID matches 103 | property AXI_BVALID_BID; 104 | @(posedge clock) 105 | intf.BVALID |=> (intf.BID == intf.AWID); 106 | endproperty 107 | AXI_BVALID_BID_a: assert property (AXI_BVALID_BID); 108 | 109 | //Check if BRESP IS STABLE AFTER BVALID IS PRESENT 110 | property AXI_BVALID_BRESP; 111 | @(posedge clock) 112 | ##1 intf.BVALID |=> $stable(intf.BRESP); 113 | endproperty 114 | AXI_BVALID_BRESP_a: assert property (AXI_BVALID_BRESP); 115 | 116 | // Check if after BVALID is asserted BREADY becomes 1 after 1 clock cycle 117 | property AXI_BVALID_BREADY; 118 | @(posedge clock) 119 | (intf.BVALID && !intf.BREADY) |=> (intf.BVALID &&intf.BREADY) ##1 (!intf.BVALID && !intf.BREADY); 120 | endproperty 121 | AXI_BVALID_BREADY_a: assert property (AXI_BVALID_BREADY); 122 | 123 | //Check if slave should initiate response, after WLAST is asserted 124 | property AXI_WLAST_BVALID; 125 | @(posedge clock) 126 | intf.WLAST |=> intf.BVALID; 127 | endproperty 128 | 129 | AXI_WLAST_BVALID_a: assert property (AXI_WLAST_BVALID); 130 | 131 | 132 | //***************** Read Address Channel Assertions************************************* 133 | // check the control signals are stable 134 | property AXI_ARVALID_STABLE; 135 | @(posedge clock) 136 | (intf.ARVALID && !intf.ARREADY) |=> ($stable(intf.ARID) && $stable(intf.ARADDR) && $stable(intf.ARLEN) && $stable(intf.ARSIZE) && $stable(intf.ARBURST)); 137 | endproperty 138 | AXI_ARVALID_STABLE_c: assert property (AXI_ARVALID_STABLE); 139 | 140 | // check of ARVALID and ARREADY 141 | property AXI_VALIDSIGNALS_RA; 142 | @(posedge clock) 143 | (reset)|=> (!$isunknown(intf.ARVALID) && !$isunknown(intf.ARREADY)); 144 | endproperty 145 | AXI_VALIDSIGNALS_RA_c: assert property (AXI_VALIDSIGNALS_RA); 146 | 147 | // Check if ARREADY and ARVALID after 1 clock cycle. 148 | property AXI_ARVALID_ARREADY; 149 | @(posedge clock) 150 | (intf.ARVALID && !intf.ARREADY) |=> (intf.ARVALID &&intf.ARREADY) ##1 (!intf.ARVALID && !intf.ARREADY); 151 | endproperty 152 | 153 | AXI_ARVALID_ARREADY_c: assert property (AXI_ARVALID_ARREADY); 154 | 155 | //**********************Read Data Channel Assertions****************************************** 156 | //Check if RID and ARID is same 157 | property AXI_RVALID_RID; 158 | @(posedge clock) 159 | intf.RVALID |=> (intf.RID == intf.ARID); 160 | endproperty 161 | AXI_RVALID_RID_c: assert property (AXI_RVALID_RID); 162 | 163 | //check if CONTROL SIGNALS ARE STABLE 164 | property AXI_RVALID_STABLE; 165 | @(posedge clock) 166 | (intf.RVALID && !intf.RREADY) |=> ($stable(intf.RID) && $stable(intf.RDATA) && $stable(intf.RRESP)); 167 | endproperty 168 | AXI_RVALID_STABLE_c: assert property (AXI_RVALID_STABLE); 169 | 170 | 171 | // Check if ARREADY becomes low after 1 clock cycle 172 | property AXI_RVALID_RREADY; 173 | @(posedge clock) 174 | (intf.RVALID && !intf.RREADY) |=> (intf.RVALID &&intf.RREADY) ##1 (!intf.RVALID && !intf.RREADY); 175 | endproperty 176 | 177 | AXI_RVALID_RREADY_c: assert property (AXI_RVALID_RREADY); 178 | 179 | 180 | endmodule 181 | -------------------------------------------------------------------------------- /AXI_Questa/driver.sv: -------------------------------------------------------------------------------- 1 | 2 | `ifndef drvr_sv 3 | `define drvr_sv 4 | 5 | 6 | class DRVI; //Creating a class for generating random signals which are passed to the driver for performing different type of transactions. 7 | rand bit [3:0] rand_awid; //Random write address id generating 8 | rand bit [31:0] rand_awaddr_valid; //Random Valid Write Address generating with Constraint S1 9 | constraint S1{ // 10 | rand_awaddr_valid > 32'h5ff; // 11 | rand_awaddr_valid <=32'hfff; // 12 | } 13 | rand bit [31:0] rand_awaddr_readonly; //Random Read-only address with Constraint S2 14 | constraint S2{ 15 | rand_awaddr_readonly > 32'h1ff; 16 | rand_awaddr_readonly <= 32'h5ff; 17 | } 18 | rand bit [31:0] rand_awaddr_invalid; //Random InValid write address with Constraint S3 19 | constraint S3{ 20 | rand_awaddr_invalid <= 32'h1ff; 21 | } 22 | rand bit [31:0] rand_wdata; //Random write data generating. 32bit used 23 | rand bit [31:0] rand_araddr_valid; // Random Valid read address with Constraint S4 24 | constraint S4{ 25 | rand_araddr_valid > 32'h1ff; 26 | rand_araddr_valid <= 32'hfff; 27 | } 28 | rand bit [31:0] rand_araddr_invalid; // Random InValid read address with Constraint S5 29 | constraint S5{ 30 | rand_araddr_invalid <= 32'h1ff; 31 | } 32 | rand bit [3:0] rand_arid; //Random read address id generating 33 | 34 | endclass 35 | 36 | 37 | class driver; //Driver class 38 | 39 | DRVI val=new(); //creating an instance of the driver stimulus class 40 | virtual axi intf; //instance of MasterSlaveAxiInterface 41 | 42 | function new(virtual axi intf); 43 | this.intf = intf; //assigning to the driver class member intf 44 | endfunction 45 | 46 | int status; //status variable used for randomize status 47 | 48 | logic [3:0] STRB = '0; 49 | logic [3:0] p; 50 | int i,n; 51 | bit [1:0] b,x; 52 | bit [2:0] k,y; 53 | bit [3:0] j,l,z,s; 54 | task stimulus; //creating a task for passing the stimulus -randomly assigned signals while performing testing. 55 | output bit [3:0] rand_awid; 56 | output bit [31:0] rand_awaddr_valid; 57 | output bit [31:0] rand_awaddr_invalid; 58 | output bit [31:0] rand_awaddr_readonly; 59 | output bit [31:0] rand_wdata; 60 | output bit [31:0] rand_araddr_valid; 61 | output bit [31:0] rand_araddr_invalid; 62 | output bit [3:0] rand_arid; 63 | 64 | DRVI val = new(); 65 | status = val.randomize(); 66 | rand_awid = val.rand_awid; 67 | rand_awaddr_valid = val.rand_awaddr_valid; 68 | rand_awaddr_invalid = val.rand_awaddr_invalid; 69 | rand_awaddr_readonly = val.rand_awaddr_readonly; 70 | rand_wdata = val.rand_wdata; 71 | rand_araddr_valid = val.rand_araddr_valid; 72 | rand_araddr_invalid = val.rand_araddr_invalid; 73 | rand_arid = val.rand_arid; 74 | 75 | $display("\nInside Driver:-"); 76 | endtask 77 | 78 | 79 | 80 | 81 | task reset_enable; //Reset task - used for clearing all signals-active low reset used. 82 | top.reset = 1'b0; 83 | intf.AWREADY = '0; 84 | intf.AWVALID = '0; 85 | intf.AWBURST = '0; 86 | intf.AWSIZE = '0; 87 | intf.AWLEN = '0; 88 | intf.AWADDR = '0; 89 | intf.AWID = '0; 90 | intf.WREADY = '0; 91 | intf.WVALID = '0; 92 | intf.WLAST = '0; 93 | intf.WSTRB = '0; 94 | intf.WDATA = '0; 95 | intf.WID = '0; 96 | intf.BID = '0; 97 | intf.BRESP = '0; 98 | intf.BVALID = '0; 99 | intf.BREADY = '0; 100 | intf.ARREADY = '0; 101 | intf.ARID = '0; 102 | intf.ARADDR = '0; 103 | intf.ARLEN = '0; 104 | intf.ARSIZE = '0; 105 | intf.ARBURST = '0; 106 | intf.ARVALID = '0; 107 | intf.RID = '0; 108 | intf.RDATA = '0; 109 | intf.RRESP = '0; 110 | intf.RLAST = '0; 111 | intf.RVALID = '0; 112 | intf.RREADY = '0; 113 | top.AWaddr = '0; 114 | top.AWid = '0; 115 | top.AWsize = '0; 116 | top.AWlen = '0; 117 | top.WStrb = '0; 118 | top.AWburst = '0; 119 | top.WData = '0; 120 | top.ARid = '0; 121 | top.ARaddr = '0; 122 | top.ARlen = '0; 123 | top.ARsize = '0; 124 | top.ARburst = '0; 125 | #10; 126 | top.reset = 1'b1; 127 | endtask 128 | 129 | 130 | 131 | ///////////////////////////////////////////////////////////Tasks for Performing the Burst Read , Write Operations-\\////////////////////////////////////// 132 | 133 | 134 | 135 | 136 | /////////////////////////////////// 1. Task for 'Alternate write and read transactions' ///////////////////////////////////////////////////////////////////// 137 | 138 | task burst_write_read(input bit [3:0] rand_awid, input bit [31:0] rand_awaddr_valid, input bit [31:0] rand_awaddr_invalid, input bit [31:0] rand_awaddr_readonly, input bit [31:0] rand_wdata, input bit [31:0] rand_araddr_valid, input bit [31:0] rand_araddr_invalid, input bit [3:0] rand_arid ); 139 | 140 | for(b=2'b10;b<2'b11;b++) begin 141 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 142 | top.AWid = rand_awid; 143 | top.AWaddr = 32'hddd; //Valid write address; 144 | top.AWburst = top.AWburst + b; 145 | top.AWsize = 3'b010; 146 | top.AWlen = 4'b0011; 147 | top.WStrb = 4'b1111; 148 | for(i='0;i<=top.AWlen;i=i+4'b1) 149 | begin 150 | wait(intf.WVALID) 151 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 152 | top.WData = rand_wdata; 153 | wait(!intf.WVALID); 154 | end 155 | wait(intf.BREADY) 156 | repeat(2) @(posedge top.clock); 157 | 158 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 159 | top.AWid = rand_awid; 160 | top.ARid = rand_arid; 161 | top.AWaddr = 32'hccc; //rand_awaddr_valid; 162 | top.ARaddr = 32'hddd; //rand_araddr_valid; 163 | top.AWburst = top.AWburst + b; 164 | top.ARburst = top.ARburst + b; 165 | top.AWsize = 3'b010; 166 | top.ARsize = 3'b010; 167 | top.AWlen = 4'b0011; 168 | top.ARlen = 4'b0011; 169 | top.WStrb = 4'b1111; 170 | for(i='0;i<=top.AWlen;i=i+4'b1) begin 171 | wait(intf.WVALID) 172 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 173 | top.WData = rand_wdata; 174 | wait(!intf.WVALID); 175 | end 176 | wait(intf.BREADY) 177 | repeat(2) @(posedge top.clock); 178 | 179 | 180 | 181 | 182 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 183 | top.AWid = rand_awid; 184 | top.ARid = rand_arid; 185 | top.AWaddr = 32'hbbb;//valid write address 186 | top.ARaddr = 32'hccc;//valid read address 187 | top.AWburst = top.AWburst + b; 188 | top.ARburst = top.ARburst + b; 189 | top.AWsize = 3'b010; 190 | top.ARsize = 3'b010; 191 | top.AWlen = 4'b0011; 192 | top.ARlen = 4'b0011; 193 | top.WStrb = 4'b1111; 194 | for(i='0;i<=top.AWlen;i=i+4'b1) begin 195 | wait(intf.WVALID) 196 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 197 | top.WData = rand_wdata; 198 | wait(!intf.WVALID); 199 | end//i_for 200 | wait(intf.BREADY) 201 | repeat(2) @(posedge top.clock); 202 | 203 | 204 | 205 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 206 | top.AWid = rand_awid; 207 | top.ARid = rand_arid; 208 | top.AWaddr = 32'haaa;//valid write address 209 | top.ARaddr = 32'hbbb;//valid read address 210 | top.AWburst = top.AWburst + b; 211 | top.ARburst = top.ARburst + b; 212 | top.AWsize = 3'b010; 213 | top.ARsize = 3'b010; 214 | top.AWlen = 4'b0011; 215 | top.ARlen = 4'b0011; 216 | top.WStrb = 4'b1111; 217 | for(i='0;i<=top.AWlen;i=i+4'b1) begin 218 | wait(intf.WVALID) 219 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 220 | top.WData = rand_wdata; 221 | wait(!intf.WVALID); 222 | end//i_for 223 | wait(intf.BREADY) 224 | repeat(2) @(posedge top.clock); 225 | 226 | 227 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 228 | top.AWid = rand_awid; 229 | top.ARid = rand_arid; 230 | top.AWaddr = 32'h999;//Valid write address 231 | top.ARaddr = 32'haaa;//Valid read address 232 | top.AWburst = top.AWburst + b; 233 | top.ARburst = top.ARburst + b; 234 | top.AWsize = 3'b010; 235 | top.ARsize = 3'b010; 236 | top.AWlen = 4'b0011; 237 | top.ARlen = 4'b0011; 238 | top.WStrb = 4'b1111; 239 | for(i='0;i<=top.AWlen;i=i+4'b1) begin 240 | wait(intf.WVALID) 241 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 242 | top.WData = rand_wdata; 243 | wait(!intf.WVALID); 244 | end 245 | wait(intf.BREADY) 246 | repeat(2) @(posedge top.clock); 247 | 248 | end 249 | endtask 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | ////////////////////////////////2. Valid Read Operation /////////////////////////////////////////////////////// 273 | 274 | task burst_read(input bit [3:0] rand_awid, input bit [31:0] rand_awaddr_valid, input bit [31:0] rand_awaddr_invalid, input bit [31:0] rand_awaddr_readonly, input bit [31:0] rand_wdata, input bit [31:0] rand_araddr_valid, input bit [31:0] rand_araddr_invalid, input bit [3:0] rand_arid ); 275 | 276 | 277 | for(x='0;x<2'b11;x++) begin 278 | for(y='0;y<=3'b010;y++) begin 279 | if(x!=2'b10) begin 280 | for(z='0;z<=4'b1111;z++) begin 281 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 282 | top.ARid = 4'b1;//id 283 | top.ARaddr = 32'ha11;// Valid Write address 284 | top.ARburst = top.ARburst + x; 285 | top.ARsize = top.ARsize + y; 286 | top.ARlen = top.ARlen + z; 287 | wait (intf.RLAST) 288 | repeat(3) @(posedge top.clock); 289 | end 290 | end 291 | else 292 | begin 293 | for(p=4'b1;p<=4'b0100;p++) 294 | begin 295 | l=((2**(p))-1); 296 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 297 | top.ARid = 4'b1;//id 298 | top.ARaddr = 32'ha11;// Valid Read address 299 | top.ARburst = top.ARburst + x; 300 | top.ARsize = top.ARsize + y; 301 | top.ARlen = top.ARlen + l; 302 | wait (intf.RLAST) 303 | repeat(3) @(posedge top.clock); 304 | end 305 | end 306 | end 307 | end 308 | 309 | endtask 310 | 311 | 312 | ///////////////////////////////// 3.Writing to a read only location ////////////////////////////////////////////////// 313 | 314 | task burst_write_readonly(input bit [3:0] rand_awid, input bit [31:0] rand_awaddr_valid, input bit [31:0] rand_awaddr_invalid, input bit [31:0] rand_awaddr_readonly, input bit [31:0] rand_wdata, input bit [31:0] rand_araddr_valid, input bit [31:0] rand_araddr_invalid, input bit [3:0] rand_arid ); 315 | 316 | for(n=0;n<10;n++) begin 317 | for(b=2'b00;b<2'b11;b++) begin 318 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 319 | top.AWid = rand_awid; 320 | top.AWaddr = rand_awaddr_readonly; 321 | top.AWburst = top.AWburst + b; 322 | top.AWsize = 3'b010; 323 | top.AWlen = 4'b0011; 324 | top.WStrb = 4'b1111; 325 | for(i='0;i<=top.AWlen;i=i+4'b1) 326 | begin 327 | 328 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 329 | top.WData = rand_wdata; 330 | 331 | end 332 | wait(intf.BREADY) 333 | repeat(2) @(posedge top.clock); 334 | end 335 | end 336 | endtask 337 | 338 | 339 | 340 | ///////////////////////////////////4. Writing to invalid address ////////////////////////////////////////////////////// 341 | 342 | task burst_write_invalid(input bit [3:0] rand_awid, input bit [31:0] rand_awaddr_valid, input bit [31:0] rand_awaddr_invalid, input bit [31:0] rand_awaddr_readonly, input bit [31:0] rand_wdata, input bit [31:0] rand_araddr_valid, input bit [31:0] rand_araddr_invalid, input bit [3:0] rand_arid ); 343 | 344 | for(n=0;n<10;n++) begin 345 | for(b=2'b00;b<2'b11;b++) begin 346 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 347 | top.AWid = rand_awid; 348 | top.AWaddr = rand_awaddr_invalid; 349 | top.AWburst = top.AWburst + b; 350 | top.AWsize = 3'b010; 351 | top.AWlen = 4'b0011; 352 | top.WStrb = 4'b1111; 353 | for(i='0;i<=top.AWlen;i=i+4'b1) 354 | begin 355 | 356 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 357 | top.WData = rand_wdata; 358 | 359 | end 360 | wait(intf.BREADY) 361 | repeat(2) @(posedge top.clock); 362 | end 363 | end 364 | endtask 365 | 366 | 367 | 368 | /////////////////////////////// 5.Reading from invalid address ///////////////////////////////////////////////////////////////// 369 | 370 | task burst_read_invalid(input bit [3:0] rand_awid, input bit [31:0] rand_awaddr_valid, input bit [31:0] rand_awaddr_invalid, input bit [31:0] rand_awaddr_readonly, input bit [31:0] rand_wdata, input bit [31:0] rand_araddr_valid, input bit [31:0] rand_araddr_invalid, input bit [3:0] rand_arid ); 371 | 372 | for(n=0;n<10;n++) begin 373 | for(x='0;x<2'b11;x++) begin //for each burst type 374 | stimulus(rand_awid,rand_awaddr_valid,rand_awaddr_invalid,rand_awaddr_readonly,rand_wdata,rand_araddr_valid,rand_araddr_invalid,rand_arid); 375 | top.ARid = rand_arid; 376 | top.ARaddr = rand_araddr_invalid; 377 | top.ARburst = top.ARburst + x; 378 | top.ARsize = 3'b010; 379 | top.ARlen = 4'b0011; 380 | wait (intf.RLAST) 381 | repeat(3) @(posedge top.clock); 382 | end 383 | end 384 | 385 | endtask 386 | 387 | 388 | 389 | 390 | 391 | endclass 392 | `endif -------------------------------------------------------------------------------- /AXI_Questa/monitor.sv: -------------------------------------------------------------------------------- 1 | `include"driver.sv" 2 | `include"MasterSlaveAxiInterface.sv" 3 | 4 | `timescale 1ns/1ns 5 | 6 | 7 | `ifndef mon 8 | `define mon 9 | class monitor; 10 | virtual axi intf; 11 | 12 | driver dv; 13 | function new(virtual axi intf); 14 | begin 15 | this.intf = intf; 16 | end 17 | endfunction 18 | 19 | 20 | task start(); 21 | forever 22 | @(posedge top.clock) 23 | begin 24 | $display("*************************** MONITOR OUTPUT ********************************************* "); 25 | $display("###Write Data#### : %b",intf.WDATA); 26 | $display("###Read Data#### : %b",intf.RDATA); 27 | $display("***************************************************************************************** "); 28 | end 29 | 30 | endtask 31 | endclass 32 | 33 | `endif -------------------------------------------------------------------------------- /AXI_Questa/run.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vmap work work 3 | vlog {../AXI_Questa/MasterSlaveAxiInterface.sv} 4 | vlog {../AXI_Questa/Master_Axi3Protocol.sv} 5 | vlog {../AXI_Questa/Slave_Axi3Protocol.sv} 6 | vlog {../AXI_Questa/Top_HDL.sv} 7 | vlog {../AXI_Questa/monitor.sv} 8 | vlog {../AXI_Questa/assertions.sv} 9 | vlog {../AXI_Questa/Top_HVL.sv} 10 | vlog {../AXI_Questa/VE.sv} 11 | vlog {../AXI_Questa/driver.sv} 12 | vlog {../AXI_Questa/testcase.sv} 13 | vsim -coverage -novopt top 14 | vsim work.top -autoexclusionsdisable=fsm 15 | add wave -position insertpoint sim:/top/intf/* 16 | run 700000 -------------------------------------------------------------------------------- /AXI_Questa/testcase.sv: -------------------------------------------------------------------------------- 1 | `include"driver.sv" 2 | `include"MasterSlaveAxiInterface.sv" 3 | `include"VE.sv" 4 | 5 | 6 | `timescale 1ns/1ns 7 | 8 | program testcase(axi intf); 9 | environment env = new(intf); 10 | reg [3:0] rand_awid; 11 | reg [31:0] rand_awaddr_valid; 12 | reg [31:0] rand_awaddr_invalid; 13 | reg [31:0] rand_awaddr_readonly; 14 | reg [31:0] rand_wdata; 15 | reg [31:0] rand_araddr_valid; 16 | reg [31:0] rand_araddr_invalid; 17 | reg [3:0] rand_arid; 18 | 19 | initial begin 20 | 21 | //Calling reset task from the driver. 22 | env.drvr.reset_enable(); 23 | 24 | 25 | //Calling burst alternate write and read task of the driver- with stimulus generating the random values inside the driver 26 | env.drvr.burst_write_read(rand_awid, rand_awaddr_valid, rand_awaddr_invalid, rand_awaddr_readonly, rand_wdata, rand_araddr_valid, rand_araddr_invalid, rand_arid ); 27 | #10; 28 | /* 29 | //Calling Burst Read task of the driver- with stimulus generating the random values inside the driver 30 | env.drvr.burst_read(rand_awid, rand_awaddr_valid, rand_awaddr_invalid, rand_awaddr_readonly, rand_wdata, rand_araddr_valid, rand_araddr_invalid, rand_arid ); 31 | #10; 32 | 33 | //Calling Burst Write for readonly address range -with stimulus generating the random values inside the driver 34 | env.drvr.burst_write_readonly(rand_awid, rand_awaddr_valid, rand_awaddr_invalid, rand_awaddr_readonly, rand_wdata, rand_araddr_valid, rand_araddr_invalid, rand_arid ); 35 | #10; 36 | 37 | //Calling Burst Write Invalid address range -with stimulus generating the random values inside the driver 38 | env.drvr.burst_write_invalid(rand_awid, rand_awaddr_valid, rand_awaddr_invalid, rand_awaddr_readonly, rand_wdata, rand_araddr_valid, rand_araddr_invalid, rand_arid ); 39 | #10; 40 | 41 | //Calling Burst Read from Invalid address range - with stimulus generating the random values inside the driver 42 | env.drvr.burst_read_invalid(rand_awid, rand_awaddr_valid, rand_awaddr_invalid, rand_awaddr_readonly, rand_wdata, rand_araddr_valid, rand_araddr_invalid, rand_arid );*/ 43 | #10; 44 | 45 | $finish; 46 | end 47 | 48 | initial begin 49 | env.mntr.start(); 50 | end 51 | 52 | 53 | 54 | endprogram -------------------------------------------------------------------------------- /Emulation/Makefile: -------------------------------------------------------------------------------- 1 | 2 | #For cleaning all the libraries 3 | all: clean lib analyze vmwclk compile run view 4 | 5 | #create work library for project and map the library to default work library 6 | lib: 7 | vellib work 8 | velmap work ./work 9 | 10 | #extracts information from RTL files for compilation 11 | analyze: 12 | -velcomp 13 | @echo -e "\nMakeInfo: You may get an error informing vmw.clk.generated file is missing if you are running this the first time. \n\tThis is normal, do not panic! You will generate this file using GUI in the next step\n" 14 | 15 | #clock from clock specification 16 | 17 | vmwclk: 18 | @echo -e "\nMakeInfo: Now Use velview to create vmw.clk clock/IO specification file. Follow steps from Standalone Flow guide. \n\t\tPress enter to continue....." 19 | @read 20 | velview 21 | #compile DUT+TB 22 | compile: 23 | velcomp -start_after rtlc 24 | #launches velrun tool and begin emulation 25 | run: 26 | velrun -nac -c -do run.do 27 | @echo -e "\nMakeInfo: Emulation run successful!" 28 | #open velview to debug 29 | view: 30 | @echo -e "\nMakeInfo: Will open velview GUI now and add wave/signals using do file" 31 | velview -do view.do 32 | 33 | clean: 34 | rm -rf edsenv debussy.cfg DEBUG_AllBoardsInfos_Host_0.txt veloce.log veloce.med veloce.map veloce.wave velrunopts.ini work 35 | 36 | -------------------------------------------------------------------------------- /Emulation/MasterSlaveAxiInterface.sv: -------------------------------------------------------------------------------- 1 | 2 | interface AXI; 3 | // pragma attribute axi partition_interface_xif 4 | 5 | //logic resetn; 6 | logic AWREADY; 7 | logic AWVALID; 8 | logic [1:0] AWBURST; 9 | logic [2:0] AWSIZE; 10 | logic [3:0] AWLEN; 11 | logic [31:0] AWADDR; 12 | logic [3:0] AWID; 13 | logic WREADY;// data write channel 14 | logic WVALID; 15 | logic WLAST; 16 | logic [3:0] WSTRB; 17 | logic [31:0] WDATA; 18 | logic [3:0] WID; 19 | logic [3:0] BID;//write response channel 20 | logic [1:0] BRESP; 21 | logic BVALID; 22 | logic BREADY; 23 | logic ARREADY;// read address channel 24 | logic [3:0] ARID; 25 | logic [31:0] ARADDR; 26 | logic [3:0] ARLEN; 27 | logic [2:0] ARSIZE; 28 | logic [1:0] ARBURST; 29 | logic ARVALID; 30 | logic [3:0] RID;// read data channel 31 | logic [31:0] RDATA; 32 | logic [1:0] RRESP; 33 | logic RLAST; 34 | logic RVALID; 35 | logic RREADY; 36 | modport master( 37 | //input resetn, 38 | input AWREADY, 39 | output AWVALID, 40 | output AWBURST, 41 | output AWSIZE, 42 | output AWLEN, 43 | output AWADDR, 44 | output AWID, 45 | input WREADY,// data write channel 46 | output WVALID, 47 | output WLAST, 48 | output WSTRB, 49 | output WDATA, 50 | output WID, 51 | input BID,// write response channel 52 | input BRESP, 53 | input BVALID, 54 | output BREADY, 55 | input ARREADY,// read address channel 56 | output ARID, 57 | output ARADDR, 58 | output ARLEN, 59 | output ARSIZE, 60 | output ARBURST, 61 | output ARVALID, 62 | input RID,// read data channel 63 | input RDATA, 64 | input RRESP, 65 | input RLAST, 66 | input RVALID, 67 | output RREADY 68 | ); 69 | modport slave( 70 | //input resetn, 71 | output AWREADY, // write address channel 72 | input AWVALID, 73 | input AWBURST, 74 | input AWSIZE, 75 | input AWLEN, 76 | input AWADDR, 77 | input AWID, 78 | output WREADY,// data write channel 79 | input WVALID, 80 | input WLAST, 81 | input WSTRB, 82 | input WDATA, 83 | input WID, 84 | output BID,// write response channel 85 | output BRESP, 86 | output BVALID, 87 | input BREADY, 88 | output ARREADY,// read address channel 89 | input ARID, 90 | input ARADDR, 91 | input ARLEN, 92 | input ARSIZE, 93 | input ARBURST, 94 | input ARVALID, 95 | output RID,// read data channel 96 | output RDATA, 97 | output RRESP, 98 | output RLAST, 99 | output RVALID, 100 | input RREADY 101 | ); 102 | endinterface 103 | -------------------------------------------------------------------------------- /Emulation/Master_Axi3Protocol.sv: -------------------------------------------------------------------------------- 1 | 2 | module AXI_Master_emulation( 3 | input clock, reset, 4 | AXI.master masterintf, 5 | input logic [31:0] AWaddr,//sending inputs to master through AXI protocol 6 | input logic [3:0] AWlen, 7 | input logic [31:0] WData, 8 | input logic [3:0] AWid, 9 | input logic [3:0] WStrb, 10 | input logic [3:0] ARid, 11 | input logic [3:0] ARlen, 12 | input logic [2:0] AWsize, 13 | input logic [1:0] AWburst, 14 | input logic [31:0] ARaddr, 15 | input logic [2:0] ARsize, 16 | input logic [1:0] ARburst, 17 | output logic AWREADY_tb_m,//inputs drom slave to master. 18 | output logic WREADY_tb_m, 19 | output logic [3:0] BID_tb_m, 20 | output logic [1:0] BRESP_tb_m, 21 | output logic BVALID_tb_m, 22 | output logic ARREADY_tb_m, 23 | output logic [3:0] RID_tb_m, 24 | output logic [31:0] RDATA_tb_m, 25 | output logic [1:0] RRESP_tb_m, 26 | output logic RLAST_tb_m, 27 | output logic RVALID_tb_m); 28 | 29 | 30 | logic [7:0] read_memory [4096];//instantiating 2D array 31 | //pragma attribute read_memory ram_block 1 //for emulator 32 | assign AWREADY_tb_m = masterintf.AWREADY;//sending inputs from slave to master 33 | assign WREADY_tb_m = masterintf.WREADY; 34 | assign BID_tb_m = masterintf.BID; 35 | assign BRESP_tb_m = masterintf.BRESP; 36 | assign BVALID_tb_m = masterintf.BVALID; 37 | assign ARREADY_tb_m = masterintf.ARREADY; 38 | assign RID_tb_m = masterintf.RID; 39 | assign RDATA_tb_m = masterintf.RDATA; 40 | assign RRESP_tb_m = masterintf.RRESP; 41 | assign RLAST_tb_m = masterintf.RLAST; 42 | assign RVALID_tb_m = masterintf.RVALID; 43 | //master write address 44 | enum logic [1:0] { 45 | MWRITE_IDLE=2'b00, 46 | MWRITE_START, 47 | MWRITE_WAIT, 48 | MWRITE_VALID } MAWRITEState, MAWRITENext_state; 49 | 50 | // master write data 51 | logic [4:0] Count, NextCount; 52 | enum logic [2:0] {MWRITE_INIT=3'b000, 53 | MWRITE_TRANSFER, 54 | MWRITE_READY, 55 | MDWRITE_VALID, 56 | MWRITE_ERROR} MWRITEState, MWRITENext_state; 57 | 58 | //master write response 59 | enum logic [1:0] { MASTERB_IDLE=2'b00, 60 | MASTERB_START, 61 | MASTERB_READY } MASTERBState, MASTERBNext_state; 62 | 63 | 64 | // master read address 65 | enum logic [2:0] {MREAD_IDLE=3'b000, 66 | MREAD_WAIT, 67 | MREAD_READY, 68 | MREAD_VALID, 69 | MREAD_EXTRA} ARMREADState,ARMREADNext_state; 70 | 71 | // master read data 72 | logic [31:0] slaveaddress, 73 | slaveaddress_r, 74 | slaveaddress_temp, 75 | ARADDR_r; 76 | enum logic [1:0] {MREAD_CLEAR=2'b00, 77 | MREAD_STARTM, 78 | MREAD_READ, 79 | MDREAD_VALID } MREADState,MREADNext_state; 80 | integer wrap_boundary,first_time1, first_time1_next; 81 | 82 | //write address channel 83 | always_ff @(posedge clock or negedge reset) 84 | begin 85 | if(!reset) begin 86 | MAWRITEState <= MWRITE_IDLE; 87 | end 88 | else begin 89 | MAWRITEState <= MAWRITENext_state; 90 | end 91 | end 92 | 93 | always_comb 94 | begin 95 | case(MAWRITEState) 96 | MWRITE_IDLE:begin 97 | masterintf.AWVALID = '0; 98 | masterintf.AWBURST = '0; 99 | masterintf.AWSIZE = '0; 100 | masterintf.AWLEN = '0; 101 | masterintf.AWADDR = '0; 102 | masterintf.AWID = '0; 103 | MAWRITENext_state = MWRITE_START; 104 | end 105 | 106 | MWRITE_START:begin 107 | if(AWaddr > 32'h0) begin 108 | masterintf.AWBURST = AWburst; 109 | masterintf.AWSIZE = AWsize; 110 | masterintf.AWLEN = AWlen; 111 | masterintf.AWADDR = AWaddr; 112 | masterintf.AWID = AWid; 113 | masterintf.AWVALID = 1'b1; 114 | MAWRITENext_state = MWRITE_WAIT; 115 | end 116 | else 117 | MAWRITENext_state = MWRITE_IDLE; 118 | end 119 | 120 | MWRITE_WAIT:begin 121 | if (masterintf.AWREADY) 122 | MAWRITENext_state = MWRITE_VALID; 123 | else 124 | MAWRITENext_state = MWRITE_WAIT; 125 | end 126 | 127 | MWRITE_VALID:begin 128 | masterintf.AWVALID = '0; 129 | if(masterintf.BREADY) 130 | MAWRITENext_state = MWRITE_IDLE; 131 | else 132 | MAWRITENext_state = MWRITE_VALID; 133 | end 134 | endcase 135 | end 136 | 137 | 138 | 139 | //write data channel master 140 | always_ff @(posedge clock or negedge reset) 141 | begin 142 | if(!reset) 143 | begin 144 | MWRITEState <= MWRITE_INIT; 145 | Count <= 4'b0; 146 | end 147 | else 148 | begin 149 | MWRITEState <= MWRITENext_state; 150 | Count <= NextCount; 151 | end 152 | end 153 | 154 | always_comb 155 | begin 156 | case(MWRITEState) 157 | 158 | MWRITE_INIT:begin 159 | masterintf.WID = '0; 160 | masterintf.WDATA = '0; 161 | masterintf.WSTRB = '0; 162 | masterintf.WLAST = '0; 163 | masterintf.WVALID = '0; 164 | NextCount = '0; 165 | if(masterintf.AWREADY == 1) MWRITENext_state = MWRITE_TRANSFER; 166 | else MWRITENext_state = MWRITE_INIT; 167 | end 168 | 169 | MWRITE_TRANSFER:begin 170 | if(AWaddr > 32'h5ff && AWaddr <=32'hfff && AWsize <3'b100) 171 | begin 172 | masterintf.WID = masterintf.AWID; 173 | masterintf.WVALID = '1; 174 | masterintf.WSTRB = WStrb; 175 | masterintf.WDATA = WData; 176 | NextCount = Count + 4'b1; 177 | MWRITENext_state = MWRITE_READY; 178 | end 179 | else begin 180 | NextCount = Count + 4'b1; 181 | MWRITENext_state = MWRITE_ERROR; 182 | end 183 | end 184 | 185 | MWRITE_READY:begin 186 | if(masterintf.WREADY) begin 187 | if(NextCount == (AWlen+1)) masterintf.WLAST = 1'b1; 188 | else masterintf.WLAST = 1'b0; 189 | 190 | MWRITENext_state = MDWRITE_VALID; 191 | end 192 | else MWRITENext_state = MWRITE_READY; 193 | end 194 | 195 | MDWRITE_VALID:begin 196 | masterintf.WVALID = '0; 197 | 198 | if(NextCount == AWlen+1) begin 199 | MWRITENext_state = MWRITE_INIT; 200 | masterintf.WLAST='0; 201 | end 202 | else MWRITENext_state = MWRITE_TRANSFER; 203 | end 204 | 205 | MWRITE_ERROR:begin 206 | if(NextCount == (AWlen+1)) begin 207 | masterintf.WLAST = 1'b1; 208 | MWRITENext_state = MDWRITE_VALID; 209 | end 210 | else begin 211 | masterintf.WLAST = 1'b0; 212 | MWRITENext_state = MWRITE_TRANSFER; 213 | end 214 | end 215 | endcase 216 | end 217 | 218 | 219 | //write response channel master 220 | 221 | always_ff @(posedge clock or negedge reset) begin 222 | if(!reset) begin 223 | MASTERBState <= MASTERB_IDLE; 224 | end 225 | else 226 | MASTERBState <= MASTERBNext_state; 227 | end 228 | 229 | always_comb begin 230 | 231 | case(MASTERBState) 232 | 233 | MASTERB_IDLE:begin 234 | masterintf.BREADY = '0; 235 | MASTERBNext_state = MASTERB_START; 236 | end 237 | 238 | MASTERB_START:begin 239 | if(masterintf.BVALID) begin 240 | MASTERBNext_state = MASTERB_READY; 241 | end 242 | end 243 | 244 | MASTERB_READY:begin 245 | masterintf.BREADY = 1'b1; 246 | MASTERBNext_state = MASTERB_IDLE; 247 | end 248 | endcase 249 | end 250 | 251 | //read address channel master 252 | always_ff @(posedge clock or negedge reset) 253 | begin 254 | if (!reset) begin 255 | ARMREADState <= MREAD_IDLE; 256 | end 257 | else begin 258 | ARMREADState <= ARMREADNext_state; 259 | end 260 | 261 | end 262 | 263 | 264 | always_comb 265 | begin 266 | case (ARMREADState) 267 | MREAD_IDLE:begin 268 | masterintf.ARID = 0; 269 | masterintf.ARADDR = 0; 270 | masterintf.ARLEN = 0; 271 | masterintf.ARSIZE = 0; 272 | masterintf.ARBURST = 0; 273 | masterintf.ARVALID = 0; 274 | ARMREADNext_state = MREAD_WAIT; 275 | end 276 | 277 | MREAD_WAIT:begin 278 | if(ARaddr > 32'h0) begin 279 | masterintf.ARID = ARid; 280 | masterintf.ARADDR = ARaddr; 281 | masterintf.ARLEN = ARlen; 282 | masterintf.ARSIZE = ARsize; 283 | masterintf.ARBURST = ARburst; 284 | masterintf.ARVALID = 1'b1; 285 | ARMREADNext_state = MREAD_READY; 286 | end 287 | else 288 | ARMREADNext_state = MREAD_IDLE; 289 | end 290 | 291 | MREAD_READY:begin 292 | if (masterintf.ARREADY) 293 | ARMREADNext_state = MREAD_VALID; 294 | else 295 | ARMREADNext_state = MREAD_READY; 296 | end 297 | 298 | MREAD_VALID:begin 299 | masterintf.ARVALID = '0; 300 | if(masterintf.RLAST) 301 | ARMREADNext_state = MREAD_EXTRA; 302 | else 303 | ARMREADNext_state = MREAD_VALID; 304 | end 305 | 306 | MREAD_EXTRA:begin 307 | ARMREADNext_state = MREAD_IDLE; 308 | end 309 | endcase 310 | end 311 | 312 | 313 | 314 | //read data channel master 315 | 316 | 317 | always_ff @(posedge clock or negedge reset) 318 | begin 319 | if(!reset) 320 | MREADState <= MREAD_CLEAR; 321 | else begin 322 | MREADState <= MREADNext_state; 323 | first_time1 <= first_time1_next; 324 | end 325 | end 326 | 327 | 328 | always_comb 329 | begin 330 | if(masterintf.ARREADY) 331 | ARADDR_r = ARaddr; 332 | 333 | case(MREADState) 334 | MREAD_CLEAR:begin 335 | MREADNext_state = MREAD_STARTM; 336 | masterintf.RREADY = '0; 337 | first_time1_next = 0; 338 | slaveaddress = '0; 339 | slaveaddress_r='0; 340 | end 341 | 342 | MREAD_STARTM:begin 343 | if(masterintf.RVALID) begin 344 | MREADNext_state = MREAD_READ; 345 | slaveaddress = slaveaddress_r; 346 | end 347 | else 348 | MREADNext_state = MREAD_STARTM; 349 | end 350 | 351 | MREAD_READ:begin 352 | MREADNext_state = MDREAD_VALID; 353 | masterintf.RREADY= '1; //setting RREADY to 1 to say to slave that master is ready to receive valid data. 354 | 355 | case(ARburst) 356 | 2'b00:begin 357 | slaveaddress = ARADDR_r; 358 | case (ARsize) 359 | 3'b000: begin 360 | read_memory[slaveaddress] = masterintf.RDATA[7:0]; 361 | end 362 | 3'b001: begin 363 | read_memory[slaveaddress] = masterintf.RDATA[7:0]; 364 | read_memory[slaveaddress+1] = masterintf.RDATA[15:8]; 365 | end 366 | 3'b010: begin 367 | read_memory[slaveaddress] = masterintf.RDATA[7:0]; 368 | read_memory[slaveaddress+1] = masterintf.RDATA[15:8]; 369 | read_memory[slaveaddress+2] = masterintf.RDATA[23:16]; 370 | read_memory[slaveaddress+3] = masterintf.RDATA[31:24]; 371 | end 372 | endcase 373 | end 374 | 375 | 2'b01:begin 376 | if(first_time1 == 0) begin 377 | slaveaddress = ARADDR_r; 378 | first_time1_next = 1; 379 | end 380 | else 381 | first_time1_next = first_time1; 382 | 383 | if(masterintf.RLAST == 1) 384 | first_time1_next = 0; 385 | else 386 | first_time1_next = first_time1; 387 | 388 | case (ARsize) 389 | 3'b000: begin 390 | read_memory[slaveaddress] = masterintf.RDATA[7:0]; 391 | end 392 | 3'b001: begin 393 | read_memory[slaveaddress] = masterintf.RDATA[7:0]; 394 | read_memory[slaveaddress+1] = masterintf.RDATA[15:8]; 395 | slaveaddress_r = slaveaddress + 2; 396 | end 397 | 3'b010: begin 398 | read_memory[slaveaddress] = masterintf.RDATA[7:0]; 399 | read_memory[slaveaddress+1] = masterintf.RDATA[15:8]; 400 | read_memory[slaveaddress+2] = masterintf.RDATA[23:16]; 401 | read_memory[slaveaddress+3] = masterintf.RDATA[31:24]; 402 | slaveaddress_r = slaveaddress + 4; 403 | end 404 | endcase 405 | end 406 | 2'b10:begin 407 | if(first_time1 == 0) begin 408 | slaveaddress = ARADDR_r; 409 | first_time1_next = 1; 410 | end 411 | else 412 | first_time1_next = first_time1; 413 | 414 | if(masterintf.RLAST == 1) 415 | first_time1_next = 0; 416 | else 417 | first_time1_next = first_time1; 418 | 419 | case(ARlen) 420 | 4'b0001:begin 421 | case(ARsize) 422 | 3'b000: begin 423 | wrap_boundary = 2 * 1; 424 | end 425 | 3'b001: begin 426 | wrap_boundary = 2 * 2; 427 | end 428 | 3'b010: begin 429 | wrap_boundary = 2 * 4; 430 | end 431 | endcase 432 | end 433 | 434 | 4'b0011: begin 435 | case(ARsize) 436 | 3'b000: begin 437 | wrap_boundary = 4 * 1; 438 | end 439 | 3'b001: begin 440 | wrap_boundary = 4 * 2; 441 | end 442 | 3'b010: begin 443 | wrap_boundary = 4 * 4; 444 | end 445 | endcase 446 | end 447 | 448 | 4'b0111:begin 449 | case(ARsize) 450 | 3'b000: begin 451 | wrap_boundary = 8 * 1; 452 | end 453 | 3'b001: begin 454 | wrap_boundary = 8 * 2; 455 | end 456 | 3'b010: begin 457 | wrap_boundary = 8 * 4; 458 | end 459 | endcase 460 | end 461 | 462 | 4'b1111: begin 463 | case(ARsize) 464 | 3'b000: begin 465 | wrap_boundary = 16 * 1; 466 | end 467 | 3'b001: begin 468 | wrap_boundary = 16 * 2; 469 | end 470 | 3'b010: begin 471 | wrap_boundary = 16 * 4; 472 | end 473 | endcase 474 | end 475 | endcase 476 | 477 | case(ARsize) 478 | 3'b000: begin 479 | read_memory[slaveaddress] = masterintf.RDATA[7:0]; 480 | slaveaddress_temp = slaveaddress + 1; 481 | 482 | if(slaveaddress_temp % wrap_boundary == 0) 483 | slaveaddress_r = slaveaddress_temp - wrap_boundary; 484 | else 485 | slaveaddress_r = slaveaddress_temp; 486 | end 487 | 488 | 3'b001: begin 489 | read_memory[slaveaddress] = masterintf.RDATA[7:0]; 490 | slaveaddress_temp = slaveaddress + 1; 491 | 492 | if(slaveaddress_temp % wrap_boundary == 0) 493 | slaveaddress_r = slaveaddress_temp - wrap_boundary; 494 | else 495 | slaveaddress_r = slaveaddress_temp; 496 | 497 | read_memory[slaveaddress_r] = masterintf.RDATA[15:8]; 498 | slaveaddress_temp = slaveaddress_r + 1; 499 | 500 | if(slaveaddress_temp % wrap_boundary == 0) 501 | slaveaddress_r = slaveaddress_temp - wrap_boundary; 502 | else 503 | slaveaddress_r = slaveaddress_temp; 504 | end 505 | 506 | 3'b010: begin 507 | read_memory[slaveaddress] = masterintf.RDATA[7:0]; 508 | slaveaddress_temp = slaveaddress + 1; 509 | 510 | if(slaveaddress_temp % wrap_boundary == 0) 511 | slaveaddress_r = slaveaddress_temp - wrap_boundary; 512 | else 513 | slaveaddress_r = slaveaddress_temp; 514 | 515 | read_memory[slaveaddress_r] = masterintf.RDATA[15:8]; 516 | slaveaddress_temp = slaveaddress_r + 1; 517 | 518 | if(slaveaddress_temp % wrap_boundary == 0) 519 | slaveaddress_r = slaveaddress_temp - wrap_boundary; 520 | else 521 | slaveaddress_r = slaveaddress_temp; 522 | 523 | read_memory[slaveaddress_r] = masterintf.RDATA[23:16]; 524 | slaveaddress_temp = slaveaddress_r + 1; 525 | 526 | if(slaveaddress_temp % wrap_boundary == 0) 527 | slaveaddress_r = slaveaddress_temp - wrap_boundary; 528 | else 529 | slaveaddress_r = slaveaddress_temp; 530 | 531 | read_memory[slaveaddress_r] = masterintf.RDATA[31:24]; 532 | slaveaddress_temp = slaveaddress_r + 1; 533 | 534 | if(slaveaddress_temp % wrap_boundary == 0) 535 | slaveaddress_r = slaveaddress_temp - wrap_boundary; 536 | else 537 | slaveaddress_r = slaveaddress_temp; 538 | end 539 | endcase 540 | end 541 | 542 | 543 | endcase 544 | end 545 | 546 | MDREAD_VALID:begin 547 | masterintf.RREADY = 1'b0; 548 | if(masterintf.RLAST) begin 549 | //$display("MASTER Mem= %p",read_memory); 550 | MREADNext_state = MREAD_CLEAR; 551 | end 552 | else 553 | MREADNext_state = MREAD_STARTM; 554 | end 555 | endcase 556 | end 557 | endmodule -------------------------------------------------------------------------------- /Emulation/Screenshot (14).png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HunterBitos/Implementation-of-AMBA-AXI3-protocol/cf3431683f6e2a583cfffcf62b15e4e2a9147b62/Emulation/Screenshot (14).png -------------------------------------------------------------------------------- /Emulation/Screenshot (15).png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HunterBitos/Implementation-of-AMBA-AXI3-protocol/cf3431683f6e2a583cfffcf62b15e4e2a9147b62/Emulation/Screenshot (15).png -------------------------------------------------------------------------------- /Emulation/Screenshot (16).png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/HunterBitos/Implementation-of-AMBA-AXI3-protocol/cf3431683f6e2a583cfffcf62b15e4e2a9147b62/Emulation/Screenshot (16).png -------------------------------------------------------------------------------- /Emulation/Slave_Axi3Protocol.sv: -------------------------------------------------------------------------------- 1 | module AXI_Slave_emulation( 2 | input clock, reset, 3 | AXI.slave slaveintf, 4 | output logic AWVALID_tb_s,//inputs received from master 5 | output logic [1:0] AWBURST_tb_s, 6 | output logic [2:0] AWSIZE_tb_s, 7 | output logic [3:0] AWLEN_tb_s, 8 | output logic [31:0] AWADDR_tb_s, 9 | output logic [3:0] AWID_tb_s, 10 | output logic WVALID_tb_s, 11 | output logic WLAST_tb_s, 12 | output logic [3:0] WSTRB_tb_s, 13 | output logic [31:0] WDATA_tb_s, 14 | output logic [3:0] WID_tb_s, 15 | output logic BREADY_tb_s, 16 | output logic [3:0] ARID_tb_s, 17 | output logic [31:0] ARADDR_tb_s, 18 | output logic [3:0] ARLEN_tb_s, 19 | output logic [2:0] ARSIZE_tb_s, 20 | output logic [1:0] ARBURST_tb_s, 21 | output logic ARVALID_tb_s, 22 | output logic RREADY_tb_s 23 | ); 24 | 25 | logic [4095:0][7:0] slave_memory ;//instantiating a 2D array 26 | //pragma attribute slave_mem ram_block 1 //for emulator 27 | assign AWVALID_tb_s = slaveintf.AWVALID;//passing inputs from master to slave 28 | assign AWBURST_tb_s = slaveintf.AWBURST; 29 | assign AWSIZE_tb_s = slaveintf.AWSIZE; 30 | assign AWLEN_tb_s = slaveintf.AWLEN; 31 | assign AWADDR_tb_s = slaveintf.AWADDR; 32 | assign AWID_tb_s = slaveintf.AWID; 33 | assign WVALID_tb_s = slaveintf.WVALID; 34 | assign WLAST_tb_s = slaveintf.WLAST; 35 | assign WSTRB_tb_s = slaveintf.WSTRB; 36 | assign WDATA_tb_s = slaveintf.WDATA; 37 | assign WID_tb_s = slaveintf.WID; 38 | assign BREADY_tb_s = slaveintf.BREADY; 39 | assign ARID_tb_s = slaveintf.ARID; 40 | assign ARADDR_tb_s = slaveintf.ARADDR; 41 | assign ARLEN_tb_s = slaveintf.ARLEN; 42 | assign ARSIZE_tb_s = slaveintf.ARSIZE; 43 | assign ARBURST_tb_s = slaveintf.ARBURST; 44 | assign ARVALID_tb_s = slaveintf.ARVALID; 45 | assign RREADY_tb_s = slaveintf.RREADY; 46 | 47 | //slave write address 48 | enum logic [1:0] { WSLAVE_IDLE=2'b00, 49 | WSLAVE_START, 50 | WSLAVE_READY } WRITEADDR_STATE, WRITEADDR_NEXTSTATE; 51 | //slave write data 52 | logic [31:0] AWADDR_r; 53 | integer first_time, first_time_next2,wrap_boundary; 54 | logic [31:0] masteraddress, masteraddress_reg, masteraddress_temp; 55 | enum logic [1:0]{WSLAVE_INIT=2'b00, 56 | WDSLAVE_START, 57 | WDSLAVE_READY, 58 | WDSLAVE_VALID} WRITED_STATE, WRITED_NEXTSTATE; 59 | //slave write response 60 | enum logic [2:0] { RESPONSEB_IDLE=3'b000, 61 | RESPONSEB_LAST, 62 | RESPONSEB_START, 63 | RESPONSEB_WAIT, 64 | RESPONSEB_VALID } SLAVEB_STATE, SLAVEB_NEXTSTATE; 65 | //slave read address 66 | enum logic [1:0] {RSLAVE_IDLE=2'b00, 67 | RSLAVE_WAIT, 68 | RSLAVE_READY} RSLAVE_STATE,RSLAVE_NEXTSTATE; 69 | //slave read data 70 | enum logic [2:0] {RDSLAVE_CLEAR=3'b000, 71 | RDSLAVE_START, 72 | RDSLAVE_WAIT, 73 | RDSLAVE_VALID, 74 | RDSLAVE_ERROR } RDSLAVE_STATE, RDSLAVE_NEXTSTATE; 75 | integer first_time2, first_time2_next,wrap_boundary2; 76 | logic [4:0] Counter, Next_Counter; 77 | logic [31:0] ARADDR_r1, readdata_address,readdata_address_r, readdata_address_temp; 78 | 79 | //write address channel slave 80 | always_ff @(posedge clock or negedge reset) 81 | begin 82 | if(!reset) begin 83 | WRITEADDR_STATE <= WSLAVE_IDLE; 84 | end 85 | else begin 86 | WRITEADDR_STATE <= WRITEADDR_NEXTSTATE; 87 | end 88 | end 89 | 90 | 91 | always_comb 92 | begin 93 | case(WRITEADDR_STATE) 94 | WSLAVE_IDLE:begin 95 | slaveintf.AWREADY = '0; 96 | WRITEADDR_NEXTSTATE = WSLAVE_START; 97 | end 98 | 99 | WSLAVE_START:begin 100 | if(slaveintf.AWVALID) begin 101 | WRITEADDR_NEXTSTATE = WSLAVE_READY; 102 | end 103 | else 104 | WRITEADDR_NEXTSTATE = WSLAVE_START; 105 | end 106 | 107 | WSLAVE_READY:begin 108 | slaveintf.AWREADY = 1'b1; 109 | WRITEADDR_NEXTSTATE = WSLAVE_IDLE; 110 | end 111 | endcase 112 | end 113 | 114 | 115 | 116 | //slave write data channel 117 | 118 | 119 | always_ff @(posedge clock or negedge reset) 120 | begin 121 | if(!reset) begin 122 | WRITED_STATE <= WSLAVE_INIT; 123 | end 124 | else begin 125 | WRITED_STATE <= WRITED_NEXTSTATE; 126 | first_time <= first_time_next2; 127 | end 128 | end 129 | 130 | always_comb 131 | begin 132 | if(slaveintf.AWVALID == 1) 133 | AWADDR_r = slaveintf.AWADDR; 134 | 135 | case(WRITED_STATE) 136 | WSLAVE_INIT:begin 137 | slaveintf.WREADY = 1'b0; 138 | WRITED_NEXTSTATE = WDSLAVE_START; 139 | first_time_next2 = 0; 140 | masteraddress_reg = '0; 141 | masteraddress = '0; 142 | end 143 | 144 | WDSLAVE_START:begin 145 | if(slaveintf.WVALID) begin 146 | WRITED_NEXTSTATE = WDSLAVE_READY; 147 | masteraddress = masteraddress_reg; 148 | end 149 | else begin 150 | WRITED_NEXTSTATE = WDSLAVE_START; 151 | end 152 | end 153 | 154 | WDSLAVE_READY:begin 155 | if(slaveintf.WLAST) begin 156 | WRITED_NEXTSTATE = WSLAVE_INIT; 157 | end 158 | else 159 | WRITED_NEXTSTATE = WDSLAVE_VALID; 160 | slaveintf.WREADY = 1'b1; 161 | 162 | case(slaveintf.AWBURST) 163 | 2'b00:begin 164 | masteraddress = AWADDR_r; 165 | 166 | case (slaveintf.WSTRB) 167 | 4'b0001:begin 168 | slave_memory[masteraddress] = slaveintf.WDATA[7:0]; 169 | end 170 | 171 | 4'b0010:begin 172 | slave_memory[masteraddress] = slaveintf.WDATA[15:8]; 173 | end 174 | 175 | 4'b0100:begin 176 | slave_memory[masteraddress] = slaveintf.WDATA[23:16]; 177 | end 178 | 179 | 4'b1000:begin 180 | slave_memory[masteraddress] = slaveintf.WDATA[31:24]; 181 | end 182 | 183 | 4'b0011:begin 184 | slave_memory[masteraddress] = slaveintf.WDATA[7:0]; 185 | slave_memory[masteraddress+1] = slaveintf.WDATA[15:8]; 186 | end 187 | 188 | 4'b0101:begin 189 | slave_memory[masteraddress] = slaveintf.WDATA[7:0]; 190 | slave_memory[masteraddress+1] = slaveintf.WDATA[23:16]; 191 | end 192 | 193 | 4'b1001:begin 194 | slave_memory[masteraddress] = slaveintf.WDATA[7:0]; 195 | slave_memory[masteraddress+1] = slaveintf.WDATA[31:24]; 196 | end 197 | 198 | 4'b0110:begin 199 | slave_memory[masteraddress] = slaveintf.WDATA[15:0]; 200 | slave_memory[masteraddress+1] = slaveintf.WDATA[23:16]; 201 | end 202 | 203 | 4'b1010:begin 204 | slave_memory[masteraddress] = slaveintf.WDATA[15:8]; 205 | slave_memory[masteraddress+1] = slaveintf.WDATA[31:24]; 206 | end 207 | 208 | 4'b1100:begin 209 | slave_memory[masteraddress] = slaveintf.WDATA[23:16]; 210 | slave_memory[masteraddress+1] = slaveintf.WDATA[31:24]; 211 | end 212 | 213 | 4'b0111:begin 214 | slave_memory[masteraddress] = slaveintf.WDATA[7:0]; 215 | slave_memory[masteraddress+1] = slaveintf.WDATA[15:8]; 216 | slave_memory[masteraddress+2] = slaveintf.WDATA[23:16]; 217 | end 218 | 219 | 4'b1110:begin 220 | slave_memory[masteraddress] = slaveintf.WDATA[15:8]; 221 | slave_memory[masteraddress+1] = slaveintf.WDATA[23:16]; 222 | slave_memory[masteraddress+2] = slaveintf.WDATA[31:24]; 223 | end 224 | 225 | 4'b1011:begin 226 | slave_memory[masteraddress] = slaveintf.WDATA[7:0]; 227 | slave_memory[masteraddress+1] = slaveintf.WDATA[15:8]; 228 | slave_memory[masteraddress+2] = slaveintf.WDATA[31:24]; 229 | end 230 | 231 | 4'b1101:begin 232 | slave_memory[masteraddress] = slaveintf.WDATA[7:0]; 233 | slave_memory[masteraddress+1] = slaveintf.WDATA[23:16]; 234 | slave_memory[masteraddress+2] = slaveintf.WDATA[31:24]; 235 | end 236 | 237 | 4'b1111:begin 238 | slave_memory[masteraddress] = slaveintf.WDATA[7:0]; 239 | slave_memory[masteraddress+1] = slaveintf.WDATA[15:8]; 240 | slave_memory[masteraddress+2] = slaveintf.WDATA [23:16]; 241 | slave_memory[masteraddress+3] = slaveintf.WDATA [31:24]; 242 | end 243 | 244 | 245 | endcase 246 | end 247 | 248 | 2'b01:begin 249 | if(first_time == 0) 250 | begin 251 | masteraddress = AWADDR_r; 252 | first_time_next2 = 1; 253 | end 254 | else 255 | first_time_next2 = first_time; 256 | 257 | if(slaveintf.BREADY == 1) 258 | first_time_next2 = 0; 259 | else 260 | first_time_next2 = first_time; 261 | 262 | case (slaveintf.WSTRB) 263 | 4'b0001:begin 264 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 265 | masteraddress_reg = masteraddress + 1; 266 | end 267 | 268 | 4'b0010:begin 269 | slave_memory[masteraddress] = slaveintf.WDATA [15:8]; 270 | masteraddress_reg = masteraddress + 1; 271 | end 272 | 273 | 4'b0100:begin 274 | slave_memory[masteraddress] = slaveintf.WDATA [23:16]; 275 | masteraddress_reg = masteraddress + 1; 276 | end 277 | 278 | 4'b1000:begin 279 | slave_memory[masteraddress] = slaveintf.WDATA [31:24]; 280 | masteraddress_reg = masteraddress + 1; 281 | end 282 | 283 | 4'b0011:begin 284 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 285 | slave_memory[masteraddress+1] = slaveintf.WDATA [15:8]; 286 | masteraddress_reg = masteraddress + 2; 287 | end 288 | 289 | 4'b0101:begin 290 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 291 | slave_memory[masteraddress+1] = slaveintf.WDATA [23:16]; 292 | masteraddress_reg = masteraddress + 2; 293 | end 294 | 295 | 4'b1001:begin 296 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 297 | slave_memory[masteraddress+1] = slaveintf.WDATA [31:24]; 298 | masteraddress_reg = masteraddress + 2; 299 | end 300 | 301 | 4'b0110:begin 302 | slave_memory[masteraddress] = slaveintf.WDATA [15:0]; 303 | slave_memory[masteraddress+1] = slaveintf.WDATA [23:16]; 304 | masteraddress_reg = masteraddress + 2; 305 | end 306 | 307 | 4'b1010:begin 308 | slave_memory[masteraddress] = slaveintf.WDATA [15:8]; 309 | slave_memory[masteraddress+1] = slaveintf.WDATA [31:24]; 310 | masteraddress_reg = masteraddress + 2; 311 | end 312 | 313 | 4'b1100:begin 314 | slave_memory[masteraddress] = slaveintf.WDATA [23:16]; 315 | slave_memory[masteraddress+1] = slaveintf.WDATA [31:24]; 316 | masteraddress_reg = masteraddress + 2; 317 | end 318 | 319 | 4'b0111:begin 320 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 321 | slave_memory[masteraddress+1] = slaveintf.WDATA [15:8]; 322 | slave_memory[masteraddress+2] = slaveintf.WDATA [23:16]; 323 | masteraddress_reg = masteraddress + 3; 324 | end 325 | 326 | 4'b1110:begin 327 | slave_memory[masteraddress] = slaveintf.WDATA [15:8]; 328 | slave_memory[masteraddress+1] = slaveintf.WDATA [23:16]; 329 | slave_memory[masteraddress+2] = slaveintf.WDATA [31:24]; 330 | masteraddress_reg = masteraddress + 3; 331 | end 332 | 333 | 4'b1011:begin 334 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 335 | slave_memory[masteraddress+1] = slaveintf.WDATA [15:8]; 336 | slave_memory[masteraddress+2] = slaveintf.WDATA [31:24]; 337 | masteraddress_reg = masteraddress + 3; 338 | end 339 | 340 | 4'b1101:begin 341 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 342 | slave_memory[masteraddress+1] = slaveintf.WDATA [23:16]; 343 | slave_memory[masteraddress+2] = slaveintf.WDATA [31:24]; 344 | masteraddress_reg = masteraddress + 3; 345 | end 346 | 347 | 4'b1111:begin 348 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 349 | slave_memory[masteraddress+1] = slaveintf.WDATA [15:8]; 350 | slave_memory[masteraddress+2] = slaveintf.WDATA [23:16]; 351 | slave_memory[masteraddress+3] = slaveintf.WDATA [31:24]; 352 | masteraddress_reg = masteraddress + 4; 353 | end 354 | 355 | endcase 356 | end 357 | 358 | 2'b10:begin 359 | if(first_time == 0) begin 360 | masteraddress = AWADDR_r; 361 | first_time_next2 = 1; 362 | end 363 | else 364 | first_time_next2 = first_time; 365 | if(slaveintf.BREADY == 1) 366 | first_time_next2 = 0; 367 | else 368 | first_time_next2 = first_time; 369 | 370 | case(slaveintf.AWLEN) 371 | 4'b0001:begin 372 | case(slaveintf.AWSIZE) 373 | 3'b000: begin 374 | wrap_boundary = 2 * 1; 375 | end 376 | 3'b001: begin 377 | wrap_boundary = 2 * 2; 378 | end 379 | 3'b010: begin 380 | wrap_boundary = 2 * 4; 381 | end 382 | endcase 383 | end 384 | 385 | 4'b0011:begin 386 | case(slaveintf.AWSIZE) 387 | 3'b000: begin 388 | wrap_boundary = 4 * 1; 389 | end 390 | 3'b001: begin 391 | wrap_boundary = 4 * 2; 392 | end 393 | 3'b010: begin 394 | wrap_boundary = 4 * 4; 395 | end 396 | 397 | endcase 398 | end 399 | 400 | 4'b0111:begin 401 | case(slaveintf.AWSIZE) 402 | 3'b000: begin 403 | wrap_boundary = 8 * 1; 404 | end 405 | 3'b001: begin 406 | wrap_boundary = 8 * 2; 407 | end 408 | 3'b010: begin 409 | wrap_boundary = 8 * 4; 410 | end 411 | 412 | endcase 413 | end 414 | 415 | 4'b1111:begin 416 | case(slaveintf.AWSIZE) 417 | 3'b000: begin 418 | wrap_boundary = 16 * 1; 419 | 420 | end 421 | 3'b001: begin 422 | wrap_boundary = 16 * 2; 423 | end 424 | 3'b010: begin 425 | wrap_boundary = 16 * 4; 426 | end 427 | 428 | endcase 429 | end 430 | endcase 431 | 432 | case(slaveintf.WSTRB) 433 | 4'b0001:begin 434 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 435 | masteraddress_temp = masteraddress + 1; 436 | 437 | if(masteraddress_temp % wrap_boundary == 0) 438 | masteraddress_reg = masteraddress_temp - wrap_boundary; 439 | else 440 | masteraddress_reg = masteraddress_temp; 441 | end 442 | 443 | 4'b0010:begin 444 | slave_memory[masteraddress] = slaveintf.WDATA [15:8]; 445 | masteraddress_temp = masteraddress + 1; 446 | 447 | if(masteraddress_temp % wrap_boundary == 0) 448 | masteraddress_reg = masteraddress_temp - wrap_boundary; 449 | else 450 | masteraddress_reg = masteraddress_temp; 451 | end 452 | 453 | 4'b0100:begin 454 | slave_memory[masteraddress] = slaveintf.WDATA [23:16]; 455 | masteraddress_temp = masteraddress + 1; 456 | 457 | if(masteraddress_temp % wrap_boundary == 0) 458 | masteraddress_reg = masteraddress_temp - wrap_boundary; 459 | else 460 | masteraddress_reg = masteraddress_temp; 461 | end 462 | 463 | 4'b1000:begin 464 | slave_memory[masteraddress] = slaveintf.WDATA [31:24]; 465 | masteraddress_temp = masteraddress + 1; 466 | 467 | if(masteraddress_temp % wrap_boundary == 0) 468 | masteraddress_reg = masteraddress_temp - wrap_boundary; 469 | else 470 | masteraddress_reg = masteraddress_temp; 471 | end 472 | 473 | 4'b0011:begin 474 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 475 | masteraddress_temp = masteraddress + 1; 476 | 477 | if(masteraddress_temp % wrap_boundary == 0) 478 | masteraddress_reg = masteraddress_temp - wrap_boundary; 479 | else 480 | masteraddress_reg = masteraddress_temp; 481 | 482 | slave_memory[masteraddress_reg] = slaveintf.WDATA [15:8]; 483 | masteraddress_temp = masteraddress_reg + 1; 484 | 485 | if(masteraddress_temp % wrap_boundary == 0) 486 | masteraddress_reg = masteraddress_temp - wrap_boundary; 487 | else 488 | masteraddress_reg = masteraddress_temp; 489 | end 490 | 491 | 4'b0101:begin 492 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 493 | masteraddress_temp = masteraddress + 1; 494 | 495 | if(masteraddress_temp % wrap_boundary == 0) 496 | masteraddress_reg = masteraddress_temp - wrap_boundary; 497 | else 498 | masteraddress_reg = masteraddress_temp; 499 | slave_memory[masteraddress_reg] = slaveintf.WDATA [23:16]; 500 | masteraddress_temp = masteraddress_reg + 1; 501 | 502 | if(masteraddress_temp % wrap_boundary == 0) 503 | masteraddress_reg = masteraddress_temp - wrap_boundary; 504 | else 505 | masteraddress_reg = masteraddress_temp; 506 | end 507 | 508 | 4'b1001:begin 509 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 510 | masteraddress_temp = masteraddress + 1; 511 | 512 | if(masteraddress_temp % wrap_boundary == 0) 513 | masteraddress_reg = masteraddress_temp - wrap_boundary; 514 | else 515 | masteraddress_reg = masteraddress_temp; 516 | 517 | slave_memory[masteraddress_reg] = slaveintf.WDATA [31:24]; 518 | masteraddress_temp = masteraddress_reg + 1; 519 | 520 | if(masteraddress_temp % wrap_boundary == 0) 521 | masteraddress_reg = masteraddress_temp - wrap_boundary; 522 | else 523 | masteraddress_reg = masteraddress_temp; 524 | end 525 | 526 | 4'b0110:begin 527 | slave_memory[masteraddress] = slaveintf.WDATA [15:0]; 528 | masteraddress_temp = masteraddress + 1; 529 | 530 | if(masteraddress_temp % wrap_boundary == 0) 531 | masteraddress_reg = masteraddress_temp - wrap_boundary; 532 | else 533 | masteraddress_reg = masteraddress_temp; 534 | 535 | slave_memory[masteraddress_reg] = slaveintf.WDATA [23:16]; 536 | masteraddress_temp = masteraddress_reg + 1; 537 | 538 | if(masteraddress_temp % wrap_boundary == 0) 539 | masteraddress_reg = masteraddress_temp - wrap_boundary; 540 | else 541 | masteraddress_reg = masteraddress_temp; 542 | end 543 | 544 | 4'b1010:begin 545 | slave_memory[masteraddress] = slaveintf.WDATA [15:8]; 546 | masteraddress_temp = masteraddress + 1; 547 | 548 | if(masteraddress_temp % wrap_boundary== 0) 549 | masteraddress_reg = masteraddress_temp - wrap_boundary; 550 | else 551 | masteraddress_reg = masteraddress_temp; 552 | 553 | slave_memory[masteraddress_reg] = slaveintf.WDATA [31:24]; 554 | masteraddress_temp = masteraddress_reg + 1; 555 | 556 | if(masteraddress_temp % wrap_boundary == 0) 557 | masteraddress_reg = masteraddress_temp - wrap_boundary; 558 | else 559 | masteraddress_reg = masteraddress_temp; 560 | end 561 | 562 | 4'b1100:begin 563 | slave_memory[masteraddress] = slaveintf.WDATA [23:16]; 564 | masteraddress_temp = masteraddress + 1; 565 | 566 | if(masteraddress_temp % wrap_boundary == 0) 567 | masteraddress_reg = masteraddress_temp - wrap_boundary; 568 | else 569 | masteraddress_reg = masteraddress_temp; 570 | 571 | slave_memory[masteraddress_reg] = slaveintf.WDATA [31:24]; 572 | masteraddress_temp = masteraddress_reg + 1; 573 | 574 | if(masteraddress_temp % wrap_boundary == 0) 575 | masteraddress_reg = masteraddress_temp - wrap_boundary; 576 | else 577 | masteraddress_reg = masteraddress_temp; 578 | end 579 | 580 | 4'b0111:begin 581 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 582 | masteraddress_temp = masteraddress + 1; 583 | 584 | if(masteraddress_temp % wrap_boundary == 0) 585 | masteraddress_reg = masteraddress_temp - wrap_boundary; 586 | else 587 | masteraddress_reg = masteraddress_temp; 588 | 589 | slave_memory[masteraddress_reg] = slaveintf.WDATA [15:8]; 590 | masteraddress_temp = masteraddress_reg + 1; 591 | 592 | if(masteraddress_temp % wrap_boundary == 0) 593 | masteraddress_reg = masteraddress_temp - wrap_boundary; 594 | else 595 | masteraddress_reg = masteraddress_temp; 596 | 597 | slave_memory[masteraddress_reg] = slaveintf.WDATA [23:16]; 598 | masteraddress_temp = masteraddress_reg + 1; 599 | 600 | if(masteraddress_temp % wrap_boundary == 0) 601 | masteraddress_reg = masteraddress_temp - wrap_boundary; 602 | else 603 | masteraddress_reg = masteraddress_temp; 604 | end 605 | 606 | 4'b1110:begin 607 | slave_memory[masteraddress] = slaveintf.WDATA [15:8]; 608 | masteraddress_temp = masteraddress + 1; 609 | 610 | if(masteraddress_temp % wrap_boundary == 0) 611 | masteraddress_reg = masteraddress_temp - wrap_boundary; 612 | else 613 | masteraddress_reg = masteraddress_temp; 614 | 615 | slave_memory[masteraddress_reg] = slaveintf.WDATA [23:16]; 616 | masteraddress_temp = masteraddress_reg + 1; 617 | 618 | if(masteraddress_temp % wrap_boundary == 0) 619 | masteraddress_reg = masteraddress_temp - wrap_boundary; 620 | else 621 | masteraddress_reg = masteraddress_temp; 622 | 623 | slave_memory[masteraddress_reg] = slaveintf.WDATA [31:24]; 624 | masteraddress_temp = masteraddress_reg + 1; 625 | 626 | if(masteraddress_temp % wrap_boundary == 0) 627 | masteraddress_reg = masteraddress_temp - wrap_boundary; 628 | else 629 | masteraddress_reg = masteraddress_temp; 630 | end 631 | 632 | 4'b1011:begin 633 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 634 | masteraddress_temp = masteraddress + 1; 635 | 636 | if(masteraddress_temp % wrap_boundary == 0) 637 | masteraddress_reg = masteraddress_temp - wrap_boundary; 638 | else 639 | masteraddress_reg = masteraddress_temp; 640 | 641 | slave_memory[masteraddress_reg] = slaveintf.WDATA [15:8]; 642 | masteraddress_temp = masteraddress_reg + 1; 643 | 644 | if(masteraddress_temp % wrap_boundary == 0) 645 | masteraddress_reg = masteraddress_temp - wrap_boundary; 646 | else 647 | masteraddress_reg = masteraddress_temp; 648 | 649 | slave_memory[masteraddress_reg] = slaveintf.WDATA [31:24]; 650 | masteraddress_temp = masteraddress_reg + 1; 651 | 652 | if(masteraddress_temp % wrap_boundary == 0) 653 | masteraddress_reg = masteraddress_temp - wrap_boundary; 654 | else 655 | masteraddress_reg = masteraddress_temp; 656 | end 657 | 4'b1101:begin 658 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 659 | masteraddress_temp = masteraddress + 1; 660 | 661 | if(masteraddress_temp % wrap_boundary == 0) 662 | masteraddress_reg = masteraddress_temp - wrap_boundary; 663 | else 664 | masteraddress_reg = masteraddress_temp; 665 | 666 | slave_memory[masteraddress_reg] = slaveintf.WDATA [23:16]; 667 | masteraddress_temp = masteraddress_reg + 1; 668 | 669 | if(masteraddress_temp % wrap_boundary == 0) 670 | masteraddress_reg = masteraddress_temp - wrap_boundary; 671 | else 672 | masteraddress_reg = masteraddress_temp; 673 | 674 | slave_memory[masteraddress_reg] = slaveintf.WDATA [31:24]; 675 | masteraddress_temp = masteraddress_reg + 1; 676 | 677 | if(masteraddress_temp % wrap_boundary == 0) 678 | masteraddress_reg = masteraddress_temp - wrap_boundary; 679 | else 680 | masteraddress_reg = masteraddress_temp; 681 | end 682 | 683 | 4'b1111: begin 684 | slave_memory[masteraddress] = slaveintf.WDATA [7:0]; 685 | masteraddress_temp = masteraddress + 1; 686 | 687 | if(masteraddress_temp % wrap_boundary == 0) 688 | masteraddress_reg = masteraddress_temp - wrap_boundary; 689 | else 690 | masteraddress_reg = masteraddress_temp; 691 | 692 | slave_memory[masteraddress_reg] = slaveintf.WDATA [15:8]; 693 | masteraddress_temp = masteraddress_reg + 1; 694 | 695 | if(masteraddress_temp % wrap_boundary == 0) 696 | masteraddress_reg = masteraddress_temp - wrap_boundary; 697 | else 698 | masteraddress_reg = masteraddress_temp; 699 | 700 | slave_memory[masteraddress_reg] = slaveintf.WDATA [23:16]; 701 | masteraddress_temp = masteraddress_reg + 1; 702 | 703 | if(masteraddress_temp % wrap_boundary == 0) 704 | masteraddress_reg = masteraddress_temp - wrap_boundary; 705 | else 706 | masteraddress_reg = masteraddress_temp; 707 | 708 | slave_memory[masteraddress_reg] = slaveintf.WDATA [31:24]; 709 | masteraddress_temp = masteraddress_reg + 1; 710 | 711 | if(masteraddress_temp % wrap_boundary == 0) 712 | masteraddress_reg = masteraddress_temp - wrap_boundary; 713 | else 714 | masteraddress_reg = masteraddress_temp; 715 | end 716 | 717 | endcase 718 | end 719 | 720 | 721 | 722 | endcase 723 | //$display("each beat Meme= %p",slave_memory); 724 | end 725 | WDSLAVE_VALID:begin 726 | slaveintf.WREADY = 1'b0; 727 | WRITED_NEXTSTATE = WDSLAVE_START; 728 | end 729 | endcase 730 | end 731 | 732 | //slave write response channel 733 | 734 | always_ff @(posedge clock or negedge reset) 735 | begin 736 | if(!reset) begin 737 | SLAVEB_STATE <= RESPONSEB_IDLE; 738 | end 739 | else 740 | SLAVEB_STATE <= SLAVEB_NEXTSTATE; 741 | end 742 | 743 | 744 | always_comb 745 | begin 746 | case(SLAVEB_STATE) 747 | RESPONSEB_IDLE:begin 748 | slaveintf.BID = '0; 749 | slaveintf.BRESP = '0; 750 | slaveintf.BVALID = '0; 751 | SLAVEB_NEXTSTATE = RESPONSEB_LAST; 752 | end 753 | 754 | RESPONSEB_LAST:begin 755 | if(slaveintf.WLAST) 756 | SLAVEB_NEXTSTATE = RESPONSEB_START; 757 | else 758 | SLAVEB_NEXTSTATE = RESPONSEB_LAST; 759 | end 760 | 761 | RESPONSEB_START:begin 762 | slaveintf.BID = slaveintf.AWID; 763 | if ( slaveintf.AWADDR > 32'h5ff && slaveintf.AWADDR <=32'hfff && slaveintf.AWSIZE < 3'b011 ) 764 | slaveintf.BRESP = 2'b00; 765 | else if(( slaveintf.AWADDR > 32'h1ff && slaveintf.AWADDR <=32'h5ff) || slaveintf.AWSIZE > 3'b010) 766 | slaveintf.BRESP = 2'b10; 767 | else 768 | slaveintf.BRESP = 2'b11; 769 | 770 | slaveintf.BVALID = 1'b1; 771 | SLAVEB_NEXTSTATE = RESPONSEB_WAIT; 772 | end 773 | 774 | RESPONSEB_WAIT:begin 775 | if (slaveintf.BREADY) begin 776 | SLAVEB_NEXTSTATE = RESPONSEB_IDLE; 777 | end 778 | end 779 | endcase 780 | end 781 | 782 | 783 | 784 | 785 | //read address channel slave 786 | 787 | 788 | always_ff @(posedge clock or negedge reset) 789 | begin 790 | if (!reset) begin 791 | RSLAVE_STATE <= RSLAVE_IDLE; 792 | end 793 | else begin 794 | RSLAVE_STATE <= RSLAVE_NEXTSTATE; 795 | end 796 | end 797 | 798 | always_comb 799 | begin 800 | case (RSLAVE_STATE) 801 | RSLAVE_IDLE:begin 802 | slaveintf.ARREADY = '0; 803 | RSLAVE_NEXTSTATE = RSLAVE_WAIT; 804 | end 805 | 806 | RSLAVE_WAIT:begin 807 | if (slaveintf.ARVALID) 808 | RSLAVE_NEXTSTATE = RSLAVE_READY; 809 | else 810 | RSLAVE_NEXTSTATE = RSLAVE_WAIT; 811 | end 812 | 813 | RSLAVE_READY:begin 814 | RSLAVE_NEXTSTATE = RSLAVE_IDLE; 815 | slaveintf.ARREADY = 1'b1; 816 | end 817 | endcase 818 | end 819 | 820 | 821 | 822 | //slave read data channel 823 | always_ff@(posedge clock or negedge reset) 824 | begin 825 | if(!reset) begin 826 | RDSLAVE_STATE <= RDSLAVE_CLEAR; 827 | Counter <= '0; 828 | end 829 | else begin 830 | RDSLAVE_STATE <= RDSLAVE_NEXTSTATE; 831 | Counter <= Next_Counter; 832 | first_time2 <= first_time2_next; 833 | end 834 | end 835 | 836 | always_comb 837 | begin 838 | if(slaveintf.ARVALID) 839 | ARADDR_r1 = slaveintf.ARADDR; 840 | 841 | case(RDSLAVE_STATE) 842 | RDSLAVE_CLEAR:begin 843 | slaveintf.RID = '0; 844 | slaveintf.RDATA = '0; 845 | slaveintf.RRESP = '0; 846 | slaveintf.RLAST = '0; 847 | slaveintf.RVALID = '0; 848 | first_time2_next = 0; 849 | Next_Counter = '0; 850 | readdata_address_r='0; 851 | readdata_address='0; 852 | if(slaveintf.ARVALID) begin 853 | RDSLAVE_NEXTSTATE = RDSLAVE_START; 854 | end 855 | else 856 | RDSLAVE_NEXTSTATE = RDSLAVE_CLEAR; 857 | end 858 | 859 | RDSLAVE_START:begin 860 | if( slaveintf.ARADDR > 32'h1ff && slaveintf.ARADDR <=32'hfff && slaveintf.ARSIZE <3'b100) begin 861 | slaveintf.RID = slaveintf.ARID; 862 | 863 | case(slaveintf.ARBURST) 864 | 2'b00:begin 865 | readdata_address = ARADDR_r1; 866 | case (slaveintf.ARSIZE) 867 | 3'b000:begin 868 | slaveintf.RDATA[7:0] = slave_memory[readdata_address]; 869 | end 870 | 871 | 3'b001:begin 872 | slaveintf.RDATA[7:0] = slave_memory[readdata_address]; 873 | slaveintf.RDATA[15:8] = slave_memory[readdata_address+1]; 874 | end 875 | 876 | 3'b010:begin 877 | slaveintf.RDATA[7:0] = slave_memory[readdata_address]; 878 | slaveintf.RDATA[15:8] = slave_memory[readdata_address+1]; 879 | slaveintf.RDATA[23:16] = slave_memory[readdata_address+2]; 880 | slaveintf.RDATA[31:24] = slave_memory[readdata_address+3]; 881 | end 882 | endcase 883 | end 884 | 885 | 2'b01:begin 886 | if(first_time2 == 0) begin 887 | readdata_address = ARADDR_r1; 888 | first_time2_next = 1; 889 | end 890 | else 891 | first_time2_next = first_time2; 892 | 893 | if(Next_Counter == slaveintf.ARLEN+4'b1) 894 | first_time2_next = 0; 895 | else 896 | first_time2_next = first_time2; 897 | 898 | case (slaveintf.ARSIZE) 899 | 3'b000:begin 900 | slaveintf.RDATA[7:0] = slave_memory[readdata_address]; 901 | end 902 | 903 | 3'b001: begin 904 | slaveintf.RDATA[7:0] = slave_memory[readdata_address]; 905 | slaveintf.RDATA[15:8] = slave_memory[readdata_address+1]; 906 | readdata_address_r = readdata_address + 2; 907 | end 908 | 3'b010: begin 909 | slaveintf.RDATA[7:0] = slave_memory[readdata_address]; 910 | slaveintf.RDATA[15:8] = slave_memory[readdata_address+1]; 911 | slaveintf.RDATA[23:16] = slave_memory[readdata_address+1]; 912 | slaveintf.RDATA[31:24] = slave_memory[readdata_address+1]; 913 | readdata_address_r = readdata_address + 4; 914 | end 915 | endcase 916 | end 917 | 2'b10:begin 918 | if(first_time2 == 0) begin 919 | readdata_address = ARADDR_r1; 920 | first_time2_next = 1; 921 | end 922 | else 923 | first_time2_next = first_time2; 924 | 925 | if(Next_Counter == slaveintf.ARLEN+4'b1) 926 | first_time2_next = 0; 927 | else 928 | first_time2_next = first_time2; 929 | 930 | case( slaveintf.ARLEN) 931 | 4'b0001:begin 932 | case( slaveintf.ARSIZE) 933 | 3'b000:begin 934 | wrap_boundary2 = 2 * 1; 935 | end 936 | 937 | 3'b001:begin 938 | wrap_boundary2 = 2 * 2; 939 | end 940 | 941 | 3'b010:begin 942 | wrap_boundary2 = 2 * 4; 943 | end 944 | 945 | endcase 946 | end 947 | 948 | 4'b0011:begin 949 | case(slaveintf.ARSIZE) 950 | 3'b000:begin 951 | wrap_boundary2 = 4 * 1; 952 | end 953 | 954 | 3'b001:begin 955 | wrap_boundary2 = 4 * 2; 956 | end 957 | 958 | 3'b010:begin 959 | wrap_boundary2 = 4 * 4; 960 | end 961 | 962 | endcase 963 | end 964 | 965 | 4'b0111:begin 966 | case(slaveintf.ARSIZE) 967 | 3'b000:begin 968 | wrap_boundary2 = 8 * 1; 969 | end 970 | 971 | 3'b001:begin 972 | wrap_boundary2 = 8 * 2; 973 | end 974 | 975 | 3'b010:begin 976 | wrap_boundary2 = 8 * 4; 977 | end 978 | 979 | endcase 980 | end 981 | 982 | 4'b1111:begin 983 | case(slaveintf.ARSIZE) 984 | 3'b000:begin 985 | wrap_boundary2 = 16 * 1; 986 | end 987 | 988 | 3'b001:begin 989 | wrap_boundary2 = 16 * 2; 990 | end 991 | 992 | 3'b010:begin 993 | wrap_boundary2 = 16 * 4; 994 | end 995 | endcase 996 | end 997 | endcase 998 | 999 | case(slaveintf.ARSIZE) 1000 | 3'b000:begin 1001 | slaveintf.RDATA[7:0] = slave_memory[readdata_address]; 1002 | readdata_address_temp = readdata_address + 1; 1003 | 1004 | if(readdata_address_temp % wrap_boundary2 == 0) 1005 | readdata_address_r = readdata_address_temp - wrap_boundary2; 1006 | else 1007 | readdata_address_r = readdata_address_temp; 1008 | end 1009 | 1010 | 3'b001:begin 1011 | slaveintf.RDATA[7:0] = slave_memory[readdata_address]; 1012 | readdata_address_temp = readdata_address + 1; 1013 | 1014 | if(readdata_address_temp % wrap_boundary2 == 0) 1015 | readdata_address_r = readdata_address_temp - wrap_boundary2; 1016 | else 1017 | readdata_address_r = readdata_address_temp; 1018 | 1019 | slaveintf.RDATA[15:8] = slave_memory[readdata_address_r]; 1020 | readdata_address_temp = readdata_address_r + 1; 1021 | 1022 | if(readdata_address_temp % wrap_boundary2 == 0) 1023 | readdata_address_r = readdata_address_temp - wrap_boundary2; 1024 | else 1025 | readdata_address_r = readdata_address_temp; 1026 | end 1027 | 1028 | 3'b010:begin 1029 | slaveintf.RDATA[7:0] = slave_memory[readdata_address]; 1030 | readdata_address_temp = readdata_address + 1; 1031 | 1032 | if(readdata_address_temp % wrap_boundary2 == 0) 1033 | readdata_address_r = readdata_address_temp - wrap_boundary2; 1034 | else 1035 | readdata_address_r = readdata_address_temp; 1036 | 1037 | slaveintf.RDATA[15:8] = slave_memory[readdata_address_r]; 1038 | readdata_address_temp = readdata_address_r + 1; 1039 | 1040 | if(readdata_address_temp % wrap_boundary2 == 0) 1041 | readdata_address_r = readdata_address_temp - wrap_boundary2; 1042 | else 1043 | readdata_address_r = readdata_address_temp; 1044 | 1045 | slaveintf.RDATA[23:16] = slave_memory[readdata_address_r]; 1046 | readdata_address_temp = readdata_address_r + 1; 1047 | 1048 | if(readdata_address_temp % wrap_boundary2 == 0) 1049 | readdata_address_r = readdata_address_temp - wrap_boundary2; 1050 | else 1051 | readdata_address_r = readdata_address_temp; 1052 | 1053 | slaveintf.RDATA[31:24] = slave_memory[readdata_address_r]; 1054 | readdata_address_temp = readdata_address_r + 1; 1055 | 1056 | if(readdata_address_temp % wrap_boundary2 == 0) 1057 | readdata_address_r = readdata_address_temp - wrap_boundary2; 1058 | else 1059 | readdata_address_r = readdata_address_temp; 1060 | end 1061 | 1062 | endcase 1063 | end 1064 | endcase 1065 | 1066 | 1067 | 1068 | 1069 | 1070 | slaveintf.RVALID = '1; 1071 | Next_Counter=Counter+4'b1; 1072 | RDSLAVE_NEXTSTATE = RDSLAVE_WAIT; 1073 | slaveintf.RRESP = 2'b00; 1074 | end 1075 | 1076 | else begin 1077 | if (slaveintf.ARSIZE >= 3'b011) 1078 | slaveintf.RRESP = 2'b10; 1079 | else 1080 | slaveintf.RRESP = 2'b11; 1081 | 1082 | Next_Counter=Counter+4'b1; 1083 | RDSLAVE_NEXTSTATE = RDSLAVE_ERROR; 1084 | end 1085 | end 1086 | 1087 | RDSLAVE_WAIT:begin 1088 | if(slaveintf.RREADY) begin 1089 | if(Next_Counter == slaveintf.ARLEN+4'b1) begin 1090 | slaveintf.RLAST = '1; 1091 | end 1092 | else 1093 | slaveintf.RLAST = '0; 1094 | 1095 | RDSLAVE_NEXTSTATE = RDSLAVE_VALID; 1096 | end 1097 | else begin 1098 | RDSLAVE_NEXTSTATE = RDSLAVE_WAIT; 1099 | end 1100 | end 1101 | 1102 | RDSLAVE_VALID:begin 1103 | slaveintf.RVALID = '0; 1104 | 1105 | if (Next_Counter == slaveintf.ARLEN+4'b1) begin 1106 | RDSLAVE_NEXTSTATE = RDSLAVE_CLEAR; 1107 | slaveintf.RLAST = '0; 1108 | end 1109 | else begin 1110 | readdata_address = readdata_address_r; 1111 | RDSLAVE_NEXTSTATE = RDSLAVE_START; 1112 | end 1113 | end 1114 | 1115 | RDSLAVE_ERROR:begin 1116 | if (Next_Counter == slaveintf.ARLEN+4'b1) begin 1117 | slaveintf.RLAST = '1; 1118 | RDSLAVE_NEXTSTATE = RDSLAVE_VALID; 1119 | end 1120 | else begin 1121 | slaveintf.RLAST = '0; 1122 | RDSLAVE_NEXTSTATE = RDSLAVE_START; 1123 | end 1124 | end 1125 | endcase 1126 | end 1127 | 1128 | endmodule -------------------------------------------------------------------------------- /Emulation/Top_HDL.sv: -------------------------------------------------------------------------------- 1 | 2 | 3 | module AXI_design_emulation( 4 | input logic clock, 5 | input logic reset, 6 | 7 | input logic [31:0] AWaddr, 8 | input logic [3:0] AWlen, 9 | input logic [31:0] WData, 10 | input logic [3:0] AWid, 11 | input logic [3:0] WStrb, 12 | input logic [3:0] ARid, 13 | input logic [3:0] ARlen, 14 | input logic [2:0] AWsize, 15 | input logic [1:0] AWburst, 16 | input logic [31:0] ARaddr, 17 | input logic [2:0] ARsize, 18 | input logic [1:0] ARburst, 19 | //viewing inputs of slave 20 | output logic AWVALID_tb_s, 21 | output logic [1:0] AWBURST_tb_s, 22 | output logic [2:0] AWSIZE_tb_s, 23 | output logic [3:0] AWLEN_tb_s, 24 | output logic [31:0] AWADDR_tb_s, 25 | output logic [3:0] AWID_tb_s, 26 | output logic WVALID_tb_s, 27 | output logic WLAST_tb_s, 28 | output logic [3:0] WSTRB_tb_s, 29 | output logic [31:0] WDATA_tb_s, 30 | output logic [3:0] WID_tb_s, 31 | output logic BREADY_tb_s, 32 | output logic [3:0] ARID_tb_s, 33 | output logic [31:0] ARADDR_tb_s, 34 | output logic [3:0] ARLEN_tb_s, 35 | output logic [2:0] ARSIZE_tb_s, 36 | output logic [1:0] ARBURST_tb_s, 37 | output logic ARVALID_tb_s, 38 | output logic RREADY_tb_s, 39 | //viewing inputs of master . 40 | output logic AWREADY_tb_m, 41 | output logic WREADY_tb_m, 42 | output logic [3:0] BID_tb_m, 43 | output logic [1:0] BRESP_tb_m, 44 | output logic BVALID_tb_m, 45 | output logic ARREADY_tb_m, 46 | output logic [3:0] RID_tb_m, 47 | output logic [31:0] RDATA_tb_m, 48 | output logic [1:0] RRESP_tb_m, 49 | output logic RLAST_tb_m, 50 | output logic RVALID_tb_m 51 | 52 | ); 53 | 54 | //interface declaration 55 | AXI bus(); 56 | logic AWREADY; 57 | logic AWVALID; 58 | logic [1:0] AWBURST; 59 | logic [2:0] AWSIZE; 60 | logic [3:0] AWLEN; 61 | logic [31:0] AWADDR; 62 | logic [3:0] AWID; 63 | logic WREADY;// write data channel 64 | logic WVALID; 65 | logic WLAST; 66 | logic [3:0] WSTRB; 67 | logic [31:0] WDATA; 68 | logic [3:0] WID; 69 | logic [3:0] BID;// write response channel 70 | logic [1:0] BRESP; 71 | logic BVALID; 72 | logic BREADY; 73 | logic ARREADY;// address read channel 74 | logic [3:0] ARID; 75 | logic [31:0] ARADDR; 76 | logic [3:0] ARLEN; 77 | logic [2:0] ARSIZE; 78 | logic [1:0] ARBURST; 79 | logic ARVALID; 80 | logic [3:0] RID;// read data channel 81 | logic [31:0] RDATA; 82 | logic [1:0] RRESP; 83 | logic RLAST; 84 | logic RVALID; 85 | logic RREADY; 86 | 87 | AXI_Master_emulation master_inst( 88 | // GLOBAL SIGNALS 89 | .clock(clock), 90 | .reset(reset), 91 | .masterintf(bus), 92 | 93 | 94 | .AWaddr(AWaddr), 95 | .AWlen(AWlen), 96 | .WStrb(WStrb), 97 | .AWsize(AWsize), 98 | .AWburst(AWburst), 99 | .WData(WData), 100 | .AWid(AWid), 101 | 102 | .ARaddr(ARaddr), 103 | .ARid(ARid), 104 | .ARlen(ARlen), 105 | .ARsize(ARsize), 106 | .ARburst(ARburst), 107 | .AWREADY_tb_m(AWREADY_tb_m), 108 | .WREADY_tb_m(WREADY_tb_m), 109 | .BID_tb_m(BID_tb_m), 110 | .BRESP_tb_m(BRESP_tb_m), 111 | .BVALID_tb_m(BVALID_tb_m), 112 | .ARREADY_tb_m(ARREADY_tb_m), 113 | .RID_tb_m(RID_tb_m), 114 | .RDATA_tb_m(RDATA_tb_m), 115 | .RRESP_tb_m(RRESP_tb_m), 116 | .RLAST_tb_m(RLAST_tb_m), 117 | .RVALID_tb_m(RVALID_tb_m) 118 | 119 | 120 | ); 121 | 122 | 123 | AXI_Slave_emulation slave_inst(.clock(clock), 124 | .reset(reset), 125 | .slaveintf(bus), 126 | .AWVALID_tb_s(AWVALID_tb_s), 127 | .AWBURST_tb_s(AWBURST_tb_s), 128 | .AWSIZE_tb_s(AWSIZE_tb_s), 129 | .AWLEN_tb_s(AWLEN_tb_s), 130 | .AWADDR_tb_s(AWADDR_tb_s), 131 | .AWID_tb_s(AWID_tb_s), 132 | .WVALID_tb_s(WVALID_tb_s), 133 | .WLAST_tb_s(WLAST_tb_s), 134 | .WSTRB_tb_s(WSTRB_tb_s), 135 | .WDATA_tb_s(WDATA_tb_s), 136 | .WID_tb_s(WID_tb_s), 137 | .BREADY_tb_s(BREADY_tb_s), 138 | .ARID_tb_s(ARID_tb_s), 139 | .ARADDR_tb_s(ARADDR_tb_s), 140 | .ARLEN_tb_s(ARLEN_tb_s), 141 | .ARSIZE_tb_s(ARSIZE_tb_s), 142 | .ARBURST_tb_s(ARBURST_tb_s), 143 | .ARVALID_tb_s(ARVALID_tb_s), 144 | .RREADY_tb_s(RREADY_tb_s) 145 | ); 146 | 147 | 148 | 149 | endmodule 150 | -------------------------------------------------------------------------------- /Emulation/run.do: -------------------------------------------------------------------------------- 1 | configure -emul velocesolo1 2 | reg setvalue AXI_design_emulation.reset 1'b0 3 | run 2 4 | reg setvalue AXI_design_emulation.reset 1'b1 5 | run 10 6 | reg setvalue AXI_design_emulation.AWid 4'b1 7 | reg setvalue AXI_design_emulation.AWaddr 32'haaa 8 | reg setvalue AXI_design_emulation.AWlen 4'd3 9 | reg setvalue AXI_design_emulation.AWsize 3'b010 10 | reg setvalue AXI_design_emulation.AWburst 2'b00 11 | reg setvalue AXI_design_emulation.WStrb 4'b1111 12 | run 2 13 | reg setvalue AXI_design_emulation.WData 32'h0000aaaa 14 | run 3 15 | reg setvalue AXI_design_emulation.WData 32'h1111eeee 16 | run 3 17 | reg setvalue AXI_design_emulation.WData 32'h23232323 18 | run 3 19 | reg setvalue AXI_design_emulation.WData 32'haaaaaaaa 20 | run 4 21 | reg setvalue AXI_design_emulation.AWid 4'b0 22 | reg setvalue AXI_design_emulation.AWaddr 32'h000 23 | reg setvalue AXI_design_emulation.AWlen 4'b0 24 | reg setvalue AXI_design_emulation.AWsize 3'b000 25 | reg setvalue AXI_design_emulation.AWburst 2'b00 26 | run 10 27 | reg setvalue AXI_design_emulation.AWid 4'b0010 28 | reg setvalue AXI_design_emulation.ARid 4'b1011 29 | reg setvalue AXI_design_emulation.ARaddr 32'haaa 30 | reg setvalue AXI_design_emulation.AWaddr 32'h999 31 | reg setvalue AXI_design_emulation.AWlen 4'd3 32 | reg setvalue AXI_design_emulation.AWsize 3'b010 33 | reg setvalue AXI_design_emulation.AWburst 2'b00 34 | reg setvalue AXI_design_emulation.ARburst 2'b00 35 | reg setvalue AXI_design_emulation.ARsize 3'b010 36 | reg setvalue AXI_design_emulation.ARlen 4'd3 37 | reg setvalue AXI_design_emulation.WStrb 4'b1111 38 | run 2 39 | reg setvalue AXI_design_emulation.WData 32'h01234567 40 | run 3 41 | reg setvalue AXI_design_emulation.WData 32'h09090909 42 | run 3 43 | reg setvalue AXI_design_emulation.WData 32'habababab 44 | run 3 45 | reg setvalue AXI_design_emulation.WData 32'h55667788 46 | run 4 47 | reg setvalue AXI_design_emulation.AWid 4'b0 48 | reg setvalue AXI_design_emulation.AWaddr 32'd0 49 | reg setvalue AXI_design_emulation.AWlen 4'b0 50 | reg setvalue AXI_design_emulation.AWsize 3'b000 51 | reg setvalue AXI_design_emulation.AWburst 2'b00 52 | reg setvalue AXI_design_emulation.ARid 4'b0 53 | reg setvalue AXI_design_emulation.ARaddr 32'd0 54 | reg setvalue AXI_design_emulation.ARlen 4'b0 55 | reg setvalue AXI_design_emulation.ARsize 3'b000 56 | reg setvalue AXI_design_emulation.ARburst 2'b00 57 | run 10 58 | 59 | 60 | reg setvalue AXI_design_emulation.AWid 4'b0110 61 | reg setvalue AXI_design_emulation.ARid 4'b1010 62 | reg setvalue AXI_design_emulation.ARaddr 32'h999 63 | reg setvalue AXI_design_emulation.AWaddr 32'he32 64 | reg setvalue AXI_design_emulation.AWlen 4'd2 65 | reg setvalue AXI_design_emulation.AWsize 3'b000 66 | reg setvalue AXI_design_emulation.AWburst 2'b01 67 | reg setvalue AXI_design_emulation.ARburst 2'b00 68 | reg setvalue AXI_design_emulation.ARsize 3'b010 69 | reg setvalue AXI_design_emulation.ARlen 4'd3 70 | reg setvalue AXI_design_emulation.WStrb 4'b0100 71 | run 2 72 | reg setvalue AXI_design_emulation.WData 32'h01234567 73 | run 3 74 | reg setvalue AXI_design_emulation.WData 32'h09090909 75 | run 3 76 | reg setvalue AXI_design_emulation.WData 32'habababab 77 | run 4 78 | reg setvalue AXI_design_emulation.AWid 4'b0 79 | reg setvalue AXI_design_emulation.AWaddr 32'd0 80 | reg setvalue AXI_design_emulation.AWlen 4'b0 81 | reg setvalue AXI_design_emulation.AWsize 3'b000 82 | reg setvalue AXI_design_emulation.AWburst 2'b00 83 | reg setvalue AXI_design_emulation.ARid 4'b0 84 | reg setvalue AXI_design_emulation.ARaddr 32'd0 85 | reg setvalue AXI_design_emulation.ARlen 4'b0 86 | reg setvalue AXI_design_emulation.ARsize 3'b000 87 | reg setvalue AXI_design_emulation.ARburst 2'b00 88 | run 10 89 | 90 | reg setvalue AXI_design_emulation.AWid 4'b0101 91 | reg setvalue AXI_design_emulation.ARid 4'b1100 92 | reg setvalue AXI_design_emulation.ARaddr 32'he32 93 | reg setvalue AXI_design_emulation.AWaddr 32'hbab 94 | reg setvalue AXI_design_emulation.AWlen 4'd0 95 | reg setvalue AXI_design_emulation.AWsize 3'b000 96 | reg setvalue AXI_design_emulation.AWburst 2'b00 97 | reg setvalue AXI_design_emulation.ARburst 2'b01 98 | reg setvalue AXI_design_emulation.ARsize 3'b000 99 | reg setvalue AXI_design_emulation.ARlen 4'd2 100 | reg setvalue AXI_design_emulation.WStrb 4'b0100 101 | run 2 102 | reg setvalue AXI_design_emulation.WData 32'h01234567 103 | run 4 104 | reg setvalue AXI_design_emulation.AWid 4'b0 105 | reg setvalue AXI_design_emulation.AWaddr 32'd0 106 | reg setvalue AXI_design_emulation.AWlen 4'b0 107 | reg setvalue AXI_design_emulation.AWsize 3'b000 108 | reg setvalue AXI_design_emulation.AWburst 2'b00 109 | reg setvalue AXI_design_emulation.ARid 4'b0 110 | reg setvalue AXI_design_emulation.ARaddr 32'd0 111 | reg setvalue AXI_design_emulation.ARlen 4'b0 112 | reg setvalue AXI_design_emulation.ARsize 3'b000 113 | reg setvalue AXI_design_emulation.ARburst 2'b00 114 | run 10 115 | 116 | 117 | reg setvalue AXI_design_emulation.AWid 4'b0110 118 | reg setvalue AXI_design_emulation.ARid 4'b0010 119 | reg setvalue AXI_design_emulation.AWaddr 32'haaa 120 | reg setvalue AXI_design_emulation.AWlen 4'd7 121 | reg setvalue AXI_design_emulation.AWsize 3'b010 122 | reg setvalue AXI_design_emulation.AWburst 2'b10 123 | reg setvalue AXI_design_emulation.WStrb 4'b1111 124 | run 2 125 | reg setvalue AXI_design_emulation.WData 32'hcccccdda 126 | run 3 127 | reg setvalue AXI_design_emulation.WData 32'h01020304 128 | run 3 129 | reg setvalue AXI_design_emulation.WData 32'h77668855 130 | run 3 131 | reg setvalue AXI_design_emulation.WData 32'h49354367 132 | run 3 133 | reg setvalue AXI_design_emulation.WData 32'h34567899 134 | run 3 135 | reg setvalue AXI_design_emulation.WData 32'h11111111 136 | run 3 137 | reg setvalue AXI_design_emulation.WData 32'h23456765 138 | run 3 139 | reg setvalue AXI_design_emulation.WData 32'h11111556 140 | run 4 141 | reg setvalue AXI_design_emulation.AWid 4'b0 142 | reg setvalue AXI_design_emulation.AWaddr 32'd1 143 | reg setvalue AXI_design_emulation.AWlen 4'b0 144 | reg setvalue AXI_design_emulation.AWsize 3'b000 145 | reg setvalue AXI_design_emulation.AWburst 2'b00 146 | reg setvalue AXI_design_emulation.ARid 4'b0 147 | reg setvalue AXI_design_emulation.ARaddr 32'd1 148 | reg setvalue AXI_design_emulation.ARlen 4'b0 149 | reg setvalue AXI_design_emulation.ARsize 3'b000 150 | reg setvalue AXI_design_emulation.ARburst 2'b00 151 | run 10 152 | 153 | reg setvalue AXI_design_emulation.AWid 4'b0111 154 | reg setvalue AXI_design_emulation.ARid 4'b1110 155 | reg setvalue AXI_design_emulation.ARaddr 32'haaa 156 | reg setvalue AXI_design_emulation.AWaddr 32'hcac 157 | reg setvalue AXI_design_emulation.AWlen 4'd0 158 | reg setvalue AXI_design_emulation.AWsize 3'b000 159 | reg setvalue AXI_design_emulation.AWburst 2'b00 160 | reg setvalue AXI_design_emulation.ARburst 2'b10 161 | reg setvalue AXI_design_emulation.ARsize 3'b010 162 | reg setvalue AXI_design_emulation.ARlen 4'd7 163 | reg setvalue AXI_design_emulation.WStrb 4'b0001 164 | run 2 165 | reg setvalue AXI_design_emulation.WData 32'h01234567 166 | run 4 167 | reg setvalue AXI_design_emulation.AWid 4'b0 168 | reg setvalue AXI_design_emulation.AWaddr 32'd1 169 | reg setvalue AXI_design_emulation.AWlen 4'b0 170 | reg setvalue AXI_design_emulation.AWsize 3'b000 171 | reg setvalue AXI_design_emulation.AWburst 2'b00 172 | reg setvalue AXI_design_emulation.ARid 4'b0 173 | reg setvalue AXI_design_emulation.ARaddr 32'd1 174 | reg setvalue AXI_design_emulation.ARlen 4'b0 175 | reg setvalue AXI_design_emulation.ARsize 3'b000 176 | reg setvalue AXI_design_emulation.ARburst 2'b00 177 | run 10 178 | upload -tracedir ./veloce.wave/wave1 179 | exit 180 | -------------------------------------------------------------------------------- /Emulation/veloce.config: -------------------------------------------------------------------------------- 1 | #The one-step analysis and compilation flow is used to support legacy ICE 2 | 3 | veanalyze Master_Axi3Protocol.sv Slave_Axi3Protocol.sv Top_HDL.sv MasterSlaveAxiInterface.sv 4 | 5 | #rtlc -partition_module_rtl axi 6 | #Declare top level module 7 | comp -top AXI_design_emulation 8 | 9 | #Declare single step compile/analysis flow 10 | comp -single_step 11 | 12 | #Solo is D1S 13 | comp -platform D1S 14 | 15 | comp -num_boards 1 16 | 17 | #ICE Legacy Support enabled 18 | comp -app legacy 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /Emulation/view.do: -------------------------------------------------------------------------------- 1 | view wave 2 | dataset open ./veloce.wave/wave1.stw wave1 3 | #wave add -d wave1 top.clock {top.reset} {top.rdata} {top.bus} 4 | wave add -d wave1 AXI_design_emulation.clock {AXI_design_emulation.reset} {AXI_design_emulation.AWid} {AXI_design_emulation.AWaddr} {AXI_design_emulation.AWlen} 5 | wave add -d wave1 {AXI_design_emulation.AWsize} {AXI_design_emulation.AWburst} {AXI_design_emulation.WData} {AXI_design_emulation.WStrb} {AXI_design_emulation.WData} 6 | wave add -d wave1 {AXI_design_emulation.AWVALID_tb_s} {AXI_design_emulation.AWBURST_tb_s} {AXI_design_emulation.AWSIZE_tb_s} {AXI_design_emulation.AWLEN_tb_s} 7 | wave add -d wave1 {AXI_design_emulation.AWADDR_tb_s} {AXI_design_emulation.AWID_tb_s} {AXI_design_emulation.WVALID_tb_s} {AXI_design_emulation.WLAST_tb_s} 8 | wave add -d wave1 {AXI_design_emulation.WSTRB_tb_s} {AXI_design_emulation.WDATA_tb_s} {AXI_design_emulation.WID_tb_s} {AXI_design_emulation.BREADY_tb_s} 9 | wave add -d wave1 {AXI_design_emulation.ARID_tb_s} {AXI_design_emulation.ARADDR_tb_s} {AXI_design_emulation.ARLEN_tb_s} {AXI_design_emulation.ARSIZE_tb_s} 10 | wave add -d wave1 {AXI_design_emulation.ARBURST_tb_s} {AXI_design_emulation.ARVALID_tb_s} {AXI_design_emulation.RREADY_tb_s} {AXI_design_emulation.AWREADY_tb_m} 11 | wave add -d wave1 {AXI_design_emulation.WREADY_tb_m} {AXI_design_emulation.BID_tb_m} {AXI_design_emulation.BRESP_tb_m} {AXI_design_emulation.BVALID_tb_m} 12 | wave add -d wave1 {AXI_design_emulation.ARREADY_tb_m} {AXI_design_emulation.RID_tb_m} {AXI_design_emulation.RDATA_tb_m} {AXI_design_emulation.RRESP_tb_m} 13 | wave add -d wave1 {AXI_design_emulation.RLAST_tb_m} {AXI_design_emulation.RVALID_tb_m} 14 | echo "wave1.stw loaded and signals added. Open the Wave window to observe outputs." 15 | 16 | 17 | -------------------------------------------------------------------------------- /README_AXI.txt: -------------------------------------------------------------------------------- 1 | Aim of the Project: IMPLEMENTATION OF INTERFACE USING AMBA AXI3 BUS PROTOCOL 2 | -The folder consists of the files for Questa Simulator and Veloce Emulator. 3 | -Standalone mode of emulation was being implemented. 4 | 5 | AXI_Questa Folder: 6 | This contains files to be run on QuestaSIM 7 | 8 | 1)Master_Axi3Protocol.sv 9 | 2)Slave_Axi3Protocol.sv 10 | 3)MasterSlaveAxiInterface.sv 11 | 4)Top_HVL.sv 12 | 5)Top_HDL.sv 13 | 6)assertions.sv 14 | 7)driver.sv 15 | 8)monitor.sv 16 | 9)VE.sv 17 | 10)testcase.sv 18 | 19 | Simulation steps: 20 | 21 | 1) Extract the contents of .zip file. 22 | 2) Create a new project in Questasim. 23 | 3) Add the files from AXI_Questa directory to the project. 24 | 4) Select Compile all 25 | FOR SIMULATION:( We commented out all the test cases except alternative Write and Read. The waveforms that get generated on the GUI window has the initial address that is manually given in the Driver module) 26 | 6) Right click on the testbench file(top.sv) and select the Simulate option. 27 | 7) Now Right click on the top file (top) and intf and select AddWave option. 28 | 8) The Wave window opens and all the signals are added to the wave. 29 | 9) Hit the runall option. 30 | 31 | [or] 32 | 33 | 1)Extract the contents of .zip file. 34 | 2)open questa and goto FILE and click on Change Directory .Navigate to the ECE571_FinalProject/AXI_QUESTA folder. 35 | 3)Now type the command "do run.do" in the transcript. 36 | The run file has commands for compiling and simulating.Also wave gets added. 37 | 38 | 39 | 40 | 41 | Emulation Folder: 42 | This contains files to be run on Emulator 43 | 44 | 1)MasterSlaveAxiInterface.sv 45 | 2)Master_Axi3Protocol.sv 46 | 3)Slave_Axi3Protocol.sv 47 | 4)Top_HDL.sv 48 | 5)Makefile 49 | 6)run.do 50 | 7)veloce.config 51 | 8)view.do 52 | 53 | Emulation steps: 54 | 1) Copy files into veloce login 55 | 2) In the terminal navigate to the directory where the files are present,and enter "make" command. 56 | 3) If you want to give other inputs and verify the design, make changes in run.do (As mentioned above, standalone mode is implemented where the inputs are manually given through a text file) 57 | 4) Add all the input output signals in the timing setup while setting the clock. 58 | 5) Check the outputs and verify them manually. --------------------------------------------------------------------------------