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Affirmer understands and acknowledges that Creative Commons is not a 120 | party to this document and has no duty or obligation with respect to 121 | this CC0 or use of the Work. 122 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Readings in Computer Architectures 2 | 3 | **Licence** : Creative Commons v1.0 Universal 4 | 5 | ## A. Purpose of This Site 6 | 7 | Collection of Educational Documents related to Computer Architecture. 8 | 9 | ## B. Target Readers 10 | 11 | Undergraduate Students related to 12 | 13 | - Computer Science and Engineering 14 | - Electric and Electrical Engineering 15 | - Information Science and Engineering 16 | 17 | Or, Person having the above Background(s) 18 | 19 | ## C. Category of Collection 20 | 21 | 1. Programming Model 22 | 2. Computer Architecture 23 | 3. Processor Architecture 24 | 4. Storage Architecture 25 | 5. Interconnect Architecture 26 | 6. Distributed Computing Architecture 27 | 7. Digital Logic Circuit and its Design 28 | 8. Semiconductor Technology 29 | 9. Constraint and Performance 30 | 31 | ## 1. Programming Model 32 | 33 | 34 | 35 | 36 | ## 2. Computer Architecture 37 | 38 | 39 | ### 2.1. Programming and Instruction-Set 40 | 41 | #### 2.1.1. Mapping State Diagram to Program 42 | 43 | #### 2.1.2. Mapping Program to Instruction Stream 44 | 45 | - "ILLIAC IV Software and Application Programming", D.J. Kuck, IEEE Transactions on Computers ( Volume: C-17, Issue: 8, August 1968) 46 | 47 | - "Programming Languages — The First 25 Years", Wegner, IEEE Transactions on Computers ( Volume: C-25, Issue: 12, December 1976) 48 | 49 | 50 | ### 2.2. Computing Mechanism 51 | 52 | #### 2.2.1. Primitives to Compute 53 | 54 | - "Architecture of the IBM System/360", G. M. Amdahl, G. A. Blaauw, F. P. Brooks, IBM Journal of Research and Development, Volume: 44, Issue: 1.2, Jan. 2000 55 | 56 | #### 2.2.2. Instruction Handling 57 | 58 | - "The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling", D. W. Anderson, F. J. Sparacio, R. M. Tomasulo, IBM Journal of Research and Development, Volume: 11, Issue: 1, Jan. 1967 59 | 60 | #### 2.2.3. Computer System 61 | 62 | - "IBM system/360 principles of operation", IBM Press, January 1964 63 | 64 | - "The CRAY-1 computer system", Richard M. Russell, Hardware Reference Manual, Cray Research, Inc., 1977 65 | 66 | - "The CDC 6600 Project", James E. Thornton, Annals of the History of Computing, Volume: 2, Issue: 4, Oct.-Dec. 1980 67 | 68 | 69 | 70 | 71 | ## 3. Processor Architecture 72 | 73 | 74 | ### 3.1. Instruction-Set 75 | 76 | #### 3.1.1. Instruction-Set: Mapping State Diagram to Processing Flow 77 | 78 | - "VLSI Processor Architecture", J.L. Hennessy, IEEE Transactions on Computers (Volume: C-33, Issue: 12, Dec. 1984) 79 | 80 | #### 3.1.2. Mapping Processing Flow to FSM-based Processor 81 | 82 | #### 3.1.3. Instruction-Set Architecture 83 | 84 | - "MIPS: A microprocessor architecture", John Hennessy, Norman Jouppi, Steven Przybylski, Christopher Rowen, Thomas Gross, Forest Baskett, John Gill, ACM SIGMICRO Newsletter, October 1982 85 | 86 | - "Reduced instruction set computer architecture", W. Stallings, Proceedings of the IEEE, Volume: 76, Issue: 1, Jan. 1988 87 | 88 | - "Measuring the Parallelism Available for Very Long Instruction Word Architectures", Nicolau Fisher, IEEE Transactions on Computers (Volume: C-33, Issue: 11, November 1984) 89 | 90 | 91 | ### 3.2. Pipelined Processor 92 | 93 | #### 3.2.1. Hazards and Bypassing 94 | 95 | - "The performance impact of incomplete bypassing in processor pipelines", P.S. Ahuja, D.W. Clark, A. Rogers, Proceedings of the 28th Annual International Symposium on Microarchitecture (MICRO-28), 29 Nov.-1 Dec. 1995 96 | 97 | - "The design space of register renaming techniques", D. Sima, IEEE Micro, Volume: 20, Issue: 5, Sep/Oct 2000 98 | 99 | #### 3.2.2. Branch Instruction and Prediction 100 | 101 | - "Hardware/software tradeoffs for increased performance", John Hennessy, Norman Jouppi, Forest Baskett, Thomas Gross, John Gill, Proceedings of the first international symposium on Architectural support for programming languages and operating systems (ASPLOS I), 1982 102 | 103 | - "A Survey of Techniques for Dynamic Branch Prediction", S Mittal, ArXiv, 2018 104 | 105 | #### 3.2.3. Pipeline Optimization 106 | 107 | - "The optimum pipeline depth for a microprocessor", A. Hartstein; T.R. Puzak, Proceedings 29th Annual International Symposium on Computer Architecture (ISCA-29), May 2002 108 | 109 | 110 | ### 3.3. Out-of-Order Enhancement 111 | 112 | #### 3.3.1. Out-of-Order Execution 113 | 114 | - "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", R. M. Tomasulo, IBM Journal of Research and Development, Volume: 11, Issue: 1, Jan. 1967 115 | 116 | - "Instruction Issue Logic in Pipelined Supercomputers", Shlomo Weiss, James E. Smith, IEEE Transactions on Computers, Volume: C-33, Issue: 11, Nov. 1984 117 | 118 | - "Checkpoint Repair for High-Performance Out-of-Order Execution Machines", Wen-Mei W. Hwu, Yale N. Patt, IEEE Transactions on Computers, Volume: C-36, Issue: 12, Dec. 1987 119 | 120 | #### 3.3.2. Superscalar Processors 121 | 122 | - "The Alpha AXP architecture and 21064 processor", E. McLellan, IEEE Micro, Volume: 13, Issue: 3, June 1993 123 | 124 | - "The microarchitecture of superscalar processors", J.E. Smith, G.S. Sohi, Proceedings of the IEEE, Volume: 83, Issue: 12, Dec. 1995 125 | 126 | - "The design space of register renaming techniques", D.Sima, IEEE Micro, Volume: 20, Issue: 5, Sept.-Oct. 2000 127 | 128 | 129 | ### 3.4. Vector Microprocessors 130 | 131 | - "Advanced Vector Architectures", Roger Espasa, Ph.D. Thesis, 1997 132 | 133 | - "Vector Microprocessors", K. Asanovic, Ph.D. Thesis, 1998 134 | 135 | - "Vector architectures: past, present and future", Roger Espasa, Mateo Valero, James E. Smith, Proceedings of the 12th international conference on Supercomputing, 1998 136 | 137 | 138 | ### 3.5. Parallelism: Limits of Processors 139 | 140 | - "Exploiting Instruction- and Data-Level Parallelism", Roger Espasa, Mateo Valero, IEEE Micro, September/October 1997, pp.20-27, vol. 17 141 | 142 | #### 3.5.1. Instruction-Level Parallelism 143 | 144 | - "Limits of instruction-level parallelism", David W. Wall, ACM SIGARCH Computer Architecture News, April 1991 145 | 146 | - "Checkpoint processing and recovery: towards scalable large instruction window processors", H. Akkary, R. Rajwar, S.T. Srinivasang, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003 147 | 148 | #### 3.5.2. Basic Block-Level Parallelism 149 | 150 | #### 3.5.3. Thread-Level Parallelism 151 | 152 | - "The case for a single-chip multiprocessor", Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, Kunyung Chang, ACM SIGPLAN Notices, September 1996 153 | 154 | - "Simultaneous multithreading: a platform for next-generation processors", S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, R.L. Stamm, D.M. Tullsen, IEEE Micro, Volume: 17, Issue: 5, Sept.-Oct. 1997 155 | 156 | - "Niagara: a 32-way multithreaded Sparc processor," P. Kongetira, K. Aingaran and K. Olukotun, IEEE Micro, vol. 25, no. 2, pp. 21-29, March-April 2005 157 | 158 | #### 3.5.4. Data-Level Parallelism 159 | 160 | - "Subword parallelism with MAX-2", Ruby B. Lee, IEEE Micro, Volume: 16, Issue: 4, Aug 1996 161 | 162 | - "Implementing streaming SIMD extensions on the Pentium III processor", S.K. Raman, V. Pentkovski, J. Keshava, IEEE Micro, Volume: 20, Issue: 4, Jul/Aug 2000 163 | 164 | 165 | ### 3.6. Exception and Interruption 166 | 167 | - "Implementing precise interrupts in pipelined processors", J.E. Smith, A.R. Pleszkun, IEEE Transactions on Computers, Volume: 37, Issue: 5, May 1988 168 | 169 | 170 | 171 | 172 | ## 4. Storage Architecture 173 | 174 | 175 | ### 4.1. Volatile Memories 176 | 177 | #### 4.1.1. Dynamic RAM 178 | 179 | #### 4.1.2. Static RAM 180 | 181 | 182 | ### 4.2. Non-Volatile Memories 183 | 184 | - "Emerging Memory Technologies: Recent Trends and Prospects", Shimeng Yu, Pai-Yu Chen, IEEE Solid-State Circuits Magazine, Volume: 8, Issue: 2, Spring 2016 185 | 186 | 187 | ### 4.3. Cache/Paged Memories 188 | 189 | - "Cache-based Computer Systems", K. R. Kaplan, R. O. Winder, Computer, Volume: 6, Issue: 3, March 1973 190 | 191 | - "Cache memories for PDP-11 family computers", Strecker, William D., Proceedings of the 3rd Annual Symposium on Computer Architecture, 1976 192 | 193 | - "Cache write policies and performance", Jouppi, Norman P., Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993 194 | 195 | #### 4.3.1. Replacement 196 | 197 | - "Thrashing: its causes and prevention", Denning, Peter J., Proceedings of the December 9-11, 1968, Fall Joint Computer Conference, Part I, 1968 198 | 199 | - "Evaluation techniques for storage hierarchies", R.L. Mattson, J. Gecsei, D. R. Slutz, I. L. Traiger, IBM Systems Journal, Volume: 9, Issue: 2, 1970 200 | 201 | #### 4.3.2. Associativity 202 | 203 | - "Evaluating associativity in CPU caches", M.D. Hill, A. J. Smith, IEEE Transactions on Computers, Volume: 38, Issue: 12, Dec 1989 204 | 205 | 206 | #### 4.3.3. Working-set 207 | 208 | - "Working sets, cache sizes, and node granularity issues for large-scale multiprocessors", Rothberg, Edward and Singh, Jaswinder Pal and Gupta, Anoop, Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993 209 | 210 | 211 | ## 5. Interconnect Architecture 212 | 213 | 214 | ### 5.1. Signaling 215 | 216 | - "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs", T. Sakurai, IEEE Transactions on Electron Devices, Volume: 40, Issue: 1, January 1993 217 | 218 | #### 5.1.1. Crosstalk 219 | 220 | - "Reflection and crosstalk in logic circuit interconnections", John A. DeFalco, IEEE Spectrum, Volume: 7, Issue: 7, July 1970 221 | 222 | #### 5.1.2. Wire Delay 223 | 224 | - "The Transient Analysis of Damped Linear Networks with Particular Regard to Wideband Amplifiers", W.C. Elmore, J. Applied Physics, vol. 19(1), 1948 225 | 226 | - "International Technology Roadmap for Semiconductors", Semiconductor Industry Association, 2001 227 | 228 | - "The future of wires", R. Ho, K.W. Mai, M.A. Horowitz, Proceedings of the IEEE, Volume: 89, Issue: 4, April 2001 229 | 230 | 231 | ### 5.2. Networks-on-Chip 232 | 233 | - "Route packets, not wires: on-chip interconnection networks", W.J. Dally, B. Towles, DAC '01: Proceedings of the 38th annual Design Automation, 2001 234 | 235 | - "A survey of research and practices of Network-on-chip", Tobias Bjerregaard, Shankar Mahadevan, ACM Computing Surveys, June 2006 236 | 237 | - "Evaluating Bufferless Flow Control for On-chip Networks", George Michelogiannakis, Daniel Sanchez, William J. Dally, Christos Kozyrakis, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip 238 | 239 | 240 | ### 5.3. Livelock and Deadlock 241 | 242 | - "Some Deadlock Properties of Computer Systems", Richard C. Holt, ACM Computing Surveys, September 1972 243 | 244 | - "Deadlock-Free Message Routing in Multiprocessor Interconnection Networks", Dally, Seitz, IEEE Transactions on Computers, Volume: C-36, Issue: 5, May 1987 245 | 246 | - "High Performance Communications In Processor Networks," C. R. Jesshope, P. R. Miller and J. T. Yantchev, The 16th Annual International Symposium on Computer Architecture (ISCA-16), 1989, pp. 150-157 247 | 248 | 249 | ### 5.4. Routing on a Chip 250 | 251 | - "Virtual-channel flow control", W.J. Dally, IEEE Transactions on Parallel and Distributed Systems, Volume: 3, Issue: 2, Mar 1992 252 | 253 | - "The Turn Model for Adaptive Routing", C.J. Glass, L.M. Ni, Proceedings the 19th Annual International Symposium on Computer Architecture, 1992 254 | 255 | - "A survey of wormhole routing techniques in direct networks", L.M. Ni, P.K. McKinley, Computer, Volume: 26, Issue: 2, Feb. 1993 256 | 257 | 258 | 259 | 260 | ## 6. Distributed Computing Architecture 261 | 262 | 263 | ### 6.1. Many-core Microprocessors 264 | 265 | - "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs", Lamport, IEEE Transactions on Computers, Volume: C-28, Issue: 9, Sept. 1979 266 | 267 | - "Baring it all to Software: The Raw Machines", E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, A. Agarwal, Computer, Volume: 30, Issue: 9, September 1997 268 | 269 | 270 | ### 6.2. Memory Coherency and Protocol 271 | 272 | - "Shared memory systems on the Futurebus", P. Sweazey, Digest of Papers. COMPCON Spring 88 Thirty-Third IEEE Computer Society International Conference 273 | 274 | - "Shared memory consistency models: a tutorial", S.V. Adve, K. Gharachorloo, Computer, Volume: 29, Issue: 12, Dec 1996 275 | 276 | 277 | 278 | 279 | ## 7. Digital Logic Circuit and its Design 280 | 281 | 282 | ### 7.1. Finite State Machine 283 | 284 | #### 7.1.1. State Diagram 285 | 286 | - "Regular Algebra and Finite Machines", John Horton Conway, Dover Books on Mathematics 287 | 288 | #### 7.1.2. Mapping State Diagram to FSM 289 | 290 | - "Introduction to the theory of finite-state machines", S. Seshu, McGraw Hill; First Edition, January 1, 1962 291 | 292 | #### 7.1.3. Optimization 293 | 294 | 295 | ### 7.2. Boolean Algebra and Logic Circuit 296 | 297 | #### 7.2.1.Boolean Algebra 298 | 299 | - "Elements of Boolean Algebra for the Study of Information-Handling Systems", Robert Serrell, Proceedings of the IRE, Volume: 41, Issue: 10, Oct. 1953 300 | 301 | #### 7.2.2. Logic Gate Primitives 302 | 303 | #### 7.2.3. Combinatorial Logic Circuit 304 | 305 | - "A Truth Table Method for the Synthesis of Combinational Logic", Sheldon B. Akers, IRE Transactions on Electronic Computers, Volume: EC-10, Issue: 4, Dec. 1961 306 | 307 | 308 | ### 7.3. Synchronous Logic and Pipelining 309 | 310 | #### 7.3.1. Clocking, Latches and Flip-Flop 311 | 312 | #### 7.3.2. Registers 313 | 314 | #### 7.3.3. Pipelining 315 | 316 | - "Pipelining of Arithmetic Functions", Thomas G. Hallin and Michael J. Flynn, IEEE Transactions on Computers, Volume: C-21, Issue: 8, Aug. 1972 317 | 318 | 319 | ### 7.4. Modular and Intellectual Properties 320 | 321 | #### 7.4.1. Module: Hierarchical Description 322 | 323 | #### 7.4.2. Reuse of Module 324 | 325 | 326 | 327 | 328 | ## 8. Semiconductor Technology 329 | 330 | 331 | ### 8.1. Band-Gap Model 332 | 333 | #### 8.1.1. Band Theory and Its Band-Gap 334 | 335 | - "Characteristics of Electrons in Solids", IRE Transactions on Education, Volume: 3, Issue: 4, Dec. 1960 336 | 337 | - "Bandgap and transport properties of Si/sub 1-x/Ge/sub x/ by analysis of nearly ideal Si/Si/sub 1-x/Ge/sub x//Si heterojunction bipolar transistors," C. A. King, J. L. Hoyt and J. F. Gibbons, IEEE Transactions on Electron Devices, vol. 36, no. 10, pp. 2093-2104, Oct. 1989 338 | 339 | #### 8.1.2. Doping 340 | 341 | - "The influence of heavy doping on the emitter efficiency of a bipolar transistor", H.J.J. De Man, IEEE Transactions on Electron Devices, Volume: 18, Issue: 10, October 1971 342 | 343 | 344 | ### 8.2. Transistor 345 | 346 | - "The transistor — A new amplifier", Electrical Engineering, vol. 67, no. 8, pp. 740-740, Aug. 1948 347 | 348 | - "Some circuit aspects of the transistor", R. M. Ryder, R. J. Kircher, The Bell System Technical Journal, Volume: 28, Issue: 3, July 1949 349 | 350 | #### 8.2.1. Band-Gap and Junction 351 | 352 | - "Carrier Generation and Recombination in P-N Junctions and P-N Junction Characteristics", Chih-tang Sah, Robert N. Noyce, William Shockley, Proceedings of the IRE, Volume: 45, Issue: 9, Sept. 1957 353 | 354 | #### 8.2.2. Historical Review of Transistor 355 | 356 | - "The invention of the transistor", Proceedings of the IEEE, Volume: 86, Issue: 1, Jan. 1998 357 | 358 | - "Evolution of the MOS transistor-from conception to VLSI", Sah Chih-Tang, Proceedings of the IEEE, Volume: 76, Issue: 10, Oct. 1988 359 | 360 | 361 | ### 8.3. Fabrication 362 | 363 | #### 8.3.1. Fabrication Process 364 | 365 | - "Stabilization of Silicon Surfaces by Thermally Grown Oxides", M. M. Atalla, E. Tannenbaum, E. J. Scheibner, Bell System Technical Journal, May 1959 366 | 367 | #### 8.3.2. Integrated Circuits 368 | 369 | - "Miniature semiconductor integrated circuit", Jack S Kilby, US3115581A, U.S. Patent 370 | 371 | - "Semiconductor Device and Lead Structure", Robert N Noyce, US2981877, U.S. Patent 372 | 373 | #### 8.3.3. Packaging 374 | 375 | - "Packaging technologies for supercomputer system", H. Hamaguchi, T. Watari and A. Dohya, IEEE International Symposium on Circuits and Systems (ISCAS), 1991, pp. 2292-2295 vol.4 376 | 377 | 378 | ### 8.4. Interposer, Die-Stacking, and Chiplet 379 | 380 | #### 8.4.1. Interposer 381 | 382 | - "Interposer Technologies for High-Performance Applications", Ahmad Usman, Etizaz Shah, Nithanth B. Satishprasad, Jialou Chen, Steven A. Bohlemann, Sajjad H. Shami, Ali A. Eftekhar, Ali Adibi, IEEE Transactions on Components, Packaging and Manufacturing Technology, Volume: 7, Issue: 6, June 2017 383 | 384 | - "Architecture, Chip, and Package Co-Design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse", Kim, Jinwoo and Murali, Gauthaman and Park, Heechun and Qin, Eric and Kwon, Hyoukjun and Chaitanya, Venkata and Chekuri, Krishna and Dasari, Nihar and Singh, Arvind and Lee, Minah and Torun, Hakki Mert and Roy, Kallol and Swaminathan, Madhavan and Mukhopadhyay, Saibal and Krishna, Tushar and Lim, Sung Kyu, Proceedings of the 56th Annual Design Automation Conference (DAC-56), 2019 385 | 386 | #### 8.4.2. Die-Stacking 387 | 388 | #### 8.4.3. Chiplet 389 | 390 | - "Design and Analysis of an APU for Exascale Computing", Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh Meswani, Indrani Paul, Matthew Poremba, Steven Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan, IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017 391 | 392 | - "A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology", Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany, HotChips 31, 2019 393 | 394 | - "Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse", Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 28, Issue: 11, Nov. 2020 395 | 396 | 397 | 398 | 399 | ## 9. Constraint and Performance 400 | 401 | 402 | ### 9.1. Performance 403 | 404 | - Amdahl's Law: "Validity of the single processor approach to achieving large scale computing capabilities", Gene M. Amdahl, Proceedings of the spring joint computer conference, AFIPS '67, April 1967 405 | 406 | 407 | ### 9.2. Scaling 408 | 409 | #### 9.2.1. MOS-FET: Moore's Law 410 | 411 | - "Progress in digital integrated electronics", Gordon E. Moore, International Electron Devices Meeting, IEEE, 1975, pp. 11-13. 412 | 413 | #### 9.2.2. Power Consumption: Dennard's Scaling 414 | 415 | - "Design of ion-implanted MOSFET's with very small physical dimensions", R.H. Dennard, F.H. Gaensslen, Hwa-Nien Yu, V.L. Rideout, E. Bassous, A.R. LeBlanc, IEEE Journal of Solid-State Circuits, Volume: 9, Issue: 5, Oct. 1974 416 | 417 | 418 | ### 9.3. Energy Consumption 419 | 420 | - "Energy dissipation in general purpose microprocessors", R. Gonzalez, M. Horowitz, IEEE Journal of Solid-State Circuits, Volume: 31, Issue: 9, Sep 1996 421 | 422 | - "Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse", Michael B. Taylor, DAC Design Automation Conference, 2012 423 | 424 | - "Computing's energy problem (and what we can do about it)", Mark Horowitz, IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 --------------------------------------------------------------------------------