├── .gitignore ├── C++ ├── FAST9.sln └── FAST9 │ ├── FAST9.vcxproj │ ├── FAST9.vcxproj.filters │ ├── Thumbs.db │ ├── fast9.cpp │ ├── supermario.png │ ├── test.tif │ └── untitled.png ├── LICENSE ├── README.md ├── Sample ├── BlockDiagram │ ├── Feature_Detection.png │ ├── Feature_Score.png │ └── Non-Maximal_Supression.png ├── camera-fast9.png ├── camera.png ├── h-fast9.png ├── h.png ├── stop-fast9.png ├── stop.png ├── supermario.mif ├── supermario.png ├── test.tif ├── untitled.mif └── untitled.png └── Verilog ├── .qsys_edit ├── filters.xml └── preferences.xml ├── Accelerator_Top.v ├── Addr_Reg.v ├── Buffer.qip ├── Buffer.v ├── Buffer_bb.v ├── DBMEM.v ├── FAST9_Top.v ├── FD_AddrCal.v ├── FD_Controller.v ├── FD_Datapath.v ├── FD_Reg.v ├── FD_Testbench.v ├── FD_Top.v ├── FS_Datapath.v ├── FS_ScoreMem.qip ├── FS_ScoreMem.v ├── FS_ScoreMem_bb.v ├── FS_Testbench.v ├── FS_Top.v ├── Mat_AddrCal.v ├── Mat_Controller.v ├── Mat_Counter.v ├── Mat_Datapath.v ├── Mat_Reg.v ├── Mat_Testbench.v ├── Mat_Top.v ├── NMS_AddrCal.v ├── NMS_Controller.v ├── NMS_Datapath.v ├── NMS_Reg.v ├── NMS_Testbench.v ├── NMS_Top.v ├── SRAM.qip ├── SRAM.v ├── SRAM_bb.v ├── Testbench_SramTest.v ├── fast9.pti_db_list.ddb ├── fast9.qpf ├── fast9.qsf ├── fast9.tis_db_list.ddb ├── fast9_assignment_defaults.qdf ├── supermario.mif └── untitled.mif /.gitignore: -------------------------------------------------------------------------------- 1 | ## Ignore Visual Studio temporary files, build results, and 2 | ## files generated by popular Visual Studio add-ons. 3 | 4 | # User-specific files 5 | *.suo 6 | *.user 7 | *.userosscache 8 | *.sln.docstates 9 | 10 | # User-specific files (MonoDevelop/Xamarin Studio) 11 | *.userprefs 12 | 13 | # Build results 14 | [Dd]ebug/ 15 | [Dd]ebugPublic/ 16 | [Rr]elease/ 17 | [Rr]eleases/ 18 | x64/ 19 | x86/ 20 | bld/ 21 | [Bb]in/ 22 | [Oo]bj/ 23 | [Ll]og/ 24 | 25 | # Visual Studio 2015 cache/options directory 26 | .vs/ 27 | # Uncomment if you have tasks that create the project's static files in wwwroot 28 | #wwwroot/ 29 | 30 | # MSTest test Results 31 | [Tt]est[Rr]esult*/ 32 | [Bb]uild[Ll]og.* 33 | 34 | # NUNIT 35 | *.VisualState.xml 36 | TestResult.xml 37 | 38 | # Build Results of an ATL Project 39 | [Dd]ebugPS/ 40 | [Rr]eleasePS/ 41 | dlldata.c 42 | 43 | # DNX 44 | project.lock.json 45 | artifacts/ 46 | 47 | *_i.c 48 | *_p.c 49 | *_i.h 50 | *.ilk 51 | *.meta 52 | *.obj 53 | *.pch 54 | *.pdb 55 | *.pgc 56 | *.pgd 57 | *.rsp 58 | *.sbr 59 | *.tlb 60 | *.tli 61 | *.tlh 62 | *.tmp 63 | *.tmp_proj 64 | *.log 65 | *.vspscc 66 | *.vssscc 67 | .builds 68 | *.pidb 69 | *.svclog 70 | *.scc 71 | 72 | # Chutzpah Test files 73 | _Chutzpah* 74 | 75 | # Visual C++ cache files 76 | ipch/ 77 | *.aps 78 | *.ncb 79 | *.opendb 80 | *.opensdf 81 | *.sdf 82 | *.cachefile 83 | *.VC.db 84 | *.VC.VC.opendb 85 | 86 | # Visual Studio profiler 87 | *.psess 88 | *.vsp 89 | *.vspx 90 | *.sap 91 | 92 | # TFS 2012 Local Workspace 93 | $tf/ 94 | 95 | # Guidance Automation Toolkit 96 | *.gpState 97 | 98 | # ReSharper is a .NET coding add-in 99 | _ReSharper*/ 100 | *.[Rr]e[Ss]harper 101 | *.DotSettings.user 102 | 103 | # JustCode is a .NET coding add-in 104 | .JustCode 105 | 106 | # TeamCity is a build add-in 107 | _TeamCity* 108 | 109 | # DotCover is a Code Coverage Tool 110 | *.dotCover 111 | 112 | # NCrunch 113 | _NCrunch_* 114 | .*crunch*.local.xml 115 | nCrunchTemp_* 116 | 117 | # MightyMoose 118 | *.mm.* 119 | AutoTest.Net/ 120 | 121 | # Web workbench (sass) 122 | .sass-cache/ 123 | 124 | # Installshield output folder 125 | [Ee]xpress/ 126 | 127 | # DocProject is a documentation generator add-in 128 | DocProject/buildhelp/ 129 | DocProject/Help/*.HxT 130 | DocProject/Help/*.HxC 131 | DocProject/Help/*.hhc 132 | DocProject/Help/*.hhk 133 | DocProject/Help/*.hhp 134 | DocProject/Help/Html2 135 | DocProject/Help/html 136 | 137 | # Click-Once directory 138 | publish/ 139 | 140 | # Publish Web Output 141 | *.[Pp]ublish.xml 142 | *.azurePubxml 143 | # TODO: Comment the next line if you want to checkin your web deploy settings 144 | # but database connection strings (with potential passwords) will be unencrypted 145 | *.pubxml 146 | *.publishproj 147 | 148 | # Microsoft Azure Web App publish settings. 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7 | using namespace cv; 8 | 9 | const unsigned char DARKER = 1; 10 | const unsigned char SIMILAR = 2; 11 | const unsigned char BRIGHTER = 3; 12 | const int RED = 2; 13 | const int GREEN = 1; 14 | const int BLUE = 0; 15 | const int MAX_CANDIDATE = 16; 16 | const int MAX_CONSECUTIVE = 9; 17 | const int MAX_ADJACENCY = 8; 18 | const int MAX_ROWS = 512; 19 | const int MAX_COLS = 512; 20 | 21 | // Feature 22 | typedef struct feature { 23 | int y; 24 | int x; 25 | unsigned char score; 26 | unsigned char s; // Darker: 1, Similar: 2, Brighter: 3 27 | } FEATURE; 28 | 29 | Mat img; // Image 30 | vector feature_candidate; // Candidate features found in stage 'Feature Detection' 31 | int limit = 30; // Threshold 32 | 33 | void convertGrayScale() 34 | { 35 | unsigned char r, g, b; 36 | 37 | for (int y = 0; y < img.rows; y++) { 38 | Vec3b* pixel = img.ptr(y); 39 | 40 | for (int x = 0; x < img.cols; x++) { 41 | r = pixel[x][RED]; 42 | g = pixel[x][GREEN]; 43 | b = pixel[x][BLUE]; 44 | 45 | // 3 channel average 46 | int avg = (((r + g + b) / 3) > 0xff) ? 0xff : (r + g + b) / 3; 47 | pixel[x][RED] = (unsigned char) avg; 48 | pixel[x][GREEN] = (unsigned char) avg; 49 | pixel[x][BLUE] = (unsigned char) avg; 50 | } 51 | } 52 | } 53 | 54 | void getAdjacentSixteenPixels(unsigned char* candidate, int y, int x) 55 | { 56 | candidate[0] = img.at(y - 3, x)[BLUE]; 57 | candidate[1] = img.at(y - 3, x + 1)[BLUE]; 58 | candidate[2] = img.at(y - 2, x + 2)[BLUE]; 59 | candidate[3] = img.at(y - 1, x + 3)[BLUE]; 60 | candidate[4] = img.at(y, x + 3)[BLUE]; 61 | candidate[5] = img.at(y + 1, x + 3)[BLUE]; 62 | candidate[6] = img.at(y + 2, x + 2)[BLUE]; 63 | candidate[7] = img.at(y + 3, x + 1)[BLUE]; 64 | candidate[8] = img.at(y + 3, x)[BLUE]; 65 | candidate[9] = img.at(y + 3, x - 1)[BLUE]; 66 | candidate[10] = img.at(y + 2, x - 2)[BLUE]; 67 | candidate[11] = img.at(y + 1, x - 3)[BLUE]; 68 | candidate[12] = img.at(y, x - 3)[BLUE]; 69 | candidate[13] = img.at(y - 1, x - 3)[BLUE]; 70 | candidate[14] = img.at(y - 2, x - 2)[BLUE]; 71 | candidate[15] = img.at(y - 3, x - 1)[BLUE]; 72 | } 73 | 74 | void getAdjacentEightPixels(unsigned char* adjacency, unsigned char (* corner)[MAX_COLS], int y, int x) 75 | { 76 | adjacency[0] = corner[y - 1][x]; 77 | adjacency[1] = corner[y - 1][x + 1]; 78 | adjacency[2] = corner[y][x + 1]; 79 | adjacency[3] = corner[y + 1][x + 1]; 80 | adjacency[4] = corner[y + 1][x]; 81 | adjacency[5] = corner[y + 1][x - 1]; 82 | adjacency[6] = corner[y][x - 1]; 83 | adjacency[7] = corner[y - 1][x - 1]; 84 | } 85 | 86 | void comparePixel(unsigned char* compare, unsigned char* candidate, int y, int x, int threshold) 87 | { 88 | int lower = (img.at(y, x)[BLUE] - threshold) < 0 ? 0 : (img.at(y, x)[BLUE] - threshold); 89 | int upper = (img.at(y, x)[BLUE] + threshold) > 0xff ? 0xff : (img.at(y, x)[BLUE] + threshold); 90 | 91 | for (int i = 0; i < MAX_CANDIDATE; i++) 92 | compare[i] = (candidate[i] < lower) ? DARKER : (candidate[i] > upper) ? BRIGHTER : SIMILAR; 93 | } 94 | 95 | bool findNineConsecutivePixel(unsigned char* compare, int y, int x, bool allowPush) 96 | { 97 | for (int i = 0; i < MAX_CANDIDATE; i++) { 98 | if (compare[i] == SIMILAR) // Similar pixel is not feature 99 | continue; 100 | 101 | bool consecutive = true; 102 | for (int j = 1; j < MAX_CONSECUTIVE; j++) { 103 | if (compare[i] != compare[(i + j) % MAX_CANDIDATE]) { 104 | consecutive = false; // No consecutive 9 pixel 105 | break; 106 | } 107 | } 108 | 109 | if (consecutive) { // Found feature 110 | if (allowPush) { 111 | FEATURE feature; 112 | feature.y = y; 113 | feature.x = x; 114 | feature.s = compare[i]; 115 | feature_candidate.push_back(feature); // Add candidate feature 116 | } 117 | 118 | return true; 119 | } 120 | } 121 | 122 | return false; 123 | } 124 | 125 | void featureDetection() 126 | { 127 | unsigned char candidate[MAX_CANDIDATE]; 128 | unsigned char compare[MAX_CANDIDATE]; 129 | 130 | for (int y = 3; y < img.rows - 3; y++) { 131 | for (int x = 3; x < img.cols - 3; x++) { 132 | getAdjacentSixteenPixels(candidate, y, x); 133 | comparePixel(compare, candidate, y, x, limit); 134 | findNineConsecutivePixel(compare, y, x, true); 135 | } 136 | } 137 | 138 | /* This below is debug code 139 | ofstream outFile("FeatureDetection_Output.txt"); 140 | for (int i = 0; i < feature_candidate.size(); i++) 141 | outFile << dec 142 | << "y: " << feature_candidate[i].y 143 | << ", x: " << feature_candidate[i].x 144 | << ", addr: " << (feature_candidate[i].y * 180 + feature_candidate[i].x) 145 | << ", data: " << hex << (int) (img.at(feature_candidate[i].y, feature_candidate[i].x)[BLUE]) << " " << endl; 146 | outFile.close(); 147 | */ 148 | } 149 | 150 | void featureScore() 151 | { 152 | unsigned char candidate[MAX_CANDIDATE]; 153 | unsigned char compare[MAX_CANDIDATE]; 154 | 155 | for (int index = 0; index < feature_candidate.size(); index++) { 156 | FEATURE feature = feature_candidate[index]; 157 | getAdjacentSixteenPixels(candidate, feature.y, feature.x); 158 | 159 | int min = limit; 160 | int max = 255; 161 | 162 | while (min < max - 1) { 163 | int avg = (((min + max) / 2) < 0) ? 0 : (((min + max) / 2) > 0xff) ? 0xff : (min + max) / 2; 164 | comparePixel(compare, candidate, feature.y, feature.x, avg); 165 | 166 | if (findNineConsecutivePixel(compare, feature.y, feature.x, false)) 167 | min = avg; 168 | else 169 | max = avg; 170 | } 171 | 172 | feature_candidate[index].score = max; // save feature score 173 | } 174 | 175 | /* This below is debug code (Score decision using formula) 176 | ofstream outFile("FeatureScore_Output.txt"); 177 | for (int index = 0; index < feature_candidate.size(); index++) { 178 | FEATURE feature = feature_candidate[index]; 179 | getAdjacentSixteenPixels(candidate, feature.y, feature.x); 180 | comparePixel(compare, candidate, feature.y, feature.x, limit); 181 | findNineConsecutivePixel(compare, feature.y, feature.x, false); 182 | 183 | int setDark = 0; 184 | int setBright = 0; 185 | for (int i = 0; i < 16; i++) { 186 | if (compare[i] == DARKER) 187 | setDark += abs((int) img.at(feature.y, feature.x)[BLUE] - (int) candidate[i]) - limit; 188 | else if (compare[i] == BRIGHTER) 189 | setBright += abs((int) candidate[i] - (int) img.at(feature.y, feature.x)[BLUE]) - limit; 190 | } 191 | 192 | outFile << dec 193 | << "y: " << feature.y 194 | << ", x: " << feature.x 195 | << ", addr: " << (feature.y * 180 + feature.x) 196 | << ", score: " << hex << (((setDark > setBright) ? setDark : setBright) & 0xff) << endl; 197 | feature_candidate[index].score = (((setDark > setBright) ? setDark : setBright) & 0xff); 198 | } 199 | outFile.close(); 200 | */ 201 | } 202 | 203 | void oneFeatureScore() 204 | { 205 | // This function is debug code 206 | // input: y, x 207 | // result: only one feature score, console output 208 | 209 | unsigned char candidate[MAX_CANDIDATE]; 210 | unsigned char compare[MAX_CANDIDATE]; 211 | 212 | // test coordinate 213 | int y = 20; 214 | int x = 55; 215 | 216 | // Using binary search 217 | getAdjacentSixteenPixels(candidate, y, x); 218 | int min = limit; 219 | int max = 255; 220 | 221 | while (min < max - 1) { 222 | int avg = (((min + max) / 2) < 0) ? 0 : (((min + max) / 2) > 0xff) ? 0xff : (min + max) / 2; 223 | comparePixel(compare, candidate, y, x, avg); 224 | 225 | printf("%d: ", avg); 226 | for (int i = 0; i < 16; i++) 227 | printf("%d ", compare[i]); 228 | printf("\n"); 229 | 230 | if (findNineConsecutivePixel(compare, y, x, false)) 231 | min = avg; 232 | else 233 | max = avg; 234 | } 235 | printf("score: %d\n", max); 236 | 237 | // Using formula 238 | int setDark = 0; 239 | int setBright = 0; 240 | comparePixel(compare, candidate, y, x, limit); 241 | findNineConsecutivePixel(compare, y, x, false); 242 | 243 | for (int i = 0; i < 16; i++) { 244 | if (compare[i] == DARKER) 245 | setDark += abs(img.at(y, x)[BLUE] - candidate[i]) - limit; 246 | else if (compare[i] == BRIGHTER) 247 | setBright += abs(candidate[i] - img.at(y, x)[BLUE]) - limit; 248 | } 249 | printf("score: %d\n", (setDark > setBright) ? setDark : setBright); 250 | } 251 | 252 | void drawCandidateFeaturePoint() 253 | { 254 | for (int i = 0; i < feature_candidate.size(); i++) { 255 | img.ptr(feature_candidate[i].y)[feature_candidate[i].x][GREEN] = 0xff; 256 | img.ptr(feature_candidate[i].y)[feature_candidate[i].x][RED] = 0; 257 | img.ptr(feature_candidate[i].y)[feature_candidate[i].x][BLUE] = 0; 258 | 259 | img.ptr(feature_candidate[i].y - 1)[feature_candidate[i].x][GREEN] = 0xff; 260 | img.ptr(feature_candidate[i].y + 1)[feature_candidate[i].x][GREEN] = 0xff; 261 | img.ptr(feature_candidate[i].y)[feature_candidate[i].x - 1][GREEN] = 0xff; 262 | img.ptr(feature_candidate[i].y)[feature_candidate[i].x + 1][GREEN] = 0xff; 263 | } 264 | } 265 | 266 | void drawFeature(int y, int x) 267 | { 268 | img.ptr(y)[x][RED] = 0xff; 269 | img.ptr(y)[x][GREEN] = 0; 270 | img.ptr(y)[x][BLUE] = 0; 271 | 272 | img.ptr(y - 1)[x][RED] = 0xff; 273 | img.ptr(y - 1)[x][GREEN] = 0; 274 | img.ptr(y - 1)[x][BLUE] = 0; 275 | img.ptr(y + 1)[x][RED] = 0xff; 276 | img.ptr(y + 1)[x][GREEN] = 0; 277 | img.ptr(y + 1)[x][BLUE] = 0; 278 | img.ptr(y)[x - 1][RED] = 0xff; 279 | img.ptr(y)[x - 1][GREEN] = 0; 280 | img.ptr(y)[x - 1][BLUE] = 0; 281 | img.ptr(y)[x + 1][RED] = 0xff; 282 | img.ptr(y)[x + 1][GREEN] = 0; 283 | img.ptr(y)[x + 1][BLUE] = 0; 284 | } 285 | 286 | void nonMaximallySuppression() 287 | { 288 | unsigned char corner[MAX_ROWS][MAX_COLS] = {{0}}; 289 | unsigned char adjacency[MAX_ADJACENCY]; 290 | drawCandidateFeaturePoint(); 291 | 292 | // Set existing features to corner array 293 | for (int i = 0; i < feature_candidate.size(); i++) 294 | corner[feature_candidate[i].y][feature_candidate[i].x] = feature_candidate[i].score; 295 | 296 | // Non-maximal suppression 297 | for (int y = 4; y < img.rows - 4; y++) { 298 | for (int x = 4; x < img.cols - 4; x++) { 299 | if (corner[y][x] != 0) { 300 | getAdjacentEightPixels(adjacency, corner, y, x); 301 | 302 | bool check = true; 303 | for (int i = 0; i < MAX_ADJACENCY; i++) 304 | if (corner[y][x] < adjacency[i]) { 305 | check = false; 306 | break; 307 | } 308 | 309 | if (check) 310 | drawFeature(y, x); 311 | } 312 | } 313 | } 314 | 315 | /* This below is debug code 316 | ofstream outFile("NMS_Output.txt"); 317 | for (int y = 4; y < img.rows - 4; y++) { 318 | for (int x = 4; x < img.cols - 4; x++) { 319 | if (corner[y][x] != 0) { 320 | getAdjacentEightPixels(adjacency, corner, y, x); 321 | 322 | bool check = true; 323 | for (int i = 0; i < MAX_ADJACENCY; i++) 324 | if (corner[y][x] < adjacency[i]) { 325 | check = false; 326 | break; 327 | } 328 | 329 | if (check) { 330 | drawFeature(y, x); 331 | outFile << dec 332 | << "y: " << y 333 | << ", x: " << x 334 | << ", addr: " << (y * 180 + x) << endl; 335 | } 336 | } 337 | } 338 | } 339 | outFile.close(); 340 | */ 341 | } 342 | 343 | void NMSforSAD() 344 | { 345 | unsigned char corner[MAX_ROWS][MAX_COLS] = {{0}}; 346 | unsigned char adjacency[MAX_ADJACENCY]; 347 | 348 | for (int i = 0; i < feature_candidate.size(); i++) 349 | corner[feature_candidate[i].y][feature_candidate[i].x] = feature_candidate[i].score; 350 | 351 | int number = 1; 352 | ofstream outFile("SAD_Output.txt"); 353 | for (int y = 4; y < img.rows - 4; y++) { 354 | for (int x = 4; x < img.cols - 4; x++) { 355 | if (corner[y][x] != 0) { 356 | getAdjacentEightPixels(adjacency, corner, y, x); 357 | 358 | bool check = true; 359 | for (int i = 0; i < MAX_ADJACENCY; i++) 360 | if (corner[y][x] < adjacency[i]) { 361 | check = false; 362 | break; 363 | } 364 | 365 | if (check) { 366 | int avg = 367 | (img.at(y - 1, x)[BLUE] + 368 | img.at(y - 1, x + 1)[BLUE] + 369 | img.at(y, x + 1)[BLUE] + 370 | img.at(y + 1, x + 1)[BLUE] + 371 | img.at(y + 1, x)[BLUE] + 372 | img.at(y + 1, x - 1)[BLUE] + 373 | img.at(y, x - 1)[BLUE] + 374 | img.at(y - 1, x - 1)[BLUE]) / 8; 375 | 376 | outFile << dec 377 | << number++ 378 | << " y: " << y 379 | << ", x: " << x 380 | << ", addr: " << (y * 180 + x) 381 | << ", avg: " << avg << endl; 382 | } 383 | } 384 | } 385 | } 386 | outFile.close(); 387 | } 388 | 389 | void fast9() 390 | { 391 | featureDetection(); // stage 1 392 | featureScore(); // stage 2 393 | nonMaximallySuppression(); // stage 3 394 | //NMSforSAD(); 395 | } 396 | 397 | int main() 398 | { 399 | img = imread("untitled.png", CV_LOAD_IMAGE_COLOR); 400 | if (img.empty()) 401 | return -1; 402 | 403 | convertGrayScale(); // Convert an image to gray scale 404 | fast9(); // FAST-9 Algorithm 405 | 406 | imshow("fast9", img); 407 | waitKey(0); 408 | destroyWindow("fast9"); 409 | return 0; 410 | } -------------------------------------------------------------------------------- /C++/FAST9/supermario.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ISKU/FAST9-Accelerator/136d8b2e53ddec6c9cf946b9bb263880e8ca04d7/C++/FAST9/supermario.png -------------------------------------------------------------------------------- /C++/FAST9/test.tif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ISKU/FAST9-Accelerator/136d8b2e53ddec6c9cf946b9bb263880e8ca04d7/C++/FAST9/test.tif -------------------------------------------------------------------------------- /C++/FAST9/untitled.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ISKU/FAST9-Accelerator/136d8b2e53ddec6c9cf946b9bb263880e8ca04d7/C++/FAST9/untitled.png -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2017-2021 Minho Kim 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # FAST-9 Accelerator 2 | FAST-9 Algorithm for Corner Detection 3 | 4 | **Software** 5 | * The C++ code used OpenCV. 6 | * Visual Studio projects are intended to be tested in software before being implemented in hardware. 7 | 8 | **Hardware** 9 | * The Verilog code is hardware that detects corners in an image of 180x120 size for real-time image processing. 10 | * One pixel operates for about 20 clocks to detect corners. 11 | * The FAST-9 algorithm 3 stage was designed as a pipeline. 12 | 13 | Design 14 | ---------- 15 | ![Alt Text](https://github.com/ISKU/FAST9-Accelerator/blob/master/Sample/BlockDiagram/Feature_Detection.png) 16 | ![Alt Text](https://github.com/ISKU/FAST9-Accelerator/blob/master/Sample/BlockDiagram/Feature_Score.png) 17 | ![Alt Text](https://github.com/ISKU/FAST9-Accelerator/blob/master/Sample/BlockDiagram/Non-Maximal_Supression.png) 18 | 19 | Example 20 | ---------- 21 | ![Alt Text](https://github.com/ISKU/FAST9-Accelerator/blob/master/Sample/h.png) 22 | ![Alt Text](https://github.com/ISKU/FAST9-Accelerator/blob/master/Sample/h-fast9.png) 23 | 24 | ![Alt Text](https://github.com/ISKU/FAST9-Accelerator/blob/master/Sample/stop.png) 25 | ![Alt Text](https://github.com/ISKU/FAST9-Accelerator/blob/master/Sample/stop-fast9.png) 26 | 27 | ![Alt Text](https://github.com/ISKU/FAST9-Accelerator/blob/master/Sample/camera.png) 28 | ![Alt Text](https://github.com/ISKU/FAST9-Accelerator/blob/master/Sample/camera-fast9.png) 29 | 30 | :bulb: I applied the FAST-9 algorithm to this project: [Autonomous-Drone-Design](https://github.com/ISKU/Autonomous-Drone-Design) 31 | 32 | Author 33 | ---------- 34 | - Minho Kim ([ISKU](https://github.com/ISKU)) 35 | - **E-mail:** minho.kim093@gmail.com 36 | -------------------------------------------------------------------------------- /Sample/BlockDiagram/Feature_Detection.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ISKU/FAST9-Accelerator/136d8b2e53ddec6c9cf946b9bb263880e8ca04d7/Sample/BlockDiagram/Feature_Detection.png -------------------------------------------------------------------------------- /Sample/BlockDiagram/Feature_Score.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ISKU/FAST9-Accelerator/136d8b2e53ddec6c9cf946b9bb263880e8ca04d7/Sample/BlockDiagram/Feature_Score.png -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/ISKU/FAST9-Accelerator/136d8b2e53ddec6c9cf946b9bb263880e8ca04d7/Sample/untitled.png -------------------------------------------------------------------------------- /Verilog/.qsys_edit/filters.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /Verilog/.qsys_edit/preferences.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /Verilog/Accelerator_Top.v: -------------------------------------------------------------------------------- 1 | module Accelerator_Top (clock, nReset, position, isMatching); 2 | input clock; 3 | input nReset; 4 | output [239:0] position; 5 | output isMatching; 6 | 7 | wire [14:0] outAddr; 8 | wire [7:0] outPixel; 9 | 10 | FAST9_Top fast9( 11 | .clock(clock), 12 | .nReset(nReset), 13 | .refAddr(outAddr), 14 | .outPixel(outPixel) 15 | ); 16 | 17 | Mat_Top matching( 18 | .clock(clock), 19 | .nReset(nReset), 20 | .refAddr(outAddr), 21 | .isFeature(outPixel), 22 | .position(position), 23 | .isMatching(isMatching) 24 | ); 25 | endmodule -------------------------------------------------------------------------------- /Verilog/Addr_Reg.v: -------------------------------------------------------------------------------- 1 | module Addr_Reg (refAddr, posAddr, posReaden, position, isMatching); 2 | input [14:0] refAddr; // 특징점 주소 3 | input [3:0] posAddr; // 레지스터 주소 4 | input posReaden; // 매칭 여부 5 | output [239:0] position; // 유효 특징점 주소 6 | output isMatching; // 매칭 여부 7 | 8 | reg [14:0] r1, r2, r3, r4, r5, r6, r7, r8, r9; 9 | reg [14:0] r10, r11, r12, r13, r14, r15, r16; 10 | 11 | // 주소로부터 저장할 레지스터를 선택하기 위한 인접한 8개의 점의 데이터를 저장한다. 12 | wire [15:0] decoder; 13 | assign decoder = 14 | (posAddr == 4'd0) ? 16'd1 : 15 | (posAddr == 4'd1) ? 16'd2 : 16 | (posAddr == 4'd2) ? 16'd4 : 17 | (posAddr == 4'd3) ? 16'd8 : 18 | (posAddr == 4'd4) ? 16'd16 : 19 | (posAddr == 4'd5) ? 16'd32 : 20 | (posAddr == 4'd6) ? 16'd64 : 21 | (posAddr == 4'd7) ? 16'd128 : 22 | (posAddr == 4'd8) ? 16'd256 : 23 | (posAddr == 4'd9) ? 16'd512 : 24 | (posAddr == 4'd10) ? 16'd1024 : 25 | (posAddr == 4'd11) ? 16'd2048 : 26 | (posAddr == 4'd12) ? 16'd4096 : 27 | (posAddr == 4'd13) ? 16'd8192 : 28 | (posAddr == 4'd14) ? 16'd16384 : 29 | (posAddr == 4'd15) ? 16'd32768 : 4'bx; 30 | 31 | // 레지스터 저장 32 | always @(posAddr) 33 | if (decoder[0]) 34 | r1 <= refAddr; 35 | 36 | always @(posAddr) 37 | if (decoder[1]) 38 | r2 <= refAddr; 39 | 40 | always @(posAddr) 41 | if (decoder[2]) 42 | r3 <= refAddr; 43 | 44 | always @(posAddr) 45 | if (decoder[3]) 46 | r4 <= refAddr; 47 | 48 | always @(posAddr) 49 | if (decoder[4]) 50 | r5 <= refAddr; 51 | 52 | always @(posAddr) 53 | if (decoder[5]) 54 | r6 <= refAddr; 55 | 56 | always @(posAddr) 57 | if (decoder[6]) 58 | r7 <= refAddr; 59 | 60 | always @(posAddr) 61 | if (decoder[7]) 62 | r8 <= refAddr; 63 | 64 | always @(posAddr) 65 | if (decoder[8]) 66 | r9 <= refAddr; 67 | 68 | always @(posAddr) 69 | if (decoder[9]) 70 | r10 <= refAddr; 71 | 72 | always @(posAddr) 73 | if (decoder[10]) 74 | r11 <= refAddr; 75 | 76 | always @(posAddr) 77 | if (decoder[11]) 78 | r12 <= refAddr; 79 | 80 | always @(posAddr) 81 | if (decoder[12]) 82 | r13 <= refAddr; 83 | 84 | always @(posAddr) 85 | if (decoder[13]) 86 | r14 <= refAddr; 87 | 88 | always @(posAddr) 89 | if (decoder[14]) 90 | r15 <= refAddr; 91 | 92 | always @(posAddr) 93 | if (decoder[15]) 94 | r16 <= refAddr; 95 | 96 | // 저장된 유효 특징점의 모든 주소를 반환 97 | assign position = 98 | (posReaden == 1'b1) ? {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, r16} : 240'bx; 99 | 100 | // 매칭 여부를 반환 101 | assign isMatching = (posReaden == 1'b1) ? 1'b1 : 1'b0; 102 | endmodule -------------------------------------------------------------------------------- /Verilog/Buffer.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Buffer.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Buffer_bb.v"] 5 | -------------------------------------------------------------------------------- /Verilog/Buffer.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: Buffer.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.1.0 Build 162 10/23/2013 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module Buffer ( 40 | address, 41 | clock, 42 | data, 43 | wren, 44 | q); 45 | 46 | input [14:0] address; 47 | input clock; 48 | input [7:0] data; 49 | input wren; 50 | output [7:0] q; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_off 53 | `endif 54 | tri1 clock; 55 | `ifndef ALTERA_RESERVED_QIS 56 | // synopsys translate_on 57 | `endif 58 | 59 | wire [7:0] sub_wire0; 60 | wire [7:0] q = sub_wire0[7:0]; 61 | 62 | altsyncram altsyncram_component ( 63 | .address_a (address), 64 | .clock0 (clock), 65 | .data_a (data), 66 | .wren_a (wren), 67 | .q_a (sub_wire0), 68 | .aclr0 (1'b0), 69 | .aclr1 (1'b0), 70 | .address_b (1'b1), 71 | .addressstall_a (1'b0), 72 | .addressstall_b (1'b0), 73 | .byteena_a (1'b1), 74 | .byteena_b (1'b1), 75 | .clock1 (1'b1), 76 | .clocken0 (1'b1), 77 | .clocken1 (1'b1), 78 | .clocken2 (1'b1), 79 | .clocken3 (1'b1), 80 | .data_b (1'b1), 81 | .eccstatus (), 82 | .q_b (), 83 | .rden_a (1'b1), 84 | .rden_b (1'b1), 85 | .wren_b (1'b0)); 86 | defparam 87 | altsyncram_component.clock_enable_input_a = "BYPASS", 88 | altsyncram_component.clock_enable_output_a = "BYPASS", 89 | altsyncram_component.init_file = "untitled.mif", 90 | altsyncram_component.intended_device_family = "Cyclone IV E", 91 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 92 | altsyncram_component.lpm_type = "altsyncram", 93 | altsyncram_component.numwords_a = 21600, 94 | altsyncram_component.operation_mode = "SINGLE_PORT", 95 | altsyncram_component.outdata_aclr_a = "NONE", 96 | altsyncram_component.outdata_reg_a = "CLOCK0", 97 | altsyncram_component.power_up_uninitialized = "FALSE", 98 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 99 | altsyncram_component.widthad_a = 15, 100 | altsyncram_component.width_a = 8, 101 | altsyncram_component.width_byteena_a = 1; 102 | 103 | 104 | endmodule 105 | 106 | // ============================================================ 107 | // CNX file retrieval info 108 | // ============================================================ 109 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 110 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 111 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 112 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 113 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 114 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 115 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 116 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 117 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 118 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 119 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 120 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 121 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 122 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 123 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 124 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 125 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 126 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 127 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 128 | // Retrieval info: PRIVATE: MIFfilename STRING "untitled.mif" 129 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "21600" 130 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 131 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 132 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 133 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 134 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 135 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 136 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 137 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 138 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 139 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "15" 140 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 141 | // Retrieval info: PRIVATE: rden NUMERIC "0" 142 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 143 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 144 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 145 | // Retrieval info: CONSTANT: INIT_FILE STRING "untitled.mif" 146 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 147 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 148 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 149 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "21600" 150 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 151 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 152 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 153 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 154 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 155 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" 156 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 157 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 158 | // Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]" 159 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 160 | // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 161 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 162 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 163 | // Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0 164 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 165 | // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 166 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 167 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 168 | // Retrieval info: GEN_FILE: TYPE_NORMAL Buffer.v TRUE 169 | // Retrieval info: GEN_FILE: TYPE_NORMAL Buffer.inc FALSE 170 | // Retrieval info: GEN_FILE: TYPE_NORMAL Buffer.cmp FALSE 171 | // Retrieval info: GEN_FILE: TYPE_NORMAL Buffer.bsf FALSE 172 | // Retrieval info: GEN_FILE: TYPE_NORMAL Buffer_inst.v FALSE 173 | // Retrieval info: GEN_FILE: TYPE_NORMAL Buffer_bb.v TRUE 174 | // Retrieval info: LIB_FILE: altera_mf 175 | -------------------------------------------------------------------------------- /Verilog/Buffer_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: Buffer.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.1.0 Build 162 10/23/2013 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2013 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module Buffer ( 35 | address, 36 | clock, 37 | data, 38 | wren, 39 | q); 40 | 41 | input [14:0] address; 42 | input clock; 43 | input [7:0] data; 44 | input wren; 45 | output [7:0] q; 46 | `ifndef ALTERA_RESERVED_QIS 47 | // synopsys translate_off 48 | `endif 49 | tri1 clock; 50 | `ifndef ALTERA_RESERVED_QIS 51 | // synopsys translate_on 52 | `endif 53 | 54 | endmodule 55 | 56 | // ============================================================ 57 | // CNX file retrieval info 58 | // ============================================================ 59 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 60 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 61 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 62 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 63 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 64 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 65 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 66 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 67 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 68 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 69 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 70 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 71 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 72 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 73 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 74 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 75 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 76 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 77 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 78 | // Retrieval info: PRIVATE: MIFfilename STRING "untitled.mif" 79 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "21600" 80 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 81 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 82 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 83 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 84 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 85 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 86 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 87 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 88 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 89 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "15" 90 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 91 | // Retrieval info: PRIVATE: rden NUMERIC "0" 92 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 93 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 94 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 95 | // Retrieval info: CONSTANT: INIT_FILE STRING "untitled.mif" 96 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 97 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 98 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 99 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "21600" 100 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 101 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 102 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 103 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 104 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 105 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" 106 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 107 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 108 | // Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]" 109 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 110 | // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 111 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 112 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 113 | // Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0 114 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 115 | // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 116 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 117 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 118 | // Retrieval info: GEN_FILE: TYPE_NORMAL Buffer.v TRUE 119 | // Retrieval info: GEN_FILE: TYPE_NORMAL Buffer.inc FALSE 120 | // Retrieval info: GEN_FILE: TYPE_NORMAL Buffer.cmp FALSE 121 | // Retrieval info: GEN_FILE: TYPE_NORMAL Buffer.bsf FALSE 122 | // Retrieval info: GEN_FILE: TYPE_NORMAL Buffer_inst.v FALSE 123 | // Retrieval info: GEN_FILE: TYPE_NORMAL Buffer_bb.v TRUE 124 | // Retrieval info: LIB_FILE: altera_mf 125 | -------------------------------------------------------------------------------- /Verilog/DBMEM.v: -------------------------------------------------------------------------------- 1 | module DBMEM (matReaden, dbValue); 2 | input matReaden; 3 | output [287:0] dbValue; 4 | 5 | // 36개의 실제 특징점의 평균값 데이터로 matReaden이 1로 셋되면 값을 반환 6 | assign dbValue = 7 | (matReaden == 1'b1) ? 8 | {8'd95, 8'd95, 8'd95, 8'd95, 8'd0, 8'd0, 8'd0, 8'd0, 8'd95, 8'd95, 8'd95, 8'd95, 9 | 8'd159, 8'd159, 8'd255, 8'd255, 8'd159, 8'd159, 8'd159, 8'd159, 8'd255, 8'd255, 10 | 8'd159, 8'd159, 8'd95, 8'd95, 8'd95, 8'd95, 8'd0, 8'd0, 8'd0, 8'd0, 8'd95, 8'd95, 8'd95, 8'd95} : 288'bx; 11 | endmodule -------------------------------------------------------------------------------- /Verilog/FAST9_Top.v: -------------------------------------------------------------------------------- 1 | module FAST9_Top (clock, nReset, refAddr, outPixel); 2 | input clock; 3 | input nReset; 4 | output [14:0] refAddr; 5 | output [7:0] outPixel; 6 | 7 | wire isCorner; // 코너 확인 8 | wire [31:0] compare; // DARK, BRIGHT, SIMILAR 값 9 | wire [14:0] refAddr; // 기준점 주소 10 | wire [7:0] refPixel; // 기준점 데이터 11 | wire [127:0] adjPixel; // 인접한 16개의 점 데이터 12 | wire [7:0] thres; // 임계값 13 | wire [14:0] outAddr; // 최종 코너 주소 14 | wire [7:0] outPixel; // 최종 코너 데이터 15 | wire [14:0] scoreAddr; // Score Memory 주소 16 | wire [7:0] scoreValue; // Score Memory에 저장할 값 17 | wire [7:0] scoreData; // Score Memory에서 Read한 값 18 | wire wren; // Score Memeory 쓰기 신호 19 | 20 | // Feature Detection 21 | FD_Top fd( 22 | .clock(clock), 23 | .nReset(nReset), 24 | .isCorner(isCorner), 25 | .refAddr(refAddr), 26 | .refPixel(refPixel), 27 | .adjPixel(adjPixel), 28 | .thres(thres), 29 | .compare(compare) 30 | ); 31 | 32 | // Feature Score 33 | FS_Top fs( 34 | .isCorner(isCorner), 35 | .compare(compare), 36 | .refAddr(refAddr), 37 | .refPixel(refPixel), 38 | .adjPixel(adjPixel), 39 | .thres(thres), 40 | .scoreValue(scoreValue), 41 | .wren(wren) 42 | ); 43 | 44 | // Non-Maximal Suppression 45 | NMS_Top nms( 46 | .clock(clock), 47 | .nReset(nReset), 48 | .refAddr(refAddr), 49 | .refPixel(refPixel), 50 | .scoreData(scoreData), 51 | .scoreAddr(scoreAddr), 52 | .outAddr(outAddr), 53 | .outPixel(outPixel) 54 | ); 55 | 56 | // Score Memory 57 | FS_ScoreMem scoreMem( 58 | .clock(clock), 59 | .address(scoreAddr), 60 | .data(scoreValue), 61 | .wren(wren), 62 | .q(scoreData) 63 | ); 64 | endmodule -------------------------------------------------------------------------------- /Verilog/FD_AddrCal.v: -------------------------------------------------------------------------------- 1 | `define COLUMNS 8'd180 2 | `define ROWS 8'd120 3 | 4 | module FD_AddrCal (refAddr, adjNumber, sramAddr); 5 | input [14:0] refAddr; // 기준점 6 | input [4:0] adjNumber; // 인접한 16개의 점 7 | output [14:0] sramAddr; // SRAM의 Input 주소 8 | 9 | assign sramAddr = 10 | (adjNumber == 5'd0) ? refAddr : // 기준점 11 | (adjNumber == 5'd1) ? refAddr - (3 * `COLUMNS) : // 1 12 | (adjNumber == 5'd2) ? refAddr - (3 * `COLUMNS) + 1 : // 2 13 | (adjNumber == 5'd3) ? refAddr - (2 * `COLUMNS) + 2 : // 3 14 | (adjNumber == 5'd4) ? refAddr - (1 * `COLUMNS) + 3 : // 4 15 | (adjNumber == 5'd5) ? refAddr + 3 : // 5 16 | (adjNumber == 5'd6) ? refAddr + (1 * `COLUMNS) + 3 : // 6 17 | (adjNumber == 5'd7) ? refAddr + (2 * `COLUMNS) + 2 : // 7 18 | (adjNumber == 5'd8) ? refAddr + (3 * `COLUMNS) + 1 : // 8 19 | (adjNumber == 5'd9) ? refAddr + (3 * `COLUMNS) : // 9 20 | (adjNumber == 5'd10) ? refAddr + (3 * `COLUMNS) - 1 : // 10 21 | (adjNumber == 5'd11) ? refAddr + (2 * `COLUMNS) - 2 : // 11 22 | (adjNumber == 5'd12) ? refAddr + (1 * `COLUMNS) - 3 : // 12 23 | (adjNumber == 5'd13) ? refAddr - 3 : // 13 24 | (adjNumber == 5'd14) ? refAddr - (1 * `COLUMNS) - 3 : // 14 25 | (adjNumber == 5'd15) ? refAddr - (2 * `COLUMNS) - 2 : // 15 26 | (adjNumber == 5'd16) ? refAddr - (3 * `COLUMNS) - 1 : 15'bx; // 16 27 | endmodule -------------------------------------------------------------------------------- /Verilog/FD_Controller.v: -------------------------------------------------------------------------------- 1 | `define INIT 5'd20 2 | `define S0 5'd0 3 | `define S1 5'd1 4 | `define S2 5'd2 5 | `define S3 5'd3 6 | `define S4 5'd4 7 | `define S5 5'd5 8 | `define S6 5'd6 9 | `define S7 5'd7 10 | `define S8 5'd8 11 | `define S9 5'd9 12 | `define S10 5'd10 13 | `define S11 5'd11 14 | `define S12 5'd12 15 | `define S13 5'd13 16 | `define S14 5'd14 17 | `define S15 5'd15 18 | `define S16 5'd16 19 | `define S17 5'd17 20 | `define S18 5'd18 21 | `define S19 5'd19 22 | 23 | module FD_Controller (clock, nReset, refAddr, adjNumber, regAddr, readen); 24 | input clock; 25 | input nReset; 26 | output [14:0] refAddr; 27 | output [4:0] adjNumber; 28 | output [4:0] regAddr; 29 | output readen; 30 | 31 | reg [14:0] refAddr; // 기준점 주소 32 | reg [4:0] adjNumber; // 16개의 점 Index 33 | reg [4:0] regAddr; // 레지스터 주소 34 | reg readen; // Datapath가 수행될 수 있도록 하는 enable 신호 35 | 36 | reg [4:0] curState, nextState; // 상태 변화 37 | 38 | // 클락이 상승할 때마다 현재 상태에서 다음상태로 변화 39 | always @(posedge clock or negedge nReset) begin 40 | if (!nReset) 41 | curState <= `INIT; 42 | else 43 | curState <= nextState; 44 | end 45 | 46 | // FSM 47 | always @(curState) begin 48 | casex (curState) 49 | `INIT: begin 50 | nextState = `S0; 51 | adjNumber = 5'bx; 52 | regAddr = 5'bx; 53 | readen = 1'b0; 54 | 55 | if (refAddr == 15'd21056) 56 | refAddr = 15'd543; 57 | //else if (refAddr % 177 == 0) 58 | // refAddr = refAddr + 7; 59 | else if (refAddr != 0) 60 | refAddr = refAddr + 1; 61 | else 62 | refAddr = 15'd543; 63 | end 64 | 65 | `S0: begin 66 | nextState = `S1; 67 | adjNumber = `S0; 68 | regAddr = 5'bx; 69 | end 70 | 71 | `S1: begin 72 | nextState = `S2; 73 | adjNumber = `S1; 74 | regAddr = 5'bx; 75 | end 76 | 77 | `S2: begin 78 | nextState = `S3; 79 | adjNumber = `S2; 80 | regAddr = `S0; 81 | end 82 | 83 | `S3: begin 84 | nextState = `S4; 85 | adjNumber = `S3; 86 | regAddr = `S1; 87 | end 88 | 89 | `S4: begin 90 | nextState = `S5; 91 | adjNumber = `S4; 92 | regAddr = `S2; 93 | end 94 | 95 | `S5: begin 96 | nextState = `S6; 97 | adjNumber = `S5; 98 | regAddr = `S3; 99 | end 100 | 101 | `S6: begin 102 | nextState = `S7; 103 | adjNumber = `S6; 104 | regAddr = `S4; 105 | end 106 | 107 | `S7: begin 108 | nextState = `S8; 109 | adjNumber = `S7; 110 | regAddr = `S5; 111 | end 112 | 113 | `S8: begin 114 | nextState = `S9; 115 | adjNumber = `S8; 116 | regAddr = `S6; 117 | end 118 | 119 | `S9: begin 120 | nextState = `S10; 121 | adjNumber = `S9; 122 | regAddr = `S7; 123 | end 124 | 125 | `S10: begin 126 | nextState = `S11; 127 | adjNumber = `S10; 128 | regAddr = `S8; 129 | end 130 | 131 | `S11: begin 132 | nextState = `S12; 133 | adjNumber = `S11; 134 | regAddr = `S9; 135 | end 136 | 137 | `S12: begin 138 | nextState = `S13; 139 | adjNumber = `S12; 140 | regAddr = `S10; 141 | end 142 | 143 | `S13: begin 144 | nextState = `S14; 145 | adjNumber = `S13; 146 | regAddr = `S11; 147 | end 148 | 149 | `S14: begin 150 | nextState = `S15; 151 | adjNumber = `S14; 152 | regAddr = `S12; 153 | end 154 | 155 | `S15: begin 156 | nextState = `S16; 157 | adjNumber = `S15; 158 | regAddr = `S13; 159 | end 160 | 161 | `S16: begin 162 | nextState = `S17; 163 | adjNumber = `S16; 164 | regAddr = `S14; 165 | end 166 | 167 | `S17: begin 168 | nextState = `S18; 169 | adjNumber = 5'bx; 170 | regAddr = `S15; 171 | end 172 | 173 | `S18: begin 174 | nextState = `S19; 175 | adjNumber = 5'bx; 176 | regAddr = `S16; 177 | end 178 | 179 | `S19: begin 180 | nextState = `INIT; 181 | adjNumber = 5'bx; 182 | regAddr = 5'bx; 183 | readen = 1'b1; 184 | end 185 | endcase 186 | end 187 | endmodule -------------------------------------------------------------------------------- /Verilog/FD_Datapath.v: -------------------------------------------------------------------------------- 1 | `define SIMILAR 2'b00 2 | `define DARK 2'b01 3 | `define BRIGHT 2'b10 4 | 5 | module FD_Datapath (refPixel, adjPixel, thres, isCorner, compare); 6 | input [7:0] refPixel; // 기준점 데이터 7 | input [127:0] adjPixel; // 16개의 점 데이터 8 | input [7:0] thres; // 임계값 9 | output isCorner; // 코너 확인 10 | output [31:0] compare; // 16개의 점에 대해서 각각 DARK, BRIGHT, SIMILAR를 저장 11 | 12 | wire [8:0] lower; // 기준점 - 임계값 13 | wire [8:0] upper; // 기준점 + 임계값 14 | 15 | assign lower = ((refPixel - thres) > 255) ? 8'd0 : (refPixel - thres); // 하한 16 | assign upper = ((refPixel + thres) > 255) ? 8'd255 : (refPixel + thres); // 상한 17 | 18 | // 01 = DARK, 10 = BRIGHT, 00 = SIMILAR 19 | assign compare[31:30] = ({1'b0, adjPixel[127:120]} < lower) ? `DARK : ({1'b0, adjPixel[127:120]} > upper) ? `BRIGHT : `SIMILAR; 20 | assign compare[29:28] = ({1'b0, adjPixel[119:112]} < lower) ? `DARK : ({1'b0, adjPixel[119:112]} > upper) ? `BRIGHT : `SIMILAR; 21 | assign compare[27:26] = ({1'b0, adjPixel[111:104]} < lower) ? `DARK : ({1'b0, adjPixel[111:104]} > upper) ? `BRIGHT : `SIMILAR; 22 | assign compare[25:24] = ({1'b0, adjPixel[103:96]} < lower) ? `DARK : ({1'b0, adjPixel[103:96]} > upper) ? `BRIGHT : `SIMILAR; 23 | assign compare[23:22] = ({1'b0, adjPixel[95:88]} < lower) ? `DARK : ({1'b0, adjPixel[95:88]} > upper) ? `BRIGHT : `SIMILAR; 24 | assign compare[21:20] = ({1'b0, adjPixel[87:80]} < lower) ? `DARK : ({1'b0, adjPixel[87:80]} > upper) ? `BRIGHT : `SIMILAR; 25 | assign compare[19:18] = ({1'b0, adjPixel[79:72]} < lower) ? `DARK : ({1'b0, adjPixel[79:72]} > upper) ? `BRIGHT : `SIMILAR; 26 | assign compare[17:16] = ({1'b0, adjPixel[71:64]} < lower) ? `DARK : ({1'b0, adjPixel[71:64]} > upper) ? `BRIGHT : `SIMILAR; 27 | assign compare[15:14] = ({1'b0, adjPixel[63:56]} < lower) ? `DARK : ({1'b0, adjPixel[63:56]} > upper) ? `BRIGHT : `SIMILAR; 28 | assign compare[13:12] = ({1'b0, adjPixel[55:48]} < lower) ? `DARK : ({1'b0, adjPixel[55:48]} > upper) ? `BRIGHT : `SIMILAR; 29 | assign compare[11:10] = ({1'b0, adjPixel[47:40]} < lower) ? `DARK : ({1'b0, adjPixel[47:40]} > upper) ? `BRIGHT : `SIMILAR; 30 | assign compare[9:8] = ({1'b0, adjPixel[39:32]} < lower) ? `DARK : ({1'b0, adjPixel[39:32]} > upper) ? `BRIGHT : `SIMILAR; 31 | assign compare[7:6] = ({1'b0, adjPixel[31:24]} < lower) ? `DARK : ({1'b0, adjPixel[31:24]} > upper) ? `BRIGHT : `SIMILAR; 32 | assign compare[5:4] = ({1'b0, adjPixel[23:16]} < lower) ? `DARK : ({1'b0, adjPixel[23:16]} > upper) ? `BRIGHT : `SIMILAR; 33 | assign compare[3:2] = ({1'b0, adjPixel[15:8]} < lower) ? `DARK : ({1'b0, adjPixel[15:8]} > upper) ? `BRIGHT : `SIMILAR; 34 | assign compare[1:0] = ({1'b0, adjPixel[7:0]} < lower) ? `DARK : ({1'b0, adjPixel[7:0]} > upper) ? `BRIGHT : `SIMILAR; 35 | 36 | // 9개의 연속한 점이 DARK 또는 BRIGHT인 모든 경우의 수를 비교하여 코너 확인 37 | assign isCorner = 38 | (compare[31:14] == 18'h15555) ? 1'b1 : 39 | (compare[31:14] == 18'h2AAAA) ? 1'b1 : 40 | (compare[29:12] == 18'h15555) ? 1'b1 : 41 | (compare[29:12] == 18'h2AAAA) ? 1'b1 : 42 | (compare[27:10] == 18'h15555) ? 1'b1 : 43 | (compare[27:10] == 18'h2AAAA) ? 1'b1 : 44 | (compare[25:8] == 18'h15555) ? 1'b1 : 45 | (compare[25:8] == 18'h2AAAA) ? 1'b1 : 46 | (compare[23:6] == 18'h15555) ? 1'b1 : 47 | (compare[23:6] == 18'h2AAAA) ? 1'b1 : 48 | (compare[21:4] == 18'h15555) ? 1'b1 : 49 | (compare[21:4] == 18'h2AAAA) ? 1'b1 : 50 | (compare[19:2] == 18'h15555) ? 1'b1 : 51 | (compare[19:2] == 18'h2AAAA) ? 1'b1 : 52 | (compare[17:0] == 18'h15555) ? 1'b1 : 53 | (compare[17:0] == 18'h2AAAA) ? 1'b1 : 54 | ((compare[31:30] == 2'b10) && (compare[15:0] == 16'hAAAA)) ? 1'b1 : 55 | ((compare[31:30] == 2'b01) && (compare[15:0] == 16'h5555)) ? 1'b1 : 56 | ((compare[31:28] == 4'hA) && (compare[13:0] == 14'h2AAA)) ? 1'b1 : 57 | ((compare[31:28] == 4'h5) && (compare[13:0] == 14'h1555)) ? 1'b1 : 58 | ((compare[31:26] == 6'h2A) && (compare[11:0] == 12'hAAA)) ? 1'b1 : 59 | ((compare[31:26] == 6'h15) && (compare[11:0] == 12'h555)) ? 1'b1 : 60 | ((compare[31:24] == 8'hAA) && (compare[9:0] == 10'h2AA)) ? 1'b1 : 61 | ((compare[31:24] == 8'h55) && (compare[9:0] == 10'h155)) ? 1'b1 : 62 | ((compare[31:22] == 10'h2AA) && (compare[7:0] == 8'hAA)) ? 1'b1 : 63 | ((compare[31:22] == 10'h155) && (compare[7:0] == 8'h55)) ? 1'b1 : 64 | ((compare[31:20] == 12'hAAA) && (compare[5:0] == 6'h2A)) ? 1'b1 : 65 | ((compare[31:20] == 12'h555) && (compare[5:0] == 6'h15)) ? 1'b1 : 66 | ((compare[31:18] == 14'h2AAA) && (compare[3:0] == 4'hA)) ? 1'b1 : 67 | ((compare[31:18] == 14'h1555) && (compare[3:0] == 4'h5)) ? 1'b1 : 68 | ((compare[31:16] == 16'hAAAA) && (compare[1:0] == 2'b10)) ? 1'b1 : 69 | ((compare[31:16] == 16'h5555) && (compare[1:0] == 2'b01)) ? 1'b1 : 1'b0; 70 | endmodule -------------------------------------------------------------------------------- /Verilog/FD_Reg.v: -------------------------------------------------------------------------------- 1 | module FD_Reg (clock, nReset, readen, regAddr, sramData, refPixel, adjPixel, thres); 2 | input clock; 3 | input nReset; 4 | input readen; // Datapath에 input으로 값을 주기 위한 신호 5 | input [4:0] regAddr; // 레지스터 주소 6 | input [7:0] sramData; // 레지스터에 저장할 값 7 | output [7:0] refPixel; // 기준점 데이터 8 | output [127:0] adjPixel; // 인접한 16개의 점 데이터 9 | output [7:0] thres; // 임계값 10 | 11 | reg [7:0] refPoint; // 기준점 데이터를 저장 12 | reg [7:0] r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, r16; // 인접한 16개 점의 데이터를 저장 13 | 14 | // 주소로부터 저장할 레지스터를 선택하기 위한 디코더로 기준점의 데이터와, 인접한 16개의 점의 데이터를 저장한다. 15 | wire [16:0] decoder; 16 | assign decoder = 17 | (regAddr == 5'd0) ? 17'd1 : 18 | (regAddr == 5'd1) ? 17'd2 : 19 | (regAddr == 5'd2) ? 17'd4 : 20 | (regAddr == 5'd3) ? 17'd8 : 21 | (regAddr == 5'd4) ? 17'd16 : 22 | (regAddr == 5'd5) ? 17'd32 : 23 | (regAddr == 5'd6) ? 17'd64 : 24 | (regAddr == 5'd7) ? 17'd128 : 25 | (regAddr == 5'd8) ? 17'd256 : 26 | (regAddr == 5'd9) ? 17'd512 : 27 | (regAddr == 5'd10) ? 17'd1024 : 28 | (regAddr == 5'd11) ? 17'd2048 : 29 | (regAddr == 5'd12) ? 17'd4096 : 30 | (regAddr == 5'd13) ? 17'd8192 : 31 | (regAddr == 5'd14) ? 17'd16384 : 32 | (regAddr == 5'd15) ? 17'd32768 : 33 | (regAddr == 5'd16) ? 17'd65536 : 17'bx; 34 | 35 | always @ (posedge clock or negedge nReset) 36 | if (!nReset) 37 | refPoint <= 8'bx; 38 | else if (decoder[0]) 39 | refPoint <= sramData; 40 | 41 | always @ (posedge clock or negedge nReset) 42 | if (!nReset) 43 | r1 <= 8'bx; 44 | else if (decoder[1]) 45 | r1 <= sramData; 46 | 47 | always @ (posedge clock or negedge nReset) 48 | if (!nReset) 49 | r2 <= 8'bx; 50 | else if (decoder[2]) 51 | r2 <= sramData; 52 | 53 | always @ (posedge clock or negedge nReset) 54 | if (!nReset) 55 | r3 <= 8'bx; 56 | else if (decoder[3]) 57 | r3 <= sramData; 58 | 59 | always @ (posedge clock or negedge nReset) 60 | if (!nReset) 61 | r4 <= 8'bx; 62 | else if (decoder[4]) 63 | r4 <= sramData; 64 | 65 | always @ (posedge clock or negedge nReset) 66 | if (!nReset) 67 | r5 <= 8'bx; 68 | else if (decoder[5]) 69 | r5 <= sramData; 70 | 71 | always @ (posedge clock or negedge nReset) 72 | if (!nReset) 73 | r6 <= 8'bx; 74 | else if (decoder[6]) 75 | r6 <= sramData; 76 | 77 | always @ (posedge clock or negedge nReset) 78 | if (!nReset) 79 | r7 <= 8'bx; 80 | else if (decoder[7]) 81 | r7 <= sramData; 82 | 83 | always @ (posedge clock or negedge nReset) 84 | if (!nReset) 85 | r8 <= 8'bx; 86 | else if (decoder[8]) 87 | r8 <= sramData; 88 | 89 | always @ (posedge clock or negedge nReset) 90 | if (!nReset) 91 | r9 <= 8'bx; 92 | else if (decoder[9]) 93 | r9 <= sramData; 94 | 95 | always @ (posedge clock or negedge nReset) 96 | if (!nReset) 97 | r10 <= 8'bx; 98 | else if (decoder[10]) 99 | r10 <= sramData; 100 | 101 | always @ (posedge clock or negedge nReset) 102 | if (!nReset) 103 | r11 <= 8'bx; 104 | else if (decoder[11]) 105 | r11 <= sramData; 106 | 107 | always @ (posedge clock or negedge nReset) 108 | if (!nReset) 109 | r12 <= 8'bx; 110 | else if (decoder[12]) 111 | r12 <= sramData; 112 | 113 | always @ (posedge clock or negedge nReset) 114 | if (!nReset) 115 | r13 <= 8'bx; 116 | else if (decoder[13]) 117 | r13 <= sramData; 118 | 119 | always @ (posedge clock or negedge nReset) 120 | if (!nReset) 121 | r14 <= 8'bx; 122 | else if (decoder[14]) 123 | r14 <= sramData; 124 | 125 | always @ (posedge clock or negedge nReset) 126 | if (!nReset) 127 | r15 <= 8'bx; 128 | else if (decoder[15]) 129 | r15 <= sramData; 130 | 131 | always @ (posedge clock or negedge nReset) 132 | if (!nReset) 133 | r16 <= 8'bx; 134 | else if (decoder[16]) 135 | r16 <= sramData; 136 | 137 | // readen이 1로 셋팅 되면 기준점 데이터와, 16개의 인접한 점의 데이터를 한번에 Output으로 보낸다. 138 | assign refPixel = (readen) ? refPoint : 8'bx; // 기준점 139 | assign adjPixel = (readen) ? {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, r16} : 128'bx; // 16개 점 140 | assign thres = (readen) ? 8'd30 : 8'bx; // 임게값 141 | endmodule -------------------------------------------------------------------------------- /Verilog/FD_Testbench.v: -------------------------------------------------------------------------------- 1 | module FD_Testbench; 2 | reg clock; 3 | reg nReset; 4 | 5 | wire isCorner; // 코너 확인 6 | wire [14:0] refAddr; // 기준점 주소 7 | wire [7:0] refPixel; // 기준점 데이터 8 | wire [127:0] adjPixel; // 인접한 16개의 점 데이터 9 | wire [7:0] thres; // 임계값 10 | wire [31:0] compare; 11 | 12 | always begin 13 | #10 clock = ~clock; 14 | if (clock && isCorner) // 코너로 확인된 특징점인 경우에 출력 15 | $display($time, " isCorner: %d, refAddr: %d, refPixel: %h", isCorner, refAddr - 1, refPixel); 16 | end 17 | 18 | // Feature Detection Top Module 19 | FD_Top fd( 20 | .clock(clock), 21 | .nReset(nReset), 22 | .isCorner(isCorner), 23 | .refAddr(refAddr), 24 | .refPixel(refPixel), 25 | .adjPixel(adjPixel), 26 | .thres(thres), 27 | .compare(compare) 28 | ); 29 | 30 | initial begin 31 | clock = 1'b0; 32 | nReset = 1'b1; 33 | #100 nReset = 1'b0; 34 | #100 nReset = 1'b1; 35 | 36 | #10000000 $finish; 37 | end 38 | endmodule -------------------------------------------------------------------------------- /Verilog/FD_Top.v: -------------------------------------------------------------------------------- 1 | module FD_Top (clock, nReset, isCorner, refAddr, refPixel, adjPixel, thres, compare); 2 | input clock; 3 | input nReset; 4 | output isCorner; // Corner 확인 5 | output [14:0] refAddr; // 기준점 주소 6 | output [7:0] refPixel; // 기준점 데이터 7 | output [127:0] adjPixel; // 인접한 16개의 점 데이터 8 | output [7:0] thres; // 임계값 9 | output [31:0] compare; 10 | 11 | wire [4:0] adjNumber; // 1~16개의 인접한 점 12 | wire [4:0] regAddr; // 레지스터 주소 13 | wire [14:0] sramAddr; // SRAM 주소 14 | wire [7:0] sramData; // SRAM Output 데이터 15 | 16 | // Controller, 기준점과 인접한 16개의 주소를 얻어, 레지스터에 저장하는 과정을 제어 17 | FD_Controller controller( 18 | .clock(clock), 19 | .nReset(nReset), 20 | .refAddr(refAddr), 21 | .adjNumber(adjNumber), 22 | .regAddr(regAddr), 23 | .readen(readen) 24 | ); 25 | 26 | // 기준점으로 부터 인접한 16개의 점을 계산 27 | FD_AddrCal addrCal( 28 | .refAddr(refAddr), 29 | .adjNumber(adjNumber), 30 | .sramAddr(sramAddr) 31 | ); 32 | 33 | // 이미지 데이터가 저장된 SRAM 34 | SRAM sram( 35 | .clock(clock), 36 | .address(sramAddr), 37 | .data(8'bx), 38 | .wren(1'b0), 39 | .q(sramData) 40 | ); 41 | 42 | // 기준점과 인접한 16개의 점을 저장할 레지스터 파일 43 | FD_Reg fd_reg( 44 | .clock(clock), 45 | .nReset(nReset), 46 | .readen(readen), 47 | .regAddr(regAddr), 48 | .sramData(sramData), 49 | .refPixel(refPixel), 50 | .adjPixel(adjPixel), 51 | .thres(thres) 52 | ); 53 | 54 | // 레지스터에 저장된 기준점과 인접한 16개의 점의 데이터를 이용하여 코너 확인 55 | FD_Datapath datapath( 56 | .refPixel(refPixel), 57 | .adjPixel(adjPixel), 58 | .thres(thres), 59 | .isCorner(isCorner), 60 | .compare(compare) 61 | ); 62 | endmodule -------------------------------------------------------------------------------- /Verilog/FS_Datapath.v: -------------------------------------------------------------------------------- 1 | `define SIMILAR 2'b00 2 | `define DARK 2'b01 3 | `define BRIGHT 2'b10 4 | 5 | module FS_Datapath (isCorner, compare, refPixel, adjPixel, thres, wren, scoreValue); 6 | input isCorner; // 코너 확인 7 | input [31:0] compare; // DARK, BRIGHT, SIMILAR 값 8 | input [7:0] refPixel; // 기준점 데이터 9 | input [127:0] adjPixel; // 인접한 16개의 점 데이터 10 | input [7:0] thres; // 임계값 11 | output wren; // 쓰기 신호 12 | output [7:0] scoreValue; // 코너 점수 값 13 | 14 | wire [11:0] sBright; // Bright Set 점수 15 | wire [11:0] sDark; // Dark Set 점수 16 | 17 | // Calculate dark set 18 | assign sDark = 19 | ((compare[31:30] == `DARK) ? 20 | (((refPixel - adjPixel[127:120]) > 255) ? 21 | (adjPixel[127:120] - refPixel - thres) : (refPixel - adjPixel[127:120] - thres)) : 12'b0) + 22 | ((compare[29:28] == `DARK) ? 23 | (((refPixel - adjPixel[119:112]) > 255) ? 24 | (adjPixel[119:112] - refPixel - thres) : (refPixel - adjPixel[119:112] - thres)) : 12'b0) + 25 | ((compare[27:26] == `DARK) ? 26 | (((refPixel - adjPixel[111:104]) > 255) ? 27 | (adjPixel[111:104] - refPixel - thres) : (refPixel - adjPixel[111:104] - thres)) : 12'b0) + 28 | ((compare[25:24] == `DARK) ? 29 | (((refPixel - adjPixel[103:96]) > 255) ? 30 | (adjPixel[103:96] - refPixel - thres) : (refPixel - adjPixel[103:96] - thres)) : 12'b0) + 31 | ((compare[23:22] == `DARK) ? 32 | (((refPixel - adjPixel[95:88]) > 255) ? 33 | (adjPixel[95:88] - refPixel - thres) : (refPixel - adjPixel[95:88] - thres)) : 12'b0) + 34 | ((compare[21:20] == `DARK) ? 35 | (((refPixel - adjPixel[87:80]) > 255) ? 36 | (adjPixel[87:80] - refPixel - thres) : (refPixel - adjPixel[87:80] - thres)) : 12'b0) + 37 | ((compare[19:18] == `DARK) ? 38 | (((refPixel - adjPixel[79:72]) > 255) ? 39 | (adjPixel[79:72] - refPixel - thres) : (refPixel - adjPixel[79:72] - thres)) : 12'b0) + 40 | ((compare[17:16] == `DARK) ? 41 | (((refPixel - adjPixel[71:64]) > 255) ? 42 | (adjPixel[71:64] - refPixel - thres) : (refPixel - adjPixel[71:64] - thres)) : 12'b0) + 43 | ((compare[15:14] == `DARK) ? 44 | (((refPixel - adjPixel[63:56]) > 255) ? 45 | (adjPixel[63:56] - refPixel - thres) : (refPixel - adjPixel[63:56] - thres)) : 12'b0) + 46 | ((compare[13:12] == `DARK) ? 47 | (((refPixel - adjPixel[55:48]) > 255) ? 48 | (adjPixel[55:48] - refPixel - thres) : (refPixel - adjPixel[55:48] - thres)) : 12'b0) + 49 | ((compare[11:10] == `DARK) ? 50 | (((refPixel - adjPixel[47:40]) > 255) ? 51 | (adjPixel[47:40] - refPixel - thres) : (refPixel - adjPixel[47:40] - thres)) : 12'b0) + 52 | ((compare[9:8] == `DARK) ? 53 | (((refPixel - adjPixel[39:32]) > 255) ? 54 | (adjPixel[39:32] - refPixel - thres) : (refPixel - adjPixel[39:32] - thres)) : 12'b0) + 55 | ((compare[7:6] == `DARK) ? 56 | (((refPixel - adjPixel[31:24]) > 255) ? 57 | (adjPixel[31:24] - refPixel - thres) : (refPixel - adjPixel[31:24] - thres)) : 12'b0) + 58 | ((compare[5:4] == `DARK) ? 59 | (((refPixel - adjPixel[23:16]) > 255) ? 60 | (adjPixel[23:16] - refPixel - thres) : (refPixel - adjPixel[23:16] - thres)) : 12'b0) + 61 | ((compare[3:2] == `DARK) ? 62 | (((refPixel - adjPixel[15:8]) > 255) ? 63 | (adjPixel[15:8] - refPixel - thres) : (refPixel - adjPixel[15:8] - thres)) : 12'b0) + 64 | ((compare[1:0] == `DARK) ? 65 | (((refPixel - adjPixel[7:0]) > 255) ? 66 | (adjPixel[7:0] - refPixel - thres) : (refPixel - adjPixel[7:0] - thres)) : 12'b0); 67 | 68 | // Calculate bright set 69 | assign sBright = 70 | ((compare[31:30] == `BRIGHT) ? 71 | (((adjPixel[127:120] - refPixel) > 255) ? 72 | (refPixel - adjPixel[127:120] - thres) : (adjPixel[127:120] - refPixel - thres)) : 12'b0) + 73 | ((compare[29:28] == `BRIGHT) ? 74 | (((adjPixel[119:112] - refPixel) > 255) ? 75 | (refPixel - adjPixel[119:112] - thres) : (adjPixel[119:112] - refPixel - thres)) : 12'b0) + 76 | ((compare[27:26] == `BRIGHT) ? 77 | (((adjPixel[111:104] - refPixel) > 255) ? 78 | (refPixel - adjPixel[111:104] - thres) : (adjPixel[111:104] - refPixel - thres)) : 12'b0) + 79 | ((compare[25:24] == `BRIGHT) ? 80 | (((adjPixel[103:96] - refPixel) > 255) ? 81 | (refPixel - adjPixel[103:96] - thres) : (adjPixel[103:96] - refPixel - thres)) : 12'b0) + 82 | ((compare[23:22] == `BRIGHT) ? 83 | (((adjPixel[95:88] - refPixel) > 255) ? 84 | (refPixel - adjPixel[95:88] - thres) : (adjPixel[95:88] - refPixel - thres)) : 12'b0) + 85 | ((compare[21:20] == `BRIGHT) ? 86 | (((adjPixel[87:80] - refPixel) > 255) ? 87 | (refPixel - adjPixel[87:80] - thres) : (adjPixel[87:80] - refPixel - thres)) : 12'b0) + 88 | ((compare[19:18] == `BRIGHT) ? 89 | (((adjPixel[79:72] - refPixel) > 255) ? 90 | (refPixel - adjPixel[79:72] - thres) : (adjPixel[79:72] - refPixel - thres)) : 12'b0) + 91 | ((compare[17:16] == `BRIGHT) ? 92 | (((adjPixel[71:64] - refPixel) > 255) ? 93 | (refPixel - adjPixel[71:64] - thres) : (adjPixel[71:64] - refPixel - thres)) : 12'b0) + 94 | ((compare[15:14] == `BRIGHT) ? 95 | (((adjPixel[63:56] - refPixel) > 255) ? 96 | (refPixel - adjPixel[63:56] - thres) : (adjPixel[63:56] - refPixel - thres)) : 12'b0) + 97 | ((compare[13:12] == `BRIGHT) ? 98 | (((adjPixel[55:48] - refPixel) > 255) ? 99 | (refPixel - adjPixel[55:48] - thres) : (adjPixel[55:48] - refPixel - thres)) : 12'b0) + 100 | ((compare[11:10] == `BRIGHT) ? 101 | (((adjPixel[47:40] - refPixel) > 255) ? 102 | (refPixel - adjPixel[47:40] - thres) : (adjPixel[47:40] - refPixel - thres)) : 12'b0) + 103 | ((compare[9:8] == `BRIGHT) ? 104 | (((adjPixel[39:32] - refPixel) > 255) ? 105 | (refPixel - adjPixel[39:32] - thres) : (adjPixel[39:32] - refPixel - thres)) : 12'b0) + 106 | ((compare[7:6] == `BRIGHT) ? 107 | (((adjPixel[31:24] - refPixel) > 255) ? 108 | (refPixel - adjPixel[31:24] - thres) : (adjPixel[31:24] - refPixel - thres)) : 12'b0) + 109 | ((compare[5:4] == `BRIGHT) ? 110 | (((adjPixel[23:16] - refPixel) > 255) ? 111 | (refPixel - adjPixel[23:16] - thres) : (adjPixel[23:16] - refPixel - thres)) : 12'b0) + 112 | ((compare[3:2] == `BRIGHT) ? 113 | (((adjPixel[15:8] - refPixel) > 255) ? 114 | (refPixel - adjPixel[15:8] - thres) : (adjPixel[15:8] - refPixel - thres)) : 12'b0) + 115 | ((compare[1:0] == `BRIGHT) ? 116 | (((adjPixel[7:0] - refPixel) > 255) ? 117 | (refPixel - adjPixel[7:0] - thres) : (adjPixel[7:0] - refPixel - thres)) : 12'b0); 118 | 119 | assign scoreValue = (sBright >= sDark) ? sBright : sDark; // Dark, Bright Set 중 큰 점수가 최종 스코어로 결정 120 | assign wren = isCorner; // 코너인 경우에만 스코어 SRAM에 저장하기 위해 쓰기 신호를 셋. 121 | endmodule -------------------------------------------------------------------------------- /Verilog/FS_ScoreMem.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "FS_ScoreMem.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FS_ScoreMem_bb.v"] 5 | -------------------------------------------------------------------------------- /Verilog/FS_ScoreMem.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: FS_ScoreMem.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.1.0 Build 162 10/23/2013 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module FS_ScoreMem ( 40 | address, 41 | clock, 42 | data, 43 | wren, 44 | q); 45 | 46 | input [14:0] address; 47 | input clock; 48 | input [7:0] data; 49 | input wren; 50 | output [7:0] q; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_off 53 | `endif 54 | tri1 clock; 55 | `ifndef ALTERA_RESERVED_QIS 56 | // synopsys translate_on 57 | `endif 58 | 59 | wire [7:0] sub_wire0; 60 | wire [7:0] q = sub_wire0[7:0]; 61 | 62 | altsyncram altsyncram_component ( 63 | .address_a (address), 64 | .clock0 (clock), 65 | .data_a (data), 66 | .wren_a (wren), 67 | .q_a (sub_wire0), 68 | .aclr0 (1'b0), 69 | .aclr1 (1'b0), 70 | .address_b (1'b1), 71 | .addressstall_a (1'b0), 72 | .addressstall_b (1'b0), 73 | .byteena_a (1'b1), 74 | .byteena_b (1'b1), 75 | .clock1 (1'b1), 76 | .clocken0 (1'b1), 77 | .clocken1 (1'b1), 78 | .clocken2 (1'b1), 79 | .clocken3 (1'b1), 80 | .data_b (1'b1), 81 | .eccstatus (), 82 | .q_b (), 83 | .rden_a (1'b1), 84 | .rden_b (1'b1), 85 | .wren_b (1'b0)); 86 | defparam 87 | altsyncram_component.clock_enable_input_a = "BYPASS", 88 | altsyncram_component.clock_enable_output_a = "BYPASS", 89 | altsyncram_component.intended_device_family = "Cyclone IV E", 90 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 91 | altsyncram_component.lpm_type = "altsyncram", 92 | altsyncram_component.numwords_a = 21600, 93 | altsyncram_component.operation_mode = "SINGLE_PORT", 94 | altsyncram_component.outdata_aclr_a = "NONE", 95 | altsyncram_component.outdata_reg_a = "CLOCK0", 96 | altsyncram_component.power_up_uninitialized = "FALSE", 97 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 98 | altsyncram_component.widthad_a = 15, 99 | altsyncram_component.width_a = 8, 100 | altsyncram_component.width_byteena_a = 1; 101 | 102 | 103 | endmodule 104 | 105 | // ============================================================ 106 | // CNX file retrieval info 107 | // ============================================================ 108 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 109 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 110 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 111 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 112 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 113 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 114 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 115 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 116 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 117 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 118 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 119 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 120 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 121 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 122 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 123 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 124 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 125 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 126 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 127 | // Retrieval info: PRIVATE: MIFfilename STRING "" 128 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "21600" 129 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 130 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 131 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 132 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 133 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 134 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 135 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 136 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 137 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 138 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "15" 139 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 140 | // Retrieval info: PRIVATE: rden NUMERIC "0" 141 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 142 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 143 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 144 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 145 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 146 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 147 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "21600" 148 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 149 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 150 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 151 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 152 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 153 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" 154 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 155 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 156 | // Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]" 157 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 158 | // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 159 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 160 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 161 | // Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0 162 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 163 | // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 164 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 165 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 166 | // Retrieval info: GEN_FILE: TYPE_NORMAL FS_ScoreMem.v TRUE 167 | // Retrieval info: GEN_FILE: TYPE_NORMAL FS_ScoreMem.inc FALSE 168 | // Retrieval info: GEN_FILE: TYPE_NORMAL FS_ScoreMem.cmp FALSE 169 | // Retrieval info: GEN_FILE: TYPE_NORMAL FS_ScoreMem.bsf FALSE 170 | // Retrieval info: GEN_FILE: TYPE_NORMAL FS_ScoreMem_inst.v FALSE 171 | // Retrieval info: GEN_FILE: TYPE_NORMAL FS_ScoreMem_bb.v TRUE 172 | // Retrieval info: LIB_FILE: altera_mf 173 | -------------------------------------------------------------------------------- /Verilog/FS_ScoreMem_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: FS_ScoreMem.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.1.0 Build 162 10/23/2013 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2013 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module FS_ScoreMem ( 35 | address, 36 | clock, 37 | data, 38 | wren, 39 | q); 40 | 41 | input [14:0] address; 42 | input clock; 43 | input [7:0] data; 44 | input wren; 45 | output [7:0] q; 46 | `ifndef ALTERA_RESERVED_QIS 47 | // synopsys translate_off 48 | `endif 49 | tri1 clock; 50 | `ifndef ALTERA_RESERVED_QIS 51 | // synopsys translate_on 52 | `endif 53 | 54 | endmodule 55 | 56 | // ============================================================ 57 | // CNX file retrieval info 58 | // ============================================================ 59 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 60 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 61 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 62 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 63 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 64 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 65 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 66 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 67 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 68 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 69 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 70 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 71 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 72 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 73 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 74 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 75 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 76 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 77 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 78 | // Retrieval info: PRIVATE: MIFfilename STRING "" 79 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "21600" 80 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 81 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 82 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 83 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 84 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 85 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 86 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 87 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 88 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 89 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "15" 90 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 91 | // Retrieval info: PRIVATE: rden NUMERIC "0" 92 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 93 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 94 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 95 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 96 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 97 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 98 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "21600" 99 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 100 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 101 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 102 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 103 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 104 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" 105 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 106 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 107 | // Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]" 108 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 109 | // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 110 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 111 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 112 | // Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0 113 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 114 | // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 115 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 116 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 117 | // Retrieval info: GEN_FILE: TYPE_NORMAL FS_ScoreMem.v TRUE 118 | // Retrieval info: GEN_FILE: TYPE_NORMAL FS_ScoreMem.inc FALSE 119 | // Retrieval info: GEN_FILE: TYPE_NORMAL FS_ScoreMem.cmp FALSE 120 | // Retrieval info: GEN_FILE: TYPE_NORMAL FS_ScoreMem.bsf FALSE 121 | // Retrieval info: GEN_FILE: TYPE_NORMAL FS_ScoreMem_inst.v FALSE 122 | // Retrieval info: GEN_FILE: TYPE_NORMAL FS_ScoreMem_bb.v TRUE 123 | // Retrieval info: LIB_FILE: altera_mf 124 | -------------------------------------------------------------------------------- /Verilog/FS_Testbench.v: -------------------------------------------------------------------------------- 1 | module FS_Testbench; 2 | reg clock; 3 | reg nReset; 4 | 5 | always begin 6 | #10 clock = ~clock; 7 | if (clock && fast9.fs.isCorner) // 코너로 확인된 특징점인 경우에 스코어를 출력 8 | $display("refAddr: %d, score: %h", fast9.fs.refAddr, fast9.fs.scoreValue); 9 | end 10 | 11 | // FAST-9 Alogrithm Top Module 12 | FAST9_Top fast9( 13 | .clock(clock), 14 | .nReset(nReset) 15 | ); 16 | 17 | initial begin 18 | clock = 1'b0; 19 | nReset = 1'b1; 20 | #100 nReset = 1'b0; 21 | #100 nReset = 1'b1; 22 | 23 | #10000000 $finish; 24 | end 25 | endmodule -------------------------------------------------------------------------------- /Verilog/FS_Top.v: -------------------------------------------------------------------------------- 1 | module FS_Top (isCorner, compare, refAddr, refPixel, adjPixel, thres, scoreValue, wren); 2 | input isCorner; // Corner 확인 3 | input [31:0] compare; // DARK, BRIGHT, SIMILAR 값 4 | input [14:0] refAddr; // 기준점 주소 5 | input [7:0] refPixel; // 기준점 데이터 6 | input [127:0] adjPixel; // 인접한 16개의 점 데이터 7 | input [7:0] thres; // 임계값 8 | output [7:0] scoreValue; // 점수 데이터 9 | output wren; // Score Memory에 쓰기 신호 10 | 11 | // 코너의 스코어를 계산하는 모듈 12 | FS_Datapath datapth( 13 | .isCorner(isCorner), 14 | .compare(compare), 15 | .refPixel(refPixel), 16 | .adjPixel(adjPixel), 17 | .thres(thres), 18 | .wren(wren), 19 | .scoreValue(scoreValue) 20 | ); 21 | endmodule -------------------------------------------------------------------------------- /Verilog/Mat_AddrCal.v: -------------------------------------------------------------------------------- 1 | `define COLUMNS 8'd180 2 | `define ROWS 8'd120 3 | 4 | module Mat_AddrCal (refAddr, adjNumber, FBAddr); 5 | input [14:0] refAddr; // 기준점 6 | input [2:0] adjNumber; // 인접한 8개의 점 번호 7 | output [14:0] FBAddr; // Frame Buffer의 Input 주소 8 | 9 | assign FBAddr = 10 | (adjNumber == 4'd0) ? refAddr - `COLUMNS : // 1 11 | (adjNumber == 4'd1) ? refAddr - `COLUMNS + 1 : // 2 12 | (adjNumber == 4'd2) ? refAddr + 1 : // 3 13 | (adjNumber == 4'd3) ? refAddr + `COLUMNS + 1 : // 4 14 | (adjNumber == 4'd4) ? refAddr + `COLUMNS : // 5 15 | (adjNumber == 4'd5) ? refAddr + `COLUMNS - 1 : // 6 16 | (adjNumber == 4'd6) ? refAddr - 1 : // 7 17 | (adjNumber == 4'd7) ? refAddr - `COLUMNS - 1 : 15'bx; // 8 18 | endmodule -------------------------------------------------------------------------------- /Verilog/Mat_Controller.v: -------------------------------------------------------------------------------- 1 | `define INIT 4'd15 2 | `define S0 4'd0 3 | `define S1 4'd1 4 | `define S2 4'd2 5 | `define S3 4'd3 6 | `define S4 4'd4 7 | `define S5 4'd5 8 | `define S6 4'd6 9 | `define S7 4'd7 10 | `define S8 4'd8 11 | `define S9 4'd9 12 | `define S10 4'd10 13 | 14 | module Mat_Controller (clock, nReset, refAddr, adjNumber, regAddr, matReaden); 15 | input clock; 16 | input nReset; 17 | input [14:0] refAddr; // 기준점 18 | output [2:0] adjNumber; // 인접한 점 번호 19 | output [2:0] regAddr; // 레지스터 주소 20 | output matReaden; 21 | 22 | reg [2:0] adjNumber; // 8개의 점 Index 23 | reg [2:0] regAddr; // 레지스터 주소 24 | reg matReaden; // Datapath가 수행될 수 있도록 하는 enable 신호 25 | 26 | reg [3:0] curState, nextState; // 상태 변화 27 | 28 | // Clock이 상승할 때마다 현재 상태에서 다음상태로 변화 29 | always @(posedge clock or negedge nReset) begin 30 | if (!nReset) 31 | curState <= `INIT; 32 | else 33 | curState <= nextState; 34 | end 35 | 36 | // FSM 37 | always @(curState or refAddr) begin 38 | casex (curState) 39 | `INIT: begin 40 | if (refAddr) 41 | nextState = `S0; 42 | 43 | adjNumber = 3'bx; 44 | regAddr = 3'bx; 45 | matReaden = 1'b0; 46 | end 47 | 48 | `S0: begin 49 | nextState = `S1; 50 | adjNumber = 3'd0; 51 | regAddr = 3'bx; 52 | end 53 | 54 | `S1: begin 55 | nextState = `S2; 56 | adjNumber = 3'd1; 57 | regAddr = 3'bx; 58 | end 59 | 60 | `S2: begin 61 | nextState = `S3; 62 | adjNumber = 3'd2; 63 | regAddr = 3'd0; 64 | end 65 | 66 | `S3: begin 67 | nextState = `S4; 68 | adjNumber = 3'd3; 69 | regAddr = 3'd1; 70 | end 71 | 72 | `S4: begin 73 | nextState = `S5; 74 | adjNumber = 3'd4; 75 | regAddr = 3'd2; 76 | end 77 | 78 | `S5: begin 79 | nextState = `S6; 80 | adjNumber = 3'd5; 81 | regAddr = 3'd3; 82 | end 83 | 84 | `S6: begin 85 | nextState = `S7; 86 | adjNumber = 3'd6; 87 | regAddr = 3'd4; 88 | end 89 | 90 | `S7: begin 91 | nextState = `S8; 92 | adjNumber = 3'd7; 93 | regAddr = 3'd5; 94 | end 95 | 96 | `S8: begin 97 | nextState = `S9; 98 | adjNumber = 3'dx; 99 | regAddr = 3'd6; 100 | end 101 | 102 | `S9: begin 103 | nextState = `S10; 104 | adjNumber = 3'dx; 105 | regAddr = 3'd7; 106 | end 107 | 108 | `S10: begin 109 | nextState = `INIT; 110 | adjNumber = 3'bx; 111 | regAddr = 3'bx; 112 | matReaden = 1'b1; 113 | end 114 | endcase 115 | end 116 | endmodule -------------------------------------------------------------------------------- /Verilog/Mat_Counter.v: -------------------------------------------------------------------------------- 1 | `define INIT 4'd0 2 | `define S1 4'd1 3 | `define S2 4'd2 4 | `define S3 4'd3 5 | `define S4 4'd4 6 | `define S5 4'd5 7 | `define S6 4'd6 8 | `define S7 4'd7 9 | `define S8 4'd8 10 | `define S9 4'd9 11 | `define S10 4'd10 12 | `define S11 4'd11 13 | `define S12 4'd12 14 | `define S13 4'd13 15 | `define S14 4'd14 16 | `define S15 4'd15 17 | 18 | module Mat_Counter (clock, nReset, matPoint, isFeature, posAddr, posReaden); 19 | input clock; 20 | input nReset; 21 | input matPoint; // Datapath에서 유효 특징점 여부 22 | input [7:0] isFeature; // 특징점 확인 변수 23 | output [3:0] posAddr; // 레지스터 주소 24 | output posReaden; // 매칭 여부 25 | 26 | reg [3:0] posAddr; 27 | reg posReaden; 28 | reg [3:0] curState, nextState; // 상태 변화 29 | 30 | // Clock이 상승할 때마다 현재 상태에서 다음상태로 변화 31 | always @(posedge clock or negedge nReset) begin 32 | if (!nReset) 33 | curState <= `INIT; 34 | else 35 | curState <= nextState; 36 | end 37 | 38 | // FSM 39 | always @(curState or matPoint or isFeature) begin 40 | casex (curState) 41 | `INIT: begin 42 | if (matPoint && isFeature) begin 43 | nextState = `S1; 44 | posAddr = 4'd0; 45 | posReaden = 1'b0; 46 | end 47 | end 48 | 49 | `S1: begin 50 | if (matPoint) begin 51 | nextState = `S2; 52 | posAddr = 4'd1; 53 | posReaden = 1'b0; 54 | end 55 | end 56 | 57 | `S2: begin 58 | if (matPoint) begin 59 | nextState = `S3; 60 | posAddr = 4'd2; 61 | posReaden = 1'b0; 62 | end 63 | end 64 | 65 | `S3: begin 66 | if (matPoint) begin 67 | nextState = `S4; 68 | posAddr = 4'd3; 69 | posReaden = 1'b0; 70 | end 71 | end 72 | 73 | `S4: begin 74 | if (matPoint) begin 75 | nextState = `S5; 76 | posAddr = 4'd4; 77 | posReaden = 1'b0; 78 | end 79 | end 80 | 81 | `S5: begin 82 | if (matPoint) begin 83 | nextState = `S6; 84 | posAddr = 4'd5; 85 | posReaden = 1'b0; 86 | end 87 | end 88 | 89 | `S6: begin 90 | if (matPoint) begin 91 | nextState = `S7; 92 | posAddr = 4'd6; 93 | posReaden = 1'b0; 94 | end 95 | end 96 | 97 | `S7: begin 98 | if (matPoint) begin 99 | nextState = `S8; 100 | posAddr = 4'd7; 101 | posReaden = 1'b0; 102 | end 103 | end 104 | 105 | `S8: begin 106 | if (matPoint) begin 107 | nextState = `S9; 108 | posAddr = 4'd8; 109 | posReaden = 1'b0; 110 | end 111 | end 112 | 113 | `S9: begin 114 | if (matPoint) begin 115 | nextState = `S10; 116 | posAddr = 4'd9; 117 | posReaden = 1'b0; 118 | end 119 | end 120 | 121 | `S10: begin 122 | if (matPoint) begin 123 | nextState = `S11; 124 | posAddr = 4'd10; 125 | posReaden = 1'b0; 126 | end 127 | end 128 | 129 | `S11: begin 130 | if (matPoint) begin 131 | nextState = `S12; 132 | posAddr = 4'd11; 133 | posReaden = 1'b0; 134 | end 135 | end 136 | 137 | `S12: begin 138 | if (matPoint) begin 139 | nextState = `S13; 140 | posAddr = 4'd12; 141 | posReaden = 1'b0; 142 | end 143 | end 144 | 145 | `S13: begin 146 | if (matPoint) begin 147 | nextState = `S14; 148 | posAddr = 4'd13; 149 | posReaden = 1'b0; 150 | end 151 | end 152 | 153 | `S14: begin 154 | if (matPoint) begin 155 | nextState = `S15; 156 | posAddr = 4'd14; 157 | posReaden = 1'b0; 158 | end 159 | end 160 | 161 | `S15: begin 162 | if (matPoint) begin 163 | nextState = `INIT; 164 | posAddr = 4'd15; 165 | posReaden = 1'b1; 166 | end 167 | end 168 | endcase 169 | end 170 | endmodule -------------------------------------------------------------------------------- /Verilog/Mat_Datapath.v: -------------------------------------------------------------------------------- 1 | module Mat_Datapath (adjFBPixel, dbValue, matPoint); 2 | input [63:0] adjFBPixel; // 인접한 8개의 점 데이터 3 | input [287:0] dbValue; // DB 데이터 4 | output matPoint; // 매칭 여부 5 | 6 | wire [7:0] refAvg; // 특징점 주변의 평균값 7 | wire [7:0] threshold; // 임계값 8 | 9 | // 임의 임계값 10 | assign threshold = 8'd30; 11 | 12 | // 특징점 평균값 계산 13 | assign refAvg = 14 | (adjFBPixel[7:0] + 15 | adjFBPixel[15:8] + 16 | adjFBPixel[23:16] + 17 | adjFBPixel[31:24] + 18 | adjFBPixel[39:32] + 19 | adjFBPixel[47:40] + 20 | adjFBPixel[55:48] + 21 | adjFBPixel[63:56]) / 8; 22 | 23 | // 각 뺄셈 결과가 threshold 이하 값이 나올 경우 해당 특징점은 유효 특징점으로 판단 24 | assign matPoint = 25 | (dbValue[7:0] - refAvg < threshold) ? 1'b1 : 26 | (dbValue[15:8] - refAvg < threshold) ? 1'b1 : 27 | (dbValue[23:16] - refAvg < threshold) ? 1'b1 : 28 | (dbValue[31:24] - refAvg < threshold) ? 1'b1 : 29 | (dbValue[39:32] - refAvg < threshold) ? 1'b1 : 30 | (dbValue[47:40] - refAvg < threshold) ? 1'b1 : 31 | (dbValue[55:48] - refAvg < threshold) ? 1'b1 : 32 | (dbValue[63:56] - refAvg < threshold) ? 1'b1 : 33 | (dbValue[71:64] - refAvg < threshold) ? 1'b1 : 34 | (dbValue[79:72] - refAvg < threshold) ? 1'b1 : 35 | (dbValue[87:80] - refAvg < threshold) ? 1'b1 : 36 | (dbValue[95:88] - refAvg < threshold) ? 1'b1 : 37 | (dbValue[103:96] - refAvg < threshold) ? 1'b1 : 38 | (dbValue[111:104] - refAvg < threshold) ? 1'b1 : 39 | (dbValue[119:112] - refAvg < threshold) ? 1'b1 : 40 | (dbValue[127:120] - refAvg < threshold) ? 1'b1 : 41 | (dbValue[135:128] - refAvg < threshold) ? 1'b1 : 42 | (dbValue[143:136] - refAvg < threshold) ? 1'b1 : 43 | (dbValue[151:144] - refAvg < threshold) ? 1'b1 : 44 | (dbValue[159:152] - refAvg < threshold) ? 1'b1 : 45 | (dbValue[167:160] - refAvg < threshold) ? 1'b1 : 46 | (dbValue[175:168] - refAvg < threshold) ? 1'b1 : 47 | (dbValue[183:176] - refAvg < threshold) ? 1'b1 : 48 | (dbValue[191:184] - refAvg < threshold) ? 1'b1 : 49 | (dbValue[199:192] - refAvg < threshold) ? 1'b1 : 50 | (dbValue[207:200] - refAvg < threshold) ? 1'b1 : 51 | (dbValue[215:208] - refAvg < threshold) ? 1'b1 : 52 | (dbValue[223:216] - refAvg < threshold) ? 1'b1 : 53 | (dbValue[231:224] - refAvg < threshold) ? 1'b1 : 54 | (dbValue[239:232] - refAvg < threshold) ? 1'b1 : 55 | (dbValue[247:240] - refAvg < threshold) ? 1'b1 : 56 | (dbValue[255:248] - refAvg < threshold) ? 1'b1 : 57 | (dbValue[263:256] - refAvg < threshold) ? 1'b1 : 58 | (dbValue[271:264] - refAvg < threshold) ? 1'b1 : 59 | (dbValue[279:272] - refAvg < threshold) ? 1'b1 : 60 | (dbValue[287:280] - refAvg < threshold) ? 1'b1 : 1'b0; 61 | endmodule -------------------------------------------------------------------------------- /Verilog/Mat_Reg.v: -------------------------------------------------------------------------------- 1 | module Mat_Reg (clock, nReset, matReaden, regAddr, FBData, adjFBPixel); 2 | input clock; 3 | input nReset; 4 | input matReaden; // Datapath에 input으로 값을 주기 위한 신호 5 | input [2:0] regAddr; // 레지스터 주소 6 | input [7:0] FBData; // 레지스터에 저장할 값 7 | output [63:0] adjFBPixel; // 인접한 8개의 점의 픽셀 데이터 8 | 9 | reg [7:0] r1, r2, r3, r4, r5, r6, r7, r8; // 인접한 8개 점의 데이터를 저장 10 | 11 | // 주소로부터 저장할 레지스터를 선택하기 위한 디코더로 인접한 8개의 점의 데이터를 저장한다. 12 | wire [7:0] decoder; 13 | assign decoder = 14 | (regAddr == 4'd0) ? 9'd1 : 15 | (regAddr == 4'd1) ? 9'd2 : 16 | (regAddr == 4'd2) ? 9'd4 : 17 | (regAddr == 4'd3) ? 9'd8 : 18 | (regAddr == 4'd4) ? 9'd16 : 19 | (regAddr == 4'd5) ? 9'd32 : 20 | (regAddr == 4'd6) ? 9'd64 : 21 | (regAddr == 4'd7) ? 9'd128 : 8'bx; 22 | 23 | // 레지스터 저장 24 | always @ (posedge clock or negedge nReset) 25 | if (!nReset) 26 | r1 <= 8'bx; 27 | else if (decoder[0]) 28 | r1 <= FBData; 29 | 30 | always @ (posedge clock or negedge nReset) 31 | if (!nReset) 32 | r2 <= 8'bx; 33 | else if (decoder[1]) 34 | r2 <= FBData; 35 | 36 | always @ (posedge clock or negedge nReset) 37 | if (!nReset) 38 | r3 <= 8'bx; 39 | else if (decoder[2]) 40 | r3 <= FBData; 41 | 42 | always @ (posedge clock or negedge nReset) 43 | if (!nReset) 44 | r4 <= 8'bx; 45 | else if (decoder[3]) 46 | r4 <= FBData; 47 | 48 | always @ (posedge clock or negedge nReset) 49 | if (!nReset) 50 | r5 <= 8'bx; 51 | else if (decoder[4]) 52 | r5 <= FBData; 53 | 54 | always @ (posedge clock or negedge nReset) 55 | if (!nReset) 56 | r6 <= 8'bx; 57 | else if (decoder[5]) 58 | r6 <= FBData; 59 | 60 | always @ (posedge clock or negedge nReset) 61 | if (!nReset) 62 | r7 <= 8'bx; 63 | else if (decoder[6]) 64 | r7 <= FBData; 65 | 66 | always @ (posedge clock or negedge nReset) 67 | if (!nReset) 68 | r8 <= 8'bx; 69 | else if (decoder[7]) 70 | r8 <= FBData; 71 | 72 | // matReaden이 1로 셋팅 되면 8개의 인접한 점의 데이터를 한번에 Output으로 보낸다. 73 | assign adjFBPixel = (matReaden) ? {r1, r2, r3, r4, r5, r6, r7, r8} : 64'bx; // 8개 점 74 | endmodule -------------------------------------------------------------------------------- /Verilog/Mat_Testbench.v: -------------------------------------------------------------------------------- 1 | module Mat_Testbench; 2 | reg clock; 3 | reg nReset; 4 | 5 | wire [239:0] position; 6 | wire isMatching; 7 | 8 | always begin 9 | #10 clock = ~clock; 10 | end 11 | 12 | // FAST-9 and SAD Matching Top Module 13 | Accelerator_Top accelerator( 14 | .clock(clock), 15 | .nReset(nReset), 16 | .position(position), 17 | .isMatching(isMatching) 18 | ); 19 | 20 | initial begin 21 | clock = 1'b0; 22 | nReset = 1'b1; 23 | #100 nReset = 1'b0; 24 | #100 nReset = 1'b1; 25 | 26 | #10000000 $finish; 27 | end 28 | endmodule -------------------------------------------------------------------------------- /Verilog/Mat_Top.v: -------------------------------------------------------------------------------- 1 | module Mat_Top (clock, nReset, refAddr, isFeature, position, isMatching); 2 | input clock; 3 | input nReset; 4 | input [14:0] refAddr; // 기준점 5 | input [7:0] isFeature; // 특징점 확인 6 | output [239:0] position; // 매칭된 유효 특징점 주소 7 | output isMatching; // 매칭 결과 8 | 9 | wire [2:0] adjNumber; // 8개의 인접한 점 10 | wire [2:0] regAddr; // 레지스터 주소 11 | wire [14:0] FBAddr; // Frame Buffer 주소 12 | wire [7:0] FBData; // Frame Buffer Output 데이터 13 | wire [63:0] adjFBPixel; // 인접한 8개의 점 데이터 14 | wire [287:0] dbValue; // DB 데이터 15 | wire [3:0] posAddr; // 레지스터 주소 16 | wire matPoint; // 매칭 여부 17 | 18 | // Controller, 특징점과 인접한 8개의 주소를 얻어, 레지스터에 저장하는 과정을 제어 19 | Mat_Controller controller( 20 | .clock(clock), 21 | .nReset(nReset), 22 | .refAddr(refAddr), 23 | .adjNumber(adjNumber), 24 | .regAddr(regAddr), 25 | .matReaden(matReaden) 26 | ); 27 | 28 | // 기준점으로부터 인접한 8개의 점의 주소를 계산 29 | Mat_AddrCal addrCal( 30 | .refAddr(refAddr), 31 | .adjNumber(adjNumber), 32 | .FBAddr(FBAddr) 33 | ); 34 | 35 | // 인접한 8개의 픽셀 값을 저장 36 | Mat_Reg mat_reg( 37 | .clock(clock), 38 | .nReset(nReset), 39 | .matReaden(matReaden), 40 | .regAddr(regAddr), 41 | .FBData(FBData), 42 | .adjFBPixel(adjFBPixel) 43 | ); 44 | 45 | // DB의 데이터와 레지스터의 저장된 특징점 주변의 평균값의 1:N 비교를 통해 매칭여부 확인 46 | Mat_Datapath datapath( 47 | .adjFBPixel(adjFBPixel), 48 | .dbValue(dbValue), 49 | .matPoint(matPoint) 50 | ); 51 | 52 | // 실제 이미지의 특징점의 평균값이 저장 53 | DBMEM dbmem( 54 | .matReaden(matReaden), 55 | .dbValue(dbValue) 56 | ); 57 | 58 | // 최종적으로 매칭된 특징점의 주소를 저장 59 | Addr_Reg addr_reg( 60 | .refAddr(refAddr), 61 | .posAddr(posAddr), 62 | .posReaden(posReaden), 63 | .position(position), 64 | .isMatching(isMatching) 65 | ); 66 | 67 | // 매칭된 특징점의 개수를 센다. 68 | Mat_Counter counter( 69 | .clock(clock), 70 | .nReset(nReset), 71 | .matPoint(matPoint), 72 | .isFeature(isFeature), 73 | .posAddr(posAddr), 74 | .posReaden(posReaden) 75 | ); 76 | 77 | // Freme Buffer 78 | Buffer buffer( 79 | .clock(clock), 80 | .address(FBAddr), 81 | .data(8'bx), 82 | .wren(1'b0), 83 | .q(FBData) 84 | ); 85 | endmodule -------------------------------------------------------------------------------- /Verilog/NMS_AddrCal.v: -------------------------------------------------------------------------------- 1 | `define COLUMNS 8'd180 2 | `define ROWS 8'd120 3 | 4 | module NMS_AddrCal (refAddr, adjNumber, scoreAddr); 5 | input [14:0] refAddr; // 기준점 6 | input [3:0] adjNumber; // 인접한 8개의 점 번호 7 | output [14:0] scoreAddr; // Score Memory의 Input 주소 8 | 9 | assign scoreAddr = 10 | (adjNumber == 4'd15) ? refAddr : // 현재 Score Memory Addr 11 | (adjNumber == 4'd0) ? refAddr - 182 : // 기준점 12 | (adjNumber == 4'd1) ? refAddr - 182 - `COLUMNS : // 1 13 | (adjNumber == 4'd2) ? refAddr - 182 - `COLUMNS + 1 : // 2 14 | (adjNumber == 4'd3) ? refAddr - 182 + 1 : // 3 15 | (adjNumber == 4'd4) ? refAddr - 182 + `COLUMNS + 1 : // 4 16 | (adjNumber == 4'd5) ? refAddr - 182 + `COLUMNS : // 5 17 | (adjNumber == 4'd6) ? refAddr - 182 + `COLUMNS - 1 : // 6 18 | (adjNumber == 4'd7) ? refAddr - 182 - 1 : // 7 19 | (adjNumber == 4'd8) ? refAddr - 182 - `COLUMNS - 1 : 15'bx; // 8 20 | endmodule -------------------------------------------------------------------------------- /Verilog/NMS_Controller.v: -------------------------------------------------------------------------------- 1 | `define INIT 5'd20 2 | `define S0 5'd0 3 | `define S1 5'd1 4 | `define S2 5'd2 5 | `define S3 5'd3 6 | `define S4 5'd4 7 | `define S5 5'd5 8 | `define S6 5'd6 9 | `define S7 5'd7 10 | `define S8 5'd8 11 | `define S9 5'd9 12 | `define S10 5'd10 13 | `define S11 5'd11 14 | `define S12 5'd12 15 | `define S13 5'd13 16 | `define S14 5'd14 17 | `define S15 5'd15 18 | `define S16 5'd16 19 | `define S17 5'd17 20 | `define S18 5'd18 21 | `define S19 5'd19 22 | 23 | module NMS_Controller (clock, nReset, refAddr, adjNumber, regAddr, readen); 24 | input clock; 25 | input nReset; 26 | input [14:0] refAddr; // 현재 주소 27 | output [3:0] adjNumber; // 인접한 8개의 점의 번호 28 | output [3:0] regAddr; // 레지스터 주소 29 | output readen; // datapath에 보낼 읽기 신호 30 | 31 | reg [3:0] adjNumber; // 8개의 점 Index 32 | reg [3:0] regAddr; // 레지스터 주소 33 | reg readen; // Datapath가 수행될 수 있도록 하는 enable 신호 34 | 35 | reg [4:0] curState, nextState; // 상태 변화 36 | 37 | // 클락이 상승할 때마다 현재 상태에서 다음상태로 변화 38 | always @(posedge clock or negedge nReset) begin 39 | if (!nReset) 40 | curState <= `INIT; 41 | else 42 | curState <= nextState; 43 | end 44 | 45 | // FSM 46 | always @(curState or refAddr) begin 47 | casex (curState) 48 | `INIT: begin 49 | if (refAddr < 15'd904) begin 50 | nextState = `INIT; 51 | readen = 1'b0; 52 | end 53 | else begin 54 | nextState = `S0; 55 | readen = 1'b0; 56 | end 57 | end 58 | 59 | `S0: begin 60 | nextState = `S1; 61 | adjNumber = `S0; 62 | regAddr = 4'bx; 63 | end 64 | 65 | `S1: begin 66 | nextState = `S2; 67 | adjNumber = `S1; 68 | regAddr = 4'bx; 69 | end 70 | 71 | `S2: begin 72 | nextState = `S3; 73 | adjNumber = `S2; 74 | regAddr = `S0; 75 | end 76 | 77 | `S3: begin 78 | nextState = `S4; 79 | adjNumber = `S3; 80 | regAddr = `S1; 81 | end 82 | 83 | `S4: begin 84 | nextState = `S5; 85 | adjNumber = `S4; 86 | regAddr = `S2; 87 | end 88 | 89 | `S5: begin 90 | nextState = `S6; 91 | adjNumber = `S5; 92 | regAddr = `S3; 93 | end 94 | 95 | `S6: begin 96 | nextState = `S7; 97 | adjNumber = `S6; 98 | regAddr = `S4; 99 | end 100 | 101 | `S7: begin 102 | nextState = `S8; 103 | adjNumber = `S7; 104 | regAddr = `S5; 105 | end 106 | 107 | `S8: begin 108 | nextState = `S9; 109 | adjNumber = `S8; 110 | regAddr = `S6; 111 | end 112 | 113 | `S9: begin 114 | nextState = `S10; 115 | adjNumber = 4'bx; 116 | regAddr = `S7; 117 | end 118 | 119 | `S10: begin 120 | nextState = `S11; 121 | adjNumber = 4'bx; 122 | regAddr = `S8; 123 | end 124 | 125 | `S11: begin 126 | nextState = `S12; 127 | adjNumber = 4'bx; 128 | regAddr = 4'bx; 129 | end 130 | 131 | `S12: begin 132 | nextState = `S13; 133 | adjNumber = 4'bx; 134 | regAddr = 4'bx; 135 | end 136 | 137 | `S13: begin 138 | nextState = `S14; 139 | adjNumber = 4'bx; 140 | regAddr = 4'bx; 141 | end 142 | 143 | `S14: begin 144 | nextState = `S15; 145 | adjNumber = 4'bx; 146 | regAddr = 4'bx; 147 | end 148 | 149 | `S15: begin 150 | nextState = `S16; 151 | adjNumber = 4'bx; 152 | regAddr = 4'bx; 153 | end 154 | 155 | `S16: begin 156 | nextState = `S17; 157 | adjNumber = 4'bx; 158 | regAddr = 4'bx; 159 | end 160 | 161 | `S17: begin 162 | nextState = `S18; 163 | adjNumber = 4'bx; 164 | regAddr = 4'bx; 165 | end 166 | 167 | `S18: begin 168 | nextState = `S19; 169 | adjNumber = 4'bx; 170 | regAddr = 4'bx; 171 | end 172 | 173 | `S19: begin 174 | nextState = `INIT; 175 | adjNumber = 4'd15; 176 | regAddr = 4'bx; 177 | readen = 1'b1; 178 | end 179 | endcase 180 | end 181 | endmodule -------------------------------------------------------------------------------- /Verilog/NMS_Datapath.v: -------------------------------------------------------------------------------- 1 | module NMS_Datapath (refScore, adjScore, refAddr, outAddr, outPixel); 2 | input [7:0] refScore; // 기준점 Score 3 | input [63:0] adjScore; // 인접한 8개의 점 Score 4 | input [14:0] refAddr; // 현재 주소 5 | output [14:0] outAddr; // 최종 Corner 주소 6 | output [7:0] outPixel; // 최종 Corner 데이터 7 | 8 | // 인접한 8개의 점과 비교하여 기준점의 Score가 모든 인접한 점보다 크면 0xff로 최종 Corner 출력 9 | assign outPixel = 10 | (refScore == 8'd0) ? 8'bx : // Corner가 아닌 경우 11 | (refScore < adjScore[63:56]) ? 8'bx : 12 | (refScore < adjScore[55:48]) ? 8'bx : 13 | (refScore < adjScore[47:40]) ? 8'bx : 14 | (refScore < adjScore[39:32]) ? 8'bx : 15 | (refScore < adjScore[31:24]) ? 8'bx : 16 | (refScore < adjScore[23:16]) ? 8'bx : 17 | (refScore < adjScore[15:8]) ? 8'bx : 18 | (refScore < adjScore[7:0]) ? 8'bx : 8'hff; 19 | 20 | // 최종적으로 결정된 코너의 주소 21 | assign outAddr = (outPixel == 8'hff) ? refAddr - 182 : 15'bx; 22 | endmodule -------------------------------------------------------------------------------- /Verilog/NMS_Reg.v: -------------------------------------------------------------------------------- 1 | module NMS_Reg (clock, nReset, readen, regAddr, scoreData, refScore, adjScore); 2 | input clock; 3 | input nReset; 4 | input readen; // Datapath에 input으로 값을 주기 위한 신호 5 | input [3:0] regAddr; // 레지스터 주소 6 | input [7:0] scoreData; // 레지스터에 저장할 값 7 | output [7:0] refScore; // 기준점 Score 8 | output [63:0] adjScore; // 인접한 8개의 점 Score 9 | 10 | reg [7:0] refPoint; // 기준점 데이터를 저장 11 | reg [7:0] r1, r2, r3, r4, r5, r6, r7, r8; // 인접한 8개 점의 데이터를 저장 12 | 13 | // 주소로부터 저장할 레지스터를 선택하기 위한 디코더로 기준점의 데이터와, 인접한 8개의 점의 데이터를 저장한다. 14 | wire [8:0] decoder; 15 | assign decoder = 16 | (regAddr == 4'd0) ? 9'd1 : 17 | (regAddr == 4'd1) ? 9'd2 : 18 | (regAddr == 4'd2) ? 9'd4 : 19 | (regAddr == 4'd3) ? 9'd8 : 20 | (regAddr == 4'd4) ? 9'd16 : 21 | (regAddr == 4'd5) ? 9'd32 : 22 | (regAddr == 4'd6) ? 9'd64 : 23 | (regAddr == 4'd7) ? 9'd128 : 24 | (regAddr == 4'd8) ? 9'd256 : 9'bx; 25 | 26 | always @ (posedge clock or negedge nReset) 27 | if (!nReset) 28 | refPoint <= 8'bx; 29 | else if (decoder[0]) 30 | refPoint <= scoreData; 31 | 32 | always @ (posedge clock or negedge nReset) 33 | if (!nReset) 34 | r1 <= 8'bx; 35 | else if (decoder[1]) 36 | r1 <= scoreData; 37 | 38 | always @ (posedge clock or negedge nReset) 39 | if (!nReset) 40 | r2 <= 8'bx; 41 | else if (decoder[2]) 42 | r2 <= scoreData; 43 | 44 | always @ (posedge clock or negedge nReset) 45 | if (!nReset) 46 | r3 <= 8'bx; 47 | else if (decoder[3]) 48 | r3 <= scoreData; 49 | 50 | always @ (posedge clock or negedge nReset) 51 | if (!nReset) 52 | r4 <= 8'bx; 53 | else if (decoder[4]) 54 | r4 <= scoreData; 55 | 56 | always @ (posedge clock or negedge nReset) 57 | if (!nReset) 58 | r5 <= 8'bx; 59 | else if (decoder[5]) 60 | r5 <= scoreData; 61 | 62 | always @ (posedge clock or negedge nReset) 63 | if (!nReset) 64 | r6 <= 8'bx; 65 | else if (decoder[6]) 66 | r6 <= scoreData; 67 | 68 | always @ (posedge clock or negedge nReset) 69 | if (!nReset) 70 | r7 <= 8'bx; 71 | else if (decoder[7]) 72 | r7 <= scoreData; 73 | 74 | always @ (posedge clock or negedge nReset) 75 | if (!nReset) 76 | r8 <= 8'bx; 77 | else if (decoder[8]) 78 | r8 <= scoreData; 79 | 80 | // readen이 1로 셋팅 되면 기준점 데이터와, 8개의 인접한 점의 데이터를 한번에 Output으로 보낸다. 81 | assign refScore = (readen) ? refPoint : 8'bx; // 기준점 82 | assign adjScore = (readen) ? {r1, r2, r3, r4, r5, r6, r7, r8} : 64'bx; // 8개 점 83 | endmodule -------------------------------------------------------------------------------- /Verilog/NMS_Testbench.v: -------------------------------------------------------------------------------- 1 | module NMS_Testbench; 2 | reg clock; 3 | reg nReset; 4 | 5 | wire [14:0] outAddr; 6 | wire [7:0] outPixel; 7 | 8 | always begin 9 | #10 clock = ~clock; 10 | if (clock && (outPixel == 8'hff)) // 최종적으로 결정된 Corner의 주소와 값 출력 11 | $display("outAddr: %d, outPixel: %h", outAddr, outPixel); 12 | end 13 | 14 | // FAST-9 Alogrithm Top Module 15 | FAST9_Top fast9( 16 | .clock(clock), 17 | .nResetedd(nReset), 18 | .outAddr(outAddr), 19 | .outPixel(outPixel) 20 | ); 21 | 22 | initial begin 23 | clock = 1'b0; 24 | nReset = 1'b1; 25 | #100 nReset = 1'b0; 26 | #100 nReset = 1'b1; 27 | 28 | #10000000 $finish; 29 | end 30 | endmodule -------------------------------------------------------------------------------- /Verilog/NMS_Top.v: -------------------------------------------------------------------------------- 1 | module NMS_Top (clock, nReset, refAddr, refPixel, scoreData, scoreAddr, outAddr, outPixel); 2 | input clock; 3 | input nReset; 4 | input [14:0] refAddr; // 기준점 주소 5 | input [7:0] refPixel; // 기준점 데이터 6 | input [7:0] scoreData; // Score Memory에 저장할 데이터 7 | output [14:0] scoreAddr; // Score Memoery 주소 8 | output [14:0] outAddr; // 최종적으로 결정된 코너의 주소 9 | output [7:0] outPixel; // 코너 여부를 확인하여 최종적으로 결정된 기준점의 데이터 10 | 11 | wire [3:0] adjNumber; // 1~8개의 인접한 점 번호 12 | wire [3:0] regAddr; // 레지스터 주소 13 | wire [7:0] refScore; // 기준점 Score 14 | wire [63:0] adjScore; // 인접한 8개의 점 Score 15 | 16 | // Controller, 기준점과 인접한 8개의 주소를 얻어, 레지스터에 저장하는 과정을 제어 17 | NMS_Controller controller( 18 | .clock(clock), 19 | .nReset(nReset), 20 | .refAddr(refAddr), 21 | .adjNumber(adjNumber), 22 | .regAddr(regAddr), 23 | .readen(readen) 24 | ); 25 | 26 | // 기준점으로 부터 인접한 8개의 점을 계산 27 | NMS_AddrCal addrCal( 28 | .refAddr(refAddr), 29 | .adjNumber(adjNumber), 30 | .scoreAddr(scoreAddr) 31 | ); 32 | 33 | // 기준점과 인접한 8개의 점을 저장할 레지스터 파일 34 | NMS_Reg nms_reg( 35 | .clock(clock), 36 | .nReset(nReset), 37 | .readen(readen), 38 | .regAddr(regAddr), 39 | .scoreData(scoreData), 40 | .refScore(refScore), 41 | .adjScore(adjScore) 42 | ); 43 | 44 | // 레지스터에 저장된 기준점과 인접한 8개의 점의 데이터를 이용하여 최종적으로 코너를 결정 45 | NMS_Datapath datapath( 46 | .refScore(refScore), 47 | .adjScore(adjScore), 48 | .refAddr(refAddr), 49 | .outAddr(outAddr), 50 | .outPixel(outPixel) 51 | ); 52 | endmodule -------------------------------------------------------------------------------- /Verilog/SRAM.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "SRAM.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "SRAM_bb.v"] 5 | -------------------------------------------------------------------------------- /Verilog/SRAM.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: SRAM.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.1.0 Build 162 10/23/2013 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module SRAM ( 40 | address, 41 | clock, 42 | data, 43 | wren, 44 | q); 45 | 46 | input [14:0] address; 47 | input clock; 48 | input [7:0] data; 49 | input wren; 50 | output [7:0] q; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_off 53 | `endif 54 | tri1 clock; 55 | `ifndef ALTERA_RESERVED_QIS 56 | // synopsys translate_on 57 | `endif 58 | 59 | wire [7:0] sub_wire0; 60 | wire [7:0] q = sub_wire0[7:0]; 61 | 62 | altsyncram altsyncram_component ( 63 | .address_a (address), 64 | .clock0 (clock), 65 | .data_a (data), 66 | .wren_a (wren), 67 | .q_a (sub_wire0), 68 | .aclr0 (1'b0), 69 | .aclr1 (1'b0), 70 | .address_b (1'b1), 71 | .addressstall_a (1'b0), 72 | .addressstall_b (1'b0), 73 | .byteena_a (1'b1), 74 | .byteena_b (1'b1), 75 | .clock1 (1'b1), 76 | .clocken0 (1'b1), 77 | .clocken1 (1'b1), 78 | .clocken2 (1'b1), 79 | .clocken3 (1'b1), 80 | .data_b (1'b1), 81 | .eccstatus (), 82 | .q_b (), 83 | .rden_a (1'b1), 84 | .rden_b (1'b1), 85 | .wren_b (1'b0)); 86 | defparam 87 | altsyncram_component.clock_enable_input_a = "BYPASS", 88 | altsyncram_component.clock_enable_output_a = "BYPASS", 89 | altsyncram_component.init_file = "untitled.mif", 90 | altsyncram_component.intended_device_family = "Cyclone IV E", 91 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 92 | altsyncram_component.lpm_type = "altsyncram", 93 | altsyncram_component.numwords_a = 21600, 94 | altsyncram_component.operation_mode = "SINGLE_PORT", 95 | altsyncram_component.outdata_aclr_a = "NONE", 96 | altsyncram_component.outdata_reg_a = "CLOCK0", 97 | altsyncram_component.power_up_uninitialized = "FALSE", 98 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 99 | altsyncram_component.widthad_a = 15, 100 | altsyncram_component.width_a = 8, 101 | altsyncram_component.width_byteena_a = 1; 102 | 103 | 104 | endmodule 105 | 106 | // ============================================================ 107 | // CNX file retrieval info 108 | // ============================================================ 109 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 110 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 111 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 112 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 113 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 114 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 115 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 116 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 117 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 118 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 119 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 120 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 121 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 122 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 123 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 124 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 125 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 126 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 127 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 128 | // Retrieval info: PRIVATE: MIFfilename STRING "untitled.mif" 129 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "21600" 130 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 131 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 132 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 133 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 134 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 135 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 136 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 137 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 138 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 139 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "15" 140 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 141 | // Retrieval info: PRIVATE: rden NUMERIC "0" 142 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 143 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 144 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 145 | // Retrieval info: CONSTANT: INIT_FILE STRING "untitled.mif" 146 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 147 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 148 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 149 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "21600" 150 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 151 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 152 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 153 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 154 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 155 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" 156 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 157 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 158 | // Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]" 159 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 160 | // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 161 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 162 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 163 | // Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0 164 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 165 | // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 166 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 167 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 168 | // Retrieval info: GEN_FILE: TYPE_NORMAL SRAM.v TRUE 169 | // Retrieval info: GEN_FILE: TYPE_NORMAL SRAM.inc FALSE 170 | // Retrieval info: GEN_FILE: TYPE_NORMAL SRAM.cmp FALSE 171 | // Retrieval info: GEN_FILE: TYPE_NORMAL SRAM.bsf FALSE 172 | // Retrieval info: GEN_FILE: TYPE_NORMAL SRAM_inst.v FALSE 173 | // Retrieval info: GEN_FILE: TYPE_NORMAL SRAM_bb.v TRUE 174 | // Retrieval info: LIB_FILE: altera_mf 175 | -------------------------------------------------------------------------------- /Verilog/SRAM_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: SRAM.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.1.0 Build 162 10/23/2013 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2013 Altera Corporation 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, Altera MegaCore Function License 28 | //Agreement, or other applicable license agreement, including, 29 | //without limitation, that your use is for the sole purpose of 30 | //programming logic devices manufactured by Altera and sold by 31 | //Altera or its authorized distributors. Please refer to the 32 | //applicable agreement for further details. 33 | 34 | module SRAM ( 35 | address, 36 | clock, 37 | data, 38 | wren, 39 | q); 40 | 41 | input [14:0] address; 42 | input clock; 43 | input [7:0] data; 44 | input wren; 45 | output [7:0] q; 46 | `ifndef ALTERA_RESERVED_QIS 47 | // synopsys translate_off 48 | `endif 49 | tri1 clock; 50 | `ifndef ALTERA_RESERVED_QIS 51 | // synopsys translate_on 52 | `endif 53 | 54 | endmodule 55 | 56 | // ============================================================ 57 | // CNX file retrieval info 58 | // ============================================================ 59 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 60 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 61 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 62 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 63 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 64 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 65 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 66 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 67 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 68 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 69 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 70 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 71 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 72 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 73 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 74 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 75 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 76 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 77 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 78 | // Retrieval info: PRIVATE: MIFfilename STRING "untitled.mif" 79 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "21600" 80 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 81 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 82 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 83 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 84 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 85 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 86 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 87 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 88 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 89 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "15" 90 | // Retrieval info: PRIVATE: WidthData NUMERIC "8" 91 | // Retrieval info: PRIVATE: rden NUMERIC "0" 92 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 93 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 94 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 95 | // Retrieval info: CONSTANT: INIT_FILE STRING "untitled.mif" 96 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 97 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 98 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 99 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "21600" 100 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 101 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 102 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 103 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 104 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 105 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" 106 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" 107 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 108 | // Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]" 109 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 110 | // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" 111 | // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" 112 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 113 | // Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0 114 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 115 | // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 116 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 117 | // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 118 | // Retrieval info: GEN_FILE: TYPE_NORMAL SRAM.v TRUE 119 | // Retrieval info: GEN_FILE: TYPE_NORMAL SRAM.inc FALSE 120 | // Retrieval info: GEN_FILE: TYPE_NORMAL SRAM.cmp FALSE 121 | // Retrieval info: GEN_FILE: TYPE_NORMAL SRAM.bsf FALSE 122 | // Retrieval info: GEN_FILE: TYPE_NORMAL SRAM_inst.v FALSE 123 | // Retrieval info: GEN_FILE: TYPE_NORMAL SRAM_bb.v TRUE 124 | // Retrieval info: LIB_FILE: altera_mf 125 | -------------------------------------------------------------------------------- /Verilog/Testbench_SramTest.v: -------------------------------------------------------------------------------- 1 | module Testbench_SramTest; 2 | reg clock; 3 | reg wren; 4 | reg [14:0] address; 5 | reg [7:0] data; 6 | wire [7:0] read; 7 | 8 | always begin 9 | #50 clock = ~clock; 10 | $display($time, "%d : %b : %h", read, read, read); 11 | end 12 | 13 | always @ (posedge clock) 14 | address <= address + 1; 15 | 16 | SRAM sram( 17 | .clock(clock), 18 | .address(address), 19 | .data(data), 20 | .wren(wren), 21 | .q(read) 22 | ); 23 | 24 | initial begin 25 | wren = 1'b0; 26 | clock = 1'b0; 27 | address = 15'b0; 28 | data = 8'b00110000; 29 | 30 | #21600 $finish; 31 | end 32 | endmodule -------------------------------------------------------------------------------- /Verilog/fast9.pti_db_list.ddb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ISKU/FAST9-Accelerator/136d8b2e53ddec6c9cf946b9bb263880e8ca04d7/Verilog/fast9.pti_db_list.ddb -------------------------------------------------------------------------------- /Verilog/fast9.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 21 | # Date created = 18:44:37 April 28, 2017 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.1" 26 | DATE = "18:44:37 April 28, 2017" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "fast9" 31 | -------------------------------------------------------------------------------- /Verilog/fast9.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 21 | # Date created = 18:44:37 April 28, 2017 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # fast9_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone IV GX" 40 | set_global_assignment -name DEVICE auto 41 | set_global_assignment -name TOP_LEVEL_ENTITY Accelerator_Top 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:44:37 APRIL 28, 2017" 44 | set_global_assignment -name LAST_QUARTUS_VERSION 13.1 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" 47 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation 48 | set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation 49 | set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH Mat_Testbench -section_id eda_simulation 50 | set_global_assignment -name VERILOG_FILE FS_Top.v 51 | set_global_assignment -name VERILOG_FILE FS_Datapath.v 52 | set_global_assignment -name QIP_FILE FS_ScoreMem.qip 53 | set_global_assignment -name VERILOG_FILE FD_Top.v 54 | set_global_assignment -name VERILOG_FILE FD_Reg.v 55 | set_global_assignment -name VERILOG_FILE FD_Datapath.v 56 | set_global_assignment -name VERILOG_FILE FD_Controller.v 57 | set_global_assignment -name VERILOG_FILE FD_AddrCal.v 58 | set_global_assignment -name VERILOG_FILE FD_Testbench.v 59 | set_global_assignment -name QIP_FILE SRAM.qip 60 | set_global_assignment -name VERILOG_FILE FS_Testbench.v 61 | set_global_assignment -name VERILOG_FILE FAST9_Top.v 62 | set_global_assignment -name VERILOG_FILE NMS_Top.v 63 | set_global_assignment -name VERILOG_FILE NMS_Controller.v 64 | set_global_assignment -name VERILOG_FILE NMS_AddrCal.v 65 | set_global_assignment -name VERILOG_FILE NMS_Reg.v 66 | set_global_assignment -name VERILOG_FILE NMS_Datapath.v 67 | set_global_assignment -name VERILOG_FILE NMS_Testbench.v 68 | set_global_assignment -name VERILOG_FILE Mat_Controller.v 69 | set_global_assignment -name VERILOG_FILE Mat_AddrCal.v 70 | set_global_assignment -name VERILOG_FILE Mat_Reg.v 71 | set_global_assignment -name VERILOG_FILE Mat_Datapath.v 72 | set_global_assignment -name VERILOG_FILE Mat_Counter.v 73 | set_global_assignment -name VERILOG_FILE Addr_Reg.v 74 | set_global_assignment -name VERILOG_FILE DBMEM.v 75 | set_global_assignment -name VERILOG_FILE Accelerator_Top.v 76 | set_global_assignment -name VERILOG_FILE Mat_Top.v 77 | set_global_assignment -name QIP_FILE Buffer.qip 78 | set_global_assignment -name VERILOG_FILE Mat_Testbench.v 79 | set_global_assignment -name EDA_TEST_BENCH_NAME Mat_Testbench -section_id eda_simulation 80 | set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id Mat_Testbench 81 | set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Mat_Testbench -section_id Mat_Testbench 82 | set_global_assignment -name EDA_TEST_BENCH_FILE Mat_Testbench.v -section_id Mat_Testbench 83 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 84 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 85 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 86 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /Verilog/fast9.tis_db_list.ddb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ISKU/FAST9-Accelerator/136d8b2e53ddec6c9cf946b9bb263880e8ca04d7/Verilog/fast9.tis_db_list.ddb -------------------------------------------------------------------------------- /Verilog/fast9_assignment_defaults.qdf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus Prime License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 22 | # Date created = 13:40:00 May 26, 2017 23 | # 24 | # -------------------------------------------------------------------------- # 25 | # 26 | # Note: 27 | # 28 | # 1) Do not modify this file. This file was generated 29 | # automatically by the Quartus Prime software and is used 30 | # to preserve global assignments across Quartus Prime versions. 31 | # 32 | # -------------------------------------------------------------------------- # 33 | 34 | set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off 35 | set_global_assignment -name IP_COMPONENT_INTERNAL Off 36 | set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On 37 | set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off 38 | set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off 39 | set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db 40 | set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off 41 | set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off 42 | set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off 43 | set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off 44 | set_global_assignment -name HC_OUTPUT_DIR hc_output 45 | set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off 46 | set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off 47 | set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On 48 | set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off 49 | set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" 50 | set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On 51 | set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On 52 | set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off 53 | set_global_assignment -name REVISION_TYPE Base 54 | set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" 55 | set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On 56 | set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On 57 | set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On 58 | set_global_assignment -name DO_COMBINED_ANALYSIS Off 59 | set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off 60 | set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off 61 | set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off 62 | set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off 63 | set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On 64 | set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On 65 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix 10" 66 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V" 67 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10" 68 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" 69 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E" 70 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10" 71 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V" 72 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V" 73 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ" 74 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" 75 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" 76 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ" 77 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" 78 | set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V" 79 | set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off 80 | set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix 10" 81 | set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" 82 | set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" 83 | set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" 84 | set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" 85 | set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" 86 | set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" 87 | set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" 88 | set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" 89 | set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" 90 | set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" 91 | set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" 92 | set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" 93 | set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" 94 | set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 95 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix 10" 96 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V" 97 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10" 98 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E" 99 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" 100 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10" 101 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V" 102 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V" 103 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ" 104 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" 105 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" 106 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ" 107 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX" 108 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V" 109 | set_global_assignment -name OPTIMIZATION_MODE Balanced 110 | set_global_assignment -name ALLOW_REGISTER_MERGING On 111 | set_global_assignment -name ALLOW_REGISTER_DUPLICATION On 112 | set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Stratix 10" 113 | set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V" 114 | set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10" 115 | set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV" 116 | set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E" 117 | set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10" 118 | set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V" 119 | set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V" 120 | set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ" 121 | set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II" 122 | set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX" 123 | set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ" 124 | set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX" 125 | set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V" 126 | set_global_assignment -name MUX_RESTRUCTURE Auto 127 | set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off 128 | set_global_assignment -name ENABLE_IP_DEBUG Off 129 | set_global_assignment -name SAVE_DISK_SPACE On 130 | set_global_assignment -name DISABLE_OCP_HW_EVAL Off 131 | set_global_assignment -name DEVICE_FILTER_PACKAGE Any 132 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any 133 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any 134 | set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" 135 | set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 136 | set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 137 | set_global_assignment -name FAMILY -value "Cyclone V" 138 | set_global_assignment -name TRUE_WYSIWYG_FLOW Off 139 | set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off 140 | set_global_assignment -name STATE_MACHINE_PROCESSING Auto 141 | set_global_assignment -name SAFE_STATE_MACHINE Off 142 | set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On 143 | set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On 144 | set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off 145 | set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 146 | set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 147 | set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On 148 | set_global_assignment -name PARALLEL_SYNTHESIS On 149 | set_global_assignment -name DSP_BLOCK_BALANCING Auto 150 | set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" 151 | set_global_assignment -name NOT_GATE_PUSH_BACK On 152 | set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On 153 | set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off 154 | set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On 155 | set_global_assignment -name IGNORE_CARRY_BUFFERS Off 156 | set_global_assignment -name IGNORE_CASCADE_BUFFERS Off 157 | set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off 158 | set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off 159 | set_global_assignment -name IGNORE_LCELL_BUFFERS Off 160 | set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO 161 | set_global_assignment -name IGNORE_SOFT_BUFFERS On 162 | set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off 163 | set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off 164 | set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On 165 | set_global_assignment -name AUTO_GLOBAL_OE_MAX On 166 | set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On 167 | set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off 168 | set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut 169 | set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced 170 | set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced 171 | set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced 172 | set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced 173 | set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced 174 | set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced 175 | set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed 176 | set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced 177 | set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area 178 | set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area 179 | set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area 180 | set_global_assignment -name ALLOW_XOR_GATE_USAGE On 181 | set_global_assignment -name AUTO_LCELL_INSERTION On 182 | set_global_assignment -name CARRY_CHAIN_LENGTH 48 183 | set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 184 | set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 185 | set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 186 | set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 187 | set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 188 | set_global_assignment -name CASCADE_CHAIN_LENGTH 2 189 | set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 190 | set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 191 | set_global_assignment -name AUTO_CARRY_CHAINS On 192 | set_global_assignment -name AUTO_CASCADE_CHAINS On 193 | set_global_assignment -name AUTO_PARALLEL_EXPANDERS On 194 | set_global_assignment -name AUTO_OPEN_DRAIN_PINS On 195 | set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off 196 | set_global_assignment -name AUTO_ROM_RECOGNITION On 197 | set_global_assignment -name AUTO_RAM_RECOGNITION On 198 | set_global_assignment -name AUTO_DSP_RECOGNITION On 199 | set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto 200 | set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto 201 | set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On 202 | set_global_assignment -name STRICT_RAM_RECOGNITION Off 203 | set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On 204 | set_global_assignment -name FORCE_SYNCH_CLEAR Off 205 | set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On 206 | set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off 207 | set_global_assignment -name AUTO_RESOURCE_SHARING Off 208 | set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off 209 | set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off 210 | set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off 211 | set_global_assignment -name MAX7000_FANIN_PER_CELL 100 212 | set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On 213 | set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" 214 | set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" 215 | set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" 216 | set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off 217 | set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off 218 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" 219 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix 10" 220 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" 221 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" 222 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" 223 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" 224 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" 225 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" 226 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" 227 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" 228 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" 229 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" 230 | set_global_assignment -name REPORT_PARAMETER_SETTINGS On 231 | set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On 232 | set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On 233 | set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off 234 | set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix 10" 235 | set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" 236 | set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" 237 | set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" 238 | set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" 239 | set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" 240 | set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" 241 | set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" 242 | set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" 243 | set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" 244 | set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" 245 | set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" 246 | set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" 247 | set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" 248 | set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" 249 | set_global_assignment -name HDL_MESSAGE_LEVEL Level2 250 | set_global_assignment -name USE_HIGH_SPEED_ADDER Auto 251 | set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 252 | set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 253 | set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off 254 | set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 255 | set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 256 | set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On 257 | set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off 258 | set_global_assignment -name BLOCK_DESIGN_NAMING Auto 259 | set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off 260 | set_global_assignment -name SYNTHESIS_EFFORT Auto 261 | set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On 262 | set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off 263 | set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium 264 | set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto 265 | set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" 266 | set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix 10" 267 | set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" 268 | set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" 269 | set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" 270 | set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" 271 | set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" 272 | set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" 273 | set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" 274 | set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" 275 | set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" 276 | set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" 277 | set_global_assignment -name MAX_LABS "-1 (Unlimited)" 278 | set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On 279 | set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" 280 | set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On 281 | set_global_assignment -name PRPOF_ID Off 282 | set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off 283 | set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off 284 | set_global_assignment -name AUTO_MERGE_PLLS On 285 | set_global_assignment -name IGNORE_MODE_FOR_MERGE Off 286 | set_global_assignment -name TXPMA_SLEW_RATE Low 287 | set_global_assignment -name ADCE_ENABLED Auto 288 | set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal 289 | set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off 290 | set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 291 | set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 292 | set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 293 | set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off 294 | set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off 295 | set_global_assignment -name DEVICE AUTO 296 | set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off 297 | set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off 298 | set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On 299 | set_global_assignment -name ENABLE_NCEO_OUTPUT Off 300 | set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" 301 | set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" 302 | set_global_assignment -name STRATIXIII_UPDATE_MODE Standard 303 | set_global_assignment -name STRATIX_UPDATE_MODE Standard 304 | set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" 305 | set_global_assignment -name CVP_MODE Off 306 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Active Serial x1" -family "Stratix 10" 307 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" 308 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" 309 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" 310 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" 311 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" 312 | set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" 313 | set_global_assignment -name USE_CONF_DONE AUTO 314 | set_global_assignment -name USE_PWRMGT_SCL AUTO 315 | set_global_assignment -name USE_PWRMGT_SDA AUTO 316 | set_global_assignment -name USE_PWRMGT_ALERT AUTO 317 | set_global_assignment -name USE_INIT_DONE AUTO 318 | set_global_assignment -name USE_CVP_CONFDONE AUTO 319 | set_global_assignment -name USE_SEU_ERROR AUTO 320 | set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" 321 | set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" 322 | set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" 323 | set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" 324 | set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" 325 | set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" 326 | set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" 327 | set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" 328 | set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" 329 | set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" 330 | set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" 331 | set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" 332 | set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" 333 | set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" 334 | set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" 335 | set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" 336 | set_global_assignment -name USER_START_UP_CLOCK Off 337 | set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off 338 | set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off 339 | set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On 340 | set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On 341 | set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC 342 | set_global_assignment -name ENABLE_VREFA_PIN Off 343 | set_global_assignment -name ENABLE_VREFB_PIN Off 344 | set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off 345 | set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off 346 | set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off 347 | set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off 348 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" 349 | set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off 350 | set_global_assignment -name INIT_DONE_OPEN_DRAIN On 351 | set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" 352 | set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" 353 | set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" 354 | set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" 355 | set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" 356 | set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" 357 | set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" 358 | set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" 359 | set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" 360 | set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" 361 | set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" 362 | set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" 363 | set_global_assignment -name ENABLE_CONFIGURATION_PINS On 364 | set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off 365 | set_global_assignment -name ENABLE_NCE_PIN Off 366 | set_global_assignment -name ENABLE_BOOT_SEL_PIN On 367 | set_global_assignment -name CRC_ERROR_CHECKING Off 368 | set_global_assignment -name INTERNAL_SCRUBBING Off 369 | set_global_assignment -name PR_ERROR_OPEN_DRAIN On 370 | set_global_assignment -name PR_READY_OPEN_DRAIN On 371 | set_global_assignment -name ENABLE_CVP_CONFDONE Off 372 | set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On 373 | set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On 374 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" 375 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix 10" 376 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" 377 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" 378 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" 379 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" 380 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" 381 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" 382 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" 383 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" 384 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" 385 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" 386 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" 387 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" 388 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix 10" 389 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" 390 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" 391 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" 392 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" 393 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" 394 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" 395 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" 396 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" 397 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" 398 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" 399 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" 400 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" 401 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" 402 | set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On 403 | set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto 404 | set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care 405 | set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" 406 | set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" 407 | set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" 408 | set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" 409 | set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 410 | set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On 411 | set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" 412 | set_global_assignment -name OPTIMIZE_SSN Off 413 | set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" 414 | set_global_assignment -name ECO_OPTIMIZE_TIMING Off 415 | set_global_assignment -name ECO_REGENERATE_REPORT Off 416 | set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal 417 | set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off 418 | set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically 419 | set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically 420 | set_global_assignment -name SEED 1 421 | set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF 422 | set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off 423 | set_global_assignment -name SLOW_SLEW_RATE Off 424 | set_global_assignment -name PCI_IO Off 425 | set_global_assignment -name TURBO_BIT On 426 | set_global_assignment -name WEAK_PULL_UP_RESISTOR Off 427 | set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off 428 | set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off 429 | set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On 430 | set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto 431 | set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto 432 | set_global_assignment -name NORMAL_LCELL_INSERT On 433 | set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On 434 | set_global_assignment -name AUTO_DELAY_CHAINS Off -family "Stratix 10" 435 | set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" 436 | set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" 437 | set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" 438 | set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" 439 | set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" 440 | set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" 441 | set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" 442 | set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" 443 | set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" 444 | set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" 445 | set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" 446 | set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" 447 | set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" 448 | set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF 449 | set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off 450 | set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off 451 | set_global_assignment -name AUTO_TURBO_BIT ON 452 | set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off 453 | set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off 454 | set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off 455 | set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off 456 | set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off 457 | set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off 458 | set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off 459 | set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On 460 | set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off 461 | set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off 462 | set_global_assignment -name FITTER_EFFORT "Auto Fit" 463 | set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns 464 | set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal 465 | set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto 466 | set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto 467 | set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off 468 | set_global_assignment -name AUTO_GLOBAL_CLOCK On 469 | set_global_assignment -name AUTO_GLOBAL_OE On 470 | set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On 471 | set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic 472 | set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off 473 | set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off 474 | set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off 475 | set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off 476 | set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off 477 | set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off 478 | set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off 479 | set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off 480 | set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off 481 | set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off 482 | set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off 483 | set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off 484 | set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off 485 | set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off 486 | set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off 487 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" 488 | set_global_assignment -name ENABLE_HOLD_BACK_OFF On 489 | set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto 490 | set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off 491 | set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto 492 | set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On 493 | set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On 494 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" 495 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" 496 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" 497 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" 498 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" 499 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" 500 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" 501 | set_global_assignment -name ENABLE_ED_CRC_CHECK On -family "Stratix 10" 502 | set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" 503 | set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" 504 | set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" 505 | set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" 506 | set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" 507 | set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ -family "Stratix 10" 508 | set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" 509 | set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" 510 | set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" 511 | set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" 512 | set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" 513 | set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" 514 | set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off 515 | set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On 516 | set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off 517 | set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off 518 | set_global_assignment -name PR_DONE_OPEN_DRAIN On 519 | set_global_assignment -name NCEO_OPEN_DRAIN On 520 | set_global_assignment -name ENABLE_CRC_ERROR_PIN Off 521 | set_global_assignment -name ENABLE_PR_PINS Off 522 | set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off 523 | set_global_assignment -name PR_PINS_OPEN_DRAIN Off 524 | set_global_assignment -name CLAMPING_DIODE Off 525 | set_global_assignment -name TRI_STATE_SPI_PINS Off 526 | set_global_assignment -name UNUSED_TSD_PINS_GND Off 527 | set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off 528 | set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off 529 | set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium 530 | set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix 10" 531 | set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" 532 | set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" 533 | set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" 534 | set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" 535 | set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" 536 | set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" 537 | set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 538 | set_global_assignment -name SEU_FIT_REPORT Off 539 | set_global_assignment -name HYPER_RETIMER Off 540 | set_global_assignment -name HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS OFF -family "Stratix 10" 541 | set_global_assignment -name HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS ON -family "Arria 10" 542 | set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" 543 | set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto 544 | set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto 545 | set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On 546 | set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On 547 | set_global_assignment -name EDA_SIMULATION_TOOL "" 548 | set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" 549 | set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" 550 | set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" 551 | set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" 552 | set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" 553 | set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" 554 | set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" 555 | set_global_assignment -name EDA_RESYNTHESIS_TOOL "" 556 | set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On 557 | set_global_assignment -name COMPRESSION_MODE Off 558 | set_global_assignment -name CLOCK_SOURCE Internal 559 | set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" 560 | set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 561 | set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On 562 | set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off 563 | set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On 564 | set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF 565 | set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF 566 | set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF 567 | set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF 568 | set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F 569 | set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF 570 | set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off 571 | set_global_assignment -name USE_CHECKSUM_AS_USERCODE On 572 | set_global_assignment -name SECURITY_BIT Off 573 | set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" 574 | set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" 575 | set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" 576 | set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" 577 | set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" 578 | set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" 579 | set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" 580 | set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" 581 | set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto 582 | set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto 583 | set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" 584 | set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 585 | set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000001 586 | set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000010 587 | set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000100 588 | set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0001000 589 | set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0010000 590 | set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" 591 | set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 592 | set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 593 | set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 594 | set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto 595 | set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto 596 | set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto 597 | set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto 598 | set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto 599 | set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto 600 | set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF 601 | set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF 602 | set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF 603 | set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF 604 | set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off 605 | set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On 606 | set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off 607 | set_global_assignment -name GENERATE_TTF_FILE Off 608 | set_global_assignment -name GENERATE_RBF_FILE Off 609 | set_global_assignment -name GENERATE_HEX_FILE Off 610 | set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 611 | set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up 612 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" 613 | set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off 614 | set_global_assignment -name AUTO_RESTART_CONFIGURATION On 615 | set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off 616 | set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off 617 | set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On 618 | set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" 619 | set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" 620 | set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" 621 | set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" 622 | set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" 623 | set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" 624 | set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" 625 | set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" 626 | set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" 627 | set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF 628 | set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off 629 | set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off 630 | set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off 631 | set_global_assignment -name POR_SCHEME "Instant ON" 632 | set_global_assignment -name EN_USER_IO_WEAK_PULLUP On 633 | set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On 634 | set_global_assignment -name POF_VERIFY_PROTECT Off 635 | set_global_assignment -name ENABLE_SPI_MODE_CHECK Off 636 | set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On 637 | set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off 638 | set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 639 | set_global_assignment -name START_TIME 0ns 640 | set_global_assignment -name SIMULATION_MODE TIMING 641 | set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off 642 | set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On 643 | set_global_assignment -name SETUP_HOLD_DETECTION Off 644 | set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off 645 | set_global_assignment -name CHECK_OUTPUTS Off 646 | set_global_assignment -name SIMULATION_COVERAGE On 647 | set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On 648 | set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On 649 | set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On 650 | set_global_assignment -name GLITCH_DETECTION Off 651 | set_global_assignment -name GLITCH_INTERVAL 1ns 652 | set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off 653 | set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On 654 | set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off 655 | set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On 656 | set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE 657 | set_global_assignment -name SIMULATION_NETLIST_VIEWER Off 658 | set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT 659 | set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT 660 | set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off 661 | set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO 662 | set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO 663 | set_global_assignment -name DRC_TOP_FANOUT 50 664 | set_global_assignment -name DRC_FANOUT_EXCEEDING 30 665 | set_global_assignment -name DRC_GATED_CLOCK_FEED 30 666 | set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY 667 | set_global_assignment -name ENABLE_DRC_SETTINGS Off 668 | set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 669 | set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 670 | set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 671 | set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 672 | set_global_assignment -name MERGE_HEX_FILE Off 673 | set_global_assignment -name GENERATE_SVF_FILE Off 674 | set_global_assignment -name GENERATE_ISC_FILE Off 675 | set_global_assignment -name GENERATE_JAM_FILE Off 676 | set_global_assignment -name GENERATE_JBC_FILE Off 677 | set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On 678 | set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off 679 | set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off 680 | set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off 681 | set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off 682 | set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On 683 | set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off 684 | set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" 685 | set_global_assignment -name HPS_EARLY_IO_RELEASE Off 686 | set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off 687 | set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off 688 | set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% 689 | set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% 690 | set_global_assignment -name POWER_USE_PVA On 691 | set_global_assignment -name POWER_USE_INPUT_FILE "No File" 692 | set_global_assignment -name POWER_USE_INPUT_FILES Off 693 | set_global_assignment -name POWER_VCD_FILTER_GLITCHES On 694 | set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off 695 | set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off 696 | set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL 697 | set_global_assignment -name POWER_AUTO_COMPUTE_TJ On 698 | set_global_assignment -name POWER_TJ_VALUE 25 699 | set_global_assignment -name POWER_USE_TA_VALUE 25 700 | set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off 701 | set_global_assignment -name POWER_BOARD_TEMPERATURE 25 702 | set_global_assignment -name POWER_HPS_ENABLE Off 703 | set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 704 | set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off 705 | set_global_assignment -name IGNORE_PARTITIONS Off 706 | set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off 707 | set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On 708 | set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" 709 | set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On 710 | set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On 711 | set_global_assignment -name RTLV_GROUP_RELATED_NODES On 712 | set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off 713 | set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off 714 | set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On 715 | set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On 716 | set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On 717 | set_global_assignment -name EQC_BBOX_MERGE On 718 | set_global_assignment -name EQC_LVDS_MERGE On 719 | set_global_assignment -name EQC_RAM_UNMERGING On 720 | set_global_assignment -name EQC_DFF_SS_EMULATION On 721 | set_global_assignment -name EQC_RAM_REGISTER_UNPACK On 722 | set_global_assignment -name EQC_MAC_REGISTER_UNPACK On 723 | set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On 724 | set_global_assignment -name EQC_STRUCTURE_MATCHING On 725 | set_global_assignment -name EQC_AUTO_BREAK_CONE On 726 | set_global_assignment -name EQC_POWER_UP_COMPARE Off 727 | set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On 728 | set_global_assignment -name EQC_AUTO_INVERSION On 729 | set_global_assignment -name EQC_AUTO_TERMINATE On 730 | set_global_assignment -name EQC_SUB_CONE_REPORT Off 731 | set_global_assignment -name EQC_RENAMING_RULES On 732 | set_global_assignment -name EQC_PARAMETER_CHECK On 733 | set_global_assignment -name EQC_AUTO_PORTSWAP On 734 | set_global_assignment -name EQC_DETECT_DONT_CARES On 735 | set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off 736 | set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? 737 | set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? 738 | set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? 739 | set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? 740 | set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? 741 | set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? 742 | set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? 743 | set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? 744 | set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? 745 | set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? 746 | set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? 747 | set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? 748 | set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? 749 | set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? 750 | set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? 751 | set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? 752 | set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? 753 | set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? 754 | set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? 755 | set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? 756 | set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? 757 | set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? 758 | set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? 759 | set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? 760 | set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? 761 | set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? 762 | set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? 763 | set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? 764 | set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? 765 | set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? 766 | set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? 767 | set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? 768 | set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? 769 | set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? 770 | set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? 771 | set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? 772 | set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? 773 | set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? 774 | set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? 775 | set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ? 776 | set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? 777 | set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? 778 | set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? 779 | set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? 780 | set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? 781 | set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? 782 | set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? 783 | set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? 784 | set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? 785 | set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? 786 | set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? 787 | set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? 788 | set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? 789 | set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? 790 | set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? 791 | set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? 792 | set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? 793 | set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? 794 | set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? 795 | set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? 796 | set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? 797 | set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? 798 | set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? 799 | set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? 800 | --------------------------------------------------------------------------------