├── Arithmetic_Logic_Unit.v ├── Defines.vh ├── Firmware ├── Assembly.s ├── Assembly.txt ├── Firmware.hex └── hexConverter.py ├── Fixed_Point_Unit.gtkw ├── Fixed_Point_Unit.v ├── Fixed_Point_Unit.vcd ├── Fixed_Point_Unit.vvp ├── Fixed_Point_Unit_Testbench.v ├── Images ├── Datapath_1.png ├── Datapath_2.png ├── Datapath_3.png └── LUMOS.png ├── Immediate_Generator.v ├── LUMOS.gtkw ├── LUMOS.v ├── LUMOS.vcd ├── LUMOS.vvp ├── LUMOS_Testbench.v ├── README.md ├── Register_File.v ├── Synthesis ├── LUMOS.sdc ├── LUMOS.v ├── LUMOS.vh ├── WORK │ ├── ARITHMETIC_LOGIC_UNIT.mr │ ├── Arithmetic_Logic_Unit-verilog.pvl │ ├── Arithmetic_Logic_Unit-verilog.syn │ ├── FIXED_POINT_UNIT.mr │ ├── Fixed_Point_Unit-verilog.pvl │ ├── Fixed_Point_Unit-verilog.syn │ ├── IMMEDIATE_GENERATOR.mr │ ├── Immediate_Generator-verilog.pvl │ ├── Immediate_Generator-verilog.syn │ ├── LUMOS-verilog.pvl │ ├── LUMOS-verilog.syn │ ├── LUMOS.mr │ ├── MULTIPLIER.mr │ ├── Multiplier-verilog.pvl │ ├── Multiplier-verilog.syn │ ├── REGISTER_FILE.mr │ ├── Register_File-verilog.pvl │ └── Register_File-verilog.syn ├── alib-52 │ └── gscl45nm.db.alib ├── command.log ├── compile_dc.tcl ├── default.svf ├── encounter.cmd ├── encounter.cmd1 ├── encounter.conf ├── encounter.log ├── encounter.log1 ├── encounter.tcl ├── reports │ ├── area.rep │ ├── cell.rep │ ├── power.rep │ └── timing.rep ├── snap.png ├── snap.xwd └── timing.rep.1.placed └── gtkwave.ini /Arithmetic_Logic_Unit.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/HEAD/Arithmetic_Logic_Unit.v -------------------------------------------------------------------------------- /Defines.vh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/HEAD/Defines.vh -------------------------------------------------------------------------------- /Firmware/Assembly.s: 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