├── Arithmetic_Logic_Unit.v ├── Defines.vh ├── Firmware ├── Assembly.s ├── Assembly.txt ├── Firmware.hex └── hexConverter.py ├── Fixed_Point_Unit.gtkw ├── Fixed_Point_Unit.v ├── Fixed_Point_Unit.vcd ├── Fixed_Point_Unit.vvp ├── Fixed_Point_Unit_Testbench.v ├── Images ├── Datapath_1.png ├── Datapath_2.png ├── Datapath_3.png └── LUMOS.png ├── Immediate_Generator.v ├── LUMOS.gtkw ├── LUMOS.v ├── LUMOS.vcd ├── LUMOS.vvp ├── LUMOS_Testbench.v ├── README.md ├── Register_File.v ├── Synthesis ├── LUMOS.sdc ├── LUMOS.v ├── LUMOS.vh ├── WORK │ ├── ARITHMETIC_LOGIC_UNIT.mr │ ├── Arithmetic_Logic_Unit-verilog.pvl │ ├── Arithmetic_Logic_Unit-verilog.syn │ ├── FIXED_POINT_UNIT.mr │ ├── Fixed_Point_Unit-verilog.pvl │ ├── Fixed_Point_Unit-verilog.syn │ ├── IMMEDIATE_GENERATOR.mr │ ├── Immediate_Generator-verilog.pvl │ ├── Immediate_Generator-verilog.syn │ ├── LUMOS-verilog.pvl │ ├── LUMOS-verilog.syn │ ├── LUMOS.mr │ ├── MULTIPLIER.mr │ ├── Multiplier-verilog.pvl │ ├── Multiplier-verilog.syn │ ├── REGISTER_FILE.mr │ ├── Register_File-verilog.pvl │ └── Register_File-verilog.syn ├── alib-52 │ └── gscl45nm.db.alib ├── command.log ├── compile_dc.tcl ├── default.svf ├── encounter.cmd ├── encounter.cmd1 ├── encounter.conf ├── encounter.log ├── encounter.log1 ├── encounter.tcl ├── reports │ ├── area.rep │ ├── cell.rep │ ├── power.rep │ └── timing.rep ├── snap.png ├── snap.xwd └── timing.rep.1.placed └── gtkwave.ini /Arithmetic_Logic_Unit.v: -------------------------------------------------------------------------------- 1 | // LUMOS - Light Utilization with Multicycle Operational Stages 2 | // A RISC-V RV32I Processor Core 3 | 4 | // Description: LUMOS Core Arithmetic Logic Unit Module 5 | // Copyright 2024 Iran University of Science and Technology. 6 | 7 | // Permission to use, copy, modify, and/or distribute this software for any 8 | // purpose with or without fee is hereby granted, provided that the above 9 | // copyright notice and this permission notice appear in all copies. 10 | 11 | `include "Defines.vh" 12 | 13 | module Arithmetic_Logic_Unit 14 | ( 15 | input wire [ 3 : 0] operation, 16 | 17 | input wire [31 : 0] operand_1, 18 | input wire [31 : 0] operand_2, 19 | 20 | output reg [31 : 0] result, 21 | output reg zero, 22 | output reg sign 23 | ); 24 | 25 | always @(*) 26 | begin 27 | case (operation) 28 | `ALU_ADD : result = operand_1 + operand_2; 29 | `ALU_SUB : result = operand_1 - operand_2; 30 | `ALU_AND : result = operand_1 & operand_2; 31 | `ALU_OR : result = operand_1 | operand_2; 32 | `ALU_XOR : result = operand_1 ^ operand_2; 33 | 34 | `ALU_SLT : result = $signed(operand_1) < $signed(operand_2) ? 1 : 0; 35 | `ALU_SLTU : result = operand_1 < operand_2 ? 1 : 0; 36 | 37 | `ALU_SLL : result = operand_1 << operand_2[4 : 0]; 38 | `ALU_SRL : result = operand_1 >> operand_2[4 : 0]; 39 | `ALU_SRA : result = operand_1 >>> operand_2[4 : 0]; 40 | default : result = 'bz; 41 | endcase 42 | end 43 | 44 | always @(*) 45 | begin 46 | sign <= result[31]; 47 | if (result == 0) 48 | zero <= 1; 49 | else 50 | zero <= 0; 51 | end 52 | endmodule -------------------------------------------------------------------------------- /Defines.vh: -------------------------------------------------------------------------------- 1 | // LUMOS - Light Utilization with Multicycle Operational Stages 2 | // A RISC-V RV32I Processor Core 3 | 4 | // Description: LUMOS Core Definitions 5 | // Copyright 2024 Iran University of Science and Technology. 6 | 7 | // Permission to use, copy, modify, and/or distribute this software for any 8 | // purpose with or without fee is hereby granted, provided that the above 9 | // copyright notice and this permission notice appear in all copies. 10 | 11 | `ifndef OPCODES 12 | `define LOAD 7'b00_000_11 13 | `define LOAD_FP 7'b00_001_11 14 | `define custom_0 7'b00_010_11 15 | `define MISC_MEM 7'b00_011_11 16 | `define OP_IMM 7'b00_100_11 17 | `define AUIPC 7'b00_101_11 18 | `define OP_IMM_32 7'b00_110_11 19 | 20 | `define STORE 7'b01_000_11 21 | `define STORE_FP 7'b01_001_11 22 | `define custom_1 7'b01_010_11 23 | `define AMO 7'b01_011_11 24 | `define OP 7'b01_100_11 25 | `define LUI 7'b01_101_11 26 | `define OP_32 7'b01_110_11 27 | 28 | `define MADD 7'b10_000_11 29 | `define MSUB 7'b10_001_11 30 | `define NMSUB 7'b10_010_11 31 | `define NMADD 7'b10_011_11 32 | `define OP_FP 7'b10_100_11 33 | `define custom_2 7'b10_110_11 34 | 35 | `define BRANCH 7'b11_000_11 36 | `define JALR 7'b11_001_11 37 | `define JAL 7'b11_011_11 38 | `define SYSTEM 7'b11_100_11 39 | `define custom_3 7'b11_110_11 40 | `endif /*OPCODES*/ 41 | 42 | `ifndef INSTRUCTION_TYPES 43 | `define R_TYPE 0 44 | `define I_TYPE 1 45 | `define S_TYPE 2 46 | `define B_TYPE 3 47 | `define U_TYPE 4 48 | `define J_TYPE 5 49 | `endif /*INSTRUCTION_TYPES*/ 50 | 51 | `ifndef I_INSTRUCTIONS 52 | `define ADDI 3'b000 53 | `define SLTI 3'b010 54 | `define SLTIU 3'b011 55 | `define XORI 3'b100 56 | `define ORI 3'b110 57 | `define ANDI 3'b111 58 | `define SLLI 3'b001 // Shift Left Immediate -> Logical 59 | `define SRI 3'b101 // Shift Right Immediate -> Logical & Arithmetic 60 | `endif /*I_INSTRUCTIONS*/ 61 | 62 | `ifndef R_INSTRUCTIONS 63 | `define ADDSUB 3'b000 64 | `define SLL 3'b001 // Shift Left -> Logical 65 | `define SLT 3'b010 66 | `define SLTU 3'b011 67 | `define XOR 3'b100 68 | `define SR 3'b101 // Shift Right -> Logical & Arithmetic 69 | `define OR 3'b110 70 | `define AND 3'b111 71 | `endif /*R_INSTRUCTIONS*/ 72 | 73 | `ifndef MUL_DIV_INSTRCUTIONS 74 | `define MUL 3'b000 75 | `define MULH 3'b001 76 | `define MULHSU 3'b010 77 | `define MULHU 3'b011 78 | 79 | `define DIV 3'b100 80 | `define DIVU 3'b101 81 | `define REM 3'b110 82 | `define REMU 3'b111 83 | 84 | `define MULDIV 7'b0000001 85 | `endif /*MUL_DIV_INSTRCUTIONS*/ 86 | 87 | `ifndef FIXED_POINT_INSTRUCTIONS 88 | `define FADD 7'b000_0000 89 | `define FSUB 7'b000_0100 90 | 91 | `define FMUL 7'b000_1000 92 | `define FDIV 7'b000_1100 93 | 94 | `define FSQRT 7'b010_1100 95 | `endif /*FIXED_POINT_INSTRUCTIONS*/ 96 | 97 | `ifndef BRANCH_INSTRUCTIONS 98 | `define BEQ 3'b000 99 | `define BNE 3'b001 100 | `define BLT 3'b100 101 | `define BGE 3'b101 102 | `define BLTU 3'b110 103 | `define BGEU 3'b111 104 | `endif /*BRANCH_INSTRUCTIONS*/ 105 | 106 | `ifndef ALU_OPERATIONS 107 | `define ALU_ADD 4'b0000 108 | `define ALU_SUB 4'b0001 109 | `define ALU_AND 4'b0010 110 | `define ALU_OR 4'b0011 111 | `define ALU_XOR 4'b0100 112 | `define ALU_SLT 4'b0101 113 | `define ALU_SLTU 4'b0110 114 | `define ALU_SLL 4'b0111 115 | `define ALU_SRL 4'b1000 116 | `define ALU_SRA 4'b1001 117 | `endif /*ALU_OPERATIONS*/ 118 | 119 | `ifndef ALU_AUXILIARY_DEFINES 120 | `define LOGICAL 7'b000_0000 121 | `define ARITHMETIC 7'b010_0000 122 | `define ADD 7'b000_0000 123 | `define SUB 7'b010_0000 124 | `endif /*ALU_AUXILIARY_DEFINES*/ 125 | 126 | `ifndef FPU_OPERATIONS 127 | `define FPU_ADD 2'b00 128 | `define FPU_SUB 2'b01 129 | `define FPU_MUL 2'b10 130 | `define FPU_SQRT 2'b11 131 | `endif /*FPU_OPERATIONS*/ 132 | 133 | `ifndef ALU_SRC_SELECT 134 | `define PC 2'b00 135 | `define RS1 2'b01 136 | `define ALU_RESULT 2'b10 137 | `define ZERO 2'b11 138 | 139 | `define RS2 2'b00 140 | `define FOUR 2'b01 141 | `define IMMEDIATE 2'b10 142 | `endif /*ALU_SRC_SELECT*/ 143 | 144 | `ifndef REGISTER_FILE_WRITE_SOURCE 145 | `define MEMORY 2'b00 146 | `define ALU 2'b01 147 | `define NEXT_PC 2'b10 148 | `define FPU 2'b11 149 | `endif /*REGISTER_FILE_WRITE_SOURCE*/ 150 | 151 | `ifndef CONTROL_SIGNALS 152 | `define INSTRUCTION 1'b0 153 | `define DATA 1'b1 154 | 155 | `define READ 1'b0 156 | `define WRITE 1'b1 157 | 158 | `define DISABLE 1'b0 159 | `define ENABLE 1'b1 160 | `endif /*CONTROL_SIGNALS*/ 161 | 162 | `ifndef CONTROLLER_STATES 163 | `define RESET 0 164 | `define FETCH_BEGIN 1 165 | `define FETCH_WAIT 2 166 | `define FETCH_DONE 3 167 | `define DECODE 4 168 | `define EXECUTE 5 169 | `define EXECUTE_BRANCH 6 170 | `define TAKE_BRANCH 7 171 | `define EXECUTE_JUMP 8 172 | `define MEMORY_WRITE 9 173 | `define MEMORY_READ_BEGIN 10 174 | `define MEMORY_READ_WAIT 11 175 | `define MEMORY_READ_DONE 12 176 | `define EXECUTE_FP 13 177 | `endif /*CONTROLLER_STATES*/ -------------------------------------------------------------------------------- /Firmware/Assembly.s: -------------------------------------------------------------------------------- 1 | main: 2 | li sp, 0x3C00 3 | addi gp, sp, 392 4 | loop: 5 | flw f1, 0(sp) 6 | flw f2, 4(sp) 7 | 8 | fmul.s f10, f1, f1 9 | fmul.s f20, f2, f2 10 | fadd.s f30, f10, f20 11 | fsqrt.s x3, f30 12 | fadd.s f0, f0, f3 13 | 14 | addi sp, sp, 8 15 | blt sp, gp, loop 16 | ebreak 17 | -------------------------------------------------------------------------------- /Firmware/Assembly.txt: -------------------------------------------------------------------------------- 1 | 0x00000000 0x00004137 lui x2 4 2 | 0x00000004 0xC0010113 addi x2 x2 -1024 3 | 0x00000008 0x18810193 addi x3 x2 392 4 | 0x0000000C 0x00012087 flw f1 0(x2) 5 | 0x00000010 0x00412107 flw f2 4(x2) 6 | 0x00000014 0x10108553 fmul.s f10 f1 f1 7 | 0x00000018 0x10210A53 fmul.s f20 f2 f2 8 | 0x0000001C 0x01450F53 fadd.s f30 f10 f20 9 | 0x00000020 0x580F01D3 fsqrt.s f3 f30 10 | 0x00000024 0x00300053 fadd.s f0 f0 f3 11 | 0x00000028 0x00810113 addi x2 x2 8 12 | 0x0000002C 0xFE3140E3 blt x2 x3 -32 13 | 0x00000030 0x00100073 ebreak 14 | -------------------------------------------------------------------------------- /Firmware/Firmware.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 00004137 3 | C0010113 4 | 18810193 5 | 00012087 6 | 00412107 7 | 10108553 8 | 10210A53 9 | 01450F53 10 | 580F01D3 11 | 00300053 12 | 00810113 13 | FE3140E3 14 | 00100073 15 | @00000F00 16 | 00000800 17 | 0000C400 18 | 00000400 19 | 00003000 20 | 00001C00 21 | 00008400 22 | 00001800 23 | 00004C00 24 | 00002000 25 | 00004000 26 | 00004800 27 | 00005800 28 | 00003800 29 | 00005000 30 | 00001000 31 | 00003C00 32 | 00000000 33 | 00007000 34 | 00001000 35 | 00006000 36 | 00001400 37 | 00005400 38 | 0000DC00 39 | 00004800 40 | 00000800 41 | 00004400 42 | 00009000 43 | 00004C00 44 | 00000400 45 | 00007400 46 | 00007000 47 | 00002C00 48 | 00004000 49 | 00003000 50 | 00001C00 51 | 00002C00 52 | 00000400 53 | 00005000 54 | 00001800 55 | 00004000 56 | 00003C00 57 | 00004400 58 | 00006400 59 | 00003800 60 | 00004000 61 | 00001400 62 | 00005400 63 | 00000C00 64 | 00007C00 65 | 00002C00 66 | 00004000 67 | 00002000 68 | 00003C00 69 | 00002800 70 | 00003400 71 | 00002C00 72 | 00003000 73 | 00003000 74 | 00002800 75 | 00003400 76 | 00003000 77 | 00005800 78 | 00001C00 79 | 00006000 80 | 00000400 81 | 00004400 82 | 00003C00 83 | 00001400 84 | 00006800 85 | 00003C00 86 | 00003C00 87 | 00002800 88 | 00003800 89 | 00002C00 90 | 00003400 91 | 00003000 92 | 00003400 93 | 00003400 94 | 00003000 95 | 00003800 96 | 00003000 97 | 00003800 98 | 00002C00 99 | 00003C00 100 | 00002800 101 | 00003C00 102 | 00000000 103 | 00008000 104 | 00001400 105 | 00006800 106 | 00003400 107 | 00007800 108 | 00001400 109 | 00002000 110 | 00003000 111 | 00003C00 112 | 00003800 113 | 00003800 -------------------------------------------------------------------------------- /Firmware/hexConverter.py: -------------------------------------------------------------------------------- 1 | import sys 2 | 3 | file_name = sys.argv[1] 4 | firmware_name = "Firmware" + ".hex" 5 | 6 | with open(file_name, "r") as file: 7 | lines = file.readlines() 8 | 9 | modified_lines = [line.split()[1][2:] +'\n' for line in lines] 10 | 11 | final_hex_code = [elem for elem in modified_lines if elem != '\n\n'] 12 | 13 | with open(firmware_name, "w") as file: 14 | file.writelines(final_hex_code) 15 | -------------------------------------------------------------------------------- /Fixed_Point_Unit.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.100 (w)1999-2019 BSI 3 | [*] Mon Jun 03 13:58:52 2024 4 | [*] 5 | [dumpfile] "D:\GitHub\IUST-Computer-Organization\LUMOS\Fixed_Point_Unit.vcd" 6 | [dumpfile_mtime] "Mon Jun 03 13:56:16 2024" 7 | [dumpfile_size] 6456 8 | [savefile] "D:\GitHub\IUST-Computer-Organization\LUMOS\Fixed_Point_Unit.gtkw" 9 | [timestart] 0 10 | [size] 1920 1009 11 | [pos] -1 -1 12 | *-4.605382 156 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] Fixed_Point_Unit_Testbench. 14 | [sst_width] 42 15 | [signals_width] 306 16 | [sst_expanded] 0 17 | [sst_vpaned_height] 297 18 | @28 19 | Fixed_Point_Unit_Testbench.clk 20 | Fixed_Point_Unit_Testbench.reset 21 | @200 22 | - 23 | @29 24 | Fixed_Point_Unit_Testbench.operation[1:0] 25 | @200 26 | - 27 | @40000024 28 | [fpshift_count] 10 29 | Fixed_Point_Unit_Testbench.operand_1[31:0] 30 | [fpshift_count] 10 31 | Fixed_Point_Unit_Testbench.operand_2[31:0] 32 | @200 33 | - 34 | @40000024 35 | [fpshift_count] 10 36 | Fixed_Point_Unit_Testbench.fpu_result[31:0] 37 | @28 38 | Fixed_Point_Unit_Testbench.fpu_ready 39 | [pattern_trace] 1 40 | [pattern_trace] 0 41 | -------------------------------------------------------------------------------- /Fixed_Point_Unit.v: -------------------------------------------------------------------------------- 1 | `include "Defines.vh" 2 | 3 | module Fixed_Point_Unit 4 | #( 5 | parameter WIDTH = 32, 6 | parameter FBITS = 10 7 | ) 8 | ( 9 | input wire clk, 10 | input wire reset, 11 | 12 | input wire [WIDTH - 1 : 0] operand_1, 13 | input wire [WIDTH - 1 : 0] operand_2, 14 | 15 | input wire [ 1 : 0] operation, 16 | 17 | output reg [WIDTH - 1 : 0] result, 18 | output reg ready 19 | ); 20 | 21 | always @(*) 22 | begin 23 | case (operation) 24 | `FPU_ADD : begin result = operand_1 + operand_2; ready = 1; end 25 | `FPU_SUB : begin result = operand_1 - operand_2; ready = 1; end 26 | `FPU_MUL : begin result = product[WIDTH + FBITS - 1 : FBITS]; ready = product_ready; end 27 | `FPU_SQRT : begin result = root; ready = root_ready; end 28 | default : begin result = 'bz; ready = 0; end 29 | endcase 30 | end 31 | 32 | always @(posedge reset) 33 | begin 34 | if (reset) ready = 0; 35 | else ready = 'bz; 36 | end 37 | // ------------------- // 38 | // Square Root Circuit // 39 | // ------------------- // 40 | reg [WIDTH - 1 : 0] root; 41 | reg root_ready; 42 | 43 | reg [1 : 0] square_root_stage; 44 | reg [1 : 0] next_square_root_stage; 45 | 46 | always @(posedge clk) 47 | begin 48 | if (operation == `FPU_SQRT) square_root_stage <= next_square_root_stage; 49 | else 50 | begin 51 | square_root_stage <= 2'b00; 52 | root_ready <= 0; 53 | end 54 | end 55 | 56 | always @(*) 57 | begin 58 | next_square_root_stage <= 'bz; 59 | case (square_root_stage) 60 | 2'b00 : begin sqrt_start <= 0; next_square_root_stage <= 2'b01; end 61 | 2'b01 : begin sqrt_start <= 1; next_square_root_stage <= 2'b10; end 62 | 2'b10 : begin sqrt_start <= 0; next_square_root_stage <= 2'b10; end 63 | endcase 64 | end 65 | reg sqrt_start; 66 | reg sqrt_busy; 67 | 68 | reg [WIDTH - 1 : 0] x, x_next; 69 | reg [WIDTH - 1 : 0] q, q_next; 70 | reg [WIDTH + 1 : 0] ac, ac_next; 71 | reg [WIDTH + 1 : 0] test_res; 72 | 73 | reg valid; 74 | 75 | localparam ITER = (WIDTH + FBITS) >> 1; 76 | reg [4 : 0] i = 0; 77 | 78 | always @(*) 79 | begin 80 | test_res = ac - {q, 2'b01}; 81 | 82 | if (test_res[WIDTH + 1] == 0) 83 | begin 84 | {ac_next, x_next} = {test_res[WIDTH - 1 : 0], x, 2'b0}; 85 | q_next = {q[WIDTH - 2 : 0], 1'b1}; 86 | end 87 | else 88 | begin 89 | {ac_next, x_next} = {ac[WIDTH - 1 : 0], x, 2'b0}; 90 | q_next = q << 1; 91 | end 92 | end 93 | 94 | always @(posedge clk) 95 | begin 96 | if (sqrt_start) 97 | begin 98 | sqrt_busy <= 1; 99 | root_ready <= 0; 100 | i <= 0; 101 | q <= 0; 102 | {ac, x} <= {{WIDTH{1'b0}}, operand_1, 2'b0}; 103 | end 104 | 105 | else if (sqrt_busy) 106 | begin 107 | if (i == ITER-1) 108 | begin 109 | sqrt_busy <= 0; 110 | root_ready <= 1; 111 | root <= q_next; 112 | end 113 | 114 | else 115 | begin 116 | i <= i + 1; 117 | x <= x_next; 118 | ac <= ac_next; 119 | q <= q_next; 120 | root_ready <= 0; 121 | end 122 | end 123 | end 124 | 125 | // ------------------ // 126 | // Multiplier Circuit // 127 | // ------------------ // 128 | reg [64 - 1 : 0] product; 129 | reg product_ready; 130 | 131 | reg [15 : 0] multiplierCircuitInput1; 132 | reg [15 : 0] multiplierCircuitInput2; 133 | wire [31 : 0] multiplierCircuitResult; 134 | 135 | Multiplier_16bit multiplier_circuit 136 | ( 137 | .operand_1(multiplierCircuitInput1), 138 | .operand_2(multiplierCircuitInput2), 139 | .product(multiplierCircuitResult) 140 | ); 141 | 142 | reg [31 : 0] partialProduct1; 143 | reg [31 : 0] partialProduct2; 144 | reg [31 : 0] partialProduct3; 145 | reg [31 : 0] partialProduct4; 146 | 147 | reg [2 : 0] multiplication_stage; 148 | reg [2 : 0] next_multiplication_stage; 149 | 150 | always @(posedge clk) 151 | begin 152 | if (operation == `FPU_MUL) multiplication_stage <= next_multiplication_stage; 153 | else multiplication_stage <= 'b0; 154 | end 155 | 156 | always @(*) 157 | begin 158 | next_multiplication_stage <= 'bz; 159 | case (multiplication_stage) 160 | 3'b000 : 161 | begin 162 | product_ready <= 0; 163 | 164 | multiplierCircuitInput1 <= 'bz; 165 | multiplierCircuitInput2 <= 'bz; 166 | 167 | partialProduct1 <= 'bz; 168 | partialProduct2 <= 'bz; 169 | partialProduct3 <= 'bz; 170 | partialProduct4 <= 'bz; 171 | 172 | next_multiplication_stage <= 3'b001; 173 | end 174 | 3'b001 : 175 | begin 176 | multiplierCircuitInput1 <= operand_1[15 : 0]; 177 | multiplierCircuitInput2 <= operand_2[15 : 0]; 178 | partialProduct1 <= multiplierCircuitResult; 179 | next_multiplication_stage <= 3'b010; 180 | end 181 | 3'b010 : 182 | begin 183 | multiplierCircuitInput1 <= operand_1[31 : 16]; 184 | multiplierCircuitInput2 <= operand_2[15 : 0]; 185 | partialProduct2 <= multiplierCircuitResult; 186 | next_multiplication_stage <= 3'b011; 187 | end 188 | 3'b011 : 189 | begin 190 | multiplierCircuitInput1 <= operand_1[15 : 0]; 191 | multiplierCircuitInput2 <= operand_2[31 : 16]; 192 | partialProduct3 <= multiplierCircuitResult; 193 | next_multiplication_stage <= 3'b100; 194 | end 195 | 3'b100 : 196 | begin 197 | multiplierCircuitInput1 <= operand_1[31 : 16]; 198 | multiplierCircuitInput2 <= operand_2[31 : 16]; 199 | partialProduct4 <= multiplierCircuitResult; 200 | next_multiplication_stage <= 3'b101; 201 | end 202 | 3'b101 : 203 | begin 204 | product <= partialProduct1 + (partialProduct2 << 16) + (partialProduct3 << 16) + (partialProduct4 << 32); 205 | next_multiplication_stage <= 3'b000; 206 | product_ready <= 1; 207 | end 208 | 209 | default: next_multiplication_stage <= 3'b000; 210 | endcase 211 | end 212 | endmodule 213 | 214 | module Multiplier_16bit 215 | ( 216 | input wire [15 : 0] operand_1, 217 | input wire [15 : 0] operand_2, 218 | output wire [31 : 0] product 219 | ); 220 | wire [7 : 0] operand_1_low = operand_1[ 7 : 0]; 221 | wire [7 : 0] operand_1_high = operand_1[15 : 8]; 222 | wire [7 : 0] operand_2_low = operand_2[ 7 : 0]; 223 | wire [7 : 0] operand_2_high = operand_2[15 : 8]; 224 | 225 | wire [15 : 0] partial_product_0; 226 | wire [15 : 0] partial_product_1; 227 | wire [15 : 0] partial_product_2; 228 | wire [15 : 0] partial_product_3; 229 | 230 | Multiplier MUL_PP_0 (.operand_1(operand_1_low), .operand_2(operand_2_low), .product(partial_product_0)); 231 | Multiplier MUL_PP_1 (.operand_1(operand_1_low), .operand_2(operand_2_high), .product(partial_product_1)); 232 | Multiplier MUL_PP_2 (.operand_1(operand_1_high), .operand_2(operand_2_low), .product(partial_product_2)); 233 | Multiplier MUL_PP_3 (.operand_1(operand_1_high), .operand_2(operand_2_high), .product(partial_product_3)); 234 | 235 | assign product = partial_product_0 + 236 | ({partial_product_1, 8'b0}) + 237 | ({partial_product_2, 8'b0}) + 238 | ({partial_product_3, 16'b0}); 239 | endmodule 240 | 241 | module Multiplier 242 | ( 243 | input wire [7 : 0] operand_1, 244 | input wire [7 : 0] operand_2, 245 | 246 | output reg [15 : 0] product 247 | ); 248 | 249 | always @(*) 250 | begin 251 | product <= operand_1 * operand_2; 252 | end 253 | endmodule -------------------------------------------------------------------------------- /Fixed_Point_Unit.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Tue Jun 04 00:34:50 2024 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1ns 9 | $end 10 | $scope module Fixed_Point_Unit_Testbench $end 11 | $var wire 32 ! fpu_result [31:0] $end 12 | $var wire 1 " fpu_ready $end 13 | $var parameter 32 # CLK_PERIOD $end 14 | $var reg 1 $ clk $end 15 | $var reg 32 % operand_1 [31:0] $end 16 | $var reg 32 & operand_2 [31:0] $end 17 | $var reg 2 ' operation [1:0] $end 18 | $var reg 1 ( reset $end 19 | $scope module uut $end 20 | $var wire 1 $ clk $end 21 | $var wire 32 ) operand_1 [31:0] $end 22 | $var wire 32 * operand_2 [31:0] $end 23 | $var wire 2 + operation [1:0] $end 24 | $var wire 1 ( reset $end 25 | $var wire 32 , multiplierCircuitResult [31:0] $end 26 | $var parameter 32 - FBITS $end 27 | $var parameter 32 . ITER $end 28 | $var parameter 32 / WIDTH $end 29 | $var reg 34 0 ac [33:0] $end 30 | $var reg 34 1 ac_next [33:0] $end 31 | $var reg 5 2 i [4:0] $end 32 | $var reg 3 3 multiplication_stage [2:0] $end 33 | $var reg 16 4 multiplierCircuitInput1 [15:0] $end 34 | $var reg 16 5 multiplierCircuitInput2 [15:0] $end 35 | $var reg 3 6 next_multiplication_stage [2:0] $end 36 | $var reg 2 7 next_square_root_stage [1:0] $end 37 | $var reg 32 8 partialProduct1 [31:0] $end 38 | $var reg 32 9 partialProduct2 [31:0] $end 39 | $var reg 32 : partialProduct3 [31:0] $end 40 | $var reg 32 ; partialProduct4 [31:0] $end 41 | $var reg 64 < product [63:0] $end 42 | $var reg 1 = product_ready $end 43 | $var reg 32 > q [31:0] $end 44 | $var reg 32 ? q_next [31:0] $end 45 | $var reg 1 " ready $end 46 | $var reg 32 @ result [31:0] $end 47 | $var reg 32 A root [31:0] $end 48 | $var reg 1 B root_ready $end 49 | $var reg 1 C sqrt_busy $end 50 | $var reg 1 D sqrt_start $end 51 | $var reg 2 E square_root_stage [1:0] $end 52 | $var reg 34 F test_res [33:0] $end 53 | $var reg 32 G x [31:0] $end 54 | $var reg 32 H x_next [31:0] $end 55 | $scope module multiplier_circuit $end 56 | $var wire 16 I operand_1 [15:0] $end 57 | $var wire 16 J operand_2 [15:0] $end 58 | $var reg 32 K product [31:0] $end 59 | $upscope $end 60 | $upscope $end 61 | $upscope $end 62 | $enddefinitions $end 63 | $comment Show the parameter values. $end 64 | $dumpall 65 | b100000 / 66 | b10101 . 67 | b1010 - 68 | b100 # 69 | $end 70 | #0 71 | $dumpvars 72 | bx K 73 | bz J 74 | bz I 75 | bx H 76 | bx G 77 | bx F 78 | b0 E 79 | 0D 80 | xC 81 | 0B 82 | bx A 83 | bz @ 84 | bx ? 85 | bx > 86 | 0= 87 | bx < 88 | bz ; 89 | bz : 90 | bz 9 91 | bz 8 92 | b1 7 93 | b1 6 94 | bz 5 95 | bz 4 96 | b0 3 97 | b0 2 98 | bx 1 99 | bx 0 100 | bx , 101 | bx + 102 | bx * 103 | bx ) 104 | 1( 105 | bx ' 106 | bx & 107 | bx % 108 | 1$ 109 | 0" 110 | bz ! 111 | $end 112 | #2 113 | 0$ 114 | #4 115 | 1$ 116 | #6 117 | 0$ 118 | #8 119 | 1$ 120 | #10 121 | 0$ 122 | #12 123 | 0( 124 | 1$ 125 | #14 126 | 0$ 127 | #16 128 | 1$ 129 | #18 130 | 0$ 131 | #20 132 | b1 6 133 | 1" 134 | b1111011000000 ! 135 | b1111011000000 @ 136 | b0 ' 137 | b0 + 138 | b1000001000000 & 139 | b1000001000000 * 140 | b111010000000 % 141 | b111010000000 ) 142 | 1$ 143 | #22 144 | 0$ 145 | #24 146 | b1 6 147 | 0" 148 | bz ! 149 | bz @ 150 | bz ' 151 | bz + 152 | bz & 153 | bz * 154 | bz % 155 | bz ) 156 | 1$ 157 | #26 158 | 0$ 159 | #28 160 | b1 6 161 | 1" 162 | b100010000000 ! 163 | b100010000000 @ 164 | b1 ' 165 | b1 + 166 | b11000000000 & 167 | b11000000000 * 168 | b111010000000 % 169 | b111010000000 ) 170 | 1$ 171 | #30 172 | 0$ 173 | #32 174 | b1 6 175 | 0" 176 | bz ! 177 | bz @ 178 | bz ' 179 | bz + 180 | bz & 181 | bz * 182 | bz % 183 | bz ) 184 | 1$ 185 | #34 186 | 0$ 187 | #36 188 | b1 6 189 | bx ! 190 | bx @ 191 | b10 ' 192 | b10 + 193 | b11000000000 & 194 | b11000000000 * 195 | b111010000000 % 196 | b111010000000 ) 197 | 1$ 198 | #38 199 | 0$ 200 | #40 201 | b10101110000000000000000 , 202 | b10101110000000000000000 K 203 | b10101110000000000000000 8 204 | b11000000000 5 205 | b11000000000 J 206 | b111010000000 4 207 | b111010000000 I 208 | b10 6 209 | b1 3 210 | 1$ 211 | #42 212 | 0$ 213 | #44 214 | b0 , 215 | b0 K 216 | b0 9 217 | b0 4 218 | b0 I 219 | b11 6 220 | b10 3 221 | 1$ 222 | #46 223 | 0$ 224 | #48 225 | b0 : 226 | b0 5 227 | b0 J 228 | b111010000000 4 229 | b111010000000 I 230 | b100 6 231 | b11 3 232 | 1$ 233 | #50 234 | 0$ 235 | #52 236 | b0 ; 237 | b0 4 238 | b0 I 239 | b101 6 240 | b100 3 241 | 1$ 242 | #54 243 | 0$ 244 | #56 245 | 1" 246 | b1010111000000 ! 247 | b1010111000000 @ 248 | 1= 249 | b10101110000000000000000 < 250 | b0 6 251 | b101 3 252 | 1$ 253 | #58 254 | 0$ 255 | #60 256 | bx , 257 | bx K 258 | bz ; 259 | bz : 260 | bz 9 261 | bz 8 262 | bz 5 263 | bz J 264 | bz 4 265 | bz I 266 | 0= 267 | b1 6 268 | b0 3 269 | 0" 270 | bz ! 271 | bz @ 272 | bz ' 273 | bz + 274 | bz & 275 | bz * 276 | bz % 277 | bz ) 278 | 1$ 279 | #62 280 | 0$ 281 | #64 282 | b1 6 283 | bx ! 284 | bx @ 285 | b11 ' 286 | b11 + 287 | b11100110000000000 % 288 | b11100110000000000 ) 289 | 1$ 290 | #66 291 | 0$ 292 | #68 293 | 1D 294 | b10 7 295 | b1 E 296 | 1$ 297 | #70 298 | 0$ 299 | #72 300 | 0D 301 | b10 7 302 | b0 ? 303 | b0 1 304 | b111001100000000000000 H 305 | b1111111111111111111111111111111111 F 306 | b10 E 307 | b0 0 308 | b1110011000000000000 G 309 | b0 > 310 | 1C 311 | 1$ 312 | #74 313 | 0$ 314 | #76 315 | b11100110000000000000000 H 316 | b111001100000000000000 G 317 | b1 2 318 | 1$ 319 | #78 320 | 0$ 321 | #80 322 | b1110011000000000000000000 H 323 | b11100110000000000000000 G 324 | b10 2 325 | 1$ 326 | #82 327 | 0$ 328 | #84 329 | b111001100000000000000000000 H 330 | b1110011000000000000000000 G 331 | b11 2 332 | 1$ 333 | #86 334 | 0$ 335 | #88 336 | b11100110000000000000000000000 H 337 | b111001100000000000000000000 G 338 | b100 2 339 | 1$ 340 | #90 341 | 0$ 342 | #92 343 | b1110011000000000000000000000000 H 344 | b11100110000000000000000000000 G 345 | b101 2 346 | 1$ 347 | #94 348 | 0$ 349 | #96 350 | b1 1 351 | b11001100000000000000000000000000 H 352 | b1110011000000000000000000000000 G 353 | b110 2 354 | 1$ 355 | #98 356 | 0$ 357 | #100 358 | b1 ? 359 | b11 1 360 | b110000000000000000000000000000 H 361 | b0 F 362 | b1 0 363 | b11001100000000000000000000000000 G 364 | b111 2 365 | 1$ 366 | #102 367 | 0$ 368 | #104 369 | b10 ? 370 | b1100 1 371 | b11000000000000000000000000000000 H 372 | b1111111111111111111111111111111110 F 373 | b1 > 374 | b11 0 375 | b110000000000000000000000000000 G 376 | b1000 2 377 | 1$ 378 | #106 379 | 0$ 380 | #108 381 | b101 ? 382 | b1111 1 383 | b0 H 384 | b11 F 385 | b10 > 386 | b1100 0 387 | b11000000000000000000000000000000 G 388 | b1001 2 389 | 1$ 390 | #110 391 | 0$ 392 | #112 393 | b1010 ? 394 | b111100 1 395 | b1111111111111111111111111111111010 F 396 | b101 > 397 | b1111 0 398 | b0 G 399 | b1010 2 400 | 1$ 401 | #114 402 | 0$ 403 | #116 404 | b10101 ? 405 | b1001100 1 406 | b10011 F 407 | b1010 > 408 | b111100 0 409 | b1011 2 410 | 1$ 411 | #118 412 | 0$ 413 | #120 414 | b101010 ? 415 | b100110000 1 416 | b1111111111111111111111111111110111 F 417 | b10101 > 418 | b1001100 0 419 | b1100 2 420 | 1$ 421 | #122 422 | 0$ 423 | #124 424 | b1010101 ? 425 | b1000011100 1 426 | b10000111 F 427 | b101010 > 428 | b100110000 0 429 | b1101 2 430 | 1$ 431 | #126 432 | 0$ 433 | #128 434 | b10101011 ? 435 | b1100011100 1 436 | b11000111 F 437 | b1010101 > 438 | b1000011100 0 439 | b1110 2 440 | 1$ 441 | #130 442 | 0$ 443 | #132 444 | b101010111 ? 445 | b110111100 1 446 | b1101111 F 447 | b10101011 > 448 | b1100011100 0 449 | b1111 2 450 | 1$ 451 | #134 452 | 0$ 453 | #136 454 | b1010101110 ? 455 | b11011110000 1 456 | b1111111111111111111111110001011111 F 457 | b101010111 > 458 | b110111100 0 459 | b10000 2 460 | 1$ 461 | #138 462 | 0$ 463 | #140 464 | b10101011100 ? 465 | b1101111000000 1 466 | b1111111111111111111111110000110111 F 467 | b1010101110 > 468 | b11011110000 0 469 | b10001 2 470 | 1$ 471 | #142 472 | 0$ 473 | #144 474 | b101010111001 ? 475 | b1100100111100 1 476 | b11001001111 F 477 | b10101011100 > 478 | b1101111000000 0 479 | b10010 2 480 | 1$ 481 | #146 482 | 0$ 483 | #148 484 | b1010101110010 ? 485 | b110010011110000 1 486 | b1111111111111111111110111001010111 F 487 | b101010111001 > 488 | b1100100111100 0 489 | b10011 2 490 | 1$ 491 | #150 492 | 0$ 493 | #152 494 | b10101011100101 ? 495 | b11110010011100 1 496 | b111100100111 F 497 | b1010101110010 > 498 | b110010011110000 0 499 | b10100 2 500 | 1$ 501 | #154 502 | 0$ 503 | #156 504 | 1" 505 | b10101011100101 ! 506 | b10101011100101 @ 507 | b10101011100101 A 508 | 1B 509 | 0C 510 | 1$ 511 | #158 512 | 0$ 513 | #160 514 | 1$ 515 | #162 516 | 0$ 517 | #164 518 | 1$ 519 | #166 520 | 0$ 521 | #168 522 | b1 7 523 | b1 6 524 | 0B 525 | b0 E 526 | 0" 527 | bz ! 528 | bz @ 529 | bz ' 530 | bz + 531 | bz % 532 | bz ) 533 | 1$ 534 | #170 535 | 0$ 536 | #172 537 | 1$ 538 | #174 539 | 0$ 540 | #176 541 | 1$ 542 | #178 543 | 0$ 544 | #180 545 | 1$ 546 | #182 547 | 0$ 548 | #184 549 | 1$ 550 | #186 551 | 0$ 552 | #188 553 | 1$ 554 | #190 555 | 0$ 556 | #192 557 | 1$ 558 | #194 559 | 0$ 560 | #196 561 | 1$ 562 | #198 563 | 0$ 564 | #200 565 | 1$ 566 | #202 567 | 0$ 568 | #204 569 | 1$ 570 | #206 571 | 0$ 572 | #208 573 | $dumpoff 574 | bx K 575 | bx J 576 | bx I 577 | bx H 578 | bx G 579 | bx F 580 | bx E 581 | xD 582 | xC 583 | xB 584 | bx A 585 | bx @ 586 | bx ? 587 | bx > 588 | x= 589 | bx < 590 | bx ; 591 | bx : 592 | bx 9 593 | bx 8 594 | bx 7 595 | bx 6 596 | bx 5 597 | bx 4 598 | bx 3 599 | bx 2 600 | bx 1 601 | bx 0 602 | bx , 603 | bx + 604 | bx * 605 | bx ) 606 | x( 607 | bx ' 608 | bx & 609 | bx % 610 | x$ 611 | x" 612 | bx ! 613 | $end 614 | 1$ 615 | -------------------------------------------------------------------------------- /Fixed_Point_Unit.vvp: -------------------------------------------------------------------------------- 1 | #! /c/Source/iverilog-install/bin/vvp 2 | :ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision - 9; 5 | :vpi_module "C:\iverilog\lib\ivl\system.vpi"; 6 | :vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi"; 7 | :vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; 8 | :vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; 9 | :vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; 10 | S_0000026cc2231840 .scope module, "Fixed_Point_Unit_Testbench" "Fixed_Point_Unit_Testbench" 2 5; 11 | .timescale -9 -9; 12 | P_0000026cc222be20 .param/l "CLK_PERIOD" 0 2 11, +C4<00000000000000000000000000000100>; 13 | v0000026cc22bbca0_0 .var "clk", 0 0; 14 | v0000026cc22bac60_0 .net "fpu_ready", 0 0, v0000026cc22bb160_0; 1 drivers 15 | v0000026cc22ba6c0_0 .net "fpu_result", 31 0, v0000026cc22bb660_0; 1 drivers 16 | v0000026cc22bb340_0 .var "operand_1", 31 0; 17 | v0000026cc22bb3e0_0 .var "operand_2", 31 0; 18 | v0000026cc22bb480_0 .var "operation", 1 0; 19 | v0000026cc22bb0c0_0 .var "reset", 0 0; 20 | E_0000026cc222c760 .event posedge, v0000026cc22bb160_0; 21 | S_0000026cc22567b0 .scope module, "uut" "Fixed_Point_Unit" 2 32, 3 4 0, S_0000026cc2231840; 22 | .timescale -9 -9; 23 | .port_info 0 /INPUT 1 "clk"; 24 | .port_info 1 /INPUT 1 "reset"; 25 | .port_info 2 /INPUT 32 "operand_1"; 26 | .port_info 3 /INPUT 32 "operand_2"; 27 | .port_info 4 /INPUT 2 "operation"; 28 | .port_info 5 /OUTPUT 32 "result"; 29 | .port_info 6 /OUTPUT 1 "ready"; 30 | P_0000026cc21ebf10 .param/l "FBITS" 0 3 7, +C4<00000000000000000000000000001010>; 31 | P_0000026cc21ebf48 .param/l "ITER" 1 3 76, +C4<00000000000000000000000000010101>; 32 | P_0000026cc21ebf80 .param/l "WIDTH" 0 3 6, +C4<00000000000000000000000000100000>; 33 | v0000026cc22332c0_0 .var "ac", 33 0; 34 | v0000026cc2233900_0 .var "ac_next", 33 0; 35 | v0000026cc22334a0_0 .net "clk", 0 0, v0000026cc22bbca0_0; 1 drivers 36 | v0000026cc22339a0_0 .var "i", 4 0; 37 | v0000026cc2233a40_0 .var "multiplication_stage", 2 0; 38 | v0000026cc2233ae0_0 .var "multiplierCircuitInput1", 15 0; 39 | v0000026cc2233360_0 .var "multiplierCircuitInput2", 15 0; 40 | v0000026cc2233d60_0 .net "multiplierCircuitResult", 31 0, v0000026cc2233400_0; 1 drivers 41 | v0000026cc2233e00_0 .var "next_multiplication_stage", 2 0; 42 | v0000026cc22330e0_0 .var "next_square_root_stage", 1 0; 43 | v0000026cc2233c20_0 .net "operand_1", 31 0, v0000026cc22bb340_0; 1 drivers 44 | v0000026cc2233b80_0 .net "operand_2", 31 0, v0000026cc22bb3e0_0; 1 drivers 45 | v0000026cc2233540_0 .net "operation", 1 0, v0000026cc22bb480_0; 1 drivers 46 | v0000026cc2233f40_0 .var "partialProduct1", 31 0; 47 | v0000026cc2233180_0 .var "partialProduct2", 31 0; 48 | v0000026cc2233cc0_0 .var "partialProduct3", 31 0; 49 | v0000026cc2233720_0 .var "partialProduct4", 31 0; 50 | v0000026cc2233040_0 .var "product", 63 0; 51 | v0000026cc22335e0_0 .var "product_ready", 0 0; 52 | v0000026cc2233860_0 .var "q", 31 0; 53 | v0000026cc22337c0_0 .var "q_next", 31 0; 54 | v0000026cc22bb160_0 .var "ready", 0 0; 55 | v0000026cc22bbc00_0 .net "reset", 0 0, v0000026cc22bb0c0_0; 1 drivers 56 | v0000026cc22bb660_0 .var "result", 31 0; 57 | v0000026cc22baa80_0 .var "root", 31 0; 58 | v0000026cc22baee0_0 .var "root_ready", 0 0; 59 | v0000026cc22bb8e0_0 .var "sqrt_busy", 0 0; 60 | v0000026cc22bab20_0 .var "sqrt_start", 0 0; 61 | v0000026cc22bb700_0 .var "square_root_stage", 1 0; 62 | v0000026cc22bb520_0 .var "test_res", 33 0; 63 | v0000026cc22bb7a0_0 .var "x", 31 0; 64 | v0000026cc22bb840_0 .var "x_next", 31 0; 65 | E_0000026cc222c1a0/0 .event anyedge, v0000026cc2233a40_0, v0000026cc2233c20_0, v0000026cc2233b80_0, v0000026cc2233400_0; 66 | E_0000026cc222c1a0/1 .event anyedge, v0000026cc2233f40_0, v0000026cc2233180_0, v0000026cc2233cc0_0, v0000026cc2233720_0; 67 | E_0000026cc222c1a0 .event/or E_0000026cc222c1a0/0, E_0000026cc222c1a0/1; 68 | E_0000026cc222be60 .event posedge, v0000026cc22334a0_0; 69 | E_0000026cc222c1e0 .event anyedge, v0000026cc22332c0_0, v0000026cc2233860_0, v0000026cc22bb520_0, v0000026cc22bb7a0_0; 70 | E_0000026cc222bb60 .event anyedge, v0000026cc22bb700_0; 71 | E_0000026cc222c420 .event posedge, v0000026cc22bbc00_0; 72 | E_0000026cc222b9e0/0 .event anyedge, v0000026cc2233540_0, v0000026cc2233c20_0, v0000026cc2233b80_0, v0000026cc2233040_0; 73 | E_0000026cc222b9e0/1 .event anyedge, v0000026cc22335e0_0, v0000026cc22baa80_0, v0000026cc22baee0_0; 74 | E_0000026cc222b9e0 .event/or E_0000026cc222b9e0/0, E_0000026cc222b9e0/1; 75 | S_0000026cc2256940 .scope module, "multiplier_circuit" "Multiplier" 3 136, 4 3 0, S_0000026cc22567b0; 76 | .timescale -9 -9; 77 | .port_info 0 /INPUT 16 "operand_1"; 78 | .port_info 1 /INPUT 16 "operand_2"; 79 | .port_info 2 /OUTPUT 32 "product"; 80 | v0000026cc2233220_0 .net "operand_1", 15 0, v0000026cc2233ae0_0; 1 drivers 81 | v0000026cc2233680_0 .net "operand_2", 15 0, v0000026cc2233360_0; 1 drivers 82 | v0000026cc2233400_0 .var "product", 31 0; 83 | E_0000026cc222c5a0 .event anyedge, v0000026cc2233220_0, v0000026cc2233680_0; 84 | .scope S_0000026cc2256940; 85 | T_0 ; 86 | %wait E_0000026cc222c5a0; 87 | %load/vec4 v0000026cc2233220_0; 88 | %pad/u 32; 89 | %load/vec4 v0000026cc2233680_0; 90 | %pad/u 32; 91 | %mul; 92 | %assign/vec4 v0000026cc2233400_0, 0; 93 | %jmp T_0; 94 | .thread T_0, $push; 95 | .scope S_0000026cc22567b0; 96 | T_1 ; 97 | %pushi/vec4 0, 0, 5; 98 | %store/vec4 v0000026cc22339a0_0, 0, 5; 99 | %end; 100 | .thread T_1; 101 | .scope S_0000026cc22567b0; 102 | T_2 ; 103 | %wait E_0000026cc222b9e0; 104 | %load/vec4 v0000026cc2233540_0; 105 | %dup/vec4; 106 | %pushi/vec4 0, 0, 2; 107 | %cmp/u; 108 | %jmp/1 T_2.0, 6; 109 | %dup/vec4; 110 | %pushi/vec4 1, 0, 2; 111 | %cmp/u; 112 | %jmp/1 T_2.1, 6; 113 | %dup/vec4; 114 | %pushi/vec4 2, 0, 2; 115 | %cmp/u; 116 | %jmp/1 T_2.2, 6; 117 | %dup/vec4; 118 | %pushi/vec4 3, 0, 2; 119 | %cmp/u; 120 | %jmp/1 T_2.3, 6; 121 | %pushi/vec4 0, 4294967295, 32; 122 | %store/vec4 v0000026cc22bb660_0, 0, 32; 123 | %pushi/vec4 0, 0, 1; 124 | %store/vec4 v0000026cc22bb160_0, 0, 1; 125 | %jmp T_2.5; 126 | T_2.0 ; 127 | %load/vec4 v0000026cc2233c20_0; 128 | %load/vec4 v0000026cc2233b80_0; 129 | %add; 130 | %store/vec4 v0000026cc22bb660_0, 0, 32; 131 | %pushi/vec4 1, 0, 1; 132 | %store/vec4 v0000026cc22bb160_0, 0, 1; 133 | %jmp T_2.5; 134 | T_2.1 ; 135 | %load/vec4 v0000026cc2233c20_0; 136 | %load/vec4 v0000026cc2233b80_0; 137 | %sub; 138 | %store/vec4 v0000026cc22bb660_0, 0, 32; 139 | %pushi/vec4 1, 0, 1; 140 | %store/vec4 v0000026cc22bb160_0, 0, 1; 141 | %jmp T_2.5; 142 | T_2.2 ; 143 | %load/vec4 v0000026cc2233040_0; 144 | %parti/s 32, 10, 5; 145 | %store/vec4 v0000026cc22bb660_0, 0, 32; 146 | %load/vec4 v0000026cc22335e0_0; 147 | %store/vec4 v0000026cc22bb160_0, 0, 1; 148 | %jmp T_2.5; 149 | T_2.3 ; 150 | %load/vec4 v0000026cc22baa80_0; 151 | %store/vec4 v0000026cc22bb660_0, 0, 32; 152 | %load/vec4 v0000026cc22baee0_0; 153 | %store/vec4 v0000026cc22bb160_0, 0, 1; 154 | %jmp T_2.5; 155 | T_2.5 ; 156 | %pop/vec4 1; 157 | %jmp T_2; 158 | .thread T_2, $push; 159 | .scope S_0000026cc22567b0; 160 | T_3 ; 161 | %wait E_0000026cc222c420; 162 | %load/vec4 v0000026cc22bbc00_0; 163 | %flag_set/vec4 8; 164 | %jmp/0xz T_3.0, 8; 165 | %pushi/vec4 0, 0, 1; 166 | %store/vec4 v0000026cc22bb160_0, 0, 1; 167 | %jmp T_3.1; 168 | T_3.0 ; 169 | %pushi/vec4 0, 1, 1; 170 | %store/vec4 v0000026cc22bb160_0, 0, 1; 171 | T_3.1 ; 172 | %jmp T_3; 173 | .thread T_3; 174 | .scope S_0000026cc22567b0; 175 | T_4 ; 176 | %wait E_0000026cc222be60; 177 | %load/vec4 v0000026cc2233540_0; 178 | %cmpi/e 3, 0, 2; 179 | %jmp/0xz T_4.0, 4; 180 | %load/vec4 v0000026cc22330e0_0; 181 | %assign/vec4 v0000026cc22bb700_0, 0; 182 | %jmp T_4.1; 183 | T_4.0 ; 184 | %pushi/vec4 0, 0, 2; 185 | %assign/vec4 v0000026cc22bb700_0, 0; 186 | %pushi/vec4 0, 0, 1; 187 | %assign/vec4 v0000026cc22baee0_0, 0; 188 | T_4.1 ; 189 | %jmp T_4; 190 | .thread T_4; 191 | .scope S_0000026cc22567b0; 192 | T_5 ; 193 | %wait E_0000026cc222bb60; 194 | %pushi/vec4 0, 3, 2; 195 | %assign/vec4 v0000026cc22330e0_0, 0; 196 | %load/vec4 v0000026cc22bb700_0; 197 | %dup/vec4; 198 | %pushi/vec4 0, 0, 2; 199 | %cmp/u; 200 | %jmp/1 T_5.0, 6; 201 | %dup/vec4; 202 | %pushi/vec4 1, 0, 2; 203 | %cmp/u; 204 | %jmp/1 T_5.1, 6; 205 | %dup/vec4; 206 | %pushi/vec4 2, 0, 2; 207 | %cmp/u; 208 | %jmp/1 T_5.2, 6; 209 | %jmp T_5.3; 210 | T_5.0 ; 211 | %pushi/vec4 0, 0, 1; 212 | %assign/vec4 v0000026cc22bab20_0, 0; 213 | %pushi/vec4 1, 0, 2; 214 | %assign/vec4 v0000026cc22330e0_0, 0; 215 | %jmp T_5.3; 216 | T_5.1 ; 217 | %pushi/vec4 1, 0, 1; 218 | %assign/vec4 v0000026cc22bab20_0, 0; 219 | %pushi/vec4 2, 0, 2; 220 | %assign/vec4 v0000026cc22330e0_0, 0; 221 | %jmp T_5.3; 222 | T_5.2 ; 223 | %pushi/vec4 0, 0, 1; 224 | %assign/vec4 v0000026cc22bab20_0, 0; 225 | %pushi/vec4 2, 0, 2; 226 | %assign/vec4 v0000026cc22330e0_0, 0; 227 | %jmp T_5.3; 228 | T_5.3 ; 229 | %pop/vec4 1; 230 | %jmp T_5; 231 | .thread T_5, $push; 232 | .scope S_0000026cc22567b0; 233 | T_6 ; 234 | %wait E_0000026cc222c1e0; 235 | %load/vec4 v0000026cc22332c0_0; 236 | %load/vec4 v0000026cc2233860_0; 237 | %concati/vec4 1, 0, 2; 238 | %sub; 239 | %store/vec4 v0000026cc22bb520_0, 0, 34; 240 | %load/vec4 v0000026cc22bb520_0; 241 | %parti/s 1, 33, 7; 242 | %pad/u 32; 243 | %cmpi/e 0, 0, 32; 244 | %jmp/0xz T_6.0, 4; 245 | %load/vec4 v0000026cc22bb520_0; 246 | %parti/s 32, 0, 2; 247 | %load/vec4 v0000026cc22bb7a0_0; 248 | %concat/vec4; draw_concat_vec4 249 | %concati/vec4 0, 0, 2; 250 | %split/vec4 32; 251 | %store/vec4 v0000026cc22bb840_0, 0, 32; 252 | %store/vec4 v0000026cc2233900_0, 0, 34; 253 | %load/vec4 v0000026cc2233860_0; 254 | %parti/s 31, 0, 2; 255 | %concati/vec4 1, 0, 1; 256 | %store/vec4 v0000026cc22337c0_0, 0, 32; 257 | %jmp T_6.1; 258 | T_6.0 ; 259 | %load/vec4 v0000026cc22332c0_0; 260 | %parti/s 32, 0, 2; 261 | %load/vec4 v0000026cc22bb7a0_0; 262 | %concat/vec4; draw_concat_vec4 263 | %concati/vec4 0, 0, 2; 264 | %split/vec4 32; 265 | %store/vec4 v0000026cc22bb840_0, 0, 32; 266 | %store/vec4 v0000026cc2233900_0, 0, 34; 267 | %load/vec4 v0000026cc2233860_0; 268 | %ix/load 4, 1, 0; 269 | %flag_set/imm 4, 0; 270 | %shiftl 4; 271 | %store/vec4 v0000026cc22337c0_0, 0, 32; 272 | T_6.1 ; 273 | %jmp T_6; 274 | .thread T_6, $push; 275 | .scope S_0000026cc22567b0; 276 | T_7 ; 277 | %wait E_0000026cc222be60; 278 | %load/vec4 v0000026cc22bab20_0; 279 | %flag_set/vec4 8; 280 | %jmp/0xz T_7.0, 8; 281 | %pushi/vec4 1, 0, 1; 282 | %assign/vec4 v0000026cc22bb8e0_0, 0; 283 | %pushi/vec4 0, 0, 1; 284 | %assign/vec4 v0000026cc22baee0_0, 0; 285 | %pushi/vec4 0, 0, 5; 286 | %assign/vec4 v0000026cc22339a0_0, 0; 287 | %pushi/vec4 0, 0, 32; 288 | %assign/vec4 v0000026cc2233860_0, 0; 289 | %pushi/vec4 0, 0, 32; 290 | %load/vec4 v0000026cc2233c20_0; 291 | %concat/vec4; draw_concat_vec4 292 | %concati/vec4 0, 0, 2; 293 | %split/vec4 32; 294 | %assign/vec4 v0000026cc22bb7a0_0, 0; 295 | %assign/vec4 v0000026cc22332c0_0, 0; 296 | %jmp T_7.1; 297 | T_7.0 ; 298 | %load/vec4 v0000026cc22bb8e0_0; 299 | %flag_set/vec4 8; 300 | %jmp/0xz T_7.2, 8; 301 | %load/vec4 v0000026cc22339a0_0; 302 | %pad/u 32; 303 | %cmpi/e 20, 0, 32; 304 | %jmp/0xz T_7.4, 4; 305 | %pushi/vec4 0, 0, 1; 306 | %assign/vec4 v0000026cc22bb8e0_0, 0; 307 | %pushi/vec4 1, 0, 1; 308 | %assign/vec4 v0000026cc22baee0_0, 0; 309 | %load/vec4 v0000026cc22337c0_0; 310 | %assign/vec4 v0000026cc22baa80_0, 0; 311 | %jmp T_7.5; 312 | T_7.4 ; 313 | %load/vec4 v0000026cc22339a0_0; 314 | %addi 1, 0, 5; 315 | %assign/vec4 v0000026cc22339a0_0, 0; 316 | %load/vec4 v0000026cc22bb840_0; 317 | %assign/vec4 v0000026cc22bb7a0_0, 0; 318 | %load/vec4 v0000026cc2233900_0; 319 | %assign/vec4 v0000026cc22332c0_0, 0; 320 | %load/vec4 v0000026cc22337c0_0; 321 | %assign/vec4 v0000026cc2233860_0, 0; 322 | %pushi/vec4 0, 0, 1; 323 | %assign/vec4 v0000026cc22baee0_0, 0; 324 | T_7.5 ; 325 | T_7.2 ; 326 | T_7.1 ; 327 | %jmp T_7; 328 | .thread T_7; 329 | .scope S_0000026cc22567b0; 330 | T_8 ; 331 | %wait E_0000026cc222be60; 332 | %load/vec4 v0000026cc2233540_0; 333 | %cmpi/e 2, 0, 2; 334 | %jmp/0xz T_8.0, 4; 335 | %load/vec4 v0000026cc2233e00_0; 336 | %assign/vec4 v0000026cc2233a40_0, 0; 337 | %jmp T_8.1; 338 | T_8.0 ; 339 | %pushi/vec4 0, 0, 3; 340 | %assign/vec4 v0000026cc2233a40_0, 0; 341 | T_8.1 ; 342 | %jmp T_8; 343 | .thread T_8; 344 | .scope S_0000026cc22567b0; 345 | T_9 ; 346 | %wait E_0000026cc222c1a0; 347 | %pushi/vec4 0, 7, 3; 348 | %assign/vec4 v0000026cc2233e00_0, 0; 349 | %load/vec4 v0000026cc2233a40_0; 350 | %dup/vec4; 351 | %pushi/vec4 0, 0, 3; 352 | %cmp/u; 353 | %jmp/1 T_9.0, 6; 354 | %dup/vec4; 355 | %pushi/vec4 1, 0, 3; 356 | %cmp/u; 357 | %jmp/1 T_9.1, 6; 358 | %dup/vec4; 359 | %pushi/vec4 2, 0, 3; 360 | %cmp/u; 361 | %jmp/1 T_9.2, 6; 362 | %dup/vec4; 363 | %pushi/vec4 3, 0, 3; 364 | %cmp/u; 365 | %jmp/1 T_9.3, 6; 366 | %dup/vec4; 367 | %pushi/vec4 4, 0, 3; 368 | %cmp/u; 369 | %jmp/1 T_9.4, 6; 370 | %dup/vec4; 371 | %pushi/vec4 5, 0, 3; 372 | %cmp/u; 373 | %jmp/1 T_9.5, 6; 374 | %pushi/vec4 0, 0, 3; 375 | %assign/vec4 v0000026cc2233e00_0, 0; 376 | %jmp T_9.7; 377 | T_9.0 ; 378 | %pushi/vec4 0, 0, 1; 379 | %assign/vec4 v0000026cc22335e0_0, 0; 380 | %pushi/vec4 0, 65535, 16; 381 | %assign/vec4 v0000026cc2233ae0_0, 0; 382 | %pushi/vec4 0, 65535, 16; 383 | %assign/vec4 v0000026cc2233360_0, 0; 384 | %pushi/vec4 0, 4294967295, 32; 385 | %assign/vec4 v0000026cc2233f40_0, 0; 386 | %pushi/vec4 0, 4294967295, 32; 387 | %assign/vec4 v0000026cc2233180_0, 0; 388 | %pushi/vec4 0, 4294967295, 32; 389 | %assign/vec4 v0000026cc2233cc0_0, 0; 390 | %pushi/vec4 0, 4294967295, 32; 391 | %assign/vec4 v0000026cc2233720_0, 0; 392 | %pushi/vec4 1, 0, 3; 393 | %assign/vec4 v0000026cc2233e00_0, 0; 394 | %jmp T_9.7; 395 | T_9.1 ; 396 | %load/vec4 v0000026cc2233c20_0; 397 | %parti/s 16, 0, 2; 398 | %assign/vec4 v0000026cc2233ae0_0, 0; 399 | %load/vec4 v0000026cc2233b80_0; 400 | %parti/s 16, 0, 2; 401 | %assign/vec4 v0000026cc2233360_0, 0; 402 | %load/vec4 v0000026cc2233d60_0; 403 | %assign/vec4 v0000026cc2233f40_0, 0; 404 | %pushi/vec4 2, 0, 3; 405 | %assign/vec4 v0000026cc2233e00_0, 0; 406 | %jmp T_9.7; 407 | T_9.2 ; 408 | %load/vec4 v0000026cc2233c20_0; 409 | %parti/s 16, 16, 6; 410 | %assign/vec4 v0000026cc2233ae0_0, 0; 411 | %load/vec4 v0000026cc2233b80_0; 412 | %parti/s 16, 0, 2; 413 | %assign/vec4 v0000026cc2233360_0, 0; 414 | %load/vec4 v0000026cc2233d60_0; 415 | %assign/vec4 v0000026cc2233180_0, 0; 416 | %pushi/vec4 3, 0, 3; 417 | %assign/vec4 v0000026cc2233e00_0, 0; 418 | %jmp T_9.7; 419 | T_9.3 ; 420 | %load/vec4 v0000026cc2233c20_0; 421 | %parti/s 16, 0, 2; 422 | %assign/vec4 v0000026cc2233ae0_0, 0; 423 | %load/vec4 v0000026cc2233b80_0; 424 | %parti/s 16, 16, 6; 425 | %assign/vec4 v0000026cc2233360_0, 0; 426 | %load/vec4 v0000026cc2233d60_0; 427 | %assign/vec4 v0000026cc2233cc0_0, 0; 428 | %pushi/vec4 4, 0, 3; 429 | %assign/vec4 v0000026cc2233e00_0, 0; 430 | %jmp T_9.7; 431 | T_9.4 ; 432 | %load/vec4 v0000026cc2233c20_0; 433 | %parti/s 16, 16, 6; 434 | %assign/vec4 v0000026cc2233ae0_0, 0; 435 | %load/vec4 v0000026cc2233b80_0; 436 | %parti/s 16, 16, 6; 437 | %assign/vec4 v0000026cc2233360_0, 0; 438 | %load/vec4 v0000026cc2233d60_0; 439 | %assign/vec4 v0000026cc2233720_0, 0; 440 | %pushi/vec4 5, 0, 3; 441 | %assign/vec4 v0000026cc2233e00_0, 0; 442 | %jmp T_9.7; 443 | T_9.5 ; 444 | %load/vec4 v0000026cc2233f40_0; 445 | %pad/u 64; 446 | %load/vec4 v0000026cc2233180_0; 447 | %pad/u 64; 448 | %ix/load 4, 16, 0; 449 | %flag_set/imm 4, 0; 450 | %shiftl 4; 451 | %add; 452 | %load/vec4 v0000026cc2233cc0_0; 453 | %pad/u 64; 454 | %ix/load 4, 16, 0; 455 | %flag_set/imm 4, 0; 456 | %shiftl 4; 457 | %add; 458 | %load/vec4 v0000026cc2233720_0; 459 | %pad/u 64; 460 | %ix/load 4, 32, 0; 461 | %flag_set/imm 4, 0; 462 | %shiftl 4; 463 | %add; 464 | %assign/vec4 v0000026cc2233040_0, 0; 465 | %pushi/vec4 0, 0, 3; 466 | %assign/vec4 v0000026cc2233e00_0, 0; 467 | %pushi/vec4 1, 0, 1; 468 | %assign/vec4 v0000026cc22335e0_0, 0; 469 | %jmp T_9.7; 470 | T_9.7 ; 471 | %pop/vec4 1; 472 | %jmp T_9; 473 | .thread T_9, $push; 474 | .scope S_0000026cc2231840; 475 | T_10 ; 476 | %pushi/vec4 1, 0, 1; 477 | %store/vec4 v0000026cc22bbca0_0, 0, 1; 478 | %pushi/vec4 1, 0, 1; 479 | %store/vec4 v0000026cc22bb0c0_0, 0, 1; 480 | %end; 481 | .thread T_10; 482 | .scope S_0000026cc2231840; 483 | T_11 ; 484 | T_11.0 ; 485 | %delay 2, 0; 486 | %load/vec4 v0000026cc22bbca0_0; 487 | %inv; 488 | %store/vec4 v0000026cc22bbca0_0, 0, 1; 489 | %jmp T_11.0; 490 | %end; 491 | .thread T_11; 492 | .scope S_0000026cc2231840; 493 | T_12 ; 494 | %vpi_call 2 48 "$dumpfile", "Fixed_Point_Unit.vcd" {0 0 0}; 495 | %vpi_call 2 49 "$dumpvars", 32'sb00000000000000000000000000000000, S_0000026cc2231840 {0 0 0}; 496 | %pushi/vec4 3, 0, 32; 497 | T_12.0 %dup/vec4; 498 | %pushi/vec4 0, 0, 32; 499 | %cmp/s; 500 | %jmp/1xz T_12.1, 5; 501 | %jmp/1 T_12.1, 4; 502 | %pushi/vec4 1, 0, 32; 503 | %sub; 504 | %wait E_0000026cc222be60; 505 | %jmp T_12.0; 506 | T_12.1 ; 507 | %pop/vec4 1; 508 | %pushi/vec4 0, 0, 1; 509 | %assign/vec4 v0000026cc22bb0c0_0, 0; 510 | %pushi/vec4 2, 0, 32; 511 | T_12.2 %dup/vec4; 512 | %pushi/vec4 0, 0, 32; 513 | %cmp/s; 514 | %jmp/1xz T_12.3, 5; 515 | %jmp/1 T_12.3, 4; 516 | %pushi/vec4 1, 0, 32; 517 | %sub; 518 | %wait E_0000026cc222be60; 519 | %jmp T_12.2; 520 | T_12.3 ; 521 | %pop/vec4 1; 522 | %pushi/vec4 3712, 0, 32; 523 | %store/vec4 v0000026cc22bb340_0, 0, 32; 524 | %pushi/vec4 4160, 0, 32; 525 | %store/vec4 v0000026cc22bb3e0_0, 0, 32; 526 | %pushi/vec4 0, 0, 2; 527 | %store/vec4 v0000026cc22bb480_0, 0, 2; 528 | %wait E_0000026cc222be60; 529 | %pushi/vec4 0, 4294967295, 32; 530 | %store/vec4 v0000026cc22bb340_0, 0, 32; 531 | %pushi/vec4 0, 4294967295, 32; 532 | %store/vec4 v0000026cc22bb3e0_0, 0, 32; 533 | %pushi/vec4 0, 3, 2; 534 | %store/vec4 v0000026cc22bb480_0, 0, 2; 535 | %wait E_0000026cc222be60; 536 | %pushi/vec4 3712, 0, 32; 537 | %store/vec4 v0000026cc22bb340_0, 0, 32; 538 | %pushi/vec4 1536, 0, 32; 539 | %store/vec4 v0000026cc22bb3e0_0, 0, 32; 540 | %pushi/vec4 1, 0, 2; 541 | %store/vec4 v0000026cc22bb480_0, 0, 2; 542 | %wait E_0000026cc222be60; 543 | %pushi/vec4 0, 4294967295, 32; 544 | %store/vec4 v0000026cc22bb340_0, 0, 32; 545 | %pushi/vec4 0, 4294967295, 32; 546 | %store/vec4 v0000026cc22bb3e0_0, 0, 32; 547 | %pushi/vec4 0, 3, 2; 548 | %store/vec4 v0000026cc22bb480_0, 0, 2; 549 | %wait E_0000026cc222be60; 550 | %pushi/vec4 3712, 0, 32; 551 | %store/vec4 v0000026cc22bb340_0, 0, 32; 552 | %pushi/vec4 1536, 0, 32; 553 | %store/vec4 v0000026cc22bb3e0_0, 0, 32; 554 | %pushi/vec4 2, 0, 2; 555 | %store/vec4 v0000026cc22bb480_0, 0, 2; 556 | %wait E_0000026cc222c760; 557 | %wait E_0000026cc222be60; 558 | %pushi/vec4 0, 4294967295, 32; 559 | %store/vec4 v0000026cc22bb340_0, 0, 32; 560 | %pushi/vec4 0, 4294967295, 32; 561 | %store/vec4 v0000026cc22bb3e0_0, 0, 32; 562 | %pushi/vec4 0, 3, 2; 563 | %store/vec4 v0000026cc22bb480_0, 0, 2; 564 | %wait E_0000026cc222be60; 565 | %pushi/vec4 117760, 0, 32; 566 | %store/vec4 v0000026cc22bb340_0, 0, 32; 567 | %pushi/vec4 3, 0, 2; 568 | %store/vec4 v0000026cc22bb480_0, 0, 2; 569 | %wait E_0000026cc222c760; 570 | %pushi/vec4 3, 0, 32; 571 | T_12.4 %dup/vec4; 572 | %pushi/vec4 0, 0, 32; 573 | %cmp/s; 574 | %jmp/1xz T_12.5, 5; 575 | %jmp/1 T_12.5, 4; 576 | %pushi/vec4 1, 0, 32; 577 | %sub; 578 | %wait E_0000026cc222be60; 579 | %jmp T_12.4; 580 | T_12.5 ; 581 | %pop/vec4 1; 582 | %pushi/vec4 0, 4294967295, 32; 583 | %store/vec4 v0000026cc22bb340_0, 0, 32; 584 | %pushi/vec4 0, 4294967295, 32; 585 | %store/vec4 v0000026cc22bb3e0_0, 0, 32; 586 | %pushi/vec4 0, 3, 2; 587 | %store/vec4 v0000026cc22bb480_0, 0, 2; 588 | %pushi/vec4 10, 0, 32; 589 | T_12.6 %dup/vec4; 590 | %pushi/vec4 0, 0, 32; 591 | %cmp/s; 592 | %jmp/1xz T_12.7, 5; 593 | %jmp/1 T_12.7, 4; 594 | %pushi/vec4 1, 0, 32; 595 | %sub; 596 | %wait E_0000026cc222be60; 597 | %jmp T_12.6; 598 | T_12.7 ; 599 | %pop/vec4 1; 600 | %vpi_call 2 95 "$dumpoff" {0 0 0}; 601 | %vpi_call 2 96 "$finish" {0 0 0}; 602 | %end; 603 | .thread T_12; 604 | # The file index is used to find the file name in the following table. 605 | :file_names 5; 606 | "N/A"; 607 | ""; 608 | ".\Fixed_Point_Unit_Testbench.v"; 609 | "./Fixed_Point_Unit.v"; 610 | "./Multiplier.v"; 611 | -------------------------------------------------------------------------------- /Fixed_Point_Unit_Testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 1 ns 2 | 3 | `include "Fixed_Point_Unit.v" 4 | 5 | module Fixed_Point_Unit_Testbench; 6 | 7 | ////////////////////// 8 | // Clock Generation // 9 | ////////////////////// 10 | parameter CLK_PERIOD = 4; 11 | reg clk = 1'b1; 12 | initial begin forever #(CLK_PERIOD/2) clk = ~clk; end 13 | reg reset = `ENABLE; 14 | 15 | ///////////////// 16 | // FPU Signals // 17 | ///////////////// 18 | 19 | reg [31 : 0] operand_1; 20 | reg [31 : 0] operand_2; 21 | reg [ 1 : 0] operation; 22 | 23 | wire [31 : 0] fpu_result; 24 | wire fpu_ready; 25 | 26 | Fixed_Point_Unit 27 | #( 28 | .WIDTH(32), 29 | .FBITS(10) 30 | ) 31 | uut 32 | ( 33 | .clk(clk), 34 | .reset(reset), 35 | 36 | .operand_1(operand_1), 37 | .operand_2(operand_2), 38 | 39 | .operation(operation), 40 | 41 | .result(fpu_result), 42 | .ready(fpu_ready) 43 | ); 44 | 45 | initial 46 | begin 47 | $dumpfile("Fixed_Point_Unit.vcd"); 48 | $dumpvars(0, Fixed_Point_Unit_Testbench); 49 | repeat (3) @(posedge clk); 50 | reset <= `DISABLE; 51 | 52 | repeat (2) @(posedge clk); 53 | operand_1 = 32'b0000_0011_1010_0000_00; 54 | operand_2 = 32'b0000_0100_0001_0000_00; 55 | operation = `FPU_ADD; 56 | 57 | repeat (1) @(posedge clk); 58 | operand_1 = 'bz; 59 | operand_2 = 'bz; 60 | operation = 'bz; 61 | 62 | repeat (1) @(posedge clk); 63 | operand_1 = 32'b0000_0011_1010_0000_00; 64 | operand_2 = 32'b0000_0001_1000_0000_00; 65 | operation = `FPU_SUB; 66 | 67 | repeat (1) @(posedge clk); 68 | operand_1 = 'bz; 69 | operand_2 = 'bz; 70 | operation = 'bz; 71 | 72 | repeat (1) @(posedge clk); 73 | operand_1 = 32'b0000_0011_1010_0000_00; 74 | operand_2 = 32'b0000_0001_1000_0000_00; 75 | operation = `FPU_MUL; 76 | 77 | repeat (1) @(posedge fpu_ready); 78 | repeat (1) @(posedge clk); 79 | operand_1 = 'bz; 80 | operand_2 = 'bz; 81 | operation = 'bz; 82 | 83 | repeat (1) @(posedge clk); 84 | operand_1 = 'b11100110000000000; 85 | operation = `FPU_SQRT; 86 | 87 | repeat (1) @(posedge fpu_ready); 88 | repeat (3) @(posedge clk); 89 | operand_1 = 'bz; 90 | operand_2 = 'bz; 91 | operation = 'bz; 92 | 93 | repeat (10) @(posedge clk); 94 | $dumpoff; 95 | $finish; 96 | end 97 | endmodule -------------------------------------------------------------------------------- /Images/Datapath_1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/17fc2dbf9701825f7623881393df2a6082481dd3/Images/Datapath_1.png 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-------------------------------------------------------------------------------- /Immediate_Generator.v: -------------------------------------------------------------------------------- 1 | // LUMOS - Light Utilization with Multicycle Operational Stages 2 | // A RISC-V RV32I Processor Core 3 | 4 | // Description: LUMOS Core Immediate Generator Unit Module 5 | // Copyright 2024 Iran University of Science and Technology. 6 | 7 | // Permission to use, copy, modify, and/or distribute this software for any 8 | // purpose with or without fee is hereby granted, provided that the above 9 | // copyright notice and this permission notice appear in all copies. 10 | 11 | `include "Defines.vh" 12 | 13 | module Immediate_Generator 14 | ( 15 | input wire [31 : 0] instruction, 16 | input wire [ 2 : 0] instruction_type, 17 | 18 | output reg [31 : 0] immediate 19 | ); 20 | always @(*) 21 | begin 22 | case (instruction_type) 23 | `I_TYPE : immediate = { {21{instruction[31]}}, instruction[30 : 20] }; 24 | `S_TYPE : immediate = { {21{instruction[31]}}, instruction[30 : 25], instruction[11 : 7] }; 25 | `B_TYPE : immediate = { {20{instruction[31]}}, instruction[7], instruction[30 : 25], instruction[11 : 8], 1'b0 }; 26 | `U_TYPE : immediate = { instruction[31 : 12], {12{1'b0}} }; 27 | `J_TYPE : immediate = { {12{instruction[31]}}, instruction[19 : 12], instruction[20], instruction[30 : 21], 1'b0 }; 28 | default : immediate = { 32{1'bz} }; 29 | endcase 30 | end 31 | endmodule -------------------------------------------------------------------------------- /LUMOS.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.100 (w)1999-2019 BSI 3 | [*] Wed Jun 05 21:32:40 2024 4 | [*] 5 | [dumpfile] "D:\GitHub\IUST-Computer-Organization\LUMOS\LUMOS.vcd" 6 | [dumpfile_mtime] "Wed Jun 05 21:31:51 2024" 7 | [dumpfile_size] 965539 8 | [savefile] "D:\GitHub\IUST-Computer-Organization\LUMOS\LUMOS.gtkw" 9 | [timestart] 23288 10 | [size] 1920 1009 11 | [pos] -1 -1 12 | *-6.945527 23807 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] LUMOS_Testbench. 14 | [treeopen] LUMOS_Testbench.uut. 15 | [sst_width] 197 16 | [signals_width] 441 17 | [sst_expanded] 1 18 | [sst_vpaned_height] 297 19 | @28 20 | LUMOS_Testbench.uut.clk 21 | LUMOS_Testbench.uut.reset 22 | @200 23 | - 24 | ----Controller State-- 25 | @24 26 | LUMOS_Testbench.uut.state[4:0] 27 | LUMOS_Testbench.uut.nextState[4:0] 28 | @200 29 | - 30 | @28 31 | LUMOS_Testbench.uut.irWrite 32 | @22 33 | LUMOS_Testbench.uut.ir[31:0] 34 | @200 35 | - 36 | @28 37 | LUMOS_Testbench.uut.pcWrite 38 | @22 39 | LUMOS_Testbench.uut.pc[31:0] 40 | @200 41 | - 42 | ----Memory Signals--- 43 | @28 44 | LUMOS_Testbench.uut.instructionOrData 45 | @22 46 | LUMOS_Testbench.uut.memoryAddress[31:0] 47 | LUMOS_Testbench.uut.memoryData[31:0] 48 | @28 49 | LUMOS_Testbench.uut.memoryReadWrite 50 | LUMOS_Testbench.uut.memoryEnable 51 | LUMOS_Testbench.uut.memoryReady 52 | @200 53 | - 54 | ----Decode--- 55 | @22 56 | LUMOS_Testbench.uut.opcode[6:0] 57 | @28 58 | LUMOS_Testbench.uut.funct3[2:0] 59 | @22 60 | LUMOS_Testbench.uut.funct7[6:0] 61 | LUMOS_Testbench.uut.immediate[31:0] 62 | @200 63 | - 64 | ----Integer Register File--- 65 | @22 66 | LUMOS_Testbench.uut.readData1[31:0] 67 | LUMOS_Testbench.uut.RS1[31:0] 68 | LUMOS_Testbench.uut.readData2[31:0] 69 | LUMOS_Testbench.uut.RS2[31:0] 70 | @200 71 | - 72 | @28 73 | LUMOS_Testbench.uut.registerWriteEnable 74 | LUMOS_Testbench.uut.registerWriteSource[1:0] 75 | @200 76 | - 77 | ----Fixed Point Register File--- 78 | @40000024 79 | [fpshift_count] 10 80 | LUMOS_Testbench.uut.fixedPointReadData1[31:0] 81 | [fpshift_count] 10 82 | LUMOS_Testbench.uut.FRS1[31:0] 83 | @40000025 84 | [fpshift_count] 10 85 | LUMOS_Testbench.uut.fixedPointReadData2[31:0] 86 | @40000024 87 | [fpshift_count] 10 88 | LUMOS_Testbench.uut.writeData[31:0] 89 | [fpshift_count] 10 90 | LUMOS_Testbench.uut.FRS2[31:0] 91 | @200 92 | - 93 | @28 94 | LUMOS_Testbench.uut.fixedPointRegisterWriteEnable 95 | LUMOS_Testbench.uut.fixedPointRegisterWriteSource[1:0] 96 | @22 97 | LUMOS_Testbench.uut.fixedPointWriteData[31:0] 98 | @200 99 | - 100 | ----FPU Signals--- 101 | @28 102 | LUMOS_Testbench.uut.fpuOperation[1:0] 103 | LUMOS_Testbench.uut.fpuReady 104 | @40000024 105 | [fpshift_count] 10 106 | LUMOS_Testbench.uut.fpuResult[31:0] 107 | [fpshift_count] 10 108 | LUMOS_Testbench.uut.fpuResultRegister[31:0] 109 | @200 110 | - 111 | ----ALU Signals--- 112 | @420 113 | LUMOS_Testbench.uut.aluOperand1[31:0] 114 | @c00420 115 | LUMOS_Testbench.uut.aluOperand2[31:0] 116 | @28 117 | (0)LUMOS_Testbench.uut.aluOperand2[31:0] 118 | (1)LUMOS_Testbench.uut.aluOperand2[31:0] 119 | (2)LUMOS_Testbench.uut.aluOperand2[31:0] 120 | (3)LUMOS_Testbench.uut.aluOperand2[31:0] 121 | (4)LUMOS_Testbench.uut.aluOperand2[31:0] 122 | (5)LUMOS_Testbench.uut.aluOperand2[31:0] 123 | (6)LUMOS_Testbench.uut.aluOperand2[31:0] 124 | (7)LUMOS_Testbench.uut.aluOperand2[31:0] 125 | (8)LUMOS_Testbench.uut.aluOperand2[31:0] 126 | (9)LUMOS_Testbench.uut.aluOperand2[31:0] 127 | (10)LUMOS_Testbench.uut.aluOperand2[31:0] 128 | (11)LUMOS_Testbench.uut.aluOperand2[31:0] 129 | (12)LUMOS_Testbench.uut.aluOperand2[31:0] 130 | (13)LUMOS_Testbench.uut.aluOperand2[31:0] 131 | (14)LUMOS_Testbench.uut.aluOperand2[31:0] 132 | (15)LUMOS_Testbench.uut.aluOperand2[31:0] 133 | (16)LUMOS_Testbench.uut.aluOperand2[31:0] 134 | (17)LUMOS_Testbench.uut.aluOperand2[31:0] 135 | (18)LUMOS_Testbench.uut.aluOperand2[31:0] 136 | (19)LUMOS_Testbench.uut.aluOperand2[31:0] 137 | (20)LUMOS_Testbench.uut.aluOperand2[31:0] 138 | (21)LUMOS_Testbench.uut.aluOperand2[31:0] 139 | (22)LUMOS_Testbench.uut.aluOperand2[31:0] 140 | (23)LUMOS_Testbench.uut.aluOperand2[31:0] 141 | (24)LUMOS_Testbench.uut.aluOperand2[31:0] 142 | (25)LUMOS_Testbench.uut.aluOperand2[31:0] 143 | (26)LUMOS_Testbench.uut.aluOperand2[31:0] 144 | (27)LUMOS_Testbench.uut.aluOperand2[31:0] 145 | (28)LUMOS_Testbench.uut.aluOperand2[31:0] 146 | (29)LUMOS_Testbench.uut.aluOperand2[31:0] 147 | (30)LUMOS_Testbench.uut.aluOperand2[31:0] 148 | (31)LUMOS_Testbench.uut.aluOperand2[31:0] 149 | @1401200 150 | -group_end 151 | @22 152 | LUMOS_Testbench.uut.aluOperation[3:0] 153 | @200 154 | - 155 | @420 156 | LUMOS_Testbench.uut.aluResult[31:0] 157 | @22 158 | LUMOS_Testbench.uut.aluResultRegister[31:0] 159 | @28 160 | LUMOS_Testbench.uut.aluZeroRegister 161 | LUMOS_Testbench.uut.aluZeroRegister 162 | @200 163 | - 164 | ----Integer Registers--- 165 | @22 166 | LUMOS_Testbench.x0_zero[31:0] 167 | LUMOS_Testbench.x1_ra[31:0] 168 | LUMOS_Testbench.x2_sp[31:0] 169 | LUMOS_Testbench.x3_gp[31:0] 170 | LUMOS_Testbench.x4_tp[31:0] 171 | LUMOS_Testbench.x5_t0[31:0] 172 | LUMOS_Testbench.x6_t1[31:0] 173 | LUMOS_Testbench.x7_t2[31:0] 174 | LUMOS_Testbench.x8_s0[31:0] 175 | LUMOS_Testbench.x9_s1[31:0] 176 | LUMOS_Testbench.x10_a0[31:0] 177 | LUMOS_Testbench.x11_a1[31:0] 178 | LUMOS_Testbench.x12_a2[31:0] 179 | LUMOS_Testbench.x13_a3[31:0] 180 | LUMOS_Testbench.x14_a4[31:0] 181 | LUMOS_Testbench.x15_a5[31:0] 182 | LUMOS_Testbench.x16_a6[31:0] 183 | LUMOS_Testbench.x17_a7[31:0] 184 | LUMOS_Testbench.x18_s2[31:0] 185 | LUMOS_Testbench.x19_s3[31:0] 186 | LUMOS_Testbench.x20_s4[31:0] 187 | LUMOS_Testbench.x21_s5[31:0] 188 | LUMOS_Testbench.x22_s6[31:0] 189 | LUMOS_Testbench.x23_s7[31:0] 190 | LUMOS_Testbench.x24_s8[31:0] 191 | LUMOS_Testbench.x25_s9[31:0] 192 | LUMOS_Testbench.x26_s10[31:0] 193 | LUMOS_Testbench.x27_s11[31:0] 194 | LUMOS_Testbench.x28_t3[31:0] 195 | LUMOS_Testbench.x29_t4[31:0] 196 | LUMOS_Testbench.x30_t5[31:0] 197 | LUMOS_Testbench.x31_t6[31:0] 198 | @200 199 | - 200 | ----Fixed Point Registers--- 201 | @40000024 202 | [fpshift_count] 10 203 | LUMOS_Testbench.f0[31:0] 204 | [fpshift_count] 10 205 | LUMOS_Testbench.f1[31:0] 206 | [fpshift_count] 10 207 | LUMOS_Testbench.f2[31:0] 208 | [fpshift_count] 10 209 | LUMOS_Testbench.f3[31:0] 210 | [fpshift_count] 10 211 | LUMOS_Testbench.f4[31:0] 212 | [fpshift_count] 10 213 | LUMOS_Testbench.f5[31:0] 214 | [fpshift_count] 10 215 | LUMOS_Testbench.f6[31:0] 216 | [fpshift_count] 10 217 | LUMOS_Testbench.f7[31:0] 218 | [fpshift_count] 10 219 | LUMOS_Testbench.f8[31:0] 220 | [fpshift_count] 10 221 | LUMOS_Testbench.f9[31:0] 222 | [fpshift_count] 10 223 | LUMOS_Testbench.f10[31:0] 224 | [fpshift_count] 10 225 | LUMOS_Testbench.f11[31:0] 226 | [fpshift_count] 10 227 | LUMOS_Testbench.f12[31:0] 228 | [fpshift_count] 10 229 | LUMOS_Testbench.f13[31:0] 230 | [fpshift_count] 10 231 | LUMOS_Testbench.f14[31:0] 232 | [fpshift_count] 10 233 | LUMOS_Testbench.f15[31:0] 234 | [fpshift_count] 10 235 | LUMOS_Testbench.f16[31:0] 236 | [fpshift_count] 10 237 | LUMOS_Testbench.f17[31:0] 238 | [fpshift_count] 10 239 | LUMOS_Testbench.f18[31:0] 240 | [fpshift_count] 10 241 | LUMOS_Testbench.f19[31:0] 242 | [fpshift_count] 10 243 | LUMOS_Testbench.f20[31:0] 244 | [fpshift_count] 10 245 | LUMOS_Testbench.f21[31:0] 246 | [fpshift_count] 10 247 | LUMOS_Testbench.f22[31:0] 248 | [fpshift_count] 10 249 | LUMOS_Testbench.f23[31:0] 250 | [fpshift_count] 10 251 | LUMOS_Testbench.f24[31:0] 252 | [fpshift_count] 10 253 | LUMOS_Testbench.f25[31:0] 254 | [fpshift_count] 10 255 | LUMOS_Testbench.f26[31:0] 256 | [fpshift_count] 10 257 | LUMOS_Testbench.f27[31:0] 258 | [fpshift_count] 10 259 | LUMOS_Testbench.f28[31:0] 260 | [fpshift_count] 10 261 | LUMOS_Testbench.f29[31:0] 262 | [fpshift_count] 10 263 | LUMOS_Testbench.f30[31:0] 264 | [fpshift_count] 10 265 | LUMOS_Testbench.f31[31:0] 266 | [pattern_trace] 1 267 | [pattern_trace] 0 268 | -------------------------------------------------------------------------------- /LUMOS.v: -------------------------------------------------------------------------------- 1 | // LUMOS - Light Utilization with Multicycle Operational Stages 2 | // A RISC-V RV32I Processor Core 3 | 4 | // Description: LUMOS Core Top-level Module 5 | // Copyright 2024 Iran University of Science and Technology. 6 | 7 | // Permission to use, copy, modify, and/or distribute this software for any 8 | // purpose with or without fee is hereby granted, provided that the above 9 | // copyright notice and this permission notice appear in all copies. 10 | 11 | `include "Defines.vh" 12 | `include "Register_File.v" 13 | `include "Arithmetic_Logic_Unit.v" 14 | `include "Immediate_Generator.v" 15 | `include "Fixed_Point_Unit.v" 16 | 17 | module LUMOS 18 | #( 19 | parameter RESET_ADDRESS = 32'h0000_0000 20 | ) 21 | ( 22 | input clk, 23 | input reset, 24 | output reg trap, 25 | 26 | inout [31 : 0] memoryData, 27 | input memoryReady, 28 | output reg memoryEnable, 29 | output reg memoryReadWrite, 30 | output reg [31 : 0] memoryAddress 31 | ); 32 | 33 | //////////////// 34 | // Controller // 35 | //////////////// 36 | 37 | reg [4 : 0] state; 38 | reg [4 : 0] nextState; 39 | 40 | reg [6 : 0] opcode; 41 | reg [2 : 0] funct3; 42 | reg [6 : 0] funct7; 43 | 44 | always @(*) 45 | begin 46 | opcode = ir[ 6 : 0]; 47 | funct3 = ir[14 : 12]; 48 | funct7 = ir[31 : 25]; 49 | end 50 | 51 | reg pcWrite; 52 | reg irWrite; 53 | reg memoryDataRegisterWrite; 54 | 55 | reg instructionOrData; 56 | 57 | reg [1 : 0] registerWriteSource; 58 | reg [1 : 0] fixedPointRegisterWriteSource; 59 | 60 | reg registerWriteEnable; 61 | reg fixedPointRegisterWriteEnable; 62 | 63 | reg [2 : 0] instructionType; 64 | 65 | reg [1 : 0] aluSrcA; 66 | reg [1 : 0] aluSrcB; 67 | reg [3 : 0] aluOperation; 68 | 69 | reg [1 : 0] fpuOperation; 70 | 71 | always @(posedge clk or posedge reset) 72 | begin 73 | if(reset) 74 | state <= `RESET; 75 | else 76 | state <= nextState; 77 | end 78 | 79 | always @(*) 80 | begin 81 | nextState <= 'bz; 82 | 83 | memoryReadWrite <= 'bz; 84 | pcWrite <= 'bz; 85 | irWrite <= 'bz; 86 | 87 | aluOperation <= 'bz; 88 | aluSrcA <= 'bz; 89 | aluSrcB <= 'bz; 90 | 91 | registerWriteSource <= 'bz; 92 | registerWriteEnable <= 'bz; 93 | 94 | fixedPointRegisterWriteSource <= 'bz; 95 | fixedPointRegisterWriteEnable <= 'bz; 96 | 97 | instructionOrData <= 'bz; 98 | 99 | case (state) 100 | `RESET : 101 | begin 102 | nextState <= `FETCH_BEGIN; 103 | memoryEnable <= `DISABLE; 104 | end 105 | 106 | `FETCH_BEGIN : 107 | begin 108 | memoryEnable <= `ENABLE; 109 | memoryReadWrite <= `READ; 110 | instructionOrData <= `INSTRUCTION; 111 | nextState <= `FETCH_WAIT; 112 | end 113 | 114 | `FETCH_WAIT : 115 | begin 116 | memoryEnable <= `ENABLE; 117 | memoryReadWrite <= `READ; 118 | instructionOrData <= `INSTRUCTION; 119 | 120 | if (memoryReady) 121 | begin 122 | irWrite <= `ENABLE; 123 | nextState <= `FETCH_DONE; 124 | end 125 | else 126 | nextState <= `FETCH_WAIT; 127 | end 128 | 129 | `FETCH_DONE : 130 | begin 131 | memoryEnable <= `DISABLE; 132 | aluSrcA <= `PC; 133 | aluSrcB <= `FOUR; 134 | aluOperation <= `ALU_ADD; 135 | pcWrite <= `ENABLE; 136 | nextState <= `DECODE; 137 | end 138 | 139 | `DECODE : 140 | begin 141 | if (opcode == `SYSTEM) 142 | trap <= `ENABLE; 143 | // else 144 | // trap <= `DISABLE; 145 | 146 | case (opcode) 147 | `OP : instructionType <= `R_TYPE; 148 | `OP_FP : instructionType <= `R_TYPE; 149 | 150 | `LOAD : instructionType <= `I_TYPE; 151 | `LOAD_FP : instructionType <= `I_TYPE; 152 | `OP_IMM : instructionType <= `I_TYPE; 153 | `OP_IMM_32 : instructionType <= `I_TYPE; 154 | `JALR : instructionType <= `I_TYPE; 155 | `SYSTEM : instructionType <= `I_TYPE; 156 | 157 | `STORE : instructionType <= `S_TYPE; 158 | `STORE_FP : instructionType <= `S_TYPE; 159 | 160 | `BRANCH : instructionType <= `B_TYPE; 161 | 162 | `AUIPC : instructionType <= `U_TYPE; 163 | `LUI : instructionType <= `U_TYPE; 164 | 165 | `JAL : instructionType <= `J_TYPE; 166 | default : instructionType <= 3'bz; 167 | endcase 168 | nextState <= `EXECUTE; 169 | end 170 | 171 | `EXECUTE : 172 | begin 173 | case (opcode) 174 | `OP : 175 | begin 176 | aluSrcA <= `RS1; 177 | aluSrcB <= `RS2; 178 | case ({funct7, funct3}) 179 | {`ADD, `ADDSUB} : 180 | begin 181 | aluOperation <= `ALU_ADD; 182 | registerWriteSource <= `ALU; 183 | registerWriteEnable <= `ENABLE; 184 | end 185 | 186 | {`SUB, `ADDSUB} : 187 | begin 188 | aluOperation <= `ALU_SUB; 189 | registerWriteSource <= `ALU; 190 | registerWriteEnable <= `ENABLE; 191 | end 192 | 193 | {7'b0, `SLL} : 194 | begin 195 | aluOperation <= `ALU_SLL; 196 | registerWriteSource <= `ALU; 197 | registerWriteEnable <= `ENABLE; 198 | end 199 | 200 | {7'b0, `SLT} : 201 | begin 202 | aluOperation <= `ALU_SLT; 203 | registerWriteSource <= `ALU; 204 | registerWriteEnable <= `ENABLE; 205 | end 206 | 207 | {7'b0, `SLTU} : 208 | begin 209 | aluOperation <= `ALU_SLTU; 210 | registerWriteSource <= `ALU; 211 | registerWriteEnable <= `ENABLE; 212 | end 213 | 214 | {7'b0, `XOR} : 215 | begin 216 | aluOperation <= `ALU_XOR; 217 | registerWriteSource <= `ALU; 218 | registerWriteEnable <= `ENABLE; 219 | end 220 | 221 | {`LOGICAL, `SR} : 222 | begin 223 | aluOperation <= `ALU_SRL; 224 | registerWriteSource <= `ALU; 225 | registerWriteEnable <= `ENABLE; 226 | end 227 | 228 | {`ARITHMETIC, `SR} : 229 | begin 230 | aluOperation <= `ALU_SRA; 231 | registerWriteSource <= `ALU; 232 | registerWriteEnable <= `ENABLE; 233 | end 234 | 235 | {7'b0, `OR} : 236 | begin 237 | aluOperation <= `ALU_OR; 238 | registerWriteSource <= `ALU; 239 | registerWriteEnable <= `ENABLE; 240 | end 241 | 242 | {7'b0, `AND} : 243 | begin 244 | aluOperation <= `ALU_AND; 245 | registerWriteSource <= `ALU; 246 | registerWriteEnable <= `ENABLE; 247 | end 248 | endcase 249 | nextState <= `FETCH_BEGIN; 250 | end 251 | 252 | `OP_IMM : 253 | begin 254 | aluSrcA <= `RS1; 255 | aluSrcB <= `IMMEDIATE; 256 | 257 | case (funct3) 258 | `ADDI : 259 | begin 260 | aluOperation <= `ALU_ADD; 261 | registerWriteSource <= `ALU; 262 | registerWriteEnable <= `ENABLE; 263 | end 264 | 265 | `SLTI : 266 | begin 267 | aluOperation <= `ALU_SLT; 268 | registerWriteSource <= `ALU; 269 | registerWriteEnable <= `ENABLE; 270 | end 271 | 272 | `SLTIU : 273 | begin 274 | aluOperation <= `ALU_SLTU; 275 | registerWriteSource <= `ALU; 276 | registerWriteEnable <= `ENABLE; 277 | end 278 | 279 | `XORI : 280 | begin 281 | aluOperation <= `ALU_XOR; 282 | registerWriteSource <= `ALU; 283 | registerWriteEnable <= `ENABLE; 284 | end 285 | 286 | `ORI : 287 | begin 288 | aluOperation <= `ALU_OR; 289 | registerWriteSource <= `ALU; 290 | registerWriteEnable <= `ENABLE; 291 | end 292 | 293 | `ANDI : 294 | begin 295 | aluOperation <= `ALU_AND; 296 | registerWriteSource <= `ALU; 297 | registerWriteEnable <= `ENABLE; 298 | end 299 | 300 | `SLLI : 301 | begin 302 | aluOperation <= `ALU_SLL; 303 | registerWriteSource <= `ALU; 304 | registerWriteEnable <= `ENABLE; 305 | end 306 | 307 | `SRI : 308 | begin 309 | case (funct7) 310 | `LOGICAL : 311 | begin 312 | aluOperation <= `ALU_SRL; 313 | registerWriteSource <= `ALU; 314 | registerWriteEnable <= `ENABLE; 315 | end 316 | 317 | `ARITHMETIC : 318 | begin 319 | aluOperation <= `ALU_SRA; 320 | registerWriteSource <= `ALU; 321 | registerWriteEnable <= `ENABLE; 322 | end 323 | endcase 324 | end 325 | endcase 326 | 327 | nextState <= `FETCH_BEGIN; 328 | end 329 | 330 | `OP_FP : 331 | begin 332 | case (funct7) 333 | `FADD : fpuOperation <= `FPU_ADD; 334 | `FSUB : fpuOperation <= `FPU_SUB; 335 | `FMUL : fpuOperation <= `FPU_MUL; 336 | `FSQRT : fpuOperation <= `FPU_SQRT; 337 | endcase 338 | 339 | nextState <= `EXECUTE_FP; 340 | end 341 | 342 | `BRANCH : 343 | begin 344 | aluSrcA <= `RS1; 345 | aluSrcB <= `RS2; 346 | 347 | case ({funct3}) 348 | `BNE : 349 | begin 350 | aluOperation <= `ALU_SUB; 351 | end 352 | 353 | `BEQ : 354 | begin 355 | aluOperation <= `ALU_SUB; 356 | end 357 | 358 | `BLT : 359 | begin 360 | aluOperation <= `ALU_SUB; 361 | end 362 | endcase 363 | nextState <= `EXECUTE_BRANCH; 364 | end 365 | 366 | `AUIPC : 367 | begin 368 | aluSrcA <= `PC; 369 | aluSrcB <= `IMMEDIATE; 370 | aluOperation <= `ALU_ADD; 371 | registerWriteSource <= `ALU; 372 | registerWriteEnable <= `ENABLE; 373 | nextState <= `FETCH_BEGIN; 374 | end 375 | 376 | `JAL : 377 | begin 378 | registerWriteSource <= `NEXT_PC; 379 | registerWriteEnable <= `ENABLE; 380 | 381 | nextState <= `EXECUTE_JUMP; 382 | end 383 | 384 | `JALR : 385 | begin 386 | 387 | registerWriteSource <= `NEXT_PC; 388 | registerWriteEnable <= `ENABLE; 389 | 390 | nextState <= `EXECUTE_JUMP; 391 | end 392 | 393 | `LUI : 394 | begin 395 | aluSrcA <= `ZERO; 396 | aluSrcB <= `IMMEDIATE; 397 | aluOperation <= `ALU_ADD; 398 | registerWriteSource <= `ALU; 399 | registerWriteEnable <= `ENABLE; 400 | nextState <= `FETCH_BEGIN; 401 | end 402 | 403 | `LOAD : 404 | begin 405 | aluSrcA <= `RS1; 406 | aluSrcB <= `IMMEDIATE; 407 | aluOperation <= `ALU_ADD; 408 | nextState <= `MEMORY_READ_BEGIN; 409 | end 410 | 411 | `LOAD_FP : 412 | begin 413 | aluSrcA <= `RS1; 414 | aluSrcB <= `IMMEDIATE; 415 | aluOperation <= `ALU_ADD; 416 | nextState <= `MEMORY_READ_BEGIN; 417 | end 418 | 419 | `STORE : 420 | begin 421 | aluSrcA <= `RS1; 422 | aluSrcB <= `IMMEDIATE; 423 | aluOperation <= `ALU_ADD; 424 | 425 | memoryReadWrite <= `WRITE; 426 | memoryDataRegisterWrite <= `ENABLE; 427 | 428 | nextState <= `MEMORY_WRITE; 429 | end 430 | 431 | `STORE_FP : 432 | begin 433 | aluSrcA <= `RS1; 434 | aluSrcB <= `IMMEDIATE; 435 | aluOperation <= `ALU_ADD; 436 | 437 | memoryReadWrite <= `WRITE; 438 | memoryDataRegisterWrite <= `ENABLE; 439 | 440 | nextState <= `MEMORY_WRITE; 441 | end 442 | endcase 443 | end 444 | 445 | `EXECUTE_FP : 446 | begin 447 | if (!fpuReady) 448 | nextState <= `EXECUTE_FP; 449 | else 450 | begin 451 | fixedPointRegisterWriteSource <= `FPU; 452 | fixedPointRegisterWriteEnable <= `ENABLE; 453 | nextState <= `FETCH_BEGIN; 454 | end 455 | end 456 | 457 | `MEMORY_READ_BEGIN : 458 | begin 459 | memoryEnable <= `ENABLE; 460 | memoryReadWrite <= `READ; 461 | instructionOrData <= `DATA; 462 | 463 | aluSrcA <= `ALU_RESULT; 464 | aluSrcB <= `ZERO; 465 | aluOperation <= `ALU_ADD; 466 | 467 | nextState <= `MEMORY_READ_WAIT; 468 | end 469 | 470 | `MEMORY_READ_WAIT : 471 | begin 472 | memoryEnable <= `ENABLE; 473 | memoryReadWrite <= `READ; 474 | instructionOrData <= `DATA; 475 | 476 | aluSrcA <= `ALU_RESULT; 477 | aluSrcB <= `ZERO; 478 | aluOperation <= `ALU_ADD; 479 | 480 | 481 | if (memoryReady) 482 | begin 483 | memoryDataRegisterWrite <= `ENABLE; 484 | nextState <= `MEMORY_READ_DONE; 485 | end 486 | else 487 | nextState <= `MEMORY_READ_WAIT; 488 | end 489 | 490 | `MEMORY_READ_DONE : 491 | begin 492 | if (opcode == `LOAD) 493 | begin 494 | registerWriteSource <= `MEMORY; 495 | registerWriteEnable <= `ENABLE; 496 | end 497 | else if (opcode == `LOAD_FP) 498 | begin 499 | fixedPointRegisterWriteSource <= `MEMORY; 500 | fixedPointRegisterWriteEnable <= `ENABLE; 501 | end 502 | 503 | memoryEnable <= `DISABLE; 504 | nextState <= `FETCH_BEGIN; 505 | end 506 | 507 | `MEMORY_WRITE : 508 | begin 509 | memoryEnable <= `ENABLE; 510 | memoryReadWrite <= `WRITE; 511 | instructionOrData <= `DATA; 512 | 513 | nextState <= `FETCH_BEGIN; 514 | end 515 | 516 | `EXECUTE_BRANCH : 517 | begin 518 | case ({funct3}) 519 | `BNE : 520 | begin 521 | if (!aluZeroRegister) 522 | begin 523 | aluSrcA <= `PC; 524 | aluSrcB <= `IMMEDIATE; 525 | aluOperation <= `ALU_ADD; 526 | nextState <= `TAKE_BRANCH; 527 | end 528 | else 529 | nextState <= `FETCH_BEGIN; 530 | end 531 | 532 | `BEQ : 533 | begin 534 | if (aluZeroRegister) 535 | begin 536 | aluSrcA <= `PC; 537 | aluSrcB <= `IMMEDIATE; 538 | aluOperation <= `ALU_ADD; 539 | nextState <= `TAKE_BRANCH; 540 | end 541 | else 542 | nextState <= `FETCH_BEGIN; 543 | end 544 | 545 | `BLT : 546 | begin 547 | if (aluSignRegister) 548 | begin 549 | aluSrcA <= `PC; 550 | aluSrcB <= `IMMEDIATE; 551 | aluOperation <= `ALU_ADD; 552 | nextState <= `TAKE_BRANCH; 553 | end 554 | else 555 | nextState <= `FETCH_BEGIN; 556 | end 557 | endcase 558 | end 559 | 560 | `TAKE_BRANCH : 561 | begin 562 | aluSrcA <= `ALU_RESULT; 563 | aluSrcB <= `FOUR; 564 | aluOperation <= `ALU_SUB; 565 | pcWrite <= `ENABLE; 566 | nextState <= `FETCH_BEGIN; 567 | end 568 | 569 | `EXECUTE_JUMP : 570 | begin 571 | case (opcode) 572 | `JAL : 573 | begin 574 | aluSrcA <= `PC; 575 | aluSrcB <= `IMMEDIATE; 576 | aluOperation <= `ALU_ADD; 577 | pcWrite <= `ENABLE; 578 | nextState <= `FETCH_BEGIN; 579 | end 580 | `JALR : 581 | begin 582 | 583 | aluSrcA <= `RS1; 584 | aluSrcB <= `IMMEDIATE; 585 | aluOperation <= `ALU_ADD; 586 | pcWrite <= `ENABLE; 587 | nextState <= `FETCH_BEGIN; 588 | end 589 | endcase 590 | end 591 | endcase 592 | end 593 | 594 | ////////////// 595 | // Datapath // 596 | ////////////// 597 | 598 | // ------------------------ // 599 | // Program Counter Register // 600 | // ------------------------ // 601 | reg [31 : 0] pc; 602 | 603 | always @(posedge clk) 604 | begin 605 | if (reset) 606 | pc <= RESET_ADDRESS; 607 | else if (pcWrite) 608 | pc <= aluResult; 609 | end 610 | 611 | // -------------------- // 612 | // Instruction Register // 613 | // -------------------- // 614 | reg [31: 0] ir; 615 | always @(posedge clk) 616 | begin 617 | if (reset) 618 | ir <= 'bz; 619 | if (irWrite) 620 | ir <= memoryData; 621 | end 622 | 623 | // -------------------- // 624 | // Memory Data Register // 625 | // -------------------- // 626 | reg [31 : 0] memoryDataRegister; 627 | always @(posedge clk) 628 | begin 629 | if (memoryDataRegisterWrite && memoryReadWrite == `READ) 630 | memoryDataRegister <= memoryData; 631 | if (memoryDataRegisterWrite && memoryReadWrite == `WRITE && opcode == `STORE) 632 | memoryDataRegister <= RS2; 633 | if (memoryDataRegisterWrite && memoryReadWrite == `WRITE && opcode == `STORE_FP) 634 | memoryDataRegister <= FRS2; 635 | end 636 | 637 | assign memoryData = (memoryEnable == `ENABLE) ? 638 | (memoryReadWrite == `WRITE) ? memoryDataRegister : 'bz : 'bz; 639 | 640 | // ------------- // 641 | // Register File // 642 | // ------------- // 643 | wire [31 : 0] readData1; 644 | wire [31 : 0] readData2; 645 | reg [31 : 0] writeData; 646 | 647 | always @(*) 648 | begin 649 | case (registerWriteSource) 650 | `NEXT_PC : writeData <= pc; 651 | `MEMORY : writeData <= memoryDataRegister; 652 | `ALU : writeData <= aluResult; 653 | default : writeData <= 'bz; 654 | endcase 655 | end 656 | 657 | Register_File 658 | #( 659 | .WIDTH(32), 660 | .DEPTH(5) 661 | ) 662 | register_file 663 | ( 664 | .clk(clk), 665 | .reset(reset), 666 | 667 | .read_enable_1(1'b1), 668 | .read_enable_2(1'b1), 669 | .write_enable(registerWriteEnable && (ir[11 : 7] != 0)), 670 | 671 | .read_index_1(ir[19 : 15]), 672 | .read_index_2(ir[24 : 20]), 673 | .write_index(ir[11 : 7]), 674 | 675 | .write_data(writeData), 676 | 677 | .read_data_1(readData1), 678 | .read_data_2(readData2) 679 | ); 680 | 681 | // ------------------- // 682 | // RS1 & RS2 Registers // 683 | // ------------------- // 684 | reg [31 : 0] RS1; 685 | reg [31 : 0] RS2; 686 | 687 | always @(posedge clk) 688 | begin 689 | RS1 <= readData1; 690 | RS2 <= readData2; 691 | end 692 | 693 | // ------------------------- // 694 | // Fixed Point Register File // 695 | // ------------------------- // 696 | wire [31 : 0] fixedPointReadData1; 697 | wire [31 : 0] fixedPointReadData2; 698 | reg [31 : 0] fixedPointWriteData; 699 | 700 | always @(*) 701 | begin 702 | case (fixedPointRegisterWriteSource) 703 | `MEMORY : fixedPointWriteData <= memoryDataRegister; 704 | `FPU : fixedPointWriteData <= fpuResult; 705 | default : fixedPointWriteData <= 'bz; 706 | endcase 707 | end 708 | 709 | Register_File 710 | #( 711 | .WIDTH(32), 712 | .DEPTH(5) 713 | ) 714 | fixed_point_register_file 715 | ( 716 | .clk(clk), 717 | .reset(reset), 718 | 719 | .read_enable_1(1'b1), 720 | .read_enable_2(1'b1), 721 | .write_enable(fixedPointRegisterWriteEnable), 722 | 723 | .read_index_1(ir[19 : 15]), 724 | .read_index_2(ir[24 : 20]), 725 | .write_index(ir[11 : 7]), 726 | 727 | .write_data(fixedPointWriteData), 728 | 729 | .read_data_1(fixedPointReadData1), 730 | .read_data_2(fixedPointReadData2) 731 | ); 732 | 733 | // --------------------- // 734 | // FRS1 & FRS2 Registers // 735 | // --------------------- // 736 | reg [31 : 0] FRS1; 737 | reg [31 : 0] FRS2; 738 | 739 | always @(posedge clk) 740 | begin 741 | FRS1 <= fixedPointReadData1; 742 | FRS2 <= fixedPointReadData2; 743 | end 744 | 745 | // ------------------- // 746 | // Immediate Generator // 747 | // ------------------- // 748 | wire [31 : 0] immediate; 749 | 750 | Immediate_Generator immediate_generator 751 | ( 752 | .instruction(ir), 753 | .instruction_type(instructionType), 754 | .immediate(immediate) 755 | ); 756 | 757 | // --------------------- // 758 | // Arithmetic Logic Unit // 759 | // --------------------- // 760 | reg [31 : 0] aluOperand1; 761 | reg [31 : 0] aluOperand2; 762 | wire [31 : 0] aluResult; 763 | wire aluZero; 764 | wire aluSign; 765 | 766 | always @(*) 767 | begin 768 | case (aluSrcA) 769 | `PC : aluOperand1 <= pc; 770 | `RS1 : aluOperand1 <= RS1; 771 | `ALU_RESULT : aluOperand1 <= aluResultRegister; 772 | `ZERO : aluOperand1 <= 0; 773 | default : aluOperand1 <= 'bz; 774 | endcase 775 | 776 | case (aluSrcB) 777 | `RS2 : aluOperand2 <= RS2; 778 | `FOUR : aluOperand2 <= 32'd4; 779 | `IMMEDIATE : aluOperand2 <= immediate; 780 | `ZERO : aluOperand2 <= 0; 781 | default : aluOperand2 <= 'bz; 782 | endcase 783 | end 784 | 785 | Arithmetic_Logic_Unit arithmetic_logic_unit 786 | ( 787 | .operation(aluOperation), 788 | .operand_1(aluOperand1), 789 | .operand_2(aluOperand2), 790 | .result(aluResult), 791 | .zero(aluZero), 792 | .sign(aluSign) 793 | ); 794 | 795 | reg [31 : 0] aluResultRegister; 796 | reg aluZeroRegister; 797 | reg aluSignRegister; 798 | 799 | always @(posedge clk) 800 | begin 801 | aluResultRegister <= aluResult; 802 | aluZeroRegister <= aluZero; 803 | aluSignRegister <= aluSign; 804 | end 805 | 806 | // ----------------------- // 807 | // Memory Address Register // 808 | // ----------------------- // 809 | always @(*) 810 | begin 811 | case (instructionOrData) 812 | `INSTRUCTION : memoryAddress <= pc; 813 | `DATA : memoryAddress <= aluResultRegister; 814 | default : memoryAddress <= 'bz; 815 | endcase 816 | end 817 | 818 | // ---------------- // 819 | // Fixed Point Unit // 820 | // ---------------- // 821 | wire [31 : 0] fpuResult; 822 | reg [31 : 0] fpuResultRegister; 823 | 824 | wire fpuReady; 825 | 826 | Fixed_Point_Unit 827 | #( 828 | .WIDTH(32), 829 | .FBITS(10) 830 | ) 831 | fixed_point_unit 832 | ( 833 | .clk(clk), 834 | .reset(reset), 835 | 836 | .operand_1(FRS1), 837 | .operand_2(FRS2), 838 | 839 | .operation(fpuOperation), 840 | 841 | .result(fpuResult), 842 | .ready(fpuReady) 843 | ); 844 | 845 | always @(posedge clk) 846 | begin 847 | fpuResultRegister <= fpuResult; 848 | end 849 | 850 | always @(posedge reset or negedge fixedPointRegisterWriteEnable) fpuOperation <= 'bz; 851 | endmodule -------------------------------------------------------------------------------- /LUMOS_Testbench.v: -------------------------------------------------------------------------------- 1 | // LUMOS - Light Utilization with Multicycle Operational Stages 2 | // A RISC-V RV32I Processor Core 3 | 4 | // Description: LUMOS Core Testbench Module 5 | // Copyright 2024 Iran University of Science and Technology. 6 | 7 | // Permission to use, copy, modify, and/or distribute this software for any 8 | // purpose with or without fee is hereby granted, provided that the above 9 | // copyright notice and this permission notice appear in all copies. 10 | 11 | `timescale 1 ns / 1 ns 12 | 13 | `include "Defines.vh" 14 | `include "LUMOS.v" 15 | 16 | `ifndef FIRMWARE 17 | `define FIRMWARE "Firmware\\Firmware.hex" 18 | `endif /*FIRMWARE*/ 19 | 20 | `ifndef MEMORY_ACCESS_TIME 21 | `define MEMORY_ACCESS_TIME #14 22 | `endif /*FIRMWARE*/ 23 | 24 | 25 | module LUMOS_Testbench; 26 | 27 | ///////////////////////////// 28 | // Multiplier Verification // 29 | ///////////////////////////// 30 | reg [ 7 : 0] test_operand_1; 31 | reg [ 7 : 0] test_operand_2; 32 | wire [15 : 0] test_product; 33 | 34 | Multiplier multiplier_8bit 35 | ( 36 | .operand_1(test_operand_1), 37 | .operand_2(test_operand_2), 38 | .product(test_product) 39 | ); 40 | 41 | integer i; 42 | integer j; 43 | 44 | initial 45 | begin 46 | for (i = 0; i < 255; i = i + 1) 47 | begin 48 | for (j = 0; j < 255; j = j + 1) 49 | begin 50 | test_operand_1 = i; 51 | test_operand_2 = j; 52 | #1; 53 | if (test_product != i * j) 54 | begin 55 | $display("\n\n\tMultiplier Verification Failed.\n\n"); 56 | $finish; 57 | end 58 | end 59 | end 60 | end 61 | 62 | ////////////////////// 63 | // Clock Generation // 64 | ////////////////////// 65 | parameter CLK_PERIOD = 4; 66 | reg clk = 1'b1; 67 | initial begin forever #(CLK_PERIOD/2) clk = ~clk; end 68 | initial #(8000 * CLK_PERIOD) $finish; 69 | reg reset = `ENABLE; 70 | 71 | wire trap; 72 | 73 | ////////////////////////////// 74 | // Memory Interface Signals // 75 | ////////////////////////////// 76 | wire [31 : 0] memoryData; 77 | reg [31 : 0] memoryData_reg; 78 | assign memoryData = memoryData_reg; 79 | 80 | wire [31 : 0] memoryAddress; 81 | wire memoryReadWrite; 82 | wire memoryEnable; 83 | reg memoryReady; 84 | 85 | LUMOS 86 | #( 87 | .RESET_ADDRESS(32'h0000_0000) 88 | ) 89 | uut 90 | ( 91 | .clk(clk), 92 | .reset(reset), 93 | .trap(trap), 94 | 95 | .memoryData(memoryData), 96 | .memoryReady(memoryReady), 97 | .memoryEnable(memoryEnable), 98 | .memoryReadWrite(memoryReadWrite), 99 | .memoryAddress(memoryAddress) 100 | ); 101 | 102 | // Debug Wires for Register File 103 | `ifndef DISABLE_DEBUG 104 | wire [31 : 0] x0_zero = uut.register_file.Registers[0]; 105 | wire [31 : 0] x1_ra = uut.register_file.Registers[1]; 106 | wire [31 : 0] x2_sp = uut.register_file.Registers[2]; 107 | wire [31 : 0] x3_gp = uut.register_file.Registers[3]; 108 | wire [31 : 0] x4_tp = uut.register_file.Registers[4]; 109 | wire [31 : 0] x5_t0 = uut.register_file.Registers[5]; 110 | wire [31 : 0] x6_t1 = uut.register_file.Registers[6]; 111 | wire [31 : 0] x7_t2 = uut.register_file.Registers[7]; 112 | wire [31 : 0] x8_s0 = uut.register_file.Registers[8]; 113 | wire [31 : 0] x9_s1 = uut.register_file.Registers[9]; 114 | wire [31 : 0] x10_a0 = uut.register_file.Registers[10]; 115 | wire [31 : 0] x11_a1 = uut.register_file.Registers[11]; 116 | wire [31 : 0] x12_a2 = uut.register_file.Registers[12]; 117 | wire [31 : 0] x13_a3 = uut.register_file.Registers[13]; 118 | wire [31 : 0] x14_a4 = uut.register_file.Registers[14]; 119 | wire [31 : 0] x15_a5 = uut.register_file.Registers[15]; 120 | wire [31 : 0] x16_a6 = uut.register_file.Registers[16]; 121 | wire [31 : 0] x17_a7 = uut.register_file.Registers[17]; 122 | wire [31 : 0] x18_s2 = uut.register_file.Registers[18]; 123 | wire [31 : 0] x19_s3 = uut.register_file.Registers[19]; 124 | wire [31 : 0] x20_s4 = uut.register_file.Registers[20]; 125 | wire [31 : 0] x21_s5 = uut.register_file.Registers[21]; 126 | wire [31 : 0] x22_s6 = uut.register_file.Registers[22]; 127 | wire [31 : 0] x23_s7 = uut.register_file.Registers[23]; 128 | wire [31 : 0] x24_s8 = uut.register_file.Registers[24]; 129 | wire [31 : 0] x25_s9 = uut.register_file.Registers[25]; 130 | wire [31 : 0] x26_s10 = uut.register_file.Registers[26]; 131 | wire [31 : 0] x27_s11 = uut.register_file.Registers[27]; 132 | wire [31 : 0] x28_t3 = uut.register_file.Registers[28]; 133 | wire [31 : 0] x29_t4 = uut.register_file.Registers[29]; 134 | wire [31 : 0] x30_t5 = uut.register_file.Registers[30]; 135 | wire [31 : 0] x31_t6 = uut.register_file.Registers[31]; 136 | 137 | wire [31 : 0] f0 = uut.fixed_point_register_file.Registers[0]; 138 | wire [31 : 0] f1 = uut.fixed_point_register_file.Registers[1]; 139 | wire [31 : 0] f2 = uut.fixed_point_register_file.Registers[2]; 140 | wire [31 : 0] f3 = uut.fixed_point_register_file.Registers[3]; 141 | wire [31 : 0] f4 = uut.fixed_point_register_file.Registers[4]; 142 | wire [31 : 0] f5 = uut.fixed_point_register_file.Registers[5]; 143 | wire [31 : 0] f6 = uut.fixed_point_register_file.Registers[6]; 144 | wire [31 : 0] f7 = uut.fixed_point_register_file.Registers[7]; 145 | wire [31 : 0] f8 = uut.fixed_point_register_file.Registers[8]; 146 | wire [31 : 0] f9 = uut.fixed_point_register_file.Registers[9]; 147 | wire [31 : 0] f10 = uut.fixed_point_register_file.Registers[10]; 148 | wire [31 : 0] f11 = uut.fixed_point_register_file.Registers[11]; 149 | wire [31 : 0] f12 = uut.fixed_point_register_file.Registers[12]; 150 | wire [31 : 0] f13 = uut.fixed_point_register_file.Registers[13]; 151 | wire [31 : 0] f14 = uut.fixed_point_register_file.Registers[14]; 152 | wire [31 : 0] f15 = uut.fixed_point_register_file.Registers[15]; 153 | wire [31 : 0] f16 = uut.fixed_point_register_file.Registers[16]; 154 | wire [31 : 0] f17 = uut.fixed_point_register_file.Registers[17]; 155 | wire [31 : 0] f18 = uut.fixed_point_register_file.Registers[18]; 156 | wire [31 : 0] f19 = uut.fixed_point_register_file.Registers[19]; 157 | wire [31 : 0] f20 = uut.fixed_point_register_file.Registers[20]; 158 | wire [31 : 0] f21 = uut.fixed_point_register_file.Registers[21]; 159 | wire [31 : 0] f22 = uut.fixed_point_register_file.Registers[22]; 160 | wire [31 : 0] f23 = uut.fixed_point_register_file.Registers[23]; 161 | wire [31 : 0] f24 = uut.fixed_point_register_file.Registers[24]; 162 | wire [31 : 0] f25 = uut.fixed_point_register_file.Registers[25]; 163 | wire [31 : 0] f26 = uut.fixed_point_register_file.Registers[26]; 164 | wire [31 : 0] f27 = uut.fixed_point_register_file.Registers[27]; 165 | wire [31 : 0] f28 = uut.fixed_point_register_file.Registers[28]; 166 | wire [31 : 0] f29 = uut.fixed_point_register_file.Registers[29]; 167 | wire [31 : 0] f30 = uut.fixed_point_register_file.Registers[30]; 168 | wire [31 : 0] f31 = uut.fixed_point_register_file.Registers[31]; 169 | `endif /*DISABLE_DEBUG*/ 170 | 171 | initial 172 | begin 173 | $dumpfile("LUMOS.vcd"); 174 | $dumpvars(0, LUMOS_Testbench); 175 | repeat (5) @(posedge clk); 176 | reset <= `DISABLE; 177 | end 178 | 179 | // Check trap at end of execution 180 | always @(*) 181 | begin 182 | if (trap == `ENABLE) 183 | reset <= `ENABLE; 184 | repeat (100) @(posedge clk); 185 | 186 | $display("\n\n\tExecution Finished.\n\n"); 187 | $finish; 188 | end 189 | 190 | //////////// 191 | // Memory // 192 | //////////// 193 | 194 | reg [31 : 0] Memory [0 : 4 * 1024 - 1]; 195 | initial $readmemh(`FIRMWARE, Memory); 196 | 197 | // Memory Interface Behaviour 198 | always @(*) 199 | begin 200 | if (!memoryEnable) 201 | begin 202 | memoryData_reg <= 32'bz; 203 | memoryReady <= `DISABLE; 204 | end 205 | end 206 | 207 | always @(posedge clk) 208 | begin 209 | if (memoryEnable) 210 | begin 211 | if (memoryReadWrite == `WRITE) 212 | Memory[memoryAddress >> 2] <= memoryData; 213 | if (memoryReadWrite == `READ & !memoryReady) 214 | begin 215 | `MEMORY_ACCESS_TIME 216 | memoryData_reg <= Memory[memoryAddress >> 2]; 217 | memoryReady <= `ENABLE; 218 | end 219 | end 220 | end 221 | 222 | always @(posedge clk) 223 | begin 224 | if (memoryReady) 225 | begin 226 | memoryData_reg <= 32'bz; 227 | memoryReady <= `DISABLE; 228 | end 229 | end 230 | endmodule 231 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Image LUMOS RISC-V 2 | ================================= 3 | > Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor Core 4 | 5 |
6 | 7 | ## Introduction 8 | 9 | **LUMOS** is a multicycle RISC-V processor that implements a subset of `RV32I` instruction set, designed for educational use in computer organization classes at **Iran University of Science and Technology**. It allows for modular design projects, enabling students to gain hands-on experience with processor architecture. 10 | 11 | ## Features 12 | 13 | - LUMOS executes instructions in multiple stages, such as `instruction_fetch`, `fetch_wait`, `fetch_done`, `decode`, `execute`, `memory_access`, and etc. This approach allows for more complex operations and better utilization of processor resources compared to single-cycle designs. This processor does not support the entire `RV32I` instruction set, which is the base integer instruction set of RISC-V. Instead, it focuses on a subset of instructions that are essential for educational purposes and demonstrating the principles of computer architecture. 14 | 15 | - The processor is designed with modularity in mind, allowing students to work on various components of the processor. As part of their course projects, students will design different execution units, such as FPUs, control units, memory interfaces, and other modules that are integral to the processor's functionality. 16 | 17 | ## LUMOS Datapath 18 | 19 | In a multicycle implementation, we can break down each instruction into a series of steps corresponding to the functional unit operations that are needed. These steps can be used to create a multi-cycle implementation. In this architecture, each step will take 1 clock cycle. This allows that components in the design and different functional units to be used more than once per instruction, as long as it is used on different clock cycles. This sharing of resources can help reduce the amount of hardware required. This classic view of CPU design partitions the design of a processor into data path design and control design. Data path design focuses on the design of ALU and other functional units as well as accessing the registers and memory. Control path design focuses on the design of the state machines to decode instructions and generate the sequence of control signals necessary to appropriately manipulate the data path. 20 | 21 | ![Alt text](https://github.com/IUST-Computer-Organization/LUMOS/blob/main/Images/Datapath_1.png "LUMOS Datapath Section 1") 22 | ![Alt text](https://github.com/IUST-Computer-Organization/LUMOS/blob/main/Images/Datapath_2.png "LUMOS Datapath Section 2") 23 | ![Alt text](https://github.com/IUST-Computer-Organization/LUMOS/blob/main/Images/Datapath_3.png "LUMOS Datapath Section 3") 24 | 25 | ## Synthesis 26 | 27 | This processor core is synthesizable in the 45nm CMOS technology node. LUMOS has gone through the RTL-to-GDS flow using *Synopsys Design Compiler* and *Cadence SoC Encounter* tools. At this node, the core can achieve a frequency of **500MHz** while occupying **12000um2** of area and consuming around **3mw** of power. 28 |
29 | 30 | 31 | 32 | 33 | The LUMOS microprocessor synthesized with Design Compiler and placed and routed by Cadence Encounter 39 | 40 | 41 | 42 | ## Copyright 43 | 44 | Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. 45 | 46 | Copyright 2024 Iran University of Science and Technology - iustCompOrg@gmail.com 47 | 48 | 49 | -------------------------------------------------------------------------------- /Register_File.v: -------------------------------------------------------------------------------- 1 | // LUMOS - Light Utilization with Multicycle Operational Stages 2 | // A RISC-V RV32I Processor Core 3 | 4 | // Description: LUMOS Core Register File Module 5 | // Copyright 2024 Iran University of Science and Technology. 6 | 7 | // Permission to use, copy, modify, and/or distribute this software for any 8 | // purpose with or without fee is hereby granted, provided that the above 9 | // copyright notice and this permission notice appear in all copies. 10 | 11 | module Register_File 12 | #( 13 | parameter WIDTH = 32, 14 | parameter DEPTH = 5 15 | ) 16 | ( 17 | input wire clk, 18 | input wire reset, 19 | 20 | input wire read_enable_1, 21 | input wire read_enable_2, 22 | input wire write_enable, 23 | 24 | input wire [DEPTH - 1 : 0] read_index_1, 25 | input wire [DEPTH - 1 : 0] read_index_2, 26 | input wire [DEPTH - 1 : 0] write_index, 27 | 28 | input wire [WIDTH - 1 : 0] write_data, 29 | 30 | output reg [WIDTH - 1 : 0] read_data_1, 31 | output reg [WIDTH - 1 : 0] read_data_2 32 | ); 33 | reg [WIDTH - 1 : 0] Registers [0 : 2 ** DEPTH - 1]; 34 | 35 | integer i; 36 | always @(posedge clk or posedge reset) 37 | begin 38 | if (reset) 39 | begin 40 | for (i = 0; i < 2 ** DEPTH; i = i + 1) 41 | Registers[i] <= {WIDTH{1'b0}}; 42 | end 43 | else 44 | if (write_enable == 1'b1) 45 | begin 46 | Registers[write_index] <= write_data; 47 | end 48 | end 49 | 50 | always @(*) 51 | begin 52 | if (read_enable_1 == 1'b1) 53 | read_data_1 <= Registers[read_index_1]; 54 | else 55 | read_data_1 <= {WIDTH{1'bz}}; 56 | 57 | if (read_enable_2 == 1'b1) 58 | read_data_2 <= Registers[read_index_2]; 59 | else 60 | read_data_2 <= {WIDTH{1'bz}}; 61 | end 62 | endmodule -------------------------------------------------------------------------------- /Synthesis/LUMOS.sdc: -------------------------------------------------------------------------------- 1 | ################################################################### 2 | 3 | # Created by write_sdc on Wed Jun 6 02:40:33 2018 4 | 5 | ################################################################### 6 | set sdc_version 1.8 7 | 8 | set_units -time ns -resistance kOhm -capacitance pF -voltage V -current uA 9 | set_driving_cell -lib_cell INVX1 [get_ports clk] 10 | set_driving_cell -lib_cell INVX1 [get_ports reset] 11 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[31]}] 12 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[30]}] 13 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[29]}] 14 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[28]}] 15 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[27]}] 16 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[26]}] 17 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[25]}] 18 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[24]}] 19 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[23]}] 20 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[22]}] 21 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[21]}] 22 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[20]}] 23 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[19]}] 24 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[18]}] 25 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[17]}] 26 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[16]}] 27 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[15]}] 28 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[14]}] 29 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[13]}] 30 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[12]}] 31 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[11]}] 32 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[10]}] 33 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[9]}] 34 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[8]}] 35 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[7]}] 36 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[6]}] 37 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[5]}] 38 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[4]}] 39 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[3]}] 40 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[2]}] 41 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[1]}] 42 | set_driving_cell -lib_cell INVX1 [get_ports {memoryData[0]}] 43 | set_driving_cell -lib_cell INVX1 [get_ports memoryReady] 44 | create_clock [get_ports clk] -period 2 -waveform {0 1} 45 | set_input_delay -clock clk 0.1 [get_ports reset] 46 | set_input_delay -clock clk 0.1 [get_ports {memoryData[31]}] 47 | set_input_delay -clock clk 0.1 [get_ports {memoryData[30]}] 48 | set_input_delay -clock clk 0.1 [get_ports {memoryData[29]}] 49 | set_input_delay -clock clk 0.1 [get_ports {memoryData[28]}] 50 | set_input_delay -clock clk 0.1 [get_ports {memoryData[27]}] 51 | set_input_delay -clock clk 0.1 [get_ports {memoryData[26]}] 52 | set_input_delay -clock clk 0.1 [get_ports {memoryData[25]}] 53 | set_input_delay -clock clk 0.1 [get_ports {memoryData[24]}] 54 | set_input_delay -clock clk 0.1 [get_ports {memoryData[23]}] 55 | set_input_delay -clock clk 0.1 [get_ports {memoryData[22]}] 56 | set_input_delay -clock clk 0.1 [get_ports {memoryData[21]}] 57 | set_input_delay -clock clk 0.1 [get_ports {memoryData[20]}] 58 | set_input_delay -clock clk 0.1 [get_ports {memoryData[19]}] 59 | set_input_delay -clock clk 0.1 [get_ports {memoryData[18]}] 60 | set_input_delay -clock clk 0.1 [get_ports {memoryData[17]}] 61 | set_input_delay -clock clk 0.1 [get_ports {memoryData[16]}] 62 | set_input_delay -clock clk 0.1 [get_ports {memoryData[15]}] 63 | set_input_delay -clock clk 0.1 [get_ports {memoryData[14]}] 64 | set_input_delay -clock clk 0.1 [get_ports {memoryData[13]}] 65 | set_input_delay -clock clk 0.1 [get_ports {memoryData[12]}] 66 | set_input_delay -clock clk 0.1 [get_ports {memoryData[11]}] 67 | set_input_delay -clock clk 0.1 [get_ports {memoryData[10]}] 68 | set_input_delay -clock clk 0.1 [get_ports {memoryData[9]}] 69 | set_input_delay -clock clk 0.1 [get_ports {memoryData[8]}] 70 | set_input_delay -clock clk 0.1 [get_ports {memoryData[7]}] 71 | set_input_delay -clock clk 0.1 [get_ports {memoryData[6]}] 72 | set_input_delay -clock clk 0.1 [get_ports {memoryData[5]}] 73 | set_input_delay -clock clk 0.1 [get_ports {memoryData[4]}] 74 | set_input_delay -clock clk 0.1 [get_ports {memoryData[3]}] 75 | set_input_delay -clock clk 0.1 [get_ports {memoryData[2]}] 76 | set_input_delay -clock clk 0.1 [get_ports {memoryData[1]}] 77 | set_input_delay -clock clk 0.1 [get_ports {memoryData[0]}] 78 | set_input_delay -clock clk 0.1 [get_ports memoryReady] 79 | set_output_delay -clock clk 0.1 [get_ports {memoryData[31]}] 80 | set_output_delay -clock clk 0.1 [get_ports {memoryData[30]}] 81 | set_output_delay -clock clk 0.1 [get_ports {memoryData[29]}] 82 | set_output_delay -clock clk 0.1 [get_ports {memoryData[28]}] 83 | set_output_delay -clock clk 0.1 [get_ports {memoryData[27]}] 84 | set_output_delay -clock clk 0.1 [get_ports {memoryData[26]}] 85 | set_output_delay -clock clk 0.1 [get_ports {memoryData[25]}] 86 | set_output_delay -clock clk 0.1 [get_ports {memoryData[24]}] 87 | set_output_delay -clock clk 0.1 [get_ports {memoryData[23]}] 88 | set_output_delay -clock clk 0.1 [get_ports {memoryData[22]}] 89 | set_output_delay -clock clk 0.1 [get_ports {memoryData[21]}] 90 | set_output_delay -clock clk 0.1 [get_ports {memoryData[20]}] 91 | set_output_delay -clock clk 0.1 [get_ports {memoryData[19]}] 92 | set_output_delay -clock clk 0.1 [get_ports {memoryData[18]}] 93 | set_output_delay -clock clk 0.1 [get_ports {memoryData[17]}] 94 | set_output_delay -clock clk 0.1 [get_ports {memoryData[16]}] 95 | set_output_delay -clock clk 0.1 [get_ports {memoryData[15]}] 96 | set_output_delay -clock clk 0.1 [get_ports {memoryData[14]}] 97 | set_output_delay -clock clk 0.1 [get_ports {memoryData[13]}] 98 | set_output_delay -clock clk 0.1 [get_ports {memoryData[12]}] 99 | set_output_delay -clock clk 0.1 [get_ports {memoryData[11]}] 100 | set_output_delay -clock clk 0.1 [get_ports {memoryData[10]}] 101 | set_output_delay -clock clk 0.1 [get_ports {memoryData[9]}] 102 | set_output_delay -clock clk 0.1 [get_ports {memoryData[8]}] 103 | set_output_delay -clock clk 0.1 [get_ports {memoryData[7]}] 104 | set_output_delay -clock clk 0.1 [get_ports {memoryData[6]}] 105 | set_output_delay -clock clk 0.1 [get_ports {memoryData[5]}] 106 | set_output_delay -clock clk 0.1 [get_ports {memoryData[4]}] 107 | set_output_delay -clock clk 0.1 [get_ports {memoryData[3]}] 108 | set_output_delay -clock clk 0.1 [get_ports {memoryData[2]}] 109 | set_output_delay -clock clk 0.1 [get_ports {memoryData[1]}] 110 | set_output_delay -clock clk 0.1 [get_ports {memoryData[0]}] 111 | set_output_delay -clock clk 0.1 [get_ports trap] 112 | set_output_delay -clock clk 0.1 [get_ports memoryEnable] 113 | set_output_delay -clock clk 0.1 [get_ports memoryReadWrite] 114 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[31]}] 115 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[30]}] 116 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[29]}] 117 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[28]}] 118 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[27]}] 119 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[26]}] 120 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[25]}] 121 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[24]}] 122 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[23]}] 123 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[22]}] 124 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[21]}] 125 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[20]}] 126 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[19]}] 127 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[18]}] 128 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[17]}] 129 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[16]}] 130 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[15]}] 131 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[14]}] 132 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[13]}] 133 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[12]}] 134 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[11]}] 135 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[10]}] 136 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[9]}] 137 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[8]}] 138 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[7]}] 139 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[6]}] 140 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[5]}] 141 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[4]}] 142 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[3]}] 143 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[2]}] 144 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[1]}] 145 | set_output_delay -clock clk 0.1 [get_ports {memoryAddress[0]}] 146 | -------------------------------------------------------------------------------- /Synthesis/WORK/ARITHMETIC_LOGIC_UNIT.mr: -------------------------------------------------------------------------------- 1 | verilog presto verilog 2 | -------------------------------------------------------------------------------- /Synthesis/WORK/Arithmetic_Logic_Unit-verilog.pvl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/17fc2dbf9701825f7623881393df2a6082481dd3/Synthesis/WORK/Arithmetic_Logic_Unit-verilog.pvl -------------------------------------------------------------------------------- /Synthesis/WORK/Arithmetic_Logic_Unit-verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/17fc2dbf9701825f7623881393df2a6082481dd3/Synthesis/WORK/Arithmetic_Logic_Unit-verilog.syn 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-------------------------------------------------------------------------------- /Synthesis/WORK/IMMEDIATE_GENERATOR.mr: -------------------------------------------------------------------------------- 1 | verilog presto verilog 2 | -------------------------------------------------------------------------------- /Synthesis/WORK/Immediate_Generator-verilog.pvl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/17fc2dbf9701825f7623881393df2a6082481dd3/Synthesis/WORK/Immediate_Generator-verilog.pvl -------------------------------------------------------------------------------- /Synthesis/WORK/Immediate_Generator-verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/17fc2dbf9701825f7623881393df2a6082481dd3/Synthesis/WORK/Immediate_Generator-verilog.syn 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/Synthesis/WORK/MULTIPLIER.mr: -------------------------------------------------------------------------------- 1 | verilog presto verilog 2 | -------------------------------------------------------------------------------- /Synthesis/WORK/Multiplier-verilog.pvl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/17fc2dbf9701825f7623881393df2a6082481dd3/Synthesis/WORK/Multiplier-verilog.pvl -------------------------------------------------------------------------------- /Synthesis/WORK/Multiplier-verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/17fc2dbf9701825f7623881393df2a6082481dd3/Synthesis/WORK/Multiplier-verilog.syn -------------------------------------------------------------------------------- /Synthesis/WORK/REGISTER_FILE.mr: -------------------------------------------------------------------------------- 1 | verilog presto verilog 2 | -------------------------------------------------------------------------------- /Synthesis/WORK/Register_File-verilog.pvl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/17fc2dbf9701825f7623881393df2a6082481dd3/Synthesis/WORK/Register_File-verilog.pvl -------------------------------------------------------------------------------- /Synthesis/WORK/Register_File-verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/17fc2dbf9701825f7623881393df2a6082481dd3/Synthesis/WORK/Register_File-verilog.syn -------------------------------------------------------------------------------- /Synthesis/alib-52/gscl45nm.db.alib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/17fc2dbf9701825f7623881393df2a6082481dd3/Synthesis/alib-52/gscl45nm.db.alib -------------------------------------------------------------------------------- /Synthesis/compile_dc.tcl: -------------------------------------------------------------------------------- 1 | #/**************************************************/ 2 | #/* Compile Script for Synopsys */ 3 | #/* */ 4 | #/* dc_shell-t -f compile_dc.tcl */ 5 | #/* */ 6 | #/* OSU FreePDK 45nm */ 7 | #/**************************************************/ 8 | 9 | 10 | #/* All verilog files, separated by spaces */ 11 | set my_verilog_files [list LUMOS.v] 12 | 13 | #/* Top-level Module */ 14 | set my_toplevel LUMOS 15 | 16 | #/* The name of the clock pin. If no clock-pin */ 17 | #/* exists, pick anything */ 18 | set my_clock_pin clk 19 | 20 | #/* Target frequency in MHz for optimization */ 21 | set my_clk_freq_MHz 500 22 | 23 | #/* Delay of input signals (Clock-to-Q, Package etc.) */ 24 | set my_input_delay_ns 0.1 25 | 26 | #/* Reserved time for output signals (Holdtime etc.) */ 27 | set my_output_delay_ns 0.1 28 | 29 | 30 | #/**************************************************/ 31 | #/* Setup Library Files */ 32 | #/**************************************************/ 33 | 34 | set link_library "/FreePDK45/osu_soc/lib/files/gscl45nm.db" 35 | set target_library "/FreePDK45/osu_soc/lib/files/gscl45nm.db" 36 | 37 | #/**************************************************/ 38 | #/* Setup Design Library */ 39 | #/**************************************************/ 40 | 41 | define_design_lib WORK -path ./WORK 42 | 43 | #/**************************************************/ 44 | #/* General Optimization Options */ 45 | #/**************************************************/ 46 | set verilogout_show_unconnected_pins "true" 47 | 48 | #/**************************************************/ 49 | #/* Analyze and Elaboration */ 50 | #/**************************************************/ 51 | 52 | analyze -f verilog $my_verilog_files 53 | elaborate $my_toplevel 54 | current_design $my_toplevel 55 | 56 | link 57 | uniquify 58 | 59 | #/**************************************************/ 60 | #/* Clock Definition & Constraints */ 61 | #/**************************************************/ 62 | 63 | set my_period [expr 1000 / $my_clk_freq_MHz] 64 | 65 | set find_clock [ find port [list $my_clock_pin] ] 66 | if { $find_clock != [list] } { 67 | set clk_name $my_clock_pin 68 | create_clock -period $my_period $clk_name 69 | } else { 70 | set clk_name vclk 71 | create_clock -period $my_period -name $clk_name 72 | } 73 | 74 | #/**************************************************/ 75 | #/* Input & Outputs Drive and Delay Options */ 76 | #/**************************************************/ 77 | 78 | set_driving_cell -lib_cell INVX1 [all_inputs] 79 | set_input_delay $my_input_delay_ns -clock $clk_name [remove_from_collection [all_inputs] $my_clock_pin] 80 | set_output_delay $my_output_delay_ns -clock $clk_name [all_outputs] 81 | 82 | 83 | #/**************************************************/ 84 | #/* Compile Design */ 85 | #/**************************************************/ 86 | 87 | compile_ultra 88 | 89 | check_design 90 | 91 | report_constraint -all_violators 92 | 93 | #/**************************************************/ 94 | #/* Generate Netlist Verilog File */ 95 | #/**************************************************/ 96 | 97 | write -f verilog -hierarchy -output "LUMOS.vh" 98 | write_sdc "LUMOS.sdc" 99 | write -f db -hier -output "LUMOS.db" 100 | 101 | #/**************************************************/ 102 | #/* Reports */ 103 | #/**************************************************/ 104 | 105 | redirect reports/timing.rep { report_timing -significant_digits 3} 106 | redirect reports/cell.rep { report_cell } 107 | redirect reports/area.rep { report_area } 108 | redirect reports/power.rep { report_power } 109 | 110 | quit 111 | -------------------------------------------------------------------------------- /Synthesis/default.svf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/17fc2dbf9701825f7623881393df2a6082481dd3/Synthesis/default.svf -------------------------------------------------------------------------------- /Synthesis/encounter.cmd: -------------------------------------------------------------------------------- 1 | ####################################################### 2 | # # 3 | # Encounter Command Logging File # 4 | # Created on Wed Jun 6 02:41:41 2018 # 5 | # # 6 | ####################################################### 7 | 8 | #@(#)CDS: First Encounter v08.10-p004_1 (32bit) 11/04/2008 14:34 (Linux 2.6) 9 | #@(#)CDS: NanoRoute v08.10-p008 NR081027-0018/USR58-UB (database version 2.30, 67.1.1) {superthreading v1.11} 10 | #@(#)CDS: CeltIC v08.10-p002_1 (32bit) 10/23/2008 22:04:14 (Linux 2.6.9-67.0.10.ELsmp) 11 | #@(#)CDS: CTE v08.10-p016_1 (32bit) Oct 26 2008 15:11:51 (Linux 2.6.9-67.0.10.ELsmp) 12 | #@(#)CDS: CPE v08.10-p009 13 | 14 | loadConfig ./encounter.conf 15 | floorPlan -r 1.0 0.6 20 20 20 20 16 | addRing -spacing_bottom 5 -width_left 5 -width_bottom 5 -width_top 5 -spacing_top 5 -layer_bottom metal5 -width_right 5 -around core -center 1 -layer_top metal5 -spacing_right 5 -spacing_left 5 -layer_right metal6 -layer_left metal6 -nets { gnd vdd } 17 | amoebaPlace 18 | sroute -noBlockPins -noPadRings 19 | trialRoute 20 | buildTimingGraph 21 | setCteReport 22 | report_timing -nworst 10 -net -late > timing.rep.1.placed 23 | setLayerPreference hinst -isVisible 0 24 | setLayerPreference fence -isVisible 0 25 | setLayerPreference guide -isVisible 0 26 | setLayerPreference obstruct -isVisible 0 27 | setLayerPreference region -isVisible 0 28 | setLayerPreference screen -isVisible 0 29 | setLayerPreference inst -isVisible 0 30 | setLayerPreference stdCell -isVisible 0 31 | setLayerPreference coverCell -isVisible 0 32 | setLayerPreference block -isVisible 0 33 | setLayerPreference io -isVisible 0 34 | setLayerPreference areaIo -isVisible 0 35 | setLayerPreference net -isVisible 0 36 | setLayerPreference power -isVisible 0 37 | setLayerPreference term -isVisible 0 38 | setLayerPreference ruler -isVisible 0 39 | setLayerPreference text -isVisible 0 40 | setLayerPreference relFPlan -isVisible 0 41 | setLayerPreference yieldCell -isVisible 0 42 | setLayerPreference yieldMap -isVisible 0 43 | setLayerPreference sdpConnect -isVisible 0 44 | setLayerPreference densityMap -isVisible 0 45 | setLayerPreference hinst -isVisible 1 46 | setLayerPreference fence -isVisible 1 47 | setLayerPreference guide -isVisible 1 48 | setLayerPreference obstruct -isVisible 1 49 | setLayerPreference region -isVisible 1 50 | setLayerPreference screen -isVisible 1 51 | setLayerPreference inst -isVisible 1 52 | setLayerPreference stdCell -isVisible 1 53 | setLayerPreference coverCell -isVisible 1 54 | setLayerPreference block -isVisible 1 55 | setLayerPreference io -isVisible 1 56 | setLayerPreference areaIo -isVisible 1 57 | setLayerPreference net -isVisible 1 58 | setLayerPreference power -isVisible 1 59 | setLayerPreference term -isVisible 1 60 | setLayerPreference ruler -isVisible 1 61 | setLayerPreference text -isVisible 1 62 | setLayerPreference relFPlan -isVisible 1 63 | setLayerPreference yieldCell -isVisible 1 64 | setLayerPreference yieldMap -isVisible 1 65 | setLayerPreference sdpConnect -isVisible 1 66 | setLayerPreference densityMap -isVisible 1 67 | setLayerPreference hinst -isSelectable 0 68 | setLayerPreference fence -isSelectable 0 69 | setLayerPreference guide -isSelectable 0 70 | setLayerPreference obstruct -isSelectable 0 71 | setLayerPreference region -isSelectable 0 72 | setLayerPreference screen -isSelectable 0 73 | setLayerPreference inst -isSelectable 0 74 | setLayerPreference stdCell -isSelectable 0 75 | setLayerPreference coverCell -isSelectable 0 76 | setLayerPreference block -isSelectable 0 77 | setLayerPreference io -isSelectable 0 78 | setLayerPreference areaIo -isSelectable 0 79 | setLayerPreference net -isSelectable 0 80 | setLayerPreference power -isSelectable 0 81 | setLayerPreference term -isSelectable 0 82 | setLayerPreference ruler -isSelectable 0 83 | setLayerPreference text -isSelectable 0 84 | setLayerPreference relFPlan -isSelectable 0 85 | setLayerPreference yieldCell -isSelectable 0 86 | setLayerPreference yieldMap -isSelectable 0 87 | setLayerPreference sdpConnect -isSelectable 0 88 | setLayerPreference densityMap -isSelectable 0 89 | setLayerPreference hinst -isSelectable 1 90 | setLayerPreference fence -isSelectable 1 91 | setLayerPreference guide -isSelectable 1 92 | setLayerPreference obstruct -isSelectable 1 93 | setLayerPreference region -isSelectable 1 94 | setLayerPreference screen -isSelectable 1 95 | setLayerPreference inst -isSelectable 1 96 | setLayerPreference stdCell -isSelectable 1 97 | setLayerPreference coverCell -isSelectable 1 98 | setLayerPreference block -isSelectable 1 99 | setLayerPreference io -isSelectable 1 100 | setLayerPreference areaIo -isSelectable 1 101 | setLayerPreference net -isSelectable 1 102 | setLayerPreference power -isSelectable 1 103 | setLayerPreference term -isSelectable 1 104 | setLayerPreference ruler -isSelectable 1 105 | setLayerPreference text -isSelectable 1 106 | setLayerPreference relFPlan -isSelectable 1 107 | setLayerPreference yieldCell -isSelectable 1 108 | setLayerPreference yieldMap -isSelectable 1 109 | setLayerPreference sdpConnect -isSelectable 1 110 | setLayerPreference densityMap -isSelectable 1 111 | setLayerPreference hinst -isSelectable 0 112 | setLayerPreference fence -isSelectable 0 113 | setLayerPreference guide -isSelectable 0 114 | setLayerPreference obstruct -isSelectable 0 115 | setLayerPreference region -isSelectable 0 116 | setLayerPreference screen -isSelectable 0 117 | setLayerPreference inst -isSelectable 0 118 | setLayerPreference stdCell -isSelectable 0 119 | setLayerPreference coverCell -isSelectable 0 120 | setLayerPreference block -isSelectable 0 121 | setLayerPreference io -isSelectable 0 122 | setLayerPreference areaIo -isSelectable 0 123 | setLayerPreference net -isSelectable 0 124 | setLayerPreference power -isSelectable 0 125 | setLayerPreference term -isSelectable 0 126 | setLayerPreference ruler -isSelectable 0 127 | setLayerPreference text -isSelectable 0 128 | setLayerPreference relFPlan -isSelectable 0 129 | setLayerPreference yieldCell -isSelectable 0 130 | setLayerPreference yieldMap -isSelectable 0 131 | setLayerPreference sdpConnect -isSelectable 0 132 | setLayerPreference densityMap -isSelectable 0 133 | setLayerPreference hinst -isSelectable 1 134 | setLayerPreference fence -isSelectable 1 135 | setLayerPreference guide -isSelectable 1 136 | setLayerPreference obstruct -isSelectable 1 137 | setLayerPreference region -isSelectable 1 138 | setLayerPreference screen -isSelectable 1 139 | setLayerPreference inst -isSelectable 1 140 | setLayerPreference stdCell -isSelectable 1 141 | setLayerPreference coverCell -isSelectable 1 142 | setLayerPreference block -isSelectable 1 143 | setLayerPreference io -isSelectable 1 144 | setLayerPreference areaIo -isSelectable 1 145 | setLayerPreference net -isSelectable 1 146 | setLayerPreference power -isSelectable 1 147 | setLayerPreference term -isSelectable 1 148 | setLayerPreference ruler -isSelectable 1 149 | setLayerPreference text -isSelectable 1 150 | setLayerPreference relFPlan -isSelectable 1 151 | setLayerPreference yieldCell -isSelectable 1 152 | setLayerPreference yieldMap -isSelectable 1 153 | setLayerPreference sdpConnect -isSelectable 1 154 | setLayerPreference densityMap -isSelectable 1 155 | setLayerPreference guide -isVisible 0 156 | setLayerPreference guide -isVisible 1 157 | setLayerPreference guide -isVisible 0 158 | setLayerPreference guide -isVisible 1 159 | setLayerPreference fence -isVisible 0 160 | setLayerPreference fence -isVisible 1 161 | setLayerPreference hinst -isVisible 0 162 | setLayerPreference hinst -isVisible 1 163 | setLayerPreference stdCell -isVisible 0 164 | setLayerPreference stdCell -isVisible 1 165 | setLayerPreference stdCell -isVisible 0 166 | setLayerPreference stdCell -isVisible 1 167 | zoomSelected 168 | fit 169 | viewSnapshot -dir {/home/icic/Desktop/lumos } -view {fplan amoeba place } 170 | createSnapshot -name snap 171 | setLayerPreference hinst -isVisible 0 172 | setLayerPreference fence -isVisible 0 173 | setLayerPreference guide -isVisible 0 174 | setLayerPreference obstruct -isVisible 0 175 | setLayerPreference region -isVisible 0 176 | setLayerPreference screen -isVisible 0 177 | setLayerPreference inst -isVisible 0 178 | setLayerPreference stdCell -isVisible 0 179 | setLayerPreference coverCell -isVisible 0 180 | setLayerPreference block -isVisible 0 181 | setLayerPreference io -isVisible 0 182 | setLayerPreference areaIo -isVisible 0 183 | setLayerPreference net -isVisible 0 184 | setLayerPreference power -isVisible 0 185 | setLayerPreference term -isVisible 0 186 | setLayerPreference ruler -isVisible 0 187 | setLayerPreference text -isVisible 0 188 | setLayerPreference relFPlan -isVisible 0 189 | setLayerPreference yieldCell -isVisible 0 190 | setLayerPreference yieldMap -isVisible 0 191 | setLayerPreference sdpConnect -isVisible 0 192 | setLayerPreference densityMap -isVisible 0 193 | setLayerPreference hinst -isVisible 1 194 | setLayerPreference fence -isVisible 1 195 | setLayerPreference guide -isVisible 1 196 | setLayerPreference obstruct -isVisible 1 197 | setLayerPreference region -isVisible 1 198 | setLayerPreference screen -isVisible 1 199 | setLayerPreference inst -isVisible 1 200 | setLayerPreference stdCell -isVisible 1 201 | setLayerPreference coverCell -isVisible 1 202 | setLayerPreference block -isVisible 1 203 | setLayerPreference io -isVisible 1 204 | setLayerPreference areaIo -isVisible 1 205 | setLayerPreference net -isVisible 1 206 | setLayerPreference power -isVisible 1 207 | setLayerPreference term -isVisible 1 208 | setLayerPreference ruler -isVisible 1 209 | setLayerPreference text -isVisible 1 210 | setLayerPreference relFPlan -isVisible 1 211 | setLayerPreference yieldCell -isVisible 1 212 | setLayerPreference yieldMap -isVisible 1 213 | setLayerPreference sdpConnect -isVisible 1 214 | setLayerPreference densityMap -isVisible 1 215 | setLayerPreference hinst -isVisible 0 216 | setLayerPreference fence -isVisible 0 217 | setLayerPreference guide -isVisible 0 218 | setLayerPreference obstruct -isVisible 0 219 | setLayerPreference region -isVisible 0 220 | setLayerPreference screen -isVisible 0 221 | setLayerPreference inst -isVisible 0 222 | setLayerPreference stdCell -isVisible 0 223 | setLayerPreference coverCell -isVisible 0 224 | setLayerPreference block -isVisible 0 225 | setLayerPreference io -isVisible 0 226 | setLayerPreference areaIo -isVisible 0 227 | setLayerPreference net -isVisible 0 228 | setLayerPreference power -isVisible 0 229 | setLayerPreference term -isVisible 0 230 | setLayerPreference ruler -isVisible 0 231 | setLayerPreference text -isVisible 0 232 | setLayerPreference relFPlan -isVisible 0 233 | setLayerPreference yieldCell -isVisible 0 234 | setLayerPreference yieldMap -isVisible 0 235 | setLayerPreference sdpConnect -isVisible 0 236 | setLayerPreference densityMap -isVisible 0 237 | setLayerPreference hinst -isVisible 1 238 | setLayerPreference fence -isVisible 1 239 | setLayerPreference guide -isVisible 1 240 | setLayerPreference obstruct -isVisible 1 241 | setLayerPreference region -isVisible 1 242 | setLayerPreference screen -isVisible 1 243 | setLayerPreference inst -isVisible 1 244 | setLayerPreference stdCell -isVisible 1 245 | setLayerPreference coverCell -isVisible 1 246 | setLayerPreference block -isVisible 1 247 | setLayerPreference io -isVisible 1 248 | setLayerPreference areaIo -isVisible 1 249 | setLayerPreference net -isVisible 1 250 | setLayerPreference power -isVisible 1 251 | setLayerPreference term -isVisible 1 252 | setLayerPreference ruler -isVisible 1 253 | setLayerPreference text -isVisible 1 254 | setLayerPreference relFPlan -isVisible 1 255 | setLayerPreference yieldCell -isVisible 1 256 | setLayerPreference yieldMap -isVisible 1 257 | setLayerPreference sdpConnect -isVisible 1 258 | setLayerPreference densityMap -isVisible 1 259 | -------------------------------------------------------------------------------- /Synthesis/encounter.cmd1: -------------------------------------------------------------------------------- 1 | ####################################################### 2 | # # 3 | # Encounter Command Logging File # 4 | # Created on Wed Jun 6 02:45:36 2018 # 5 | # # 6 | ####################################################### 7 | 8 | #@(#)CDS: First Encounter v08.10-p004_1 (32bit) 11/04/2008 14:34 (Linux 2.6) 9 | #@(#)CDS: NanoRoute v08.10-p008 NR081027-0018/USR58-UB (database version 2.30, 67.1.1) {superthreading v1.11} 10 | #@(#)CDS: CeltIC v08.10-p002_1 (32bit) 10/23/2008 22:04:14 (Linux 2.6.9-67.0.10.ELsmp) 11 | #@(#)CDS: CTE v08.10-p016_1 (32bit) Oct 26 2008 15:11:51 (Linux 2.6.9-67.0.10.ELsmp) 12 | #@(#)CDS: CPE v08.10-p009 13 | 14 | loadConfig ./encounter.conf 15 | floorPlan -r 1.0 0.6 20 20 20 20 16 | addRing -spacing_bottom 5 -width_left 5 -width_bottom 5 -width_top 5 -spacing_top 5 -layer_bottom metal5 -width_right 5 -around core -center 1 -layer_top metal5 -spacing_right 5 -spacing_left 5 -layer_right metal6 -layer_left metal6 -nets { gnd vdd } 17 | amoebaPlace 18 | sroute -noBlockPins -noPadRings 19 | trialRoute 20 | buildTimingGraph 21 | setCteReport 22 | report_timing -nworst 10 -net -late > timing.rep.1.placed 23 | fit 24 | -------------------------------------------------------------------------------- /Synthesis/encounter.conf: -------------------------------------------------------------------------------- 1 | ################################################ 2 | # # 3 | # FirstEncounter Input configuration file # 4 | # # 5 | ################################################ 6 | # 7 | # 8 | 9 | # Specify the name of your toplevel module 10 | set my_toplevel LUMOS 11 | 12 | ################################################ 13 | # No changes required below 14 | ################################################ 15 | 16 | global env 17 | set OSU_FREEPDK /FreePDK45/osu_soc 18 | 19 | global rda_Input 20 | set rda_Input(ui_netlist) $my_toplevel.vh 21 | set rda_Input(ui_timingcon_file) $my_toplevel.sdc 22 | set rda_Input(ui_topcell) $my_toplevel 23 | 24 | set rda_Input(ui_netlisttype) {Verilog} 25 | set rda_Input(ui_ilmlist) {} 26 | set rda_Input(ui_settop) {1} 27 | set rda_Input(ui_celllib) {} 28 | set rda_Input(ui_iolib) {} 29 | set rda_Input(ui_areaiolib) {} 30 | set rda_Input(ui_blklib) {} 31 | set rda_Input(ui_kboxlib) "" 32 | set rda_Input(ui_timelib) "$OSU_FREEPDK/lib/files/gscl45nm.tlf" 33 | set rda_Input(ui_smodDef) {} 34 | set rda_Input(ui_smodData) {} 35 | set rda_Input(ui_dpath) {} 36 | set rda_Input(ui_tech_file) {} 37 | set rda_Input(ui_io_file) "" 38 | set rda_Input(ui_buf_footprint) {buf} 39 | set rda_Input(ui_delay_footprint) {buf} 40 | set rda_Input(ui_inv_footprint) {inv} 41 | set rda_Input(ui_leffile) "$OSU_FREEPDK/lib/files/gscl45nm.lef" 42 | set rda_Input(ui_core_cntl) {aspect} 43 | set rda_Input(ui_aspect_ratio) {1.0} 44 | set rda_Input(ui_core_util) {0.7} 45 | set rda_Input(ui_core_height) {} 46 | set rda_Input(ui_core_width) {} 47 | set rda_Input(ui_core_to_left) {} 48 | set rda_Input(ui_core_to_right) {} 49 | set rda_Input(ui_core_to_top) {} 50 | set rda_Input(ui_core_to_bottom) {} 51 | set rda_Input(ui_max_io_height) {0} 52 | set rda_Input(ui_row_height) {} 53 | set rda_Input(ui_isHorTrackHalfPitch) {0} 54 | set rda_Input(ui_isVerTrackHalfPitch) {1} 55 | set rda_Input(ui_ioOri) {R0} 56 | set rda_Input(ui_isOrigCenter) {0} 57 | set rda_Input(ui_exc_net) {} 58 | set rda_Input(ui_delay_limit) {1000} 59 | set rda_Input(ui_net_delay) {1000.0ps} 60 | set rda_Input(ui_net_load) {0.5pf} 61 | set rda_Input(ui_in_tran_delay) {120.0ps} 62 | set rda_Input(ui_captbl_file) {} 63 | set rda_Input(ui_cap_scale) {1.0} 64 | set rda_Input(ui_xcap_scale) {1.0} 65 | set rda_Input(ui_res_scale) {1.0} 66 | set rda_Input(ui_shr_scale) {1.0} 67 | set rda_Input(ui_time_unit) {none} 68 | set rda_Input(ui_cap_unit) {} 69 | set rda_Input(ui_sigstormlib) {} 70 | set rda_Input(ui_cdb_file) {} 71 | set rda_Input(ui_echo_file) {} 72 | set rda_Input(ui_qxtech_file) {} 73 | set rda_Input(ui_qxlib_file) {} 74 | set rda_Input(ui_qxconf_file) {} 75 | set rda_Input(ui_pwrnet) {vdd} 76 | set rda_Input(ui_gndnet) {gnd} 77 | set rda_Input(flip_first) {1} 78 | set rda_Input(double_back) {1} 79 | set rda_Input(assign_buffer) {0} 80 | set rda_Input(ui_pg_connections) [list \ 81 | {PIN:vdd:} \ 82 | {PIN:gnd:} \ 83 | ] 84 | set rda_Input(PIN:vdd:) {vdd} 85 | set rda_Input(PIN:gnd:) {gnd} 86 | -------------------------------------------------------------------------------- /Synthesis/encounter.log: -------------------------------------------------------------------------------- 1 | Checking out Encounter license ... 2 | SOC_Encounter_GXL 8.1 license checkout succeeded. 3 | This Encounter release has been compiled with OA version 22.04-p032. 4 | sourcing /opt/Cadence/SOC8.1USR3/etc/fe/rdaDSL.tcl 5 | ******************************************************************* 6 | * Copyright (c) Cadence Design Systems, Inc. 1996 - 2008. * 7 | * All rights reserved. * 8 | * * 9 | * * 10 | * * 11 | * This program contains confidential and trade secret information * 12 | * of Cadence Design Systems, Inc. and is protected by copyright * 13 | * law and international treaties. Any reproduction, use, * 14 | * distribution or disclosure of this program or any portion of it,* 15 | * or any attempt to obtain a human-readable version of this * 16 | * program, without the express, prior written consent of * 17 | * Cadence Design Systems, Inc., is strictly prohibited. * 18 | * * 19 | * Cadence Design Systems, Inc. * 20 | * 2655 Seely Avenue * 21 | * San Jose, CA 95134, USA * 22 | * * 23 | * * 24 | ******************************************************************* 25 | 26 | @(#)CDS: First Encounter v08.10-p004_1 (32bit) 11/04/2008 14:34 (Linux 2.6) 27 | @(#)CDS: NanoRoute v08.10-p008 NR081027-0018/USR58-UB (database version 2.30, 67.1.1) {superthreading v1.11} 28 | @(#)CDS: CeltIC v08.10-p002_1 (32bit) 10/23/2008 22:04:14 (Linux 2.6.9-67.0.10.ELsmp) 29 | @(#)CDS: CTE v08.10-p016_1 (32bit) Oct 26 2008 15:11:51 (Linux 2.6.9-67.0.10.ELsmp) 30 | @(#)CDS: CPE v08.10-p009 31 | --- Starting "First Encounter v08.10-p004_1" on Wed Jun 6 02:41:40 2018 (mem=62.3M) --- 32 | --- Running on ICICVM.lab.edu (i686 w/Linux 2.6.9-78.EL) --- 33 | This version was compiled on Tue Nov 4 14:34:21 PST 2008. 34 | Set DBUPerIGU to 1000. 35 | Set Default Mode Total Cap Scale Factor to 1.00 36 | Set Detail Mode Total Cap Scale Factor to 1.00 37 | Set Coupling Total Cap Scale Factor to 1.00 38 | Set Total Res Scale Factor to 1.00 39 | Set net toggle Scale Factor to 1.00 40 | Set Shrink Factor to 1.00000 41 | Sourcing tcl/tk file "encounter.tcl" ... 42 | loadConfig ./encounter.conf 43 | Reading config file - ./encounter.conf 44 | 45 | Loading Lef file /home/icic/FreePDK45/osu_soc/lib/files/gscl45nm.lef... 46 | **WARN: (SOCLF-155): ViaRule only supports routing/cut layer, but poly layer found for viaRule 'M1_POLY', 47 | Set DBUPerIGU to M2 pitch 380. 48 | Initializing default via types and wire widths ... 49 | 50 | Power Planner/ViaGen version 8.1.45 promoted on 09/01/2008. 51 | viaInitial starts at Wed Jun 6 02:41:41 2018 52 | **WARN: (SOCPP-547): Cut 'contact' does not fit in viaRule 'M1_POLY'. 53 | viaInitial ends at Wed Jun 6 02:41:41 2018 54 | Reading netlist ... 55 | Backslashed names will retain backslash and a trailing blank character. 56 | Reading verilog netlist 'LUMOS.vh' 57 | Module Fixed_Point_Unit not defined. Created automatically. 58 | **WARN: (SOCVL-346): Module Fixed_Point_Unit is not defined in LEF files. It will be treated as an empty module. 59 | Undeclared bus operand_1 in module Fixed_Point_Unit ... created as [31:0]. 60 | Undeclared bus operand_2 in module Fixed_Point_Unit ... created as [31:0]. 61 | Undeclared bus operation in module Fixed_Point_Unit ... created as [1:0]. 62 | Undeclared bus result in module Fixed_Point_Unit ... created as [31:0]. 63 | 64 | *** Memory Usage v0.144 (Current mem = 196.371M, initial mem = 62.277M) *** 65 | *** End netlist parsing (cpu=0:00:00.0, real=0:00:00.0, mem=196.4M) *** 66 | Set top cell to LUMOS. 67 | Reading common timing library '/home/icic/FreePDK45/osu_soc/lib/files/gscl45nm.tlf' ... 68 | read 31 cells in library 'gscl45nm' 69 | *** End library_loading (cpu=0.00min, mem=0.3M, fe_cpu=0.04min, fe_mem=196.7M) *** 70 | Found empty module (Fixed_Point_Unit). 71 | Starting recursive module instantiation check. 72 | No recursion found. 73 | *****NEW dbFlattenCell is used. 74 | Flattening Cell LUMOS ... 75 | *** Netlist is unique. 76 | Set DBUPerIGU to techSite CoreSite width 760. 77 | ** info: there are 37 modules. 78 | ** info: there are 4032 stdCell insts. 79 | 80 | *** Memory Usage v0.144 (Current mem = 198.457M, initial mem = 62.277M) *** 81 | CTE reading timing constraint file 'LUMOS.sdc' ... 82 | INFO (CTE): constraints read successfully 83 | WARNING (CTE-25): Line: 8 of File LUMOS.sdc : Skipped unsupported command: set_units 84 | 85 | 86 | *** Read timing constraints (cpu=0:00:00.0 mem=202.1M) *** 87 | Total number of combinational cells: 25 88 | Total number of sequential cells: 4 89 | Total number of tristate cells: 2 90 | Total number of level shifter cells: 0 91 | Total number of power gating cells: 0 92 | Total number of isolation cells: 0 93 | Total number of power switch cells: 0 94 | Total number of pulse generator cells: 0 95 | Total number of always on buffers: 0 96 | Total number of retention cells: 0 97 | List of usable buffers: BUFX2 BUFX4 98 | Total number of usable buffers: 2 99 | List of unusable buffers: 100 | Total number of unusable buffers: 0 101 | List of usable inverters: INVX2 INVX1 INVX4 INVX8 102 | Total number of usable inverters: 4 103 | List of unusable inverters: 104 | Total number of unusable inverters: 0 105 | List of identified usable delay cells: CLKBUF1 CLKBUF2 CLKBUF3 106 | Total number of identified usable delay cells: 3 107 | List of identified unusable delay cells: 108 | Total number of identified unusable delay cells: 0 109 | *info: set bottom ioPad orient R0 110 | Horizontal Layer M1 offset = 190 (guessed) 111 | Vertical Layer M2 offset = 190 (guessed) 112 | Suggestion: specify LAYER OFFSET in LEF file 113 | Reason: hard to extract LAYER OFFSET from standard cells 114 | Set Using Default Delay Limit as 1000. 115 | Set Default Net Delay as 1000 ps. 116 | Set Default Net Load as 0.5 pF. 117 | Set Input Pin Transition Delay as 120 ps. 118 | **WARN: (SOCOPT-3465): The buffer cells were automatically identified. The command setBufFootPrint is ignored. If you want to use this manual setting, rerun encounter with dbgGPSAutoCellFunction set to 0. 119 | **WARN: (SOCOPT-3466): The inverter cells were automatically identified. The command setInvFootPrint is ignored. If you want to use this manual setting, rerun encounter with dbgGPSAutoCellFunction set to 0. 120 | **WARN: (SOCOPT-3467): The delay cells were automatically identified. The command setDelayFootPrint is ignored. If you want to use this manual setting, rerun encounter with dbgGPSAutoCellFunction set to 0. 121 | floorPlan -r 1.0 0.6 20 20 20 20 122 | Adjusting Core to Left to: 20.1400. Core to Bottom to: 20.1400. 123 | Horizontal Layer M1 offset = 190 (guessed) 124 | Vertical Layer M2 offset = 190 (guessed) 125 | Suggestion: specify LAYER OFFSET in LEF file 126 | Reason: hard to extract LAYER OFFSET from standard cells 127 | addRing -spacing_bottom 5 -width_left 5 -width_bottom 5 -width_top 5 -spacing_top 5 -layer_bottom metal5 -width_right 5 -around core -center 1 -layer_top metal5 -spacing_right 5 -spacing_left 5 -layer_right metal6 -layer_left metal6 -nets { gnd vdd } 128 | 129 | 130 | The power planner created 8 wires. 131 | 132 | amoebaPlace 133 | **WARN: (SOCSP-9007): The command 'amoebaPlace' is obsolete. It has been replaced by 'placeDesign'. 134 | Extracting standard cell pins and blockage ...... 135 | Pin and blockage extraction finished 136 | Extracting macro/IO cell pins and blockage ...... 137 | Pin and blockage extraction finished 138 | *** Starting "NanoPlace(TM) placement v0.845 (mem=203.2M)" ... 139 | Options: ignoreSpare pinGuide gpeffort=medium 140 | #std cell=4032 #block=0 (0 floating + 0 preplaced) #ioInst=0 #net=4007 #term=11658 #term/net=2.91, #fixedIo=0, #floatIo=0, #fixedPin=0, #floatPin=69 141 | stdCell: 4032 single + 0 double + 0 multi 142 | Total standard cell length = 4.1794 (mm), area = 0.0103 (mm^2) 143 | Design contains fractional cell. 144 | Average module density = 0.602. 145 | Density for the design = 0.602. 146 | = stdcell_area 10998 (10323 um^2) / alloc_area 18285 (17162 um^2). 147 | Pin Density = 1.060. 148 | = total # of pins 11658 / total Instance area 10998. 149 | Found multi-fanin net memoryData[31] 150 | Found multi-fanin net memoryData[30] 151 | Found multi-fanin net memoryData[29] 152 | Found multi-fanin net memoryData[28] 153 | Found multi-fanin net memoryData[27] 154 | Found multi-fanin net memoryData[26] 155 | Found multi-fanin net memoryData[25] 156 | Found multi-fanin net memoryData[24] 157 | Found multi-fanin net memoryData[23] 158 | Found multi-fanin net memoryData[22] 159 | ...... 160 | Found 32 (out of 4007) multi-fanin nets. 161 | Iteration 1: Total net bbox = 1.035e+04 (1.04e+04 0.00e+00) 162 | Est. stn bbox = 1.182e+04 (1.18e+04 0.00e+00) 163 | cpu = 0:00:00.0 real = 0:00:01.0 mem = 203.3M 164 | Iteration 2: Total net bbox = 2.428e+04 (1.01e+04 1.42e+04) 165 | Est. stn bbox = 2.915e+04 (1.15e+04 1.76e+04) 166 | cpu = 0:00:00.1 real = 0:00:00.0 mem = 203.3M 167 | Iteration 3: Total net bbox = 2.650e+04 (1.08e+04 1.57e+04) 168 | Est. stn bbox = 3.233e+04 (1.29e+04 1.95e+04) 169 | cpu = 0:00:00.1 real = 0:00:00.0 mem = 203.3M 170 | Iteration 4: Total net bbox = 3.366e+04 (1.26e+04 2.11e+04) 171 | Est. stn bbox = 4.045e+04 (1.46e+04 2.58e+04) 172 | cpu = 0:00:00.1 real = 0:00:00.0 mem = 203.3M 173 | Iteration 5: Total net bbox = 3.738e+04 (1.62e+04 2.12e+04) 174 | Est. stn bbox = 4.479e+04 (1.88e+04 2.60e+04) 175 | cpu = 0:00:00.0 real = 0:00:00.0 mem = 203.3M 176 | Iteration 6: Total net bbox = 4.103e+04 (1.62e+04 2.48e+04) 177 | Est. stn bbox = 4.878e+04 (1.89e+04 2.99e+04) 178 | cpu = 0:00:00.0 real = 0:00:00.0 mem = 203.3M 179 | Iteration 7: Total net bbox = 4.328e+04 (1.83e+04 2.50e+04) 180 | Est. stn bbox = 5.119e+04 (2.11e+04 3.01e+04) 181 | cpu = 0:00:00.0 real = 0:00:00.0 mem = 203.5M 182 | Iteration 8: Total net bbox = 4.623e+04 (1.83e+04 2.79e+04) 183 | Est. stn bbox = 5.451e+04 (2.12e+04 3.33e+04) 184 | cpu = 0:00:00.1 real = 0:00:00.0 mem = 203.5M 185 | Iteration 9: Total net bbox = 4.754e+04 (1.96e+04 2.79e+04) 186 | Est. stn bbox = 5.593e+04 (2.25e+04 3.34e+04) 187 | cpu = 0:00:00.1 real = 0:00:00.0 mem = 203.5M 188 | Iteration 10: Total net bbox = 4.985e+04 (1.96e+04 3.02e+04) 189 | Est. stn bbox = 5.839e+04 (2.26e+04 3.58e+04) 190 | cpu = 0:00:00.1 real = 0:00:00.0 mem = 203.6M 191 | Iteration 11: Total net bbox = 5.022e+04 (1.96e+04 3.06e+04) 192 | Est. stn bbox = 5.878e+04 (2.26e+04 3.62e+04) 193 | cpu = 0:00:00.0 real = 0:00:00.0 mem = 203.7M 194 | Iteration 12: Total net bbox = 5.538e+04 (2.39e+04 3.15e+04) 195 | Est. stn bbox = 6.409e+04 (2.69e+04 3.71e+04) 196 | cpu = 0:00:00.0 real = 0:00:00.0 mem = 203.7M 197 | *** cost = 5.538e+04 (2.39e+04 3.15e+04) (cpu for global=0:00:00.7) real=0:00:01.0*** 198 | Design contains fractional cell. 199 | Starting refinePlace ... 200 | Placement tweakage begins. 201 | wire length = 5.540e+04 = 2.390e+04 H + 3.150e+04 V 202 | wire length = 5.176e+04 = 2.080e+04 H + 3.097e+04 V 203 | Placement tweakage ends. 204 | Statistics of distance of Instance movement in detailed placement: 205 | maximum (X+Y) = 38.76 um 206 | inst (U1356) with max move: (135.66, 104.12) -> (101.84, 99.18) 207 | mean (X+Y) = 3.30 um 208 | Total instances moved : 2679 209 | *** cpu=0:00:00.1 mem=203.5M mem(used)=0.0M*** 210 | Total net length = 5.191e+04 (2.084e+04 3.107e+04) (ext = 2.815e+03) 211 | *** End of Placement (cpu=0:00:00.8, real=0:00:02.0, mem=203.5M) *** 212 | Design contains fractional cell. 213 | default core: bins with density > 0.75 = 8.33 % ( 3 / 36 ) 214 | Starting IO pin assignment... 215 | Completed IO pin assignment. 216 | sroute -noBlockPins -noPadRings 217 | **WARN: (SOCSR-4053): SRoute option "-noBlockPins" is obsolete and has been replaced by "-connect". The obsolete option still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your script to use "-connect". 218 | **WARN: (SOCSR-4053): SRoute option "-noPadRings" is obsolete and has been replaced by "-connect". The obsolete option still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your script to use "-connect". 219 | No routing obstructions were found in the design. 220 | *** Begin SPECIAL ROUTE on Wed Jun 6 02:41:43 2018 *** 221 | Sroute/fcroute version 8.1.45 promoted on 09/01/2008. 222 | SPECIAL ROUTE ran on directory: /home/icic/Desktop/lumos 223 | SPECIAL ROUTE ran on machine: ICICVM.lab.edu (Linux 2.6.9-78.EL i686 3.29Ghz) 224 | 225 | Begin option processing ... 226 | (from .sroute_9360.conf) srouteConnectPowerBump set to false 227 | (from .sroute_9360.conf) routeSpecial set to true 228 | (from .sroute_9360.conf) srouteConnectBlockPin set to false 229 | (from .sroute_9360.conf) srouteFollowCorePinEnd set to 3 230 | (from .sroute_9360.conf) srouteJogControl set to "preferWithChanges differentLayer" 231 | (from .sroute_9360.conf) sroutePadPinAllPorts set to true 232 | (from .sroute_9360.conf) sroutePreserveExistingRoutes set to true 233 | End option processing: cpu: 0:00:00, real: 0:00:00, peak: 372.00 megs. 234 | 235 | Reading LEF technology information... 236 | Reading floorplan and netlist information... 237 | Finished reading floorplan and netlist information. 238 | Read in 22 layers, 10 routing layers, 1 overlap layer 239 | Read in 33 macros, 25 used 240 | Read in 4032 components 241 | 4032 core components: 0 unplaced, 4032 placed, 0 fixed 242 | Read in 70 physical pins 243 | 70 physical pins: 0 unplaced, 70 placed, 0 fixed 244 | Read in 70 nets 245 | Read in 2 special nets, 2 routed 246 | Read in 8134 terminals 247 | Begin power routing ... 248 | **WARN: (SOCSR-1256): Net vdd does not have CORE class pad pins to be routed. 249 | Please check net list or port class. 250 | Net vdd does not have AREAIO class pad pins to be routed. 251 | Please check net list or port class. 252 | **WARN: (SOCSR-1256): Net gnd does not have CORE class pad pins to be routed. 253 | Please check net list or port class. 254 | Net gnd does not have AREAIO class pad pins to be routed. 255 | Please check net list or port class. 256 | CPU time for FollowPin 0 seconds 257 | CPU time for FollowPin 0 seconds 258 | Number of IO ports routed: 0 259 | Number of Stripe ports routed: 0 260 | Number of Core ports routed: 108 261 | Number of Followpin connections: 54 262 | End power routing: cpu: 0:00:00, real: 0:00:00, peak: 383.00 megs. 263 | 264 | 265 | 266 | Begin updating DB with routing results ... 267 | Updating DB with 70 io pins ... 268 | Updating DB with 20 via definition ... 269 | 270 | sroute post-processing starts at Wed Jun 6 02:41:43 2018 271 | The viaGen is rebuilding shadow vias for net gnd. 272 | sroute post-processing ends at Wed Jun 6 02:41:43 2018 273 | 274 | sroute post-processing starts at Wed Jun 6 02:41:43 2018 275 | The viaGen is rebuilding shadow vias for net vdd. 276 | sroute post-processing ends at Wed Jun 6 02:41:43 2018 277 | 278 | 279 | sroute: Total CPU time used = 0:0:0 280 | sroute: Total Real time used = 0:0:0 281 | sroute: Total Memory used = 1.52 megs 282 | sroute: Total Peak Memory used = 204.98 megs 283 | trialRoute 284 | *** Starting trialRoute (mem=205.0M) *** 285 | 286 | There are 0 pin guide points passed to trialRoute. 287 | Options: -noPinGuide 288 | 289 | routingBox: (0 0) (343140 342100) 290 | coreBox: (40280 40280) (303140 302100) 291 | Number of multi-gpin terms=87, multi-gpins=179, moved blk term=0/0 292 | 293 | Phase 1a route (0:00:00.0 206.6M): 294 | Est net length = 5.794e+04um = 2.509e+04H + 3.284e+04V 295 | Usage: (11.3%H 14.0%V) = (2.924e+04um 5.707e+04um) = (30287 23179) 296 | Obstruct: 0 = 0 (0.0%H) + 0 (0.0%V) 297 | Overflow: 0 = 0 (0.00% H) + 0 (0.00% V) 298 | 299 | Phase 1b route (0:00:00.0 207.8M): 300 | Usage: (11.3%H 14.0%V) = (2.918e+04um 5.707e+04um) = (30220 23179) 301 | Overflow: 0 = 0 (0.00% H) + 0 (0.00% V) 302 | 303 | Phase 1c route (0:00:00.0 207.8M): 304 | Usage: (11.3%H 14.0%V) = (2.914e+04um 5.702e+04um) = (30181 23160) 305 | Overflow: 0 = 0 (0.00% H) + 0 (0.00% V) 306 | 307 | Phase 1d route (0:00:00.0 207.8M): 308 | Usage: (11.3%H 14.0%V) = (2.914e+04um 5.702e+04um) = (30181 23160) 309 | Overflow: 0 = 0 (0.00% H) + 0 (0.00% V) 310 | 311 | Phase 1e route (0:00:00.0 208.5M): 312 | Usage: (11.3%H 14.0%V) = (2.914e+04um 5.702e+04um) = (30181 23160) 313 | Overflow: 0 = 0 (0.00% H) + 0 (0.00% V) 314 | 315 | Usage: (11.3%H 14.0%V) = (2.914e+04um 5.702e+04um) = (30181 23160) 316 | Overflow: 0 = 0 (0.00% H) + 0 (0.00% V) 317 | 318 | Congestion distribution: 319 | 320 | Remain cntH cntV 321 | -------------------------------------- 322 | -------------------------------------- 323 | 2: 0 0.00% 3 0.03% 324 | 3: 0 0.00% 116 0.98% 325 | 4: 0 0.00% 184 1.55% 326 | 5: 0 0.00% 286 2.41% 327 | 6: 0 0.00% 377 3.18% 328 | 7: 0 0.00% 560 4.73% 329 | 8: 0 0.00% 805 6.79% 330 | 9: 0 0.00% 1060 8.95% 331 | 10: 0 0.00% 1258 10.62% 332 | 11: 0 0.00% 1240 10.46% 333 | 12: 605 5.11% 1680 14.18% 334 | 13: 909 7.67% 1641 13.85% 335 | 14: 11 0.09% 784 6.62% 336 | 15: 320 2.70% 520 4.39% 337 | 16: 234 1.97% 462 3.90% 338 | 17: 463 3.91% 22 0.19% 339 | 18: 857 7.23% 0 0.00% 340 | 19: 850 7.17% 0 0.00% 341 | 20: 7601 64.14% 852 7.19% 342 | 343 | 344 | *** Memory Usage v0.144 (Current mem = 211.496M, initial mem = 62.277M) *** 345 | Phase 1l route (0:00:00.0 207.5M): 346 | 347 | 348 | *** After '-updateRemainTrks' operation: 349 | 350 | Usage: (11.6%H 14.6%V) = (2.995e+04um 5.920e+04um) = (31024 24042) 351 | Overflow: 0 = 0 (0.00% H) + 0 (0.00% V) 352 | 353 | Congestion distribution: 354 | 355 | Remain cntH cntV 356 | -------------------------------------- 357 | -------------------------------------- 358 | 0: 0 0.00% 2 0.02% 359 | 1: 0 0.00% 2 0.02% 360 | 2: 0 0.00% 6 0.05% 361 | 3: 0 0.00% 141 1.19% 362 | 4: 0 0.00% 210 1.77% 363 | 5: 0 0.00% 344 2.90% 364 | 6: 0 0.00% 403 3.40% 365 | 7: 0 0.00% 567 4.78% 366 | 8: 0 0.00% 812 6.85% 367 | 9: 0 0.00% 1013 8.55% 368 | 10: 0 0.00% 1199 10.12% 369 | 11: 0 0.00% 1219 10.29% 370 | 12: 605 5.11% 1659 14.00% 371 | 13: 909 7.67% 1641 13.85% 372 | 14: 15 0.13% 779 6.57% 373 | 15: 327 2.76% 517 4.36% 374 | 16: 244 2.06% 462 3.90% 375 | 17: 488 4.12% 22 0.19% 376 | 18: 894 7.54% 0 0.00% 377 | 19: 869 7.33% 0 0.00% 378 | 20: 7499 63.28% 852 7.19% 379 | 380 | 381 | 382 | *** Completed Phase 1 route (0:00:00.1 205.9M) *** 383 | 384 | 385 | Total length: 6.173e+04um, number of vias: 23442 386 | M1(H) length: 8.082e+02um, number of vias: 11294 387 | M2(V) length: 2.397e+04um, number of vias: 10296 388 | M3(H) length: 2.462e+04um, number of vias: 1592 389 | M4(V) length: 1.050e+04um, number of vias: 135 390 | M5(H) length: 2.481e+02um, number of vias: 121 391 | M6(V) length: 1.577e+03um, number of vias: 3 392 | M7(H) length: 2.300e-01um, number of vias: 1 393 | M8(V) length: 9.050e-01um, number of vias: 0 394 | M9(H) length: 0.000e+00um, number of vias: 0 395 | M10(V) length: 0.000e+00um 396 | *** Completed Phase 2 route (0:00:00.1 207.9M) *** 397 | 398 | *** Finished all Phases (cpu=0:00:00.2 mem=207.9M) *** 399 | Peak Memory Usage was 211.5M 400 | *** Finished trialRoute (cpu=0:00:00.2 mem=207.9M) *** 401 | 402 | buildTimingGraph 403 | setCteReport 404 | WARNING: The reportTA command is obsolete. To generate a timing report that 405 | provides information about the various paths in the design, use the 406 | report_timing command. 407 | 408 | report_timing -nworst 10 -net -late > timing.rep.1.placed 409 | Default RC Extraction called for design LUMOS. 410 | RCMode: Default 411 | Capacitance Scaling Factor : 1.00000 412 | Coupling Cap. Scaling Factor : 1.00000 413 | Resistance Scaling Factor : 1.00000 414 | Shrink Factor : 1.00000 415 | Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets. 416 | Using detail cap. scale factor for clock nets. 417 | Default RC Extraction DONE (CPU Time: 0:00:00.0 Real Time: 0:00:00.0 MEM: 210.957M) 418 | Calculate delays in Single mode... 419 | Topological Sorting (CPU = 0:00:00.0, MEM = 220.5M) 420 | Number of Loop : 0 421 | Start delay calculation (mem=220.480M)... 422 | **WARN: (SOCEXT-2882): Unable to find resistance for via 'M3_M2_via' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms. 423 | **WARN: (SOCEXT-2882): Unable to find resistance for via 'M2_M1_via' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms. 424 | **WARN: (SOCEXT-2882): Unable to find resistance for via 'M4_M3_via' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms. 425 | **WARN: (SOCEXT-2882): Unable to find resistance for via 'M5_M4_via' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms. 426 | **WARN: (SOCEXT-2882): Unable to find resistance for via 'M6_M5_via' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms. 427 | **WARN: (SOCEXT-2882): Unable to find resistance for via 'M7_M6_via' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms. 428 | **WARN: (SOCEXT-2882): Unable to find resistance for via 'M8_M7_via' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms. 429 | Delay calculation completed. 430 | (0:00:00.1 220.480M 0) 431 | *** CDM Built up (cpu=0:00:00.2 mem= 220.5M) *** 432 | *** reportTA (0:00:00.2) *** 433 | **ERROR: (SOCSYT-6692): [encounter.tcl]: Invalid return code while executing "encounter.tcl" 434 | **ERROR: (SOCSYT-6693): invalid command name "setIPOMode" 435 | setLayerPreference hinst -isVisible 0 436 | setLayerPreference fence -isVisible 0 437 | setLayerPreference guide -isVisible 0 438 | setLayerPreference obstruct -isVisible 0 439 | setLayerPreference region -isVisible 0 440 | setLayerPreference screen -isVisible 0 441 | setLayerPreference inst -isVisible 0 442 | setLayerPreference stdCell -isVisible 0 443 | setLayerPreference coverCell -isVisible 0 444 | setLayerPreference block -isVisible 0 445 | setLayerPreference io -isVisible 0 446 | setLayerPreference areaIo -isVisible 0 447 | setLayerPreference net -isVisible 0 448 | setLayerPreference power -isVisible 0 449 | setLayerPreference term -isVisible 0 450 | setLayerPreference ruler -isVisible 0 451 | setLayerPreference text -isVisible 0 452 | setLayerPreference relFPlan -isVisible 0 453 | setLayerPreference yieldCell -isVisible 0 454 | setLayerPreference yieldMap -isVisible 0 455 | setLayerPreference sdpConnect -isVisible 0 456 | setLayerPreference densityMap -isVisible 0 457 | setLayerPreference hinst -isVisible 1 458 | setLayerPreference fence -isVisible 1 459 | setLayerPreference guide -isVisible 1 460 | setLayerPreference obstruct -isVisible 1 461 | setLayerPreference region -isVisible 1 462 | setLayerPreference screen -isVisible 1 463 | setLayerPreference inst -isVisible 1 464 | setLayerPreference stdCell -isVisible 1 465 | setLayerPreference coverCell -isVisible 1 466 | setLayerPreference block -isVisible 1 467 | setLayerPreference io -isVisible 1 468 | setLayerPreference areaIo -isVisible 1 469 | setLayerPreference net -isVisible 1 470 | setLayerPreference power -isVisible 1 471 | setLayerPreference term -isVisible 1 472 | setLayerPreference ruler -isVisible 1 473 | setLayerPreference text -isVisible 1 474 | setLayerPreference relFPlan -isVisible 1 475 | setLayerPreference yieldCell -isVisible 1 476 | setLayerPreference yieldMap -isVisible 1 477 | setLayerPreference sdpConnect -isVisible 1 478 | setLayerPreference densityMap -isVisible 1 479 | setLayerPreference hinst -isSelectable 0 480 | setLayerPreference fence -isSelectable 0 481 | setLayerPreference guide -isSelectable 0 482 | setLayerPreference obstruct -isSelectable 0 483 | setLayerPreference region -isSelectable 0 484 | setLayerPreference screen -isSelectable 0 485 | setLayerPreference inst -isSelectable 0 486 | setLayerPreference stdCell -isSelectable 0 487 | setLayerPreference coverCell -isSelectable 0 488 | setLayerPreference block -isSelectable 0 489 | setLayerPreference io -isSelectable 0 490 | setLayerPreference areaIo -isSelectable 0 491 | setLayerPreference net -isSelectable 0 492 | setLayerPreference power -isSelectable 0 493 | setLayerPreference term -isSelectable 0 494 | setLayerPreference ruler -isSelectable 0 495 | setLayerPreference text -isSelectable 0 496 | setLayerPreference relFPlan -isSelectable 0 497 | setLayerPreference yieldCell -isSelectable 0 498 | setLayerPreference yieldMap -isSelectable 0 499 | setLayerPreference sdpConnect -isSelectable 0 500 | setLayerPreference densityMap -isSelectable 0 501 | setLayerPreference hinst -isSelectable 1 502 | setLayerPreference fence -isSelectable 1 503 | setLayerPreference guide -isSelectable 1 504 | setLayerPreference obstruct -isSelectable 1 505 | setLayerPreference region -isSelectable 1 506 | setLayerPreference screen -isSelectable 1 507 | setLayerPreference inst -isSelectable 1 508 | setLayerPreference stdCell -isSelectable 1 509 | setLayerPreference coverCell -isSelectable 1 510 | setLayerPreference block -isSelectable 1 511 | setLayerPreference io -isSelectable 1 512 | setLayerPreference areaIo -isSelectable 1 513 | setLayerPreference net -isSelectable 1 514 | setLayerPreference power -isSelectable 1 515 | setLayerPreference term -isSelectable 1 516 | setLayerPreference ruler -isSelectable 1 517 | setLayerPreference text -isSelectable 1 518 | setLayerPreference relFPlan -isSelectable 1 519 | setLayerPreference yieldCell -isSelectable 1 520 | setLayerPreference yieldMap -isSelectable 1 521 | setLayerPreference sdpConnect -isSelectable 1 522 | setLayerPreference densityMap -isSelectable 1 523 | setLayerPreference hinst -isSelectable 0 524 | setLayerPreference fence -isSelectable 0 525 | setLayerPreference guide -isSelectable 0 526 | setLayerPreference obstruct -isSelectable 0 527 | setLayerPreference region -isSelectable 0 528 | setLayerPreference screen -isSelectable 0 529 | setLayerPreference inst -isSelectable 0 530 | setLayerPreference stdCell -isSelectable 0 531 | setLayerPreference coverCell -isSelectable 0 532 | setLayerPreference block -isSelectable 0 533 | setLayerPreference io -isSelectable 0 534 | setLayerPreference areaIo -isSelectable 0 535 | setLayerPreference net -isSelectable 0 536 | setLayerPreference power -isSelectable 0 537 | setLayerPreference term -isSelectable 0 538 | setLayerPreference ruler -isSelectable 0 539 | setLayerPreference text -isSelectable 0 540 | setLayerPreference relFPlan -isSelectable 0 541 | setLayerPreference yieldCell -isSelectable 0 542 | setLayerPreference yieldMap -isSelectable 0 543 | setLayerPreference sdpConnect -isSelectable 0 544 | setLayerPreference densityMap -isSelectable 0 545 | setLayerPreference hinst -isSelectable 1 546 | setLayerPreference fence -isSelectable 1 547 | setLayerPreference guide -isSelectable 1 548 | setLayerPreference obstruct -isSelectable 1 549 | setLayerPreference region -isSelectable 1 550 | setLayerPreference screen -isSelectable 1 551 | setLayerPreference inst -isSelectable 1 552 | setLayerPreference stdCell -isSelectable 1 553 | setLayerPreference coverCell -isSelectable 1 554 | setLayerPreference block -isSelectable 1 555 | setLayerPreference io -isSelectable 1 556 | setLayerPreference areaIo -isSelectable 1 557 | setLayerPreference net -isSelectable 1 558 | setLayerPreference power -isSelectable 1 559 | setLayerPreference term -isSelectable 1 560 | setLayerPreference ruler -isSelectable 1 561 | setLayerPreference text -isSelectable 1 562 | setLayerPreference relFPlan -isSelectable 1 563 | setLayerPreference yieldCell -isSelectable 1 564 | setLayerPreference yieldMap -isSelectable 1 565 | setLayerPreference sdpConnect -isSelectable 1 566 | setLayerPreference densityMap -isSelectable 1 567 | setLayerPreference guide -isVisible 0 568 | setLayerPreference guide -isVisible 1 569 | setLayerPreference guide -isVisible 0 570 | setLayerPreference guide -isVisible 1 571 | setLayerPreference fence -isVisible 0 572 | setLayerPreference fence -isVisible 1 573 | setLayerPreference hinst -isVisible 0 574 | setLayerPreference hinst -isVisible 1 575 | setLayerPreference stdCell -isVisible 0 576 | setLayerPreference stdCell -isVisible 1 577 | setLayerPreference stdCell -isVisible 0 578 | setLayerPreference stdCell -isVisible 1 579 | zoomSelected 580 | fit 581 | viewSnapshot -dir {/home/icic/Desktop/lumos } -view {fplan amoeba place } 582 | createSnapshot -name snap 583 | Starting snapshot creation... 584 | setLayerPreference hinst -isVisible 0 585 | setLayerPreference fence -isVisible 0 586 | setLayerPreference guide -isVisible 0 587 | setLayerPreference obstruct -isVisible 0 588 | setLayerPreference region -isVisible 0 589 | setLayerPreference screen -isVisible 0 590 | setLayerPreference inst -isVisible 0 591 | setLayerPreference stdCell -isVisible 0 592 | setLayerPreference coverCell -isVisible 0 593 | setLayerPreference block -isVisible 0 594 | setLayerPreference io -isVisible 0 595 | setLayerPreference areaIo -isVisible 0 596 | setLayerPreference net -isVisible 0 597 | setLayerPreference power -isVisible 0 598 | setLayerPreference term -isVisible 0 599 | setLayerPreference ruler -isVisible 0 600 | setLayerPreference text -isVisible 0 601 | setLayerPreference relFPlan -isVisible 0 602 | setLayerPreference yieldCell -isVisible 0 603 | setLayerPreference yieldMap -isVisible 0 604 | setLayerPreference sdpConnect -isVisible 0 605 | setLayerPreference densityMap -isVisible 0 606 | setLayerPreference hinst -isVisible 1 607 | setLayerPreference fence -isVisible 1 608 | setLayerPreference guide -isVisible 1 609 | setLayerPreference obstruct -isVisible 1 610 | setLayerPreference region -isVisible 1 611 | setLayerPreference screen -isVisible 1 612 | setLayerPreference inst -isVisible 1 613 | setLayerPreference stdCell -isVisible 1 614 | setLayerPreference coverCell -isVisible 1 615 | setLayerPreference block -isVisible 1 616 | setLayerPreference io -isVisible 1 617 | setLayerPreference areaIo -isVisible 1 618 | setLayerPreference net -isVisible 1 619 | setLayerPreference power -isVisible 1 620 | setLayerPreference term -isVisible 1 621 | setLayerPreference ruler -isVisible 1 622 | setLayerPreference text -isVisible 1 623 | setLayerPreference relFPlan -isVisible 1 624 | setLayerPreference yieldCell -isVisible 1 625 | setLayerPreference yieldMap -isVisible 1 626 | setLayerPreference sdpConnect -isVisible 1 627 | setLayerPreference densityMap -isVisible 1 628 | setLayerPreference hinst -isVisible 0 629 | setLayerPreference fence -isVisible 0 630 | setLayerPreference guide -isVisible 0 631 | setLayerPreference obstruct -isVisible 0 632 | setLayerPreference region -isVisible 0 633 | setLayerPreference screen -isVisible 0 634 | setLayerPreference inst -isVisible 0 635 | setLayerPreference stdCell -isVisible 0 636 | setLayerPreference coverCell -isVisible 0 637 | setLayerPreference block -isVisible 0 638 | setLayerPreference io -isVisible 0 639 | setLayerPreference areaIo -isVisible 0 640 | setLayerPreference net -isVisible 0 641 | setLayerPreference power -isVisible 0 642 | setLayerPreference term -isVisible 0 643 | setLayerPreference ruler -isVisible 0 644 | setLayerPreference text -isVisible 0 645 | setLayerPreference relFPlan -isVisible 0 646 | setLayerPreference yieldCell -isVisible 0 647 | setLayerPreference yieldMap -isVisible 0 648 | setLayerPreference sdpConnect -isVisible 0 649 | setLayerPreference densityMap -isVisible 0 650 | setLayerPreference hinst -isVisible 1 651 | setLayerPreference fence -isVisible 1 652 | setLayerPreference guide -isVisible 1 653 | setLayerPreference obstruct -isVisible 1 654 | setLayerPreference region -isVisible 1 655 | setLayerPreference screen -isVisible 1 656 | setLayerPreference inst -isVisible 1 657 | setLayerPreference stdCell -isVisible 1 658 | setLayerPreference coverCell -isVisible 1 659 | setLayerPreference block -isVisible 1 660 | setLayerPreference io -isVisible 1 661 | setLayerPreference areaIo -isVisible 1 662 | setLayerPreference net -isVisible 1 663 | setLayerPreference power -isVisible 1 664 | setLayerPreference term -isVisible 1 665 | setLayerPreference ruler -isVisible 1 666 | setLayerPreference text -isVisible 1 667 | setLayerPreference relFPlan -isVisible 1 668 | setLayerPreference yieldCell -isVisible 1 669 | setLayerPreference yieldMap -isVisible 1 670 | setLayerPreference sdpConnect -isVisible 1 671 | setLayerPreference densityMap -isVisible 1 672 | 673 | *** Memory Usage v0.144 (Current mem = 223.031M, initial mem = 62.277M) *** 674 | --- Ending "First Encounter" (totcpu=0:00:06.2, real=0:03:53, mem=223.0M) --- 675 | -------------------------------------------------------------------------------- /Synthesis/encounter.log1: -------------------------------------------------------------------------------- 1 | Checking out Encounter license ... 2 | SOC_Encounter_GXL 8.1 license checkout succeeded. 3 | This Encounter release has been compiled with OA version 22.04-p032. 4 | sourcing /opt/Cadence/SOC8.1USR3/etc/fe/rdaDSL.tcl 5 | ******************************************************************* 6 | * Copyright (c) Cadence Design Systems, Inc. 1996 - 2008. * 7 | * All rights reserved. * 8 | * * 9 | * * 10 | * * 11 | * This program contains confidential and trade secret information * 12 | * of Cadence Design Systems, Inc. and is protected by copyright * 13 | * law and international treaties. Any reproduction, use, * 14 | * distribution or disclosure of this program or any portion of it,* 15 | * or any attempt to obtain a human-readable version of this * 16 | * program, without the express, prior written consent of * 17 | * Cadence Design Systems, Inc., is strictly prohibited. * 18 | * * 19 | * Cadence Design Systems, Inc. * 20 | * 2655 Seely Avenue * 21 | * San Jose, CA 95134, USA * 22 | * * 23 | * * 24 | ******************************************************************* 25 | 26 | @(#)CDS: First Encounter v08.10-p004_1 (32bit) 11/04/2008 14:34 (Linux 2.6) 27 | @(#)CDS: NanoRoute v08.10-p008 NR081027-0018/USR58-UB (database version 2.30, 67.1.1) {superthreading v1.11} 28 | @(#)CDS: CeltIC v08.10-p002_1 (32bit) 10/23/2008 22:04:14 (Linux 2.6.9-67.0.10.ELsmp) 29 | @(#)CDS: CTE v08.10-p016_1 (32bit) Oct 26 2008 15:11:51 (Linux 2.6.9-67.0.10.ELsmp) 30 | @(#)CDS: CPE v08.10-p009 31 | --- Starting "First Encounter v08.10-p004_1" on Wed Jun 6 02:45:36 2018 (mem=62.3M) --- 32 | --- Running on ICICVM.lab.edu (i686 w/Linux 2.6.9-78.EL) --- 33 | This version was compiled on Tue Nov 4 14:34:21 PST 2008. 34 | Set DBUPerIGU to 1000. 35 | Set Default Mode Total Cap Scale Factor to 1.00 36 | Set Detail Mode Total Cap Scale Factor to 1.00 37 | Set Coupling Total Cap Scale Factor to 1.00 38 | Set Total Res Scale Factor to 1.00 39 | Set net toggle Scale Factor to 1.00 40 | Set Shrink Factor to 1.00000 41 | Sourcing tcl/tk file "encounter.tcl" ... 42 | loadConfig ./encounter.conf 43 | Reading config file - ./encounter.conf 44 | 45 | Loading Lef file /home/icic/FreePDK45/osu_soc/lib/files/gscl45nm.lef... 46 | **WARN: (SOCLF-155): ViaRule only supports routing/cut layer, but poly layer found for viaRule 'M1_POLY', 47 | Set DBUPerIGU to M2 pitch 380. 48 | Initializing default via types and wire widths ... 49 | 50 | Power Planner/ViaGen version 8.1.45 promoted on 09/01/2008. 51 | viaInitial starts at Wed Jun 6 02:45:36 2018 52 | **WARN: (SOCPP-547): Cut 'contact' does not fit in viaRule 'M1_POLY'. 53 | viaInitial ends at Wed Jun 6 02:45:36 2018 54 | Reading netlist ... 55 | Backslashed names will retain backslash and a trailing blank character. 56 | Reading verilog netlist 'LUMOS.vh' 57 | Module Fixed_Point_Unit not defined. Created automatically. 58 | **WARN: (SOCVL-346): Module Fixed_Point_Unit is not defined in LEF files. It will be treated as an empty module. 59 | Undeclared bus operand_1 in module Fixed_Point_Unit ... created as [31:0]. 60 | Undeclared bus operand_2 in module Fixed_Point_Unit ... created as [31:0]. 61 | Undeclared bus operation in module Fixed_Point_Unit ... created as [1:0]. 62 | Undeclared bus result in module Fixed_Point_Unit ... created as [31:0]. 63 | 64 | *** Memory Usage v0.144 (Current mem = 196.332M, initial mem = 62.277M) *** 65 | *** End netlist parsing (cpu=0:00:00.0, real=0:00:00.0, mem=196.3M) *** 66 | Set top cell to LUMOS. 67 | Reading common timing library '/home/icic/FreePDK45/osu_soc/lib/files/gscl45nm.tlf' ... 68 | read 31 cells in library 'gscl45nm' 69 | *** End library_loading (cpu=0.00min, mem=0.3M, fe_cpu=0.04min, fe_mem=196.7M) *** 70 | Found empty module (Fixed_Point_Unit). 71 | Starting recursive module instantiation check. 72 | No recursion found. 73 | *****NEW dbFlattenCell is used. 74 | Flattening Cell LUMOS ... 75 | *** Netlist is unique. 76 | Set DBUPerIGU to techSite CoreSite width 760. 77 | ** info: there are 37 modules. 78 | ** info: there are 4032 stdCell insts. 79 | 80 | *** Memory Usage v0.144 (Current mem = 198.457M, initial mem = 62.277M) *** 81 | CTE reading timing constraint file 'LUMOS.sdc' ... 82 | INFO (CTE): constraints read successfully 83 | WARNING (CTE-25): Line: 8 of File LUMOS.sdc : Skipped unsupported command: set_units 84 | 85 | 86 | *** Read timing constraints (cpu=0:00:00.0 mem=202.1M) *** 87 | Total number of combinational cells: 25 88 | Total number of sequential cells: 4 89 | Total number of tristate cells: 2 90 | Total number of level shifter cells: 0 91 | Total number of power gating cells: 0 92 | Total number of isolation cells: 0 93 | Total number of power switch cells: 0 94 | Total number of pulse generator cells: 0 95 | Total number of always on buffers: 0 96 | Total number of retention cells: 0 97 | List of usable buffers: BUFX2 BUFX4 98 | Total number of usable buffers: 2 99 | List of unusable buffers: 100 | Total number of unusable buffers: 0 101 | List of usable inverters: INVX2 INVX1 INVX4 INVX8 102 | Total number of usable inverters: 4 103 | List of unusable inverters: 104 | Total number of unusable inverters: 0 105 | List of identified usable delay cells: CLKBUF1 CLKBUF2 CLKBUF3 106 | Total number of identified usable delay cells: 3 107 | List of identified unusable delay cells: 108 | Total number of identified unusable delay cells: 0 109 | *info: set bottom ioPad orient R0 110 | Horizontal Layer M1 offset = 190 (guessed) 111 | Vertical Layer M2 offset = 190 (guessed) 112 | Suggestion: specify LAYER OFFSET in LEF file 113 | Reason: hard to extract LAYER OFFSET from standard cells 114 | Set Using Default Delay Limit as 1000. 115 | Set Default Net Delay as 1000 ps. 116 | Set Default Net Load as 0.5 pF. 117 | Set Input Pin Transition Delay as 120 ps. 118 | **WARN: (SOCOPT-3465): The buffer cells were automatically identified. The command setBufFootPrint is ignored. If you want to use this manual setting, rerun encounter with dbgGPSAutoCellFunction set to 0. 119 | **WARN: (SOCOPT-3466): The inverter cells were automatically identified. The command setInvFootPrint is ignored. If you want to use this manual setting, rerun encounter with dbgGPSAutoCellFunction set to 0. 120 | **WARN: (SOCOPT-3467): The delay cells were automatically identified. The command setDelayFootPrint is ignored. If you want to use this manual setting, rerun encounter with dbgGPSAutoCellFunction set to 0. 121 | floorPlan -r 1.0 0.6 20 20 20 20 122 | Adjusting Core to Left to: 20.1400. Core to Bottom to: 20.1400. 123 | Horizontal Layer M1 offset = 190 (guessed) 124 | Vertical Layer M2 offset = 190 (guessed) 125 | Suggestion: specify LAYER OFFSET in LEF file 126 | Reason: hard to extract LAYER OFFSET from standard cells 127 | addRing -spacing_bottom 5 -width_left 5 -width_bottom 5 -width_top 5 -spacing_top 5 -layer_bottom metal5 -width_right 5 -around core -center 1 -layer_top metal5 -spacing_right 5 -spacing_left 5 -layer_right metal6 -layer_left metal6 -nets { gnd vdd } 128 | 129 | 130 | The power planner created 8 wires. 131 | 132 | amoebaPlace 133 | **WARN: (SOCSP-9007): The command 'amoebaPlace' is obsolete. It has been replaced by 'placeDesign'. 134 | Extracting standard cell pins and blockage ...... 135 | Pin and blockage extraction finished 136 | Extracting macro/IO cell pins and blockage ...... 137 | Pin and blockage extraction finished 138 | *** Starting "NanoPlace(TM) placement v0.845 (mem=203.1M)" ... 139 | Options: ignoreSpare pinGuide gpeffort=medium 140 | #std cell=4032 #block=0 (0 floating + 0 preplaced) #ioInst=0 #net=4007 #term=11658 #term/net=2.91, #fixedIo=0, #floatIo=0, #fixedPin=0, #floatPin=69 141 | stdCell: 4032 single + 0 double + 0 multi 142 | Total standard cell length = 4.1794 (mm), area = 0.0103 (mm^2) 143 | Design contains fractional cell. 144 | Average module density = 0.602. 145 | Density for the design = 0.602. 146 | = stdcell_area 10998 (10323 um^2) / alloc_area 18285 (17162 um^2). 147 | Pin Density = 1.060. 148 | = total # of pins 11658 / total Instance area 10998. 149 | Found multi-fanin net memoryData[31] 150 | Found multi-fanin net memoryData[30] 151 | Found multi-fanin net memoryData[29] 152 | Found multi-fanin net memoryData[28] 153 | Found multi-fanin net memoryData[27] 154 | Found multi-fanin net memoryData[26] 155 | Found multi-fanin net memoryData[25] 156 | Found multi-fanin net memoryData[24] 157 | Found multi-fanin net memoryData[23] 158 | Found multi-fanin net memoryData[22] 159 | ...... 160 | Found 32 (out of 4007) multi-fanin nets. 161 | Iteration 1: Total net bbox = 1.035e+04 (1.04e+04 0.00e+00) 162 | Est. stn bbox = 1.182e+04 (1.18e+04 0.00e+00) 163 | cpu = 0:00:00.0 real = 0:00:00.0 mem = 203.3M 164 | Iteration 2: Total net bbox = 2.428e+04 (1.01e+04 1.42e+04) 165 | Est. stn bbox = 2.915e+04 (1.15e+04 1.76e+04) 166 | cpu = 0:00:00.0 real = 0:00:00.0 mem = 203.3M 167 | Iteration 3: Total net bbox = 2.650e+04 (1.08e+04 1.57e+04) 168 | Est. stn bbox = 3.233e+04 (1.29e+04 1.95e+04) 169 | cpu = 0:00:00.1 real = 0:00:00.0 mem = 203.3M 170 | Iteration 4: Total net bbox = 3.366e+04 (1.26e+04 2.11e+04) 171 | Est. stn bbox = 4.045e+04 (1.46e+04 2.58e+04) 172 | cpu = 0:00:00.1 real = 0:00:00.0 mem = 203.3M 173 | Iteration 5: Total net bbox = 3.738e+04 (1.62e+04 2.12e+04) 174 | Est. stn bbox = 4.479e+04 (1.88e+04 2.60e+04) 175 | cpu = 0:00:00.0 real = 0:00:00.0 mem = 203.3M 176 | Iteration 6: Total net bbox = 4.103e+04 (1.62e+04 2.48e+04) 177 | Est. stn bbox = 4.878e+04 (1.89e+04 2.99e+04) 178 | cpu = 0:00:00.0 real = 0:00:01.0 mem = 203.3M 179 | Iteration 7: Total net bbox = 4.328e+04 (1.83e+04 2.50e+04) 180 | Est. stn bbox = 5.119e+04 (2.11e+04 3.01e+04) 181 | cpu = 0:00:00.0 real = 0:00:00.0 mem = 203.5M 182 | Iteration 8: Total net bbox = 4.623e+04 (1.83e+04 2.79e+04) 183 | Est. stn bbox = 5.451e+04 (2.12e+04 3.33e+04) 184 | cpu = 0:00:00.0 real = 0:00:00.0 mem = 203.5M 185 | Iteration 9: Total net bbox = 4.754e+04 (1.96e+04 2.79e+04) 186 | Est. stn bbox = 5.593e+04 (2.25e+04 3.34e+04) 187 | cpu = 0:00:00.1 real = 0:00:00.0 mem = 203.5M 188 | Iteration 10: Total net bbox = 4.985e+04 (1.96e+04 3.02e+04) 189 | Est. stn bbox = 5.839e+04 (2.26e+04 3.58e+04) 190 | cpu = 0:00:00.1 real = 0:00:00.0 mem = 203.6M 191 | Iteration 11: Total net bbox = 5.022e+04 (1.96e+04 3.06e+04) 192 | Est. stn bbox = 5.878e+04 (2.26e+04 3.62e+04) 193 | cpu = 0:00:00.0 real = 0:00:00.0 mem = 203.8M 194 | Iteration 12: Total net bbox = 5.538e+04 (2.39e+04 3.15e+04) 195 | Est. stn bbox = 6.409e+04 (2.69e+04 3.71e+04) 196 | cpu = 0:00:00.0 real = 0:00:00.0 mem = 203.8M 197 | *** cost = 5.538e+04 (2.39e+04 3.15e+04) (cpu for global=0:00:00.6) real=0:00:01.0*** 198 | Design contains fractional cell. 199 | Starting refinePlace ... 200 | Placement tweakage begins. 201 | wire length = 5.540e+04 = 2.390e+04 H + 3.150e+04 V 202 | wire length = 5.176e+04 = 2.080e+04 H + 3.097e+04 V 203 | Placement tweakage ends. 204 | Statistics of distance of Instance movement in detailed placement: 205 | maximum (X+Y) = 38.76 um 206 | inst (U1356) with max move: (135.66, 104.12) -> (101.84, 99.18) 207 | mean (X+Y) = 3.30 um 208 | Total instances moved : 2679 209 | *** cpu=0:00:00.1 mem=203.5M mem(used)=0.0M*** 210 | Total net length = 5.191e+04 (2.084e+04 3.107e+04) (ext = 2.815e+03) 211 | *** End of Placement (cpu=0:00:00.8, real=0:00:01.0, mem=203.5M) *** 212 | Design contains fractional cell. 213 | default core: bins with density > 0.75 = 8.33 % ( 3 / 36 ) 214 | Starting IO pin assignment... 215 | Completed IO pin assignment. 216 | sroute -noBlockPins -noPadRings 217 | **WARN: (SOCSR-4053): SRoute option "-noBlockPins" is obsolete and has been replaced by "-connect". The obsolete option still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your script to use "-connect". 218 | **WARN: (SOCSR-4053): SRoute option "-noPadRings" is obsolete and has been replaced by "-connect". The obsolete option still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your script to use "-connect". 219 | No routing obstructions were found in the design. 220 | *** Begin SPECIAL ROUTE on Wed Jun 6 02:45:38 2018 *** 221 | Sroute/fcroute version 8.1.45 promoted on 09/01/2008. 222 | SPECIAL ROUTE ran on directory: /home/icic/Desktop/lumos 223 | SPECIAL ROUTE ran on machine: ICICVM.lab.edu (Linux 2.6.9-78.EL i686 3.29Ghz) 224 | 225 | Begin option processing ... 226 | (from .sroute_9537.conf) srouteConnectPowerBump set to false 227 | (from .sroute_9537.conf) routeSpecial set to true 228 | (from .sroute_9537.conf) srouteConnectBlockPin set to false 229 | (from .sroute_9537.conf) srouteFollowCorePinEnd set to 3 230 | (from .sroute_9537.conf) srouteJogControl set to "preferWithChanges differentLayer" 231 | (from .sroute_9537.conf) sroutePadPinAllPorts set to true 232 | (from .sroute_9537.conf) sroutePreserveExistingRoutes set to true 233 | End option processing: cpu: 0:00:00, real: 0:00:00, peak: 372.00 megs. 234 | 235 | Reading LEF technology information... 236 | Reading floorplan and netlist information... 237 | Finished reading floorplan and netlist information. 238 | Read in 22 layers, 10 routing layers, 1 overlap layer 239 | Read in 33 macros, 25 used 240 | Read in 4032 components 241 | 4032 core components: 0 unplaced, 4032 placed, 0 fixed 242 | Read in 70 physical pins 243 | 70 physical pins: 0 unplaced, 70 placed, 0 fixed 244 | Read in 70 nets 245 | Read in 2 special nets, 2 routed 246 | Read in 8134 terminals 247 | Begin power routing ... 248 | **WARN: (SOCSR-1256): Net vdd does not have CORE class pad pins to be routed. 249 | Please check net list or port class. 250 | Net vdd does not have AREAIO class pad pins to be routed. 251 | Please check net list or port class. 252 | **WARN: (SOCSR-1256): Net gnd does not have CORE class pad pins to be routed. 253 | Please check net list or port class. 254 | Net gnd does not have AREAIO class pad pins to be routed. 255 | Please check net list or port class. 256 | CPU time for FollowPin 0 seconds 257 | CPU time for FollowPin 0 seconds 258 | Number of IO ports routed: 0 259 | Number of Stripe ports routed: 0 260 | Number of Core ports routed: 108 261 | Number of Followpin connections: 54 262 | End power routing: cpu: 0:00:00, real: 0:00:01, peak: 383.00 megs. 263 | 264 | 265 | 266 | Begin updating DB with routing results ... 267 | Updating DB with 70 io pins ... 268 | Updating DB with 20 via definition ... 269 | 270 | sroute post-processing starts at Wed Jun 6 02:45:39 2018 271 | The viaGen is rebuilding shadow vias for net gnd. 272 | sroute post-processing ends at Wed Jun 6 02:45:39 2018 273 | 274 | sroute post-processing starts at Wed Jun 6 02:45:39 2018 275 | The viaGen is rebuilding shadow vias for net vdd. 276 | sroute post-processing ends at Wed Jun 6 02:45:39 2018 277 | 278 | 279 | sroute: Total CPU time used = 0:0:0 280 | sroute: Total Real time used = 0:0:1 281 | sroute: Total Memory used = 1.50 megs 282 | sroute: Total Peak Memory used = 204.99 megs 283 | trialRoute 284 | *** Starting trialRoute (mem=205.0M) *** 285 | 286 | There are 0 pin guide points passed to trialRoute. 287 | Options: -noPinGuide 288 | 289 | routingBox: (0 0) (343140 342100) 290 | coreBox: (40280 40280) (303140 302100) 291 | Number of multi-gpin terms=87, multi-gpins=179, moved blk term=0/0 292 | 293 | Phase 1a route (0:00:00.0 206.5M): 294 | Est net length = 5.794e+04um = 2.509e+04H + 3.284e+04V 295 | Usage: (11.3%H 14.0%V) = (2.924e+04um 5.707e+04um) = (30287 23179) 296 | Obstruct: 0 = 0 (0.0%H) + 0 (0.0%V) 297 | Overflow: 0 = 0 (0.00% H) + 0 (0.00% V) 298 | 299 | Phase 1b route (0:00:00.0 207.8M): 300 | Usage: (11.3%H 14.0%V) = (2.918e+04um 5.707e+04um) = (30220 23179) 301 | Overflow: 0 = 0 (0.00% H) + 0 (0.00% V) 302 | 303 | Phase 1c route (0:00:00.0 207.8M): 304 | Usage: (11.3%H 14.0%V) = (2.914e+04um 5.702e+04um) = (30181 23160) 305 | Overflow: 0 = 0 (0.00% H) + 0 (0.00% V) 306 | 307 | Phase 1d route (0:00:00.0 207.8M): 308 | Usage: (11.3%H 14.0%V) = (2.914e+04um 5.702e+04um) = (30181 23160) 309 | Overflow: 0 = 0 (0.00% H) + 0 (0.00% V) 310 | 311 | Phase 1e route (0:00:00.0 208.4M): 312 | Usage: (11.3%H 14.0%V) = (2.914e+04um 5.702e+04um) = (30181 23160) 313 | Overflow: 0 = 0 (0.00% H) + 0 (0.00% V) 314 | 315 | Usage: (11.3%H 14.0%V) = (2.914e+04um 5.702e+04um) = (30181 23160) 316 | Overflow: 0 = 0 (0.00% H) + 0 (0.00% V) 317 | 318 | Congestion distribution: 319 | 320 | Remain cntH cntV 321 | -------------------------------------- 322 | -------------------------------------- 323 | 2: 0 0.00% 3 0.03% 324 | 3: 0 0.00% 116 0.98% 325 | 4: 0 0.00% 184 1.55% 326 | 5: 0 0.00% 286 2.41% 327 | 6: 0 0.00% 377 3.18% 328 | 7: 0 0.00% 560 4.73% 329 | 8: 0 0.00% 805 6.79% 330 | 9: 0 0.00% 1060 8.95% 331 | 10: 0 0.00% 1258 10.62% 332 | 11: 0 0.00% 1240 10.46% 333 | 12: 605 5.11% 1680 14.18% 334 | 13: 909 7.67% 1641 13.85% 335 | 14: 11 0.09% 784 6.62% 336 | 15: 320 2.70% 520 4.39% 337 | 16: 234 1.97% 462 3.90% 338 | 17: 463 3.91% 22 0.19% 339 | 18: 857 7.23% 0 0.00% 340 | 19: 850 7.17% 0 0.00% 341 | 20: 7601 64.14% 852 7.19% 342 | 343 | 344 | *** Memory Usage v0.144 (Current mem = 211.449M, initial mem = 62.277M) *** 345 | Phase 1l route (0:00:00.0 207.4M): 346 | 347 | 348 | *** After '-updateRemainTrks' operation: 349 | 350 | Usage: (11.6%H 14.6%V) = (2.995e+04um 5.920e+04um) = (31024 24042) 351 | Overflow: 0 = 0 (0.00% H) + 0 (0.00% V) 352 | 353 | Congestion distribution: 354 | 355 | Remain cntH cntV 356 | -------------------------------------- 357 | -------------------------------------- 358 | 0: 0 0.00% 2 0.02% 359 | 1: 0 0.00% 2 0.02% 360 | 2: 0 0.00% 6 0.05% 361 | 3: 0 0.00% 141 1.19% 362 | 4: 0 0.00% 210 1.77% 363 | 5: 0 0.00% 344 2.90% 364 | 6: 0 0.00% 403 3.40% 365 | 7: 0 0.00% 567 4.78% 366 | 8: 0 0.00% 812 6.85% 367 | 9: 0 0.00% 1013 8.55% 368 | 10: 0 0.00% 1199 10.12% 369 | 11: 0 0.00% 1219 10.29% 370 | 12: 605 5.11% 1659 14.00% 371 | 13: 909 7.67% 1641 13.85% 372 | 14: 15 0.13% 779 6.57% 373 | 15: 327 2.76% 517 4.36% 374 | 16: 244 2.06% 462 3.90% 375 | 17: 488 4.12% 22 0.19% 376 | 18: 894 7.54% 0 0.00% 377 | 19: 869 7.33% 0 0.00% 378 | 20: 7499 63.28% 852 7.19% 379 | 380 | 381 | 382 | *** Completed Phase 1 route (0:00:00.1 206.1M) *** 383 | 384 | 385 | Total length: 6.173e+04um, number of vias: 23442 386 | M1(H) length: 8.082e+02um, number of vias: 11294 387 | M2(V) length: 2.397e+04um, number of vias: 10296 388 | M3(H) length: 2.462e+04um, number of vias: 1592 389 | M4(V) length: 1.050e+04um, number of vias: 135 390 | M5(H) length: 2.481e+02um, number of vias: 121 391 | M6(V) length: 1.577e+03um, number of vias: 3 392 | M7(H) length: 2.300e-01um, number of vias: 1 393 | M8(V) length: 9.050e-01um, number of vias: 0 394 | M9(H) length: 0.000e+00um, number of vias: 0 395 | M10(V) length: 0.000e+00um 396 | *** Completed Phase 2 route (0:00:00.1 208.0M) *** 397 | 398 | *** Finished all Phases (cpu=0:00:00.2 mem=208.0M) *** 399 | Peak Memory Usage was 211.4M 400 | *** Finished trialRoute (cpu=0:00:00.2 mem=208.0M) *** 401 | 402 | buildTimingGraph 403 | setCteReport 404 | WARNING: The reportTA command is obsolete. To generate a timing report that 405 | provides information about the various paths in the design, use the 406 | report_timing command. 407 | 408 | report_timing -nworst 10 -net -late > timing.rep.1.placed 409 | Default RC Extraction called for design LUMOS. 410 | RCMode: Default 411 | Capacitance Scaling Factor : 1.00000 412 | Coupling Cap. Scaling Factor : 1.00000 413 | Resistance Scaling Factor : 1.00000 414 | Shrink Factor : 1.00000 415 | Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets. 416 | Using detail cap. scale factor for clock nets. 417 | Default RC Extraction DONE (CPU Time: 0:00:00.0 Real Time: 0:00:00.0 MEM: 210.961M) 418 | Calculate delays in Single mode... 419 | Topological Sorting (CPU = 0:00:00.0, MEM = 220.5M) 420 | Number of Loop : 0 421 | Start delay calculation (mem=220.484M)... 422 | **WARN: (SOCEXT-2882): Unable to find resistance for via 'M3_M2_via' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms. 423 | **WARN: (SOCEXT-2882): Unable to find resistance for via 'M2_M1_via' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms. 424 | **WARN: (SOCEXT-2882): Unable to find resistance for via 'M4_M3_via' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms. 425 | **WARN: (SOCEXT-2882): Unable to find resistance for via 'M5_M4_via' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms. 426 | **WARN: (SOCEXT-2882): Unable to find resistance for via 'M6_M5_via' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms. 427 | **WARN: (SOCEXT-2882): Unable to find resistance for via 'M7_M6_via' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms. 428 | **WARN: (SOCEXT-2882): Unable to find resistance for via 'M8_M7_via' in capacitance table or LEF files. Check the capacitance table and LEF files. Assigning default value of 4.0 ohms. 429 | Delay calculation completed. 430 | (0:00:00.1 220.484M 0) 431 | *** CDM Built up (cpu=0:00:00.1 mem= 220.5M) *** 432 | *** reportTA (0:00:00.2) *** 433 | **ERROR: (SOCSYT-6692): [encounter.tcl]: Invalid return code while executing "encounter.tcl" 434 | **ERROR: (SOCSYT-6693): invalid command name "setIPOMode" 435 | fit 436 | XWindow dump put in file snap 437 | XWindow dump put in file snap.xwd 438 | 439 | *** Memory Usage v0.144 (Current mem = 222.270M, initial mem = 62.277M) *** 440 | --- Ending "First Encounter" (totcpu=0:00:04.1, real=0:05:53, mem=222.3M) --- 441 | -------------------------------------------------------------------------------- /Synthesis/encounter.tcl: -------------------------------------------------------------------------------- 1 | ################################### 2 | # Run the design through Encounter 3 | ################################### 4 | 5 | # Setup design and create floorplan 6 | loadConfig ./encounter.conf 7 | #commitConfig 8 | 9 | # Create Initial Floorplan 10 | floorplan -r 1.0 0.6 20 20 20 20 11 | 12 | # Create Power structures 13 | addRing -spacing_bottom 5 -width_left 5 -width_bottom 5 -width_top 5 -spacing_top 5 -layer_bottom metal5 -width_right 5 -around core -center 1 -layer_top metal5 -spacing_right 5 -spacing_left 5 -layer_right metal6 -layer_left metal6 -nets { gnd vdd } 14 | 15 | # Place standard cells 16 | amoebaPlace 17 | 18 | # Route power nets 19 | sroute -noBlockPins -noPadRings 20 | 21 | # Perform trial route and get initial timing results 22 | trialroute 23 | buildTimingGraph 24 | setCteReport 25 | reportTA -nworst 10 -net > timing.rep.1.placed 26 | 27 | # Run in-place optimization 28 | # to fix setup problems 29 | setIPOMode -mediumEffort -fixDRC -addPortAsNeeded 30 | initECO ./ipo1.txt 31 | fixSetupViolation 32 | endECO 33 | buildTimingGraph 34 | setCteReport 35 | reportTA -nworst 10 -net > timing.rep.2.ipo1 36 | 37 | # Run Clock Tree Synthesis 38 | createClockTreeSpec -output encounter.cts -bufFootprint buf -invFootprint inv 39 | specifyClockTree -clkfile encounter.cts 40 | ckSynthesis -rguide cts.rguide -report report.ctsrpt -macromodel report.ctsmdl -fix_added_buffers 41 | 42 | # Output Results of CTS 43 | trialRoute -highEffort -guide cts.rguide 44 | extractRC 45 | reportClockTree -postRoute -localSkew -report skew.post_troute_local.ctsrpt 46 | reportClockTree -postRoute -report report.post_troute.ctsrpt 47 | 48 | # Run Post-CTS Timing analysis 49 | setAnalysisMode -setup -async -skew -autoDetectClockTree 50 | buildTimingGraph 51 | setCteReport 52 | reportTA -nworst 10 -net > timing.rep.3.cts 53 | 54 | # Perform post-CTS IPO 55 | setIPOMode -highEffort -fixDrc -addPortAsNeeded -incrTrialRoute -restruct -topomap 56 | initECO ipo2.txt 57 | setExtractRCMode -default -assumeMetFill 58 | extractRC 59 | fixSetupViolation -guide cts.rguide 60 | 61 | # Fix all remaining violations 62 | setExtractRCMode -detail -assumeMetFill 63 | extractRC 64 | if {[isDRVClean -maxTran -maxCap -maxFanout] != 1} { 65 | fixDRCViolation -maxTran -maxCap -maxFanout 66 | } 67 | 68 | endECO 69 | cleanupECO 70 | 71 | # Run Post IPO-2 timing analysis 72 | buildTimingGraph 73 | setCteReport 74 | reportTA -nworst 10 -net > timing.rep.4.ipo2 75 | 76 | # Add filler cells 77 | addFiller -cell FILL -prefix FILL -fillBoundary 78 | 79 | # Connect all new cells to VDD/GND 80 | globalNetConnect vdd -type tiehi 81 | globalNetConnect vdd -type pgpin -pin vdd -override 82 | 83 | globalNetConnect gnd -type tielo 84 | globalNetConnect gnd -type pgpin -pin gnd -override 85 | 86 | # Run global Routing 87 | globalDetailRoute 88 | 89 | # Get final timing results 90 | setExtractRCMode -detail -noReduce 91 | extractRC 92 | buildTimingGraph 93 | setCteReport 94 | reportTA -nworst 10 -net > timing.rep.5.final 95 | 96 | # Output GDSII 97 | streamOut final.gds2 -mapFile gds2_encounter.map -stripes 1 -units 1000 -mode ALL 98 | saveNetlist -excludeLeafCell final.v 99 | 100 | # Output DSPF RC Data 101 | rcout -spf final.dspf 102 | 103 | # Run DRC and Connection checks 104 | verifyGeometry 105 | verifyConnectivity -type all 106 | 107 | win 108 | 109 | puts "**************************************" 110 | puts "* Encounter script finished *" 111 | puts "* *" 112 | puts "* Results: *" 113 | puts "* -------- *" 114 | puts "* Layout: final.gds2 *" 115 | puts "* Netlist: final.v *" 116 | puts "* Timing: timing.rep.5.final *" 117 | puts "* *" 118 | puts "* Type 'exit' to quit *" 119 | puts "* *" 120 | puts "**************************************" 121 | -------------------------------------------------------------------------------- /Synthesis/reports/area.rep: -------------------------------------------------------------------------------- 1 | Warning: Design 'LUMOS' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) 2 | 3 | **************************************** 4 | Report : area 5 | Design : LUMOS 6 | Version: C-2009.06-SP5 7 | Date : Wed Jun 6 02:40:33 2018 8 | **************************************** 9 | 10 | Library(s) Used: 11 | 12 | gscl45nm (File: /home/icic/FreePDK45/osu_soc/lib/files/gscl45nm.db) 13 | 14 | Number of ports: 70 15 | Number of nets: 4150 16 | Number of cells: 3907 17 | Number of references: 28 18 | 19 | Combinational area: 8071.490544 20 | Noncombinational area: 3447.947055 21 | Net Interconnect area: undefined (No wire load specified) 22 | 23 | Total cell area: 11519.437599 24 | Total area: undefined 25 | 26 | Information: This design contains black box (unknown) components. (RPT-8) 27 | 1 28 | -------------------------------------------------------------------------------- /Synthesis/reports/power.rep: -------------------------------------------------------------------------------- 1 | Loading db file '/home/icic/FreePDK45/osu_soc/lib/files/gscl45nm.db' 2 | Information: Propagating switching activity (low effort zero delay simulation). (PWR-6) 3 | Warning: Design has unannotated primary inputs. (PWR-414) 4 | Warning: Design has unannotated sequential cell outputs. (PWR-415) 5 | Warning: Design has unannotated black-box outputs. (PWR-428) 6 | 7 | **************************************** 8 | Report : power 9 | -analysis_effort low 10 | Design : LUMOS 11 | Version: C-2009.06-SP5 12 | Date : Wed Jun 6 02:40:33 2018 13 | **************************************** 14 | 15 | 16 | Library(s) Used: 17 | 18 | gscl45nm (File: /home/icic/FreePDK45/osu_soc/lib/files/gscl45nm.db) 19 | 20 | 21 | Operating Conditions: typical Library: gscl45nm 22 | Wire Load Model Mode: top 23 | 24 | 25 | Global Operating Voltage = 1.1 26 | Power-specific unit information : 27 | Voltage Units = 1V 28 | Capacitance Units = 1.000000pf 29 | Time Units = 1ns 30 | Dynamic Power Units = 1mW (derived from V,C,T units) 31 | Leakage Power Units = 1nW 32 | 33 | 34 | Cell Internal Power = 2.2655 mW (74%) 35 | Net Switching Power = 815.6647 uW (26%) 36 | --------- 37 | Total Dynamic Power = 3.0812 mW (100%) 38 | 39 | Cell Leakage Power = 56.2227 uW 40 | 41 | 1 42 | -------------------------------------------------------------------------------- /Synthesis/reports/timing.rep: -------------------------------------------------------------------------------- 1 | Warning: Design 'LUMOS' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341) 2 | 3 | **************************************** 4 | Report : timing 5 | -path full 6 | -delay max 7 | -max_paths 1 8 | Design : LUMOS 9 | Version: C-2009.06-SP5 10 | Date : Wed Jun 6 02:40:33 2018 11 | **************************************** 12 | 13 | Operating Conditions: typical Library: gscl45nm 14 | Wire Load Model Mode: top 15 | 16 | Startpoint: ir_tri_enable_reg[12] 17 | (rising edge-triggered flip-flop clocked by clk) 18 | Endpoint: aluZeroRegister_reg 19 | (rising edge-triggered flip-flop clocked by clk) 20 | Path Group: clk 21 | Path Type: max 22 | 23 | Point Incr Path 24 | -------------------------------------------------------------------------- 25 | clock clk (rise edge) 0.000 0.000 26 | clock network delay (ideal) 0.000 0.000 27 | ir_tri_enable_reg[12]/CLK (DFFPOSX1) 0.000 0.000 r 28 | ir_tri_enable_reg[12]/Q (DFFPOSX1) 0.103 0.103 f 29 | U3878/Y (INVX1) 0.010 0.113 r 30 | ir_tri[12]/Y (TBUFX2) 0.057 0.170 r 31 | U2892/Y (OR2X2) 0.050 0.220 r 32 | U2782/Y (INVX1) 0.018 0.238 f 33 | U2821/Y (MUX2X1) 0.041 0.279 r 34 | U4415/Y (NAND3X1) 0.017 0.296 f 35 | U3248/Y (INVX1) 0.001 0.296 r 36 | U3249/Y (INVX1) 0.014 0.311 f 37 | U4416/Y (AOI22X1) 0.038 0.349 r 38 | U2910/Y (BUFX2) 0.035 0.384 r 39 | U2895/Y (AND2X2) 0.033 0.417 r 40 | U2211/Y (INVX2) 0.025 0.442 f 41 | U4417/Y (NOR3X1) 0.060 0.502 r 42 | U1852/Y (BUFX2) 0.038 0.540 r 43 | U3871/Y (INVX1) 0.017 0.557 f 44 | U4430/Y (AOI21X1) 0.017 0.574 r 45 | U2730/Y (BUFX2) 0.054 0.628 r 46 | aluOperation_tri[3]/Y (TBUFX2) 0.085 0.713 f 47 | U1383/Y (NOR3X1) 0.192 0.904 r 48 | U3283/Y (AND2X2) 0.177 1.082 r 49 | U2276/Y (INVX2) 0.116 1.197 f 50 | U2088/Y (OAI21X1) 0.061 1.258 r 51 | U1909/Y (AND2X2) 0.032 1.290 r 52 | U1910/Y (INVX1) 0.015 1.305 f 53 | U1978/Y (AND2X2) 0.037 1.342 f 54 | U1979/Y (INVX1) -0.002 1.339 r 55 | U2087/Y (AOI21X1) 0.007 1.347 f 56 | U1933/Y (BUFX2) 0.034 1.380 f 57 | U2086/Y (OAI21X1) 0.016 1.397 r 58 | U2085/Y (AOI21X1) 0.019 1.416 f 59 | U2032/Y (BUFX2) 0.037 1.453 f 60 | arithmetic_logic_unit/result_tri[8]/Y (TBUFX2) 0.037 1.490 r 61 | U1697/Y (NOR3X1) 0.047 1.538 f 62 | U1700/Y (NAND3X1) 0.041 1.579 r 63 | U1704/Y (BUFX2) 0.036 1.615 r 64 | U1709/Y (NOR3X1) 0.026 1.641 f 65 | U1711/Y (NAND3X1) 0.036 1.676 r 66 | U1712/Y (BUFX2) 0.036 1.712 r 67 | U1715/Y (NOR3X1) 0.025 1.737 f 68 | U1716/Y (NAND3X1) 0.041 1.778 r 69 | U1717/Y (BUFX2) 0.036 1.814 r 70 | U1720/Y (NOR3X1) 0.025 1.840 f 71 | U1721/Y (NAND3X1) 0.041 1.880 r 72 | U1722/Y (BUFX2) 0.036 1.916 r 73 | U1724/Y (NOR3X1) 0.024 1.940 f 74 | aluZeroRegister_reg/D (DFFPOSX1) 0.000 1.940 f 75 | data arrival time 1.940 76 | 77 | clock clk (rise edge) 2.000 2.000 78 | clock network delay (ideal) 0.000 2.000 79 | aluZeroRegister_reg/CLK (DFFPOSX1) 0.000 2.000 r 80 | library setup time -0.060 1.940 81 | data required time 1.940 82 | -------------------------------------------------------------------------- 83 | data required time 1.940 84 | data arrival time -1.940 85 | -------------------------------------------------------------------------- 86 | slack (MET) 0.000 87 | 88 | 89 | 1 90 | -------------------------------------------------------------------------------- /Synthesis/snap.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/17fc2dbf9701825f7623881393df2a6082481dd3/Synthesis/snap.png -------------------------------------------------------------------------------- /Synthesis/snap.xwd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/IUST-Computer-Organization/LUMOS/17fc2dbf9701825f7623881393df2a6082481dd3/Synthesis/snap.xwd -------------------------------------------------------------------------------- /gtkwave.ini: -------------------------------------------------------------------------------- 1 | # 2 | # sample rc file 3 | # (rename to .gtkwaverc and copy 4 | # to home directory to be loaded automatically) 5 | # 6 | 7 | # NOTE: env var GTKWAVE_EDITOR can also be used for this, however the rc file overrides it 8 | # %d is line number (can be combined inside a string as shown for vimx) 9 | # %s is filename (must stand by itself, can't add anything to it) 10 | # 11 | # editor "vimx -g +%d %s" 12 | # editor "gedit +%d %s" 13 | # editor "emacs +%d %s" 14 | 15 | # For OSX 16 | # editor "mate -l %d %s" 17 | 18 | dragzoom_threshold 0 19 | sst_dbl_action_type insert 20 | 21 | use_standard_trace_select no 22 | highlight_wavewindow no 23 | fill_waveform no 24 | alt_wheel_mode yes 25 | vcd_preserve_glitches no 26 | vcd_preserve_glitches_real no 27 | 28 | ignore_savefile_pane_pos no 29 | ignore_savefile_pos no 30 | ignore_savefile_size no 31 | 32 | ruler_origin 0 33 | ruler_step 0 34 | disable_ae2_alias no 35 | keep_xz_colors no 36 | disable_auto_comphier no 37 | 38 | strace_repeat_count 1 39 | enable_fast_exit yes 40 | disable_empty_gui off 41 | analog_redraw_skip_count 20 42 | splash_disable off 43 | hide_sst off 44 | sst_dynamic_filter on 45 | use_standard_clicking on 46 | use_toolbutton_interface on 47 | use_pango_fonts on 48 | use_scrollwheel_as_y off 49 | scale_to_time_dimension * 50 | zoom_dynamic off 51 | zoom_dynamic_end off 52 | 53 | vlist_spill off 54 | vlist_prepack off 55 | vlist_compression 4 56 | 57 | hier_max_level 1 58 | force_toolbars 0 59 | #cursor_snap 8 60 | zoom_pow10_snap on 61 | 62 | dynamic_resizing 1 63 | hpane_pack 1 64 | #initial_window_x 1000 65 | #initial_window_y 600 66 | #initial_window_xpos 50 67 | #initial_window_ypos 50 68 | 69 | use_maxtime_display 0 70 | 71 | enable_vcd_autosave 0 72 | use_roundcaps 1 73 | 74 | use_nonprop_fonts yes 75 | enable_horiz_grid yes 76 | use_big_fonts no 77 | constant_marker_update yes 78 | show_grid yes 79 | show_base_symbols no 80 | 81 | atomic_vectors yes 82 | vcd_explicit_zero_subscripts no 83 | 84 | disable_mouseover no 85 | clipboard_mouseover yes 86 | 87 | 88 | # 89 | # color additions 90 | # 91 | color_back 000000 92 | color_baseline ffffff 93 | color_grid 202070 94 | color_grid2 6a5acd 95 | color_high 79f6f2 96 | color_highfill 4ca09d 97 | color_low 5dbebb 98 | color_1 00ff00 99 | color_1fill 004d00 100 | color_0 008000 101 | color_trans 00c000 102 | color_mid c0c000 103 | 104 | color_value ffffff 105 | color_vbox 00ff00 106 | color_vtrans 00c000 107 | 108 | color_x ff0000 109 | color_xfill 400000 110 | color_u cc0000 111 | color_ufill 200000 112 | color_w 79f6f2 113 | color_wfill 3f817f 114 | color_dash edf508 115 | color_dashfill 7d8104 116 | 117 | color_umark ff8080 118 | color_mark ffff80 119 | 120 | color_time ffffff 121 | color_timeb 000000 122 | 123 | color_brkred cc0000 124 | color_ltblue 5dbebb 125 | color_gmstrd 7d8104 126 | 127 | 128 | # 129 | # menu accelerators 130 | # 131 | accel "/File/Open New Window" N 132 | accel "/File/Open New Tab" T 133 | accel "/File/Reload Waveform" R 134 | accel "/File/Export/Write VCD File As" (null) 135 | accel "/File/Export/Write LXT File As" (null) 136 | accel "/File/Export/Write TIM File As" (null) 137 | accel "/File/Close" W 138 | accel "/File/" (null) 139 | accel "/File/Print To File" P 140 | accel "/File/Grab To File" (null) 141 | accel "/File/" (null) 142 | accel "/File/Read Save File" O 143 | accel "/File/Write Save File" S 144 | accel "/File/Write Save File As" S 145 | accel "/File/" (null) 146 | accel "/File/Read Sim Logfile" L 147 | accel "/File/" (null) 148 | accel "/File/Read Verilog Stemsfile" (null) 149 | accel "/File/" (null) 150 | accel "/File/Read Tcl Script File" (null) 151 | accel "/File/" (null) 152 | accel "/File/Quit" Q 153 | accel "/Edit/Set Trace Max Hier" (null) 154 | accel "/Edit/Toggle Trace Hier" H 155 | accel "/Edit/" (null) 156 | accel "/Edit/Insert Blank" B 157 | accel "/Edit/Insert Comment" (null) 158 | accel "/Edit/Insert Analog Height Extension" (null) 159 | accel "/Edit/Cut" X 160 | accel "/Edit/Copy" C 161 | accel "/Edit/Paste" V 162 | accel "/Edit/Delete" Delete 163 | accel "/Edit/" (null) 164 | accel "/Edit/Alias Highlighted Trace" A 165 | accel "/Edit/Remove Highlighted Aliases" A 166 | accel "/Edit/" (null) 167 | accel "/Edit/Expand" F3 168 | accel "/Edit/Combine Down" F4 169 | accel "/Edit/Combine Up" F5 170 | accel "/Edit/" (null) 171 | accel "/Edit/Data Format/Hex" X 172 | accel "/Edit/Data Format/Decimal" D 173 | accel "/Edit/Data Format/Signed Decimal" (null) 174 | accel "/Edit/Data Format/Binary" B 175 | accel "/Edit/Data Format/Octal" O 176 | accel "/Edit/Data Format/ASCII" (null) 177 | accel "/Edit/Data Format/Time", (null) 178 | accel "/Edit/Data Format/Enum", (null) 179 | accel "/Edit/Data Format/BitsToReal" (null) 180 | accel "/Edit/Data Format/RealToBits/On" (null) 181 | accel "/Edit/Data Format/RealToBits/Off" (null) 182 | accel "/Edit/Data Format/Right Justify/On" J 183 | accel "/Edit/Data Format/Right Justify/Off" J 184 | accel "/Edit/Data Format/Invert/On" I 185 | accel "/Edit/Data Format/Invert/Off" I 186 | accel "/Edit/Data Format/Reverse Bits/On" V 187 | accel "/Edit/Data Format/Reverse Bits/Off" V 188 | accel "/Edit/Data Format/Translate Filter File/Disable" (null) 189 | accel "/Edit/Data Format/Translate Filter File/Enable and Select" (null) 190 | accel "/Edit/Data Format/Translate Filter Process/Disable" (null) 191 | accel "/Edit/Data Format/Translate Filter Process/Enable and Select" (null) 192 | accel "/Edit/Data Format/Transaction Filter Process/Disable" (null) 193 | accel "/Edit/Data Format/Transaction Filter Process/Enable and Select" (null) 194 | accel "/Edit/Data Format/Analog/Off" (null) 195 | accel "/Edit/Data Format/Analog/Step" (null) 196 | accel "/Edit/Data Format/Analog/Interpolated" (null) 197 | accel "/Edit/Data Format/Analog/Interpolated Annotated" (null) 198 | accel "/Edit/Data Format/Analog/Resizing/Screen Data" (null) 199 | accel "/Edit/Data Format/Analog/Resizing/All Data" (null) 200 | accel "/Edit/Data Format/Range Fill/With 0s" (null) 201 | accel "/Edit/Data Format/Range Fill/With 1s" (null) 202 | accel "/Edit/Data Format/Range Fill/Off" (null) 203 | accel "/Edit/Data Format/Gray Filters/To Gray" (null) 204 | accel "/Edit/Data Format/Gray Filters/From Gray" (null) 205 | accel "/Edit/Data Format/Gray Filters/None" (null) 206 | accel "/Edit/Color Format/Normal" (null) 207 | accel "/Edit/Color Format/Red" (null) 208 | accel "/Edit/Color Format/Orange" (null) 209 | accel "/Edit/Color Format/Yellow" (null) 210 | accel "/Edit/Color Format/Green" (null) 211 | accel "/Edit/Color Format/Blue" (null) 212 | accel "/Edit/Color Format/Indigo" (null) 213 | accel "/Edit/Color Format/Violet" (null) 214 | accel "/Edit/Color Format/Cycle" (null) 215 | accel "/Edit/Color Format/" (null) 216 | accel "/Edit/Color Format/Keep xz Colors" (null) 217 | accel "/Edit/Show-Change All Highlighted" (null) 218 | accel "/Edit/Show-Change First Highlighted" F 219 | accel "/Edit/" (null) 220 | accel "/Edit/Time Warp/Warp Marked" (null) 221 | accel "/Edit/Time Warp/Unwarp Marked" (null) 222 | accel "/Edit/Time Warp/Unwarp All" (null) 223 | accel "/Edit/" (null) 224 | accel "/Edit/Exclude" E 225 | accel "/Edit/Show" S 226 | accel "/Edit/" (null) 227 | accel "/Edit/Toggle Group Open|Close" T 228 | accel "/Edit/Create Group" G 229 | accel "/Edit/" (null) 230 | accel "/Edit/Highlight Regexp" R 231 | accel "/Edit/UnHighlight Regexp" R 232 | accel "/Edit/Highlight All" A 233 | accel "/Edit/UnHighlight All" A 234 | accel "/Edit/" (null) 235 | accel "/Edit/Sort/Alphabetize All" (null) 236 | accel "/Edit/Sort/Alphabetize All (CaseIns)" (null) 237 | accel "/Edit/Sort/Sigsort All" (null) 238 | accel "/Edit/Sort/Reverse All" (null) 239 | accel "/Search/Pattern Search 1" (null) 240 | accel "/Search/Pattern Search 2" (null) 241 | accel "/Search/" (null) 242 | accel "/Search/Signal Search Regexp" S 243 | accel "/Search/Signal Search Hierarchy" T 244 | accel "/Search/Signal Search Tree" T 245 | accel "/Search/" (null) 246 | accel "/Search/Open Source Definition" (null) 247 | accel "/Search/Open Source Instantiation" (null) 248 | accel "/Search/Open Scope" (null) 249 | accel "/Search/" (null) 250 | accel "/Search/Autocoalesce" (null) 251 | accel "/Search/Autocoalesce Reversal" (null) 252 | accel "/Search/Autoname Bundles" (null) 253 | accel "/Search/Search Hierarchy Grouping" (null) 254 | accel "/Search/" (null) 255 | accel "/Search/Set Pattern Search Repeat Count" (null) 256 | accel "/Time/Move To Time" F1 257 | accel "/Time/Zoom/Zoom Amount" F2 258 | accel "/Time/Zoom/Zoom Base" F2 259 | accel "/Time/Zoom/Zoom In" plus 260 | accel "/Time/Zoom/Zoom Out" minus 261 | accel "/Time/Zoom/Zoom Full" 0 262 | accel "/Time/Zoom/Zoom Best Fit" F 263 | accel "/Time/Zoom/Zoom To Start" Home 264 | accel "/Time/Zoom/Zoom To End" End 265 | accel "/Time/Zoom/Undo Zoom" U 266 | accel "/Time/Fetch/Fetch Size" F7 267 | accel "/Time/Fetch/Fetch ->" 2 268 | accel "/Time/Fetch/Fetch <-" 1 269 | accel "/Time/Discard/Discard ->" 4 270 | accel "/Time/Discard/Discard <-" 3 271 | accel "/Time/Shift/Shift ->" 6 272 | accel "/Time/Shift/Shift <-" 5 273 | accel "/Time/Page/Page ->" 8 274 | accel "/Time/Page/Page <-" 7 275 | accel "/Markers/Show-Change Marker Data" M 276 | accel "/Markers/Drop Named Marker" N 277 | accel "/Markers/Collect Named Marker" N 278 | accel "/Markers/Collect All Named Markers" N 279 | accel "/Markers/Copy Primary->B Marker" (null) 280 | accel "/Markers/Copy Primary->B Marker" B 281 | accel "/Markers/Delete Primary Marker" M 282 | accel "/Markers/" (null) 283 | accel "/Markers/Find Previous Edge" (null) 284 | accel "/Markers/Find Next Edge" (null) 285 | accel "/Markers/" (null) 286 | accel "/Markers/Alternate Wheel Mode" (null) 287 | accel "/Markers/" (null) 288 | accel "/Markers/Wave Scrolling" F9 289 | accel "/Markers/Locking/Lock to Lesser Named Marker" Q 290 | accel "/Markers/Locking/Lock to Greater Named Marker" W 291 | accel "/Markers/Locking/Unlock from Named Marker" O 292 | accel "/View/Show Grid" G 293 | accel "/View/" (null) 294 | accel "/View/Show Wave Highlight" (null) 295 | accel "/View/Show Filled High Values" (null) 296 | accel "/View/" (null) 297 | accel "/View/Show Mouseover" (null) 298 | accel "/View/Mouseover Copies To Clipboard" (null) 299 | accel "/View/" (null) 300 | accel "/View/Show Base Symbols" F1 301 | accel "/View/" (null) 302 | accel "/View/Standard Trace Select" (null) 303 | accel "/View/" (null) 304 | accel "/View/Dynamic Resize" 9 305 | accel "/View/" (null) 306 | accel "/View/Center Zooms" F8 307 | accel "/View/" (null) 308 | accel "/View/Toggle Delta-Frequency" (null) 309 | accel "/View/Toggle Max-Marker" F10 310 | accel "/View/" (null) 311 | accel "/View/Constant Marker Update" F11 312 | accel "/View/" (null) 313 | accel "/View/Draw Roundcapped Vectors" F2 314 | accel "/View/" (null) 315 | accel "/View/Left Justified Signals" Home 316 | accel "/View/Right Justified Signals" End 317 | accel "/View/" (null) 318 | accel "/View/Zoom Pow10 Snap" Pause 319 | accel "/View/Partial VCD Dynamic Zoom Full" (null) 320 | accel "/View/Partial VCD Dynamic Zoom To End" (null) 321 | accel "/View/Full Precision" Pause 322 | accel "/View/" (null) 323 | accel "/View/Define Time Ruler Marks" (null) 324 | accel "/View/Remove Pattern Marks" (null) 325 | accel "/View/" (null) 326 | accel "/View/Use Color" (null) 327 | accel "/View/Use Black and White" (null) 328 | accel "/View/" (null) 329 | accel "/View/LXT Clock Compress to Z" (null) 330 | accel "/View/" (null) 331 | accel "/View/Scale To Time Dimension/None" (null) 332 | accel "/View/Scale To Time Dimension/sec" (null) 333 | accel "/View/Scale To Time Dimension/ms" (null) 334 | accel "/View/Scale To Time Dimension/us" (null) 335 | accel "/View/Scale To Time Dimension/ns" (null) 336 | accel "/View/Scale To Time Dimension/ps" (null) 337 | accel "/View/Scale To Time Dimension/fs" (null) 338 | accel "/Help/WAVE Help" H 339 | accel "/Help/WAVE User Manual" (null) 340 | accel "/Help/Wave Version" (null) 341 | 342 | # Custom 343 | ; font_name_signals Monospace 56B 344 | ; font_name_waves Monospace 30B 345 | use_big_fonts 1 346 | use_fat_lines 1 --------------------------------------------------------------------------------