├── .gitignore ├── LICENSE ├── Makefile ├── README.md ├── alu.v ├── alu_tb.v ├── c.c ├── config └── tb_timescale.v ├── control_rv.v ├── gen_simple_memory_rom.c ├── ice_risc_rv.v ├── instr_decode_rv.v ├── instr_split_rv.v ├── last_word_memory.v ├── macros ├── aluops.v ├── control.v ├── control_rv.v ├── functions_rv.v ├── instructions_rv.v └── opcodes_rv.v ├── next_pc_rv.v ├── pc.v ├── regfile_32.v ├── regfile_32_tb.v ├── s.S ├── sign_extend_12_32.v ├── sign_extend_13_32.v ├── sign_extend_16_32.v ├── sign_extend_20_32.v ├── sign_extend_21_32.v ├── sign_extend_8_32.v ├── sim.v ├── simple_memory.v ├── simple_memory_rom.v ├── sub_word_d_mem_read_rv.v └── test.lds /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Icenowy/ice-risc/HEAD/.gitignore -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 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