├── 1_VerilogSourceCode ├── 1_CPUCore_src │ ├── ALU.v │ ├── BRAMModule │ │ ├── DataRam.v │ │ └── InstructionRam.v │ ├── BranchDecisionMaking.v │ ├── ControlUnit.v │ ├── DataExt.v │ ├── EXSegReg.v │ ├── HarzardUnit.v │ ├── IDSegReg.v │ ├── IFSegReg.v │ ├── ImmOperandUnit.v │ ├── MEMSegReg.v │ ├── NPC_Generator.v │ ├── Parameters.v │ ├── RV32Core.v │ ├── RegisterFile.v │ └── WBSegReg.v └── 2_Simulation │ ├── 1testAll.data │ ├── 1testAll.inst │ ├── 1testAll.txt │ ├── 2testAll.data │ ├── 2testAll.inst │ ├── 2testAll.txt │ ├── 3testAll.data │ ├── 3testAll.inst │ ├── 3testAll.txt │ ├── DataRamContent.txt │ ├── InstRamContent.txt │ ├── test.S │ ├── test.data │ ├── test.inst │ └── testBench.v ├── 2_BRAMInputFileGenerator ├── ExampleCode │ ├── ASMCode │ │ ├── Fibonacci.S │ │ ├── Number2Ascii.S │ │ └── QuickSort.S │ └── RISCVTest_rv32ui │ │ ├── 1testAll.S │ │ ├── 2testAll.S │ │ ├── 3testAll.S │ │ ├── SourceCode │ │ ├── 1testAll.S │ │ ├── 2testAll.S │ │ ├── 3testAll.S │ │ ├── encoding.h │ │ ├── riscv_test.h │ │ └── test_macros.h │ │ ├── add.S │ │ ├── addi.S │ │ ├── and.S │ │ ├── andi.S │ │ ├── auipc.S │ │ ├── beq.S │ │ ├── bge.S │ │ ├── bgeu.S │ │ ├── blt.S │ │ ├── bltu.S │ │ ├── bne.S │ │ ├── fence_i.S │ │ ├── include │ │ ├── encoding.h │ │ ├── riscv_test.h │ │ └── test_macros.h │ │ ├── jal.S │ │ ├── jalr.S │ │ ├── lb.S │ │ ├── lbu.S │ │ ├── lh.S │ │ ├── lhu.S │ │ ├── lui.S │ │ ├── lw.S │ │ ├── or.S │ │ ├── ori.S │ │ ├── sb.S │ │ ├── sh.S │ │ ├── simple.S │ │ ├── sll.S │ │ ├── slli.S │ │ ├── slt.S │ │ ├── slti.S │ │ ├── sltiu.S │ │ ├── sltu.S │ │ ├── sra.S │ │ ├── srai.S │ │ ├── srl.S │ │ ├── srli.S │ │ ├── sub.S │ │ ├── sw.S │ │ ├── xor.S │ │ └── xori.S ├── Makefile ├── README.md └── Utils │ ├── Bin2Data.c │ ├── riscv32-unknown-elf-as │ ├── riscv32-unknown-elf-ld │ ├── riscv32-unknown-elf-objcopy │ └── riscv32-unknown-elf-objdump ├── 4_ProjectDesignFiles └── CPU设计图.pdf ├── 5_DetailDocuments ├── Lab1-CPU设计报告.docx ├── Lab1-CPU设计报告.pdf ├── Lab2-CPU代码实现验收标准和实验报告要求.docx ├── Lab2-CPU代码实现验收标准和实验报告要求.pdf ├── 夏昊珺-Lab1总结和Lab2讲解.pptx └── 资料 │ ├── RISC-V 指令集卷1-用户级指令-中文版.pdf │ ├── RISC-V 指令集卷2-特权级指令-中文版.pdf │ ├── RISCV指令集总览表格.pdf │ ├── The RISC-V Instruction Set Manual Volume I User-Level ISA-V2.2.pdf │ └── The RISC-V Instruction Set Manual Volume II Privileged Architecture V1.9.1.pdf ├── LICENSE ├── README.md └── images ├── IDSegReg.jpg ├── RISC-V.png └── imm.png /1_VerilogSourceCode/1_CPUCore_src/ALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB (Embeded System Lab) 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: ALU 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: ALU unit of RISCV CPU 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | `include "Parameters.v" 13 | module ALU( 14 | input wire [31:0] Operand1, 15 | input wire [31:0] Operand2, 16 | input wire [3:0] AluContrl, 17 | output reg [31:0] AluOut 18 | ); 19 | 20 | always@(*) 21 | begin 22 | case(AluContrl) 23 | `ADD: AluOut <= Operand1 + Operand2; 24 | `SUB: AluOut <= Operand1 - Operand2; 25 | `XOR: AluOut <= Operand1 ^ Operand2; 26 | `OR: AluOut <= Operand1 | Operand2; 27 | `AND: AluOut <= Operand1 & Operand2; 28 | `SRL: AluOut <= (Operand1>>Operand2[4:0]); 29 | `SLL: AluOut <= (Operand1<>>Operand2[4:0]); 31 | `SLT: AluOut <= ($signed(Operand1) < $signed(Operand2)) ? 32'b1 : 32'b0; 32 | `SLTU:AluOut <= (Operand1 < Operand2) ? 32'b1 : 32'b0; 33 | `LUI: AluOut <= Operand2;//待补全!!! 34 | default:AluOut<=32'hxxxxxxxx; 35 | endcase 36 | end 37 | endmodule 38 | 39 | //功能和接口说明 40 | //ALU接受两个操作数，根据AluContrl的不同，进行不同的计算操作，将计算结果输出到AluOut 41 | //AluContrl的类型定义在Parameters.v中 42 | //推荐格式： 43 | //case() 44 | // `ADD: AluOut<=Operand1 + Operand2; 45 | // ....... 46 | // default: AluOut <= 32'hxxxxxxxx; 47 | //endcase 48 | //实验要求 49 | //实现ALU模块 50 | //已实现 51 | -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/BRAMModule/DataRam.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB 4 | // Engineer: Xuan Wang (wgg@mail.ustc.edu.cn) 5 | // 6 | // Create Date: 2019/02/08 16:29:41 7 | // Design Name: RISCV-Pipline CPU 8 | // Module Name: InstructionRamWrapper 9 | // Target Devices: Nexys4 10 | // Tool Versions: Vivado 2017.4.1 11 | // Description: a Verilog-based ram which can be systhesis as BRAM 12 | // 13 | ////////////////////////////////////////////////////////////////////////////////// 14 | module DataRam( 15 | input clk, 16 | input [ 3:0] wea, web, 17 | input [31:2] addra, addrb, 18 | input [31:0] dina , dinb, 19 | output reg [31:0] douta, doutb 20 | ); 21 | initial begin douta=0; doutb=0; end 22 | 23 | wire addra_valid = ( addra[31:14]==18'h0 ); 24 | wire addrb_valid = ( addrb[31:14]==18'h0 ); 25 | wire [11:0] addral = addra[13:2]; 26 | wire [11:0] addrbl = addrb[13:2]; 27 | 28 | reg [31:0] ram_cell [0:4095]; 29 | 30 | initial begin // add simulation data here 31 | ram_cell[0] = 32'h00000000; 32 | // ...... 33 | end 34 | 35 | always @ (posedge clk) 36 | douta <= addra_valid ? ram_cell[addral] : 0; 37 | 38 | always @ (posedge clk) 39 | doutb <= addrb_valid ? ram_cell[addrbl] : 0; 40 | 41 | always @ (posedge clk) 42 | if(wea[0] & addra_valid) 43 | ram_cell[addral][ 7: 0] <= dina[ 7: 0]; 44 | 45 | always @ (posedge clk) 46 | if(wea[1] & addra_valid) 47 | ram_cell[addral][15: 8] <= dina[15: 8]; 48 | 49 | always @ (posedge clk) 50 | if(wea[2] & addra_valid) 51 | ram_cell[addral][23:16] <= dina[23:16]; 52 | 53 | always @ (posedge clk) 54 | if(wea[3] & addra_valid) 55 | ram_cell[addral][31:24] <= dina[31:24]; 56 | 57 | always @ (posedge clk) 58 | if(web[0] & addrb_valid) 59 | ram_cell[addrbl][ 7: 0] <= dinb[ 7: 0]; 60 | 61 | always @ (posedge clk) 62 | if(web[1] & addrb_valid) 63 | ram_cell[addrbl][15: 8] <= dinb[15: 8]; 64 | 65 | always @ (posedge clk) 66 | if(web[2] & addrb_valid) 67 | ram_cell[addrbl][23:16] <= dinb[23:16]; 68 | 69 | always @ (posedge clk) 70 | if(web[3] & addrb_valid) 71 | ram_cell[addrbl][31:24] <= dinb[31:24]; 72 | 73 | endmodule 74 | //功能说明 75 | //同步读写bram，a、b双口可读写，a口用于CPU访问dataRam，b口用于外接debug_module进行读写 76 | //写使能为4bit，支持byte write 77 | //输入 78 | //clk 输入时钟 79 | //addra a口读写地址 80 | //dina a口写输入数据 81 | //wea a口写使能 82 | //addrb b口读写地址 83 | //dinb b口写输入数据 84 | //web b口写使能 85 | //输出 86 | //douta a口读数据 87 | //doutb b口读数据 88 | //实验要求 89 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/BRAMModule/InstructionRam.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB 4 | // Engineer: Xuan Wang (wgg@mail.ustc.edu.cn) 5 | // 6 | // Create Date: 2019/02/08 16:29:41 7 | // Design Name: RISCV-Pipline CPU 8 | // Module Name: InstructionRamWrapper 9 | // Target Devices: Nexys4 10 | // Tool Versions: Vivado 2017.4.1 11 | // Description: a Verilog-based ram which can be systhesis as BRAM 12 | // 13 | ////////////////////////////////////////////////////////////////////////////////// 14 | module InstructionRam( 15 | input clk, 16 | input web, 17 | input [31:2] addra, addrb, 18 | input [31:0] dinb, 19 | output reg [31:0] douta, doutb 20 | ); 21 | initial begin douta=0; doutb=0; end 22 | 23 | wire addra_valid = ( addra[31:14]==18'h0 ); 24 | wire addrb_valid = ( addrb[31:14]==18'h0 ); 25 | wire [11:0] addral = addra[13:2]; 26 | wire [11:0] addrbl = addrb[13:2]; 27 | 28 | reg [31:0] ram_cell [0:4095]; 29 | 30 | initial begin // you can add simulation instructions here 31 | ram_cell[0] = 32'h00000000; 32 | // ...... 33 | end 34 | 35 | always @ (posedge clk) 36 | douta <= addra_valid ? ram_cell[addral] : 0; 37 | 38 | always @ (posedge clk) 39 | doutb <= addrb_valid ? ram_cell[addrbl] : 0; 40 | 41 | always @ (posedge clk) 42 | if(web & addrb_valid) 43 | ram_cell[addrbl] <= dinb; 44 | 45 | endmodule 46 | 47 | //功能说明 48 | //同步读写bram，a口只读，用于取指，b口可读写，用于外接debug_module进行读写 49 | //写使能为1bit，不支持byte write 50 | //输入 51 | //clk 输入时钟 52 | //addra a口读地址 53 | //addrb b口读写地址 54 | //dinb b口写输入数据 55 | //web b口写使能 56 | //输出 57 | //douta a口读数据 58 | //doutb b口读数据 59 | //实验要求 60 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/BranchDecisionMaking.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB(Embeded System Lab） 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/03/14 12:03:15 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: BranchDecisionMaking 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: Decide whether to branch 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | `include "Parameters.v" 13 | module BranchDecisionMaking( 14 | input wire [2:0] BranchTypeE, 15 | input wire [31:0] Operand1,Operand2, 16 | output reg BranchE 17 | ); 18 | 19 | always@(*) 20 | begin 21 | case(BranchTypeE) 22 | `NOBRANCH: BranchE<=1'b0; 23 | `BEQ: BranchE<=(Operand1 == Operand2) ? 1'b1 : 1'b0; 24 | `BNE: BranchE<=(Operand1 != Operand2) ? 1'b1 : 1'b0; 25 | `BLT: BranchE<=($signed(Operand1) < $signed(Operand2)) ? 1'b1 : 1'b0; 26 | `BLTU:BranchE<=(Operand1 < Operand2) ? 1'b1 : 1'b0; 27 | `BGE: BranchE<=($signed(Operand1) >= $signed(Operand2)) ? 1'b1 : 1'b0; 28 | `BGEU: BranchE<=(Operand1 >= Operand2) ? 1'b1 : 1'b0; 29 | default:BranchE<=1'b0; 30 | endcase 31 | end 32 | endmodule 33 | 34 | //功能和接口说�? 35 | //BranchDecisionMaking接受两个操作数，根据BranchTypeE的不同，进行不同的判断，当分支应该taken时，令BranchE=1'b1 36 | //BranchTypeE的类型定义在Parameters.v�? 37 | //推荐格式�? 38 | //case() 39 | // `BEQ: ??? 40 | // ....... 41 | // default: BranchE<=1'b0; //NOBRANCH 42 | //endcase 43 | //实验要求 44 | //实现BranchDecisionMaking模块 45 | //已实现 46 | -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/ControlUnit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB (Embeded System Lab) 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: ControlUnit 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: RISC-V Instruction Decoder 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | `include "Parameters.v" 13 | module ControlUnit( 14 | input wire [6:0] Op, 15 | input wire [2:0] Fn3, 16 | input wire [6:0] Fn7, 17 | output reg JalD, 18 | output reg JalrD, 19 | output reg [2:0] RegWriteD, 20 | output reg MemToRegD, 21 | output reg [3:0] MemWriteD, 22 | output reg LoadNpcD, 23 | output reg [1:0] RegReadD, 24 | output reg [2:0] BranchTypeD, 25 | output reg [3:0] AluContrlD, 26 | output reg [1:0] AluSrc2D, 27 | output reg AluSrc1D, 28 | output reg [2:0] ImmType 29 | ); 30 | //待补全！！！ 31 | 32 | always@(*) 33 | begin 34 | case(Op) 35 | 7'b1101111: //Jal 36 | begin 37 | JalD <= 1'b1; 38 | JalrD <= 1'b0; 39 | RegWriteD <= `LW; 40 | MemToRegD <= 1'b0; 41 | MemWriteD <= 4'b0000; 42 | LoadNpcD <= 1'b1; 43 | RegReadD <= 2'b00; 44 | BranchTypeD <= 3'b000; 45 | AluContrlD <= `ADD; 46 | AluSrc2D <= 2'b00; 47 | AluSrc1D <= 1'b0; 48 | ImmType <= `JTYPE; 49 | end 50 | 7'b1100111: //Jalr 51 | begin 52 | JalD <= 1'b0; 53 | JalrD <= 1'b1; 54 | RegWriteD <= `LW; 55 | MemToRegD <= 1'b0; 56 | MemWriteD <= 4'b0000; 57 | LoadNpcD <= 1'b1; 58 | RegReadD <= 2'b10; 59 | BranchTypeD <= 3'b000; 60 | AluContrlD <= `ADD; 61 | AluSrc2D <= 2'b10; //imm 62 | AluSrc1D <= 1'b0; //rs1 63 | ImmType <= `ITYPE; 64 | end 65 | 7'b1100011: //Branch 66 | begin 67 | JalD <= 1'b0; 68 | JalrD <= 1'b0; 69 | RegWriteD <= 3'b000; 70 | MemToRegD <= 1'b0; 71 | MemWriteD <= 4'b0000; 72 | LoadNpcD <= 1'b0; 73 | RegReadD <= 2'b11; 74 | AluContrlD <= `ADD; 75 | AluSrc2D <= 2'b00; //reg 76 | AluSrc1D <= 1'b0; //reg 77 | ImmType <= `BTYPE; 78 | case(Fn3) 79 | 3'b000: BranchTypeD <= `BEQ; 80 | 3'b001: BranchTypeD <= `BNE; 81 | 3'b100: BranchTypeD <= `BLT; 82 | 3'b101: BranchTypeD <= `BGE; 83 | 3'b110: BranchTypeD <= `BLTU; 84 | 3'b111: BranchTypeD <= `BGEU; 85 | default: BranchTypeD <= 3'b000; 86 | endcase 87 | end 88 | 7'b0110111: //LUI 89 | begin 90 | JalD <= 1'b0; 91 | JalrD <= 1'b0; 92 | RegWriteD <= `LW; 93 | MemToRegD <= 1'b0; 94 | MemWriteD <= 4'b0000; 95 | LoadNpcD <= 1'b0; 96 | RegReadD <= 2'b00; 97 | BranchTypeD <= 3'b000; 98 | AluContrlD <= `LUI; 99 | AluSrc2D <= 2'b10; //imm 100 | AluSrc1D <= 1'b0; //irrelavant 101 | ImmType <= `UTYPE; 102 | end 103 | 7'b0010111: //AUIPC 104 | begin 105 | JalD <= 1'b0; 106 | JalrD <= 1'b0; 107 | RegWriteD <= `LW; 108 | MemToRegD <= 1'b0; 109 | MemWriteD <= 4'b0000; 110 | LoadNpcD <= 1'b0; 111 | RegReadD <= 2'b00; 112 | BranchTypeD <= 3'b000; 113 | AluContrlD <= `ADD; 114 | AluSrc2D <= 2'b10; //imm 115 | AluSrc1D <= 1'b1; //pc 116 | ImmType <= `UTYPE; 117 | end 118 | 7'b0010011: //alu imm 119 | begin 120 | JalD <= 1'b0; 121 | JalrD <= 1'b0; 122 | RegWriteD <= `LW; 123 | MemToRegD <= 1'b0; 124 | MemWriteD <= 4'b0000; 125 | LoadNpcD <= 1'b0; 126 | RegReadD <= 2'b10; 127 | BranchTypeD <= 3'b000; 128 | AluSrc1D <= 1'b0; //rs1 129 | ImmType <= `ITYPE; 130 | case(Fn3) 131 | 3'b000: 132 | begin 133 | AluContrlD <= `ADD; 134 | AluSrc2D <= 2'b10; //imm 135 | end 136 | 3'b010: 137 | begin 138 | AluContrlD <= `SLT; 139 | AluSrc2D <= 2'b10; //imm 140 | end 141 | 3'b011: 142 | begin 143 | AluContrlD <= `SLTU; 144 | AluSrc2D <= 2'b10; //imm 145 | end 146 | 3'b100: 147 | begin 148 | AluContrlD <= `XOR; 149 | AluSrc2D <= 2'b10; //imm 150 | end 151 | 3'b110: 152 | begin 153 | AluContrlD <= `OR; 154 | AluSrc2D <= 2'b10; //imm 155 | end 156 | 3'b111: 157 | begin 158 | AluContrlD <= `AND; 159 | AluSrc2D <= 2'b10; //imm 160 | end 161 | 3'b001: 162 | begin 163 | AluContrlD <= `SLL; 164 | AluSrc2D <= 2'b01; //shamt 165 | end 166 | 3'b101: 167 | begin 168 | case(Fn7) 169 | 7'b0000000: 170 | begin 171 | AluContrlD <= `SRL; 172 | AluSrc2D <= 2'b01; 173 | end 174 | 7'b0100000: 175 | begin 176 | AluContrlD <= `SRA; 177 | AluSrc2D <= 2'b01; 178 | end 179 | endcase 180 | end 181 | endcase 182 | end 183 | 7'b0110011: //alu reg 184 | begin 185 | JalD <= 1'b0; 186 | JalrD <= 1'b0; 187 | RegWriteD <= `LW; 188 | MemToRegD <= 1'b0; 189 | MemWriteD <= 4'b0000; 190 | LoadNpcD <= 1'b0; 191 | RegReadD <= 2'b11; 192 | BranchTypeD <= 3'b000; 193 | AluSrc2D <= 2'b00; //rs2 194 | AluSrc1D <= 1'b0; //rs1 195 | ImmType <= `RTYPE; 196 | case(Fn3) 197 | 3'b000: 198 | begin 199 | case(Fn7) 200 | 7'b0000000: AluContrlD <= `ADD; 201 | 7'b0100000: AluContrlD <= `SUB; 202 | endcase 203 | end 204 | 3'b001: AluContrlD <= `SLL; 205 | 3'b010: AluContrlD <= `SLT; 206 | 3'b011: AluContrlD <= `SLTU; 207 | 3'b100: AluContrlD <= `XOR; 208 | 3'b101: 209 | begin 210 | case(Fn7) 211 | 7'b0000000: AluContrlD <= `SRL; 212 | 7'b0100000: AluContrlD <= `SRA; 213 | endcase 214 | end 215 | 3'b110: AluContrlD <= `OR; 216 | 3'b111: AluContrlD <= `AND; 217 | endcase 218 | end 219 | 7'b0000011: //load 220 | begin 221 | JalD <= 1'b0; 222 | JalrD <= 1'b0; 223 | MemToRegD <= 1'b1; 224 | MemWriteD <= 4'b0000; 225 | LoadNpcD <= 1'b0; 226 | RegReadD <= 2'b10; 227 | BranchTypeD <= 3'b000; 228 | AluContrlD <= `ADD; 229 | AluSrc2D <= 2'b10; //imm 230 | AluSrc1D <= 1'b0; //rs1 231 | ImmType <= `ITYPE; 232 | case(Fn3) 233 | 3'b000: RegWriteD <= `LB; 234 | 3'b001: RegWriteD <= `LH; 235 | 3'b010: RegWriteD <= `LW; 236 | 3'b100: RegWriteD <= `LBU; 237 | 3'b101: RegWriteD <= `LHU; 238 | endcase 239 | end 240 | 7'b0100011: //store 241 | begin 242 | JalD <= 1'b0; 243 | JalrD <= 1'b0; 244 | RegWriteD <= 3'b000; 245 | MemToRegD <= 1'b0; 246 | LoadNpcD <= 1'b0; 247 | RegReadD <= 2'b11; 248 | BranchTypeD <= 3'b000; 249 | AluContrlD <= `ADD; 250 | AluSrc2D <= 2'b10; //imm 251 | AluSrc1D <= 1'b0; //rs1 252 | ImmType <= `STYPE; 253 | case(Fn3) 254 | 3'b000: MemWriteD <= 4'b0001; 255 | 3'b001: MemWriteD <= 4'b0011; 256 | 3'b010: MemWriteD <= 4'b1111; 257 | endcase 258 | end 259 | default 260 | begin 261 | JalD <= 1'b0; 262 | JalrD <= 1'b0; 263 | RegWriteD <= 3'b000; 264 | MemToRegD <= 1'b0; 265 | MemWriteD <= 4'b0000; 266 | LoadNpcD <= 1'b0; 267 | RegReadD <= 2'b00; 268 | BranchTypeD <= 3'b000; 269 | AluContrlD <= 4'd15; 270 | AluSrc2D <= 2'b00; 271 | AluSrc1D <= 1'b0; 272 | ImmType <= `JTYPE; 273 | end 274 | endcase 275 | end 276 | endmodule 277 | 278 | //功能说明 279 | //ControlUnit 是本CPU的指令译码器，组合�?�辑电路 280 | //输入 281 | // Op 是指令的操作码部�?? 282 | // Fn3 是指令的func3部分 283 | // Fn7 是指令的func7部分 284 | //输出 285 | // JalD==1 表示Jal指令到达ID译码阶段 286 | // JalrD==1 表示Jalr指令到达ID译码阶段 287 | // RegWriteD 表示ID阶段的指令对应的 寄存器写入模�? ，所有模式定义在Parameters.v�? 288 | // MemToRegD==1 表示ID阶段的指令需要将data memory读取的�?�写入寄存器, 289 | // MemWriteD �?4bit，采用独热码格式，对于data memory�?32bit字按byte进行写入,MemWriteD=0001表示只写入最�?1个byte，和xilinx bram的接口类�? 290 | // LoadNpcD==1 表示将NextPC输出到ResultM 291 | // RegReadD[1]==1 表示A1对应的寄存器值被使用到了，RegReadD[0]==1表示A2对应的寄存器值被使用到了，用于forward的处�? 292 | // BranchTypeD 表示不同的分支类型，�?有类型定义在Parameters.v�? 293 | // AluContrlD 表示不同的ALU计算功能，所有类型定义在Parameters.v�? 294 | // AluSrc2D 表示Alu输入�?2的�?�择 295 | // AluSrc1D 表示Alu输入�?1的�?�择 296 | // ImmType 表示指令的立即数格式，所有类型定义在Parameters.v�? 297 | //实验要求 298 | //实现ControlUnit模块 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/DataExt.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: qihao 5 | // Create Date: 03/09/2019 09:03:05 PM 6 | // Design Name: 7 | // Module Name: DataExt 8 | // Target Devices: 9 | // Tool Versions: 10 | // Description: 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | 13 | `include "Parameters.v" 14 | module DataExt( 15 | input wire [31:0] IN, 16 | input wire [1:0] LoadedBytesSelect, 17 | input wire [2:0] RegWriteW, 18 | output reg [31:0] OUT 19 | ); 20 | 21 | always@(*) 22 | begin 23 | case(RegWriteW) 24 | `LB: 25 | begin 26 | case(LoadedBytesSelect) 27 | 2'b11: OUT<={{24{IN[31]}},IN[31:24]}; 28 | 2'b10: OUT<={{24{IN[23]}},IN[23:16]}; 29 | 2'b01: OUT<={{24{IN[15]}},IN[15:8]}; 30 | 2'b00: OUT<={{24{IN[7]}},IN[7:0]}; 31 | default: OUT<=32'hxxxxxxxx; 32 | endcase 33 | end 34 | `LH: 35 | begin 36 | case(LoadedBytesSelect) 37 | 2'b10: OUT<={{16{IN[31]}},IN[31:16]}; 38 | 2'b00: OUT<={{16{IN[15]}},IN[15:0]}; 39 | default: OUT<=32'hxxxxxxxx; 40 | endcase 41 | end 42 | `LW: OUT<=IN; 43 | `LBU: 44 | begin 45 | case(LoadedBytesSelect) 46 | 2'b11: OUT<={24'b0,IN[31:24]}; 47 | 2'b10: OUT<={24'b0,IN[23:16]}; 48 | 2'b01: OUT<={24'b0,IN[15:8]}; 49 | 2'b00: OUT<={24'b0,IN[7:0]}; 50 | default: OUT<=32'hxxxxxxxx; 51 | endcase 52 | end 53 | `LHU: 54 | begin 55 | case(LoadedBytesSelect) 56 | 2'b10: OUT<={16'b0,IN[31:16]}; 57 | 2'b00: OUT<={16'b0,IN[15:0]}; 58 | default: OUT<=32'hxxxxxxxx; 59 | endcase 60 | end 61 | default: OUT<=32'hxxxxxxxx; 62 | endcase 63 | end 64 | endmodule 65 | 66 | //功能说明 67 | //DataExt是用来处理非字对齐load的情形，同时根据load的不同模式对Data Mem中load的数进行符号或�?�无符号拓展，组合�?�辑电路 68 | //输入 69 | //IN 是从Data Memory中load�?32bit�? 70 | //LoadedBytesSelect 等价于AluOutM[1:0]，是读Data Memory地址的低两位�? 71 | //因为DataMemory是按字（32bit）进行访问的，所以需要把字节地址转化为字地址传给DataMem 72 | //DataMem�?次返回一个字，低两位地址用来�?32bit字中挑�?�出我们�?要的字节 73 | //RegWriteW 表示不同�? 寄存器写入模�? ，所有模式定义在Parameters.v�? 74 | //输出 75 | //OUT表示要写入寄存器的最终�?? 76 | //实验要求 77 | //实现DataExt模块 78 | //已实�? 79 | -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/EXSegReg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB（Embeded System Lab） 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: EXSegReg 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: ID-EX Segment Register 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module EXSegReg( 13 | input wire clk, 14 | input wire en, 15 | input wire clear, 16 | //Data Signals 17 | input wire [31:0] PCD, 18 | output reg [31:0] PCE, 19 | input wire [31:0] JalNPC, 20 | output reg [31:0] BrNPC, 21 | input wire [31:0] ImmD, 22 | output reg [31:0] ImmE, 23 | input wire [4:0] RdD, 24 | output reg [4:0] RdE, 25 | input wire [4:0] Rs1D, 26 | output reg [4:0] Rs1E, 27 | input wire [4:0] Rs2D, 28 | output reg [4:0] Rs2E, 29 | input wire [31:0] RegOut1D, 30 | output reg [31:0] RegOut1E, 31 | input wire [31:0] RegOut2D, 32 | output reg [31:0] RegOut2E, 33 | //Control Signals 34 | input wire JalrD, 35 | output reg JalrE, 36 | input wire [2:0] RegWriteD, 37 | output reg [2:0] RegWriteE, 38 | input wire MemToRegD, 39 | output reg MemToRegE, 40 | input wire [3:0] MemWriteD, 41 | output reg [3:0] MemWriteE, 42 | input wire LoadNpcD, 43 | output reg LoadNpcE, 44 | input wire [1:0] RegReadD, 45 | output reg [1:0] RegReadE, 46 | input wire [2:0] BranchTypeD, 47 | output reg [2:0] BranchTypeE, 48 | input wire [4:0] AluContrlD, 49 | output reg [4:0] AluContrlE, 50 | input wire AluSrc1D, 51 | output reg AluSrc1E, 52 | input wire [1:0] AluSrc2D, 53 | output reg [1:0] AluSrc2E 54 | ); 55 | initial begin 56 | PCE = 32'b0; 57 | BrNPC = 32'b0; 58 | ImmE = 32'b0; 59 | RdE = 32'b0; 60 | Rs1E = 5'b0; 61 | Rs2E = 5'b0; 62 | RegOut1E = 32'b0; 63 | RegOut2E = 32'b0; 64 | JalrE = 1'b0; 65 | RegWriteE = 1'b0; 66 | MemToRegE = 1'b0; 67 | MemWriteE = 1'b0; 68 | LoadNpcE = 1'b0; 69 | RegReadE = 2'b00; 70 | BranchTypeE = 3'b0; 71 | AluContrlE = 5'b0; 72 | AluSrc1E = 1'b0; 73 | AluSrc2E = 2'b0; 74 | end 75 | // 76 | always@(posedge clk) begin 77 | if(en) 78 | if(clear) 79 | begin 80 | PCE<=32'b0; 81 | BrNPC<=32'b0; 82 | ImmE<=32'b0; 83 | RdE<=32'b0; 84 | Rs1E<=5'b0; 85 | Rs2E<=5'b0; 86 | RegOut1E<=32'b0; 87 | RegOut2E<=32'b0; 88 | JalrE<=1'b0; 89 | RegWriteE<=1'b0; 90 | MemToRegE<=1'b0; 91 | MemWriteE<=1'b0; 92 | LoadNpcE<=1'b0; 93 | RegReadE<=2'b00; 94 | BranchTypeE = 3'b0; 95 | AluContrlE<=5'b0; 96 | AluSrc1E<=1'b0; 97 | AluSrc2E<=2'b0; 98 | end else begin 99 | PCE<=PCD; 100 | BrNPC<=JalNPC; 101 | ImmE<=ImmD; 102 | RdE<=RdD; 103 | Rs1E<=Rs1D; 104 | Rs2E<=Rs2D; 105 | RegOut1E<=RegOut1D; 106 | RegOut2E<=RegOut2D; 107 | JalrE<=JalrD; 108 | RegWriteE=RegWriteD; 109 | MemToRegE<=MemToRegD; 110 | MemWriteE<=MemWriteD; 111 | LoadNpcE<=LoadNpcD; 112 | RegReadE<=RegReadD; 113 | BranchTypeE = BranchTypeD; 114 | AluContrlE<=AluContrlD; 115 | AluSrc1E<=AluSrc1D; 116 | AluSrc2E<=AluSrc2D; 117 | end 118 | end 119 | 120 | endmodule 121 | 122 | //功能说明 123 | //本模块是支持同步清零的段寄存器，当EN==0时寄存器状态保持不变（也不会执行清零） 124 | //实验要求 125 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/HarzardUnit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB（Embeded System Lab�? 4 | // Engineer: Haojun Xia & Xuan Wang 5 | // Create Date: 2019/02/22 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: HarzardUnit 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: Deal with harzards in pipline 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module HarzardUnit( 13 | input wire CpuRst, ICacheMiss, DCacheMiss, 14 | input wire BranchE, JalrE, JalD, 15 | input wire [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, 16 | input wire [1:0] RegReadE, 17 | input wire MemToRegE, 18 | input wire [2:0] RegWriteM, RegWriteW, 19 | output reg StallF, FlushF, StallD, FlushD, StallE, FlushE, StallM, FlushM, StallW, FlushW, 20 | output reg [1:0] Forward1E, Forward2E 21 | ); 22 | 23 | always @(*) 24 | begin 25 | if(!CpuRst) 26 | begin 27 | FlushF<=0; 28 | StallE<=0; 29 | StallM<=0; 30 | FlushM<=0; 31 | StallW<=0; 32 | FlushW<=0; 33 | Forward1E<=0; 34 | Forward2E<=0; 35 | begin 36 | if(RegReadE[1]==1 && RegWriteM!=3'b0 && Rs1E==RdM && Rs1E!=5'b0) 37 | Forward1E<=2'b10; 38 | else if(RegReadE[1]==1 && RegWriteW!=3'b 0&& Rs1E==RdW && Rs1E!=5'b0) 39 | //�? else if 是因为优先转�? RdM �?, 因为修改更晚, 优先级更�? 40 | Forward1E<=2'b01; 41 | else Forward1E = 2'b00; 42 | end 43 | begin 44 | if(RegReadE[0]==1 && RegWriteM!=3'b0 && Rs2E==RdM && Rs2E!=5'b0) 45 | Forward2E<=2'b10; 46 | else if(RegReadE[0]==1 && RegWriteW!=3'b0 && Rs2E==RdW && Rs2E!=5'b0) 47 | Forward2E<=2'b01; 48 | else Forward2E = 2'b00; 49 | end 50 | begin 51 | if(JalrE==1 || BranchE==1) 52 | begin 53 | FlushD<=1; 54 | FlushE<=1; 55 | StallD<=0; 56 | StallF<=0; 57 | end 58 | else if(JalD==1) //执行到E阶段的控制指令优先级更高 59 | begin 60 | FlushD<=1; 61 | FlushE<=0; 62 | StallD<=0; 63 | StallF<=0; 64 | end 65 | else 66 | begin 67 | FlushD<=0; 68 | FlushE<=0; 69 | StallD<=0; 70 | StallF<=0; 71 | end 72 | if(MemToRegE==1 && (Rs1D==RdE || Rs2D==RdE)) 73 | begin 74 | FlushE<=1; 75 | FlushD<=0; 76 | StallD<=1; 77 | StallF<=1; 78 | end 79 | end 80 | end 81 | else 82 | begin 83 | StallF<=0; 84 | FlushF<=1; 85 | StallD<=0; 86 | FlushD<=1; 87 | StallE<=0; 88 | FlushE<=1; 89 | StallM<=0; 90 | FlushM<=1; 91 | StallW<=0; 92 | FlushW<=1; 93 | Forward1E<=0; 94 | Forward2E<=0; 95 | end 96 | end 97 | 98 | //待补全！！！ 99 | //Stall and Flush signals generate 100 | 101 | //Forward Register Source 1 102 | 103 | //Forward Register Source 2 104 | 105 | endmodule 106 | 107 | //功能说明 108 | //HarzardUnit用来处理流水线冲突，通过插入气泡，forward以及冲刷流水段解决数据相关和控制相关，组合�?�辑电路 109 | //可以�?后实现�?�前期测试CPU正确性时，可以在每两条指令间插入四条空指令，然后直接把本模块输出定为，不forward，不stall，不flush 110 | //输入 111 | //CpuRst 外部信号，用来初始化CPU，当CpuRst==1时CPU全局复位清零（所有段寄存器flush），Cpu_Rst==0时cpu�?始执行指�? 112 | //ICacheMiss, DCacheMiss 为后续实验预留信号，暂时可以无视，用来处理cache miss 113 | //BranchE, JalrE, JalD 用来处理控制相关 114 | //Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW 用来处理数据相关，分别表示源寄存�?1号码，源寄存�?2号码，目标寄存器号码 115 | //RegReadE RegReadD[1]==1 表示A1对应的寄存器值被使用到了，RegReadD[0]==1表示A2对应的寄存器值被使用到了，用于forward的处�? 116 | //RegWriteM, RegWriteW 用来处理数据相关，RegWrite!=3'b0说明对目标寄存器有写入操�? 117 | //MemToRegE 表示Ex段当前指�? 从Data Memory中加载数据到寄存器中 118 | //输出 119 | //StallF, FlushF, StallD, FlushD, StallE, FlushE, StallM, FlushM, StallW, FlushW 控制五个段寄存器进行stall（维持状态不变）和flush（清零） 120 | //Forward1E, Forward2E 控制forward 121 | //实验要求 122 | //实现HarzardUnit模块 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/IDSegReg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB（Embeded System Lab） 4 | // Engineer: Haojun Xia & Xuan Wang 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: IDSegReg 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: IF-ID Segment Register 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module IDSegReg( 13 | input wire clk, 14 | input wire clear, 15 | input wire en, 16 | //Instrution Memory Access 17 | input wire [31:0] A, 18 | output wire [31:0] RD, 19 | //Instruction Memory Debug 20 | input wire [31:0] A2, 21 | input wire [31:0] WD2, 22 | input wire [3:0] WE2, 23 | output wire [31:0] RD2, 24 | // 25 | input wire [31:0] PCF, 26 | output reg [31:0] PCD 27 | ); 28 | 29 | initial PCD = 0; 30 | always@(posedge clk) 31 | if(en) 32 | PCD <= clear ? 0: PCF; 33 | 34 | wire [31:0] RD_raw; 35 | InstructionRam InstructionRamInst ( 36 | .clk ( clk), //请完善代码!!! 37 | .addra ( A[31:2]), //请完善代码!!! 38 | .douta ( RD_raw ), 39 | .web ( |WE2 ), 40 | .addrb ( A2[31:2] ), 41 | .dinb ( WD2 ), 42 | .doutb ( RD2 ) 43 | ); 44 | // Add clear and stall support 45 | // if chip not enabled, output output last read result 46 | // else if chip clear, output 0 47 | // else output values from bram 48 | reg stall_ff= 1'b0; 49 | reg clear_ff= 1'b0; 50 | reg [31:0] RD_old=32'b0; 51 | always @ (posedge clk) 52 | begin 53 | stall_ff<=~en; 54 | clear_ff<=clear; 55 | RD_old<=RD_raw; 56 | end 57 | assign RD = stall_ff ? RD_old : (clear_ff ? 32'b0 : RD_raw ); 58 | 59 | endmodule 60 | 61 | //功能说明 62 | //IDSegReg是IF-ID段寄存器，同时包含了一个同步读写的Bram（此处你可以调用我们提供的InstructionRam， 63 | //它将会自动综合为block memory，你也可以替代性的调用xilinx的bram ip核）。 64 | //同步读memory 相当于 异步读memory 的输出外接D触发器，需要时钟上升沿才能读取数据。 65 | //此时如果再通过段寄存器缓存，那么需要两个时钟上升沿才能将数据传递到Ex段 66 | //因此在段寄存器模块中调用该同步memory，直接将输出传递到ID段组合逻辑 67 | //调用mem模块后输出为RD_raw，通过assign RD = stall_ff ? RD_old : (clear_ff ? 32'b0 : RD_raw ); 68 | //从而实现RD段寄存器stall和clear功能 69 | //实验要求 70 | //你需要补全上方代码，需补全的片段截取如下 71 | //InstructionRam InstructionRamInst ( 72 | // .clk (), //请完善代码 73 | // .addra (), //请完善代码 74 | // .douta ( RD_raw ), 75 | // .web ( |WE2 ), 76 | // .addrb ( A2[31:2] ), 77 | // .dinb ( WD2 ), 78 | // .doutb ( RD2 ) 79 | // ); 80 | //注意事项 81 | //输入到DataRam的addra是字地址，一个字32bit 82 | //已实现 83 | -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/IFSegReg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB (Embeded System Lab) 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: IFSegReg 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: PC Register 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module IFSegReg( 13 | input wire clk, 14 | input wire en, clear, 15 | input wire [31:0] PC_In, 16 | output reg [31:0] PCF 17 | ); 18 | initial PCF = 0; 19 | 20 | always@(posedge clk) 21 | if(en) begin 22 | if(clear) 23 | PCF <= 0; 24 | else 25 | PCF <= PC_In; 26 | end 27 | 28 | endmodule 29 | 30 | //功能说明 31 | //IFSegReg是PC寄存器 32 | //实验要求 33 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/ImmOperandUnit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB (Embeded System Lab) 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: ImmOperandUnit 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: Generate different type of Immediate Operand 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | `include "Parameters.v" 13 | module ImmOperandUnit( 14 | input wire [31:7] In, 15 | input wire [2:0] Type, 16 | output reg [31:0] Out 17 | ); 18 | // 19 | always@(*) 20 | begin 21 | case(Type) 22 | `ITYPE: Out<={ {21{In[31]}}, In[30:20] }; 23 | `STYPE: Out<={ {21{In[31]}}, In[30:25], In[11:7]}; 24 | `BTYPE: Out<={ {20{In[31]}}, {In[7]}, In[30:25], In[11:8], {1'b0} }; 25 | `UTYPE: Out<={ In[31:12], {12{1'b0}} }; 26 | `JTYPE: Out<={ {12{In[31]}}, In[19:12], In[20], In[30:21], {1'b0} }; 27 | `RTYPE: Out<=32'hxxxxxxxx; //请补全!!! 28 | default:Out<=32'hxxxxxxxx; 29 | endcase 30 | end 31 | 32 | endmodule 33 | 34 | //功能说明 35 | //ImmOperandUnit利用正在被译码的指令的部分编码值，生成不同类型的32bit立即数 36 | //输入 37 | //IN 是指令除了opcode以外的部分编码值 38 | //Type 表示立即数编码类型，全部类型定义在Parameters.v中 39 | //输出 40 | //OUT 表示指令对应的立即数32bit实际值 41 | //实验要求 42 | //补全ImmOperandUnit模块 43 | //待补全部分如下 44 | 45 | //always@(*) 46 | //begin 47 | // case(Type) 48 | // `ITYPE: Out<={ {21{In[31]}}, In[30:20] }; 49 | // //...... //请补全!!! 50 | // default:Out<=32'hxxxxxxxx; 51 | // endcase 52 | //end 53 | 54 | //已实现 55 | -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/MEMSegReg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB（Embeded System Lab） 4 | // Engineer: Haojun Xia & Xuan Wang 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: MEMSegReg 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: EX-MEM Segment Register 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module MEMSegReg( 13 | input wire clk, 14 | input wire en, 15 | input wire clear, 16 | //Data Signals 17 | input wire [31:0] AluOutE, 18 | output reg [31:0] AluOutM, 19 | input wire [31:0] ForwardData2, 20 | output reg [31:0] StoreDataM, 21 | input wire [4:0] RdE, 22 | output reg [4:0] RdM, 23 | input wire [31:0] PCE, 24 | output reg [31:0] PCM, 25 | //Control Signals 26 | input wire [2:0] RegWriteE, 27 | output reg [2:0] RegWriteM, 28 | input wire MemToRegE, 29 | output reg MemToRegM, 30 | input wire [3:0] MemWriteE, 31 | output reg [3:0] MemWriteM, 32 | input wire LoadNpcE, 33 | output reg LoadNpcM 34 | ); 35 | initial begin 36 | AluOutM = 0; 37 | StoreDataM = 0; 38 | RdM = 5'h0; 39 | PCM = 0; 40 | RegWriteM = 3'h0; 41 | MemToRegM = 1'b0; 42 | MemWriteM = 4'b0; 43 | LoadNpcM = 0; 44 | end 45 | 46 | always@(posedge clk) 47 | if(en) begin 48 | AluOutM <= clear ? 0 : AluOutE; 49 | StoreDataM <= clear ? 0 : ForwardData2; 50 | RdM <= clear ? 5'h0 : RdE; 51 | PCM <= clear ? 0 : PCE; 52 | RegWriteM <= clear ? 3'h0 : RegWriteE; 53 | MemToRegM <= clear ? 1'b0 : MemToRegE; 54 | MemWriteM <= clear ? 4'b0 : MemWriteE; 55 | LoadNpcM <= clear ? 0 : LoadNpcE; 56 | end 57 | 58 | endmodule 59 | 60 | //功能说明 61 | //MEMSegReg是EX-MEM段寄存器 62 | //实验要求 63 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/NPC_Generator.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB（Embeded System Lab） 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/03/14 11:21:33 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: NPC_Generator 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: Choose Next PC value 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module NPC_Generator( 13 | input wire [31:0] PCF,JalrTarget, BranchTarget, JalTarget, 14 | input wire BranchE,JalD,JalrE, 15 | output reg [31:0] PC_In 16 | ); 17 | 18 | always@(*) 19 | begin 20 | if(BranchE==1) PC_In <= BranchTarget; 21 | else if(JalrE==1) PC_In <= JalrTarget; 22 | else if(JalD==1) PC_In <= JalTarget; 23 | else PC_In <= PCF +4; 24 | end 25 | endmodule 26 | 27 | 28 | //功能说明 29 | //NPC_Generator是用来生成Next PC值得模块，根据不同的跳转信号选择不同的新PC�? 30 | //输入 31 | //PCF 旧的PC�? 32 | //JalrTarget jalr指令的对应的跳转目标 33 | //BranchTarget branch指令的对应的跳转目标 34 | //JalTarget jal指令的对应的跳转目标 35 | //BranchE==1 Ex阶段的Branch指令确定跳转 36 | //JalD==1 ID阶段的Jal指令确定跳转 37 | //JalrE==1 Ex阶段的Jalr指令确定跳转 38 | //输出 39 | //PC_In NPC的�?? 40 | //实验要求 41 | //实现NPC_Generator模块 42 | //已实�? 43 | -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/Parameters.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB (Embeded System Lab) 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: Define some constant values 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | `ifndef CONST_VALUES 13 | `define CONST_VALUES 14 | //ALUContrl[3:0] 15 | `define SLL 4'd0 16 | `define SRL 4'd1 17 | `define SRA 4'd2 18 | `define ADD 4'd3 19 | `define SUB 4'd4 20 | `define XOR 4'd5 21 | `define OR 4'd6 22 | `define AND 4'd7 23 | `define SLT 4'd8 24 | `define SLTU 4'd9 25 | `define LUI 4'd10 26 | //BranchType[2:0] 27 | `define NOBRANCH 3'd0 28 | `define BEQ 3'd1 29 | `define BNE 3'd2 30 | `define BLT 3'd3 31 | `define BLTU 3'd4 32 | `define BGE 3'd5 33 | `define BGEU 3'd6 34 | //ImmType[2:0] 35 | `define RTYPE 3'd0 36 | `define ITYPE 3'd1 37 | `define STYPE 3'd2 38 | `define BTYPE 3'd3 39 | `define UTYPE 3'd4 40 | `define JTYPE 3'd5 41 | //RegWrite[2:0] six kind of ways to save values to Register 42 | `define NOREGWRITE 3'b0 // Do not write Register 43 | `define LB 3'd1 // load 8bit from Mem then signed extended to 32bit 44 | `define LH 3'd2 // load 16bit from Mem then signed extended to 32bit 45 | `define LW 3'd3 // write 32bit to Register 46 | `define LBU 3'd4 // load 8bit from Mem then unsigned extended to 32bit 47 | `define LHU 3'd5 // load 16bit from Mem then unsigned extended to 32bit 48 | `endif 49 | 50 | //功能说明 51 | //为了代码可读性，定义了常量值 52 | //实验要求 53 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/RV32Core.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB (Embeded System Lab) 4 | // Engineer: Haojun Xia , Xuan Wang , qihao 5 | // Create Date: 2019/02/08 16:29:41 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: RV32Core 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: Top level of our CPU Core 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module RV32Core( 13 | input wire CPU_CLK, 14 | input wire CPU_RST, 15 | input wire [31:0] CPU_Debug_DataRAM_A2, 16 | input wire [31:0] CPU_Debug_DataRAM_WD2, 17 | input wire [3:0] CPU_Debug_DataRAM_WE2, 18 | output wire [31:0] CPU_Debug_DataRAM_RD2, 19 | input wire [31:0] CPU_Debug_InstRAM_A2, 20 | input wire [31:0] CPU_Debug_InstRAM_WD2, 21 | input wire [ 3:0] CPU_Debug_InstRAM_WE2, 22 | output wire [31:0] CPU_Debug_InstRAM_RD2 23 | ); 24 | //wire values definitions 25 | wire StallF, FlushF, StallD, FlushD, StallE, FlushE, StallM, FlushM, StallW, FlushW; 26 | wire [31:0] PC_In; 27 | wire [31:0] PCF; 28 | wire [31:0] Instr, PCD; 29 | wire JalD, JalrD, LoadNpcD, MemToRegD, AluSrc1D; 30 | wire [2:0] RegWriteD; 31 | wire [3:0] MemWriteD; 32 | wire [1:0] RegReadD; 33 | wire [2:0] BranchTypeD; 34 | wire [4:0] AluContrlD; 35 | wire [1:0] AluSrc2D; 36 | wire [2:0] RegWriteW; 37 | wire [4:0] RdW; 38 | wire [31:0] RegWriteData; 39 | wire [31:0] DM_RD_Ext; 40 | wire [2:0] ImmType; 41 | wire [31:0] ImmD; 42 | wire [31:0] JalNPC; 43 | wire [31:0] BrNPC; 44 | wire [31:0] ImmE; 45 | wire [6:0] OpCodeD, Funct7D; 46 | wire [2:0] Funct3D; 47 | wire [4:0] Rs1D, Rs2D, RdD; 48 | wire [4:0] Rs1E, Rs2E, RdE; 49 | wire [31:0] RegOut1D; 50 | wire [31:0] RegOut1E; 51 | wire [31:0] RegOut2D; 52 | wire [31:0] RegOut2E; 53 | wire JalrE; 54 | wire [2:0] RegWriteE; 55 | wire MemToRegE; 56 | wire [3:0] MemWriteE; 57 | wire LoadNpcE; 58 | wire [1:0] RegReadE; 59 | wire [2:0] BranchTypeE; 60 | wire [3:0] AluContrlE; 61 | wire AluSrc1E; 62 | wire [1:0] AluSrc2E; 63 | wire [31:0] Operand1; 64 | wire [31:0] Operand2; 65 | wire BranchE; 66 | wire [31:0] AluOutE; 67 | wire [31:0] AluOutM; 68 | wire [31:0] ForwardData1; 69 | wire [31:0] ForwardData2; 70 | wire [31:0] PCE; 71 | wire [31:0] StoreDataM; 72 | wire [4:0] RdM; 73 | wire [31:0] PCM; 74 | wire [2:0] RegWriteM; 75 | wire MemToRegM; 76 | wire [3:0] MemWriteM; 77 | wire LoadNpcM; 78 | wire [31:0] DM_RD; 79 | wire [31:0] ResultM; 80 | wire [31:0] ResultW; 81 | wire MemToRegW; 82 | wire [1:0] Forward1E; 83 | wire [1:0] Forward2E; 84 | wire [1:0] LoadedBytesSelect; 85 | //wire values assignments 86 | assign {Funct7D, Rs2D, Rs1D, Funct3D, RdD, OpCodeD} = Instr; 87 | assign JalNPC=ImmD+PCD; 88 | assign ForwardData1 = Forward1E[1]?(AluOutM):( Forward1E[0]?RegWriteData:RegOut1E ); 89 | assign Operand1 = AluSrc1E?PCE:ForwardData1; 90 | assign ForwardData2 = Forward2E[1]?(AluOutM):( Forward2E[0]?RegWriteData:RegOut2E ); 91 | assign Operand2 = AluSrc2E[1]?(ImmE):( AluSrc2E[0]?Rs2E:ForwardData2 ); 92 | assign ResultM = LoadNpcM ? (PCM+4) : AluOutM; 93 | assign RegWriteData = ~MemToRegW?ResultW:DM_RD_Ext; 94 | 95 | //Module connections 96 | // --------------------------------------------- 97 | // PC-IF 98 | // --------------------------------------------- 99 | NPC_Generator NPC_Generator1( 100 | .PCF(PCF), 101 | .JalrTarget(AluOutE), 102 | .BranchTarget(BrNPC), 103 | .JalTarget(JalNPC), 104 | .BranchE(BranchE), 105 | .JalD(JalD), 106 | .JalrE(JalrE), 107 | .PC_In(PC_In) 108 | ); 109 | 110 | IFSegReg IFSegReg1( 111 | .clk(CPU_CLK), 112 | .en(~StallF), 113 | .clear(FlushF), 114 | .PC_In(PC_In), 115 | .PCF(PCF) 116 | ); 117 | 118 | // --------------------------------------------- 119 | // ID stage 120 | // --------------------------------------------- 121 | IDSegReg IDSegReg1( 122 | .clk(CPU_CLK), 123 | .clear(FlushD), 124 | .en(~StallD), 125 | .A(PCF), 126 | .RD(Instr), 127 | .A2(CPU_Debug_InstRAM_A2), 128 | .WD2(CPU_Debug_InstRAM_WD2), 129 | .WE2(CPU_Debug_InstRAM_WE2), 130 | .RD2(CPU_Debug_InstRAM_RD2), 131 | .PCF(PCF), 132 | .PCD(PCD) 133 | ); 134 | 135 | ControlUnit ControlUnit1( 136 | .Op(OpCodeD), 137 | .Fn3(Funct3D), 138 | .Fn7(Funct7D), 139 | .JalD(JalD), 140 | .JalrD(JalrD), 141 | .RegWriteD(RegWriteD), 142 | .MemToRegD(MemToRegD), 143 | .MemWriteD(MemWriteD), 144 | .LoadNpcD(LoadNpcD), 145 | .RegReadD(RegReadD), 146 | .BranchTypeD(BranchTypeD), 147 | .AluContrlD(AluContrlD), 148 | .AluSrc1D(AluSrc1D), 149 | .AluSrc2D(AluSrc2D), 150 | .ImmType(ImmType) 151 | ); 152 | 153 | ImmOperandUnit ImmOperandUnit1( 154 | .In(Instr[31:7]), 155 | .Type(ImmType), 156 | .Out(ImmD) 157 | ); 158 | 159 | RegisterFile RegisterFile1( 160 | .clk(CPU_CLK), 161 | .rst(CPU_RST), 162 | .WE3(|RegWriteW), 163 | .A1(Rs1D), 164 | .A2(Rs2D), 165 | .A3(RdW), 166 | .WD3(RegWriteData), 167 | .RD1(RegOut1D), 168 | .RD2(RegOut2D) 169 | ); 170 | 171 | // --------------------------------------------- 172 | // EX stage 173 | // --------------------------------------------- 174 | EXSegReg EXSegReg1( 175 | .clk(CPU_CLK), 176 | .en(~StallE), 177 | .clear(FlushE), 178 | .PCD(PCD), 179 | .PCE(PCE), 180 | .JalNPC(JalNPC), 181 | .BrNPC(BrNPC), 182 | .ImmD(ImmD), 183 | .ImmE(ImmE), 184 | .RdD(RdD), 185 | .RdE(RdE), 186 | .Rs1D(Rs1D), 187 | .Rs1E(Rs1E), 188 | .Rs2D(Rs2D), 189 | .Rs2E(Rs2E), 190 | .RegOut1D(RegOut1D), 191 | .RegOut1E(RegOut1E), 192 | .RegOut2D(RegOut2D), 193 | .RegOut2E(RegOut2E), 194 | .JalrD(JalrD), 195 | .JalrE(JalrE), 196 | .RegWriteD(RegWriteD), 197 | .RegWriteE(RegWriteE), 198 | .MemToRegD(MemToRegD), 199 | .MemToRegE(MemToRegE), 200 | .MemWriteD(MemWriteD), 201 | .MemWriteE(MemWriteE), 202 | .LoadNpcD(LoadNpcD), 203 | .LoadNpcE(LoadNpcE), 204 | .RegReadD(RegReadD), 205 | .RegReadE(RegReadE), 206 | .BranchTypeD(BranchTypeD), 207 | .BranchTypeE(BranchTypeE), 208 | .AluContrlD(AluContrlD), 209 | .AluContrlE(AluContrlE), 210 | .AluSrc1D(AluSrc1D), 211 | .AluSrc1E(AluSrc1E), 212 | .AluSrc2D(AluSrc2D), 213 | .AluSrc2E(AluSrc2E) 214 | ); 215 | 216 | ALU ALU1( 217 | .Operand1(Operand1), 218 | .Operand2(Operand2), 219 | .AluContrl(AluContrlE), 220 | .AluOut(AluOutE) 221 | ); 222 | 223 | BranchDecisionMaking BranchDecisionMaking1( 224 | .BranchTypeE(BranchTypeE), 225 | .Operand1(Operand1), 226 | .Operand2(Operand2), 227 | .BranchE(BranchE) 228 | ); 229 | 230 | // --------------------------------------------- 231 | // MEM stage 232 | // --------------------------------------------- 233 | MEMSegReg MEMSegReg1( 234 | .clk(CPU_CLK), 235 | .en(~StallM), 236 | .clear(FlushM), 237 | .AluOutE(AluOutE), 238 | .AluOutM(AluOutM), 239 | .ForwardData2(ForwardData2), 240 | .StoreDataM(StoreDataM), 241 | .RdE(RdE), 242 | .RdM(RdM), 243 | .PCE(PCE), 244 | .PCM(PCM), 245 | .RegWriteE(RegWriteE), 246 | .RegWriteM(RegWriteM), 247 | .MemToRegE(MemToRegE), 248 | .MemToRegM(MemToRegM), 249 | .MemWriteE(MemWriteE), 250 | .MemWriteM(MemWriteM), 251 | .LoadNpcE(LoadNpcE), 252 | .LoadNpcM(LoadNpcM) 253 | ); 254 | 255 | // --------------------------------------------- 256 | // WB stage 257 | // --------------------------------------------- 258 | WBSegReg WBSegReg1( 259 | .clk(CPU_CLK), 260 | .en(~StallW), 261 | .clear(FlushW), 262 | .A(AluOutM), 263 | .WD(StoreDataM), 264 | .WE(MemWriteM), 265 | .RD(DM_RD), 266 | .LoadedBytesSelect(LoadedBytesSelect), 267 | .A2(CPU_Debug_DataRAM_A2), 268 | .WD2(CPU_Debug_DataRAM_WD2), 269 | .WE2(CPU_Debug_DataRAM_WE2), 270 | .RD2(CPU_Debug_DataRAM_RD2), 271 | .ResultM(ResultM), 272 | .ResultW(ResultW), 273 | .RdM(RdM), 274 | .RdW(RdW), 275 | .RegWriteM(RegWriteM), 276 | .RegWriteW(RegWriteW), 277 | .MemToRegM(MemToRegM), 278 | .MemToRegW(MemToRegW) 279 | ); 280 | 281 | DataExt DataExt1( 282 | .IN(DM_RD), 283 | .LoadedBytesSelect(LoadedBytesSelect), 284 | .RegWriteW(RegWriteW), 285 | .OUT(DM_RD_Ext) 286 | ); 287 | // --------------------------------------------- 288 | // Harzard Unit 289 | // --------------------------------------------- 290 | HarzardUnit HarzardUnit1( 291 | .CpuRst(CPU_RST), 292 | .BranchE(BranchE), 293 | .JalrE(JalrE), 294 | .JalD(JalD), 295 | .Rs1D(Rs1D), 296 | .Rs2D(Rs2D), 297 | .Rs1E(Rs1E), 298 | .Rs2E(Rs2E), 299 | .RegReadE(RegReadE), 300 | .MemToRegE(MemToRegE), 301 | .RdE(RdE), 302 | .RdM(RdM), 303 | .RegWriteM(RegWriteM), 304 | .RdW(RdW), 305 | .RegWriteW(RegWriteW), 306 | .ICacheMiss(1'b0), 307 | .DCacheMiss(1'b0), 308 | .StallF(StallF), 309 | .FlushF(FlushF), 310 | .StallD(StallD), 311 | .FlushD(FlushD), 312 | .StallE(StallE), 313 | .FlushE(FlushE), 314 | .StallM(StallM), 315 | .FlushM(FlushM), 316 | .StallW(StallW), 317 | .FlushW(FlushW), 318 | .Forward1E(Forward1E), 319 | .Forward2E(Forward2E) 320 | ); 321 | 322 | endmodule 323 | 324 | //功能说明 325 | //RV32I 指令集CPU的顶层模块 326 | //实验要求 327 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/RegisterFile.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB（Embeded System Lab） 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: RegisterFile 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module RegisterFile( 13 | input wire clk, 14 | input wire rst, 15 | input wire WE3, 16 | input wire [4:0] A1, 17 | input wire [4:0] A2, 18 | input wire [4:0] A3, 19 | input wire [31:0] WD3, 20 | output wire [31:0] RD1, 21 | output wire [31:0] RD2 22 | ); 23 | 24 | reg [31:0] RegFile[31:1]; 25 | integer i; 26 | // 27 | always@(negedge clk or posedge rst) 28 | begin 29 | if(rst) for(i=1;i<32;i=i+1) RegFile[i][31:0]<=32'b0; 30 | else if( (WE3==1'b1) && (A3!=5'b0) ) RegFile[A3]<=WD3; 31 | end 32 | // 33 | assign RD1= (A1==5'b0)?32'b0:RegFile[A1]; 34 | assign RD2= (A2==5'b0)?32'b0:RegFile[A2]; 35 | 36 | endmodule 37 | 38 | //功能说明 39 | //上升沿写入，异步读的寄存器堆，0号寄存器值始终为32'b0 40 | //在接入RV32Core时，输入为~clk，因此本模块时钟输入和其他部件始终相反 41 | //等价于例化本模块时正常接入时钟clk，同时修改代码为always@(negedge clk or negedge rst) 42 | //实验要求 43 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/WBSegReg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB（Embeded System Lab） 4 | // Engineer: Haojun Xia & Xuan Wang 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: WBSegReg 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: Write Back Segment Register 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module WBSegReg( 13 | input wire clk, 14 | input wire en, 15 | input wire clear, 16 | //Data Memory Access 17 | input wire [31:0] A, 18 | input wire [31:0] WD, 19 | input wire [3:0] WE, 20 | output wire [31:0] RD, 21 | output reg [1:0] LoadedBytesSelect, 22 | //Data Memory Debug 23 | input wire [31:0] A2, 24 | input wire [31:0] WD2, 25 | input wire [3:0] WE2, 26 | output wire [31:0] RD2, 27 | //input control signals 28 | input wire [31:0] ResultM, 29 | output reg [31:0] ResultW, 30 | input wire [4:0] RdM, 31 | output reg [4:0] RdW, 32 | //output constrol signals 33 | input wire [2:0] RegWriteM, 34 | output reg [2:0] RegWriteW, 35 | input wire MemToRegM, 36 | output reg MemToRegW 37 | ); 38 | 39 | // 40 | initial begin 41 | LoadedBytesSelect = 2'b00; 42 | RegWriteW = 1'b0; 43 | MemToRegW = 1'b0; 44 | ResultW = 0; 45 | RdW = 5'b0; 46 | end 47 | // 48 | always@(posedge clk) 49 | if(en) begin 50 | LoadedBytesSelect <= clear ? 2'b00 : A[1:0]; 51 | RegWriteW <= clear ? 1'b0 : RegWriteM; 52 | MemToRegW <= clear ? 1'b0 : MemToRegM; 53 | ResultW <= clear ? 0 : ResultM; 54 | RdW <= clear ? 5'b0 : RdM; 55 | end 56 | 57 | wire [31:0] RD_raw; 58 | DataRam DataRamInst ( 59 | .clk (clk), //请补全 60 | .wea (WE<=t4(3), jmp to tag 32 | ori t1, t0, 0 # t1 = t0 33 | jalr zero, ra, 0 # pc = ra 34 | 35 | tag: 36 | addi t0, t0, -1 # t0-- 37 | 38 | addi sp, sp, -4 # sp-=4 # push ra to stack 39 | sw ra, (sp) # mem[sp] = ra 40 | 41 | addi sp, sp, -4 # sp-=4 # push t0 to stack 42 | sw t0, (sp) # mem[sp] = t0 43 | 44 | jal ra, Fibonacci # 计算 Fib(n-1) 45 | 46 | lw t0, (sp) # t0=mem[sp] # pop t0 from stack 47 | addi t0, t0, -1 # t0-- 48 | 49 | sw t1, (sp) # mem[sp] = t1 50 | jal ra, Fibonacci # 计算 Fib(n-2) 51 | lw t2, (sp) # ra=mem[sp] # pop t2 from stack 52 | addi sp, sp, 4 # sp+=4 53 | add t1, t1, t2 # t1+=t2 54 | 55 | lw ra, (sp) # ra=mem[sp] # pop ra from stack 56 | addi sp, sp, 4 # sp+=4 57 | 58 | jalr zero, ra,0 # pc = ra 59 | 60 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/ASMCode/Number2Ascii.S: -------------------------------------------------------------------------------- 1 | # 概述：数字转十进制ASCII码 2 | # Author: WangXuan 3 | # 4 | # 系统要求：1、具有一个数据RAM 5 | # 2、测试该代码时，不需要初始化DataRam，只需要将指令流烧入InstrRam。 6 | # 3、请根据实际情况将a0设置为你的DataRam的地址，例如该系统中DataRam起始地址为0x00000000，则我将计算结果写入了0x00000000 7 | # 8 | 9 | 10 | .org 0x0 11 | .global _start 12 | _start: 13 | 14 | ori a0, zero, 1395 # a0 = 1395 15 | add a0, a0 , a0 # a0 = 2790 16 | add a0, a0 , a0 # a0 = 5580 17 | jal ra, Number2DecimalAscii # 调用函数Number2DecimalAscii计算 a0 的十进制ASCII，结果应该是 0x30383535，存在 a0 里 18 | 19 | lui t0, 0x00000 # t0 = 0x00000000 20 | sw a0, 0(t0) # a0写入(t0) 21 | infinity_loop: 22 | jal zero, infinity_loop # 死循环 23 | 24 | 25 | Number2DecimalAscii: 26 | # 函数:Number2DecimalAscii：计算a0里低13位二进制数对应的十进制的ASCII码，存放在a0里 27 | # 例: a0=0x12345678，其低13位为0x1678，即5752 28 | # 则调用该函数后 a0=0x32353735，因为0x32, 0x35, 0x37, 0x35分别为2 5 7 5 的ASCII码 29 | # 之所以使用低13位，因为13位二进制数取值范围位0~8191，不会超过4位十进制数 30 | # 改变数据RAM： 无 31 | # 改变的寄存器：a0, t0, t1, t2 32 | # 调用方法：使用 jal ra, Number2DecimalAscii 指令调用，因为返回时需要用到 ra 寄存器作为返回地址 33 | lui t0, 0x01fff # t0 = 0x01fff000 34 | srl t0, t0 , 12 # t0 = 0x00001fff 35 | and t0, a0 , t0 # t0 = t0 & a0 36 | lui a0, 0x30303 # a0 = 0x30303000 37 | ori a0, a0 , 0x030 # a0 = 0x30303030 38 | 39 | ori t1, zero, 1000 # t1 = 1000 40 | thousand: 41 | bltu t0, t1 , thousand_next # if t0<1000 jump to thousand_next 42 | addi t0, t0 , -1000 # t0 -= 1000 43 | addi a0, a0 , 0x1 # a0 += 0x00000001 44 | jal zero, thousand # jump to thousand 45 | thousand_next: 46 | 47 | ori t1, zero, 100 # t1 = 100 48 | hundred: 49 | bltu t0, t1 , hundred_next # if t0<100 jump to hundred_next 50 | addi t0, t0 , -100 # t0 -= 100 51 | addi a0, a0 , 0x100 # a0 += 0x00000100 52 | jal zero, hundred 53 | hundred_next: 54 | 55 | lui t2, 0x00010 # t2 = 0x00010000 56 | ori t1, zero, 10 # t1 = 10 57 | ten: 58 | bltu t0, t1 , ten_next # if t0<10 jump to ten_next 59 | addi t0, t0 , -10 # t0 -= 10 60 | add a0, a0 , t2 # a0 += 0x00010000 61 | jal zero, ten 62 | ten_next: 63 | 64 | lui t2, 0x01000 # t2 = 0x01000000 65 | ori t1, zero, 1 # t1 = 1 66 | one: 67 | bltu t0, t1 , one_next # if t0<1 jump to one_next 68 | addi t0, t0 , -1 # t0 -= 1 69 | add a0, a0 , t2 # a0 += 0x01000000 70 | jal zero, one 71 | one_next: 72 | jalr zero, ra, 0 73 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/ASMCode/QuickSort.S: -------------------------------------------------------------------------------- 1 | # 概述：对数组进行原地快速排序 2 | # Author: WangXuan 3 | # 4 | # 系统要求：1、具有一个大小至少为0x400 Byte的数据RAM （该程序中，其高地址用作栈，低地址用作被排序的数组） 5 | # 2、测试该代码时，不需要初始化DataRam，只需要将指令流烧入InstrRam。因为有一系列指令去准备被排序的数组。 6 | # 3、请根据实际情况将a0设置为你的DataRam的地址，例如该系统中DataRam起始地址为0x00000000，则第一条指令就是 lui a0, 0x00000 7 | # 8 | 9 | 10 | .org 0x0 11 | .global _start 12 | _start: 13 | 14 | main: # main函数开始，在DataRam里初始化一段数据，然后调用QuickSort进行排序，排序后进入死循环。请使用仿真或UART调试器查看排序后的数据 15 | lui a0, 0x00000 # 设置DataRam的起始地址为0x00000000，也用作被排序数组的起始地址，即DataRam的起始地址 16 | addi sp, a0 , 0x400 # 设置栈顶指针 17 | 18 | or a2, a0, zero 19 | 20 | addi t0, zero, -3 # 用一系列指令向a0里写入被排序的数组，可以是负数 21 | sw t0, (a2) 22 | addi a2, a2, 4 23 | addi t0, zero, -7 24 | sw t0, (a2) 25 | addi a2, a2, 4 26 | addi t0, zero, 6 27 | sw t0, (a2) 28 | addi a2, a2, 4 29 | addi t0, zero, 5 30 | sw t0, (a2) 31 | addi a2, a2, 4 32 | addi t0, zero, -2 33 | sw t0, (a2) 34 | addi a2, a2, 4 35 | addi t0, zero, 2 36 | sw t0, (a2) 37 | addi a2, a2, 4 38 | addi t0, zero, -9 39 | sw t0, (a2) 40 | addi a2, a2, 4 41 | addi t0, zero, -4 42 | sw t0, (a2) 43 | addi a2, a2, 4 44 | addi t0, zero, -6 45 | sw t0, (a2) 46 | addi a2, a2, 4 47 | addi t0, zero, 8 48 | sw t0, (a2) 49 | addi a2, a2, 4 50 | addi t0, zero, 1 51 | sw t0, (a2) 52 | addi a2, a2, 4 53 | addi t0, zero, -5 54 | sw t0, (a2) 55 | addi a2, a2, 4 56 | addi t0, zero, 7 57 | sw t0, (a2) 58 | addi a2, a2, 4 59 | addi t0, zero, 0 60 | sw t0, (a2) 61 | addi a2, a2, 4 62 | addi t0, zero, 3 63 | sw t0, (a2) 64 | addi a2, a2, 4 65 | addi t0, zero, -1 66 | sw t0, (a2) 67 | addi a2, a2, 4 68 | addi t0, zero, 4 69 | sw t0, (a2) 70 | addi a2, a2, 4 71 | addi t0, zero, 9 72 | sw t0, (a2) 73 | addi a2, a2, 4 74 | addi t0, zero, -8 75 | sw t0, (a2) 76 | 77 | 78 | or a1, zero, zero # 准备函数参数，a1=0 79 | sub a2, a2, a0 # 准备函数参数，a2=数组最后一个元素的地址偏移 80 | jal ra , QuickSort # 开始排序 81 | infinity_loop: 82 | jal zero, infinity_loop # 排序结束，死循环 83 | 84 | QuickSort: 85 | # 函数:QuickSort：以a0为基地址的原地升序快速排序，a1是start即开始下标，a2是end即结束下标 86 | # 例: a0=0x00000100，a1=0, a2=32，则计算从0x00000100开始的32个4Byte数的快速排序 87 | # 注: 以有符号数为比较标准。例如0xffffffff应该排在0x00000001前面，因为0xffffffff代表-1，比1要小 88 | # 之所以使用低13位，因为13位二进制数取值范围位0~8191，不会超过4位十进制数 89 | # 改变数据RAM： 除了被排序的数组外，还使用了以sp寄存器为栈顶指针的栈。使用栈的大小根据排序长度而不同，调用前合理设置sp的值以防爆栈 90 | # 改变的寄存器： t0, t1, t2, t3, t4 91 | 92 | bge a1, a2, QuickSortReturn # if a1>=a2, end<=start, jump to return 93 | or t1, a1, zero # t1=i=a1=start 94 | or t2, a2, zero # t2=j=a2=end 95 | add t0, a0, t1 # 96 | lw t0, (t0) # t0=key=lst[start] 97 | 98 | PartationStart: 99 | PartationFirstStart: # start of for loop 100 | bge t1, t2, PartationEnd # if i>=j, branch to next step 101 | add t3, a0, t2 # 102 | lw t3, (t3) # t3=lst[j] 103 | blt t3, t0, PartationFirstEnd # if lst[j]=j, branch to next step 112 | add t3, a0, t1 # 113 | lw t3, (t3) # t3=lst[i] 114 | blt t0, t3, PartationSecondEnd # if keystart){ 168 | # int i = start,j = end,key = lst[start]; 169 | # while(i < j){ 170 | # for (;i < j && key <= lst[j];j--); 171 | # lst[i] = lst[j]; 172 | # for (;i < j && key >= lst[i];i++); 173 | # lst[j] = lst[i]; 174 | # } 175 | # lst[i] = key; 176 | # QuickSort(lst, start, i - 1); 177 | # QuickSort(lst, i + 1, end); 178 | # } 179 | # } 180 | # 181 | # 182 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/SourceCode/riscv_test.h: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #ifndef _ENV_PHYSICAL_SINGLE_CORE_H 4 | #define _ENV_PHYSICAL_SINGLE_CORE_H 5 | 6 | #include "./encoding.h" 7 | 8 | //----------------------------------------------------------------------- 9 | // Begin Macro 10 | //----------------------------------------------------------------------- 11 | #define RVTEST_CODE_BEGIN \ 12 | .section .text; \ 13 | .align 6; \ 14 | .globl _start; \ 15 | _start: \ 16 | addi zero,zero, 0 17 | 18 | //----------------------------------------------------------------------- 19 | // End Macro 20 | //----------------------------------------------------------------------- 21 | 22 | #define RVTEST_CODE_END \ 23 | unimp 24 | 25 | //----------------------------------------------------------------------- 26 | // Pass/Fail Macro 27 | //----------------------------------------------------------------------- 28 | #define TESTNUM gp 29 | 30 | #define TEST_PASSFAIL \ 31 | bne x0, TESTNUM, pass; \ 32 | fail: \ 33 | RVTEST_FAIL; \ 34 | pass: \ 35 | RVTEST_PASS \ 36 | 37 | #define RVTEST_PASS \ 38 | li TESTNUM,1;\ 39 | finish1: jal x20,finish1 40 | 41 | #define RVTEST_FAIL \ 42 | finish2: jal x20,finish2 43 | 44 | //----------------------------------------------------------------------- 45 | // Data Section Macro 46 | //----------------------------------------------------------------------- 47 | 48 | #define EXTRA_DATA 49 | 50 | #define RVTEST_DATA_BEGIN \ 51 | EXTRA_DATA \ 52 | .pushsection .tohost,"aw",@progbits; \ 53 | .align 6; .global tohost; tohost: .dword 0; \ 54 | .align 6; .global fromhost; fromhost: .dword 0; \ 55 | .popsection; \ 56 | .align 4; .global begin_signature; begin_signature: 57 | 58 | #define RVTEST_DATA_END .align 4; .global end_signature; end_signature: 59 | 60 | #endif 61 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/add.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # add.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test add instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, add, 0x00000000, 0x00000000, 0x00000000 ); 21 | TEST_RR_OP( 3, add, 0x00000002, 0x00000001, 0x00000001 ); 22 | TEST_RR_OP( 4, add, 0x0000000a, 0x00000003, 0x00000007 ); 23 | 24 | TEST_RR_OP( 5, add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); 25 | TEST_RR_OP( 6, add, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 ); 26 | TEST_RR_OP( 7, add, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); 27 | 28 | TEST_RR_OP( 8, add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); 29 | TEST_RR_OP( 9, add, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); 30 | TEST_RR_OP( 10, add, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff ); 31 | 32 | TEST_RR_OP( 11, add, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff ); 33 | TEST_RR_OP( 12, add, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 ); 34 | 35 | TEST_RR_OP( 13, add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); 36 | TEST_RR_OP( 14, add, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 ); 37 | TEST_RR_OP( 15, add, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff ); 38 | 39 | TEST_RR_OP( 16, add, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff ); 40 | 41 | #------------------------------------------------------------- 42 | # Source/Destination tests 43 | #------------------------------------------------------------- 44 | 45 | TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 ); 46 | TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 ); 47 | TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 ); 48 | 49 | #------------------------------------------------------------- 50 | # Bypassing tests 51 | #------------------------------------------------------------- 52 | 53 | TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 ); 54 | TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 ); 55 | TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 ); 56 | 57 | TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 ); 58 | TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 ); 59 | TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 ); 60 | TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 ); 61 | TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 ); 62 | TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 ); 63 | 64 | TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 ); 65 | TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 ); 66 | TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 ); 67 | TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 ); 68 | TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 ); 69 | TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 ); 70 | 71 | TEST_RR_ZEROSRC1( 35, add, 15, 15 ); 72 | TEST_RR_ZEROSRC2( 36, add, 32, 32 ); 73 | TEST_RR_ZEROSRC12( 37, add, 0 ); 74 | TEST_RR_ZERODEST( 38, add, 16, 30 ); 75 | 76 | TEST_PASSFAIL 77 | 78 | RVTEST_CODE_END 79 | 80 | .data 81 | RVTEST_DATA_BEGIN 82 | 83 | TEST_DATA 84 | 85 | RVTEST_DATA_END 86 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/addi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # addi.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test addi instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, addi, 0x00000000, 0x00000000, 0x000 ); 21 | TEST_IMM_OP( 3, addi, 0x00000002, 0x00000001, 0x001 ); 22 | TEST_IMM_OP( 4, addi, 0x0000000a, 0x00000003, 0x007 ); 23 | 24 | TEST_IMM_OP( 5, addi, 0xfffffffffffff800, 0x0000000000000000, 0x800 ); 25 | TEST_IMM_OP( 6, addi, 0xffffffff80000000, 0xffffffff80000000, 0x000 ); 26 | TEST_IMM_OP( 7, addi, 0xffffffff7ffff800, 0xffffffff80000000, 0x800 ); 27 | 28 | TEST_IMM_OP( 8, addi, 0x00000000000007ff, 0x00000000, 0x7ff ); 29 | TEST_IMM_OP( 9, addi, 0x000000007fffffff, 0x7fffffff, 0x000 ); 30 | TEST_IMM_OP( 10, addi, 0x00000000800007fe, 0x7fffffff, 0x7ff ); 31 | 32 | TEST_IMM_OP( 11, addi, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff ); 33 | TEST_IMM_OP( 12, addi, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 ); 34 | 35 | TEST_IMM_OP( 13, addi, 0xffffffffffffffff, 0x0000000000000000, 0xfff ); 36 | TEST_IMM_OP( 14, addi, 0x0000000000000000, 0xffffffffffffffff, 0x001 ); 37 | TEST_IMM_OP( 15, addi, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff ); 38 | 39 | TEST_IMM_OP( 16, addi, 0x0000000080000000, 0x7fffffff, 0x001 ); 40 | 41 | #------------------------------------------------------------- 42 | # Source/Destination tests 43 | #------------------------------------------------------------- 44 | 45 | TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 ); 46 | 47 | #------------------------------------------------------------- 48 | # Bypassing tests 49 | #------------------------------------------------------------- 50 | 51 | TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 ); 52 | TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 ); 53 | TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13, 9 ); 54 | 55 | TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 ); 56 | TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 ); 57 | TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13, 9 ); 58 | 59 | TEST_IMM_ZEROSRC1( 24, addi, 32, 32 ); 60 | TEST_IMM_ZERODEST( 25, addi, 33, 50 ); 61 | 62 | TEST_PASSFAIL 63 | 64 | RVTEST_CODE_END 65 | 66 | .data 67 | RVTEST_DATA_BEGIN 68 | 69 | TEST_DATA 70 | 71 | RVTEST_DATA_END 72 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/and.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # and.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test and instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Logical tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); 21 | TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); 22 | TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); 23 | TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 ); 24 | 25 | #------------------------------------------------------------- 26 | # Source/Destination tests 27 | #------------------------------------------------------------- 28 | 29 | TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); 30 | TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); 31 | TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 ); 32 | 33 | #------------------------------------------------------------- 34 | # Bypassing tests 35 | #------------------------------------------------------------- 36 | 37 | TEST_RR_DEST_BYPASS( 9, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); 38 | TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); 39 | TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); 40 | 41 | TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); 42 | TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); 43 | TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); 44 | #TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); 45 | #TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); 46 | #TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); 47 | 48 | #TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); 49 | #TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); 50 | #TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); 51 | #TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); 52 | #TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); 53 | #TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); 54 | 55 | #TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 ); 56 | #TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff ); 57 | #TEST_RR_ZEROSRC12( 26, and, 0 ); 58 | #TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 ); 59 | 60 | TEST_PASSFAIL 61 | 62 | RVTEST_CODE_END 63 | 64 | .data 65 | RVTEST_DATA_BEGIN 66 | 67 | TEST_DATA 68 | 69 | RVTEST_DATA_END 70 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/andi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # andi.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test andi instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Logical tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f ); 21 | TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 ); 22 | TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f ); 23 | TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 ); 24 | 25 | #------------------------------------------------------------- 26 | # Source/Destination tests 27 | #------------------------------------------------------------- 28 | 29 | TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 ); 30 | 31 | #------------------------------------------------------------- 32 | # Bypassing tests 33 | #------------------------------------------------------------- 34 | 35 | TEST_IMM_DEST_BYPASS( 7, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f ); 36 | TEST_IMM_DEST_BYPASS( 8, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 ); 37 | TEST_IMM_DEST_BYPASS( 9, 2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f ); 38 | 39 | TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f ); 40 | TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 ); 41 | TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f ); 42 | 43 | TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 ); 44 | TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f ); 45 | 46 | TEST_PASSFAIL 47 | 48 | RVTEST_CODE_END 49 | 50 | .data 51 | RVTEST_DATA_BEGIN 52 | 53 | TEST_DATA 54 | 55 | RVTEST_DATA_END 56 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/auipc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # auipc.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test auipc instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a0, 10000, \ 17 | .align 3; \ 18 | lla a0, 1f + 10000; \ 19 | jal a1, 1f; \ 20 | 1: sub a0, a0, a1; \ 21 | ) 22 | 23 | TEST_CASE(3, a0, -10000, \ 24 | .align 3; \ 25 | lla a0, 1f - 10000; \ 26 | jal a1, 1f; \ 27 | 1: sub a0, a0, a1; \ 28 | ) 29 | 30 | TEST_PASSFAIL 31 | 32 | RVTEST_CODE_END 33 | 34 | .data 35 | RVTEST_DATA_BEGIN 36 | 37 | TEST_DATA 38 | 39 | RVTEST_DATA_END 40 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/beq.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # beq.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test beq instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Branch tests 18 | #------------------------------------------------------------- 19 | 20 | # Each test checks both forward and backward branches 21 | 22 | TEST_BR2_OP_TAKEN( 2, beq, 0, 0 ); 23 | TEST_BR2_OP_TAKEN( 3, beq, 1, 1 ); 24 | TEST_BR2_OP_TAKEN( 4, beq, -1, -1 ); 25 | 26 | TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 ); 27 | TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 ); 28 | TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 ); 29 | TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 ); 30 | 31 | #------------------------------------------------------------- 32 | # Bypassing tests 33 | #------------------------------------------------------------- 34 | 35 | TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 ); 36 | TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 ); 37 | TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 ); 38 | TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 ); 39 | TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 ); 40 | TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 ); 41 | 42 | TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 ); 43 | TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 ); 44 | TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 ); 45 | TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 ); 46 | TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 ); 47 | TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 ); 48 | 49 | #------------------------------------------------------------- 50 | # Test delay slot instructions not executed nor bypassed 51 | #------------------------------------------------------------- 52 | 53 | TEST_CASE( 21, x1, 3, \ 54 | li x1, 1; \ 55 | beq x0, x0, 1f; \ 56 | addi x1, x1, 1; \ 57 | addi x1, x1, 1; \ 58 | addi x1, x1, 1; \ 59 | addi x1, x1, 1; \ 60 | 1: addi x1, x1, 1; \ 61 | addi x1, x1, 1; \ 62 | ) 63 | 64 | TEST_PASSFAIL 65 | 66 | RVTEST_CODE_END 67 | 68 | .data 69 | RVTEST_DATA_BEGIN 70 | 71 | TEST_DATA 72 | 73 | RVTEST_DATA_END 74 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bge.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # bge.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test bge instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Branch tests 18 | #------------------------------------------------------------- 19 | 20 | # Each test checks both forward and backward branches 21 | 22 | TEST_BR2_OP_TAKEN( 2, bge, 0, 0 ); 23 | TEST_BR2_OP_TAKEN( 3, bge, 1, 1 ); 24 | TEST_BR2_OP_TAKEN( 4, bge, -1, -1 ); 25 | TEST_BR2_OP_TAKEN( 5, bge, 1, 0 ); 26 | TEST_BR2_OP_TAKEN( 6, bge, 1, -1 ); 27 | TEST_BR2_OP_TAKEN( 7, bge, -1, -2 ); 28 | 29 | TEST_BR2_OP_NOTTAKEN( 8, bge, 0, 1 ); 30 | TEST_BR2_OP_NOTTAKEN( 9, bge, -1, 1 ); 31 | TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 ); 32 | TEST_BR2_OP_NOTTAKEN( 11, bge, -2, 1 ); 33 | 34 | #------------------------------------------------------------- 35 | # Bypassing tests 36 | #------------------------------------------------------------- 37 | 38 | TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 ); 39 | TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 ); 40 | TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 ); 41 | TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 ); 42 | TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 ); 43 | TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 ); 44 | 45 | TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 ); 46 | TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 ); 47 | TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 ); 48 | TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 ); 49 | TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 ); 50 | TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 ); 51 | 52 | #------------------------------------------------------------- 53 | # Test delay slot instructions not executed nor bypassed 54 | #------------------------------------------------------------- 55 | 56 | TEST_CASE( 24, x1, 3, \ 57 | li x1, 1; \ 58 | bge x1, x0, 1f; \ 59 | addi x1, x1, 1; \ 60 | addi x1, x1, 1; \ 61 | addi x1, x1, 1; \ 62 | addi x1, x1, 1; \ 63 | 1: addi x1, x1, 1; \ 64 | addi x1, x1, 1; \ 65 | ) 66 | 67 | TEST_PASSFAIL 68 | 69 | RVTEST_CODE_END 70 | 71 | .data 72 | RVTEST_DATA_BEGIN 73 | 74 | TEST_DATA 75 | 76 | RVTEST_DATA_END 77 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bgeu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # bgeu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test bgeu instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | #------------------------------------------------------------- 16 | # Branch tests 17 | #------------------------------------------------------------- 18 | 19 | # Each test checks both forward and backward branches 20 | 21 | TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 ); 22 | TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 ); 23 | TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff ); 24 | TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 ); 25 | TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe ); 26 | TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 ); 27 | 28 | TEST_BR2_OP_NOTTAKEN( 8, bgeu, 0x00000000, 0x00000001 ); 29 | TEST_BR2_OP_NOTTAKEN( 9, bgeu, 0xfffffffe, 0xffffffff ); 30 | TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff ); 31 | TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 ); 32 | 33 | #------------------------------------------------------------- 34 | # Bypassing tests 35 | #------------------------------------------------------------- 36 | 37 | TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 ); 38 | TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 ); 39 | TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 ); 40 | TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 ); 41 | TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 ); 42 | TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 ); 43 | 44 | TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 ); 45 | TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 ); 46 | TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 ); 47 | TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 ); 48 | TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 ); 49 | TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 ); 50 | 51 | #------------------------------------------------------------- 52 | # Test delay slot instructions not executed nor bypassed 53 | #------------------------------------------------------------- 54 | 55 | TEST_CASE( 24, x1, 3, \ 56 | li x1, 1; \ 57 | bgeu x1, x0, 1f; \ 58 | addi x1, x1, 1; \ 59 | addi x1, x1, 1; \ 60 | addi x1, x1, 1; \ 61 | addi x1, x1, 1; \ 62 | 1: addi x1, x1, 1; \ 63 | addi x1, x1, 1; \ 64 | ) 65 | 66 | TEST_PASSFAIL 67 | 68 | RVTEST_CODE_END 69 | 70 | .data 71 | RVTEST_DATA_BEGIN 72 | 73 | TEST_DATA 74 | 75 | RVTEST_DATA_END 76 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/blt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # blt.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test blt instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Branch tests 18 | #------------------------------------------------------------- 19 | 20 | # Each test checks both forward and backward branches 21 | 22 | TEST_BR2_OP_TAKEN( 2, blt, 0, 1 ); 23 | TEST_BR2_OP_TAKEN( 3, blt, -1, 1 ); 24 | TEST_BR2_OP_TAKEN( 4, blt, -2, -1 ); 25 | 26 | TEST_BR2_OP_NOTTAKEN( 5, blt, 1, 0 ); 27 | TEST_BR2_OP_NOTTAKEN( 6, blt, 1, -1 ); 28 | TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 ); 29 | TEST_BR2_OP_NOTTAKEN( 8, blt, 1, -2 ); 30 | 31 | #------------------------------------------------------------- 32 | # Bypassing tests 33 | #------------------------------------------------------------- 34 | 35 | TEST_BR2_SRC12_BYPASS( 9, 0, 0, blt, 0, -1 ); 36 | TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 ); 37 | TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 ); 38 | TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 ); 39 | TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 ); 40 | TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 ); 41 | 42 | TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 ); 43 | TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 ); 44 | TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 ); 45 | TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 ); 46 | TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 ); 47 | TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 ); 48 | 49 | #------------------------------------------------------------- 50 | # Test delay slot instructions not executed nor bypassed 51 | #------------------------------------------------------------- 52 | 53 | TEST_CASE( 21, x1, 3, \ 54 | li x1, 1; \ 55 | blt x0, x1, 1f; \ 56 | addi x1, x1, 1; \ 57 | addi x1, x1, 1; \ 58 | addi x1, x1, 1; \ 59 | addi x1, x1, 1; \ 60 | 1: addi x1, x1, 1; \ 61 | addi x1, x1, 1; \ 62 | ) 63 | 64 | TEST_PASSFAIL 65 | 66 | RVTEST_CODE_END 67 | 68 | .data 69 | RVTEST_DATA_BEGIN 70 | 71 | TEST_DATA 72 | 73 | RVTEST_DATA_END 74 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bltu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # bltu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test bltu instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Branch tests 18 | #------------------------------------------------------------- 19 | 20 | # Each test checks both forward and backward branches 21 | 22 | TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 ); 23 | TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff ); 24 | TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff ); 25 | 26 | TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 ); 27 | TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe ); 28 | TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 ); 29 | TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff ); 30 | 31 | #------------------------------------------------------------- 32 | # Bypassing tests 33 | #------------------------------------------------------------- 34 | 35 | TEST_BR2_SRC12_BYPASS( 9, 0, 0, bltu, 0xf0000000, 0xefffffff ); 36 | TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff ); 37 | TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff ); 38 | TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff ); 39 | TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff ); 40 | TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff ); 41 | 42 | TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff ); 43 | TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff ); 44 | TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff ); 45 | TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff ); 46 | TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff ); 47 | TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff ); 48 | 49 | #------------------------------------------------------------- 50 | # Test delay slot instructions not executed nor bypassed 51 | #------------------------------------------------------------- 52 | 53 | TEST_CASE( 21, x1, 3, \ 54 | li x1, 1; \ 55 | bltu x0, x1, 1f; \ 56 | addi x1, x1, 1; \ 57 | addi x1, x1, 1; \ 58 | addi x1, x1, 1; \ 59 | addi x1, x1, 1; \ 60 | 1: addi x1, x1, 1; \ 61 | addi x1, x1, 1; \ 62 | ) 63 | 64 | TEST_PASSFAIL 65 | 66 | RVTEST_CODE_END 67 | 68 | .data 69 | RVTEST_DATA_BEGIN 70 | 71 | TEST_DATA 72 | 73 | RVTEST_DATA_END 74 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bne.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # bne.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test bne instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Branch tests 18 | #------------------------------------------------------------- 19 | 20 | # Each test checks both forward and backward branches 21 | 22 | TEST_BR2_OP_TAKEN( 2, bne, 0, 1 ); 23 | TEST_BR2_OP_TAKEN( 3, bne, 1, 0 ); 24 | TEST_BR2_OP_TAKEN( 4, bne, -1, 1 ); 25 | TEST_BR2_OP_TAKEN( 5, bne, 1, -1 ); 26 | 27 | TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 ); 28 | TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 ); 29 | TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 ); 30 | 31 | #------------------------------------------------------------- 32 | # Bypassing tests 33 | #------------------------------------------------------------- 34 | 35 | TEST_BR2_SRC12_BYPASS( 9, 0, 0, bne, 0, 0 ); 36 | TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 ); 37 | TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 ); 38 | TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 ); 39 | TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 ); 40 | TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 ); 41 | 42 | TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 ); 43 | TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 ); 44 | TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 ); 45 | TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 ); 46 | TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 ); 47 | TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 ); 48 | 49 | #------------------------------------------------------------- 50 | # Test delay slot instructions not executed nor bypassed 51 | #------------------------------------------------------------- 52 | 53 | TEST_CASE( 21, x1, 3, \ 54 | li x1, 1; \ 55 | bne x1, x0, 1f; \ 56 | addi x1, x1, 1; \ 57 | addi x1, x1, 1; \ 58 | addi x1, x1, 1; \ 59 | addi x1, x1, 1; \ 60 | 1: addi x1, x1, 1; \ 61 | addi x1, x1, 1; \ 62 | ) 63 | 64 | TEST_PASSFAIL 65 | 66 | RVTEST_CODE_END 67 | 68 | .data 69 | RVTEST_DATA_BEGIN 70 | 71 | TEST_DATA 72 | 73 | RVTEST_DATA_END 74 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/fence_i.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fence_i.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test self-modifying code and the fence.i instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | li a3, 111 17 | lh a0, insn 18 | lh a1, insn+2 19 | 20 | # test I$ hit 21 | .align 6 22 | sh a0, 1f, t0 23 | sh a1, 1f+2, t0 24 | fence.i 25 | 26 | 1: addi a3, a3, 222 27 | TEST_CASE( 2, a3, 444, nop ) 28 | 29 | # test prefetcher hit 30 | li a4, 100 31 | 1: addi a4, a4, -1 32 | bnez a4, 1b 33 | 34 | sh a0, 1f, t0 35 | sh a1, 1f+2, t0 36 | fence.i 37 | 38 | .align 6 39 | 1: addi a3, a3, 555 40 | TEST_CASE( 3, a3, 777, nop ) 41 | 42 | TEST_PASSFAIL 43 | 44 | RVTEST_CODE_END 45 | 46 | .data 47 | RVTEST_DATA_BEGIN 48 | 49 | TEST_DATA 50 | 51 | insn: 52 | addi a3, a3, 333 53 | 54 | RVTEST_DATA_END 55 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/include/riscv_test.h: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #ifndef _ENV_PHYSICAL_SINGLE_CORE_H 4 | #define _ENV_PHYSICAL_SINGLE_CORE_H 5 | 6 | #include "./encoding.h" 7 | 8 | //----------------------------------------------------------------------- 9 | // Begin Macro 10 | //----------------------------------------------------------------------- 11 | #define RVTEST_CODE_BEGIN \ 12 | .section .text; \ 13 | .align 6; \ 14 | .globl _start; \ 15 | _start: \ 16 | addi zero,zero, 0 17 | 18 | //----------------------------------------------------------------------- 19 | // End Macro 20 | //----------------------------------------------------------------------- 21 | 22 | #define RVTEST_CODE_END \ 23 | unimp 24 | 25 | //----------------------------------------------------------------------- 26 | // Pass/Fail Macro 27 | //----------------------------------------------------------------------- 28 | #define TESTNUM gp 29 | 30 | #define TEST_PASSFAIL \ 31 | bne x0, TESTNUM, pass; \ 32 | fail: \ 33 | RVTEST_FAIL; \ 34 | pass: \ 35 | RVTEST_PASS \ 36 | 37 | #define RVTEST_PASS \ 38 | li TESTNUM,1;\ 39 | finish1: jal x20,finish1 40 | 41 | #define RVTEST_FAIL \ 42 | finish2: jal x20,finish2 43 | 44 | //----------------------------------------------------------------------- 45 | // Data Section Macro 46 | //----------------------------------------------------------------------- 47 | 48 | #define EXTRA_DATA 49 | 50 | #define RVTEST_DATA_BEGIN \ 51 | EXTRA_DATA \ 52 | .pushsection .tohost,"aw",@progbits; \ 53 | .align 6; .global tohost; tohost: .dword 0; \ 54 | .align 6; .global fromhost; fromhost: .dword 0; \ 55 | .popsection; \ 56 | .align 4; .global begin_signature; begin_signature: 57 | 58 | #define RVTEST_DATA_END .align 4; .global end_signature; end_signature: 59 | 60 | #endif 61 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/jal.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # jal.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test jal instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Test 2: Basic test 18 | #------------------------------------------------------------- 19 | 20 | test_2: 21 | li TESTNUM, 2 22 | li ra, 0 23 | 24 | jal x4, target_2 25 | linkaddr_2: 26 | nop 27 | nop 28 | 29 | j fail 30 | 31 | target_2: 32 | la x6, linkaddr_2 33 | bne x6, x4, fail 34 | 35 | #------------------------------------------------------------- 36 | # Test delay slot instructions not executed nor bypassed 37 | #------------------------------------------------------------- 38 | 39 | TEST_CASE( 3, ra, 3, \ 40 | li ra, 1; \ 41 | jal x0, 1f; \ 42 | addi ra, ra, 1; \ 43 | addi ra, ra, 1; \ 44 | addi ra, ra, 1; \ 45 | addi ra, ra, 1; \ 46 | 1: addi ra, ra, 1; \ 47 | addi ra, ra, 1; \ 48 | ) 49 | 50 | TEST_PASSFAIL 51 | 52 | RVTEST_CODE_END 53 | 54 | .data 55 | RVTEST_DATA_BEGIN 56 | 57 | TEST_DATA 58 | 59 | RVTEST_DATA_END 60 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/jalr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # jalr.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test jalr instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Test 2: Basic test 18 | #------------------------------------------------------------- 19 | 20 | test_2: 21 | li TESTNUM, 2 22 | li t0, 0 23 | la t1, target_2 24 | 25 | jalr t0, t1, 0 26 | linkaddr_2: 27 | j fail 28 | 29 | target_2: 30 | la t1, linkaddr_2 31 | bne t0, t1, fail 32 | 33 | #------------------------------------------------------------- 34 | # Bypassing tests 35 | #------------------------------------------------------------- 36 | 37 | TEST_JALR_SRC1_BYPASS( 4, 0, jalr ); 38 | TEST_JALR_SRC1_BYPASS( 5, 1, jalr ); 39 | TEST_JALR_SRC1_BYPASS( 6, 2, jalr ); 40 | 41 | #------------------------------------------------------------- 42 | # Test delay slot instructions not executed nor bypassed 43 | #------------------------------------------------------------- 44 | 45 | .option push 46 | .align 2 47 | .option norvc 48 | TEST_CASE( 7, t0, 4, \ 49 | li t0, 1; \ 50 | la t1, 1f; \ 51 | jr t1, -4; \ 52 | addi t0, t0, 1; \ 53 | addi t0, t0, 1; \ 54 | addi t0, t0, 1; \ 55 | addi t0, t0, 1; \ 56 | 1: addi t0, t0, 1; \ 57 | addi t0, t0, 1; \ 58 | ) 59 | .option pop 60 | 61 | TEST_PASSFAIL 62 | 63 | RVTEST_CODE_END 64 | 65 | .data 66 | RVTEST_DATA_BEGIN 67 | 68 | TEST_DATA 69 | 70 | RVTEST_DATA_END 71 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lb.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lb.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lb instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_LD_OP( 2, lb, 0xffffffffffffffff, 0, tdat ); 21 | TEST_LD_OP( 3, lb, 0x0000000000000000, 1, tdat ); 22 | TEST_LD_OP( 4, lb, 0xfffffffffffffff0, 2, tdat ); 23 | TEST_LD_OP( 5, lb, 0x000000000000000f, 3, tdat ); 24 | 25 | # Test with negative offset 26 | 27 | TEST_LD_OP( 6, lb, 0xffffffffffffffff, -3, tdat4 ); 28 | TEST_LD_OP( 7, lb, 0x0000000000000000, -2, tdat4 ); 29 | TEST_LD_OP( 8, lb, 0xfffffffffffffff0, -1, tdat4 ); 30 | TEST_LD_OP( 9, lb, 0x000000000000000f, 0, tdat4 ); 31 | 32 | # Test with a negative base 33 | 34 | TEST_CASE( 10, x5, 0xffffffffffffffff, \ 35 | la x1, tdat; \ 36 | addi x1, x1, -32; \ 37 | lb x5, 32(x1); \ 38 | ) 39 | 40 | # Test with unaligned base 41 | 42 | TEST_CASE( 11, x5, 0x0000000000000000, \ 43 | la x1, tdat; \ 44 | addi x1, x1, -6; \ 45 | lb x5, 7(x1); \ 46 | ) 47 | 48 | #------------------------------------------------------------- 49 | # Bypassing tests 50 | #------------------------------------------------------------- 51 | 52 | TEST_LD_DEST_BYPASS( 12, 0, lb, 0xfffffffffffffff0, 1, tdat2 ); 53 | TEST_LD_DEST_BYPASS( 13, 1, lb, 0x000000000000000f, 1, tdat3 ); 54 | TEST_LD_DEST_BYPASS( 14, 2, lb, 0x0000000000000000, 1, tdat1 ); 55 | 56 | TEST_LD_SRC1_BYPASS( 15, 0, lb, 0xfffffffffffffff0, 1, tdat2 ); 57 | TEST_LD_SRC1_BYPASS( 16, 1, lb, 0x000000000000000f, 1, tdat3 ); 58 | TEST_LD_SRC1_BYPASS( 17, 2, lb, 0x0000000000000000, 1, tdat1 ); 59 | 60 | #------------------------------------------------------------- 61 | # Test write-after-write hazard 62 | #------------------------------------------------------------- 63 | 64 | TEST_CASE( 18, x2, 2, \ 65 | la x5, tdat; \ 66 | lb x2, 0(x5); \ 67 | li x2, 2; \ 68 | ) 69 | 70 | TEST_CASE( 19, x2, 2, \ 71 | la x5, tdat; \ 72 | lb x2, 0(x5); \ 73 | nop; \ 74 | li x2, 2; \ 75 | ) 76 | 77 | TEST_PASSFAIL 78 | 79 | RVTEST_CODE_END 80 | 81 | .data 82 | RVTEST_DATA_BEGIN 83 | 84 | TEST_DATA 85 | 86 | tdat: 87 | tdat1: .byte 0xff 88 | tdat2: .byte 0x00 89 | tdat3: .byte 0xf0 90 | tdat4: .byte 0x0f 91 | 92 | RVTEST_DATA_END 93 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lbu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lbu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lbu instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_LD_OP( 2, lbu, 0x00000000000000ff, 0, tdat ); 21 | TEST_LD_OP( 3, lbu, 0x0000000000000000, 1, tdat ); 22 | TEST_LD_OP( 4, lbu, 0x00000000000000f0, 2, tdat ); 23 | TEST_LD_OP( 5, lbu, 0x000000000000000f, 3, tdat ); 24 | 25 | # Test with negative offset 26 | 27 | TEST_LD_OP( 6, lbu, 0x00000000000000ff, -3, tdat4 ); 28 | TEST_LD_OP( 7, lbu, 0x0000000000000000, -2, tdat4 ); 29 | TEST_LD_OP( 8, lbu, 0x00000000000000f0, -1, tdat4 ); 30 | TEST_LD_OP( 9, lbu, 0x000000000000000f, 0, tdat4 ); 31 | 32 | # Test with a negative base 33 | 34 | TEST_CASE( 10, x5, 0x00000000000000ff, \ 35 | la x1, tdat; \ 36 | addi x1, x1, -32; \ 37 | lbu x5, 32(x1); \ 38 | ) 39 | 40 | # Test with unaligned base 41 | 42 | TEST_CASE( 11, x5, 0x0000000000000000, \ 43 | la x1, tdat; \ 44 | addi x1, x1, -6; \ 45 | lbu x5, 7(x1); \ 46 | ) 47 | 48 | #------------------------------------------------------------- 49 | # Bypassing tests 50 | #------------------------------------------------------------- 51 | 52 | TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x00000000000000f0, 1, tdat2 ); 53 | TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x000000000000000f, 1, tdat3 ); 54 | TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x0000000000000000, 1, tdat1 ); 55 | 56 | TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x00000000000000f0, 1, tdat2 ); 57 | TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x000000000000000f, 1, tdat3 ); 58 | TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x0000000000000000, 1, tdat1 ); 59 | 60 | #------------------------------------------------------------- 61 | # Test write-after-write hazard 62 | #------------------------------------------------------------- 63 | 64 | TEST_CASE( 18, x2, 2, \ 65 | la x5, tdat; \ 66 | lbu x2, 0(x5); \ 67 | li x2, 2; \ 68 | ) 69 | 70 | TEST_CASE( 19, x2, 2, \ 71 | la x5, tdat; \ 72 | lbu x2, 0(x5); \ 73 | nop; \ 74 | li x2, 2; \ 75 | ) 76 | 77 | TEST_PASSFAIL 78 | 79 | RVTEST_CODE_END 80 | 81 | .data 82 | RVTEST_DATA_BEGIN 83 | 84 | TEST_DATA 85 | 86 | tdat: 87 | tdat1: .byte 0xff 88 | tdat2: .byte 0x00 89 | tdat3: .byte 0xf0 90 | tdat4: .byte 0x0f 91 | 92 | RVTEST_DATA_END 93 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lh.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lh.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lh instruction. 8 | # 9 | #include "./include/riscv_test.h" 10 | #include "./include/test_macros.h" 11 | 12 | 13 | RVTEST_CODE_BEGIN 14 | 15 | #------------------------------------------------------------- 16 | # Basic tests 17 | #------------------------------------------------------------- 18 | 19 | TEST_LD_OP( 2, lh, 0x00000000000000ff, 0, tdat ); 20 | TEST_LD_OP( 3, lh, 0xffffffffffffff00, 2, tdat ); 21 | TEST_LD_OP( 4, lh, 0x0000000000000ff0, 4, tdat ); 22 | TEST_LD_OP( 5, lh, 0xfffffffffffff00f, 6, tdat ); 23 | 24 | # Test with negative offset 25 | 26 | TEST_LD_OP( 6, lh, 0x00000000000000ff, -6, tdat4 ); 27 | TEST_LD_OP( 7, lh, 0xffffffffffffff00, -4, tdat4 ); 28 | TEST_LD_OP( 8, lh, 0x0000000000000ff0, -2, tdat4 ); 29 | TEST_LD_OP( 9, lh, 0xfffffffffffff00f, 0, tdat4 ); 30 | 31 | # Test with a negative base 32 | 33 | TEST_CASE( 10, x5, 0x00000000000000ff, \ 34 | la x1, tdat; \ 35 | addi x1, x1, -32; \ 36 | lh x5, 32(x1); \ 37 | ) 38 | 39 | # Test with unaligned base 40 | 41 | TEST_CASE( 11, x5, 0xffffffffffffff00, \ 42 | la x1, tdat; \ 43 | addi x1, x1, -5; \ 44 | lh x5, 7(x1); \ 45 | ) 46 | 47 | #------------------------------------------------------------- 48 | # Bypassing tests 49 | #------------------------------------------------------------- 50 | 51 | TEST_LD_DEST_BYPASS( 12, 0, lh, 0x0000000000000ff0, 2, tdat2 ); 52 | TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffffffffffff00f, 2, tdat3 ); 53 | TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffffffffffff00, 2, tdat1 ); 54 | 55 | TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x0000000000000ff0, 2, tdat2 ); 56 | TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffffffffffff00f, 2, tdat3 ); 57 | TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffffffffffff00, 2, tdat1 ); 58 | 59 | #------------------------------------------------------------- 60 | # Test write-after-write hazard 61 | #------------------------------------------------------------- 62 | 63 | TEST_CASE( 18, x2, 2, \ 64 | la x5, tdat; \ 65 | lh x2, 0(x5); \ 66 | li x2, 2; \ 67 | ) 68 | 69 | TEST_CASE( 19, x2, 2, \ 70 | la x5, tdat; \ 71 | lh x2, 0(x5); \ 72 | nop; \ 73 | li x2, 2; \ 74 | ) 75 | 76 | TEST_PASSFAIL 77 | 78 | RVTEST_CODE_END 79 | 80 | .data 81 | RVTEST_DATA_BEGIN 82 | 83 | TEST_DATA 84 | 85 | tdat: 86 | tdat1: .half 0x00ff 87 | tdat2: .half 0xff00 88 | tdat3: .half 0x0ff0 89 | tdat4: .half 0xf00f 90 | 91 | RVTEST_DATA_END 92 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lhu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lhu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lhu instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_LD_OP( 2, lhu, 0x00000000000000ff, 0, tdat ); 21 | TEST_LD_OP( 3, lhu, 0x000000000000ff00, 2, tdat ); 22 | TEST_LD_OP( 4, lhu, 0x0000000000000ff0, 4, tdat ); 23 | TEST_LD_OP( 5, lhu, 0x000000000000f00f, 6, tdat ); 24 | 25 | # Test with negative offset 26 | 27 | TEST_LD_OP( 6, lhu, 0x00000000000000ff, -6, tdat4 ); 28 | TEST_LD_OP( 7, lhu, 0x000000000000ff00, -4, tdat4 ); 29 | TEST_LD_OP( 8, lhu, 0x0000000000000ff0, -2, tdat4 ); 30 | TEST_LD_OP( 9, lhu, 0x000000000000f00f, 0, tdat4 ); 31 | 32 | # Test with a negative base 33 | 34 | TEST_CASE( 10, x5, 0x00000000000000ff, \ 35 | la x1, tdat; \ 36 | addi x1, x1, -32; \ 37 | lhu x5, 32(x1); \ 38 | ) 39 | 40 | # Test with unaligned base 41 | 42 | TEST_CASE( 11, x5, 0x000000000000ff00, \ 43 | la x1, tdat; \ 44 | addi x1, x1, -5; \ 45 | lhu x5, 7(x1); \ 46 | ) 47 | 48 | #------------------------------------------------------------- 49 | # Bypassing tests 50 | #------------------------------------------------------------- 51 | 52 | TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x0000000000000ff0, 2, tdat2 ); 53 | TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x000000000000f00f, 2, tdat3 ); 54 | TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x000000000000ff00, 2, tdat1 ); 55 | 56 | TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x0000000000000ff0, 2, tdat2 ); 57 | TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x000000000000f00f, 2, tdat3 ); 58 | TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x000000000000ff00, 2, tdat1 ); 59 | 60 | #------------------------------------------------------------- 61 | # Test write-after-write hazard 62 | #------------------------------------------------------------- 63 | 64 | TEST_CASE( 18, x2, 2, \ 65 | la x5, tdat; \ 66 | lhu x2, 0(x5); \ 67 | li x2, 2; \ 68 | ) 69 | 70 | TEST_CASE( 19, x2, 2, \ 71 | la x5, tdat; \ 72 | lhu x2, 0(x5); \ 73 | nop; \ 74 | li x2, 2; \ 75 | ) 76 | 77 | TEST_PASSFAIL 78 | 79 | RVTEST_CODE_END 80 | 81 | .data 82 | RVTEST_DATA_BEGIN 83 | 84 | TEST_DATA 85 | 86 | tdat: 87 | tdat1: .half 0x00ff 88 | tdat2: .half 0xff00 89 | tdat3: .half 0x0ff0 90 | tdat4: .half 0xf00f 91 | 92 | RVTEST_DATA_END 93 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lui.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lui.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lui instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_CASE( 2, x1, 0x0000000000000000, lui x1, 0x00000 ); 21 | TEST_CASE( 3, x1, 0xfffffffffffff800, lui x1, 0xfffff;sra x1,x1,1); 22 | TEST_CASE( 4, x1, 0x00000000000007ff, lui x1, 0x7ffff;sra x1,x1,20); 23 | TEST_CASE( 5, x1, 0xfffffffffffff800, lui x1, 0x80000;sra x1,x1,20); 24 | 25 | TEST_CASE( 6, x0, 0, lui x0, 0x80000 ); 26 | 27 | TEST_PASSFAIL 28 | 29 | RVTEST_CODE_END 30 | 31 | .data 32 | RVTEST_DATA_BEGIN 33 | 34 | TEST_DATA 35 | 36 | RVTEST_DATA_END 37 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lw.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lw instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_LD_OP( 2, lw, 0x0000000000ff00ff, 0, tdat ); 21 | TEST_LD_OP( 3, lw, 0xffffffffff00ff00, 4, tdat ); 22 | TEST_LD_OP( 4, lw, 0x000000000ff00ff0, 8, tdat ); 23 | TEST_LD_OP( 5, lw, 0xfffffffff00ff00f, 12, tdat ); 24 | 25 | # Test with negative offset 26 | 27 | TEST_LD_OP( 6, lw, 0x0000000000ff00ff, -12, tdat4 ); 28 | TEST_LD_OP( 7, lw, 0xffffffffff00ff00, -8, tdat4 ); 29 | TEST_LD_OP( 8, lw, 0x000000000ff00ff0, -4, tdat4 ); 30 | TEST_LD_OP( 9, lw, 0xfffffffff00ff00f, 0, tdat4 ); 31 | 32 | # Test with a negative base 33 | 34 | TEST_CASE( 10, x5, 0x0000000000ff00ff, \ 35 | la x1, tdat; \ 36 | addi x1, x1, -32; \ 37 | lw x5, 32(x1); \ 38 | ) 39 | 40 | # Test with unaligned base 41 | 42 | TEST_CASE( 11, x5, 0xffffffffff00ff00, \ 43 | la x1, tdat; \ 44 | addi x1, x1, -3; \ 45 | lw x5, 7(x1); \ 46 | ) 47 | 48 | #------------------------------------------------------------- 49 | # Bypassing tests 50 | #------------------------------------------------------------- 51 | 52 | TEST_LD_DEST_BYPASS( 12, 0, lw, 0x000000000ff00ff0, 4, tdat2 ); 53 | TEST_LD_DEST_BYPASS( 13, 1, lw, 0xfffffffff00ff00f, 4, tdat3 ); 54 | TEST_LD_DEST_BYPASS( 14, 2, lw, 0xffffffffff00ff00, 4, tdat1 ); 55 | 56 | TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x000000000ff00ff0, 4, tdat2 ); 57 | TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xfffffffff00ff00f, 4, tdat3 ); 58 | TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xffffffffff00ff00, 4, tdat1 ); 59 | 60 | #------------------------------------------------------------- 61 | # Test write-after-write hazard 62 | #------------------------------------------------------------- 63 | 64 | TEST_CASE( 18, x2, 2, \ 65 | la x5, tdat; \ 66 | lw x2, 0(x5); \ 67 | li x2, 2; \ 68 | ) 69 | 70 | TEST_CASE( 19, x2, 2, \ 71 | la x5, tdat; \ 72 | lw x2, 0(x5); \ 73 | nop; \ 74 | li x2, 2; \ 75 | ) 76 | 77 | TEST_PASSFAIL 78 | 79 | RVTEST_CODE_END 80 | 81 | .data 82 | RVTEST_DATA_BEGIN 83 | 84 | TEST_DATA 85 | 86 | tdat: 87 | tdat1: .word 0x00ff00ff 88 | tdat2: .word 0xff00ff00 89 | tdat3: .word 0x0ff00ff0 90 | tdat4: .word 0xf00ff00f 91 | 92 | RVTEST_DATA_END 93 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/or.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # or.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test or instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Logical tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 21 | TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); 22 | TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); 23 | TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 ); 24 | 25 | #------------------------------------------------------------- 26 | # Source/Destination tests 27 | #------------------------------------------------------------- 28 | 29 | TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 30 | TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 31 | TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 ); 32 | 33 | #------------------------------------------------------------- 34 | # Bypassing tests 35 | #------------------------------------------------------------- 36 | 37 | TEST_RR_DEST_BYPASS( 9, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 38 | TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); 39 | TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); 40 | 41 | TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 42 | TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); 43 | TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); 44 | TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 45 | TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); 46 | TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); 47 | 48 | TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 49 | TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); 50 | TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); 51 | TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 52 | TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); 53 | TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); 54 | 55 | TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 ); 56 | TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff ); 57 | TEST_RR_ZEROSRC12( 26, or, 0 ); 58 | TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 ); 59 | 60 | TEST_PASSFAIL 61 | 62 | RVTEST_CODE_END 63 | 64 | .data 65 | RVTEST_DATA_BEGIN 66 | 67 | TEST_DATA 68 | 69 | RVTEST_DATA_END 70 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/ori.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # ori.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test ori instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Logical tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, ori, 0xffffffffffffff0f, 0xffffffffff00ff00, 0xf0f ); 21 | TEST_IMM_OP( 3, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); 22 | TEST_IMM_OP( 4, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f ); 23 | TEST_IMM_OP( 5, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); 24 | 25 | #------------------------------------------------------------- 26 | # Source/Destination tests 27 | #------------------------------------------------------------- 28 | 29 | TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 ); 30 | 31 | #------------------------------------------------------------- 32 | # Bypassing tests 33 | #------------------------------------------------------------- 34 | 35 | TEST_IMM_DEST_BYPASS( 7, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); 36 | TEST_IMM_DEST_BYPASS( 8, 1, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f ); 37 | TEST_IMM_DEST_BYPASS( 9, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); 38 | 39 | TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); 40 | TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffffffffffff, 0x0000000000ff00ff, 0xf0f ); 41 | TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); 42 | 43 | TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 ); 44 | TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f ); 45 | 46 | TEST_PASSFAIL 47 | 48 | RVTEST_CODE_END 49 | 50 | .data 51 | RVTEST_DATA_BEGIN 52 | 53 | TEST_DATA 54 | 55 | RVTEST_DATA_END 56 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sb.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sb.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sb instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_ST_OP( 2, lb, sb, 0xffffffffffffffaa, 0, tdat ); 21 | TEST_ST_OP( 3, lb, sb, 0x0000000000000000, 1, tdat ); 22 | TEST_ST_OP( 4, lh, sb, 0xffffffffffffefa0, 2, tdat ); 23 | TEST_ST_OP( 5, lb, sb, 0x000000000000000a, 3, tdat ); 24 | 25 | # Test with negative offset 26 | 27 | TEST_ST_OP( 6, lb, sb, 0xffffffffffffffaa, -3, tdat8 ); 28 | TEST_ST_OP( 7, lb, sb, 0x0000000000000000, -2, tdat8 ); 29 | TEST_ST_OP( 8, lb, sb, 0xffffffffffffffa0, -1, tdat8 ); 30 | TEST_ST_OP( 9, lb, sb, 0x000000000000000a, 0, tdat8 ); 31 | 32 | # Test with a negative base 33 | 34 | TEST_CASE( 10, x5, 0x78, \ 35 | la x1, tdat9; \ 36 | li x2, 0x12345678; \ 37 | addi x4, x1, -32; \ 38 | sb x2, 32(x4); \ 39 | lb x5, 0(x1); \ 40 | ) 41 | 42 | # Test with unaligned base 43 | 44 | TEST_CASE( 11, x5, 0xffffffffffffff98, \ 45 | la x1, tdat9; \ 46 | li x2, 0x00003098; \ 47 | addi x1, x1, -6; \ 48 | sb x2, 7(x1); \ 49 | la x4, tdat10; \ 50 | lb x5, 0(x4); \ 51 | ) 52 | 53 | #------------------------------------------------------------- 54 | # Bypassing tests 55 | #------------------------------------------------------------- 56 | 57 | TEST_ST_SRC12_BYPASS( 12, 0, 0, lb, sb, 0xffffffffffffffdd, 0, tdat ); 58 | TEST_ST_SRC12_BYPASS( 13, 0, 1, lb, sb, 0xffffffffffffffcd, 1, tdat ); 59 | TEST_ST_SRC12_BYPASS( 14, 0, 2, lb, sb, 0xffffffffffffffcc, 2, tdat ); 60 | TEST_ST_SRC12_BYPASS( 15, 1, 0, lb, sb, 0xffffffffffffffbc, 3, tdat ); 61 | TEST_ST_SRC12_BYPASS( 16, 1, 1, lb, sb, 0xffffffffffffffbb, 4, tdat ); 62 | TEST_ST_SRC12_BYPASS( 17, 2, 0, lb, sb, 0xffffffffffffffab, 5, tdat ); 63 | 64 | TEST_ST_SRC21_BYPASS( 18, 0, 0, lb, sb, 0x33, 0, tdat ); 65 | TEST_ST_SRC21_BYPASS( 19, 0, 1, lb, sb, 0x23, 1, tdat ); 66 | TEST_ST_SRC21_BYPASS( 20, 0, 2, lb, sb, 0x22, 2, tdat ); 67 | TEST_ST_SRC21_BYPASS( 21, 1, 0, lb, sb, 0x12, 3, tdat ); 68 | TEST_ST_SRC21_BYPASS( 22, 1, 1, lb, sb, 0x11, 4, tdat ); 69 | TEST_ST_SRC21_BYPASS( 23, 2, 0, lb, sb, 0x01, 5, tdat ); 70 | 71 | li a0, 0xef 72 | la a1, tdat 73 | sb a0, 3(a1) 74 | 75 | TEST_PASSFAIL 76 | 77 | RVTEST_CODE_END 78 | 79 | .data 80 | RVTEST_DATA_BEGIN 81 | 82 | TEST_DATA 83 | 84 | tdat: 85 | tdat1: .byte 0xef 86 | tdat2: .byte 0xef 87 | tdat3: .byte 0xef 88 | tdat4: .byte 0xef 89 | tdat5: .byte 0xef 90 | tdat6: .byte 0xef 91 | tdat7: .byte 0xef 92 | tdat8: .byte 0xef 93 | tdat9: .byte 0xef 94 | tdat10: .byte 0xef 95 | 96 | RVTEST_DATA_END 97 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sh.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sh.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sh instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_ST_OP( 2, lh, sh, 0x00000000000000aa, 0, tdat ); 21 | TEST_ST_OP( 3, lh, sh, 0xffffffffffffaa00, 2, tdat ); 22 | TEST_ST_OP( 4, lw, sh, 0xffffffffbeef0aa0, 4, tdat ); 23 | TEST_ST_OP( 5, lh, sh, 0xffffffffffffa00a, 6, tdat ); 24 | 25 | # Test with negative offset 26 | 27 | TEST_ST_OP( 6, lh, sh, 0x00000000000000aa, -6, tdat8 ); 28 | TEST_ST_OP( 7, lh, sh, 0xffffffffffffaa00, -4, tdat8 ); 29 | TEST_ST_OP( 8, lh, sh, 0x0000000000000aa0, -2, tdat8 ); 30 | TEST_ST_OP( 9, lh, sh, 0xffffffffffffa00a, 0, tdat8 ); 31 | 32 | # Test with a negative base 33 | 34 | TEST_CASE( 10, x5, 0x5678, \ 35 | la x1, tdat9; \ 36 | li x2, 0x12345678; \ 37 | addi x4, x1, -32; \ 38 | sh x2, 32(x4); \ 39 | lh x5, 0(x1); \ 40 | ) 41 | 42 | # Test with unaligned base 43 | 44 | TEST_CASE( 11, x5, 0x3098, \ 45 | la x1, tdat9; \ 46 | li x2, 0x00003098; \ 47 | addi x1, x1, -5; \ 48 | sh x2, 7(x1); \ 49 | la x4, tdat10; \ 50 | lh x5, 0(x4); \ 51 | ) 52 | 53 | #------------------------------------------------------------- 54 | # Bypassing tests 55 | #------------------------------------------------------------- 56 | 57 | TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffffffffffccdd, 0, tdat ); 58 | TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffffffffffbccd, 2, tdat ); 59 | TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffffffffffbbcc, 4, tdat ); 60 | TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffffffffffabbc, 6, tdat ); 61 | TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffffffffffaabb, 8, tdat ); 62 | TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffffffffffdaab, 10, tdat ); 63 | 64 | TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0, tdat ); 65 | TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2, tdat ); 66 | TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4, tdat ); 67 | TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat ); 68 | TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat ); 69 | TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat ); 70 | 71 | li a0, 0xbeef 72 | la a1, tdat 73 | sh a0, 6(a1) 74 | 75 | TEST_PASSFAIL 76 | 77 | RVTEST_CODE_END 78 | 79 | .data 80 | RVTEST_DATA_BEGIN 81 | 82 | TEST_DATA 83 | 84 | tdat: 85 | tdat1: .half 0xbeef 86 | tdat2: .half 0xbeef 87 | tdat3: .half 0xbeef 88 | tdat4: .half 0xbeef 89 | tdat5: .half 0xbeef 90 | tdat6: .half 0xbeef 91 | tdat7: .half 0xbeef 92 | tdat8: .half 0xbeef 93 | tdat9: .half 0xbeef 94 | tdat10: .half 0xbeef 95 | 96 | RVTEST_DATA_END 97 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/simple.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # simple.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This is the most basic self checking test. If your simulator does not 8 | # pass thiss then there is little chance that it will pass any of the 9 | # more complicated self checking tests. 10 | # 11 | 12 | #include "./include/riscv_test.h" 13 | #include "./include/test_macros.h" 14 | 15 | 16 | RVTEST_CODE_BEGIN 17 | 18 | RVTEST_PASS 19 | 20 | RVTEST_CODE_END 21 | 22 | .data 23 | RVTEST_DATA_BEGIN 24 | 25 | TEST_DATA 26 | 27 | RVTEST_DATA_END 28 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sll.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sll.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sll instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, sll, 0x0000000000000001, 0x0000000000000001, 0 ); 21 | TEST_RR_OP( 3, sll, 0x0000000000000002, 0x0000000000000001, 1 ); 22 | TEST_RR_OP( 4, sll, 0x0000000000000080, 0x0000000000000001, 7 ); 23 | TEST_RR_OP( 5, sll, 0x0000000000004000, 0x0000000000000001, 14 ); 24 | TEST_RR_OP( 6, sll, 0x0000000080000000, 0x0000000000000001, 31 ); 25 | 26 | TEST_RR_OP( 7, sll, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); 27 | TEST_RR_OP( 8, sll, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); 28 | TEST_RR_OP( 9, sll, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); 29 | TEST_RR_OP( 10, sll, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); 30 | TEST_RR_OP( 11, sll, 0xffffffff80000000, 0xffffffffffffffff, 31 ); 31 | 32 | TEST_RR_OP( 12, sll, 0x0000000021212121, 0x0000000021212121, 0 ); 33 | TEST_RR_OP( 13, sll, 0x0000000042424242, 0x0000000021212121, 1 ); 34 | TEST_RR_OP( 14, sll, 0x0000001090909080, 0x0000000021212121, 7 ); 35 | TEST_RR_OP( 15, sll, 0x0000084848484000, 0x0000000021212121, 14 ); 36 | TEST_RR_OP( 16, sll, 0x1090909080000000, 0x0000000021212121, 31 ); 37 | 38 | # Verify that shifts only use bottom six bits 39 | 40 | TEST_RR_OP( 17, sll, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); 41 | TEST_RR_OP( 18, sll, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 ); 42 | TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 ); 43 | TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce ); 44 | 45 | #if __riscv_xlen == 64 46 | TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff ); 47 | TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 ); 48 | TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 ); 49 | TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 ); 50 | #endif 51 | 52 | #------------------------------------------------------------- 53 | # Source/Destination tests 54 | #------------------------------------------------------------- 55 | 56 | TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7 ); 57 | TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 ); 58 | TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 ); 59 | 60 | #------------------------------------------------------------- 61 | # Bypassing tests 62 | #------------------------------------------------------------- 63 | 64 | TEST_RR_DEST_BYPASS( 25, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); 65 | TEST_RR_DEST_BYPASS( 26, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); 66 | TEST_RR_DEST_BYPASS( 27, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); 67 | 68 | TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); 69 | TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); 70 | TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); 71 | TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); 72 | TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); 73 | TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 ); 74 | 75 | TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); 76 | TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); 77 | TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); 78 | TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); 79 | TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); 80 | TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 ); 81 | 82 | TEST_RR_ZEROSRC1( 40, sll, 0, 15 ); 83 | TEST_RR_ZEROSRC2( 41, sll, 32, 32 ); 84 | TEST_RR_ZEROSRC12( 42, sll, 0 ); 85 | TEST_RR_ZERODEST( 43, sll, 1024, 2048 ); 86 | 87 | TEST_PASSFAIL 88 | 89 | RVTEST_CODE_END 90 | 91 | .data 92 | RVTEST_DATA_BEGIN 93 | 94 | TEST_DATA 95 | 96 | RVTEST_DATA_END 97 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/slli.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # slli.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test slli instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, slli, 0x0000000000000001, 0x0000000000000001, 0 ); 21 | TEST_IMM_OP( 3, slli, 0x0000000000000002, 0x0000000000000001, 1 ); 22 | TEST_IMM_OP( 4, slli, 0x0000000000000080, 0x0000000000000001, 7 ); 23 | TEST_IMM_OP( 5, slli, 0x0000000000004000, 0x0000000000000001, 14 ); 24 | TEST_IMM_OP( 6, slli, 0x0000000080000000, 0x0000000000000001, 31 ); 25 | 26 | TEST_IMM_OP( 7, slli, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); 27 | TEST_IMM_OP( 8, slli, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); 28 | TEST_IMM_OP( 9, slli, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); 29 | TEST_IMM_OP( 10, slli, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); 30 | TEST_IMM_OP( 11, slli, 0xffffffff80000000, 0xffffffffffffffff, 31 ); 31 | 32 | TEST_IMM_OP( 12, slli, 0x0000000021212121, 0x0000000021212121, 0 ); 33 | TEST_IMM_OP( 13, slli, 0x0000000042424242, 0x0000000021212121, 1 ); 34 | TEST_IMM_OP( 14, slli, 0x0000001090909080, 0x0000000021212121, 7 ); 35 | TEST_IMM_OP( 15, slli, 0x0000084848484000, 0x0000000021212121, 14 ); 36 | TEST_IMM_OP( 16, slli, 0x1090909080000000, 0x0000000021212121, 31 ); 37 | 38 | #if __riscv_xlen == 64 39 | TEST_IMM_OP( 50, slli, 0x8000000000000000, 0x0000000000000001, 63 ); 40 | TEST_IMM_OP( 51, slli, 0xffffff8000000000, 0xffffffffffffffff, 39 ); 41 | TEST_IMM_OP( 52, slli, 0x0909080000000000, 0x0000000021212121, 43 ); 42 | #endif 43 | 44 | #------------------------------------------------------------- 45 | # Source/Destination tests 46 | #------------------------------------------------------------- 47 | 48 | TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 ); 49 | 50 | #------------------------------------------------------------- 51 | # Bypassing tests 52 | #------------------------------------------------------------- 53 | 54 | TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 ); 55 | TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 ); 56 | TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 ); 57 | 58 | TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 ); 59 | TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 ); 60 | TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 ); 61 | 62 | TEST_IMM_ZEROSRC1( 24, slli, 0, 31 ); 63 | TEST_IMM_ZERODEST( 25, slli, 33, 20 ); 64 | 65 | TEST_PASSFAIL 66 | 67 | RVTEST_CODE_END 68 | 69 | .data 70 | RVTEST_DATA_BEGIN 71 | 72 | TEST_DATA 73 | 74 | RVTEST_DATA_END 75 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/slt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # slt.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test slt instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, slt, 0, 0x0000000000000000, 0x0000000000000000 ); 21 | TEST_RR_OP( 3, slt, 0, 0x0000000000000001, 0x0000000000000001 ); 22 | TEST_RR_OP( 4, slt, 1, 0x0000000000000003, 0x0000000000000007 ); 23 | TEST_RR_OP( 5, slt, 0, 0x0000000000000007, 0x0000000000000003 ); 24 | 25 | TEST_RR_OP( 6, slt, 0, 0x0000000000000000, 0xffffffffffff8000 ); 26 | TEST_RR_OP( 7, slt, 1, 0xffffffff80000000, 0x0000000000000000 ); 27 | TEST_RR_OP( 8, slt, 1, 0xffffffff80000000, 0xffffffffffff8000 ); 28 | 29 | TEST_RR_OP( 9, slt, 1, 0x0000000000000000, 0x0000000000007fff ); 30 | TEST_RR_OP( 10, slt, 0, 0x000000007fffffff, 0x0000000000000000 ); 31 | TEST_RR_OP( 11, slt, 0, 0x000000007fffffff, 0x0000000000007fff ); 32 | 33 | TEST_RR_OP( 12, slt, 1, 0xffffffff80000000, 0x0000000000007fff ); 34 | TEST_RR_OP( 13, slt, 0, 0x000000007fffffff, 0xffffffffffff8000 ); 35 | 36 | TEST_RR_OP( 14, slt, 0, 0x0000000000000000, 0xffffffffffffffff ); 37 | TEST_RR_OP( 15, slt, 1, 0xffffffffffffffff, 0x0000000000000001 ); 38 | TEST_RR_OP( 16, slt, 0, 0xffffffffffffffff, 0xffffffffffffffff ); 39 | 40 | #------------------------------------------------------------- 41 | # Source/Destination tests 42 | #------------------------------------------------------------- 43 | 44 | TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 ); 45 | TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 ); 46 | TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 ); 47 | 48 | #------------------------------------------------------------- 49 | # Bypassing tests 50 | #------------------------------------------------------------- 51 | 52 | TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 ); 53 | TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 ); 54 | TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 ); 55 | 56 | TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 ); 57 | TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 ); 58 | TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 ); 59 | TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 ); 60 | TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 ); 61 | TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1, 9, 13 ); 62 | 63 | TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 ); 64 | TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1, 8, 13 ); 65 | TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 ); 66 | TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1, 7, 13 ); 67 | TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 ); 68 | TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1, 6, 13 ); 69 | 70 | TEST_RR_ZEROSRC1( 35, slt, 0, -1 ); 71 | TEST_RR_ZEROSRC2( 36, slt, 1, -1 ); 72 | TEST_RR_ZEROSRC12( 37, slt, 0 ); 73 | TEST_RR_ZERODEST( 38, slt, 16, 30 ); 74 | 75 | TEST_PASSFAIL 76 | 77 | RVTEST_CODE_END 78 | 79 | .data 80 | RVTEST_DATA_BEGIN 81 | 82 | TEST_DATA 83 | 84 | RVTEST_DATA_END 85 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/slti.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # slti.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test slti instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, slti, 0, 0x0000000000000000, 0x000 ); 21 | TEST_IMM_OP( 3, slti, 0, 0x0000000000000001, 0x001 ); 22 | TEST_IMM_OP( 4, slti, 1, 0x0000000000000003, 0x007 ); 23 | TEST_IMM_OP( 5, slti, 0, 0x0000000000000007, 0x003 ); 24 | 25 | TEST_IMM_OP( 6, slti, 0, 0x0000000000000000, 0x800 ); 26 | TEST_IMM_OP( 7, slti, 1, 0xffffffff80000000, 0x000 ); 27 | TEST_IMM_OP( 8, slti, 1, 0xffffffff80000000, 0x800 ); 28 | 29 | TEST_IMM_OP( 9, slti, 1, 0x0000000000000000, 0x7ff ); 30 | TEST_IMM_OP( 10, slti, 0, 0x000000007fffffff, 0x000 ); 31 | TEST_IMM_OP( 11, slti, 0, 0x000000007fffffff, 0x7ff ); 32 | 33 | TEST_IMM_OP( 12, slti, 1, 0xffffffff80000000, 0x7ff ); 34 | TEST_IMM_OP( 13, slti, 0, 0x000000007fffffff, 0x800 ); 35 | 36 | TEST_IMM_OP( 14, slti, 0, 0x0000000000000000, 0xfff ); 37 | TEST_IMM_OP( 15, slti, 1, 0xffffffffffffffff, 0x001 ); 38 | TEST_IMM_OP( 16, slti, 0, 0xffffffffffffffff, 0xfff ); 39 | 40 | #------------------------------------------------------------- 41 | # Source/Destination tests 42 | #------------------------------------------------------------- 43 | 44 | TEST_IMM_SRC1_EQ_DEST( 17, slti, 1, 11, 13 ); 45 | 46 | #------------------------------------------------------------- 47 | # Bypassing tests 48 | #------------------------------------------------------------- 49 | 50 | TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 ); 51 | TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 ); 52 | TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16, 9 ); 53 | 54 | TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 ); 55 | TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17, 8 ); 56 | TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 ); 57 | 58 | TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff ); 59 | TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff ); 60 | 61 | TEST_PASSFAIL 62 | 63 | RVTEST_CODE_END 64 | 65 | .data 66 | RVTEST_DATA_BEGIN 67 | 68 | TEST_DATA 69 | 70 | RVTEST_DATA_END 71 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sltiu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sltiu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sltiu instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, sltiu, 0, 0x0000000000000000, 0x000 ); 21 | TEST_IMM_OP( 3, sltiu, 0, 0x0000000000000001, 0x001 ); 22 | TEST_IMM_OP( 4, sltiu, 1, 0x0000000000000003, 0x007 ); 23 | TEST_IMM_OP( 5, sltiu, 0, 0x0000000000000007, 0x003 ); 24 | 25 | TEST_IMM_OP( 6, sltiu, 1, 0x0000000000000000, 0x800 ); 26 | TEST_IMM_OP( 7, sltiu, 0, 0xffffffff80000000, 0x000 ); 27 | TEST_IMM_OP( 8, sltiu, 1, 0xffffffff80000000, 0x800 ); 28 | 29 | TEST_IMM_OP( 9, sltiu, 1, 0x0000000000000000, 0x7ff ); 30 | TEST_IMM_OP( 10, sltiu, 0, 0x000000007fffffff, 0x000 ); 31 | TEST_IMM_OP( 11, sltiu, 0, 0x000000007fffffff, 0x7ff ); 32 | 33 | TEST_IMM_OP( 12, sltiu, 0, 0xffffffff80000000, 0x7ff ); 34 | TEST_IMM_OP( 13, sltiu, 1, 0x000000007fffffff, 0x800 ); 35 | 36 | TEST_IMM_OP( 14, sltiu, 1, 0x0000000000000000, 0xfff ); 37 | TEST_IMM_OP( 15, sltiu, 0, 0xffffffffffffffff, 0x001 ); 38 | TEST_IMM_OP( 16, sltiu, 0, 0xffffffffffffffff, 0xfff ); 39 | 40 | #------------------------------------------------------------- 41 | # Source/Destination tests 42 | #------------------------------------------------------------- 43 | 44 | TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 ); 45 | 46 | #------------------------------------------------------------- 47 | # Bypassing tests 48 | #------------------------------------------------------------- 49 | 50 | TEST_IMM_DEST_BYPASS( 18, 0, sltiu, 0, 15, 10 ); 51 | TEST_IMM_DEST_BYPASS( 19, 1, sltiu, 1, 10, 16 ); 52 | TEST_IMM_DEST_BYPASS( 20, 2, sltiu, 0, 16, 9 ); 53 | 54 | TEST_IMM_SRC1_BYPASS( 21, 0, sltiu, 1, 11, 15 ); 55 | TEST_IMM_SRC1_BYPASS( 22, 1, sltiu, 0, 17, 8 ); 56 | TEST_IMM_SRC1_BYPASS( 23, 2, sltiu, 1, 12, 14 ); 57 | 58 | TEST_IMM_ZEROSRC1( 24, sltiu, 1, 0xfff ); 59 | TEST_IMM_ZERODEST( 25, sltiu, 0x00ff00ff, 0xfff ); 60 | 61 | TEST_PASSFAIL 62 | 63 | RVTEST_CODE_END 64 | 65 | .data 66 | RVTEST_DATA_BEGIN 67 | 68 | TEST_DATA 69 | 70 | RVTEST_DATA_END 71 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sltu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sltu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sltu instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, sltu, 0, 0x00000000, 0x00000000 ); 21 | TEST_RR_OP( 3, sltu, 0, 0x00000001, 0x00000001 ); 22 | TEST_RR_OP( 4, sltu, 1, 0x00000003, 0x00000007 ); 23 | TEST_RR_OP( 5, sltu, 0, 0x00000007, 0x00000003 ); 24 | 25 | TEST_RR_OP( 6, sltu, 1, 0x00000000, 0xffff8000 ); 26 | TEST_RR_OP( 7, sltu, 0, 0x80000000, 0x00000000 ); 27 | TEST_RR_OP( 8, sltu, 1, 0x80000000, 0xffff8000 ); 28 | 29 | TEST_RR_OP( 9, sltu, 1, 0x00000000, 0x00007fff ); 30 | TEST_RR_OP( 10, sltu, 0, 0x7fffffff, 0x00000000 ); 31 | TEST_RR_OP( 11, sltu, 0, 0x7fffffff, 0x00007fff ); 32 | 33 | TEST_RR_OP( 12, sltu, 0, 0x80000000, 0x00007fff ); 34 | TEST_RR_OP( 13, sltu, 1, 0x7fffffff, 0xffff8000 ); 35 | 36 | TEST_RR_OP( 14, sltu, 1, 0x00000000, 0xffffffff ); 37 | TEST_RR_OP( 15, sltu, 0, 0xffffffff, 0x00000001 ); 38 | TEST_RR_OP( 16, sltu, 0, 0xffffffff, 0xffffffff ); 39 | 40 | #------------------------------------------------------------- 41 | # Source/Destination tests 42 | #------------------------------------------------------------- 43 | 44 | TEST_RR_SRC1_EQ_DEST( 17, sltu, 0, 14, 13 ); 45 | TEST_RR_SRC2_EQ_DEST( 18, sltu, 1, 11, 13 ); 46 | TEST_RR_SRC12_EQ_DEST( 19, sltu, 0, 13 ); 47 | 48 | #------------------------------------------------------------- 49 | # Bypassing tests 50 | #------------------------------------------------------------- 51 | 52 | TEST_RR_DEST_BYPASS( 20, 0, sltu, 1, 11, 13 ); 53 | TEST_RR_DEST_BYPASS( 21, 1, sltu, 0, 14, 13 ); 54 | TEST_RR_DEST_BYPASS( 22, 2, sltu, 1, 12, 13 ); 55 | 56 | TEST_RR_SRC12_BYPASS( 23, 0, 0, sltu, 0, 14, 13 ); 57 | TEST_RR_SRC12_BYPASS( 24, 0, 1, sltu, 1, 11, 13 ); 58 | TEST_RR_SRC12_BYPASS( 25, 0, 2, sltu, 0, 15, 13 ); 59 | TEST_RR_SRC12_BYPASS( 26, 1, 0, sltu, 1, 10, 13 ); 60 | TEST_RR_SRC12_BYPASS( 27, 1, 1, sltu, 0, 16, 13 ); 61 | TEST_RR_SRC12_BYPASS( 28, 2, 0, sltu, 1, 9, 13 ); 62 | 63 | TEST_RR_SRC21_BYPASS( 29, 0, 0, sltu, 0, 17, 13 ); 64 | TEST_RR_SRC21_BYPASS( 30, 0, 1, sltu, 1, 8, 13 ); 65 | TEST_RR_SRC21_BYPASS( 31, 0, 2, sltu, 0, 18, 13 ); 66 | TEST_RR_SRC21_BYPASS( 32, 1, 0, sltu, 1, 7, 13 ); 67 | TEST_RR_SRC21_BYPASS( 33, 1, 1, sltu, 0, 19, 13 ); 68 | TEST_RR_SRC21_BYPASS( 34, 2, 0, sltu, 1, 6, 13 ); 69 | 70 | TEST_RR_ZEROSRC1( 35, sltu, 1, -1 ); 71 | TEST_RR_ZEROSRC2( 36, sltu, 0, -1 ); 72 | TEST_RR_ZEROSRC12( 37, sltu, 0 ); 73 | TEST_RR_ZERODEST( 38, sltu, 16, 30 ); 74 | 75 | TEST_PASSFAIL 76 | 77 | RVTEST_CODE_END 78 | 79 | .data 80 | RVTEST_DATA_BEGIN 81 | 82 | TEST_DATA 83 | 84 | RVTEST_DATA_END 85 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sra.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sra.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sra instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, sra, 0xffffffff80000000, 0xffffffff80000000, 0 ); 21 | TEST_RR_OP( 3, sra, 0xffffffffc0000000, 0xffffffff80000000, 1 ); 22 | TEST_RR_OP( 4, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); 23 | TEST_RR_OP( 5, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 24 | TEST_RR_OP( 6, sra, 0xffffffffffffffff, 0xffffffff80000001, 31 ); 25 | 26 | TEST_RR_OP( 7, sra, 0x000000007fffffff, 0x000000007fffffff, 0 ); 27 | TEST_RR_OP( 8, sra, 0x000000003fffffff, 0x000000007fffffff, 1 ); 28 | TEST_RR_OP( 9, sra, 0x0000000000ffffff, 0x000000007fffffff, 7 ); 29 | TEST_RR_OP( 10, sra, 0x000000000001ffff, 0x000000007fffffff, 14 ); 30 | TEST_RR_OP( 11, sra, 0x0000000000000000, 0x000000007fffffff, 31 ); 31 | 32 | TEST_RR_OP( 12, sra, 0xffffffff81818181, 0xffffffff81818181, 0 ); 33 | TEST_RR_OP( 13, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 ); 34 | TEST_RR_OP( 14, sra, 0xffffffffff030303, 0xffffffff81818181, 7 ); 35 | TEST_RR_OP( 15, sra, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); 36 | TEST_RR_OP( 16, sra, 0xffffffffffffffff, 0xffffffff81818181, 31 ); 37 | 38 | # Verify that shifts only use bottom five bits 39 | 40 | TEST_RR_OP( 17, sra, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffc0 ); 41 | TEST_RR_OP( 18, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffc1 ); 42 | TEST_RR_OP( 19, sra, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffc7 ); 43 | TEST_RR_OP( 20, sra, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffce ); 44 | TEST_RR_OP( 21, sra, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff ); 45 | 46 | #------------------------------------------------------------- 47 | # Source/Destination tests 48 | #------------------------------------------------------------- 49 | 50 | TEST_RR_SRC1_EQ_DEST( 22, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); 51 | TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 52 | TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 ); 53 | 54 | #------------------------------------------------------------- 55 | # Bypassing tests 56 | #------------------------------------------------------------- 57 | 58 | TEST_RR_DEST_BYPASS( 25, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); 59 | TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 60 | TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); 61 | 62 | TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); 63 | TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 64 | TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); 65 | TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); 66 | TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 67 | TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); 68 | 69 | TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); 70 | TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 71 | TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); 72 | TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); 73 | TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 74 | TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); 75 | 76 | TEST_RR_ZEROSRC1( 40, sra, 0, 15 ); 77 | TEST_RR_ZEROSRC2( 41, sra, 32, 32 ); 78 | TEST_RR_ZEROSRC12( 42, sra, 0 ); 79 | TEST_RR_ZERODEST( 43, sra, 1024, 2048 ); 80 | 81 | TEST_PASSFAIL 82 | 83 | RVTEST_CODE_END 84 | 85 | .data 86 | RVTEST_DATA_BEGIN 87 | 88 | TEST_DATA 89 | 90 | RVTEST_DATA_END 91 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/srai.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # srai.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test srai instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, srai, 0xffffff8000000000, 0xffffff8000000000, 0 ); 21 | TEST_IMM_OP( 3, srai, 0xffffffffc0000000, 0xffffffff80000000, 1 ); 22 | TEST_IMM_OP( 4, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); 23 | TEST_IMM_OP( 5, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 24 | TEST_IMM_OP( 6, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); 25 | 26 | TEST_IMM_OP( 7, srai, 0x000000007fffffff, 0x000000007fffffff, 0 ); 27 | TEST_IMM_OP( 8, srai, 0x000000003fffffff, 0x000000007fffffff, 1 ); 28 | TEST_IMM_OP( 9, srai, 0x0000000000ffffff, 0x000000007fffffff, 7 ); 29 | TEST_IMM_OP( 10, srai, 0x000000000001ffff, 0x000000007fffffff, 14 ); 30 | TEST_IMM_OP( 11, srai, 0x0000000000000000, 0x000000007fffffff, 31 ); 31 | 32 | TEST_IMM_OP( 12, srai, 0xffffffff81818181, 0xffffffff81818181, 0 ); 33 | TEST_IMM_OP( 13, srai, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 ); 34 | TEST_IMM_OP( 14, srai, 0xffffffffff030303, 0xffffffff81818181, 7 ); 35 | TEST_IMM_OP( 15, srai, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); 36 | TEST_IMM_OP( 16, srai, 0xffffffffffffffff, 0xffffffff81818181, 31 ); 37 | 38 | #------------------------------------------------------------- 39 | # Source/Destination tests 40 | #------------------------------------------------------------- 41 | 42 | TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); 43 | 44 | #------------------------------------------------------------- 45 | # Bypassing tests 46 | #------------------------------------------------------------- 47 | 48 | TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); 49 | TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 50 | TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); 51 | 52 | TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); 53 | TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 54 | TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); 55 | 56 | TEST_IMM_ZEROSRC1( 24, srai, 0, 4 ); 57 | TEST_IMM_ZERODEST( 25, srai, 33, 10 ); 58 | 59 | TEST_PASSFAIL 60 | 61 | RVTEST_CODE_END 62 | 63 | .data 64 | RVTEST_DATA_BEGIN 65 | 66 | TEST_DATA 67 | 68 | RVTEST_DATA_END 69 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/srl.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # srl.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test srl instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | #define TEST_SRL(n, v, a) \ 21 | TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) 22 | 23 | TEST_SRL( 2, 0xffffffff80000000, 0 ); 24 | TEST_SRL( 3, 0xffffffff80000000, 1 ); 25 | TEST_SRL( 4, 0xffffffff80000000, 7 ); 26 | TEST_SRL( 5, 0xffffffff80000000, 14 ); 27 | TEST_SRL( 6, 0xffffffff80000001, 31 ); 28 | 29 | TEST_SRL( 7, 0xffffffffffffffff, 0 ); 30 | TEST_SRL( 8, 0xffffffffffffffff, 1 ); 31 | TEST_SRL( 9, 0xffffffffffffffff, 7 ); 32 | TEST_SRL( 10, 0xffffffffffffffff, 14 ); 33 | TEST_SRL( 11, 0xffffffffffffffff, 31 ); 34 | 35 | TEST_SRL( 12, 0x0000000021212121, 0 ); 36 | TEST_SRL( 13, 0x0000000021212121, 1 ); 37 | TEST_SRL( 14, 0x0000000021212121, 7 ); 38 | TEST_SRL( 15, 0x0000000021212121, 14 ); 39 | TEST_SRL( 16, 0x0000000021212121, 31 ); 40 | 41 | # Verify that shifts only use bottom five bits 42 | 43 | TEST_RR_OP( 17, srl, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); 44 | TEST_RR_OP( 18, srl, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffc1 ); 45 | TEST_RR_OP( 19, srl, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffc7 ); 46 | TEST_RR_OP( 20, srl, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffce ); 47 | TEST_RR_OP( 21, srl, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff ); 48 | 49 | #------------------------------------------------------------- 50 | # Source/Destination tests 51 | #------------------------------------------------------------- 52 | 53 | TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01000000, 0x80000000, 7 ); 54 | TEST_RR_SRC2_EQ_DEST( 23, srl, 0x00020000, 0x80000000, 14 ); 55 | TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 ); 56 | 57 | #------------------------------------------------------------- 58 | # Bypassing tests 59 | #------------------------------------------------------------- 60 | 61 | TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01000000, 0x80000000, 7 ); 62 | TEST_RR_DEST_BYPASS( 26, 1, srl, 0x00020000, 0x80000000, 14 ); 63 | TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001, 0x80000000, 31 ); 64 | 65 | TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01000000, 0x80000000, 7 ); 66 | TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x00020000, 0x80000000, 14 ); 67 | TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001, 0x80000000, 31 ); 68 | TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01000000, 0x80000000, 7 ); 69 | TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x00020000, 0x80000000, 14 ); 70 | TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001, 0x80000000, 31 ); 71 | 72 | TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01000000, 0x80000000, 7 ); 73 | TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x00020000, 0x80000000, 14 ); 74 | TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001, 0x80000000, 31 ); 75 | TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01000000, 0x80000000, 7 ); 76 | TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x00020000, 0x80000000, 14 ); 77 | TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001, 0x80000000, 31 ); 78 | 79 | TEST_RR_ZEROSRC1( 40, srl, 0, 15 ); 80 | TEST_RR_ZEROSRC2( 41, srl, 32, 32 ); 81 | TEST_RR_ZEROSRC12( 42, srl, 0 ); 82 | TEST_RR_ZERODEST( 43, srl, 1024, 2048 ); 83 | 84 | TEST_PASSFAIL 85 | 86 | RVTEST_CODE_END 87 | 88 | .data 89 | RVTEST_DATA_BEGIN 90 | 91 | TEST_DATA 92 | 93 | RVTEST_DATA_END 94 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/srli.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # srli.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test srli instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | #define TEST_SRL(n, v, a) \ 21 | TEST_IMM_OP(n, srli, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) 22 | 23 | TEST_SRL( 2, 0xffffffff80000000, 0 ); 24 | TEST_SRL( 3, 0xffffffff80000000, 1 ); 25 | TEST_SRL( 4, 0xffffffff80000000, 7 ); 26 | TEST_SRL( 5, 0xffffffff80000000, 14 ); 27 | TEST_SRL( 6, 0xffffffff80000001, 31 ); 28 | 29 | TEST_SRL( 7, 0xffffffffffffffff, 0 ); 30 | TEST_SRL( 8, 0xffffffffffffffff, 1 ); 31 | TEST_SRL( 9, 0xffffffffffffffff, 7 ); 32 | TEST_SRL( 10, 0xffffffffffffffff, 14 ); 33 | TEST_SRL( 11, 0xffffffffffffffff, 31 ); 34 | 35 | TEST_SRL( 12, 0x0000000021212121, 0 ); 36 | TEST_SRL( 13, 0x0000000021212121, 1 ); 37 | TEST_SRL( 14, 0x0000000021212121, 7 ); 38 | TEST_SRL( 15, 0x0000000021212121, 14 ); 39 | TEST_SRL( 16, 0x0000000021212121, 31 ); 40 | 41 | #------------------------------------------------------------- 42 | # Source/Destination tests 43 | #------------------------------------------------------------- 44 | 45 | TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01000000, 0x80000000, 7 ); 46 | 47 | #------------------------------------------------------------- 48 | # Bypassing tests 49 | #------------------------------------------------------------- 50 | 51 | TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01000000, 0x80000000, 7 ); 52 | TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x00020000, 0x80000000, 14 ); 53 | TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001, 0x80000001, 31 ); 54 | 55 | TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01000000, 0x80000000, 7 ); 56 | TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x00020000, 0x80000000, 14 ); 57 | TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001, 0x80000001, 31 ); 58 | 59 | TEST_IMM_ZEROSRC1( 24, srli, 0, 4 ); 60 | TEST_IMM_ZERODEST( 25, srli, 33, 10 ); 61 | 62 | TEST_PASSFAIL 63 | 64 | RVTEST_CODE_END 65 | 66 | .data 67 | RVTEST_DATA_BEGIN 68 | 69 | TEST_DATA 70 | 71 | RVTEST_DATA_END 72 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sub.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sub.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sub instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, sub, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); 21 | TEST_RR_OP( 3, sub, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 ); 22 | TEST_RR_OP( 4, sub, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 ); 23 | 24 | TEST_RR_OP( 5, sub, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 ); 25 | TEST_RR_OP( 6, sub, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 ); 26 | TEST_RR_OP( 7, sub, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 ); 27 | 28 | TEST_RR_OP( 8, sub, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff ); 29 | TEST_RR_OP( 9, sub, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); 30 | TEST_RR_OP( 10, sub, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff ); 31 | 32 | TEST_RR_OP( 11, sub, 0xffffffff7fff8001, 0xffffffff80000000, 0x0000000000007fff ); 33 | TEST_RR_OP( 12, sub, 0x0000000080007fff, 0x000000007fffffff, 0xffffffffffff8000 ); 34 | 35 | TEST_RR_OP( 13, sub, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff ); 36 | TEST_RR_OP( 14, sub, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 ); 37 | TEST_RR_OP( 15, sub, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff ); 38 | 39 | #------------------------------------------------------------- 40 | # Source/Destination tests 41 | #------------------------------------------------------------- 42 | 43 | TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 ); 44 | TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 ); 45 | TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 ); 46 | 47 | #------------------------------------------------------------- 48 | # Bypassing tests 49 | #------------------------------------------------------------- 50 | 51 | TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 ); 52 | TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 ); 53 | TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 ); 54 | 55 | TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 ); 56 | TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 ); 57 | TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 ); 58 | TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 ); 59 | TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 ); 60 | TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 ); 61 | 62 | TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 ); 63 | TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 ); 64 | TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 ); 65 | TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 ); 66 | TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 ); 67 | TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 ); 68 | 69 | TEST_RR_ZEROSRC1( 34, sub, 15, -15 ); 70 | TEST_RR_ZEROSRC2( 35, sub, 32, 32 ); 71 | TEST_RR_ZEROSRC12( 36, sub, 0 ); 72 | TEST_RR_ZERODEST( 37, sub, 16, 30 ); 73 | 74 | TEST_PASSFAIL 75 | 76 | RVTEST_CODE_END 77 | 78 | .data 79 | RVTEST_DATA_BEGIN 80 | 81 | TEST_DATA 82 | 83 | RVTEST_DATA_END 84 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sw.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sw instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_ST_OP( 2, lw, sw, 0x0000000000aa00aa, 0, tdat ); 21 | TEST_ST_OP( 3, lw, sw, 0xffffffffaa00aa00, 4, tdat ); 22 | TEST_ST_OP( 4, lw, sw, 0x000000000aa00aa0, 8, tdat ); 23 | TEST_ST_OP( 5, lw, sw, 0xffffffffa00aa00a, 12, tdat ); 24 | 25 | # Test with negative offset 26 | 27 | TEST_ST_OP( 6, lw, sw, 0x0000000000aa00aa, -12, tdat8 ); 28 | TEST_ST_OP( 7, lw, sw, 0xffffffffaa00aa00, -8, tdat8 ); 29 | TEST_ST_OP( 8, lw, sw, 0x000000000aa00aa0, -4, tdat8 ); 30 | TEST_ST_OP( 9, lw, sw, 0xffffffffa00aa00a, 0, tdat8 ); 31 | 32 | # Test with a negative base 33 | 34 | TEST_CASE( 10, x5, 0x12345678, \ 35 | la x1, tdat9; \ 36 | li x2, 0x12345678; \ 37 | addi x4, x1, -32; \ 38 | sw x2, 32(x4); \ 39 | lw x5, 0(x1); \ 40 | ) 41 | 42 | # Test with unaligned base 43 | 44 | TEST_CASE( 11, x5, 0x58213098, \ 45 | la x1, tdat9; \ 46 | li x2, 0x58213098; \ 47 | addi x1, x1, -3; \ 48 | sw x2, 7(x1); \ 49 | la x4, tdat10; \ 50 | lw x5, 0(x4); \ 51 | ) 52 | 53 | #------------------------------------------------------------- 54 | # Bypassing tests 55 | #------------------------------------------------------------- 56 | 57 | TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xffffffffaabbccdd, 0, tdat ); 58 | TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xffffffffdaabbccd, 4, tdat ); 59 | TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xffffffffddaabbcc, 8, tdat ); 60 | TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xffffffffcddaabbc, 12, tdat ); 61 | TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xffffffffccddaabb, 16, tdat ); 62 | TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xffffffffbccddaab, 20, tdat ); 63 | 64 | TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0, tdat ); 65 | TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4, tdat ); 66 | TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8, tdat ); 67 | TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat ); 68 | TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat ); 69 | TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat ); 70 | 71 | TEST_PASSFAIL 72 | 73 | RVTEST_CODE_END 74 | 75 | .data 76 | RVTEST_DATA_BEGIN 77 | 78 | TEST_DATA 79 | 80 | tdat: 81 | tdat1: .word 0xdeadbeef 82 | tdat2: .word 0xdeadbeef 83 | tdat3: .word 0xdeadbeef 84 | tdat4: .word 0xdeadbeef 85 | tdat5: .word 0xdeadbeef 86 | tdat6: .word 0xdeadbeef 87 | tdat7: .word 0xdeadbeef 88 | tdat8: .word 0xdeadbeef 89 | tdat9: .word 0xdeadbeef 90 | tdat10: .word 0xdeadbeef 91 | 92 | RVTEST_DATA_END 93 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/xor.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # xor.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test xor instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Logical tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 21 | TEST_RR_OP( 3, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); 22 | TEST_RR_OP( 4, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); 23 | TEST_RR_OP( 5, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 ); 24 | 25 | #------------------------------------------------------------- 26 | # Source/Destination tests 27 | #------------------------------------------------------------- 28 | 29 | TEST_RR_SRC1_EQ_DEST( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 30 | TEST_RR_SRC2_EQ_DEST( 7, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 31 | TEST_RR_SRC12_EQ_DEST( 8, xor, 0x00000000, 0xff00ff00 ); 32 | 33 | #------------------------------------------------------------- 34 | # Bypassing tests 35 | #------------------------------------------------------------- 36 | 37 | TEST_RR_DEST_BYPASS( 9, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 38 | TEST_RR_DEST_BYPASS( 10, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); 39 | TEST_RR_DEST_BYPASS( 11, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); 40 | 41 | TEST_RR_SRC12_BYPASS( 12, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 42 | TEST_RR_SRC12_BYPASS( 13, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); 43 | TEST_RR_SRC12_BYPASS( 14, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); 44 | TEST_RR_SRC12_BYPASS( 15, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 45 | TEST_RR_SRC12_BYPASS( 16, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); 46 | TEST_RR_SRC12_BYPASS( 17, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); 47 | 48 | TEST_RR_SRC21_BYPASS( 18, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 49 | TEST_RR_SRC21_BYPASS( 19, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); 50 | TEST_RR_SRC21_BYPASS( 20, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); 51 | TEST_RR_SRC21_BYPASS( 21, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 52 | TEST_RR_SRC21_BYPASS( 22, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); 53 | TEST_RR_SRC21_BYPASS( 23, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); 54 | 55 | TEST_RR_ZEROSRC1( 24, xor, 0xff00ff00, 0xff00ff00 ); 56 | TEST_RR_ZEROSRC2( 25, xor, 0x00ff00ff, 0x00ff00ff ); 57 | TEST_RR_ZEROSRC12( 26, xor, 0 ); 58 | TEST_RR_ZERODEST( 27, xor, 0x11111111, 0x22222222 ); 59 | 60 | TEST_PASSFAIL 61 | 62 | RVTEST_CODE_END 63 | 64 | .data 65 | RVTEST_DATA_BEGIN 66 | 67 | TEST_DATA 68 | 69 | RVTEST_DATA_END 70 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/xori.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # xori.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test xori instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Logical tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, xori, 0xffffffffff00f00f, 0x0000000000ff0f00, 0xf0f ); 21 | TEST_IMM_OP( 3, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); 22 | TEST_IMM_OP( 4, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f ); 23 | TEST_IMM_OP( 5, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); 24 | 25 | #------------------------------------------------------------- 26 | # Source/Destination tests 27 | #------------------------------------------------------------- 28 | 29 | TEST_IMM_SRC1_EQ_DEST( 6, xori, 0xffffffffff00f00f, 0xffffffffff00f700, 0x70f ); 30 | 31 | #------------------------------------------------------------- 32 | # Bypassing tests 33 | #------------------------------------------------------------- 34 | 35 | TEST_IMM_DEST_BYPASS( 7, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); 36 | TEST_IMM_DEST_BYPASS( 8, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f ); 37 | TEST_IMM_DEST_BYPASS( 9, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); 38 | 39 | TEST_IMM_SRC1_BYPASS( 10, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); 40 | TEST_IMM_SRC1_BYPASS( 11, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff0fff, 0x00f ); 41 | TEST_IMM_SRC1_BYPASS( 12, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); 42 | 43 | TEST_IMM_ZEROSRC1( 13, xori, 0x0f0, 0x0f0 ); 44 | TEST_IMM_ZERODEST( 14, xori, 0x00ff00ff, 0x70f ); 45 | 46 | TEST_PASSFAIL 47 | 48 | RVTEST_CODE_END 49 | 50 | .data 51 | RVTEST_DATA_BEGIN 52 | 53 | TEST_DATA 54 | 55 | RVTEST_DATA_END 56 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/Makefile: -------------------------------------------------------------------------------- 1 | #Copyright (c) 2019 HaojunXia 2 | 3 | #This script can change .S Files into .inst & .data files which can be loaded by our FPGA's Block memories. 4 | #Decided upon which level of files you want, you can choose one of these commands listed below 5 | #make/make all: 6 | <<<<<<< HEAD 7 | #change all .S files into .data & .inst files, meanwhile all intermediate files will be saved. 8 | ======= 9 | #change all .S files into .data & .inst files, meanwhile get assembly code 10 | >>>>>>> eb6a9bb3e09cf42ef8beb09a5c9ad229ca47bce1 11 | #make DataAndInst: 12 | #dump both Data and Instructions and save them to .data files 13 | #make InstOnly: 14 | #dump ONLY Instructions and save them to .inst files 15 | #make OMFile: 16 | #assembly the .S files into .o files, then link the .o files into .om files 17 | #make OFile: 18 | #assembly the .S files into .o files 19 | <<<<<<< HEAD 20 | ======= 21 | #make Objdump 22 | #get the disassembly code of riscv test 23 | >>>>>>> eb6a9bb3e09cf42ef8beb09a5c9ad229ca47bce1 24 | #Other options: 25 | #make clean: 26 | #clean all files generated by this makefile, but do not delete .S files 27 | #make cleanASM: 28 | #clean all .S files 29 | 30 | #Deal with .S Files 31 | ASM_SOURCE = $(wildcard *.S) 32 | INSTONLY = $(patsubst %.S,%.inst,$(ASM_SOURCE)) 33 | DATAANDINST = $(patsubst %.S,%.data,$(ASM_SOURCE)) 34 | OMFILE = $(patsubst %.S,%.om,$(ASM_SOURCE)) 35 | OFILE = $(patsubst %.S,%.o,$(ASM_SOURCE)) 36 | <<<<<<< HEAD 37 | all: InstOnly DataAndInst OMFile OFile 38 | ======= 39 | OBJDUMP = $(patsubst %.S,%.txt,$(ASM_SOURCE)) 40 | all: InstOnly DataAndInst Objdump cleanTMP 41 | >>>>>>> eb6a9bb3e09cf42ef8beb09a5c9ad229ca47bce1 42 | InstOnly: $(INSTONLY) 43 | DataAndInst: $(DATAANDINST) 44 | OMFile: $(OMFILE) 45 | OFile: $(OFILE) 46 | <<<<<<< HEAD 47 | ======= 48 | Objdump: $(OBJDUMP) 49 | >>>>>>> eb6a9bb3e09cf42ef8beb09a5c9ad229ca47bce1 50 | 51 | #rules 52 | Bin2Data: ./Utils/Bin2Data.c 53 | gcc -o Bin2Data ./Utils/Bin2Data.c 54 | %.o: %.S 55 | <<<<<<< HEAD 56 | riscv32-unknown-elf-gcc -c $< -o $@ -march=rv32i 57 | %.om: %.o 58 | riscv32-unknown-elf-ld $< -o $@ 59 | %-Data.bin: %.om 60 | riscv32-unknown-elf-objcopy -O binary $< $@ 61 | %-Inst.bin: %.om 62 | riscv32-unknown-elf-objcopy --dump-section .text=$@ $< 63 | ======= 64 | ./Utils/riscv32-unknown-elf-as $< -o $@ -march=rv32i 65 | %.om: %.o 66 | ./Utils/riscv32-unknown-elf-ld $< -o $@ 67 | %-Data.bin: %.om 68 | ./Utils/riscv32-unknown-elf-objcopy -O binary $< $@ 69 | %-Inst.bin: %.om 70 | ./Utils/riscv32-unknown-elf-objcopy --dump-section .text=$@ $< 71 | >>>>>>> eb6a9bb3e09cf42ef8beb09a5c9ad229ca47bce1 72 | %.data: %-Data.bin Bin2Data 73 | ./Bin2Data $< $@ 74 | %.inst: %-Inst.bin Bin2Data 75 | ./Bin2Data $< $@ 76 | <<<<<<< HEAD 77 | clean: 78 | -rm -f *.o *.om *.bin *.data *.inst Bin2Data 79 | ======= 80 | %.txt: %.om 81 | ./Utils/riscv32-unknown-elf-objdump -d $< > $@ 82 | cleanTMP: 83 | -rm -f *.om *.o *.bin Bin2Data 84 | clean: 85 | -rm -f *.data *.inst *.txt *.om *.o *.bin Bin2Data 86 | >>>>>>> eb6a9bb3e09cf42ef8beb09a5c9ad229ca47bce1 87 | cleanASM: 88 | -rm -f *.S 89 | 90 | .SUFFIXES: 91 | 92 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/README.md: -------------------------------------------------------------------------------- 1 | 2_BRAMInputFileGenerator 2 | ===================== 3 | ####此文件夹用于存放文件处理MakeFile脚本，Makefile具体用法参加Makefile文件注释。 4 | * Utils文件夹内预置了编译好的riscv-tools，Makefile需要调用到，Ubuntu-64bit机器应该都可以运行 5 | * ExampleCode/ASMCode中包含了一些简单的汇编测试文件，文档尚无 6 | * ExampleCode/RISCVTest_rv32ui中包含了已经经过cpp程序预处理过的汇编文件，预处理前的汇编代码放在SourceCode文件夹中（你应该用不到） 7 | * ExampleCode/RISCVTest_rv32ui中代码修改自https://github.com/riscv/riscv-tests ，总共包含800+项riscv CPU功能测试，作为最终的验收标准 8 | 9 | ####你只需要将需要处理的.S文件放置到Makefile相同路径下，执行make既可以获得你需要的.inst和.data文件，用于初始化CPU的blcok memory 10 | 11 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/Utils/Bin2Data.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | void bytesToHexstring(char* bytes,int bytelength,char *hexstring,int hexstrlength) 5 | { 6 | char str2[16] = {'0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f'}; 7 | int i,j,b; 8 | char s1,s2; 9 | for (i=0,j=0;i>4); 12 | s1 = str2[b]; 13 | hexstring[j] = s1; 14 | b = 0x0f & bytes[i]; 15 | s2 = str2[b]; 16 | j++; 17 | hexstring[j] = s2; 18 | } 19 | } 20 | 21 | int main(int argc, char* argv[]) 22 | { 23 | char tmp[4]; 24 | char str[4*2+1]; 25 | if(argc!=3) 26 | { 27 | printf("Usage: ./BIN2BRAM BinFileName BRAMFileName\n"); 28 | exit(-1); 29 | } 30 | FILE* fp1=fopen(argv[1],"rb"); 31 | if(!fp1) 32 | { 33 | printf("File %s Doesn't Exist!\n",argv[1]); 34 | exit(-1); 35 | } 36 | FILE* fp2=fopen(argv[2],"wt"); 37 | if(!fp2) 38 | { 39 | printf("Failed to open File %s!\n",argv[2]); 40 | exit(-1); 41 | } 42 | // 43 | fread(tmp+3,sizeof(char),1,fp1); 44 | fread(tmp+2,sizeof(char),1,fp1); 45 | fread(tmp+1,sizeof(char),1,fp1); 46 | fread(tmp,sizeof(char),1,fp1); 47 | while(!feof(fp1)) 48 | { 49 | // 50 | bytesToHexstring(tmp,1,str,2); 51 | bytesToHexstring(tmp+1,1,str+2,2); 52 | bytesToHexstring(tmp+2,1,str+4,2); 53 | bytesToHexstring(tmp+3,1,str+6,2); 54 | <<<<<<< HEAD 55 | ======= 56 | str[8] = 0; 57 | >>>>>>> eb6a9bb3e09cf42ef8beb09a5c9ad229ca47bce1 58 | fprintf(fp2,"%s\n",str); 59 | // 60 | fread(tmp+3,sizeof(char),1,fp1); 61 | fread(tmp+2,sizeof(char),1,fp1); 62 | fread(tmp+1,sizeof(char),1,fp1); 63 | fread(tmp,sizeof(char),1,fp1); 64 | } 65 | 66 | fclose(fp1); 67 | fclose(fp2); 68 | return 0; 69 | } 70 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/Utils/riscv32-unknown-elf-as: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Indigo6/Computer-Architecture_Lab1-2/bda98bd15c870277a4b0af4e739f0004b7e284df/2_BRAMInputFileGenerator/Utils/riscv32-unknown-elf-as -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/Utils/riscv32-unknown-elf-ld: -------------------------------------------------------------------------------- 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指令集卷2-特权级指令-中文版.pdf -------------------------------------------------------------------------------- /5_DetailDocuments/资料/RISCV指令集总览表格.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Indigo6/Computer-Architecture_Lab1-2/bda98bd15c870277a4b0af4e739f0004b7e284df/5_DetailDocuments/资料/RISCV指令集总览表格.pdf -------------------------------------------------------------------------------- /5_DetailDocuments/资料/The RISC-V Instruction Set Manual Volume I User-Level ISA-V2.2.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Indigo6/Computer-Architecture_Lab1-2/bda98bd15c870277a4b0af4e739f0004b7e284df/5_DetailDocuments/资料/The RISC-V Instruction Set Manual Volume I User-Level ISA-V2.2.pdf -------------------------------------------------------------------------------- /5_DetailDocuments/资料/The RISC-V Instruction Set Manual Volume II Privileged Architecture V1.9.1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Indigo6/Computer-Architecture_Lab1-2/bda98bd15c870277a4b0af4e739f0004b7e284df/5_DetailDocuments/资料/The RISC-V Instruction Set Manual Volume II Privileged Architecture V1.9.1.pdf -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 HaojunXia 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # RISC-V CPU 设计报告 2 | 3 | RV32I 指令格式包括以下 6 种，每种指令格式都是固定的 32 位指令，所以指令在内存中必须4字节对齐，否则将触发异常。其中 rd 表示目的寄存器，rs1 是源操作数寄存器1，rs2 是源操作数寄存器2。 4 | 5 | ![RISC-V](./images/RISC-V.png) 6 | 7 | 需要实现的指令分别有，类型通过指令格式/立即数生成方式不同而不同: 8 | 9 | + R-Type: 寄存器-寄存器操作，ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND 10 | + I-Type: **加入JALR**，短立即数操作和 load 操作，SLLI, SRLI, SRAI,（前三者**被编码为I类格式的特例**） ADDI, SLTI, SLTIU, XORI, ORI, ANDI, LB, LH, LW, LBU, LHU 11 | + S-Type: Store操作，SB, SH, SW 12 | + B-Type: Branch操作，BEQ, BNE, BLTU, BGE, BGEU 13 | + U-Type: 长立即数指令，LUI, AUIPC 14 | + J-Type: JMP操作，JAL，~~JALR~~ 15 | 16 | ## 易错点汇总 17 | 1. JalR 为 I 型指令； 18 | 2. 不同类型指令的立即数扩展，RVI32 麦克老狼的博客有误； 19 | 3. Operand 默认无符号，算术右移要指明 Operand1 是 $signed 而类型， 而且运算符是 '>>>'，且移位运算的位数只需要取 Operand2 的低五位； 20 | 4. Store 语句写入的数据 WD 也需要和根据地址 A 进行调整，因为 sb/sh 只把 WD 最低的 byte/half-word 存入相应位置，而不是相应的 byte/half-word 存入相应位置（刚开始还理解错了）。 21 | 例如 WE = 4'b0011 (sh)， A = 32'b\*10，WD = 32'hef\*，则 wea=4'b1100，dina = 32'h\*ef。总结可得，wea = WE< IDSegReg 是 IF-ID 段寄存器，同时包含了一个同步读写的 Bram。此时如果再通过段寄存器缓存，那么需要两个时钟上升沿才能将数据传递到 Ex 段，因此在段寄存器模块中调用该同步 memory，直接将输出传递到 ID 段组合逻辑。调用mem模块后输出为RD_raw，通过assign RD = stall_ff ? RD_old : (clear_ff ? 32'b0 : RD_raw ); 从而实现RD段寄存器 stall 和 clear 功能 64 | 65 | 如下图所示，一个上升沿 Instr 即可传到 ID 段。如果有冲突，则此时 RD_Old 在上升沿保存的是上一次的 RD_Raw，而 stall/clear 信号马上作用，使得 RD=RD_Old。 66 | 67 | 因此，InstructionRam InstructionRamInst() 传参部分，clk 不需要取反，addr 传入 A (其实即PCF) 68 | 69 | ![instr_mem](./images/IDSegReg.jpg) 70 | 71 | ### ImmOperandUnit 72 | 73 | imm表示指令中的立即数，比如imm[11:0]，表示一个12位的立即数，它的高20位会符号位扩展，imm[31:12]表示一个32位的立即数，它的低12位会补0。 74 | 75 | ~~下图是各种指令格式扩展后的32位立即数。~~ 76 | 77 | **修正: 仍参照开头的指令格式图，RVI32 麦克老狼的博客有误！** 78 | 79 | ```verilog 80 | always@(*) 81 | begin 82 | case(Type) 83 | `ITYPE: Out<={ {21{In[31]}}, In[30:20] }; 84 | `STYPE: Out<={ {21{In[31]}}, In[30:25], In[11:7]}; 85 | `BTYPE: Out<={ {20{In[31]}}, {In[7]}, In[30:25], In[11:8], {1'b0} }; 86 | `UTYPE: Out<={ In[31:12], {12{1'b0}} }; 87 | `JTYPE: Out<={ {12{In[31]}}, In[19:12], In[20], In[30:21], {1'b0} }; 88 | `RTYPE: Out<=32'hxxxxxxxx; 89 | default:Out<=32'hxxxxxxxx; 90 | endcase 91 | end 92 | ``` 93 | 94 | 95 | 96 | ### ALU 97 | 98 | > ALU接受两个操作数，根据AluContrl的不同，进行不同的计算操作，将计算结果输出到AluOut。AluContrl的类型定义在Parameters.v中 99 | 100 | 根据指令的实际功能进行实现，如下 101 | 102 | + **容易错的点：** 103 | 1. Operand 默认无符号 104 | 2. 算术右移要指明 Operand1 是 $signed 而类型， 而且运算符是 '>>>' 105 | 3. 移位运算的位数只需要取 Operand2 的低五位 106 | 107 | ```verilog 108 | always@(*) 109 | begin 110 | case(AluContrl) 111 | `ADD: AluOut <= Operand1 + Operand2; 112 | `SUB: AluOut <= Operand1 - Operand2; 113 | `XOR: AluOut <= Operand1 ^ Operand2; 114 | `OR: AluOut <= Operand1 | Operand2; 115 | `AND: AluOut <= Operand1 & Operand2; 116 | `SRL: AluOut <= (Operand1>>Operand2[4:0]); 117 | `SLL: AluOut <= (Operand1<>>Operand2[4:0]); 119 | `SLT: AluOut <= ($signed(Operand1) < $signed(Operand2)) ? 32'b1 : 32'b0; 120 | `SLTU:AluOut <= (Operand1 < Operand2) ? 32'b1 : 32'b0; 121 | `LUI: AluOut <= Operand2;//待补全!!! 122 | default:AluOut<=32'hxxxxxxxx; 123 | endcase 124 | ``` 125 | 126 | ### BranchDecisionMaking 127 | 128 | 根据不同的 BranchTypeE 来对 Operand1, Operand2 进行逻辑运算，从而判断是跳转 (即产生 BranchE 信号)，如下（注意的地方仍然是有符号运算需要指明） 129 | 130 | ```verilog 131 | always@(*) 132 | begin 133 | case(BranchTypeE) 134 | `NOBRANCH: BranchE<=1'b0; 135 | `BEQ: BranchE<=(Operand1 == Operand2) ? 1'b1 : 1'b0; 136 | `BNE: BranchE<=(Operand1 != Operand2) ? 1'b1 : 1'b0; 137 | `BLT: BranchE<=($signed(Operand1) < $signed(Operand2)) ? 1'b1 : 1'b0; 138 | `BLTU:BranchE<=(Operand1 < Operand2) ? 1'b1 : 1'b0; 139 | `BGE: BranchE<=($signed(Operand1) >= $signed(Operand2)) ? 1'b1 : 1'b0; 140 | `BGEU: BranchE<=(Operand1 >= Operand2) ? 1'b1 : 1'b0; 141 | default:BranchE<=1'b0; 142 | end 143 | ``` 144 | 145 | ### WBSegReg 146 | 147 | > WBSegReg 是 Write Back 段寄存器，类似于 IDSegReg.V 中对 Bram 的调用和拓展，在段寄存器模块中调用该同步memory，直接将输出传递到 WB 段组合逻辑。调用 mem 模块后输出为 RD_raw，通过 assign RD = stall_ff ? RD_old : (clear_ff ? 32'b0 : RD_raw ); 从而实现 RD 段寄存器 stall 和 clear 功能 148 | 149 | 与 IDSegReg 模块同理，clk 不需要取反。通过查看 RV32Core.v 的接口参数，可知 150 | 151 | 1. wea 表示相应地址可以写入的字节序号, wea[i]=1 时, 则表示 32 位数据中 0~3 字节中第 i 个字节可以写入。但 WE(MemWrite) 独热码只能表示存储指令类型（存字/半字/字节)，需与 A(AluOut) 即计算所得的写目标地址结合。 152 | + **修正：写入的数据 WD 也需要和根据地址 A 进行调整，因为 sb/sh 只把 WD 最低的 byte/half-word 存入相应位置，而不是相应的 b/h 存入相应位置（刚开始还理解错了）** 153 | + 例如 WE = 4'b0011 (sh)， A = 32'b\*10，WD = 32'hef\*，则 wea=4'b1100，dina = 32'h\*ef。**总结可得，wea = WE<修正：addra 传入 A[31:2]** 157 | 158 | 3. ~~dina 传入 WD (即 StoreData，由 Forward 选择器在 AluOut, RegWriteData 和 RegOut2 中选择产生)~~ 159 | 160 | ### DataExt 161 | 162 | > DataExt 是用来处理非字对齐load的情形，同时根据 load 的不同模式对 Data Mem 中 load 的数进行符号或者无符号拓展，组合逻辑电路 163 | 164 | 根据 RegWrite 和 LoadedBytesSelect 生成 OUT，如下 165 | 166 | ```verilog 167 | always@(*) 168 | begin 169 | case(RegWriteW) 170 | `LB: 171 | begin 172 | case(LoadedBytesSelect) 173 | 2'b11: OUT<={24{IN[31]},IN[31:24]}; 174 | 2'b10: OUT<={24{IN[23]},IN[23:16]}; 175 | 2'b01: OUT<={24{IN[15]},IN[15:8]}; 176 | 2'b00: OUT<={24{IN[7]},IN[7:0]}; 177 | end 178 | ······ 179 | ``` 180 | 181 | ### ControlUnit 182 | 183 | > 功能说明：ControlUnit 是本CPU的指令译码器，组合逻辑电路 184 | > 185 | > 输入：Op, Fn3, Fn7 186 | > 187 | > 输出：JalD, JalrD, RegWriteD, MemToRegD, MemWriteD, LoadNpcD, RegReadD[1], BranchTypeD, AluContrlD, AluSrc2D, AluSrc1D, ImmType. 188 | 189 | 自己理解的功能：根据指令的opcode, funct3 和 funct7 字段进行 Instrcution Decode，并生成各种控制信号。 190 | 191 | 大体思路：先根据 opcode 确定指令类型，然后再根据该类型指令的指令格式进行解码。 192 | 193 | 具体思路如下： 194 | 195 | 1. JalD：只有 Jal 指令为1 196 | 197 | 2. JalrD：只有 Jalr 指令为1 198 | 199 | 3. RegWriteD：Branch/Store 指令为0，其它为 3'd3，LB 3'd1, LH 3'd2, LW 3'd3, LBU 3'd4, LHU 3'd5 200 | 201 | 4. MemToRegD：只有 Load 指令为1 202 | 203 | 5. MemWriteD：SW 4'b1111, SH 4'b0011, SB 4'b0001，其他为4'd0 204 | 205 | 6. LoadNpcD：只有 Jal/Jalr 指令为1 206 | 207 | 7. **RegReadD：I 型指令为 2'b10, R/S/B 型指令为 2’b11, 其他指令为 2'b00** 208 | 209 | 8. BranchTypeD：BEQ 3'd1, BNE 3'd2, BLT 3'd3, BLTU 3'd4, BGE 3'd5, BGEU 3'd6，其他指令为 3'd0 210 | 211 | 9. AluContrlD：运算指令已再 Parameter.v 中定义好了，Jalr/Load/Store/AUIPC/LUI 为 4'd3，其他指令无关 AluContrlD 212 | 213 | 10. ~~AluSrc2D：SLLI/SRLI/SRAI 指令为 2’b01，其它 I、J 型指令 为 2'b10，其他类型指令为 2'b0~~ 214 | **修正：AluSrc2D：SLLI/SRLI/SRAI 指令为 2’b01，I(除前三者)\U\S 型指令 为 3'b10，其他类型指令为 2'b00** 215 | 216 | 11. AluSrc1D：JALR/AUIPC/LUI 指令为1，其他为0 217 | 218 | 12. ImmTpye： 219 | 220 | > - R-Type: 寄存器-寄存器操作，ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND 221 | > - I-Type: **加入JALR**, 短立即数操作和 load 操作，SLLI, SRLI, SRAI,（前三者**被编码为I类格式的特例**） ADDI, SLTI, SLTIU, XORI, ORI, ANDI, LB, LH, LW, LBU, LHU 222 | > - S-Type: Store操作，SB, SH, SW 223 | > - B-Type: Branch操作，BEQ, BNE, BLTU, BGE, BGEU 224 | > - U-Type: 长立即数指令，LUI, AUIPC 225 | > - J-Type: JMP操作，JAL，~~JALR~~ 226 | 227 | ### HarzardUnit 228 | 229 | > HarzardUnit用来处理流水线冲突，通过插入气泡，forward以及冲刷流水段解决数据相关和控制相关，组合逻辑电路 230 | > 231 | > 输出: 232 | > 233 | > ​ StallF, FlushF, StallD, FlushD, StallE, FlushE, StallM, FlushM, StallW, FlushW，控制五个段寄存器进行stall（维持状态不变）和 flush（清零） 234 | > 235 | > ​ Forward1E, Forward2E，控制 forward 236 | 237 | 大体思路：由于 CPU 设计图中只有 RegWriteData 能被写进 RegFile，所以不存在读后写和写后写相关，只考虑写后读和控制冲突。体通过不同阶段的 reg 地址比对和是否为控制指令，进行判断是否存在冲突，然后根据冲突类型产生 stall/flush/forward信号。 238 | 239 | 具体思路（R0 寄存器不会改变，所以不考虑冲突）： 240 | 241 | 1. CPU 重置 clear: 242 | 所有stall置0, flush置1 243 | 2. 转发: 244 | 写指令非 load 指令的写后读冲突，即靠后的读取操作读取的寄存器没有被及时更新，需要将 AluOutM 和 RegWriteData 转发到EX段。(这里只讨论 Forward1E，Forward2E 同理): 245 | + RegReadE[1]==1, RegWriteM==1, 且Rs1E==RdM, 那么 Forward1E 置为 2'b10 246 | + RegReadE[1]==1, RegWriteW==1, 且Rs1E==RdW, 那么 Forward1E 置为 2'b01 247 | 3. 分支跳转处理: 248 | + 检测到JalD: 清空 IF/ID 寄存器段内容, StallD置0, FlushD置1。 249 | + 检测到BranchE, JalrE: 清空 IF/ID、ID/EX寄存器段内容，FlushD/E=1。 250 | 4. 停等: 一条 load 指令，与紧跟其后的一条指令有写后读数据相关, 那么就要在他们插入气泡，停等一个周期, 再通过转发消除解决冲突。 251 | + ~~具体做法就是,当 RegReadE[1] 或 RegReadE[0] 为1 且 RdM 与 Rs1E 或 Rs2E 相等时，清空 EX/MEM 寄存器段 (Stall=0, Flush=1)，并使 IF/ID 与 ID/EX 寄存器段保持不变 (Stall=1,Flush=0) 即可。~~ 252 | **修改：具体做法就是，当 MemToRegE 为 1 且 RdE 与 Rs1D 或 Rs2D 相等时，清空 EX/MEM 寄存器段 (StallE=0, FlushE=1)，并使 IF/ID 与 ID/EX 寄存器段保持不变 (StallD/F=1,FlushD/F=0) 即可。** 253 | 254 | ## 回答问题 255 | 256 | 1. 为什么将 DataMemory 和 InstructionMemory 嵌入在段寄存器中? 257 | 258 | DataMemory 和 InstructionMemory 是同步读写的，寄存器文件的数据出口处自带了 D 锁存器, 因此不需要在段寄存其中暂存 259 | 260 | 2. DataMemory 和 InstructionMemory 输入地址是字 (32bit) 地址,如何将访存地址转化为字地址输入进去? 261 | 262 | InstructionMemory的地址输入是 PCF, 已经对齐，无需转化；DataMemory的输入地址是 ALUOUT, 需要低两位清零 (如果是 store，用 wea 独热码表示写入的地址；如果是 load, 在清零之前把低两位存入 LoadedBytesSelect：`LoadedBytesSelect <= clear ? 2'b00 : A[1:0];`) 263 | 264 | 3. 如何实现 DataMemory 的非字对齐的 Load? 265 | 266 | DataMemory addra 传入 `{A[32:2],{2'b00}}`，(即 AluOut 低两位清零，计算所得的写目标地址对齐后的地址)，在清零之前把低两位存入 LoadedBytesSelect，再在 DataExt 模块选择数据。 267 | 268 | 4. 如何实现 DataMemory 的非字对齐的Store? 269 | 270 | DataMemory addra 传入 `{A[32:2],{2'b00}}`，(即 AluOut 低两位清零，计算所得的写目标地址对齐后的地址)，wea 表示相应地址可以写入的字节序号, wea[i]=1 时, 则表示 32 位数据中 0~3 字节中第 i 个字节可以写入。但 WE(MemWrite) 独热码只能表示存储指令类型（存字/半字/字节)，需与 A(AluOut) 即计算所得的写目标地址结合。 271 | 272 | 例如 WE = 4'b0011 (sh)， A = 32'b*10，则 wea=4'b1100，**总结可得，wea = WE<