├── quartus ├── db │ ├── Safe.cmp.logdb │ ├── Safe.map.logdb │ ├── Safe.map_bb.logdb │ ├── Safe.smart_action.txt │ ├── Safe.asm.rdb │ ├── Safe.cmp.bpm │ ├── Safe.cmp.cdb │ ├── Safe.cmp.hdb │ ├── Safe.cmp.kpt │ ├── Safe.cmp.rdb │ ├── Safe.cmp.tdb │ ├── Safe.eco.cdb │ ├── Safe.lpc.rdb │ ├── Safe.map.bpm │ ├── Safe.map.cdb │ ├── Safe.map.hdb │ ├── Safe.map.kpt │ ├── Safe.cmp.ecobp │ ├── Safe.cmp0.ddb │ ├── Safe.map.ecobp │ ├── Safe.rtlv.hdb │ ├── Safe.(0).cnf.cdb │ ├── Safe.(0).cnf.hdb │ ├── Safe.(1).cnf.cdb │ ├── Safe.(1).cnf.hdb │ ├── Safe.(2).cnf.cdb │ ├── Safe.(2).cnf.hdb │ ├── Safe.(3).cnf.cdb │ ├── Safe.(3).cnf.hdb │ ├── Safe.asm_labs.ddb │ ├── Safe.map_bb.cdb │ ├── Safe.map_bb.hdb │ ├── Safe.pre_map.cdb │ ├── Safe.pre_map.hdb │ ├── Safe.rtlv_sg.cdb │ ├── Safe.sgdiff.cdb │ ├── Safe.sgdiff.hdb │ ├── Safe.cmp_merge.kpt │ ├── Safe.rtlv_sg_swap.cdb │ ├── Safe.tis_db_list.ddb │ ├── Safe.cbx.xml │ ├── logic_util_heursitic.dat │ ├── Safe.sld_design_entry.sci │ ├── Safe.sld_design_entry_dsc.sci │ ├── Safe.db_info │ ├── Safe.tmw_info │ ├── Safe.smp_dump.txt │ ├── Safe.lpc.html │ ├── Safe.lpc.txt │ ├── Safe.asm.qmsg │ ├── prev_cmp_Safe.asm.qmsg │ ├── Safe.eda.qmsg │ ├── prev_cmp_Safe.eda.qmsg │ ├── Safe.hif │ ├── Safe.hier_info │ ├── prev_cmp_Safe.map.qmsg │ ├── Safe.map.qmsg │ └── Safe.fit.qmsg ├── Safe.done ├── incremental_db │ ├── compiled_partitions │ │ ├── Safe.root_partition.cmp.logdb │ │ ├── Safe.root_partition.cmp.cdb │ │ ├── Safe.root_partition.cmp.dfp │ │ ├── Safe.root_partition.cmp.hdb │ │ ├── Safe.root_partition.cmp.kpt │ │ ├── Safe.root_partition.map.cdb │ │ ├── Safe.root_partition.map.dpi │ │ ├── Safe.root_partition.map.hdb │ │ ├── Safe.root_partition.map.kpt │ │ ├── Safe.root_partition.cmp.rcfdb │ │ └── Safe.root_partition.cmp.re.rcfdb │ └── README ├── Safe.pof ├── Safe.sof ├── Safe.fit.rpt ├── Safe.map.smsg ├── simulation │ └── modelsim │ │ ├── Safe.sft │ │ └── Safe_modelsim.xrf ├── Safe.dpf ├── Safe.map.summary ├── Safe.fit.summary ├── Safe.qws ├── Safe.qpf ├── Safe.tan.summary ├── Safe.qsf ├── Safe.eda.rpt ├── Safe.asm.rpt ├── Safe.flow.rpt └── Safe.map.rpt └── src ├── LCD_Reset_Delay.v ├── Servo_Controller.v ├── LCD_Controller.v ├── LCD_Print.v └── Safe.v /quartus/db/Safe.cmp.logdb: -------------------------------------------------------------------------------- 1 | v1 2 | -------------------------------------------------------------------------------- /quartus/db/Safe.map.logdb: -------------------------------------------------------------------------------- 1 | v1 2 | -------------------------------------------------------------------------------- /quartus/db/Safe.map_bb.logdb: -------------------------------------------------------------------------------- 1 | v1 2 | -------------------------------------------------------------------------------- /quartus/Safe.done: -------------------------------------------------------------------------------- 1 | Tue Apr 30 16:12:37 2019 2 | -------------------------------------------------------------------------------- /quartus/db/Safe.smart_action.txt: -------------------------------------------------------------------------------- 1 | SOURCE 2 | -------------------------------------------------------------------------------- /quartus/incremental_db/compiled_partitions/Safe.root_partition.cmp.logdb: -------------------------------------------------------------------------------- 1 | v1 2 | -------------------------------------------------------------------------------- /quartus/Safe.pof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ItamarRocha/verilog-safe/master/quartus/Safe.pof -------------------------------------------------------------------------------- /quartus/Safe.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ItamarRocha/verilog-safe/master/quartus/Safe.sof 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-------------------------------------------------------------------------------- 1 | Quartus_Version = Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition 2 | Version_Index = 184638978 3 | Creation_Time = Mon Apr 29 15:24:40 2019 4 | -------------------------------------------------------------------------------- /quartus/incremental_db/compiled_partitions/Safe.root_partition.cmp.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ItamarRocha/verilog-safe/master/quartus/incremental_db/compiled_partitions/Safe.root_partition.cmp.cdb -------------------------------------------------------------------------------- /quartus/incremental_db/compiled_partitions/Safe.root_partition.cmp.dfp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ItamarRocha/verilog-safe/master/quartus/incremental_db/compiled_partitions/Safe.root_partition.cmp.dfp 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https://raw.githubusercontent.com/ItamarRocha/verilog-safe/master/quartus/incremental_db/compiled_partitions/Safe.root_partition.cmp.re.rcfdb -------------------------------------------------------------------------------- /quartus/Safe.dpf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /src/LCD_Reset_Delay.v: -------------------------------------------------------------------------------- 1 | module Reset_Delay( input iCLK, output reg oRESET); 2 | reg [19:0] Cont; 3 | 4 | always@(posedge iCLK) 5 | begin 6 | if(Cont!=20'hFFFFF) 7 | begin 8 | Cont <= Cont + 1'b1; 9 | oRESET <= 1'b0; 10 | end 11 | else 12 | oRESET <= 1'b1; 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /quartus/db/Safe.tmw_info: -------------------------------------------------------------------------------- 1 | start_full_compilation:s:00:00:13 2 | start_analysis_synthesis:s:00:00:03-start_full_compilation 3 | start_analysis_elaboration:s-start_full_compilation 4 | start_fitter:s:00:00:05-start_full_compilation 5 | start_assembler:s:00:00:02-start_full_compilation 6 | start_timing_analyzer:s:00:00:01-start_full_compilation 7 | start_eda_netlist_writer:s:00:00:02-start_full_compilation 8 | -------------------------------------------------------------------------------- /quartus/Safe.map.summary: -------------------------------------------------------------------------------- 1 | Analysis & Synthesis Status : Successful - Tue Apr 30 16:12:26 2019 2 | Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition 3 | Revision Name : Safe 4 | Top-level Entity Name : Safe 5 | Family : Cyclone II 6 | Total logic elements : 209 7 | Total combinational functions : 206 8 | Dedicated logic registers : 110 9 | Total registers : 110 10 | Total pins : 40 11 | Total virtual pins : 0 12 | Total memory bits : 0 13 | Embedded Multiplier 9-bit elements : 0 14 | Total PLLs : 0 15 | -------------------------------------------------------------------------------- /quartus/db/Safe.smp_dump.txt: -------------------------------------------------------------------------------- 1 | 2 | State Machine - |Safe|message 3 | Name message.00 message.10 message.01 4 | message.00 0 0 0 5 | message.01 1 0 1 6 | message.10 1 1 0 7 | 8 | State Machine - |Safe|mLCD_ST 9 | Name mLCD_ST.000011 mLCD_ST.000010 mLCD_ST.000001 mLCD_ST.000000 10 | mLCD_ST.000000 0 0 0 0 11 | mLCD_ST.000001 0 0 1 1 12 | mLCD_ST.000010 0 1 0 1 13 | mLCD_ST.000011 1 0 0 1 14 | 15 | State Machine - |Safe|LCD_Controller:u0|ST 16 | Name ST.11 ST.10 ST.01 ST.00 17 | ST.00 0 0 0 0 18 | ST.01 0 0 1 1 19 | ST.10 0 1 0 1 20 | ST.11 1 0 0 1 21 | -------------------------------------------------------------------------------- /quartus/Safe.fit.summary: -------------------------------------------------------------------------------- 1 | Fitter Status : Successful - Tue Apr 30 16:12:31 2019 2 | Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition 3 | Revision Name : Safe 4 | Top-level Entity Name : Safe 5 | Family : Cyclone II 6 | Device : EP2C35F672C6 7 | Timing Models : Final 8 | Total logic elements : 207 / 33,216 ( < 1 % ) 9 | Total combinational functions : 206 / 33,216 ( < 1 % ) 10 | Dedicated logic registers : 110 / 33,216 ( < 1 % ) 11 | Total registers : 110 12 | Total pins : 40 / 475 ( 8 % ) 13 | Total virtual pins : 0 14 | Total memory bits : 0 / 483,840 ( 0 % ) 15 | Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % ) 16 | Total PLLs : 0 / 4 ( 0 % ) 17 | -------------------------------------------------------------------------------- /quartus/incremental_db/README: -------------------------------------------------------------------------------- 1 | This folder contains data for incremental compilation. 2 | 3 | The compiled_partitions sub-folder contains previous compilation results for each partition. 4 | As long as this folder is preserved, incremental compilation results from earlier compiles 5 | can be re-used. To perform a clean compilation from source files for all partitions, both 6 | the db and incremental_db folder should be removed. 7 | 8 | The imported_partitions sub-folder contains the last imported QXP for each imported partition. 9 | As long as this folder is preserved, imported partitions will be automatically re-imported 10 | when the db or incremental_db/compiled_partitions folders are removed. 11 | 12 | -------------------------------------------------------------------------------- /quartus/Safe.qws: -------------------------------------------------------------------------------- 1 | [ProjectWorkspace] 2 | ptn_Child1=Frames 3 | [ProjectWorkspace.Frames] 4 | ptn_Child1=ChildFrames 5 | [ProjectWorkspace.Frames.ChildFrames] 6 | ptn_Child1=Document-0 7 | ptn_Child2=Document-1 8 | ptn_Child3=Document-2 9 | [ProjectWorkspace.Frames.ChildFrames.Document-2] 10 | ptn_Child1=ViewFrame-0 11 | [ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0] 12 | DocPathName=../../../../../altera/91sp2/quartus/bin/pin_planner.ppl 13 | DocumentCLSID={428be327-2a68-4a16-a2c9-0502a8811afc} 14 | IsChildFrameDetached=True 15 | IsActiveChildFrame=False 16 | ptn_Child1=StateMap 17 | [ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0.StateMap] 18 | AFC_CMP_AP_NAME=Safe 19 | AFC_PROJ_DB_PATH=C:/Users/aluno/Desktop/Projeto CL2/Quartus/db/Safe.quartus_db 20 | AFC_IN_REPORT=False 21 | -------------------------------------------------------------------------------- /src/Servo_Controller.v: -------------------------------------------------------------------------------- 1 | /* 2 | Code from @mcgodfrey 3 | https://gist.github.com/mcgodfrey/b94acfc796c240a4a164 4 | 5 | Takes an 8-bit position as an input 6 | Output a single pwm signal with period of ~20ms 7 | Pulse width = 1ms -> 2ms full scale. 1.5ms is center position 8 | */ 9 | module Servo_Controller ( 10 | input clk, 11 | input rst, 12 | input [7:0] position, 13 | output servo 14 | ); 15 | 16 | reg pwm_q, pwm_d; 17 | reg [19:0] ctr_q, ctr_d; 18 | assign servo = pwm_q; 19 | //position (0-255) maps to 50,000-100,000 (which corresponds to 1ms-2ms @ 50MHz) 20 | //this is approximately (position+165)<<8 21 | //The servo output is set by comparing the position input with the value of the counter (ctr_q) 22 | always @(*) begin 23 | ctr_d = ctr_q + 1'b1; 24 | if (position + 9'd165 > ctr_q[19:8]) begin 25 | pwm_d = 1'b1; 26 | end else begin 27 | pwm_d = 1'b0; 28 | end 29 | end 30 | 31 | always @(posedge clk) begin 32 | if (rst) begin 33 | ctr_q <= 1'b0; 34 | end else begin 35 | ctr_q <= ctr_d; 36 | end 37 | pwm_q <= pwm_d; 38 | end 39 | endmodule 40 | -------------------------------------------------------------------------------- /quartus/Safe.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2010 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 20 | # Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition 21 | # Date created = 15:24:40 April 29, 2019 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "9.1" 26 | DATE = "15:24:40 April 29, 2019" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "Safe" 31 | -------------------------------------------------------------------------------- /quartus/Safe.tan.summary: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------------- 2 | Timing Analyzer Summary 3 | -------------------------------------------------------------------------------------- 4 | 5 | Type : Worst-case tsu 6 | Slack : N/A 7 | Required Time : None 8 | Actual Time : 7.867 ns 9 | From : SW[14] 10 | To : mLCD_DATA[6] 11 | From Clock : -- 12 | To Clock : CLOCK_50 13 | Failed Paths : 0 14 | 15 | Type : Worst-case tco 16 | Slack : N/A 17 | Required Time : None 18 | Actual Time : 10.019 ns 19 | From : ledG[1] 20 | To : LEDR 21 | From Clock : CLOCK_50 22 | To Clock : -- 23 | Failed Paths : 0 24 | 25 | Type : Worst-case th 26 | Slack : N/A 27 | Required Time : None 28 | Actual Time : -1.388 ns 29 | From : SW[6] 30 | To : message.10 31 | From Clock : -- 32 | To Clock : CLOCK_50 33 | Failed Paths : 0 34 | 35 | Type : Clock Setup: 'CLOCK_50' 36 | Slack : N/A 37 | Required Time : None 38 | Actual Time : 250.75 MHz ( period = 3.988 ns ) 39 | From : mDLY[10] 40 | To : mDLY[0] 41 | From Clock : CLOCK_50 42 | To Clock : CLOCK_50 43 | Failed Paths : 0 44 | 45 | Type : Total number of failed paths 46 | Slack : 47 | Required Time : 48 | Actual Time : 49 | From : 50 | To : 51 | From Clock : 52 | To Clock : 53 | Failed Paths : 0 54 | 55 | -------------------------------------------------------------------------------------- 56 | 57 | -------------------------------------------------------------------------------- /quartus/db/Safe.lpc.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 |
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
s010000100000000
u0121011211100000
r01000100000000
67 | -------------------------------------------------------------------------------- /quartus/db/Safe.lpc.txt: -------------------------------------------------------------------------------- 1 | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 2 | ; Legal Partition Candidates ; 3 | +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 4 | ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; 5 | +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 6 | ; s0 ; 10 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 | ; u0 ; 12 ; 1 ; 0 ; 1 ; 12 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 | ; r0 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 | +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 10 | -------------------------------------------------------------------------------- /src/LCD_Controller.v: -------------------------------------------------------------------------------- 1 | module LCD_Controller ( 2 | // Host Side 3 | input [7:0] iDATA, 4 | input iRS, 5 | input iStart, 6 | output reg oDone, 7 | input iCLK,iRST_N, 8 | 9 | // LCD Interface 10 | output [7:0] LCD_DATA, 11 | output LCD_RW, 12 | output reg LCD_EN, 13 | output LCD_RS 14 | ); 15 | 16 | parameter CLK_Divide = 16; 17 | 18 | // Internal Register 19 | reg [4:0] Cont; 20 | reg [1:0] ST; 21 | reg preStart,mStart; 22 | 23 | ///////////////////////////////////////////// 24 | // Only write to LCD, bypass iRS to LCD_RS 25 | assign LCD_DATA = iDATA; 26 | assign LCD_RW = 1'b0; 27 | assign LCD_RS = iRS; 28 | ///////////////////////////////////////////// 29 | 30 | always@(posedge iCLK or negedge iRST_N) 31 | begin 32 | if(!iRST_N) 33 | begin 34 | oDone <= 1'b0; 35 | LCD_EN <= 1'b0; 36 | preStart<= 1'b0; 37 | mStart <= 1'b0; 38 | Cont <= 0; 39 | ST <= 0; 40 | end 41 | else 42 | begin 43 | ////// Input Start Detect /////// 44 | preStart<= iStart; 45 | if({preStart,iStart}==2'b01) 46 | begin 47 | mStart <= 1'b1; 48 | oDone <= 1'b0; 49 | end 50 | ////////////////////////////////// 51 | if(mStart) 52 | begin 53 | case(ST) 54 | 0: ST <= 1; // Wait Setup 55 | 1: begin 56 | LCD_EN <= 1'b1; 57 | ST <= 2; 58 | end 59 | 2: begin 60 | if(Cont ? 82 | --g 4 | @ A B C D E F G H I J K L M N O 83 | --h 5 | P Q R S T U V W X Y Z [ \ ] ^ _ 84 | -- 6 | ` a b c d e f g h i j k l m n o 85 | -- 7 | p q r s t u v w x y z { | } ~ DEL 86 | ----------------------------------------------------------------------- 87 | -- Example "A" is row 4 column 1, so hex value is 8'h41" 88 | -- *see LCD Controller's Datasheet for other graphics characters available 89 | */ 90 | 91 | always @ (iCLK) 92 | begin 93 | if(MESSAGE == 2'b00) begin 94 | case(LUT_INDEX) 95 | // Initial 96 | LCD_INTIAL+0: LUT_DATA <= 9'h038; 97 | LCD_INTIAL+1: LUT_DATA <= 9'h00C; 98 | LCD_INTIAL+2: LUT_DATA <= 9'h001; 99 | LCD_INTIAL+3: LUT_DATA <= 9'h006; 100 | LCD_INTIAL+4: LUT_DATA <= 9'h080; 101 | 102 | // Line 1 103 | LCD_LINE1+14: LUT_DATA <= 9'h120; // Fim 104 | endcase 105 | end 106 | 107 | 108 | if(MESSAGE == 2'b01) begin 109 | case(LUT_INDEX) 110 | // Initial 111 | LCD_INTIAL+0: LUT_DATA <= 9'h038; 112 | LCD_INTIAL+1: LUT_DATA <= 9'h00C; 113 | LCD_INTIAL+2: LUT_DATA <= 9'h001; 114 | LCD_INTIAL+3: LUT_DATA <= 9'h006; 115 | LCD_INTIAL+4: LUT_DATA <= 9'h080; 116 | 117 | 118 | // Line 1 119 | LCD_LINE1+0: LUT_DATA <= 9'h141; // A 120 | LCD_LINE1+1: LUT_DATA <= 9'h143; // C 121 | LCD_LINE1+2: LUT_DATA <= 9'h143; // C 122 | LCD_LINE1+3: LUT_DATA <= 9'h145; // E 123 | LCD_LINE1+4: LUT_DATA <= 9'h153; // S 124 | LCD_LINE1+5: LUT_DATA <= 9'h153; // S 125 | 126 | LCD_LINE1+6: LUT_DATA <= 9'h120; // Space 127 | 128 | // Line 1 129 | LCD_LINE1+7: LUT_DATA <= 9'h144; // D 130 | LCD_LINE1+8: LUT_DATA <= 9'h145; // E 131 | LCD_LINE1+9: LUT_DATA <= 9'h14E; // N 132 | LCD_LINE1+10: LUT_DATA <= 9'h149; // I 133 | LCD_LINE1+11: LUT_DATA <= 9'h145; // E 134 | LCD_LINE1+12: LUT_DATA <= 9'h144; // D 135 | 136 | LCD_LINE1+13: LUT_DATA <= 9'h120; // Fim 137 | endcase 138 | end 139 | 140 | 141 | if(MESSAGE == 2'b10) begin 142 | case(LUT_INDEX) 143 | // Initial 144 | LCD_INTIAL+0: LUT_DATA <= 9'h038; 145 | LCD_INTIAL+1: LUT_DATA <= 9'h00C; 146 | LCD_INTIAL+2: LUT_DATA <= 9'h001; 147 | LCD_INTIAL+3: LUT_DATA <= 9'h006; 148 | LCD_INTIAL+4: LUT_DATA <= 9'h080; 149 | 150 | // Line 1 151 | LCD_LINE1+0: LUT_DATA <= 9'h141; // A 152 | LCD_LINE1+1: LUT_DATA <= 9'h143; // C 153 | LCD_LINE1+2: LUT_DATA <= 9'h143; // C 154 | LCD_LINE1+3: LUT_DATA <= 9'h145; // E 155 | LCD_LINE1+4: LUT_DATA <= 9'h153; // S 156 | LCD_LINE1+5: LUT_DATA <= 9'h153; // S 157 | 158 | LCD_LINE1+6: LUT_DATA <= 9'h120; // Space 159 | 160 | LCD_LINE1+7: LUT_DATA <= 9'h147; // G 161 | LCD_LINE1+8: LUT_DATA <= 9'h152; // R 162 | LCD_LINE1+9: LUT_DATA <= 9'h141; // A 163 | LCD_LINE1+10: LUT_DATA <= 9'h14E; // N 164 | LCD_LINE1+11: LUT_DATA <= 9'h154; // T 165 | LCD_LINE1+12: LUT_DATA <= 9'h145; // E 166 | LCD_LINE1+13: LUT_DATA <= 9'h144; // D 167 | 168 | LCD_LINE1+14: LUT_DATA <= 9'h120; // Fim 169 | endcase 170 | end 171 | end 172 | 173 | LCD_Controller u0 ( // Host Side 174 | .iDATA(mLCD_DATA), 175 | .iRS(mLCD_RS), 176 | .iStart(mLCD_Start), 177 | .oDone(mLCD_Done), 178 | .iCLK(iCLK), 179 | .iRST_N(iRST_N), 180 | // LCD Interface 181 | .LCD_DATA(LCD_DATA), 182 | .LCD_RW(LCD_RW), 183 | .LCD_EN(LCD_EN), 184 | .LCD_RS(LCD_RS) ); 185 | 186 | endmodule 187 | -------------------------------------------------------------------------------- /quartus/Safe.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2010 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 20 | # Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition 21 | # Date created = 15:24:40 April 29, 2019 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # Safe_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone II" 40 | set_global_assignment -name DEVICE EP2C35F672C6 41 | set_global_assignment -name TOP_LEVEL_ENTITY Safe 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2" 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:24:40 APRIL 29, 2019" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2" 45 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 46 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 47 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 48 | set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga 49 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 50 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 51 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 52 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 53 | set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" 54 | set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" 55 | set_global_assignment -name MISC_FILE "C:/Users/aluno/Downloads/Safe Project/Quartus/Safe.dpf" 56 | set_global_assignment -name USE_CONFIGURATION_DEVICE ON 57 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" 58 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 59 | set_location_assignment PIN_N25 -to SW[0] 60 | set_location_assignment PIN_N26 -to SW[1] 61 | set_location_assignment PIN_P25 -to SW[2] 62 | set_location_assignment PIN_AE14 -to SW[3] 63 | set_location_assignment PIN_AF14 -to SW[4] 64 | set_location_assignment PIN_AD13 -to SW[5] 65 | set_location_assignment PIN_AC13 -to SW[6] 66 | set_location_assignment PIN_C13 -to SW[7] 67 | set_location_assignment PIN_B13 -to SW[8] 68 | set_location_assignment PIN_A13 -to SW[9] 69 | set_location_assignment PIN_N1 -to SW[10] 70 | set_location_assignment PIN_P1 -to SW[11] 71 | set_location_assignment PIN_P2 -to SW[12] 72 | set_location_assignment PIN_T7 -to SW[13] 73 | set_location_assignment PIN_U3 -to SW[14] 74 | set_location_assignment PIN_U4 -to SW[15] 75 | set_location_assignment PIN_V1 -to SW[16] 76 | set_location_assignment PIN_AE23 -to LEDR 77 | set_location_assignment PIN_AE22 -to LEDG[0] 78 | set_location_assignment PIN_AF22 -to LEDG[1] 79 | set_location_assignment PIN_K4 -to LCD_RW 80 | set_location_assignment PIN_K1 -to LCD_RS 81 | set_location_assignment PIN_L4 -to LCD_ON 82 | set_location_assignment PIN_K3 -to LCD_EN 83 | set_location_assignment PIN_J1 -to LCD_DATA[0] 84 | set_location_assignment PIN_J2 -to LCD_DATA[1] 85 | set_location_assignment PIN_H1 -to LCD_DATA[2] 86 | set_location_assignment PIN_H2 -to LCD_DATA[3] 87 | set_location_assignment PIN_J4 -to LCD_DATA[4] 88 | set_location_assignment PIN_J3 -to LCD_DATA[5] 89 | set_location_assignment PIN_H4 -to LCD_DATA[6] 90 | set_location_assignment PIN_H3 -to LCD_DATA[7] 91 | set_location_assignment PIN_K2 -to LCD_BLON 92 | set_location_assignment PIN_G26 -to KEY[0] 93 | set_location_assignment PIN_N23 -to KEY[1] 94 | set_location_assignment PIN_K25 -to GPIO_O 95 | set_location_assignment PIN_K26 -to GPIO_I 96 | set_location_assignment PIN_N2 -to CLOCK_50 97 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" 98 | set_global_assignment -name MISC_FILE "C:/Users/aluno/Desktop/Projeto CL2/Quartus/Safe.dpf" 99 | set_location_assignment PIN_V2 -to SW[17] 100 | set_location_assignment PIN_W26 -to KEY[2] 101 | set_global_assignment -name VERILOG_FILE "../Safe Project/Servo_Controller.v" 102 | set_global_assignment -name VERILOG_FILE "../Safe Project/Safe.v" 103 | set_global_assignment -name VERILOG_FILE "../Safe Project/LCD_Reset_Delay.v" 104 | set_global_assignment -name VERILOG_FILE "../Safe Project/LCD_Controller.v" 105 | set_global_assignment -name VERILOG_FILE "../Safe Project/LCD_Print.v" 106 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /quartus/Safe.eda.rpt: -------------------------------------------------------------------------------- 1 | EDA Netlist Writer report for Safe 2 | Tue Apr 30 16:12:36 2019 3 | Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. EDA Netlist Writer Summary 11 | 3. Simulation Settings 12 | 4. Simulation Generated Files 13 | 5. EDA Netlist Writer Messages 14 | 15 | 16 | 17 | ---------------- 18 | ; Legal Notice ; 19 | ---------------- 20 | Copyright (C) 1991-2010 Altera Corporation 21 | Your use of Altera Corporation's design tools, logic functions 22 | and other software and tools, and its AMPP partner logic 23 | functions, and any output files from any of the foregoing 24 | (including device programming or simulation files), and any 25 | associated documentation or information are expressly subject 26 | to the terms and conditions of the Altera Program License 27 | Subscription Agreement, Altera MegaCore Function License 28 | Agreement, or other applicable license agreement, including, 29 | without limitation, that your use is for the sole purpose of 30 | programming logic devices manufactured by Altera and sold by 31 | Altera or its authorized distributors. Please refer to the 32 | applicable agreement for further details. 33 | 34 | 35 | 36 | +-------------------------------------------------------------------+ 37 | ; EDA Netlist Writer Summary ; 38 | +---------------------------+---------------------------------------+ 39 | ; EDA Netlist Writer Status ; Successful - Tue Apr 30 16:12:36 2019 ; 40 | ; Revision Name ; Safe ; 41 | ; Top-level Entity Name ; Safe ; 42 | ; Family ; Cyclone II ; 43 | ; Simulation Files Creation ; Successful ; 44 | +---------------------------+---------------------------------------+ 45 | 46 | 47 | +-------------------------------------------------------------------------------------------------------------------------------+ 48 | ; Simulation Settings ; 49 | +---------------------------------------------------------------------------------------------------+---------------------------+ 50 | ; Option ; Setting ; 51 | +---------------------------------------------------------------------------------------------------+---------------------------+ 52 | ; Tool Name ; ModelSim-Altera (Verilog) ; 53 | ; Generate netlist for functional simulation only ; Off ; 54 | ; Time scale ; 1 ps ; 55 | ; Truncate long hierarchy paths ; Off ; 56 | ; Map illegal HDL characters ; Off ; 57 | ; Flatten buses into individual nodes ; Off ; 58 | ; Maintain hierarchy ; Off ; 59 | ; Bring out device-wide set/reset signals as ports ; Off ; 60 | ; Enable glitch filtering ; Off ; 61 | ; Do not write top level VHDL entity ; Off ; 62 | ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; 63 | ; Architecture name in VHDL output netlist ; structure ; 64 | ; Generate third-party EDA tool command script for RTL functional simulation ; Off ; 65 | ; Generate third-party EDA tool command script for gate-level simulation ; Off ; 66 | +---------------------------------------------------------------------------------------------------+---------------------------+ 67 | 68 | 69 | +---------------------------------------------------------------------------+ 70 | ; Simulation Generated Files ; 71 | +---------------------------------------------------------------------------+ 72 | ; Generated Files ; 73 | +---------------------------------------------------------------------------+ 74 | ; C:/Users/aluno/Desktop/Projeto CL2/Quartus/simulation/modelsim/Safe.vo ; 75 | ; C:/Users/aluno/Desktop/Projeto CL2/Quartus/simulation/modelsim/Safe_v.sdo ; 76 | +---------------------------------------------------------------------------+ 77 | 78 | 79 | +-----------------------------+ 80 | ; EDA Netlist Writer Messages ; 81 | +-----------------------------+ 82 | Info: ******************************************************************* 83 | Info: Running Quartus II EDA Netlist Writer 84 | Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition 85 | Info: Processing started: Tue Apr 30 16:12:36 2019 86 | Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Safe -c Safe 87 | Info: Generated simulation netlist will be non-hierarchical because the design has SignalTap II partitions, termination control logic and/or a design partition that contains bidirectional ports 88 | Info: Generated files "Safe.vo" and "Safe_v.sdo" in directory "C:/Users/aluno/Desktop/Projeto CL2/Quartus/simulation/modelsim/" for EDA simulation tool 89 | Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings 90 | Info: Peak virtual memory: 181 megabytes 91 | Info: Processing ended: Tue Apr 30 16:12:36 2019 92 | Info: Elapsed time: 00:00:00 93 | Info: Total CPU time (on all processors): 00:00:00 94 | 95 | 96 | -------------------------------------------------------------------------------- /quartus/db/Safe.hier_info: -------------------------------------------------------------------------------- 1 | |Safe 2 | CLOCK_50 => CLOCK_50.IN3 3 | KEY[0] => always0.IN1 4 | KEY[0] => always0.IN1 5 | KEY[0] => always0.IN1 6 | KEY[1] => position.OUTPUTSELECT 7 | KEY[1] => position.OUTPUTSELECT 8 | KEY[1] => position.OUTPUTSELECT 9 | KEY[1] => position.OUTPUTSELECT 10 | KEY[1] => position.OUTPUTSELECT 11 | KEY[1] => position.OUTPUTSELECT 12 | KEY[1] => position.OUTPUTSELECT 13 | KEY[1] => position.OUTPUTSELECT 14 | KEY[1] => correctPass.OUTPUTSELECT 15 | KEY[1] => correctFacial.OUTPUTSELECT 16 | KEY[1] => message.OUTPUTSELECT 17 | KEY[1] => message.OUTPUTSELECT 18 | KEY[1] => message.OUTPUTSELECT 19 | KEY[1] => LUT_INDEX.OUTPUTSELECT 20 | KEY[1] => LUT_INDEX.OUTPUTSELECT 21 | KEY[1] => LUT_INDEX.OUTPUTSELECT 22 | KEY[1] => LUT_INDEX.OUTPUTSELECT 23 | KEY[1] => LUT_INDEX.OUTPUTSELECT 24 | KEY[1] => LUT_INDEX.OUTPUTSELECT 25 | KEY[1] => mLCD_ST.OUTPUTSELECT 26 | KEY[1] => mLCD_ST.OUTPUTSELECT 27 | KEY[1] => mLCD_ST.OUTPUTSELECT 28 | KEY[1] => mLCD_ST.OUTPUTSELECT 29 | KEY[1] => mDLY.OUTPUTSELECT 30 | KEY[1] => mDLY.OUTPUTSELECT 31 | KEY[1] => mDLY.OUTPUTSELECT 32 | KEY[1] => mDLY.OUTPUTSELECT 33 | KEY[1] => mDLY.OUTPUTSELECT 34 | KEY[1] => mDLY.OUTPUTSELECT 35 | KEY[1] => mDLY.OUTPUTSELECT 36 | KEY[1] => mDLY.OUTPUTSELECT 37 | KEY[1] => mDLY.OUTPUTSELECT 38 | KEY[1] => mDLY.OUTPUTSELECT 39 | KEY[1] => mDLY.OUTPUTSELECT 40 | KEY[1] => mDLY.OUTPUTSELECT 41 | KEY[1] => mDLY.OUTPUTSELECT 42 | KEY[1] => mDLY.OUTPUTSELECT 43 | KEY[1] => mDLY.OUTPUTSELECT 44 | KEY[1] => mDLY.OUTPUTSELECT 45 | KEY[1] => mDLY.OUTPUTSELECT 46 | KEY[1] => mDLY.OUTPUTSELECT 47 | KEY[1] => mLCD_Start.OUTPUTSELECT 48 | KEY[1] => mLCD_DATA.OUTPUTSELECT 49 | KEY[1] => mLCD_DATA.OUTPUTSELECT 50 | KEY[1] => mLCD_DATA.OUTPUTSELECT 51 | KEY[1] => mLCD_DATA.OUTPUTSELECT 52 | KEY[1] => mLCD_DATA.OUTPUTSELECT 53 | KEY[1] => mLCD_DATA.OUTPUTSELECT 54 | KEY[1] => mLCD_DATA.OUTPUTSELECT 55 | KEY[1] => mLCD_DATA.OUTPUTSELECT 56 | KEY[1] => mLCD_RS.OUTPUTSELECT 57 | KEY[2] => _.IN1 58 | SW[0] => Equal0.IN17 59 | SW[1] => Equal0.IN16 60 | SW[2] => Equal0.IN15 61 | SW[3] => Equal0.IN14 62 | SW[4] => Equal0.IN13 63 | SW[5] => Equal0.IN12 64 | SW[6] => Equal0.IN11 65 | SW[7] => Equal0.IN10 66 | SW[8] => Equal0.IN9 67 | SW[9] => Equal0.IN8 68 | SW[10] => Equal0.IN7 69 | SW[11] => Equal0.IN6 70 | SW[12] => Equal0.IN5 71 | SW[13] => Equal0.IN4 72 | SW[14] => Equal0.IN3 73 | SW[15] => Equal0.IN2 74 | SW[16] => Equal0.IN1 75 | SW[17] => Equal0.IN0 76 | LEDG[0] <= ledG[0].DB_MAX_OUTPUT_PORT_TYPE 77 | LEDG[1] <= ledG[1].DB_MAX_OUTPUT_PORT_TYPE 78 | LEDR <= WideNand0.DB_MAX_OUTPUT_PORT_TYPE 79 | GPIO_I => correctFacial.OUTPUTSELECT 80 | GPIO_O <= Servo_Controller:s0.servo 81 | LCD_ON <= 82 | LCD_BLON <= 83 | LCD_RW <= LCD_Controller:u0.LCD_RW 84 | LCD_EN <= LCD_Controller:u0.LCD_EN 85 | LCD_RS <= LCD_Controller:u0.LCD_RS 86 | LCD_DATA[0] <> LCD_Controller:u0.LCD_DATA 87 | LCD_DATA[1] <> LCD_Controller:u0.LCD_DATA 88 | LCD_DATA[2] <> LCD_Controller:u0.LCD_DATA 89 | LCD_DATA[3] <> LCD_Controller:u0.LCD_DATA 90 | LCD_DATA[4] <> LCD_Controller:u0.LCD_DATA 91 | LCD_DATA[5] <> LCD_Controller:u0.LCD_DATA 92 | LCD_DATA[6] <> LCD_Controller:u0.LCD_DATA 93 | LCD_DATA[7] <> LCD_Controller:u0.LCD_DATA 94 | 95 | 96 | |Safe|Reset_Delay:r0 97 | iCLK => oRESET~reg0.CLK 98 | iCLK => Cont[0].CLK 99 | iCLK => Cont[1].CLK 100 | iCLK => Cont[2].CLK 101 | iCLK => Cont[3].CLK 102 | iCLK => Cont[4].CLK 103 | iCLK => Cont[5].CLK 104 | iCLK => Cont[6].CLK 105 | iCLK => Cont[7].CLK 106 | iCLK => Cont[8].CLK 107 | iCLK => Cont[9].CLK 108 | iCLK => Cont[10].CLK 109 | iCLK => Cont[11].CLK 110 | iCLK => Cont[12].CLK 111 | iCLK => Cont[13].CLK 112 | iCLK => Cont[14].CLK 113 | iCLK => Cont[15].CLK 114 | iCLK => Cont[16].CLK 115 | iCLK => Cont[17].CLK 116 | iCLK => Cont[18].CLK 117 | iCLK => Cont[19].CLK 118 | oRESET <= oRESET~reg0.DB_MAX_OUTPUT_PORT_TYPE 119 | 120 | 121 | |Safe|LCD_Controller:u0 122 | iDATA[0] => LCD_DATA[0].DATAIN 123 | iDATA[1] => LCD_DATA[1].DATAIN 124 | iDATA[2] => LCD_DATA[2].DATAIN 125 | iDATA[3] => LCD_DATA[3].DATAIN 126 | iDATA[4] => LCD_DATA[4].DATAIN 127 | iDATA[5] => LCD_DATA[5].DATAIN 128 | iDATA[6] => LCD_DATA[6].DATAIN 129 | iDATA[7] => LCD_DATA[7].DATAIN 130 | iRS => LCD_RS.DATAIN 131 | iStart => preStart.DATAIN 132 | iStart => Equal0.IN0 133 | oDone <= oDone~reg0.DB_MAX_OUTPUT_PORT_TYPE 134 | iCLK => Cont[0].CLK 135 | iCLK => Cont[1].CLK 136 | iCLK => Cont[2].CLK 137 | iCLK => Cont[3].CLK 138 | iCLK => Cont[4].CLK 139 | iCLK => mStart.CLK 140 | iCLK => preStart.CLK 141 | iCLK => LCD_EN~reg0.CLK 142 | iCLK => oDone~reg0.CLK 143 | iCLK => ST~5.DATAIN 144 | iRST_N => Cont[0].ACLR 145 | iRST_N => Cont[1].ACLR 146 | iRST_N => Cont[2].ACLR 147 | iRST_N => Cont[3].ACLR 148 | iRST_N => Cont[4].ACLR 149 | iRST_N => mStart.ACLR 150 | iRST_N => preStart.ACLR 151 | iRST_N => LCD_EN~reg0.ACLR 152 | iRST_N => oDone~reg0.ACLR 153 | iRST_N => ST~7.DATAIN 154 | LCD_DATA[0] <= iDATA[0].DB_MAX_OUTPUT_PORT_TYPE 155 | LCD_DATA[1] <= iDATA[1].DB_MAX_OUTPUT_PORT_TYPE 156 | LCD_DATA[2] <= iDATA[2].DB_MAX_OUTPUT_PORT_TYPE 157 | LCD_DATA[3] <= iDATA[3].DB_MAX_OUTPUT_PORT_TYPE 158 | LCD_DATA[4] <= iDATA[4].DB_MAX_OUTPUT_PORT_TYPE 159 | LCD_DATA[5] <= iDATA[5].DB_MAX_OUTPUT_PORT_TYPE 160 | LCD_DATA[6] <= iDATA[6].DB_MAX_OUTPUT_PORT_TYPE 161 | LCD_DATA[7] <= iDATA[7].DB_MAX_OUTPUT_PORT_TYPE 162 | LCD_RW <= 163 | LCD_EN <= LCD_EN~reg0.DB_MAX_OUTPUT_PORT_TYPE 164 | LCD_RS <= iRS.DB_MAX_OUTPUT_PORT_TYPE 165 | 166 | 167 | |Safe|Servo_Controller:s0 168 | clk => pwm_q.CLK 169 | clk => ctr_q[0].CLK 170 | clk => ctr_q[1].CLK 171 | clk => ctr_q[2].CLK 172 | clk => ctr_q[3].CLK 173 | clk => ctr_q[4].CLK 174 | clk => ctr_q[5].CLK 175 | clk => ctr_q[6].CLK 176 | clk => ctr_q[7].CLK 177 | clk => ctr_q[8].CLK 178 | clk => ctr_q[9].CLK 179 | clk => ctr_q[10].CLK 180 | clk => ctr_q[11].CLK 181 | clk => ctr_q[12].CLK 182 | clk => ctr_q[13].CLK 183 | clk => ctr_q[14].CLK 184 | clk => ctr_q[15].CLK 185 | clk => ctr_q[16].CLK 186 | clk => ctr_q[17].CLK 187 | clk => ctr_q[18].CLK 188 | clk => ctr_q[19].CLK 189 | rst => ctr_q.OUTPUTSELECT 190 | rst => ctr_q.OUTPUTSELECT 191 | rst => ctr_q.OUTPUTSELECT 192 | rst => ctr_q.OUTPUTSELECT 193 | rst => ctr_q.OUTPUTSELECT 194 | rst => ctr_q.OUTPUTSELECT 195 | rst => ctr_q.OUTPUTSELECT 196 | rst => ctr_q.OUTPUTSELECT 197 | rst => ctr_q.OUTPUTSELECT 198 | rst => ctr_q.OUTPUTSELECT 199 | rst => ctr_q.OUTPUTSELECT 200 | rst => ctr_q.OUTPUTSELECT 201 | rst => ctr_q.OUTPUTSELECT 202 | rst => ctr_q.OUTPUTSELECT 203 | rst => ctr_q.OUTPUTSELECT 204 | rst => ctr_q.OUTPUTSELECT 205 | rst => ctr_q.OUTPUTSELECT 206 | rst => ctr_q.OUTPUTSELECT 207 | rst => ctr_q.OUTPUTSELECT 208 | rst => ctr_q.OUTPUTSELECT 209 | position[0] => Add1.IN16 210 | position[1] => Add1.IN15 211 | position[2] => Add1.IN14 212 | position[3] => Add1.IN13 213 | position[4] => Add1.IN12 214 | position[5] => Add1.IN11 215 | position[6] => Add1.IN10 216 | position[7] => Add1.IN9 217 | servo <= pwm_q.DB_MAX_OUTPUT_PORT_TYPE 218 | 219 | 220 | -------------------------------------------------------------------------------- /src/Safe.v: -------------------------------------------------------------------------------- 1 | module Safe( 2 | input CLOCK_50, // 50 MHz clock 3 | input [2:0] KEY, // 2 Pushbuttons 4 | input [17:0] SW, // 18 Switches 5 | output [1:0]LEDG, // LEDs Green 6 | output LEDR, // LED Red 7 | 8 | //GPIO Connections 9 | input GPIO_I, 10 | output GPIO_O, 11 | 12 | //LCD Module 16X2 13 | output LCD_ON, // LCD Power ON/OFF 14 | output LCD_BLON, // LCD Back Light ON/OFF 15 | output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read 16 | output LCD_EN, // LCD Enable 17 | output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data 18 | inout [7:0] LCD_DATA // LCD Data bus 8 bits 19 | ); 20 | 21 | //-----------------------VARIABLES_INICIALIZATION----------------------------- 22 | 23 | //--------------===============LCD=================----------------- 24 | // Reset delay gives some time for peripherals to initialize 25 | wire DLY_RST; 26 | Reset_Delay r0(.iCLK(CLOCK_50),.oRESET(DLY_RST)); 27 | 28 | //----Turn LCD ON---- 29 | assign LCD_ON = 1'b1; 30 | assign LCD_BLON = 1'b1; 31 | //------------------- 32 | 33 | 34 | // Internal Wires/Registers 35 | reg [5:0] LUT_INDEX; 36 | reg [8:0] LUT_DATA; 37 | reg [5:0] mLCD_ST; 38 | reg [17:0] mDLY; 39 | reg mLCD_Start; 40 | reg [7:0] mLCD_DATA; 41 | reg mLCD_RS; 42 | wire mLCD_Done; 43 | 44 | parameter LCD_INTIAL = 0; 45 | parameter LCD_LINE1 = 5; 46 | parameter LCD_CH_LINE = LCD_LINE1+16; 47 | parameter LCD_LINE2 = LCD_LINE1+16+1; 48 | parameter LUT_SIZE = LCD_LINE1+32+1; 49 | 50 | //--------------===================================----------------- 51 | 52 | //reg servo = 1'b0; 53 | //assign GPIO_O = servo; 54 | reg [7:0]position = 0; 55 | 56 | reg [1:0]ledG = 2'b00; 57 | 58 | assign LEDG = ledG; 59 | assign LEDR = ~&ledG; 60 | 61 | reg correctPass = 1'b0; 62 | reg correctFacial = 1'b0; 63 | 64 | reg [1:0]message = 2'b00; 65 | 66 | parameter PASSWORD = 18'b111111111111111111; 67 | 68 | //----------------------------------------------------------------------------- 69 | 70 | always @ (posedge CLOCK_50) begin 71 | if(!DLY_RST) 72 | begin 73 | LUT_INDEX <= 0; 74 | mLCD_ST <= 0; 75 | mDLY <= 0; 76 | mLCD_Start <= 0; 77 | mLCD_DATA <= 0; 78 | mLCD_RS <= 0; 79 | end 80 | else 81 | begin 82 | if(LUT_INDEX < LUT_SIZE) 83 | begin 84 | case(mLCD_ST) 85 | 0: begin 86 | mLCD_DATA <= LUT_DATA[7:0]; 87 | mLCD_RS <= LUT_DATA[8]; 88 | mLCD_Start <= 1; 89 | mLCD_ST <= 1; 90 | end 91 | 1: begin 92 | if(mLCD_Done) 93 | begin 94 | mLCD_Start <= 0; 95 | mLCD_ST <= 2; 96 | end 97 | end 98 | 2: begin 99 | if(mDLY<18'h3FFFE) 100 | mDLY <= mDLY+1; 101 | else 102 | begin 103 | mDLY <= 0; 104 | mLCD_ST <= 3; 105 | end 106 | end 107 | 3: begin 108 | LUT_INDEX <= LUT_INDEX+1; 109 | mLCD_ST <= 0; 110 | end 111 | endcase 112 | end 113 | end 114 | 115 | if(!KEY[0] && SW == PASSWORD) 116 | correctPass <= 1'b1; 117 | 118 | if(GPIO_I == 1'b0) 119 | correctFacial <= 1'b1; 120 | 121 | ledG[1] <= correctFacial; 122 | ledG[0] <= correctPass; 123 | 124 | if(!KEY[0] && (SW != PASSWORD || !correctFacial) )begin 125 | message <= 2'b01; 126 | LUT_INDEX <= 0; 127 | mLCD_ST <= 0; 128 | mDLY <= 0; 129 | mLCD_Start <= 0; 130 | mLCD_DATA <= 0; 131 | mLCD_RS <= 0; 132 | end 133 | 134 | 135 | if(!KEY[0] && (correctFacial && correctPass))begin 136 | //servo <= 1'b1; 137 | position <= 8'b11001000; 138 | message <= 2'b10; 139 | LUT_INDEX <= 0; 140 | mLCD_ST <= 0; 141 | mDLY <= 0; 142 | mLCD_Start <= 0; 143 | mLCD_DATA <= 0; 144 | mLCD_RS <= 0; 145 | end 146 | 147 | if(!KEY[1])begin 148 | //servo <= 1'b0; 149 | position <= 0; 150 | correctPass <= 1'b0; 151 | correctFacial <= 1'b0; 152 | message <= 2'b00; 153 | LUT_INDEX <= 0; 154 | mLCD_ST <= 0; 155 | mDLY <= 0; 156 | mLCD_Start <= 0; 157 | mLCD_DATA <= 0; 158 | mLCD_RS <= 0; 159 | end 160 | 161 | if(message == 2'b00) begin 162 | case(LUT_INDEX) 163 | // Initial 164 | LCD_INTIAL+0: LUT_DATA <= 9'h038; 165 | LCD_INTIAL+1: LUT_DATA <= 9'h00C; 166 | LCD_INTIAL+2: LUT_DATA <= 9'h001; 167 | LCD_INTIAL+3: LUT_DATA <= 9'h006; 168 | LCD_INTIAL+4: LUT_DATA <= 9'h080; 169 | 170 | // Line 1 171 | LCD_LINE1+14: LUT_DATA <= 9'h120; // End 172 | endcase 173 | end 174 | 175 | 176 | if(message == 2'b01) begin 177 | case(LUT_INDEX) 178 | // Initial 179 | LCD_INTIAL+0: LUT_DATA <= 9'h038; 180 | LCD_INTIAL+1: LUT_DATA <= 9'h00C; 181 | LCD_INTIAL+2: LUT_DATA <= 9'h001; 182 | LCD_INTIAL+3: LUT_DATA <= 9'h006; 183 | LCD_INTIAL+4: LUT_DATA <= 9'h080; 184 | 185 | 186 | // Line 1 187 | LCD_LINE1+0: LUT_DATA <= 9'h141; // A 188 | LCD_LINE1+1: LUT_DATA <= 9'h143; // C 189 | LCD_LINE1+2: LUT_DATA <= 9'h143; // C 190 | LCD_LINE1+3: LUT_DATA <= 9'h145; // E 191 | LCD_LINE1+4: LUT_DATA <= 9'h153; // S 192 | LCD_LINE1+5: LUT_DATA <= 9'h153; // S 193 | 194 | LCD_LINE1+6: LUT_DATA <= 9'h120; // Space 195 | 196 | // Line 1 197 | LCD_LINE1+7: LUT_DATA <= 9'h144; // D 198 | LCD_LINE1+8: LUT_DATA <= 9'h145; // E 199 | LCD_LINE1+9: LUT_DATA <= 9'h14E; // N 200 | LCD_LINE1+10: LUT_DATA <= 9'h149; // I 201 | LCD_LINE1+11: LUT_DATA <= 9'h145; // E 202 | LCD_LINE1+12: LUT_DATA <= 9'h144; // D 203 | 204 | LCD_LINE1+13: LUT_DATA <= 9'h120; // End 205 | endcase 206 | end 207 | 208 | 209 | if(message == 2'b10) begin 210 | case(LUT_INDEX) 211 | // Initial 212 | LCD_INTIAL+0: LUT_DATA <= 9'h038; 213 | LCD_INTIAL+1: LUT_DATA <= 9'h00C; 214 | LCD_INTIAL+2: LUT_DATA <= 9'h001; 215 | LCD_INTIAL+3: LUT_DATA <= 9'h006; 216 | LCD_INTIAL+4: LUT_DATA <= 9'h080; 217 | 218 | // Line 1 219 | LCD_LINE1+0: LUT_DATA <= 9'h141; // A 220 | LCD_LINE1+1: LUT_DATA <= 9'h143; // C 221 | LCD_LINE1+2: LUT_DATA <= 9'h143; // C 222 | LCD_LINE1+3: LUT_DATA <= 9'h145; // E 223 | LCD_LINE1+4: LUT_DATA <= 9'h153; // S 224 | LCD_LINE1+5: LUT_DATA <= 9'h153; // S 225 | 226 | LCD_LINE1+6: LUT_DATA <= 9'h120; // Space 227 | 228 | LCD_LINE1+7: LUT_DATA <= 9'h147; // G 229 | LCD_LINE1+8: LUT_DATA <= 9'h152; // R 230 | LCD_LINE1+9: LUT_DATA <= 9'h141; // A 231 | LCD_LINE1+10: LUT_DATA <= 9'h14E; // N 232 | LCD_LINE1+11: LUT_DATA <= 9'h154; // T 233 | LCD_LINE1+12: LUT_DATA <= 9'h145; // E 234 | LCD_LINE1+13: LUT_DATA <= 9'h144; // D 235 | 236 | LCD_LINE1+14: LUT_DATA <= 9'h120; // End 237 | endcase 238 | end 239 | end 240 | 241 | 242 | LCD_Controller u0 ( // Host Side 243 | .iDATA(mLCD_DATA), 244 | .iRS(mLCD_RS), 245 | .iStart(mLCD_Start), 246 | .oDone(mLCD_Done), 247 | .iCLK(CLOCK_50), 248 | .iRST_N(DLY_RST), 249 | // LCD Interface 250 | .LCD_DATA(LCD_DATA), 251 | .LCD_RW(LCD_RW), 252 | .LCD_EN(LCD_EN), 253 | .LCD_RS(LCD_RS) ); 254 | 255 | Servo_Controller s0( 256 | .clk(CLOCK_50), 257 | .rst(!KEY[2]), 258 | .position(position), 259 | .servo(GPIO_O) 260 | ); 261 | 262 | endmodule 263 | -------------------------------------------------------------------------------- /quartus/Safe.asm.rpt: -------------------------------------------------------------------------------- 1 | Assembler report for Safe 2 | Tue Apr 30 16:12:34 2019 3 | Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Assembler Summary 11 | 3. Assembler Settings 12 | 4. Assembler Generated Files 13 | 5. Assembler Device Options: C:/Users/aluno/Desktop/Projeto CL2/Quartus/Safe.sof 14 | 6. Assembler Device Options: C:/Users/aluno/Desktop/Projeto CL2/Quartus/Safe.pof 15 | 7. Assembler Messages 16 | 17 | 18 | 19 | ---------------- 20 | ; Legal Notice ; 21 | ---------------- 22 | Copyright (C) 1991-2010 Altera Corporation 23 | Your use of Altera Corporation's design tools, logic functions 24 | and other software and tools, and its AMPP partner logic 25 | functions, and any output files from any of the foregoing 26 | (including device programming or simulation files), and any 27 | associated documentation or information are expressly subject 28 | to the terms and conditions of the Altera Program License 29 | Subscription Agreement, Altera MegaCore Function License 30 | Agreement, or other applicable license agreement, including, 31 | without limitation, that your use is for the sole purpose of 32 | programming logic devices manufactured by Altera and sold by 33 | Altera or its authorized distributors. Please refer to the 34 | applicable agreement for further details. 35 | 36 | 37 | 38 | +---------------------------------------------------------------+ 39 | ; Assembler Summary ; 40 | +-----------------------+---------------------------------------+ 41 | ; Assembler Status ; Successful - Tue Apr 30 16:12:34 2019 ; 42 | ; Revision Name ; Safe ; 43 | ; Top-level Entity Name ; Safe ; 44 | ; Family ; Cyclone II ; 45 | ; Device ; EP2C35F672C6 ; 46 | +-----------------------+---------------------------------------+ 47 | 48 | 49 | +--------------------------------------------------------------------------------------------------------+ 50 | ; Assembler Settings ; 51 | +-----------------------------------------------------------------------------+----------+---------------+ 52 | ; Option ; Setting ; Default Value ; 53 | +-----------------------------------------------------------------------------+----------+---------------+ 54 | ; Use smart compilation ; Off ; Off ; 55 | ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; 56 | ; Enable compact report table ; Off ; Off ; 57 | ; Generate compressed bitstreams ; On ; On ; 58 | ; Compression mode ; Off ; Off ; 59 | ; Clock source for configuration device ; Internal ; Internal ; 60 | ; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; 61 | ; Divide clock frequency by ; 1 ; 1 ; 62 | ; Auto user code ; Off ; Off ; 63 | ; Use configuration device ; On ; On ; 64 | ; Configuration device ; Auto ; Auto ; 65 | ; Configuration device auto user code ; Off ; Off ; 66 | ; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; 67 | ; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; 68 | ; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; 69 | ; Hexadecimal Output File start address ; 0 ; 0 ; 70 | ; Hexadecimal Output File count direction ; Up ; Up ; 71 | ; Release clears before tri-states ; Off ; Off ; 72 | ; Auto-restart configuration after error ; On ; On ; 73 | ; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; 74 | ; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; 75 | ; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; 76 | ; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; 77 | ; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; 78 | +-----------------------------------------------------------------------------+----------+---------------+ 79 | 80 | 81 | +-----------------------------------------------------+ 82 | ; Assembler Generated Files ; 83 | +-----------------------------------------------------+ 84 | ; File Name ; 85 | +-----------------------------------------------------+ 86 | ; C:/Users/aluno/Desktop/Projeto CL2/Quartus/Safe.sof ; 87 | ; C:/Users/aluno/Desktop/Projeto CL2/Quartus/Safe.pof ; 88 | +-----------------------------------------------------+ 89 | 90 | 91 | +-------------------------------------------------------------------------------+ 92 | ; Assembler Device Options: C:/Users/aluno/Desktop/Projeto CL2/Quartus/Safe.sof ; 93 | +----------------+--------------------------------------------------------------+ 94 | ; Option ; Setting ; 95 | +----------------+--------------------------------------------------------------+ 96 | ; Device ; EP2C35F672C6 ; 97 | ; JTAG usercode ; 0xFFFFFFFF ; 98 | ; Checksum ; 0x003064D0 ; 99 | +----------------+--------------------------------------------------------------+ 100 | 101 | 102 | +-------------------------------------------------------------------------------+ 103 | ; Assembler Device Options: C:/Users/aluno/Desktop/Projeto CL2/Quartus/Safe.pof ; 104 | +--------------------+----------------------------------------------------------+ 105 | ; Option ; Setting ; 106 | +--------------------+----------------------------------------------------------+ 107 | ; Device ; EPCS16 ; 108 | ; JTAG usercode ; 0x00000000 ; 109 | ; Checksum ; 0x1C72D498 ; 110 | ; Compression Ratio ; 3 ; 111 | +--------------------+----------------------------------------------------------+ 112 | 113 | 114 | +--------------------+ 115 | ; Assembler Messages ; 116 | +--------------------+ 117 | Info: ******************************************************************* 118 | Info: Running Quartus II Assembler 119 | Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition 120 | Info: Processing started: Tue Apr 30 16:12:32 2019 121 | Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Safe -c Safe 122 | Info: Writing out detailed assembly data for power analysis 123 | Info: Assembler is generating device programming files 124 | Info: Quartus II Assembler was successful. 0 errors, 0 warnings 125 | Info: Peak virtual memory: 250 megabytes 126 | Info: Processing ended: Tue Apr 30 16:12:34 2019 127 | Info: Elapsed time: 00:00:02 128 | Info: Total CPU time (on all processors): 00:00:02 129 | 130 | 131 | -------------------------------------------------------------------------------- /quartus/Safe.flow.rpt: -------------------------------------------------------------------------------- 1 | Flow report for Safe 2 | Tue Apr 30 16:12:36 2019 3 | Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Flow Summary 11 | 3. Flow Settings 12 | 4. Flow Non-Default Global Settings 13 | 5. Flow Elapsed Time 14 | 6. Flow OS Summary 15 | 7. Flow Log 16 | 17 | 18 | 19 | ---------------- 20 | ; Legal Notice ; 21 | ---------------- 22 | Copyright (C) 1991-2010 Altera Corporation 23 | Your use of Altera Corporation's design tools, logic functions 24 | and other software and tools, and its AMPP partner logic 25 | functions, and any output files from any of the foregoing 26 | (including device programming or simulation files), and any 27 | associated documentation or information are expressly subject 28 | to the terms and conditions of the Altera Program License 29 | Subscription Agreement, Altera MegaCore Function License 30 | Agreement, or other applicable license agreement, including, 31 | without limitation, that your use is for the sole purpose of 32 | programming logic devices manufactured by Altera and sold by 33 | Altera or its authorized distributors. Please refer to the 34 | applicable agreement for further details. 35 | 36 | 37 | 38 | +-----------------------------------------------------------------------------------+ 39 | ; Flow Summary ; 40 | +------------------------------------+----------------------------------------------+ 41 | ; Flow Status ; Successful - Tue Apr 30 16:12:36 2019 ; 42 | ; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; 43 | ; Revision Name ; Safe ; 44 | ; Top-level Entity Name ; Safe ; 45 | ; Family ; Cyclone II ; 46 | ; Device ; EP2C35F672C6 ; 47 | ; Timing Models ; Final ; 48 | ; Met timing requirements ; Yes ; 49 | ; Total logic elements ; 207 / 33,216 ( < 1 % ) ; 50 | ; Total combinational functions ; 206 / 33,216 ( < 1 % ) ; 51 | ; Dedicated logic registers ; 110 / 33,216 ( < 1 % ) ; 52 | ; Total registers ; 110 ; 53 | ; Total pins ; 40 / 475 ( 8 % ) ; 54 | ; Total virtual pins ; 0 ; 55 | ; Total memory bits ; 0 / 483,840 ( 0 % ) ; 56 | ; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ; 57 | ; Total PLLs ; 0 / 4 ( 0 % ) ; 58 | +------------------------------------+----------------------------------------------+ 59 | 60 | 61 | +-----------------------------------------+ 62 | ; Flow Settings ; 63 | +-------------------+---------------------+ 64 | ; Option ; Setting ; 65 | +-------------------+---------------------+ 66 | ; Start date & time ; 04/30/2019 16:12:25 ; 67 | ; Main task ; Compilation ; 68 | ; Revision Name ; Safe ; 69 | +-------------------+---------------------+ 70 | 71 | 72 | +--------------------------------------------------------------------------------------------------------------------------------------------+ 73 | ; Flow Non-Default Global Settings ; 74 | +------------------------------------+--------------------------------------------------------+---------------+-------------+----------------+ 75 | ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; 76 | +------------------------------------+--------------------------------------------------------+---------------+-------------+----------------+ 77 | ; COMPILER_SIGNATURE_ID ; 176231577066004.155665154506728 ; -- ; -- ; -- ; 78 | ; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; 79 | ; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; 80 | ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; 81 | ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; 82 | ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; 83 | ; MISC_FILE ; C:/Users/aluno/Downloads/Safe Project/Quartus/Safe.dpf ; -- ; -- ; -- ; 84 | ; MISC_FILE ; C:/Users/aluno/Desktop/Projeto CL2/Quartus/Safe.dpf ; -- ; -- ; -- ; 85 | ; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; 86 | ; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; 87 | ; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; 88 | +------------------------------------+--------------------------------------------------------+---------------+-------------+----------------+ 89 | 90 | 91 | +-----------------------------------------------------------------------------------------------------------------------------+ 92 | ; Flow Elapsed Time ; 93 | +-------------------------+--------------+-------------------------+---------------------+------------------------------------+ 94 | ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; 95 | +-------------------------+--------------+-------------------------+---------------------+------------------------------------+ 96 | ; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 211 MB ; 00:00:01 ; 97 | ; Fitter ; 00:00:04 ; 1.0 ; 265 MB ; 00:00:05 ; 98 | ; Assembler ; 00:00:02 ; 1.0 ; 250 MB ; 00:00:02 ; 99 | ; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 156 MB ; 00:00:00 ; 100 | ; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 168 MB ; 00:00:00 ; 101 | ; Total ; 00:00:07 ; -- ; -- ; 00:00:08 ; 102 | +-------------------------+--------------+-------------------------+---------------------+------------------------------------+ 103 | 104 | 105 | +------------------------------------------------------------------------------------------+ 106 | ; Flow OS Summary ; 107 | +-------------------------+------------------+---------------+------------+----------------+ 108 | ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; 109 | +-------------------------+------------------+---------------+------------+----------------+ 110 | ; Analysis & Synthesis ; CI-HP ; Windows Vista ; 6.1 ; x86_64 ; 111 | ; Fitter ; CI-HP ; Windows Vista ; 6.1 ; x86_64 ; 112 | ; Assembler ; CI-HP ; Windows Vista ; 6.1 ; x86_64 ; 113 | ; Classic Timing Analyzer ; CI-HP ; Windows Vista ; 6.1 ; x86_64 ; 114 | ; EDA Netlist Writer ; CI-HP ; Windows Vista ; 6.1 ; x86_64 ; 115 | +-------------------------+------------------+---------------+------------+----------------+ 116 | 117 | 118 | ------------ 119 | ; Flow Log ; 120 | ------------ 121 | quartus_map --read_settings_files=on --write_settings_files=off Safe -c Safe 122 | quartus_fit --read_settings_files=off --write_settings_files=off Safe -c Safe 123 | quartus_asm --read_settings_files=off --write_settings_files=off Safe -c Safe 124 | quartus_tan --read_settings_files=off --write_settings_files=off Safe -c Safe --timing_analysis_only 125 | quartus_eda --read_settings_files=off --write_settings_files=off Safe -c Safe 126 | 127 | 128 | 129 | -------------------------------------------------------------------------------- /quartus/db/prev_cmp_Safe.map.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 30 16:10:54 2019 " "Info: Processing started: Tue Apr 30 16:10:54 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Safe -c Safe " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Safe -c Safe" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} 4 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/aluno/desktop/projeto cl2/safe project/servo.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/servo.v" { { "Info" "ISGN_ENTITY_NAME" "1 Servo_Controller " "Info: Found entity 1: Servo_Controller" { } { { "../Safe Project/Servo.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Servo.v" 10 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} 5 | { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "LEDG ledG Safe.v(5) " "Info (10281): Verilog HDL Declaration information at Safe.v(5): object \"LEDG\" differs only in case from object \"ledG\" in the same scope" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 5 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0 -1} 6 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/aluno/desktop/projeto cl2/safe project/safe.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/safe.v" { { "Info" "ISGN_ENTITY_NAME" "1 Safe " "Info: Found entity 1: Safe" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} 7 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/aluno/desktop/projeto cl2/safe project/lcd_reset_delay.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/lcd_reset_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 Reset_Delay " "Info: Found entity 1: Reset_Delay" { } { { "../Safe Project/LCD_Reset_Delay.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/LCD_Reset_Delay.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} 8 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/aluno/desktop/projeto cl2/safe project/lcd_controller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/lcd_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_Controller " "Info: Found entity 1: LCD_Controller" { } { { "../Safe Project/LCD_Controller.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/LCD_Controller.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} 9 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/aluno/desktop/projeto cl2/safe project/lcd_print.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/lcd_print.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_Print " "Info: Found entity 1: LCD_Print" { } { { "../Safe Project/LCD_Print.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/LCD_Print.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} 10 | { "Info" "ISGN_START_ELABORATION_TOP" "Safe " "Info: Elaborating entity \"Safe\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} 11 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 Safe.v(100) " "Warning (10230): Verilog HDL assignment warning at Safe.v(100): truncated value with size 32 to match size of target (18)" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1} 12 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 Safe.v(108) " "Warning (10230): Verilog HDL assignment warning at Safe.v(108): truncated value with size 32 to match size of target (6)" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 108 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1} 13 | { "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay Reset_Delay:r0 " "Info: Elaborating entity \"Reset_Delay\" for hierarchy \"Reset_Delay:r0\"" { } { { "../Safe Project/Safe.v" "r0" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 26 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} 14 | { "Info" "ISGN_START_ELABORATION_HIERARCHY" "LCD_Controller LCD_Controller:u0 " "Info: Elaborating entity \"LCD_Controller\" for hierarchy \"LCD_Controller:u0\"" { } { { "../Safe Project/Safe.v" "u0" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 253 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} 15 | { "Info" "ISGN_START_ELABORATION_HIERARCHY" "Servo_Controller Servo_Controller:s0 " "Info: Elaborating entity \"Servo_Controller\" for hierarchy \"Servo_Controller:s0\"" { } { { "../Safe Project/Safe.v" "s0" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 260 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} 16 | { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "Warning: The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[0\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[0\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[1\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[1\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[2\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[2\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[3\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[3\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[4\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[4\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[5\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[5\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[6\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[6\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[7\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[7\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} } { } 0 0 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "" 0 -1} 17 | { "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[0\]~synth " "Warning: Node \"LCD_DATA\[0\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[1\]~synth " "Warning: Node \"LCD_DATA\[1\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[2\]~synth " "Warning: Node \"LCD_DATA\[2\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[3\]~synth " "Warning: Node \"LCD_DATA\[3\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[4\]~synth " "Warning: Node \"LCD_DATA\[4\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[5\]~synth " "Warning: Node \"LCD_DATA\[5\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[6\]~synth " "Warning: Node \"LCD_DATA\[6\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[7\]~synth " "Warning: Node \"LCD_DATA\[7\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0 -1} 18 | { "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_ON VCC " "Warning (13410): Pin \"LCD_ON\" is stuck at VCC" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 13 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_BLON VCC " "Warning (13410): Pin \"LCD_BLON\" is stuck at VCC" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 14 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_RW GND " "Warning (13410): Pin \"LCD_RW\" is stuck at GND" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1} 19 | { "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "8 8 " "Info: 8 registers lost all their fanouts during netlist optimizations. The first 8 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mLCD_ST~6 " "Info: Register \"mLCD_ST~6\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mLCD_ST~7 " "Info: Register \"mLCD_ST~7\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mLCD_ST~8 " "Info: Register \"mLCD_ST~8\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mLCD_ST~9 " "Info: Register \"mLCD_ST~9\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mLCD_ST~10 " "Info: Register \"mLCD_ST~10\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mLCD_ST~11 " "Info: Register \"mLCD_ST~11\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "LCD_Controller:u0\|ST~8 " "Info: Register \"LCD_Controller:u0\|ST~8\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "LCD_Controller:u0\|ST~9 " "Info: Register \"LCD_Controller:u0\|ST~9\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1} 20 | { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/aluno/Desktop/Projeto CL2/Quartus/Safe.map.smsg " "Info: Generated suppressed messages file C:/Users/aluno/Desktop/Projeto CL2/Quartus/Safe.map.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} 21 | { "Info" "ICUT_CUT_TM_SUMMARY" "249 " "Info: Implemented 249 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "23 " "Info: Implemented 23 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" { } { } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "209 " "Info: Implemented 209 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} 22 | { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 24 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "211 " "Info: Peak virtual memory: 211 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 30 16:10:55 2019 " "Info: Processing ended: Tue Apr 30 16:10:55 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} 23 | -------------------------------------------------------------------------------- /quartus/db/Safe.map.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 30 16:12:25 2019 " "Info: Processing started: Tue Apr 30 16:12:25 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Safe -c Safe " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Safe -c Safe" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} 4 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/aluno/desktop/projeto cl2/safe project/servo_controller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/servo_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 Servo_Controller " "Info: Found entity 1: Servo_Controller" { } { { "../Safe Project/Servo_Controller.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Servo_Controller.v" 10 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} 5 | { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "LEDG ledG Safe.v(5) " "Info (10281): Verilog HDL Declaration information at Safe.v(5): object \"LEDG\" differs only in case from object \"ledG\" in the same scope" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 5 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0 -1} 6 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/aluno/desktop/projeto cl2/safe project/safe.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/safe.v" { { "Info" "ISGN_ENTITY_NAME" "1 Safe " "Info: Found entity 1: Safe" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} 7 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/aluno/desktop/projeto cl2/safe project/lcd_reset_delay.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/lcd_reset_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 Reset_Delay " "Info: Found entity 1: Reset_Delay" { } { { "../Safe Project/LCD_Reset_Delay.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/LCD_Reset_Delay.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} 8 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/aluno/desktop/projeto cl2/safe project/lcd_controller.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/lcd_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_Controller " "Info: Found entity 1: LCD_Controller" { } { { "../Safe Project/LCD_Controller.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/LCD_Controller.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} 9 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/aluno/desktop/projeto cl2/safe project/lcd_print.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/lcd_print.v" { { "Info" "ISGN_ENTITY_NAME" "1 LCD_Print " "Info: Found entity 1: LCD_Print" { } { { "../Safe Project/LCD_Print.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/LCD_Print.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} 10 | { "Info" "ISGN_START_ELABORATION_TOP" "Safe " "Info: Elaborating entity \"Safe\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} 11 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 Safe.v(100) " "Warning (10230): Verilog HDL assignment warning at Safe.v(100): truncated value with size 32 to match size of target (18)" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1} 12 | { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 Safe.v(108) " "Warning (10230): Verilog HDL assignment warning at Safe.v(108): truncated value with size 32 to match size of target (6)" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 108 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1} 13 | { "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay Reset_Delay:r0 " "Info: Elaborating entity \"Reset_Delay\" for hierarchy \"Reset_Delay:r0\"" { } { { "../Safe Project/Safe.v" "r0" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 26 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} 14 | { "Info" "ISGN_START_ELABORATION_HIERARCHY" "LCD_Controller LCD_Controller:u0 " "Info: Elaborating entity \"LCD_Controller\" for hierarchy \"LCD_Controller:u0\"" { } { { "../Safe Project/Safe.v" "u0" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 253 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} 15 | { "Info" "ISGN_START_ELABORATION_HIERARCHY" "Servo_Controller Servo_Controller:s0 " "Info: Elaborating entity \"Servo_Controller\" for hierarchy \"Servo_Controller:s0\"" { } { { "../Safe Project/Safe.v" "s0" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 260 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} 16 | { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "Warning: The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[0\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[0\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[1\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[1\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[2\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[2\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[3\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[3\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[4\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[4\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[5\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[5\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[6\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[6\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} { "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "LCD_DATA\[7\] " "Warning: Inserted always-enabled tri-state buffer between \"LCD_DATA\[7\]\" and its non-tri-state driver." { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1} } { } 0 0 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "" 0 -1} 17 | { "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[0\]~synth " "Warning: Node \"LCD_DATA\[0\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[1\]~synth " "Warning: Node \"LCD_DATA\[1\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[2\]~synth " "Warning: Node \"LCD_DATA\[2\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[3\]~synth " "Warning: Node \"LCD_DATA\[3\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[4\]~synth " "Warning: Node \"LCD_DATA\[4\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[5\]~synth " "Warning: Node \"LCD_DATA\[5\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[6\]~synth " "Warning: Node \"LCD_DATA\[6\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_NODE_NAME" "LCD_DATA\[7\]~synth " "Warning: Node \"LCD_DATA\[7\]~synth\"" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0 -1} 18 | { "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_ON VCC " "Warning (13410): Pin \"LCD_ON\" is stuck at VCC" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 13 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_BLON VCC " "Warning (13410): Pin \"LCD_BLON\" is stuck at VCC" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 14 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_RW GND " "Warning (13410): Pin \"LCD_RW\" is stuck at GND" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1} 19 | { "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "8 8 " "Info: 8 registers lost all their fanouts during netlist optimizations. The first 8 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mLCD_ST~6 " "Info: Register \"mLCD_ST~6\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mLCD_ST~7 " "Info: Register \"mLCD_ST~7\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mLCD_ST~8 " "Info: Register \"mLCD_ST~8\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mLCD_ST~9 " "Info: Register \"mLCD_ST~9\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mLCD_ST~10 " "Info: Register \"mLCD_ST~10\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "mLCD_ST~11 " "Info: Register \"mLCD_ST~11\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "LCD_Controller:u0\|ST~8 " "Info: Register \"LCD_Controller:u0\|ST~8\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "LCD_Controller:u0\|ST~9 " "Info: Register \"LCD_Controller:u0\|ST~9\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1} 20 | { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/aluno/Desktop/Projeto CL2/Quartus/Safe.map.smsg " "Info: Generated suppressed messages file C:/Users/aluno/Desktop/Projeto CL2/Quartus/Safe.map.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} 21 | { "Info" "ICUT_CUT_TM_SUMMARY" "249 " "Info: Implemented 249 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "23 " "Info: Implemented 23 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" { } { } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "209 " "Info: Implemented 209 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} 22 | { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 24 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "211 " "Info: Peak virtual memory: 211 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 30 16:12:26 2019 " "Info: Processing ended: Tue Apr 30 16:12:26 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} 23 | -------------------------------------------------------------------------------- /quartus/simulation/modelsim/Safe_modelsim.xrf: -------------------------------------------------------------------------------- 1 | vendor_name = ModelSim 2 | source_file = 1, C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Servo_Controller.v 3 | source_file = 1, C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v 4 | source_file = 1, C:/Users/aluno/Desktop/Projeto CL2/Safe Project/LCD_Reset_Delay.v 5 | source_file = 1, C:/Users/aluno/Desktop/Projeto CL2/Safe Project/LCD_Controller.v 6 | source_file = 1, C:/Users/aluno/Desktop/Projeto CL2/Safe Project/LCD_Print.v 7 | source_file = 1, C:/Users/aluno/Desktop/Projeto CL2/Quartus/db/Safe.cbx.xml 8 | design_name = Safe 9 | instance = comp, \s0|ctr_q[17] , s0|ctr_q[17], Safe, 1 10 | instance = comp, \s0|ctr_q[18] , s0|ctr_q[18], Safe, 1 11 | instance = comp, \s0|ctr_q[19] , s0|ctr_q[19], Safe, 1 12 | instance = comp, \s0|ctr_q[15] , s0|ctr_q[15], Safe, 1 13 | instance = comp, \s0|ctr_q[6] , s0|ctr_q[6], Safe, 1 14 | instance = comp, \s0|ctr_q[4] , s0|ctr_q[4], Safe, 1 15 | instance = comp, \s0|ctr_q[2] , s0|ctr_q[2], Safe, 1 16 | instance = comp, \s0|ctr_q[0] , s0|ctr_q[0], Safe, 1 17 | instance = comp, \s0|ctr_q[0]~20 , s0|ctr_q[0]~20, Safe, 1 18 | instance = comp, \s0|ctr_q[2]~24 , s0|ctr_q[2]~24, Safe, 1 19 | instance = comp, \s0|ctr_q[4]~28 , s0|ctr_q[4]~28, Safe, 1 20 | instance = comp, \s0|ctr_q[6]~32 , s0|ctr_q[6]~32, Safe, 1 21 | instance = comp, \s0|ctr_q[15]~50 , s0|ctr_q[15]~50, Safe, 1 22 | instance = comp, \s0|ctr_q[16]~52 , s0|ctr_q[16]~52, Safe, 1 23 | instance = comp, \s0|ctr_q[17]~54 , s0|ctr_q[17]~54, Safe, 1 24 | instance = comp, \s0|ctr_q[18]~56 , s0|ctr_q[18]~56, Safe, 1 25 | instance = comp, \s0|ctr_q[19]~58 , s0|ctr_q[19]~58, Safe, 1 26 | instance = comp, \r0|Cont[1] , r0|Cont[1], Safe, 1 27 | instance = comp, \r0|Cont[2] , r0|Cont[2], Safe, 1 28 | instance = comp, \r0|Cont[6] , r0|Cont[6], Safe, 1 29 | instance = comp, \r0|Cont[13] , r0|Cont[13], Safe, 1 30 | instance = comp, \mDLY[1] , mDLY[1], Safe, 1 31 | instance = comp, \mDLY[5] , mDLY[5], Safe, 1 32 | instance = comp, \mDLY[12] , mDLY[12], Safe, 1 33 | instance = comp, \mDLY[14] , mDLY[14], Safe, 1 34 | instance = comp, \mDLY[17] , mDLY[17], Safe, 1 35 | instance = comp, \u0|Add0~0 , u0|Add0~0, Safe, 1 36 | instance = comp, \u0|Add0~2 , u0|Add0~2, Safe, 1 37 | instance = comp, \u0|Add0~4 , u0|Add0~4, Safe, 1 38 | instance = comp, \u0|Add0~6 , u0|Add0~6, Safe, 1 39 | instance = comp, \u0|Add0~8 , u0|Add0~8, Safe, 1 40 | instance = comp, \r0|Cont[1]~19 , r0|Cont[1]~19, Safe, 1 41 | instance = comp, \r0|Cont[2]~21 , r0|Cont[2]~21, Safe, 1 42 | instance = comp, \r0|Cont[6]~29 , r0|Cont[6]~29, Safe, 1 43 | instance = comp, \r0|Cont[13]~43 , r0|Cont[13]~43, Safe, 1 44 | instance = comp, \mDLY[1]~20 , mDLY[1]~20, Safe, 1 45 | instance = comp, \mDLY[5]~30 , mDLY[5]~30, Safe, 1 46 | instance = comp, \mDLY[12]~44 , mDLY[12]~44, Safe, 1 47 | instance = comp, \mDLY[14]~48 , mDLY[14]~48, Safe, 1 48 | instance = comp, \mDLY[16]~52 , mDLY[16]~52, Safe, 1 49 | instance = comp, \mDLY[17]~54 , mDLY[17]~54, Safe, 1 50 | instance = comp, \s0|LessThan0~0 , s0|LessThan0~0, Safe, 1 51 | instance = comp, \Equal0~2 , Equal0~2, Safe, 1 52 | instance = comp, \mLCD_ST.000000 , mLCD_ST.000000, Safe, 1 53 | instance = comp, \Equal0~5 , Equal0~5, Safe, 1 54 | instance = comp, \u0|Cont[4] , u0|Cont[4], Safe, 1 55 | instance = comp, \r0|Equal0~1 , r0|Equal0~1, Safe, 1 56 | instance = comp, \LUT_DATA[4]~14 , LUT_DATA[4]~14, Safe, 1 57 | instance = comp, \message.00 , message.00, Safe, 1 58 | instance = comp, \mLCD_ST~19 , mLCD_ST~19, Safe, 1 59 | instance = comp, \mLCD_ST~22 , mLCD_ST~22, Safe, 1 60 | instance = comp, \mLCD_ST~23 , mLCD_ST~23, Safe, 1 61 | instance = comp, \u0|Cont~0 , u0|Cont~0, Safe, 1 62 | instance = comp, \u0|Cont[3] , u0|Cont[3], Safe, 1 63 | instance = comp, \u0|Cont[2] , u0|Cont[2], Safe, 1 64 | instance = comp, \u0|Cont[1] , u0|Cont[1], Safe, 1 65 | instance = comp, \u0|Cont[0] , u0|Cont[0], Safe, 1 66 | instance = comp, \u0|Selector4~0 , u0|Selector4~0, Safe, 1 67 | instance = comp, \always0~0 , always0~0, Safe, 1 68 | instance = comp, \message.00~0 , message.00~0, Safe, 1 69 | instance = comp, \u0|oDone~0 , u0|oDone~0, Safe, 1 70 | instance = comp, \LUT_DATA[0] , LUT_DATA[0], Safe, 1 71 | instance = comp, \LUT_DATA[6] , LUT_DATA[6], Safe, 1 72 | instance = comp, \u0|Selector5~0 , u0|Selector5~0, Safe, 1 73 | instance = comp, \u0|Selector6~0 , u0|Selector6~0, Safe, 1 74 | instance = comp, \u0|Selector7~0 , u0|Selector7~0, Safe, 1 75 | instance = comp, \u0|Selector8~0 , u0|Selector8~0, Safe, 1 76 | instance = comp, \LUT_DATA~25 , LUT_DATA~25, Safe, 1 77 | instance = comp, \LUT_DATA~26 , LUT_DATA~26, Safe, 1 78 | instance = comp, \LUT_DATA~29 , LUT_DATA~29, Safe, 1 79 | instance = comp, \LUT_DATA~30 , LUT_DATA~30, Safe, 1 80 | instance = comp, \LUT_DATA~31 , LUT_DATA~31, Safe, 1 81 | instance = comp, \LUT_DATA~32 , LUT_DATA~32, Safe, 1 82 | instance = comp, \LUT_DATA~33 , LUT_DATA~33, Safe, 1 83 | instance = comp, \LUT_DATA~35 , LUT_DATA~35, Safe, 1 84 | instance = comp, \LUT_DATA~36 , LUT_DATA~36, Safe, 1 85 | instance = comp, \LUT_DATA~37 , LUT_DATA~37, Safe, 1 86 | instance = comp, \LUT_DATA~38 , LUT_DATA~38, Safe, 1 87 | instance = comp, \LUT_DATA~39 , LUT_DATA~39, Safe, 1 88 | instance = comp, \LUT_DATA~43 , LUT_DATA~43, Safe, 1 89 | instance = comp, \Mux2~0 , Mux2~0, Safe, 1 90 | instance = comp, \Selector15~0 , Selector15~0, Safe, 1 91 | instance = comp, \Mux2~1 , Mux2~1, Safe, 1 92 | instance = comp, \Mux2~2 , Mux2~2, Safe, 1 93 | instance = comp, \Mux2~3 , Mux2~3, Safe, 1 94 | instance = comp, \WideOr2~0 , WideOr2~0, Safe, 1 95 | instance = comp, \Mux2~4 , Mux2~4, Safe, 1 96 | instance = comp, \Mux2~5 , Mux2~5, Safe, 1 97 | instance = comp, \Mux2~6 , Mux2~6, Safe, 1 98 | instance = comp, \SW[1]~I , SW[1], Safe, 1 99 | instance = comp, \SW[7]~I , SW[7], Safe, 1 100 | instance = comp, \SW[8]~I , SW[8], Safe, 1 101 | instance = comp, \SW[9]~I , SW[9], Safe, 1 102 | instance = comp, \SW[10]~I , SW[10], Safe, 1 103 | instance = comp, \SW[11]~I , SW[11], Safe, 1 104 | instance = comp, \SW[15]~I , SW[15], Safe, 1 105 | instance = comp, \CLOCK_50~I , CLOCK_50, Safe, 1 106 | instance = comp, \CLOCK_50~clkctrl , CLOCK_50~clkctrl, Safe, 1 107 | instance = comp, \KEY[0]~I , KEY[0], Safe, 1 108 | instance = comp, \SW[5]~I , SW[5], Safe, 1 109 | instance = comp, \SW[4]~I , SW[4], Safe, 1 110 | instance = comp, \SW[6]~I , SW[6], Safe, 1 111 | instance = comp, \Equal0~1 , Equal0~1, Safe, 1 112 | instance = comp, \SW[0]~I , SW[0], Safe, 1 113 | instance = comp, \SW[3]~I , SW[3], Safe, 1 114 | instance = comp, \SW[2]~I , SW[2], Safe, 1 115 | instance = comp, \Equal0~0 , Equal0~0, Safe, 1 116 | instance = comp, \SW[14]~I , SW[14], Safe, 1 117 | instance = comp, \SW[12]~I , SW[12], Safe, 1 118 | instance = comp, \SW[13]~I , SW[13], Safe, 1 119 | instance = comp, \Equal0~3 , Equal0~3, Safe, 1 120 | instance = comp, \Equal0~4 , Equal0~4, Safe, 1 121 | instance = comp, \SW[16]~I , SW[16], Safe, 1 122 | instance = comp, \SW[17]~I , SW[17], Safe, 1 123 | instance = comp, \correctPass~0 , correctPass~0, Safe, 1 124 | instance = comp, \KEY[1]~I , KEY[1], Safe, 1 125 | instance = comp, \mLCD_ST~16 , mLCD_ST~16, Safe, 1 126 | instance = comp, \mLCD_ST~17 , mLCD_ST~17, Safe, 1 127 | instance = comp, \r0|Cont[0]~57 , r0|Cont[0]~57, Safe, 1 128 | instance = comp, \r0|Cont[0] , r0|Cont[0], Safe, 1 129 | instance = comp, \r0|Cont[3]~23 , r0|Cont[3]~23, Safe, 1 130 | instance = comp, \r0|Cont[3] , r0|Cont[3], Safe, 1 131 | instance = comp, \r0|Cont[4]~25 , r0|Cont[4]~25, Safe, 1 132 | instance = comp, \r0|Cont[5]~27 , r0|Cont[5]~27, Safe, 1 133 | instance = comp, \r0|Cont[5] , r0|Cont[5], Safe, 1 134 | instance = comp, \r0|Cont[7]~31 , r0|Cont[7]~31, Safe, 1 135 | instance = comp, \r0|Cont[7] , r0|Cont[7], Safe, 1 136 | instance = comp, \r0|Cont[4] , r0|Cont[4], Safe, 1 137 | instance = comp, \r0|Equal0~2 , r0|Equal0~2, Safe, 1 138 | instance = comp, \r0|Cont[8]~33 , r0|Cont[8]~33, Safe, 1 139 | instance = comp, \r0|Cont[8] , r0|Cont[8], Safe, 1 140 | instance = comp, \r0|Cont[9]~35 , r0|Cont[9]~35, Safe, 1 141 | instance = comp, \r0|Cont[9] , r0|Cont[9], Safe, 1 142 | instance = comp, \r0|Cont[10]~37 , r0|Cont[10]~37, Safe, 1 143 | instance = comp, \r0|Cont[10] , r0|Cont[10], Safe, 1 144 | instance = comp, \r0|Cont[11]~39 , r0|Cont[11]~39, Safe, 1 145 | instance = comp, \r0|Cont[11] , r0|Cont[11], Safe, 1 146 | instance = comp, \r0|Cont[12]~41 , r0|Cont[12]~41, Safe, 1 147 | instance = comp, \r0|Cont[12] , r0|Cont[12], Safe, 1 148 | instance = comp, \r0|Cont[14]~45 , r0|Cont[14]~45, Safe, 1 149 | instance = comp, \r0|Cont[14] , r0|Cont[14], Safe, 1 150 | instance = comp, \r0|Cont[15]~47 , r0|Cont[15]~47, Safe, 1 151 | instance = comp, \r0|Cont[16]~49 , r0|Cont[16]~49, Safe, 1 152 | instance = comp, \r0|Cont[16] , r0|Cont[16], Safe, 1 153 | instance = comp, \r0|Cont[17]~51 , r0|Cont[17]~51, Safe, 1 154 | instance = comp, \r0|Cont[17] , r0|Cont[17], Safe, 1 155 | instance = comp, \r0|Cont[18]~53 , r0|Cont[18]~53, Safe, 1 156 | instance = comp, \r0|Cont[18] , r0|Cont[18], Safe, 1 157 | instance = comp, \r0|Cont[19]~55 , r0|Cont[19]~55, Safe, 1 158 | instance = comp, \r0|Cont[19] , r0|Cont[19], Safe, 1 159 | instance = comp, \r0|Equal0~0 , r0|Equal0~0, Safe, 1 160 | instance = comp, \r0|Cont[15] , r0|Cont[15], Safe, 1 161 | instance = comp, \r0|Equal0~4 , r0|Equal0~4, Safe, 1 162 | instance = comp, \r0|Equal0~3 , r0|Equal0~3, Safe, 1 163 | instance = comp, \r0|Equal0~5 , r0|Equal0~5, Safe, 1 164 | instance = comp, \r0|Equal0~6 , r0|Equal0~6, Safe, 1 165 | instance = comp, \r0|Equal0~6_wirecell , r0|Equal0~6_wirecell, Safe, 1 166 | instance = comp, \r0|oRESET , r0|oRESET, Safe, 1 167 | instance = comp, \mLCD_DATA~1 , mLCD_DATA~1, Safe, 1 168 | instance = comp, \LUT_INDEX[0]~6 , LUT_INDEX[0]~6, Safe, 1 169 | instance = comp, \mLCD_ST~18 , mLCD_ST~18, Safe, 1 170 | instance = comp, \LUT_INDEX[0]~18 , LUT_INDEX[0]~18, Safe, 1 171 | instance = comp, \LUT_INDEX[0] , LUT_INDEX[0], Safe, 1 172 | instance = comp, \LUT_INDEX[1]~8 , LUT_INDEX[1]~8, Safe, 1 173 | instance = comp, \LUT_INDEX[1] , LUT_INDEX[1], Safe, 1 174 | instance = comp, \LUT_INDEX[2]~10 , LUT_INDEX[2]~10, Safe, 1 175 | instance = comp, \LUT_INDEX[2] , LUT_INDEX[2], Safe, 1 176 | instance = comp, \LUT_INDEX[3]~12 , LUT_INDEX[3]~12, Safe, 1 177 | instance = comp, \LUT_INDEX[4]~14 , LUT_INDEX[4]~14, Safe, 1 178 | instance = comp, \LUT_INDEX[4] , LUT_INDEX[4], Safe, 1 179 | instance = comp, \LUT_INDEX[3] , LUT_INDEX[3], Safe, 1 180 | instance = comp, \LUT_DATA~12 , LUT_DATA~12, Safe, 1 181 | instance = comp, \LessThan0~0 , LessThan0~0, Safe, 1 182 | instance = comp, \mLCD_DATA[7]~0 , mLCD_DATA[7]~0, Safe, 1 183 | instance = comp, \mLCD_DATA[0] , mLCD_DATA[0], Safe, 1 184 | instance = comp, \LUT_DATA[4]~21 , LUT_DATA[4]~21, Safe, 1 185 | instance = comp, \message~9 , message~9, Safe, 1 186 | instance = comp, \message.01 , message.01, Safe, 1 187 | instance = comp, \message~8 , message~8, Safe, 1 188 | instance = comp, \message.10 , message.10, Safe, 1 189 | instance = comp, \LUT_INDEX[5]~16 , LUT_INDEX[5]~16, Safe, 1 190 | instance = comp, \LUT_INDEX[5] , LUT_INDEX[5], Safe, 1 191 | instance = comp, \LUT_DATA[4]~15 , LUT_DATA[4]~15, Safe, 1 192 | instance = comp, \LUT_DATA[4]~16 , LUT_DATA[4]~16, Safe, 1 193 | instance = comp, \LUT_DATA~34 , LUT_DATA~34, Safe, 1 194 | instance = comp, \LUT_DATA~40 , LUT_DATA~40, Safe, 1 195 | instance = comp, \LUT_DATA[4]~18 , LUT_DATA[4]~18, Safe, 1 196 | instance = comp, \LUT_DATA[4]~19 , LUT_DATA[4]~19, Safe, 1 197 | instance = comp, \LUT_DATA[4]~20 , LUT_DATA[4]~20, Safe, 1 198 | instance = comp, \LUT_DATA~22 , LUT_DATA~22, Safe, 1 199 | instance = comp, \LUT_DATA[4]~23 , LUT_DATA[4]~23, Safe, 1 200 | instance = comp, \LUT_DATA[4]~24 , LUT_DATA[4]~24, Safe, 1 201 | instance = comp, \LUT_DATA[1] , LUT_DATA[1], Safe, 1 202 | instance = comp, \mLCD_DATA~2 , mLCD_DATA~2, Safe, 1 203 | instance = comp, \mLCD_DATA[1] , mLCD_DATA[1], Safe, 1 204 | instance = comp, \LUT_DATA~41 , LUT_DATA~41, Safe, 1 205 | instance = comp, \LUT_DATA[4]~27 , LUT_DATA[4]~27, Safe, 1 206 | instance = comp, \LUT_DATA[4]~28 , LUT_DATA[4]~28, Safe, 1 207 | instance = comp, \LUT_DATA~44 , LUT_DATA~44, Safe, 1 208 | instance = comp, \LUT_DATA~42 , LUT_DATA~42, Safe, 1 209 | instance = comp, \LUT_DATA~45 , LUT_DATA~45, Safe, 1 210 | instance = comp, \LUT_DATA~46 , LUT_DATA~46, Safe, 1 211 | instance = comp, \LUT_DATA[2] , LUT_DATA[2], Safe, 1 212 | instance = comp, \mLCD_DATA~3 , mLCD_DATA~3, Safe, 1 213 | instance = comp, \mLCD_DATA[2] , mLCD_DATA[2], Safe, 1 214 | instance = comp, \LUT_DATA~47 , LUT_DATA~47, Safe, 1 215 | instance = comp, \LUT_DATA~48 , LUT_DATA~48, Safe, 1 216 | instance = comp, \LUT_DATA~49 , LUT_DATA~49, Safe, 1 217 | instance = comp, \LUT_DATA[3] , LUT_DATA[3], Safe, 1 218 | instance = comp, \mLCD_DATA~4 , mLCD_DATA~4, Safe, 1 219 | instance = comp, \mLCD_DATA[3] , mLCD_DATA[3], Safe, 1 220 | instance = comp, \LUT_DATA~52 , LUT_DATA~52, Safe, 1 221 | instance = comp, \LUT_DATA~51 , LUT_DATA~51, Safe, 1 222 | instance = comp, \LUT_DATA~13 , LUT_DATA~13, Safe, 1 223 | instance = comp, \LUT_DATA~50 , LUT_DATA~50, Safe, 1 224 | instance = comp, \LUT_DATA~53 , LUT_DATA~53, Safe, 1 225 | instance = comp, \LUT_DATA[4] , LUT_DATA[4], Safe, 1 226 | instance = comp, \mLCD_DATA~5 , mLCD_DATA~5, Safe, 1 227 | instance = comp, \mLCD_DATA[4] , mLCD_DATA[4], Safe, 1 228 | instance = comp, \LUT_DATA~59 , LUT_DATA~59, Safe, 1 229 | instance = comp, \LUT_DATA~54 , LUT_DATA~54, Safe, 1 230 | instance = comp, \LUT_DATA~55 , LUT_DATA~55, Safe, 1 231 | instance = comp, \LUT_DATA~56 , LUT_DATA~56, Safe, 1 232 | instance = comp, \LUT_DATA[5] , LUT_DATA[5], Safe, 1 233 | instance = comp, \mLCD_DATA~6 , mLCD_DATA~6, Safe, 1 234 | instance = comp, \mLCD_DATA[5] , mLCD_DATA[5], Safe, 1 235 | instance = comp, \mLCD_DATA~7 , mLCD_DATA~7, Safe, 1 236 | instance = comp, \mLCD_DATA[6] , mLCD_DATA[6], Safe, 1 237 | instance = comp, \LUT_DATA~57 , LUT_DATA~57, Safe, 1 238 | instance = comp, \LUT_DATA[7] , LUT_DATA[7], Safe, 1 239 | instance = comp, \mLCD_DATA~8 , mLCD_DATA~8, Safe, 1 240 | instance = comp, \mLCD_DATA[7] , mLCD_DATA[7], Safe, 1 241 | instance = comp, \ledG[0] , ledG[0], Safe, 1 242 | instance = comp, \GPIO_I~I , GPIO_I, Safe, 1 243 | instance = comp, \correctFacial~0 , correctFacial~0, Safe, 1 244 | instance = comp, \ledG[1]~feeder , ledG[1]~feeder, Safe, 1 245 | instance = comp, \ledG[1] , ledG[1], Safe, 1 246 | instance = comp, \s0|ctr_q[1]~22 , s0|ctr_q[1]~22, Safe, 1 247 | instance = comp, \KEY[2]~I , KEY[2], Safe, 1 248 | instance = comp, \s0|ctr_q[1] , s0|ctr_q[1], Safe, 1 249 | instance = comp, \s0|ctr_q[3]~26 , s0|ctr_q[3]~26, Safe, 1 250 | instance = comp, \s0|ctr_q[3] , s0|ctr_q[3], Safe, 1 251 | instance = comp, \s0|ctr_q[5]~30 , s0|ctr_q[5]~30, Safe, 1 252 | instance = comp, \s0|ctr_q[5] , s0|ctr_q[5], Safe, 1 253 | instance = comp, \s0|ctr_q[7]~34 , s0|ctr_q[7]~34, Safe, 1 254 | instance = comp, \s0|ctr_q[7] , s0|ctr_q[7], Safe, 1 255 | instance = comp, \s0|ctr_q[8]~36 , s0|ctr_q[8]~36, Safe, 1 256 | instance = comp, \s0|ctr_q[8] , s0|ctr_q[8], Safe, 1 257 | instance = comp, \s0|ctr_q[9]~38 , s0|ctr_q[9]~38, Safe, 1 258 | instance = comp, \s0|ctr_q[9] , s0|ctr_q[9], Safe, 1 259 | instance = comp, \s0|ctr_q[10]~40 , s0|ctr_q[10]~40, Safe, 1 260 | instance = comp, \s0|ctr_q[10] , s0|ctr_q[10], Safe, 1 261 | instance = comp, \s0|ctr_q[11]~42 , s0|ctr_q[11]~42, Safe, 1 262 | instance = comp, \s0|ctr_q[11] , s0|ctr_q[11], Safe, 1 263 | instance = comp, \s0|ctr_q[12]~44 , s0|ctr_q[12]~44, Safe, 1 264 | instance = comp, \s0|ctr_q[12] , s0|ctr_q[12], Safe, 1 265 | instance = comp, \s0|ctr_q[13]~46 , s0|ctr_q[13]~46, Safe, 1 266 | instance = comp, \s0|ctr_q[14]~48 , s0|ctr_q[14]~48, Safe, 1 267 | instance = comp, \s0|ctr_q[14] , s0|ctr_q[14], Safe, 1 268 | instance = comp, \position~0 , position~0, Safe, 1 269 | instance = comp, \position[3] , position[3], Safe, 1 270 | instance = comp, \s0|ctr_q[13] , s0|ctr_q[13], Safe, 1 271 | instance = comp, \s0|LessThan0~5 , s0|LessThan0~5, Safe, 1 272 | instance = comp, \s0|ctr_q[16] , s0|ctr_q[16], Safe, 1 273 | instance = comp, \s0|LessThan0~1 , s0|LessThan0~1, Safe, 1 274 | instance = comp, \s0|LessThan0~2 , s0|LessThan0~2, Safe, 1 275 | instance = comp, \s0|LessThan0~3 , s0|LessThan0~3, Safe, 1 276 | instance = comp, \s0|LessThan0~4 , s0|LessThan0~4, Safe, 1 277 | instance = comp, \s0|LessThan0~6 , s0|LessThan0~6, Safe, 1 278 | instance = comp, \s0|pwm_q , s0|pwm_q, Safe, 1 279 | instance = comp, \u0|ST~14 , u0|ST~14, Safe, 1 280 | instance = comp, \r0|oRESET~clkctrl , r0|oRESET~clkctrl, Safe, 1 281 | instance = comp, \mDLY[0]~18 , mDLY[0]~18, Safe, 1 282 | instance = comp, \mDLY[8]~22 , mDLY[8]~22, Safe, 1 283 | instance = comp, \u0|oDone~1 , u0|oDone~1, Safe, 1 284 | instance = comp, \u0|oDone , u0|oDone, Safe, 1 285 | instance = comp, \mLCD_ST~20 , mLCD_ST~20, Safe, 1 286 | instance = comp, \mLCD_ST~21 , mLCD_ST~21, Safe, 1 287 | instance = comp, \mLCD_ST~26 , mLCD_ST~26, Safe, 1 288 | instance = comp, \mLCD_ST~27 , mLCD_ST~27, Safe, 1 289 | instance = comp, \mLCD_ST.000001 , mLCD_ST.000001, Safe, 1 290 | instance = comp, \mLCD_ST~28 , mLCD_ST~28, Safe, 1 291 | instance = comp, \mLCD_ST~29 , mLCD_ST~29, Safe, 1 292 | instance = comp, \mLCD_ST~25 , mLCD_ST~25, Safe, 1 293 | instance = comp, \mLCD_ST.000010 , mLCD_ST.000010, Safe, 1 294 | instance = comp, \mDLY[8]~23 , mDLY[8]~23, Safe, 1 295 | instance = comp, \mDLY[0] , mDLY[0], Safe, 1 296 | instance = comp, \mDLY[2]~24 , mDLY[2]~24, Safe, 1 297 | instance = comp, \mDLY[2] , mDLY[2], Safe, 1 298 | instance = comp, \mDLY[3]~26 , mDLY[3]~26, Safe, 1 299 | instance = comp, \mDLY[4]~28 , mDLY[4]~28, Safe, 1 300 | instance = comp, \mDLY[4] , mDLY[4], Safe, 1 301 | instance = comp, \mDLY[6]~32 , mDLY[6]~32, Safe, 1 302 | instance = comp, \mDLY[6] , mDLY[6], Safe, 1 303 | instance = comp, \mDLY[7]~34 , mDLY[7]~34, Safe, 1 304 | instance = comp, \mDLY[7] , mDLY[7], Safe, 1 305 | instance = comp, \mDLY[8]~36 , mDLY[8]~36, Safe, 1 306 | instance = comp, \mDLY[8] , mDLY[8], Safe, 1 307 | instance = comp, \mDLY[9]~38 , mDLY[9]~38, Safe, 1 308 | instance = comp, \mDLY[9] , mDLY[9], Safe, 1 309 | instance = comp, \mDLY[10]~40 , mDLY[10]~40, Safe, 1 310 | instance = comp, \mDLY[10] , mDLY[10], Safe, 1 311 | instance = comp, \mDLY[11]~42 , mDLY[11]~42, Safe, 1 312 | instance = comp, \mDLY[11] , mDLY[11], Safe, 1 313 | instance = comp, \mDLY[13]~46 , mDLY[13]~46, Safe, 1 314 | instance = comp, \mDLY[13] , mDLY[13], Safe, 1 315 | instance = comp, \LessThan1~2 , LessThan1~2, Safe, 1 316 | instance = comp, \mDLY[15]~50 , mDLY[15]~50, Safe, 1 317 | instance = comp, \mDLY[16] , mDLY[16], Safe, 1 318 | instance = comp, \mDLY[15] , mDLY[15], Safe, 1 319 | instance = comp, \LessThan1~3 , LessThan1~3, Safe, 1 320 | instance = comp, \LessThan1~4 , LessThan1~4, Safe, 1 321 | instance = comp, \mDLY[3] , mDLY[3], Safe, 1 322 | instance = comp, \LessThan1~0 , LessThan1~0, Safe, 1 323 | instance = comp, \LessThan1~1 , LessThan1~1, Safe, 1 324 | instance = comp, \LessThan1~5 , LessThan1~5, Safe, 1 325 | instance = comp, \mLCD_ST~24 , mLCD_ST~24, Safe, 1 326 | instance = comp, \mLCD_ST.000011 , mLCD_ST.000011, Safe, 1 327 | instance = comp, \mLCD_Start~1 , mLCD_Start~1, Safe, 1 328 | instance = comp, \mLCD_Start~0 , mLCD_Start~0, Safe, 1 329 | instance = comp, \mLCD_Start~2 , mLCD_Start~2, Safe, 1 330 | instance = comp, \u0|preStart , u0|preStart, Safe, 1 331 | instance = comp, \u0|mStart~0 , u0|mStart~0, Safe, 1 332 | instance = comp, \u0|mStart , u0|mStart, Safe, 1 333 | instance = comp, \u0|ST.11 , u0|ST.11, Safe, 1 334 | instance = comp, \u0|ST.00~0 , u0|ST.00~0, Safe, 1 335 | instance = comp, \u0|ST.00 , u0|ST.00, Safe, 1 336 | instance = comp, \u0|ST.01~0 , u0|ST.01~0, Safe, 1 337 | instance = comp, \u0|ST.01 , u0|ST.01, Safe, 1 338 | instance = comp, \u0|Selector2~0 , u0|Selector2~0, Safe, 1 339 | instance = comp, \u0|ST.10 , u0|ST.10, Safe, 1 340 | instance = comp, \u0|Selector3~0 , u0|Selector3~0, Safe, 1 341 | instance = comp, \u0|LCD_EN , u0|LCD_EN, Safe, 1 342 | instance = comp, \LUT_DATA~58 , LUT_DATA~58, Safe, 1 343 | instance = comp, \LUT_DATA~17 , LUT_DATA~17, Safe, 1 344 | instance = comp, \LUT_DATA[8] , LUT_DATA[8], Safe, 1 345 | instance = comp, \mLCD_RS~0 , mLCD_RS~0, Safe, 1 346 | instance = comp, \LCD_DATA[0]~I , LCD_DATA[0], Safe, 1 347 | instance = comp, \LCD_DATA[1]~I , LCD_DATA[1], Safe, 1 348 | instance = comp, \LCD_DATA[2]~I , LCD_DATA[2], Safe, 1 349 | instance = comp, \LCD_DATA[3]~I , LCD_DATA[3], Safe, 1 350 | instance = comp, \LCD_DATA[4]~I , LCD_DATA[4], Safe, 1 351 | instance = comp, \LCD_DATA[5]~I , LCD_DATA[5], Safe, 1 352 | instance = comp, \LCD_DATA[6]~I , LCD_DATA[6], Safe, 1 353 | instance = comp, \LCD_DATA[7]~I , LCD_DATA[7], Safe, 1 354 | instance = comp, \LEDG[0]~I , LEDG[0], Safe, 1 355 | instance = comp, \LEDG[1]~I , LEDG[1], Safe, 1 356 | instance = comp, \LEDR~I , LEDR, Safe, 1 357 | instance = comp, \GPIO_O~I , GPIO_O, Safe, 1 358 | instance = comp, \LCD_ON~I , LCD_ON, Safe, 1 359 | instance = comp, \LCD_BLON~I , LCD_BLON, Safe, 1 360 | instance = comp, \LCD_RW~I , LCD_RW, Safe, 1 361 | instance = comp, \LCD_EN~I , LCD_EN, Safe, 1 362 | instance = comp, \LCD_RS~I , LCD_RS, Safe, 1 363 | -------------------------------------------------------------------------------- /quartus/Safe.map.rpt: -------------------------------------------------------------------------------- 1 | Analysis & Synthesis report for Safe 2 | Tue Apr 30 16:12:26 2019 3 | Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Analysis & Synthesis Summary 11 | 3. Analysis & Synthesis Settings 12 | 4. Parallel Compilation 13 | 5. Analysis & Synthesis Source Files Read 14 | 6. Analysis & Synthesis Resource Usage Summary 15 | 7. Analysis & Synthesis Resource Utilization by Entity 16 | 8. State Machine - |Safe|message 17 | 9. State Machine - |Safe|mLCD_ST 18 | 10. State Machine - |Safe|LCD_Controller:u0|ST 19 | 11. Registers Removed During Synthesis 20 | 12. General Register Statistics 21 | 13. Multiplexer Restructuring Statistics (Restructuring Performed) 22 | 14. Parameter Settings for User Entity Instance: Top-level Entity: |Safe 23 | 15. Parameter Settings for User Entity Instance: LCD_Controller:u0 24 | 16. Analysis & Synthesis Messages 25 | 17. Analysis & Synthesis Suppressed Messages 26 | 27 | 28 | 29 | ---------------- 30 | ; Legal Notice ; 31 | ---------------- 32 | Copyright (C) 1991-2010 Altera Corporation 33 | Your use of Altera Corporation's design tools, logic functions 34 | and other software and tools, and its AMPP partner logic 35 | functions, and any output files from any of the foregoing 36 | (including device programming or simulation files), and any 37 | associated documentation or information are expressly subject 38 | to the terms and conditions of the Altera Program License 39 | Subscription Agreement, Altera MegaCore Function License 40 | Agreement, or other applicable license agreement, including, 41 | without limitation, that your use is for the sole purpose of 42 | programming logic devices manufactured by Altera and sold by 43 | Altera or its authorized distributors. Please refer to the 44 | applicable agreement for further details. 45 | 46 | 47 | 48 | +-----------------------------------------------------------------------------------+ 49 | ; Analysis & Synthesis Summary ; 50 | +------------------------------------+----------------------------------------------+ 51 | ; Analysis & Synthesis Status ; Successful - Tue Apr 30 16:12:26 2019 ; 52 | ; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; 53 | ; Revision Name ; Safe ; 54 | ; Top-level Entity Name ; Safe ; 55 | ; Family ; Cyclone II ; 56 | ; Total logic elements ; 209 ; 57 | ; Total combinational functions ; 206 ; 58 | ; Dedicated logic registers ; 110 ; 59 | ; Total registers ; 110 ; 60 | ; Total pins ; 40 ; 61 | ; Total virtual pins ; 0 ; 62 | ; Total memory bits ; 0 ; 63 | ; Embedded Multiplier 9-bit elements ; 0 ; 64 | ; Total PLLs ; 0 ; 65 | +------------------------------------+----------------------------------------------+ 66 | 67 | 68 | +----------------------------------------------------------------------------------------------------------------------+ 69 | ; Analysis & Synthesis Settings ; 70 | +----------------------------------------------------------------------------+--------------------+--------------------+ 71 | ; Option ; Setting ; Default Value ; 72 | +----------------------------------------------------------------------------+--------------------+--------------------+ 73 | ; Device ; EP2C35F672C6 ; ; 74 | ; Top-level entity name ; Safe ; Safe ; 75 | ; Family name ; Cyclone II ; Stratix II ; 76 | ; Type of Retiming Performed During Resynthesis ; Full ; ; 77 | ; Resynthesis Optimization Effort ; Normal ; ; 78 | ; Physical Synthesis Level for Resynthesis ; Normal ; ; 79 | ; Use Generated Physical Constraints File ; On ; ; 80 | ; Use smart compilation ; Off ; Off ; 81 | ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; 82 | ; Enable compact report table ; Off ; Off ; 83 | ; Restructure Multiplexers ; Auto ; Auto ; 84 | ; Create Debugging Nodes for IP Cores ; Off ; Off ; 85 | ; Preserve fewer node names ; On ; On ; 86 | ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; 87 | ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; 88 | ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; 89 | ; State Machine Processing ; Auto ; Auto ; 90 | ; Safe State Machine ; Off ; Off ; 91 | ; Extract Verilog State Machines ; On ; On ; 92 | ; Extract VHDL State Machines ; On ; On ; 93 | ; Ignore Verilog initial constructs ; Off ; Off ; 94 | ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; 95 | ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; 96 | ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; 97 | ; Parallel Synthesis ; On ; On ; 98 | ; DSP Block Balancing ; Auto ; Auto ; 99 | ; NOT Gate Push-Back ; On ; On ; 100 | ; Power-Up Don't Care ; On ; On ; 101 | ; Remove Redundant Logic Cells ; Off ; Off ; 102 | ; Remove Duplicate Registers ; On ; On ; 103 | ; Ignore CARRY Buffers ; Off ; Off ; 104 | ; Ignore CASCADE Buffers ; Off ; Off ; 105 | ; Ignore GLOBAL Buffers ; Off ; Off ; 106 | ; Ignore ROW GLOBAL Buffers ; Off ; Off ; 107 | ; Ignore LCELL Buffers ; Off ; Off ; 108 | ; Ignore SOFT Buffers ; On ; On ; 109 | ; Limit AHDL Integers to 32 Bits ; Off ; Off ; 110 | ; Optimization Technique ; Balanced ; Balanced ; 111 | ; Carry Chain Length ; 70 ; 70 ; 112 | ; Auto Carry Chains ; On ; On ; 113 | ; Auto Open-Drain Pins ; On ; On ; 114 | ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; 115 | ; Auto ROM Replacement ; On ; On ; 116 | ; Auto RAM Replacement ; On ; On ; 117 | ; Auto Shift Register Replacement ; Auto ; Auto ; 118 | ; Auto Clock Enable Replacement ; On ; On ; 119 | ; Strict RAM Replacement ; Off ; Off ; 120 | ; Allow Synchronous Control Signals ; On ; On ; 121 | ; Force Use of Synchronous Clear Signals ; Off ; Off ; 122 | ; Auto RAM to Logic Cell Conversion ; Off ; Off ; 123 | ; Auto Resource Sharing ; Off ; Off ; 124 | ; Allow Any RAM Size For Recognition ; Off ; Off ; 125 | ; Allow Any ROM Size For Recognition ; Off ; Off ; 126 | ; Allow Any Shift Register Size For Recognition ; Off ; Off ; 127 | ; Use LogicLock Constraints during Resource Balancing ; On ; On ; 128 | ; Ignore translate_off and synthesis_off directives ; Off ; Off ; 129 | ; Timing-Driven Synthesis ; Off ; Off ; 130 | ; Show Parameter Settings Tables in Synthesis Report ; On ; On ; 131 | ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; 132 | ; Synchronization Register Chain Length ; 2 ; 2 ; 133 | ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; 134 | ; HDL message level ; Level2 ; Level2 ; 135 | ; Suppress Register Optimization Related Messages ; Off ; Off ; 136 | ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; 137 | ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; 138 | ; Clock MUX Protection ; On ; On ; 139 | ; Auto Gated Clock Conversion ; Off ; Off ; 140 | ; Block Design Naming ; Auto ; Auto ; 141 | ; SDC constraint protection ; Off ; Off ; 142 | ; Synthesis Effort ; Auto ; Auto ; 143 | ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; 144 | ; Analysis & Synthesis Message Level ; Medium ; Medium ; 145 | ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; 146 | ; Resource Aware Inference For Block RAM ; On ; On ; 147 | +----------------------------------------------------------------------------+--------------------+--------------------+ 148 | 149 | 150 | Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. 151 | +-------------------------------------+ 152 | ; Parallel Compilation ; 153 | +----------------------------+--------+ 154 | ; Processors ; Number ; 155 | +----------------------------+--------+ 156 | ; Number detected on machine ; 4 ; 157 | ; Maximum allowed ; 1 ; 158 | +----------------------------+--------+ 159 | 160 | 161 | +----------------------------------------------------------------------------------------------------------------------------------------------------+ 162 | ; Analysis & Synthesis Source Files Read ; 163 | +------------------------------------+-----------------+------------------------+--------------------------------------------------------------------+ 164 | ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; 165 | +------------------------------------+-----------------+------------------------+--------------------------------------------------------------------+ 166 | ; ../Safe Project/Servo_Controller.v ; yes ; User Verilog HDL File ; C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Servo_Controller.v ; 167 | ; ../Safe Project/Safe.v ; yes ; User Verilog HDL File ; C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v ; 168 | ; ../Safe Project/LCD_Reset_Delay.v ; yes ; User Verilog HDL File ; C:/Users/aluno/Desktop/Projeto CL2/Safe Project/LCD_Reset_Delay.v ; 169 | ; ../Safe Project/LCD_Controller.v ; yes ; User Verilog HDL File ; C:/Users/aluno/Desktop/Projeto CL2/Safe Project/LCD_Controller.v ; 170 | +------------------------------------+-----------------+------------------------+--------------------------------------------------------------------+ 171 | 172 | 173 | +--------------------------------------------------------+ 174 | ; Analysis & Synthesis Resource Usage Summary ; 175 | +---------------------------------------------+----------+ 176 | ; Resource ; Usage ; 177 | +---------------------------------------------+----------+ 178 | ; Estimated Total logic elements ; 209 ; 179 | ; ; ; 180 | ; Total combinational functions ; 206 ; 181 | ; Logic element usage by number of LUT inputs ; ; 182 | ; -- 4 input functions ; 97 ; 183 | ; -- 3 input functions ; 24 ; 184 | ; -- <=2 input functions ; 85 ; 185 | ; ; ; 186 | ; Logic elements by mode ; ; 187 | ; -- normal mode ; 143 ; 188 | ; -- arithmetic mode ; 63 ; 189 | ; ; ; 190 | ; Total registers ; 110 ; 191 | ; -- Dedicated logic registers ; 110 ; 192 | ; -- I/O registers ; 0 ; 193 | ; ; ; 194 | ; I/O pins ; 40 ; 195 | ; Maximum fan-out node ; CLOCK_50 ; 196 | ; Maximum fan-out ; 110 ; 197 | ; Total fan-out ; 989 ; 198 | ; Average fan-out ; 2.78 ; 199 | +---------------------------------------------+----------+ 200 | 201 | 202 | +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 203 | ; Analysis & Synthesis Resource Utilization by Entity ; 204 | +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+ 205 | ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; 206 | +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+ 207 | ; |Safe ; 206 (132) ; 110 (55) ; 0 ; 0 ; 0 ; 0 ; 40 ; 0 ; |Safe ; work ; 208 | ; |LCD_Controller:u0| ; 19 (19) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Safe|LCD_Controller:u0 ; ; 209 | ; |Reset_Delay:r0| ; 28 (28) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Safe|Reset_Delay:r0 ; ; 210 | ; |Servo_Controller:s0| ; 27 (27) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Safe|Servo_Controller:s0 ; ; 211 | +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+ 212 | Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. 213 | 214 | 215 | Encoding Type: One-Hot 216 | +---------------------------------------------------+ 217 | ; State Machine - |Safe|message ; 218 | +------------+------------+------------+------------+ 219 | ; Name ; message.00 ; message.10 ; message.01 ; 220 | +------------+------------+------------+------------+ 221 | ; message.00 ; 0 ; 0 ; 0 ; 222 | ; message.01 ; 1 ; 0 ; 1 ; 223 | ; message.10 ; 1 ; 1 ; 0 ; 224 | +------------+------------+------------+------------+ 225 | 226 | 227 | Encoding Type: One-Hot 228 | +------------------------------------------------------------------------------------+ 229 | ; State Machine - |Safe|mLCD_ST ; 230 | +----------------+----------------+----------------+----------------+----------------+ 231 | ; Name ; mLCD_ST.000011 ; mLCD_ST.000010 ; mLCD_ST.000001 ; mLCD_ST.000000 ; 232 | +----------------+----------------+----------------+----------------+----------------+ 233 | ; mLCD_ST.000000 ; 0 ; 0 ; 0 ; 0 ; 234 | ; mLCD_ST.000001 ; 0 ; 0 ; 1 ; 1 ; 235 | ; mLCD_ST.000010 ; 0 ; 1 ; 0 ; 1 ; 236 | ; mLCD_ST.000011 ; 1 ; 0 ; 0 ; 1 ; 237 | +----------------+----------------+----------------+----------------+----------------+ 238 | 239 | 240 | Encoding Type: One-Hot 241 | +--------------------------------------------+ 242 | ; State Machine - |Safe|LCD_Controller:u0|ST ; 243 | +-------+-------+-------+-------+------------+ 244 | ; Name ; ST.11 ; ST.10 ; ST.01 ; ST.00 ; 245 | +-------+-------+-------+-------+------------+ 246 | ; ST.00 ; 0 ; 0 ; 0 ; 0 ; 247 | ; ST.01 ; 0 ; 0 ; 1 ; 1 ; 248 | ; ST.10 ; 0 ; 1 ; 0 ; 1 ; 249 | ; ST.11 ; 1 ; 0 ; 0 ; 1 ; 250 | +-------+-------+-------+-------+------------+ 251 | 252 | 253 | +---------------------------------------------------------------------------------+ 254 | ; Registers Removed During Synthesis ; 255 | +----------------------------------------+----------------------------------------+ 256 | ; Register name ; Reason for Removal ; 257 | +----------------------------------------+----------------------------------------+ 258 | ; position[1..2,4..5] ; Merged with position[0] ; 259 | ; position[6..7] ; Merged with position[3] ; 260 | ; position[0] ; Stuck at GND due to stuck port data_in ; 261 | ; mLCD_ST~6 ; Lost fanout ; 262 | ; mLCD_ST~7 ; Lost fanout ; 263 | ; mLCD_ST~8 ; Lost fanout ; 264 | ; mLCD_ST~9 ; Lost fanout ; 265 | ; mLCD_ST~10 ; Lost fanout ; 266 | ; mLCD_ST~11 ; Lost fanout ; 267 | ; LCD_Controller:u0|ST~8 ; Lost fanout ; 268 | ; LCD_Controller:u0|ST~9 ; Lost fanout ; 269 | ; Total Number of Removed Registers = 15 ; ; 270 | +----------------------------------------+----------------------------------------+ 271 | 272 | 273 | +------------------------------------------------------+ 274 | ; General Register Statistics ; 275 | +----------------------------------------------+-------+ 276 | ; Statistic ; Value ; 277 | +----------------------------------------------+-------+ 278 | ; Total registers ; 110 ; 279 | ; Number of registers using Synchronous Clear ; 48 ; 280 | ; Number of registers using Synchronous Load ; 0 ; 281 | ; Number of registers using Asynchronous Clear ; 13 ; 282 | ; Number of registers using Asynchronous Load ; 0 ; 283 | ; Number of registers using Clock Enable ; 72 ; 284 | ; Number of registers using Preset ; 0 ; 285 | +----------------------------------------------+-------+ 286 | 287 | 288 | +----------------------------------------------------------------------------------------------------------------------------------------------+ 289 | ; Multiplexer Restructuring Statistics (Restructuring Performed) ; 290 | +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+ 291 | ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; 292 | +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+ 293 | ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |Safe|LCD_Controller:u0|mStart ; 294 | ; 6:1 ; 6 bits ; 24 LEs ; 6 LEs ; 18 LEs ; Yes ; |Safe|LUT_INDEX[0] ; 295 | ; 7:1 ; 9 bits ; 36 LEs ; 9 LEs ; 27 LEs ; Yes ; |Safe|mLCD_DATA[7] ; 296 | ; 8:1 ; 18 bits ; 90 LEs ; 18 LEs ; 72 LEs ; Yes ; |Safe|mDLY[8] ; 297 | ; 104:1 ; 8 bits ; 552 LEs ; 224 LEs ; 328 LEs ; Yes ; |Safe|LUT_DATA[4] ; 298 | ; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |Safe|message ; 299 | ; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |Safe|mLCD_ST ; 300 | ; 11:1 ; 2 bits ; 14 LEs ; 12 LEs ; 2 LEs ; No ; |Safe|mLCD_ST ; 301 | +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+ 302 | 303 | 304 | +----------------------------------------------------------------------+ 305 | ; Parameter Settings for User Entity Instance: Top-level Entity: |Safe ; 306 | +----------------+--------------------+--------------------------------+ 307 | ; Parameter Name ; Value ; Type ; 308 | +----------------+--------------------+--------------------------------+ 309 | ; LCD_INTIAL ; 0 ; Signed Integer ; 310 | ; LCD_LINE1 ; 5 ; Signed Integer ; 311 | ; LCD_CH_LINE ; 21 ; Signed Integer ; 312 | ; LCD_LINE2 ; 22 ; Signed Integer ; 313 | ; LUT_SIZE ; 38 ; Signed Integer ; 314 | ; PASSWORD ; 111111111111111111 ; Unsigned Binary ; 315 | +----------------+--------------------+--------------------------------+ 316 | Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". 317 | 318 | 319 | +----------------------------------------------------------------+ 320 | ; Parameter Settings for User Entity Instance: LCD_Controller:u0 ; 321 | +----------------+-------+---------------------------------------+ 322 | ; Parameter Name ; Value ; Type ; 323 | +----------------+-------+---------------------------------------+ 324 | ; CLK_Divide ; 16 ; Signed Integer ; 325 | +----------------+-------+---------------------------------------+ 326 | Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". 327 | 328 | 329 | +-------------------------------+ 330 | ; Analysis & Synthesis Messages ; 331 | +-------------------------------+ 332 | Info: ******************************************************************* 333 | Info: Running Quartus II Analysis & Synthesis 334 | Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition 335 | Info: Processing started: Tue Apr 30 16:12:25 2019 336 | Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Safe -c Safe 337 | Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/servo_controller.v 338 | Info: Found entity 1: Servo_Controller 339 | Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/safe.v 340 | Info: Found entity 1: Safe 341 | Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/lcd_reset_delay.v 342 | Info: Found entity 1: Reset_Delay 343 | Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/lcd_controller.v 344 | Info: Found entity 1: LCD_Controller 345 | Info: Found 1 design units, including 1 entities, in source file /users/aluno/desktop/projeto cl2/safe project/lcd_print.v 346 | Info: Found entity 1: LCD_Print 347 | Info: Elaborating entity "Safe" for the top level hierarchy 348 | Warning (10230): Verilog HDL assignment warning at Safe.v(100): truncated value with size 32 to match size of target (18) 349 | Warning (10230): Verilog HDL assignment warning at Safe.v(108): truncated value with size 32 to match size of target (6) 350 | Info: Elaborating entity "Reset_Delay" for hierarchy "Reset_Delay:r0" 351 | Info: Elaborating entity "LCD_Controller" for hierarchy "LCD_Controller:u0" 352 | Info: Elaborating entity "Servo_Controller" for hierarchy "Servo_Controller:s0" 353 | Warning: The following nodes have both tri-state and non-tri-state drivers 354 | Warning: Inserted always-enabled tri-state buffer between "LCD_DATA[0]" and its non-tri-state driver. 355 | Warning: Inserted always-enabled tri-state buffer between "LCD_DATA[1]" and its non-tri-state driver. 356 | Warning: Inserted always-enabled tri-state buffer between "LCD_DATA[2]" and its non-tri-state driver. 357 | Warning: Inserted always-enabled tri-state buffer between "LCD_DATA[3]" and its non-tri-state driver. 358 | Warning: Inserted always-enabled tri-state buffer between "LCD_DATA[4]" and its non-tri-state driver. 359 | Warning: Inserted always-enabled tri-state buffer between "LCD_DATA[5]" and its non-tri-state driver. 360 | Warning: Inserted always-enabled tri-state buffer between "LCD_DATA[6]" and its non-tri-state driver. 361 | Warning: Inserted always-enabled tri-state buffer between "LCD_DATA[7]" and its non-tri-state driver. 362 | Warning: TRI or OPNDRN buffers permanently enabled 363 | Warning: Node "LCD_DATA[0]~synth" 364 | Warning: Node "LCD_DATA[1]~synth" 365 | Warning: Node "LCD_DATA[2]~synth" 366 | Warning: Node "LCD_DATA[3]~synth" 367 | Warning: Node "LCD_DATA[4]~synth" 368 | Warning: Node "LCD_DATA[5]~synth" 369 | Warning: Node "LCD_DATA[6]~synth" 370 | Warning: Node "LCD_DATA[7]~synth" 371 | Warning: Output pins are stuck at VCC or GND 372 | Warning (13410): Pin "LCD_ON" is stuck at VCC 373 | Warning (13410): Pin "LCD_BLON" is stuck at VCC 374 | Warning (13410): Pin "LCD_RW" is stuck at GND 375 | Info: 8 registers lost all their fanouts during netlist optimizations. The first 8 are displayed below. 376 | Info: Register "mLCD_ST~6" lost all its fanouts during netlist optimizations. 377 | Info: Register "mLCD_ST~7" lost all its fanouts during netlist optimizations. 378 | Info: Register "mLCD_ST~8" lost all its fanouts during netlist optimizations. 379 | Info: Register "mLCD_ST~9" lost all its fanouts during netlist optimizations. 380 | Info: Register "mLCD_ST~10" lost all its fanouts during netlist optimizations. 381 | Info: Register "mLCD_ST~11" lost all its fanouts during netlist optimizations. 382 | Info: Register "LCD_Controller:u0|ST~8" lost all its fanouts during netlist optimizations. 383 | Info: Register "LCD_Controller:u0|ST~9" lost all its fanouts during netlist optimizations. 384 | Info: Generated suppressed messages file C:/Users/aluno/Desktop/Projeto CL2/Quartus/Safe.map.smsg 385 | Info: Implemented 249 device resources after synthesis - the final resource count might be different 386 | Info: Implemented 23 input pins 387 | Info: Implemented 9 output pins 388 | Info: Implemented 8 bidirectional pins 389 | Info: Implemented 209 logic cells 390 | Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings 391 | Info: Peak virtual memory: 211 megabytes 392 | Info: Processing ended: Tue Apr 30 16:12:26 2019 393 | Info: Elapsed time: 00:00:01 394 | Info: Total CPU time (on all processors): 00:00:02 395 | 396 | 397 | +------------------------------------------+ 398 | ; Analysis & Synthesis Suppressed Messages ; 399 | +------------------------------------------+ 400 | The suppressed messages can be found in C:/Users/aluno/Desktop/Projeto CL2/Quartus/Safe.map.smsg. 401 | 402 | 403 | -------------------------------------------------------------------------------- /quartus/db/Safe.fit.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 30 16:12:27 2019 " "Info: Processing started: Tue Apr 30 16:12:27 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off Safe -c Safe " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Safe -c Safe" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} 4 | { "Info" "IMPP_MPP_USER_DEVICE" "Safe EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"Safe\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} 5 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} 6 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} 7 | { "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} 8 | { "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." { } { } 0 0 "Feature %1!s! is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." 0 0 "" 0 -1} 9 | { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} 10 | { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Info: Pin ~ASDO~ is reserved at location E3" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 485 3016 4149 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Info: Pin ~nCSO~ is reserved at location D3" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 486 3016 4149 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { ~LVDS150p/nCEO~ } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS150p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 487 3016 4149 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} 11 | { "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Timing-driven compilation is using the Classic Timing Analyzer" { } { } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} 12 | { "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} 13 | { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50 (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CLOCK_50 (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 2 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 181 3016 4149 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1} 14 | { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Reset_Delay:r0\|oRESET " "Info: Automatically promoted node Reset_Delay:r0\|oRESET " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mLCD_RS~0 " "Info: Destination node mLCD_RS~0" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 41 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { mLCD_RS~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 224 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mLCD_ST~18 " "Info: Destination node mLCD_ST~18" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 37 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { mLCD_ST~18 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 225 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mLCD_ST~19 " "Info: Destination node mLCD_ST~19" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 37 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { mLCD_ST~19 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 294 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mLCD_ST~22 " "Info: Destination node mLCD_ST~22" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 37 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { mLCD_ST~22 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 303 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LUT_INDEX\[0\]~18 " "Info: Destination node LUT_INDEX\[0\]~18" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 70 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LUT_INDEX[0]~18 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 317 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mLCD_Start~2 " "Info: Destination node mLCD_Start~2" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 39 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { mLCD_Start~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 372 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mLCD_ST~25 " "Info: Destination node mLCD_ST~25" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 37 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { mLCD_ST~25 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 378 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mLCD_ST~26 " "Info: Destination node mLCD_ST~26" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 37 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { mLCD_ST~26 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 379 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mDLY\[8\]~22 " "Info: Destination node mDLY\[8\]~22" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 70 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { mDLY[8]~22 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 389 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "mLCD_DATA~1 " "Info: Destination node mLCD_DATA~1" { } { { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 40 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { mLCD_DATA~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 423 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" { } { } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1} } { { "../Safe Project/LCD_Reset_Delay.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/LCD_Reset_Delay.v" 1 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reset_Delay:r0|oRESET } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 73 3016 4149 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1} 15 | { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} 16 | { "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1} 17 | { "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1} 18 | { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0 -1} 19 | { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 -1} 20 | { "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 0 0 "" 0 -1} 21 | { "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 0 0 "" 0 -1} 22 | { "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} 23 | { "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} 24 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} 25 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} 26 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} 27 | { "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} 28 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} 29 | { "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.160 ns register register " "Info: Estimated most critical path is register to register delay of 4.160 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns correctPass 1 REG LAB_X35_Y16 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X35_Y16; Fanout = 5; REG Node = 'correctPass'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { correctPass } "NODE_NAME" } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 61 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.185 ns) + CELL(0.398 ns) 0.583 ns mLCD_ST~16 2 COMB LAB_X35_Y16 1 " "Info: 2: + IC(0.185 ns) + CELL(0.398 ns) = 0.583 ns; Loc. = LAB_X35_Y16; Fanout = 1; COMB Node = 'mLCD_ST~16'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.583 ns" { correctPass mLCD_ST~16 } "NODE_NAME" } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.150 ns) 1.148 ns mLCD_ST~17 3 COMB LAB_X35_Y16 20 " "Info: 3: + IC(0.415 ns) + CELL(0.150 ns) = 1.148 ns; Loc. = LAB_X35_Y16; Fanout = 20; COMB Node = 'mLCD_ST~17'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { mLCD_ST~16 mLCD_ST~17 } "NODE_NAME" } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.777 ns) + CELL(0.275 ns) 2.200 ns mLCD_ST~18 4 COMB LAB_X36_Y14 10 " "Info: 4: + IC(0.777 ns) + CELL(0.275 ns) = 2.200 ns; Loc. = LAB_X36_Y14; Fanout = 10; COMB Node = 'mLCD_ST~18'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.052 ns" { mLCD_ST~17 mLCD_ST~18 } "NODE_NAME" } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.438 ns) 2.765 ns mLCD_DATA\[7\]~0 5 COMB LAB_X36_Y14 9 " "Info: 5: + IC(0.127 ns) + CELL(0.438 ns) = 2.765 ns; Loc. = LAB_X36_Y14; Fanout = 9; COMB Node = 'mLCD_DATA\[7\]~0'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { mLCD_ST~18 mLCD_DATA[7]~0 } "NODE_NAME" } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 70 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.735 ns) + CELL(0.660 ns) 4.160 ns mLCD_DATA\[6\] 6 REG LAB_X36_Y16 1 " "Info: 6: + IC(0.735 ns) + CELL(0.660 ns) = 4.160 ns; Loc. = LAB_X36_Y16; Fanout = 1; REG Node = 'mLCD_DATA\[6\]'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.395 ns" { mLCD_DATA[7]~0 mLCD_DATA[6] } "NODE_NAME" } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 70 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.921 ns ( 46.18 % ) " "Info: Total cell delay = 1.921 ns ( 46.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.239 ns ( 53.82 % ) " "Info: Total interconnect delay = 2.239 ns ( 53.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.160 ns" { correctPass mLCD_ST~16 mLCD_ST~17 mLCD_ST~18 mLCD_DATA[7]~0 mLCD_DATA[6] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1} 30 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} 31 | { "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X33_Y12 X43_Y23 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X33_Y12 to location X43_Y23" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} 32 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} 33 | { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} 34 | { "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} 35 | { "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "17 " "Warning: Found 17 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[0\] 0 " "Info: Pin \"LCD_DATA\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[1\] 0 " "Info: Pin \"LCD_DATA\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[2\] 0 " "Info: Pin \"LCD_DATA\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[3\] 0 " "Info: Pin \"LCD_DATA\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[4\] 0 " "Info: Pin \"LCD_DATA\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[5\] 0 " "Info: Pin \"LCD_DATA\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[6\] 0 " "Info: Pin \"LCD_DATA\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[7\] 0 " "Info: Pin \"LCD_DATA\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[0\] 0 " "Info: Pin \"LEDG\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[1\] 0 " "Info: Pin \"LEDG\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR 0 " "Info: Pin \"LEDR\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_O 0 " "Info: Pin \"GPIO_O\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_ON 0 " "Info: Pin \"LCD_ON\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_BLON 0 " "Info: Pin \"LCD_BLON\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_RW 0 " "Info: Pin \"LCD_RW\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_EN 0 " "Info: Pin \"LCD_EN\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_RS 0 " "Info: Pin \"LCD_RS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} 36 | { "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} 37 | { "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "8 " "Warning: Following 8 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[0\] a permanently enabled " "Info: Pin LCD_DATA\[0\] has a permanently enabled output enable" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { LCD_DATA[0] } } } { "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_DATA[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 152 3016 4149 0} } } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[1\] a permanently enabled " "Info: Pin LCD_DATA\[1\] has a permanently enabled output enable" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { LCD_DATA[1] } } } { "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_DATA[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 153 3016 4149 0} } } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[2\] a permanently enabled " "Info: Pin LCD_DATA\[2\] has a permanently enabled output enable" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { LCD_DATA[2] } } } { "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_DATA[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 154 3016 4149 0} } } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[3\] a permanently enabled " "Info: Pin LCD_DATA\[3\] has a permanently enabled output enable" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { LCD_DATA[3] } } } { "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_DATA[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 155 3016 4149 0} } } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[4\] a permanently enabled " "Info: Pin LCD_DATA\[4\] has a permanently enabled output enable" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { LCD_DATA[4] } } } { "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_DATA[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 156 3016 4149 0} } } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[5\] a permanently enabled " "Info: Pin LCD_DATA\[5\] has a permanently enabled output enable" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { LCD_DATA[5] } } } { "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_DATA[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 157 3016 4149 0} } } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[6\] a permanently enabled " "Info: Pin LCD_DATA\[6\] has a permanently enabled output enable" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { LCD_DATA[6] } } } { "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_DATA[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 158 3016 4149 0} } } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[7\] a permanently enabled " "Info: Pin LCD_DATA\[7\] has a permanently enabled output enable" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { LCD_DATA[7] } } } { "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } { "../Safe Project/Safe.v" "" { Text "C:/Users/aluno/Desktop/Projeto CL2/Safe Project/Safe.v" 19 -1 0 } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_DATA[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/aluno/Desktop/Projeto CL2/Quartus/" 0 { } { { 0 { 0 ""} 0 159 3016 4149 0} } } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1} } { } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0 -1} 38 | { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "265 " "Info: Peak virtual memory: 265 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 30 16:12:31 2019 " "Info: Processing ended: Tue Apr 30 16:12:31 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} 39 | --------------------------------------------------------------------------------