├── .github ├── docker-compose.yml ├── jitx-client │ ├── Dockerfile │ └── user.params └── workflows │ └── test.yml ├── .gitignore ├── LICENSE ├── README.md ├── artwork ├── board-text.stanza ├── esd-symbol.stanza ├── flag.stanza ├── jitx-logo.stanza ├── voltage-symbol.stanza └── warning-symbol.stanza ├── components ├── abracon │ ├── ABM12-32-B2X-T3.stanza │ ├── AMB7.stanza │ ├── AMPM.stanza │ └── ASPI-0530HI.stanza ├── alpsalpine │ ├── SSSS811101.stanza │ └── SW-SMD_SSSS811101.wrl ├── american-opto │ └── L196L.stanza ├── amphenol │ ├── 10103594-0001LF.stanza │ ├── 112640.stanza │ ├── delta-d.stanza │ └── minitek127.stanza ├── analog-devices │ ├── AD7124-8BBCPZ.stanza │ ├── AD8429.stanza │ ├── ADA4004.stanza │ ├── ADG1408YCPZ-REEL7.stanza │ ├── ADM7150.stanza │ ├── ADM7154.stanza │ ├── ADP1720ARMZ-3-3-R7.stanza │ ├── LT3045.stanza │ └── LT3093.stanza ├── anaren │ └── X3C19E2-20S.stanza ├── avago │ └── ADNS9800.stanza ├── belfuse │ └── SS-52400-003.stanza ├── bencent │ └── BV05C.stanza ├── bosch │ └── BMX160.stanza ├── bourns │ └── CMH322522.stanza ├── changjiang-electronics-tech │ ├── 2N7002.stanza │ └── SS8050.stanza ├── cherry │ └── MX.stanza ├── citizen │ └── CMJ206T32768DZBT.stanza ├── cixi-kefa-elec │ └── KF350-3-5-2P.stanza ├── ck-switches │ ├── JS202011CQN.stanza │ └── PTS-540.stanza ├── cnc-tech │ └── _3020-xx-0300-00.stanza ├── connfly │ ├── DS1023-23SF11.stanza │ └── HDR-TH_6P-P2.54-V-F-R2-C3-S2.54.wrl ├── cree │ └── CLMUC-FK.stanza ├── cts │ └── 219.stanza ├── cui-devices │ └── PJ-002BH-SMT-TR.stanza ├── diodes-incorporated │ ├── AP2112.stanza │ ├── AP7365-33WG-7.stanza │ └── KN3270012.stanza ├── epson │ ├── FC-135.stanza │ └── TSX-3225.stanza ├── espressif │ ├── ESP32-PICO-D4.stanza │ ├── WIFI-SMD_ESP32-WROOM-32E.wrl │ └── esp32-wroom-32.stanza ├── everlight-elec │ ├── ELM-2001EWB-P17-Socket.stanza │ └── ELM-2001EWB-P17.stanza ├── fine-made │ └── SC1117-3-3V.stanza ├── foshan-optoelectronics │ └── FM-B2020RGBA-HG.stanza ├── fremont-micro-devices │ └── FT25H04.stanza ├── future-designs │ ├── FT232RL.stanza │ └── FT234XD.stanza ├── htcsemi │ └── HT1302A.stanza ├── hubei-kento-elec │ └── C2290.stanza ├── idt │ └── 5PB11xx.stanza ├── johanson │ ├── 2450AT18A100.stanza │ ├── 2450AT18D0100.stanza │ ├── 2450BM14G0011.stanza │ └── 2450FM07A0029.stanza ├── johnson │ ├── 142-0701-801.stanza │ └── 142-0761-881.stanza ├── jst │ ├── JST-BxxB-PASK.stanza │ └── S2B-PH-K-S.stanza ├── keystone │ ├── 500xx.stanza │ ├── 5017.stanza │ └── 82.stanza ├── kinghelm │ └── KH-2_54FH-1X6P-H8_5.stanza ├── korean-hroparts-elec │ ├── DC-182-25A.stanza │ ├── K2-1102SP-C4SC-04.stanza │ ├── TYPE-C-31-M-12.stanza │ ├── TYPE-C-31-M-23.stanza │ └── USB-C_SMD-TYPE-C-31-M-12.wrl ├── kyocera │ └── KC2520B.stanza ├── labjack │ └── T7.stanza ├── laird │ └── LI0805H151R-10.stanza ├── littelfuse │ └── SP0503BAHTG.stanza ├── marki │ └── MMIQ-0205HSM-2.stanza ├── marvell │ └── 88E1510-A0-NNB2C000.stanza ├── maxim │ ├── MAX1606x.stanza │ └── MAX300x.stanza ├── microchip │ ├── ATmega32U4.stanza │ ├── MCP7381x.stanza │ └── MCP9600.stanza ├── microsemi │ └── A2F200M3F-FGG256I.stanza ├── monolithic-power │ └── MPM3630.stanza ├── murata │ ├── BLM18HE152SN1D.stanza │ ├── LQM2HPN2R2MG0L.stanza │ ├── MM5829-2700R.stanza │ └── NCP03WF104F05RL.stanza ├── nexperia │ ├── BC846.stanza │ ├── PESD1CAN.stanza │ ├── PMBT3904.stanza │ └── PUSB3FR4.stanza ├── nordic │ ├── nRF52832.stanza │ └── nRF52840.stanza ├── on-semiconductor │ ├── BAS21LT1G.stanza │ ├── FDN352AP.stanza │ ├── MBR0520L.stanza │ ├── NCP30x.stanza │ └── NSR0240HT1G.stanza ├── phoenix │ └── combicon-mc.stanza ├── pomona │ └── 1581.stanza ├── pulse-electronics │ ├── J0G-0009NL.stanza │ └── P1167_183NLT.stanza ├── q-n-j │ └── CR2032-BS-6-1.stanza ├── qorvo │ └── QPL9065SR.stanza ├── raspberry-pi │ └── gpio-header.stanza ├── raytac │ └── MDBT50Q.stanza ├── samtec │ ├── ASP-134488-01.stanza │ ├── FTSH-105-01-D-RA.stanza │ ├── FTSH-105-01-DV.stanza │ └── QTH.stanza ├── semtech │ └── 1N4148W.stanza ├── shikues │ ├── BSN20.stanza │ └── SOT-23-3_L2.9-W1.6-P1.90-LS2.8-BR.wrl ├── si-labs │ ├── CP2102N.stanza │ ├── CP2105.stanza │ ├── Si862x.stanza │ └── Si864x.stanza ├── soberton │ └── GT-111P.stanza ├── st-microelectronics │ ├── LIS3DH.stanza │ ├── STM32F031F4P6.stanza │ ├── STM32F031F6P6.stanza │ ├── STM32F038G6U6.stanza │ ├── STM32F102C4T6A.stanza │ ├── STM32F102C6T6A.stanza │ ├── STM32F102R4T6A.stanza │ ├── STM32F102R6T6A.stanza │ ├── STM32F103RBH6.stanza │ ├── STM32F103T4U6A.stanza │ ├── STM32F103T6U6A.stanza │ ├── STM32F105V8H6.stanza │ ├── STM32F105VBH6.stanza │ ├── STM32F107VCH6.stanza │ ├── STM32F407ZET6.stanza │ ├── STM32L031F6P6.stanza │ ├── USBLC6-2SC6.stanza │ ├── VL53L1X.stanza │ ├── VL53L4CD.stanza │ ├── generate-ioc.stanza │ ├── landpatterns.stanza │ ├── stm-api.stanza │ └── supports │ │ ├── STM32F031F_4-6_Px.stanza │ │ ├── STM32F038G6Ux.stanza │ │ ├── STM32F102C_4-6_Tx.stanza │ │ ├── STM32F102R_4-6_Tx.stanza │ │ ├── STM32F103R_4-6_Hx.stanza │ │ ├── STM32F103R_8-B_Hx.stanza │ │ ├── STM32F103T_4-6_Ux.stanza │ │ ├── STM32F105V_8-B_Hx.stanza │ │ ├── STM32F107VCHx.stanza │ │ └── STM32L031F_4-6_Px.stanza ├── sunlord │ ├── GZ2012D601TF.stanza │ └── SWPA6045S1R8NT.stanza ├── tag-connect │ ├── TC2030-IDC-NL.stanza │ ├── TC2030-IDC.stanza │ ├── TC2050-IDC-NL.stanza │ └── TC2050-IDC.stanza ├── tdk │ └── MPZ1608.stanza ├── te-connectivity │ ├── 1825910-6.stanza │ ├── 2102735-1.stanza │ ├── 2102736-1.stanza │ ├── 2102771-1.stanza │ ├── 2102772-1.stanza │ └── RC.stanza ├── texas-instruments │ ├── BQ24075.stanza │ ├── BQ27441-G1.stanza │ ├── CC2640.stanza │ ├── FDC2214.stanza │ ├── HDC1080.stanza │ ├── ISO1540.stanza │ ├── SN6501.stanza │ ├── SN65HVD1781.stanza │ ├── SN65HVD1786.stanza │ ├── SN74LVC245A.stanza │ ├── SN74LVTH573PWR.stanza │ ├── TCAN1051.stanza │ ├── TLV62130.stanza │ ├── TLV743P.stanza │ ├── TMP75AIDR.stanza │ ├── TPD1E10B06.stanza │ ├── TPD3S0x4.stanza │ ├── TPS27081A.stanza │ ├── TPS54620RHLR.stanza │ ├── TPS610986.stanza │ ├── TPS65217.stanza │ └── TPS65988.stanza ├── toshiba │ ├── DF2B6M4ASL-L3F.stanza │ ├── TLP175A.stanza │ └── TLP3409S.stanza ├── ublox │ └── CAM-M8.stanza ├── unisonic │ ├── LM317A.stanza │ ├── TO-252-2_L6.5-W6.1-P4.58-LS10.0-TL.wrl │ └── U74LVC1G125G-AL5-R.stanza ├── windbond │ └── W25Q128JVSIQ.stanza ├── wurth │ ├── 691412320002M.stanza │ └── 760390012.stanza ├── xkb │ ├── TS-1187A-C-C-B.stanza │ ├── U263-241N-4BQC11-1.stanza │ └── USB-C-SMD_U263-241N-4BQC11-1.wrl └── yangxing-tech │ └── X322516MLB4SI.stanza ├── deprecated-tests ├── esir2-harness.stanza ├── multimap-test.stanza ├── rc-network.stanza ├── simple-boxes.stanza ├── stanza.proj ├── test-blank.stanza ├── test-bom.stanza ├── test-box-symbol.stanza ├── test-debug-utils.stanza ├── test-emodel-sym.stanza ├── test-node-removal.stanza ├── test-pinspec.stanza ├── test-powergen.stanza ├── test-refdb.stanza ├── test-simple-package.stanza └── test-user-checks.stanza ├── derating └── space-derating.stanza ├── designs ├── ble-mote.stanza ├── can-stm32.stanza ├── class-a.stanza ├── comprehensive-checks.stanza ├── doc-examples.stanza ├── ethernet-fmc.stanza ├── example-designs.md ├── grid-resistors.stanza ├── lp-examples.stanza ├── mcu.stanza ├── power-monitor.stanza ├── power-state-demo.stanza ├── run-checks │ ├── capacitors.stanza │ ├── checked-design.stanza │ ├── digital-io.stanza │ ├── inductors.stanza │ └── resistors.stanza ├── smd-landpatterns.stanza ├── stanza.proj ├── test-component-checks.stanza ├── tutorial.stanza ├── usb-accel.stanza ├── usb-light.stanza └── voltage-divider.stanza ├── doc └── generated-tests.md ├── manufacturers ├── rules.stanza └── stackups.stanza ├── modules ├── passive-circuits.stanza ├── power-regulators.stanza ├── protection.stanza ├── solvers │ └── voltage-divider.stanza └── terminations.stanza ├── ocdb.stanza ├── scripts ├── cubemx-importer-utils.stanza ├── cubemx-importer.stanza ├── cubemx-parser.stanza ├── evaluate_pcb_objects.py ├── gen-components-file.sh ├── gen-ocdb-app.stanza ├── kle-importer.stanza ├── ocdb-gen.stanza └── run-ocdb-tests.sh ├── slm.toml ├── stanza.proj ├── style-guide ├── fig │ ├── style-guide-01.png │ └── style-guide-02.png └── style-guide.md ├── tests ├── all.stanza ├── bom-related.stanza ├── bundle-connects.stanza ├── checks.stanza ├── connects.stanza ├── default-component.stanza ├── design.stanza ├── landpattern-generators.stanza ├── landpatterns.stanza ├── microcontroller.stanza ├── naming-conventions.stanza ├── pads.stanza ├── part-query.stanza ├── pin-properties-index-field.stanza ├── placeholder-components.stanza ├── pth-pads.stanza ├── relative-voltages.stanza ├── stm-pin-parsing.stanza ├── stm32-mcu-props.stanza ├── symbols.stanza ├── tag-connects.stanza ├── terminations.stanza └── th-landpatterns.stanza └── utils ├── box-symbol.stanza ├── bundles.stanza ├── calculate-connected.stanza ├── checks.stanza ├── connections.stanza ├── connects.stanza ├── db-parts.stanza ├── debug-utils.stanza ├── defaults.stanza ├── design-vars.stanza ├── fonts.stanza ├── generator-utils.stanza ├── generic-components.stanza ├── land-protrusions.stanza ├── landpatterns.stanza ├── mechanical.stanza ├── micro-controllers.stanza ├── module-utils.stanza ├── netlist-checks ├── all.stanza ├── io-checks.stanza ├── power-states.stanza ├── single-pin-nets.stanza └── utils.stanza ├── parts.stanza ├── passive-checks ├── capacitor-checks.stanza ├── inductor-checks.stanza ├── resistor-checks.stanza ├── resonator-checks.stanza └── utils.stanza ├── pin-checks ├── all.stanza ├── generic-pin-checks.stanza ├── power-pin-checks.stanza ├── reset-pin-checks.stanza └── utils.stanza ├── placeholder-components.stanza ├── propagation.stanza ├── property-structs.stanza ├── relative-voltages.stanza ├── stm-to-jitx.stanza ├── stm.stanza ├── symbol-utils.stanza ├── symbols.stanza └── voltage-propagation.stanza /.github/docker-compose.yml: -------------------------------------------------------------------------------- 1 | version: "3.1" 2 | 3 | services: 4 | jitx-client: 5 | build: jitx-client/ 6 | volumes: 7 | - /etc/machine-id:/etc/machine-id 8 | - ..:/app/open-components-database/ 9 | -------------------------------------------------------------------------------- /.github/jitx-client/Dockerfile: -------------------------------------------------------------------------------- 1 | FROM 657302324634.dkr.ecr.us-west-2.amazonaws.com/jitx-client:3.16.0 2 | # To pull this image locally, you need to authenticate with JITX's ECR assuming you have a jitx profile with credentials: 3 | # aws ecr --profile jitx get-login-password --region us-west-2 | docker login --username AWS --password-stdin 657302324634.dkr.ecr.us-west-2.amazonaws.com 4 | 5 | WORKDIR /app 6 | COPY ./user.params /root/.jitx/user.params 7 | COPY ./license /root/.jitx/license 8 | 9 | CMD ["/bin/bash", "-c", "cd open-components-database ; scripts/run-ocdb-tests.sh"] 10 | 11 | -------------------------------------------------------------------------------- /.github/jitx-client/user.params: -------------------------------------------------------------------------------- 1 | server : 2 | base-url = "https://app-testing.jitx.com" 3 | url = "https://app-testing.jitx.com/api/" 4 | 5 | bom : 6 | vendors = () 7 | -------------------------------------------------------------------------------- /.github/workflows/test.yml: -------------------------------------------------------------------------------- 1 | on: 2 | pull_request: 3 | workflow_dispatch: 4 | name: Check that esir definitions are valid 5 | 6 | jobs: 7 | evaluate-macros: 8 | name: Test macro validity 9 | runs-on: ubuntu-latest 10 | 11 | steps: 12 | - name: Checkout 13 | uses: actions/checkout@v2 14 | 15 | - name: Configure JITX's AWS credentials 16 | uses: aws-actions/configure-aws-credentials@v2 17 | with: 18 | aws-access-key-id: ${{ secrets.AWS_ACCESS_KEY_ID }} 19 | aws-secret-access-key: ${{ secrets.AWS_SECRET_ACCESS_KEY }} 20 | aws-region: ${{ secrets.AWS_REGION }} 21 | 22 | - name: Login to JITX's Amazon ECR 23 | id: login-jitx-ecr 24 | uses: aws-actions/amazon-ecr-login@v1 25 | 26 | - name: Evaluate public pcb-* macros + run unit-tests + run integration tests 27 | run: | 28 | # Excludes modules and only supports pcb-* macros that take 0 or 1 argument of primitive type 29 | cd .github/ 30 | # Expires April 6th 2022 (same as JITX CI) 31 | echo "${{ secrets.JITX_LICENSE }}" > jitx-client/license 32 | # Remove automatic end line (truncate last byte) at the end of the license file 33 | truncate -s -1 jitx-client/license 34 | docker compose up --exit-code-from jitx-client 35 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.sw* 2 | /.vscode/* 3 | .DS_Store 4 | pending*dat 5 | voltage-propagation-iteration* 6 | designs/output-* 7 | parts-db 8 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2020, JITx-Inc 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | 1. Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | 2. Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | 3. Neither the name of the copyright holder nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | -------------------------------------------------------------------------------- /components/abracon/ABM12-32-B2X-T3.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/abracon/ABM12-32-B2X-T3: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "Abracon" 19 | mpn = "ABM12-32.000MHZ-B2X-T3" 20 | description = "32MHz ±20ppm Crystal 8pF 200 Ohms 4-SMD, No Lead" 21 | port p : pin[[1 2]] 22 | port gnd 23 | val sym = crystal-sym(2) 24 | val pkg = XTAL-TSX-3225 25 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2], gnd => sym.gnd) 26 | landpattern = pkg(p[1] => pkg.p[2], p[2] => pkg.p[3], gnd => pkg.p[1], gnd => pkg.p[4]) 27 | reference-prefix = "X" 28 | 29 | property(self.crystal-resonator) = ocdb/utils/property-structs/CrystalResonator(8.0e-12, 5.0e-12, 20.0e-15, 200.0, 32.0e6, 50.0e-6, 100.0e-6) 30 | 31 | pcb-landpattern XTAL-TSX-3225 : 32 | for (i in 0 to 4, l in grid-locs(C, 2, 2, 2.2, 1.6)) do : 33 | pad p[i + 1] : smd-pad(1.4, 1.15) at loc(0.0, 0.0) * l 34 | layer(Courtyard(Top)) = Rectangle(3.6, 2.8) 35 | ref-label() 36 | -------------------------------------------------------------------------------- /components/abracon/ASPI-0530HI.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/abracon/ASPI-0530HI: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | import ocdb/utils/property-structs 17 | 18 | 19 | public pcb-component component (Ind:Double): 20 | manufacturer = "Abracon" 21 | description = "2.2µH Shielded Molded Inductor 5.5A 35mOhm Max " 22 | val code = switch(Ind) : 23 | 1.0 : "1R0" 24 | 1.5 : "1R5" 25 | 2.2 : "2R2" 26 | else : fatal("Invalid Inductance for ASPI-0530HI %_" % [Ind]) 27 | mpn = to-string("ASPI-0530HI-%_" % [code]) 28 | 29 | port p : pin[1 through 2] 30 | val pkg = two-pin-landpattern(5.99, 2.20, 2.5, 5.6, 5.2) 31 | val sym = inductor-sym() 32 | landpattern = pkg(p[1] => pkg.p[1], p[2] => pkg.p[2]) 33 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2]) 34 | reference-prefix = "L" 35 | 36 | property(self.rated-temperature) = min-max(-55.0, 125.0) 37 | 38 | 39 | ; public unique pcb-module module : 40 | -------------------------------------------------------------------------------- /components/american-opto/L196L.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/american-opto/L196L : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | ; 18 | color: "red" 19 | 20 | public pcb-component component (color:String): 21 | manufacturer = "American Opto Plus LED" 22 | val code = switch(color) : 23 | "red" : "UEC" 24 | "green" : "SGC" 25 | else : 26 | fatal("%_ is not a supported color for ocdb/components/american-opto/L196L" % [color]) 27 | 28 | mpn = to-string("L196L-%_-TR" % [code]) 29 | description = to-string("1.6 x 0.8 x 0.4 mm %_ SMD LED" % [color]) 30 | 31 | port a 32 | port c 33 | 34 | val sym = diode-sym(DiodeLED) 35 | symbol = sym(a => sym.a, c => sym.c) 36 | val land = two-pin-polarized-landpattern(2.3, 0.7, 0.8, 1.6, 0.8) 37 | landpattern = land(a => land.a, c => land.c) 38 | reference-prefix = "D" 39 | 40 | -------------------------------------------------------------------------------- /components/amphenol/112640.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/amphenol/112640 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/symbols 13 | import ocdb/utils/box-symbol 14 | 15 | public pcb-component component : 16 | name = "112640" 17 | manufacturer = "Amphenol RF" 18 | mpn = "112640" 19 | description = "CONN BNC JACK STR 50OHM EDGE MNT" 20 | pin-properties : 21 | [pin:Ref | pads:Int ... | side:Dir] 22 | [sig | 1 | Left] 23 | [gnd | 2 3 4 5 | Down] 24 | make-box-symbol() 25 | assign-landpattern(amphenol-112640-pkg) 26 | reference-prefix = "J" 27 | 28 | pcb-landpattern amphenol-112640-pkg : 29 | 30 | pad p[1] : smd-pad(S, 0.86, 4.72) at loc(0.0, 0.127) 31 | pad p[2] : smd-pad(S, 1.35, 4.72) at loc(4.925, 0.127) 32 | pad p[3] : smd-pad(S, 1.35, 4.72) at loc(-4.925, 0.127) 33 | pad p[4] : smd-pad(S, 1.7, 4.72) at loc(-4.46, 0.127) on Bottom 34 | pad p[5] : smd-pad(S, 1.7, 4.72) at loc(4.46, 0.127) on Bottom 35 | 36 | layer(Courtyard(Top)) = Rectangle(11.2, 5.0, loc(0.0, 2.36)) 37 | layer(Courtyard(Bottom)) = Rectangle(11.2, 5.0, loc(0.0, 2.36)) 38 | layer(BoardEdge())= Line(0.0, [Point(11.2 / -2.0, 0.0), Point(11.2 / 2.0, 0.0)]) 39 | 40 | ref-label() 41 | 42 | public pcb-module module : 43 | inst i : component 44 | -------------------------------------------------------------------------------- /components/amphenol/minitek127.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/amphenol/minitek127 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/symbols 13 | import ocdb/utils/box-symbol 14 | import ocdb/utils/property-structs 15 | 16 | ; 17 | n-pins: 6 8 10 12 14 16 18 20 18 | 19 | public pcb-component component (n-pins:Int) : 20 | name = to-string("Minitek127 %_x2 Header" % [n-pins / 2]) 21 | manufacturer = "Amphenol" 22 | val n-str = if n-pins < 10 : to-string("0%_" % [n-pins]) else: to-string(n-pins) 23 | mpn = to-string("20021321-000%_C4LF" % [n-str]) 24 | description = "SMD Female 1.27mm pitch header" 25 | port p : pin[1 through n-pins] 26 | val pkg = amphenol-minitek127-pkg(n-pins) 27 | val sym = header-symbol(n-pins, 2) 28 | landpattern = pkg(for i in 1 through n-pins do: p[i] => pkg.p[i]) 29 | symbol = sym(for i in 1 through n-pins do: p[i] => sym.p[i]) 30 | reference-prefix = "J" 31 | property(self.rated-temperature) = min-max(-40.0, 105.0) 32 | 33 | pcb-landpattern amphenol-minitek127-pkg (n-pins:Int) : 34 | if not contains?([6 8 10 12 14 16 18 20], n-pins): 35 | fatal("amphenol-minitek127-pkg only supports n-pins in [6 8 10 12 14 16 18 20]") 36 | val pitch = 1.27 37 | val y = (to-double(n-pins) - 2.0) / 2.0 * pitch + 1.73 38 | for (l in grid-locs(n-pins / 2, 2, 3.55, 1.27), i in 1 through n-pins) do : 39 | pad p[i] : smd-pad(2.05, 0.76) at l 40 | 41 | layer(Courtyard(Top)) = Rectangle(5.6, y) 42 | layer(Silkscreen("f-silk", Top)) = Union([symmetric-about-y([Line(0.1, [Point(-1.5, y / 2.0) Point(1.5, y / 2.0)])])]) 43 | layer(Silkscreen("pol", Top)) = Circle(-3.5, y / 2.0 - 0.865, 0.2) 44 | ref-label() 45 | -------------------------------------------------------------------------------- /components/analog-devices/AD8429.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/analog-devices/AD8429: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import ocdb/utils/defaults 8 | import ocdb/utils/landpatterns 9 | import ocdb/utils/generic-components 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import jitx/commands 14 | 15 | ; Amplifiers 16 | public pcb-component component : 17 | name = "AD8429" 18 | manufacturer = "Analog Devices" 19 | mpn = "AD8429BRZ-R7" 20 | description = "SP Amp INSTR Amp Single ±18V 8-Pin SOIC N T/R" 21 | pin-properties : 22 | [pin:Ref | pads:Int ... | side:Dir ] 23 | [in- | 1 | Left] 24 | [rg0 | 2 | Left] 25 | [rg1 | 3 | Left] 26 | [in+ | 4 | Left] 27 | [vout | 7 | Right] 28 | [ref | 6 | Right] 29 | [vs- | 5 | Down] 30 | [vs+ | 8 | Up] 31 | make-box-symbol() 32 | assign-landpattern(soic127p-landpattern(8)) 33 | 34 | public pcb-module module (gain:Double) : 35 | port vs+ 36 | port vs- 37 | port in+ 38 | port in- 39 | port vout 40 | port ref 41 | inst opa : ocdb/components/analog-devices/AD8429/component 42 | if gain < 1.0 : 43 | fatal("Unsupported gain %_ for AD8429" % [gain]) 44 | else if gain != 1.0 : 45 | val rg-val = 6.0e3 / (gain - 1.0) 46 | inst rg : chip-resistor(closest-std-val(rg-val, 0.1), 0.001) 47 | net (opa.rg0, rg.p[1]) 48 | net (opa.rg1, rg.p[2]) 49 | bypass-caps(vs+, ref, 35.0, [10.0e-6 0.1e-9], `vs+) 50 | bypass-caps(vs-, ref, 35.0, [10.0e-6 0.1e-9], `vs-) 51 | net (opa.in+, in+) 52 | net (opa.in-, in-) 53 | net (opa.vs+, vs+) 54 | net (opa.vs-, vs-) 55 | net (opa.vout, vout) 56 | net (opa.in+, in+) 57 | net (opa.ref, ref) 58 | 59 | public pcb-module module () : 60 | inst i : module(10.0) 61 | -------------------------------------------------------------------------------- /components/analog-devices/LT3045.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/analog-devices/LT3045: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generic-components 11 | import ocdb/utils/generator-utils 12 | import ocdb/utils/symbols 13 | import ocdb/utils/box-symbol 14 | 15 | public pcb-component component : 16 | name = "LT3045" 17 | manufacturer = "Analog Devices" 18 | mpn = "LT3045EDD-1" 19 | description = "20V, 500mA, Ultralow Noise, Ultrahigh PSRR Linear Regulator with VIOC Control" 20 | pin-properties : 21 | [pin:Ref | pads:Int ... | side:Dir ] 22 | [in | 1 2 | Left] 23 | [en | 4 | Left] 24 | [pg | 5 | Left] 25 | [set | 8 | Left] 26 | [vioc | 3 | Left] 27 | [ilim | 6 | Left] 28 | [out | 11 12 | Right] 29 | [outs | 10 | Right] 30 | [pgfb | 7 | Right] 31 | [gnd | 9 13 | Down] 32 | make-box-symbol() 33 | assign-landpattern(dfn-landpattern(12, 0.45, [0.25, 0.7], -1.4, [3.5, 3.0], [1.65, 2.38])) 34 | 35 | public pcb-module module (v-out:Double) : 36 | port vin 37 | port vout 38 | port gnd 39 | port en 40 | inst ps : ocdb/components/analog-devices/LT3045/component 41 | val r-set = v-out / 100.0e-6 42 | val r-fb = res-strap(ps.set, gnd, closest-std-val(r-set, 0.1)) 43 | val c0 = cap-strap(ps.set, gnd, 4.7e-6) 44 | val c1 = cap-strap(ps.in, gnd, ["capacitance" => 4.7e-6 "min-rated-voltage" => 30.0]) 45 | val c2 = cap-strap(ps.out, gnd, ["capacitance" => 4.7e-6 "min-rated-voltage" => 30.0]) 46 | ; short-trace(r-fb.p[1], ps.set) 47 | ; short-trace(r-fb.p[1], c0.p[1]) 48 | ; short-trace(c1.p[1], ps.in) 49 | ; short-trace(c2.p[1], ps.out) 50 | net (ps.en, en) 51 | net (ps.in, ps.pgfb, vin) 52 | net (ps.out, ps.outs, vout) 53 | net (ps.gnd, ps.ilim, gnd) 54 | 55 | public pcb-module module () : 56 | inst i : module(5.0) 57 | -------------------------------------------------------------------------------- /components/analog-devices/LT3093.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/analog-devices/LT3093: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generic-components 11 | import ocdb/utils/generator-utils 12 | import ocdb/utils/symbols 13 | import ocdb/utils/box-symbol 14 | 15 | public pcb-component component : 16 | name = "LT3093" 17 | manufacturer = "Analog Devices" 18 | mpn = "LT3093EDD" 19 | description = "–20V, 200mA, Ultralow Noise, Ultrahigh PSRR Negative Linear Regulator" 20 | pin-properties : 21 | [pin:Ref | pads:Int ... | side:Dir ] 22 | [in | 1 2 13 | Left] 23 | [en | 3 | Left] 24 | [pg | 4 | Left] 25 | [set | 8 | Left] 26 | [vioc | 7 | Left] 27 | [ilim | 6 | Left] 28 | [out | 11 12 | Right] 29 | [outs | 10 | Right] 30 | [pgfb | 5 | Right] 31 | [gnd | 9 | Down] 32 | make-box-symbol() 33 | assign-landpattern(dfn-landpattern(12, 0.45, [0.25, 0.7], -1.4, [3.5, 3.0], [1.65, 2.38])) 34 | 35 | public pcb-module module (v-out:Double) : 36 | port vin 37 | port vout 38 | port gnd 39 | port en 40 | inst ps : ocdb/components/analog-devices/LT3093/component 41 | val r-set = v-out / -100.0e-6 42 | val r-fb = res-strap(ps.set, gnd, closest-std-val(r-set, 0.1)) 43 | val c0 = cap-strap(ps.set, gnd, 4.7e-6) 44 | val c1 = cap-strap(ps.in, gnd, ["capacitance" => 4.7e-6 "min-rated-voltage" => 30.0]) 45 | val c2 = cap-strap(ps.out, gnd, ["capacitance" => 4.7e-6 "min-rated-voltage" => 30.0]) 46 | ; short-trace(r-fb.p[1], ps.set) 47 | ; short-trace(r-fb.p[1], c0.p[1]) 48 | ; short-trace(c1.p[1], ps.in) 49 | ; short-trace(c2.p[1], ps.out) 50 | net (ps.en, en) 51 | net (ps.in, ps.pgfb, vin) 52 | net (ps.out, ps.outs, vout) 53 | net (ps.gnd, ps.ilim, gnd) 54 | 55 | public pcb-module module () : 56 | inst i : module(-5.0) 57 | -------------------------------------------------------------------------------- /components/anaren/X3C19E2-20S.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/anaren/X3C19E2-20S: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/symbols 13 | import ocdb/utils/box-symbol 14 | 15 | public pcb-component component : 16 | name = "X3C19E2-20S" 17 | manufacturer = "Anaren" 18 | mpn = "X3C19E2-20S" 19 | description = "RF DIR COUPLER 1.4GHZ-2.7GHZ SMD" 20 | pin-properties : 21 | [pin:Ref | pads:Int ... | side:Dir] 22 | [p[1] | 1 | Left] 23 | [p[2] | 2 | Right] 24 | [p[3] | 3 | Right] 25 | [p[4] | 4 | Left] 26 | [gnd | 5 | Down] 27 | make-box-symbol() 28 | assign-landpattern(X3C19E2-20S-pkg) 29 | 30 | pcb-landpattern X3C19E2-20S-pkg : 31 | val dx = 11.43 / 2.0 + 1.55 / 2.0 32 | val dy = 2.29 / 2.0 + 1.55 / 2.0 33 | pad p[1] : smd-pad(1.55, 1.55) at loc((- dx), dy) 34 | pad p[2] : smd-pad(1.55, 1.55) at loc(dx, dy) 35 | pad p[3] : smd-pad(1.55, 1.55) at loc(dx, (- dy)) 36 | pad p[4] : smd-pad(1.55, 1.55) at loc((- dx), (- dy)) 37 | pad p[5] : smd-pad(10.15, 5.08) at loc(0.0, 0.0) 38 | 39 | layer(Courtyard(Top)) = Rectangle(14.75, 5.5) 40 | layer(Silkscreen("pol", Top)) = Circle((- dx), dy + 1.5, 0.254) 41 | 42 | ref-label() 43 | 44 | public pcb-module module : 45 | inst i : component 46 | -------------------------------------------------------------------------------- /components/bencent/BV05C.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/bencent/BV05C : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | 9 | import ocdb/utils/defaults 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/symbol-utils 13 | import ocdb/utils/generic-components 14 | import ocdb/utils/bundles 15 | import ocdb/utils/box-symbol 16 | 17 | 18 | import ocdb/utils/property-structs 19 | import ocdb/utils/generator-utils 20 | import ocdb/utils/checks 21 | 22 | pcb-landpattern SOD323-lp : 23 | pad p[1] : smd-pad(1.06, 0.54) at loc(-1.07, 0.0) 24 | pad p[2] : smd-pad(1.06, 0.54) at loc(1.07, 0.0) 25 | layer(Courtyard(Top)) = Rectangle(3.6, 1.6) 26 | layer(Silkscreen("f-silk", Top)) = Line(0.12, [ Point(-1.9, -0.75), Point(-1.9, 0.0) ]) 27 | ref-label() 28 | 29 | public pcb-component component : 30 | port a 31 | port c 32 | manufacturer = "Bencent" 33 | description = "5V 6V Bidirectional 9.8V 1A (8/20us) SOD-323 TVS ROHS" 34 | mpn = "BV05C" 35 | reference-prefix = "D" 36 | datasheet = "https://datasheet.lcsc.com/lcsc/1912111437_Bencent-BV05C_C409434.pdf" 37 | val sym = diode-sym(DiodeZener) 38 | symbol = sym(a => sym.a, c => sym.c) 39 | val land = SOD323-lp 40 | landpattern = land(a => land.p[1], c => land.p[2]) 41 | 42 | property(self.rated-temperature) = min-max(-40.0, 85.0) 43 | -------------------------------------------------------------------------------- /components/bourns/CMH322522.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/bourns/CMH322522 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import jitx/emodels 9 | import ocdb/utils/defaults 10 | 11 | import ocdb/utils/landpatterns 12 | import ocdb/utils/symbols 13 | import ocdb/utils/box-symbol 14 | import ocdb/utils/bundles 15 | import ocdb/utils/generator-utils 16 | import ocdb/utils/generic-components 17 | 18 | ; 19 | ind: 18.0e-6 20 | 21 | public pcb-component component (ind:Double) : 22 | manufacturer = "Bourns" 23 | name = "CMH322522" 24 | mpn = 25 | switch(ind) : 26 | 18.0e-6 : 27 | "CMH322522-180KL" 28 | else : 29 | fatal("Unsupported or unconfirmed part variant: %_ H" % [ind]) 30 | description = "FIXED IND 18UH 120MA 3.3 OHM SMD" 31 | emodel = Inductor(ind, 0.1, 0.12) 32 | 33 | port p : pin[[1 2]] 34 | 35 | val sym = inductor-sym() 36 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2]) 37 | val land = ind-pkg 38 | landpattern = land(p[1] => land.p[1], p[2] => land.p[2]) 39 | reference-prefix = "I" 40 | 41 | pcb-landpattern ind-pkg : 42 | pad p[1] : smd-pad(1.2, 2.0) at loc((-1.6), 0.0) 43 | pad p[2] : smd-pad(1.2, 2.0) at loc(1.6, 0.0) 44 | -------------------------------------------------------------------------------- /components/changjiang-electronics-tech/2N7002.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/changjiang-electronics-tech/2N7002 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | import ocdb/utils/property-structs 17 | 18 | public pcb-component component : 19 | manufacturer = "Changjiang-Electronics-Tech" 20 | description = "Changjiang-Electronics-Tech 2N7002" 21 | datasheet = "https://datasheet.lcsc.com/lcsc/1810151612_Changjiang-Electronics-Tech--CJ-2N7002_C8545.pdf" 22 | mpn = "2N7002" 23 | port d 24 | port s 25 | port g 26 | reference-prefix = "Q" 27 | val pkg = SOT23() 28 | val sym = fet-sym() 29 | landpattern = pkg(d => pkg.p[3], s => pkg.p[2], g => pkg.p[1]) 30 | symbol = sym(d => sym.d, s => sym.s, g => sym.g) 31 | property(self.rated-temperature) = min-max(-40.0, 85.0) 32 | -------------------------------------------------------------------------------- /components/changjiang-electronics-tech/SS8050.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/changjiang-electronics-tech/SS8050 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | 15 | import ocdb/utils/property-structs 16 | import ocdb/utils/checks 17 | 18 | public pcb-component component : 19 | manufacturer = "Changjiang Electronics Tech (CJ)" 20 | mpn = "SS8050" 21 | description = "1.5A 0.3W NPN 25V SOT-23(SOT-23-3) Bipolar Transistors - BJT ROHS" 22 | port b 23 | port e 24 | port c 25 | reference-prefix = "Q" 26 | val pkg = SOT95P280X100-3N 27 | val sym = bjt-sym(BJTNpn) 28 | landpattern = pkg(b => pkg.p[1], e => pkg.p[2], c => pkg.p[3]) 29 | symbol = sym(b => sym.b, c => sym.c, e => sym.e) 30 | property(self.rated-temperature) = min-max(-40.0, 85.0) 31 | -------------------------------------------------------------------------------- /components/cixi-kefa-elec/KF350-3-5-2P.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/cixi-kefa-elec/KF350-3-5-2P : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | 9 | import ocdb/utils/defaults 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/symbol-utils 13 | import ocdb/utils/generic-components 14 | import ocdb/utils/bundles 15 | import ocdb/utils/box-symbol 16 | import ocdb/utils/property-structs 17 | 18 | pcb-landpattern conn-lp : 19 | pad p[1] : pth-pad(0.5) at loc(-1.75, 0.0) 20 | pad p[2] : pth-pad(0.5) at loc(1.75, 0.0) 21 | 22 | layer(Courtyard(Top)) = Rectangle(7.0, 7.0) 23 | layer(Silkscreen("f-silk", Top)) = LineRectangle(7.0, 7.0) 24 | layer(Silkscreen("f-silk", Top)) = Line(0.12, [ Point(-3.5, -3.5), Point(-3.0, -4.0), Point(-2.5, -3.5) ]) 25 | ref-label() 26 | 27 | public pcb-component component : 28 | port h : pin[[1 through 2]] 29 | ; Datasheet = https://datasheet.lcsc.com/lcsc/2001160007_Cixi-Kefa-Elec-KF350-3.5-2P_C474892.pdf 30 | manufacturer = "Cixi Kefa Elec" 31 | description = "CONN, TH, SCREW TERMINAL, 3.50mm, KF350-3.5-2P" 32 | mpn = "KF350-3.5-2P" 33 | pin-properties : 34 | [pin:Ref | pads:Int ... | side:Dir] 35 | [h[2] | 2 | Left] 36 | [h[1] | 1 | Left] 37 | make-box-symbol() 38 | assign-landpattern(conn-lp) 39 | supports power: 40 | power.vdd => self.h[2] 41 | power.gnd => self.h[1] 42 | property(self.rated-temperature) = min-max(-20.0, 70.0) 43 | -------------------------------------------------------------------------------- /components/ck-switches/JS202011CQN.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/ck-switches/JS202011CQN : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | pcb-landpattern switch-package : 18 | ; The grid-locs function makes generating m x n grids of pads easy 19 | for (l in grid-locs(2, 3, 2.5, 3.3), i in [4 5 6 1 2 3]) do : 20 | pad p[i] : pth-pad(0.45) at l 21 | 22 | layer(Courtyard(Top)) = Rectangle(9.0, 3.6) 23 | layer(Silkscreen("f-silk", Top)) = LineRectangle(9.1, 3.7) 24 | ref-label() 25 | 26 | public pcb-component component : 27 | manufacturer = "C&K Switches" 28 | description = "Slide Switch DPDT Through Hole" 29 | mpn = "JS202011CQN" 30 | 31 | ; Use unified generator to create pins 32 | port p : pin[[1 through 2]] 33 | port t : pin[[1 through 4]] 34 | 35 | val sym = spst(2, 4) 36 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2], t[1] => sym.t[1], t[2] => sym.t[2], t[3] => sym.t[3], t[4] => sym.t[4]) 37 | val land = switch-package 38 | landpattern = land(p[1] => land.p[2], p[2] => land.p[5], t[1] => land.p[1], t[2] => land.p[3], t[3] => land.p[4], t[4] => land.p[6]) 39 | -------------------------------------------------------------------------------- /components/ck-switches/PTS-540.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | ; Include space before colon in definitions 3 | defpackage ocdb/components/ck-switches/PTS-540 : 4 | import core 5 | import collections 6 | import math 7 | import jitx 8 | import jitx/commands 9 | import ocdb/utils/defaults 10 | 11 | import ocdb/utils/landpatterns 12 | import ocdb/utils/symbols 13 | import ocdb/utils/box-symbol 14 | import ocdb/utils/bundles 15 | import ocdb/utils/generator-utils 16 | import ocdb/utils/generic-components 17 | 18 | pcb-landpattern sw-landpattern : 19 | ; The grid-locs function makes generating m x n grids of pads easy 20 | for (l in grid-locs(2, 2, 3.1, 2.75), i in [3 4 1 2]) do : 21 | pad p[i] : smd-pad(0.6, 0.65) at l 22 | 23 | layer(Courtyard(Top)) = Rectangle(3.7, 3.7) 24 | layer(Silkscreen("f-silk", Top)) = LineRectangle(3.7, 3.7) 25 | ref-label() 26 | 27 | public pcb-component component : 28 | manufacturer = "C&K Switches" 29 | description = "Tactile Switch" 30 | mpn = "PTS540-JM035-SMTR-LFS" 31 | 32 | ; Use unified generator to create pins 33 | port p : pin[1 through 4] 34 | 35 | val sym = spst(2, 2) 36 | symbol = sym(p[1] => sym.t[1], p[2] => sym.t[2], p[3] => sym.p[1], p[4] => sym.p[2]) 37 | landpattern = sw-landpattern(p[1] => sw-landpattern.p[1], p[2] => sw-landpattern.p[2], p[3] => sw-landpattern.p[3], p[4] => sw-landpattern.p[4]) 38 | 39 | public pcb-module module : 40 | ; Define pins or ports to externally interface with other modules 41 | port pwr : power 42 | port button 43 | 44 | inst sw : ocdb/components/ck-switches/PTS-540/component 45 | inst r : chip-resistor(1.0e6) 46 | net (button, sw.p[1], sw.p[2]) 47 | net (pwr.gnd, sw.p[3], sw.p[4]) 48 | net (r.p[1], sw.p[1]) 49 | net (pwr.vdd, r.p[2]) 50 | -------------------------------------------------------------------------------- /components/connfly/DS1023-23SF11.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/connfly/DS1023-23SF11 : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/box-symbol 8 | import ocdb/utils/landpatterns 9 | 10 | pcb-pad circle-th-pad : 11 | type = TH 12 | shape = Circle(0.8) 13 | layer(SolderMask(Top)) = Circle(0.8) 14 | layer(SolderMask(Bottom)) = Circle(0.8) 15 | layer(Cutout()) = Circle(0.5) 16 | 17 | pcb-pad rect-th-pad : 18 | type = TH 19 | shape = Rectangle(1.7, 1.6) 20 | layer(SolderMask(Top)) = Rectangle(1.7, 1.6) 21 | layer(SolderMask(Bottom)) = Rectangle(1.7, 1.6) 22 | layer(Cutout()) = Circle(0.5) 23 | 24 | public pcb-landpattern HDR-TH_6P-P254-V-F-R2-C3-S254-3 : 25 | pad p[1] : rect-th-pad at loc(-2.540005, -1.270003) on Top 26 | pad p[2] : circle-th-pad at loc(-2.540005, 1.270003) on Top 27 | pad p[3] : circle-th-pad at loc(0.0, -1.270003) on Top 28 | pad p[4] : circle-th-pad at loc(0.0, 1.270003) on Top 29 | pad p[5] : circle-th-pad at loc(2.540005, -1.270003) on Top 30 | pad p[6] : circle-th-pad at loc(2.540005, 1.270003) on Top 31 | 32 | ref-label() 33 | 34 | model3d = Model3D("HDR-TH_6P-P2.54-V-F-R2-C3-S2.54.wrl", 35 | Vec3D(0.0, 0.0, 0.0), 36 | Vec3D(1.0, 1.0, 1.0), 37 | Vec3D(0.0, 0.0, 0.0)) 38 | 39 | public pcb-component component : 40 | description = "Header-Female-2_54_2x3" 41 | mpn = "DS1023-2*3SF11" 42 | manufacturer = "CONNFLY Elec" 43 | pin-properties : 44 | [pin:Ref | pads:Ref ... | side:Dir ] 45 | [p[1] | p[1] | Left ] 46 | [p[2] | p[2] | Right ] 47 | [p[3] | p[3] | Left ] 48 | [p[4] | p[4] | Right ] 49 | [p[5] | p[5] | Left ] 50 | [p[6] | p[6] | Right ] 51 | 52 | assign-landpattern(HDR-TH_6P-P254-V-F-R2-C3-S254-3) 53 | make-box-symbol() 54 | reference-prefix = "J" 55 | 56 | property(self.LCSC) = "C92272" 57 | datasheet = "https://item.szlcsc.com/562474.html" 58 | 59 | -------------------------------------------------------------------------------- /components/cree/CLMUC-FK.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | ; Include space before colon in definitions 3 | defpackage ocdb/components/cree/CLMUC-FK : 4 | import core 5 | import collections 6 | import math 7 | import jitx 8 | import jitx/commands 9 | import ocdb/utils/defaults 10 | 11 | import ocdb/utils/landpatterns 12 | import ocdb/utils/symbols 13 | import ocdb/utils/box-symbol 14 | import ocdb/utils/bundles 15 | import ocdb/utils/generator-utils 16 | import ocdb/utils/generic-components 17 | 18 | pcb-landpattern package-rgb : 19 | for (l in grid-locs(2, 2, 1.14, 0.7), i in [1 4 2 3]) do: 20 | pad p[i] : smd-pad(0.55, 0.45) at l 21 | 22 | layer(Courtyard(Top)) = Rectangle(1.7, 1.7) 23 | layer(Silkscreen("f-silk", Top)) = LineRectangle(1.7, 1.7) 24 | ref-label() 25 | 26 | ; Group together pins that can be easily named where it makes sense 27 | ; and create a bundle in bundles.stanza. 28 | 29 | public pcb-component component : 30 | manufacturer = "Cree" 31 | mpn = "CLMUC-FKA-CL8LCFL5L8BB79353" 32 | description = "3 in 1 RGB SMD LED" 33 | 34 | ; Use unified generator to create pins 35 | port rgb-led : rgb-led 36 | symbol = diode-rgb-led(rgb-led.a => diode-rgb-led.a, rgb-led.r => diode-rgb-led.r, rgb-led.g => diode-rgb-led.g, 37 | rgb-led.b => diode-rgb-led.b) 38 | landpattern = package-rgb(rgb-led.a => package-rgb.p[1], rgb-led.r => package-rgb.p[2], 39 | rgb-led.g => package-rgb.p[3], rgb-led.b => package-rgb.p[4]) 40 | 41 | public pcb-module module : 42 | ; Define pins or ports to externally interface with other modules 43 | port rgb-led : rgb-led 44 | port vcc 45 | inst led : ocdb/components/cree/CLMUC-FK/component 46 | inst r-res : chip-resistor(470.0) 47 | inst g-res : chip-resistor(330.0) 48 | inst b-res : chip-resistor(100.0) 49 | 50 | net (led.rgb-led.r, r-res.p[1]) 51 | net (led.rgb-led.g, g-res.p[1]) 52 | net (led.rgb-led.b, b-res.p[1]) 53 | 54 | net (rgb-led.r, r-res.p[2]) 55 | net (rgb-led.g, g-res.p[2]) 56 | net (rgb-led.b, b-res.p[2]) 57 | net (vcc, rgb-led.a) 58 | -------------------------------------------------------------------------------- /components/cts/219.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/cts/219 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/box-symbol 14 | import ocdb/utils/symbols 15 | 16 | public pcb-component component (n-sw:Int): 17 | manufacturer = "CTS Electrocomponents" 18 | mpn = to-string("219-%_MSTR"%[n-sw]) 19 | description = "SWITCH SLIDE DIP SPST 100MA 20V" 20 | port sw : pin[n-sw][2] 21 | pin-properties : 22 | [pin:Ref | pads:Int ... | side:Dir] 23 | for i in 0 to n-sw do : 24 | [sw[i][0] | (2 * i + 1) | Left] 25 | [sw[i][1] | (2 * i + 2) | Right] 26 | 27 | make-box-symbol() 28 | assign-landpattern(cts-219-pkg(n-sw)) 29 | 30 | for i in 0 to n-sw do : 31 | supports SPST : 32 | SPST.p => self.sw[i][0] 33 | SPST.t => self.sw[i][1] 34 | reference-prefix = "SW" 35 | 36 | pcb-landpattern cts-219-pkg (n-sw:Int) : 37 | 38 | val n-col = n-sw 39 | val n-row = 2 40 | val row-pitch = 8.6 41 | val pin-pitch = 2.54 42 | 43 | val l0 = loc((to-double(n-row - 1) * row-pitch) / -2.0, (to-double(n-col - 1) * pin-pitch) / 2.0) 44 | 45 | for i in 0 to n-col do : 46 | for j in 0 to n-row do : 47 | pad p[n-row * i + j + 1] : smd-pad(2.44, 1.13) at l0 * loc(to-double(j) * row-pitch, (- to-double(i) * pin-pitch)) 48 | 49 | val c-w = 11.04 50 | val c-h = to-double(n-col - 1) * 2.54 + 1.13 + 5.14 51 | layer(Silkscreen("f-silk", Top)) = LineRectangle(c-w, c-h) 52 | layer(Courtyard(Top)) = Rectangle(c-w, c-h) 53 | ref-label() 54 | -------------------------------------------------------------------------------- /components/cui-devices/PJ-002BH-SMT-TR.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/cui-devices/PJ-002BH-SMT-TR : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | 9 | import ocdb/utils/defaults 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/symbol-utils 13 | import ocdb/utils/generic-components 14 | import ocdb/utils/bundles 15 | import ocdb/utils/box-symbol 16 | 17 | import ocdb/utils/property-structs 18 | import ocdb/utils/generator-utils 19 | import ocdb/utils/checks 20 | 21 | pcb-landpattern plug-lp : 22 | pad p[1] : smd-pad(2.8, 2.4) at loc( 5.00, 2.40 / 2.00 + 4.50) ; 1.9 + 4.9 23 | pad p[4] : smd-pad(2.8, 2.4) at loc( 11.10, 2.40 / 2.00 + 4.50) 24 | pad p[2] : smd-pad(2.8, 2.4) at loc( 5.00, 2.40 / 2.00 - 6.90) 25 | pad p[3] : smd-pad(2.8, 2.4) at loc( 11.10, 2.40 / 2.00 - 6.90) 26 | 27 | layer(Cutout()) = Circle(Point( 5.00, 0.00), 1.70 / 2.0) 28 | layer(Cutout()) = Circle(Point( 9.50, 0.00), 1.85 / 2.0) 29 | 30 | layer(Courtyard(Top)) = Rectangle(14.8, 12.6, loc(7.40, 0.00)) 31 | layer(Silkscreen("f-silk", Top)) = LineRectangle(8.90, 6.50, 8.90 / 2.00, 0.00) 32 | ; layer(Silkscreen("f-silk", Top)) = Circle(Point( 0.00, 0.00), 1.25) 33 | ; layer(Silkscreen("f-silk", Top)) = Circle(Point( 0.00, 0.00), 3.20) 34 | ; ;layer(Silkscreen("f-silk", Top)) = LineRectangle(7.0, 7.0) 35 | ;layer(Silkscreen("f-silk", Top)) = Line(0.12, [ Point(-3.5, -3.5), Point(-3.0, -4.0), Point(-2.5, -3.5) ]) 36 | ref-label() 37 | 38 | public pcb-component component : 39 | port p : pin[[1 through 3]] 40 | manufacturer = "CUI Devices" 41 | description = "Power Barrel Connector Jack 2.50mm ID (0.098\"), 5.50mm OD (0.217\") Surface Mount, Right Angle" 42 | datasheet = "https://www.cuidevices.com/product/resource/pj-002bh-smt-tr.pdf" 43 | mpn = "PJ-002BH-SMT-TR" 44 | pin-properties : 45 | [pin:Ref | pads:Int ... | side:Dir] 46 | [p[1] | 1 4 | Right ] 47 | [p[2] | 2 | Down ] 48 | [p[3] | 3 | Left ] 49 | make-box-symbol() 50 | assign-landpattern(plug-lp) 51 | supports power: 52 | power.vdd => self.p[1] 53 | power.gnd => self.p[2] 54 | property(self.rated-temperature) = min-max(-20.0, 70.0) 55 | -------------------------------------------------------------------------------- /components/diodes-incorporated/AP2112.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/diodes-incorporated/AP2112: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | import ocdb/utils/property-structs 16 | 17 | public pcb-component component : 18 | name = "AP2112" 19 | manufacturer = "Diodes Incorporated" 20 | description = "600-mA, Low-Dropout Regulator" 21 | mpn = "AP2112K-3.3TRG1" 22 | pin-properties : 23 | [pin:Ref | pads:Int ... | side:Dir | generic-pin:GenericPin] 24 | [GND | 2 | Down | -] 25 | [VOUT | 5 | Right | GenericPin(min-max(0.0, 6.0), 4.0e3)] 26 | [VIN | 1 | Left | GenericPin(min-max(0.0, 6.0), 4.0e3)] 27 | [VEN | 3 | Left | GenericPin(min-max(0.0, 6.0), 4.0e3)] 28 | [nc | 4 | Down | -] 29 | make-box-symbol() 30 | assign-landpattern(SOT95P280X145-5N) 31 | 32 | property(self.VOUT.power-supply-pin) = PowerSupplyPin(typ(3.3), 0.6) 33 | property(self.VIN.power-pin) = PowerPin(min-max(3.7, 6.5)) 34 | property(self.rated-temperature) = min-max(-40.0, 85.0) 35 | property(self.VOUT.voltage) = tol%(3.3, 1.5) 36 | 37 | public pcb-module module : 38 | port vin : power 39 | port vout : power 40 | port gnd 41 | port en 42 | public inst ps : ocdb/components/diodes-incorporated/AP2112/component 43 | bypass-cap-strap(ps.VIN, gnd, 1.0e-6) 44 | bypass-cap-strap(ps.VOUT, gnd, 1.0e-6) 45 | net (vin.vdd, ps.VIN) 46 | net (ps.VOUT vout.vdd) 47 | net (gnd, ps.GND vout.gnd vin.gnd) 48 | net (en, ps.VEN) 49 | 50 | schematic-group(self) = AP2112 51 | -------------------------------------------------------------------------------- /components/diodes-incorporated/AP7365-33WG-7.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/diodes-incorporated/AP7365-33WG-7: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | import ocdb/utils/property-structs 16 | 17 | public pcb-component component : 18 | port VEN 19 | port GND 20 | port VIN 21 | port VOUT 22 | port nc 23 | name = "AP7365-33WG-7" 24 | manufacturer = "Diodes Incorporated" 25 | description = "600-mA, Low-Dropout Regulator" 26 | mpn = "AP7365-33WG-7" 27 | pin-properties : 28 | [pin:Ref | pads:Int ... | side:Dir | generic-pin:GenericPin] 29 | [GND | 2 | Down | -] 30 | [VOUT | 5 | Right | GenericPin(min-max(0.0, 6.0), 4.0e3)] 31 | [VIN | 1 | Left | GenericPin(min-max(0.0, 6.0), 4.0e3)] 32 | [VEN | 3 | Left | GenericPin(min-max(0.0, 6.0), 4.0e3)] 33 | [nc | 4 | Down | -] 34 | make-box-symbol() 35 | assign-landpattern(SOT95P280X145-5N) 36 | 37 | property(VOUT.power-supply-pin) = PowerSupplyPin(typ(3.3), 0.6) 38 | property(VIN.power-pin) = PowerPin(min-max(2.0, 6.0)) 39 | property(self.rated-temperature) = min-max(-40.0, 85.0) 40 | 41 | public pcb-module module : 42 | port vin : power 43 | port vout : power 44 | port gnd 45 | port en 46 | public inst ps : ocdb/components/diodes-incorporated/AP7365-33WG-7/component 47 | bypass-cap-strap(ps.VIN, gnd, 1.0e-6) 48 | bypass-cap-strap(ps.VOUT, gnd, 1.0e-6) 49 | net (vin.vdd, ps.VIN) 50 | net (ps.VOUT vout.vdd) 51 | net (gnd, ps.GND vout.gnd vin.gnd) 52 | net (en, ps.VEN) 53 | 54 | schematic-group(self) = AP7365-33WG-7 55 | -------------------------------------------------------------------------------- /components/diodes-incorporated/KN3270012.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/diodes-incorporated/KN3270012 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | 9 | import ocdb/utils/defaults 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/symbol-utils 13 | import ocdb/utils/generic-components 14 | import ocdb/utils/box-symbol 15 | import ocdb/utils/bundles 16 | import ocdb/utils/property-structs 17 | 18 | pcb-landpattern osc-lp : 19 | val padx = 1.8 20 | val pady = 2.0 21 | val padlocx = 2.2 22 | val padlocy = 2.54 23 | pad p[1] : smd-pad(padx, pady) at loc(-1.0 * padlocx, -1.0 * padlocy, 0.0) 24 | pad p[2] : smd-pad(padx, pady) at loc( padlocx, -1.0 * padlocy, 0.0) 25 | pad p[3] : smd-pad(padx, pady) at loc(padlocx, padlocy, 0.0) 26 | pad p[4] : smd-pad(padx, pady) at loc(-1.0 * padlocx, padlocy, 0.0) 27 | 28 | layer(Courtyard(Top)) = Rectangle(7.5, 7.5) 29 | layer(Silkscreen("f-silk", Top)) = Line(0.12, [ Point(-3.8, -3.5), Point(-3.8, -1.5) ]) 30 | ref-label() 31 | 32 | public pcb-component component : 33 | pin-properties : 34 | [pin:Ref| pads:Ref ... | side:Dir] 35 | [OE | p[1] | Left] 36 | [GND | p[2] | Down] 37 | [OUT | p[3] | Right] 38 | [VDD | p[4] | Up] 39 | supports power: 40 | power.vdd => self.VDD 41 | power.gnd => self.GND 42 | manufacturer = "Diodes Inc." 43 | description = "3.3V, 7.0x5.0mm, 32.768kHz CMOS Crystal Oscillator" 44 | datasheet = "https://datasheet.lcsc.com/lcsc/1811082113_Korean-Hroparts-Elec-K2-1102SP-C4SC-04_C127509.pdf" 45 | mpn = "KN3270012" 46 | assign-landpattern(osc-lp) 47 | make-box-symbol() 48 | property(self.rated-temperature) = min-max(-20.0, 70.0) 49 | -------------------------------------------------------------------------------- /components/epson/FC-135.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/epson/FC-135 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | pcb-landpattern xtal-2-3215 : 18 | for (l in grid-locs(1, 2, 2.5, 0.0), i in [1 2]) do : 19 | pad p[i] : smd-pad(1.0, 1.8) at l 20 | 21 | ; Ensure any pads don't breach the courtyard 22 | layer(Courtyard(Top)) = Rectangle(3.5, 1.8) 23 | ref-label() 24 | 25 | public pcb-component component : 26 | name = "32.768kHz Crystal" 27 | description = "CRYSTAL 32.7680KHZ 7PF SMD" 28 | manufacturer = "Epson" 29 | mpn = "FC-135 32.768KA-AG0" 30 | 31 | port p : pin[[1 2]] 32 | 33 | val sym = crystal-sym(0) 34 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2]) 35 | landpattern = xtal-2-3215(p[1] => xtal-2-3215.p[1], p[2] => xtal-2-3215.p[2]) 36 | 37 | property(self.crystal-resonator) = ocdb/utils/property-structs/CrystalResonator(7.0e-12, 1.0e-12, 3.4e-15, 70.0e3, 32.768e3, 20.0e-6, 0.5e-6) 38 | 39 | public pcb-module module : 40 | inst i : component 41 | -------------------------------------------------------------------------------- /components/fine-made/SC1117-3-3V.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/fine-made/SC1117-3-3V : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | 9 | import ocdb/utils/defaults 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/symbol-utils 13 | import ocdb/utils/generic-components 14 | import ocdb/utils/bundles 15 | import ocdb/utils/box-symbol 16 | import ocdb/utils/property-structs 17 | 18 | pcb-landpattern SOT223-lp : 19 | pad p[1] : smd-pad(1.2, 1.6) at loc(-2.3, -3.2) 20 | pad p[2] : smd-pad(1.2, 1.6) at loc(0.0, -3.2) 21 | pad p[3] : smd-pad(1.2, 1.6) at loc(2.3, -3.2) 22 | pad p[4] : smd-pad(3.3, 1.6) at loc(0.0, 3.2) 23 | layer(Courtyard(Top)) = Rectangle(6.8, 8.2) 24 | layer(Silkscreen("f-silk", Top)) = Line(0.12, [ Point(-3.4, -3.2), Point(-3.4, -4.0) ]) 25 | ref-label() 26 | 27 | public pcb-component component : 28 | port IN 29 | port GND 30 | port OUT 31 | val pkg = SOT223-lp 32 | val generic-props = GenericPin(min-max(-0.3, 3.6), 1500.0) 33 | val power-props = PowerPin(min-max(3.1, 3.5)) ; best interpretation 34 | val power-in = PowerPin(min-max(4.0, 7.0)) 35 | pin-properties : 36 | [pin:Ref | pads:Int ... | side:Dir| generic-pin:GenericPin | power-pin:PowerPin] 37 | [IN | 3 | Left | - | power-in ] 38 | [GND | 1 | Down | generic-props | - ] 39 | [OUT | 2 4 | Right | - | power-props ] 40 | name = "3.3V LDO" 41 | reference-prefix = "U" 42 | manufacturer = "Fine Made" 43 | description = "3.3V LDO" 44 | datasheet = "https://datasheet.lcsc.com/lcsc/2105181504_Shenzhen-Fuman-Elec-SC1117-3.3V_C173386.pdf" 45 | mpn = "SC1117-3.3V / AMS1117" 46 | supports power: 47 | power.vdd => self.OUT 48 | power.gnd => self.GND 49 | make-box-symbol() 50 | assign-landpattern(pkg) 51 | 52 | property(self.rated-temperature) = min-max(-40.0, 85.0) 53 | -------------------------------------------------------------------------------- /components/foshan-optoelectronics/FM-B2020RGBA-HG.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/foshan-optoelectronics/FM-B2020RGBA-HG : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/bundles 13 | import ocdb/utils/generator-utils 14 | import ocdb/utils/generic-components 15 | import ocdb/utils/property-structs 16 | 17 | public pcb-component component : 18 | manufacturer = "Foshan NationStar Optoelectronics" 19 | description = "2020 RGB LED" 20 | mpn = "FM-B2020RGBA-HG" 21 | 22 | port l : rgb-led 23 | 24 | val sym = diode-rgb-led 25 | val pkg = rgb-2020 26 | symbol = sym(l.r => sym.r, l.g => sym.g, l.b => sym.b, l.a => sym.a) 27 | landpattern = pkg(l.r => pkg.p[1], l.g => pkg.p[3], l.b => pkg.p[2], l.a => pkg.p[4]) 28 | 29 | property(l.r.max-current) = 20.0e-3 30 | property(l.r.forward-voltage) = 2.0 31 | property(l.r.color) = "red" 32 | property(l.r.mcd-current) = [[0.0 0.0] [68.75 10.0e-3]] 33 | 34 | property(l.g.max-current) = 20.0e-3 35 | property(l.g.forward-voltage) = 3.0 36 | property(l.g.color) = "green" 37 | property(l.g.mcd-current) = [[0.0 0.0] [300.0 10.0e-3]] 38 | 39 | property(l.b.max-current) = 20.0e-3 40 | property(l.b.forward-voltage) = 3.0 41 | property(l.b.color) = "blue" 42 | property(l.b.mcd-current) = [[0.0 0.0] [83.0 10.0e-3]] 43 | 44 | property(self.rated-temperature) = min-max(-30.0, 85.0) 45 | 46 | 47 | pcb-landpattern rgb-2020 : 48 | for (l in grid-locs(2, 2, 1.7, 1.1), i in 1 through 4) do : 49 | pad p[i] : smd-pad(0.8, 0.7) at l 50 | 51 | layer(Courtyard(Top)) = Rectangle(2.5, 1.8) 52 | layer(Silkscreen("pol", Top)) = Circle(-1.6, 0.55, 0.2) 53 | ref-label() 54 | -------------------------------------------------------------------------------- /components/fremont-micro-devices/FT25H04.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/fremont-micro-devices/FT25H04 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "Fremont Micro Devices" 19 | mpn = "FT25H04S" 20 | description = "4M-bit Serial Flash - SPI" 21 | port spi : spi-peripheral() 22 | 23 | pin-properties : 24 | [pin:Ref | pads:Int ... | side:Dir ] 25 | [spi.cs | 1 | Left ] 26 | [spi.sdo | 2 | Left ] 27 | [NC | 3, 7 | Down ] 28 | [VSS | 4 | Left ] 29 | [spi.sdi | 5 | Right ] 30 | [spi.sck | 6 | Right ] 31 | [VCC | 8 | Right ] 32 | 33 | make-box-symbol() 34 | assign-landpattern(sop65-landpattern(8)) 35 | 36 | public pcb-module module : 37 | port pwr : power 38 | port spi : spi-peripheral() 39 | inst flash : ocdb/components/fremont-micro-devices/FT25H04/component 40 | net (pwr.gnd, flash.VSS) 41 | net (pwr.vdd, flash.VCC) 42 | net (flash.spi spi) 43 | cap-strap(flash.VCC, flash.VSS, 0.1e-6) 44 | res-strap(flash.CS, flash.VCC, 100.0e3) 45 | -------------------------------------------------------------------------------- /components/hubei-kento-elec/C2290.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/hubei-kento-elec/C2290 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | 9 | import ocdb/utils/defaults 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/symbol-utils 13 | import ocdb/utils/generic-components 14 | import ocdb/utils/property-structs 15 | 16 | public pcb-component component : 17 | port a 18 | port c 19 | ; Datasheet = https://datasheet.lcsc.com/lcsc/1809041711_Hubei-KENTO-Elec-C2290_C2290.pdf If 20mA Vf 2.7-3.0V 0603 C2290 20 | manufacturer = "Hubei-KENTO-Elec" 21 | description = "LED WHITE 0603 If 20mA Vf 2.7-3.0V" 22 | mpn = "C2290" 23 | val sym = diode-sym(DiodeLED) 24 | symbol = sym(a => sym.a, c => sym.c) 25 | val land = ipc-two-pin-landpattern("0603", true) 26 | landpattern = land(a => land.a, c => land.c) 27 | reference-prefix = "D" 28 | property(self.rated-temperature) = min-max(-40.0, 85.0) 29 | 30 | ; two-pin-chip-landpattern (length:Toleranced, 31 | ; width:Toleranced, 32 | ; lead-length:Toleranced, 33 | ; density-level:DensityLevel, 34 | ; polarized?:True|False): -------------------------------------------------------------------------------- /components/johanson/2450AT18A100.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/johanson/2450AT18A100 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | pcb-landpattern johanson-2450AT18A100-pkg : 18 | make-two-pin-landpattern(4.2, 2.6, 1.6, 4.2, 1.6) 19 | layer(Silkscreen("pol", Top)) = Line(0.25, [Point(-2.25, -0.3), Point(-2.25, 0.3)]) 20 | layer(ForbidCopper(LayerIndex(0), LayerIndex(0, Bottom))) = Rectangle(7.0, 10.0) 21 | layer(Courtyard(Top)) = Rectangle(7.0, 10.0) 22 | ref-label() 23 | 24 | public pcb-component component : 25 | manufacturer = "Johanson Technology" 26 | mpn = "2450AT18A100E" 27 | description = "2.4-2.5 GHz Antenna" 28 | 29 | port feed 30 | port nc 31 | 32 | landpattern = johanson-2450AT18A100-pkg(feed => johanson-2450AT18A100-pkg.p[1], nc => johanson-2450AT18A100-pkg.p[2]) 33 | val sym = antenna-symbol(1, 1) 34 | symbol = sym(feed => sym.p[1], nc => sym.p[2]) 35 | 36 | public pcb-module module : 37 | inst i : component 38 | -------------------------------------------------------------------------------- /components/johanson/2450AT18D0100.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/johanson/2450AT18D0100 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | pcb-landpattern antenna-landpattern : 18 | for (l in grid-locs(2, 2, 3.0, 1.3), i in [4 3 1 2]) do : 19 | pad p[i] : smd-pad(1.0, 0.6) at l 20 | 21 | layer(Courtyard(Top)) = Rectangle(4.0, 1.9) 22 | layer(Silkscreen("f-silk", Top)) = LineRectangle(4.0, 1.9) 23 | ref-label() 24 | 25 | public pcb-component component : 26 | manufacturer = "Johanson Technology" 27 | description = "2.4-2.5 GHz Antenna" 28 | mpn = "2450AT18D0100" 29 | 30 | port p : pin[1 through 4] 31 | 32 | landpattern = antenna-landpattern(p[1] => antenna-landpattern.p[1], p[2] => antenna-landpattern.p[2], 33 | p[3] => antenna-landpattern.p[3], p[4] => antenna-landpattern.p[4]) 34 | val sym = antenna-symbol(1, 3) 35 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2], p[3] => sym.p[3], p[4] => sym.p[4]) 36 | 37 | public pcb-module module : 38 | inst i : component 39 | -------------------------------------------------------------------------------- /components/johanson/2450BM14G0011.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/johanson/2450BM14G0011 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | pcb-landpattern balun-landpattern : 18 | for (l in grid-locs(2, 3, 0.5, 0.82), i in [3 2 1 4 5 6]) do : 19 | pad p[i] : smd-pad(0.25, 0.45) at l 20 | 21 | layer(Courtyard(Top)) = Rectangle(1.8, 1.27) 22 | layer(Silkscreen("f-silk", Top)) = LineRectangle(1.8, 1.27) 23 | ref-label() 24 | 25 | public pcb-component component : 26 | manufacturer = "Johanson Technology" 27 | description = "2.4GHz Impedance Matched Balun + Embedded FCC/ETSI Band Pass Filter for TI CC2640" 28 | mpn = "2450BM14G0011" 29 | 30 | pin-properties : 31 | [pin:Ref | pads:Int ... | side:Dir ] 32 | [UBAL | 1 | Right ] 33 | [GND | 5, 6 | Down ] 34 | [BAL1 | 3 | Left ] 35 | [BAL2 | 4 | Left ] 36 | [NC | 2 | Left ] 37 | 38 | make-box-symbol() 39 | assign-landpattern(balun-landpattern) 40 | 41 | public pcb-module module : 42 | inst i : component 43 | -------------------------------------------------------------------------------- /components/johanson/2450FM07A0029.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/johanson/2450FM07A0029 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | pcb-landpattern johanson-2450FM07A0029-pkg : 18 | make-two-pin-landpattern(1.825, 0.625, 0.6, 1.825, 0.6) 19 | layer(Silkscreen("pol", Top)) = Line(0.25, [Point(-1.0, -0.3), Point(-1.0, 0.3)]) 20 | pad p[3] : smd-pad(0.3, 1.45) at loc(0.0, 0.0) 21 | ref-label() 22 | 23 | public pcb-component component : 24 | manufacturer = "Johanson Technology" 25 | mpn = "2450FM07A0029" 26 | description = "Low pass filter for nRF52" 27 | pin-properties : 28 | [pin:Ref | pads:Int ... | side:Dir] 29 | [in | 1 | Left] 30 | [out | 2 | Right] 31 | [gnd | 3 | Down] 32 | make-box-symbol() 33 | assign-landpattern(johanson-2450FM07A0029-pkg) 34 | 35 | public pcb-module module : 36 | inst i : component 37 | -------------------------------------------------------------------------------- /components/johnson/142-0701-801.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/johnson/142-0701-801: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | 16 | public pcb-component component : 17 | name = "142-0701-801" 18 | manufacturer = "Johnson / Cinch Connectivity Solutions" 19 | mpn = "142-0701-801" 20 | description = "RF Connectors / Coaxial Connectors END LAUNCH .042 PCB GOLD" 21 | pin-properties : 22 | [pin:Ref | pads:Int ... | side:Dir] 23 | [sig | 1 | Left] 24 | [gnd | 2 3 4 5 | Down] 25 | make-box-symbol() 26 | assign-landpattern(johnson-142-0701-801-pkg) 27 | reference-prefix = "J" 28 | 29 | pcb-landpattern johnson-142-0701-801-pkg : 30 | 31 | pad p[1] : smd-pad(2.286, 5.08) at loc(0.0, 2.54) 32 | pad p[2] : smd-pad(2.413, 5.08) at loc(-4.3815, 2.54) 33 | pad p[3] : smd-pad(2.413, 5.08) at loc(4.3815, 2.54) 34 | pad p[4] : smd-pad(2.413, 5.08) at loc(-4.3815, 2.54) on Bottom 35 | pad p[5] : smd-pad(2.413, 5.08) at loc(4.3815, 2.54) on Bottom 36 | 37 | layer(Courtyard(Top)) = Rectangle(11.2, 5.1, loc(0.0, 2.55)) 38 | layer(Courtyard(Bottom)) = Rectangle(11.2, 5.1, loc(0.0, 2.55)) 39 | layer(BoardEdge())= Line(0.0, [Point(11.2 / 2.0, 5.5), Point(11.2 / -2.0, 5.5)]) 40 | 41 | ref-label() 42 | 43 | public pcb-module module : 44 | inst i : component 45 | -------------------------------------------------------------------------------- /components/johnson/142-0761-881.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/johnson/142-0761-881: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | import ocdb/utils/property-structs 16 | 17 | 18 | public pcb-component component : 19 | name = "142-0761-881" 20 | manufacturer = "Johnson / Cinch Connectivity Solutions" 21 | mpn = "142-0761-881" 22 | description = "SMA Connector Jack, Female Socket 50Ohm Board Edge, End Launch; Through Hole, Right Angle Solder" 23 | pin-properties : 24 | [pin:Ref | pads:Int ... | side:Dir] 25 | [sig | 1 | Left] 26 | [gnd | 2 3 4 5 6 7| Down] 27 | assign-symbol(coax-sym) 28 | assign-landpattern(johnson-142-0761-881-pkg) 29 | reference-prefix = "J" 30 | property(self.rated-temperature) = min-max(-65.0, 165.0) 31 | 32 | 33 | 34 | pcb-landpattern johnson-142-0761-881-pkg : 35 | val w = (8.128 - 0.9144) / 2.0 36 | pad p[1] : smd-pad(N, 0.4064, 5.53) at loc(0.0, 0.0) 37 | pad p[2] : smd-pad(N, w, 5.53) at loc(-2.26, 0.0) 38 | pad p[3] : smd-pad(N, w, 5.53) at loc(2.26, 0.0) 39 | pad p[4] : pth-pad(0.5715, 0.71) at loc(1.2192, -1.7526) 40 | pad p[5] : pth-pad(0.5715, 0.71) at loc(-1.2192, -1.7526) 41 | pad p[6] : pth-pad(0.5715, 0.71) at loc(1.2192, -3.9624) 42 | pad p[7] : pth-pad(0.5715, 0.71) at loc(-1.2192, -3.9624) 43 | 44 | layer(Courtyard(Top)) = Rectangle(8.18, 5.54, loc(0.0, -2.769)) 45 | layer(BoardEdge())= Line(0.0, [Point(8.18 / 2.0, 0.0), Point(8.18 / -2.0, 0.0)]) 46 | 47 | 48 | ref-label() 49 | 50 | public pcb-module module : 51 | inst i : component 52 | -------------------------------------------------------------------------------- /components/jst/JST-BxxB-PASK.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/jst/JST-BxxB-PASK : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/symbols 11 | import ocdb/utils/symbol-utils 12 | import ocdb/utils/generic-components 13 | import ocdb/utils/bundles 14 | import ocdb/utils/box-symbol 15 | import ocdb/utils/property-structs 16 | 17 | ; 18 | n-pin: 2 19 | B: 2.54 20 | 21 | public pcb-landpattern JST-BxxB-PASK-pkg (n-pin:Int, B:Double) : 22 | val offset-x = (5.3 / 2.0) - (1.7 + 0.8 / 2.0) ;Connector Dims 23 | make-pin-grid(n-pin, 1, 2.0, 0.0, pth-pad(0.4), offset-x, 0.0) 24 | layer(Courtyard(Top)) = Rectangle(5.4, B + 0.1) 25 | layer(Silkscreen("F-SilkS", Top)) = Line(0.2, [ 26 | Point(5.3 / 2.0 + 0.1, B / 2.0), 27 | Point(5.3 / 2.0 + 0.1, B / 2.0 - 0.8) 28 | ]) 29 | ref-label() 30 | 31 | ; 32 | n-pin: 2 33 | 34 | public pcb-component component (n-pin:Int): 35 | var first-part : String = "B" 36 | var A = to-double((n-pin -2) * 2) + 2.0 37 | var B = to-double(n-pin * 2) + 2.0 38 | if (n-pin < 2 or n-pin > 16): 39 | println("Invalid n-pins for JST-BxxB-PASK/component: %_. n-pin must be in range [2, 16]") 40 | 41 | if n-pin < 10: 42 | first-part = "B0" 43 | pin-properties : 44 | [pin:Ref | pads:Int ... | side:Dir] 45 | for i in 1 through n-pin do : 46 | [p[i] | i | Left] 47 | else: 48 | pin-properties : 49 | [pin:Ref | pads:Int ... | side:Dir] 50 | for i in 1 through n-pin by 2 do : 51 | [p[i] | i | Left] 52 | [p[i + 1] | (i + 1) | Right] 53 | 54 | reference-prefix = "J" 55 | name = string-join(["JST ", first-part, n-pin, "B-PASK Top Entry TH"]) 56 | mpn = string-join([first-part n-pin "B-PASK-1(LF)(SN)"]) 57 | assign-landpattern(JST-BxxB-PASK-pkg(n-pin, B)) 58 | make-box-symbol() 59 | -------------------------------------------------------------------------------- /components/jst/S2B-PH-K-S.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/jst/S2B-PH-K-S: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | port p : pin[[1 2]] 19 | 20 | val sym = header-symbol(2, 1) 21 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2]) 22 | val land = jst-2-pkg 23 | landpattern = land(p[1] => land.p[1], p[2] => land.p[2]) 24 | 25 | 26 | pcb-landpattern jst-2-pkg : 27 | val n-pin = 2 28 | val n-row = 2 29 | val pin-pitch = 2.0 30 | val row-pitch = 2.0 31 | make-pin-grid(n-pin, n-row, pin-pitch, row-pitch, pth-pad(0.7)) 32 | 33 | val n-col = to-int(ceil(to-double(n-pin) / to-double(n-row))) 34 | 35 | val c-w = to-double(n-row) * row-pitch 36 | val c-h = to-double(n-col) * pin-pitch 37 | 38 | layer(Courtyard(Top)) = Rectangle(6.0, 8.0, loc(0.0, 2.2)) 39 | layer(Courtyard(Bottom)) = Rectangle(c-w, c-h) 40 | layer(Silkscreen("f-silk", Top)) = LineRectangle(c-w, c-h) 41 | 42 | ref-label() -------------------------------------------------------------------------------- /components/keystone/500xx.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/keystone/500xx : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | import ocdb/utils/property-structs 15 | 16 | public pcb-component component (color:String) : 17 | name = "500xx" 18 | manufacturer = "Keystone Electronics" 19 | mpn = switch(color) : 20 | "red" : "5000" 21 | "black" : "5001" 22 | "white" : "5002" 23 | "orange" : "5003" 24 | "yellow" : "5004" 25 | description = "Circuit Board Hardware - PCB TEST POINT" 26 | port p 27 | landpattern = keystone-500x-pkg(p => keystone-500x-pkg.p) 28 | reference-prefix = "J" 29 | symbol = test-point-sym(p => test-point-sym.p) 30 | property(self.rated-temperature) = min-max(-50.0, 145.0) 31 | 32 | 33 | pcb-landpattern keystone-500x-pkg : 34 | 35 | pad p : pth-pad(1.02 / 2.0) at loc(0.0, 0.0) 36 | 37 | layer(Courtyard(Top)) = Rectangle(2.54, 2.54) 38 | layer(Courtyard(Bottom)) = Rectangle(2.54, 2.54) 39 | 40 | ref-label() 41 | -------------------------------------------------------------------------------- /components/keystone/5017.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/keystone/5017: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | 15 | public pcb-component component: 16 | port p 17 | manufacturer = "Keystone Electronics" 18 | mpn = "5017" 19 | description = "Circuit Board Hardware - PCB TEST POINT" 20 | landpattern = keystone-5017-pkg(p => keystone-5017-pkg.p) 21 | symbol = test-point-sym(p => test-point-sym.p) 22 | reference-prefix = "J" 23 | 24 | pcb-landpattern keystone-5017-pkg : 25 | 26 | pad p : smd-pad(3.43, 1.78) at loc(0.0, 0.0) 27 | 28 | layer(Courtyard(Top)) = Rectangle(3.43, 1.78) 29 | 30 | ref-label() 31 | -------------------------------------------------------------------------------- /components/keystone/82.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/keystone/82 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | pcb-landpattern batt-clip-landpattern : 18 | val pth-pad = pth-pad(0.905) 19 | pad pos[1] : pth-pad at loc((- 13.715), 0.0) 20 | pad pos[2] : pth-pad at loc((- 21.335), 0.0) 21 | pad neg[1] : pth-pad at loc(13.715, 0.0) 22 | pad neg[2] : pth-pad at loc(21.335, 0.0) 23 | layer(Courtyard(Top)) = Rectangle(50.0, 10.0) 24 | layer(Silkscreen("f-silk", Top)) = LineRectangle(50.0, 10.0) 25 | ref-label() 26 | 27 | public pcb-component component : 28 | manufacturer = "Keystone Electronics" 29 | description = "AAA PC Battery Clip" 30 | mpn = "82" 31 | 32 | port pos : pin[[1 2]] 33 | port neg : pin[[1 2]] 34 | 35 | landpattern = batt-clip-landpattern(pos[1] => batt-clip-landpattern.pos[1], pos[2] => batt-clip-landpattern.pos[2], 36 | neg[1] => batt-clip-landpattern.neg[1], neg[2] => batt-clip-landpattern.neg[2]) 37 | val sym = header-symbol(4, 2) 38 | symbol = sym(pos[1] => sym.p[1], pos[2] => sym.p[2], neg[1] => sym.p[3], neg[2] => sym.p[4]) 39 | 40 | public pcb-module module : 41 | inst i : component 42 | -------------------------------------------------------------------------------- /components/kinghelm/KH-2_54FH-1X6P-H8_5.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/kinghelm/KH-2_54FH-1X6P-H8_5 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | import ocdb/utils/property-structs 16 | 17 | pcb-landpattern lp-KH-2_54FH-1X6P-H8_5: 18 | defn make-pad (r:Int) : 19 | val x = to-double(r) * 2.54 20 | pad p[r] : pth-pad(1.02 / 2.0) at loc(x, 0.0) 21 | 22 | for c in 0 to 6 do : 23 | make-pad(c) 24 | 25 | layer(Courtyard(Top)) = Rectangle(7.0 * 2.54, 3.0, loc(2.5 * 2.54, 0.0)) 26 | layer(Silkscreen("f-silk", Top)) = LineRectangle(7.0 * 2.54, 3.0, 2.5 * 2.54, 0.0) 27 | ref-label() 28 | 29 | 30 | public pcb-component component: 31 | name = "KH-2.54FH-1X6P-H8.5" 32 | manufacturer = "Kinghelm" 33 | mpn = "KH-2.54FH-1X6P-H8.5" 34 | description = "2.54mm 3A -40℃~+105℃ Straight 1x6P 8.5mm Top 6 1 Square Holes Straight,P=2.54mm Female Headers ROHS" 35 | datasheet = "https://datasheet.lcsc.com/lcsc/2110191530_Shenzhen-Kinghelm-Elec-KH-2-54FH-1X6P-H8-5_C2905416.pdf" 36 | 37 | pin-properties : 38 | [pin:Ref | pads:Int ... | side:Dir] 39 | for c in 0 to 6 do : 40 | [ p[c] | c | Right] 41 | reference-prefix = "J" 42 | 43 | make-box-symbol() 44 | assign-landpattern(lp-KH-2_54FH-1X6P-H8_5) 45 | -------------------------------------------------------------------------------- /components/korean-hroparts-elec/DC-182-25A.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/korean-hroparts-elec/DC-182-25A : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | 9 | import ocdb/utils/defaults 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/symbol-utils 13 | import ocdb/utils/generic-components 14 | import ocdb/utils/bundles 15 | import ocdb/utils/property-structs 16 | import ocdb/utils/box-symbol 17 | 18 | pcb-landpattern plug-lp : 19 | pad p[1] : smd-pad(3.6, 3.8) at loc( -6.80, 0.00) ; 1.9 + 4.9 20 | pad p[2] : smd-pad(2.8, 4.4) at loc( -1.45, -7.00) 21 | pad p[3] : smd-pad(2.8, 7.0) at loc( 4.65, -5.50) 22 | 23 | layer(Cutout()) = Circle(Point( 4.825, 0.45), 1.10) 24 | layer(Cutout()) = Circle(Point( -4.825, -4.15), 1.10) 25 | 26 | layer(Courtyard(Top)) = Rectangle(15.5, 15.0) 27 | layer(Silkscreen("f-silk", Top)) = Circle(Point( 0.00, 0.00), 1.25) 28 | layer(Silkscreen("f-silk", Top)) = Circle(Point( 0.00, 0.00), 3.20) 29 | ;layer(Silkscreen("f-silk", Top)) = LineRectangle(7.0, 7.0) 30 | ;layer(Silkscreen("f-silk", Top)) = Line(0.12, [ Point(-3.5, -3.5), Point(-3.0, -4.0), Point(-2.5, -3.5) ]) 31 | ref-label() 32 | 33 | public pcb-component component : 34 | port p : pin[[1 through 3]] 35 | datasheet = "https://datasheet.lcsc.com/lcsc/1810121720_Korean-Hroparts-Elec-DC-182-25A_C145920.pdf" 36 | manufacturer = "Korean Hroparts Elec" 37 | description = "2.5mm 6.4mm 13.35*9mm AC/DC Power Plugs & Receptacles ROHS" 38 | mpn = "DC-182-25A" 39 | pin-properties : 40 | [pin:Ref | pads:Int ... | side:Dir] 41 | [p[1] | 1 | Right ] 42 | [p[2] | 2 | Down ] 43 | [p[3] | 3 | Left ] 44 | make-box-symbol() 45 | assign-landpattern(plug-lp) 46 | supports power: 47 | power.vdd => self.p[1] 48 | power.gnd => self.p[2] 49 | property(self.rated-temperature) = min-max(-20.0, 70.0) 50 | -------------------------------------------------------------------------------- /components/korean-hroparts-elec/K2-1102SP-C4SC-04.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/korean-hroparts-elec/K2-1102SP-C4SC-04 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | 9 | import ocdb/utils/defaults 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/symbol-utils 13 | import ocdb/utils/generic-components 14 | 15 | import ocdb/utils/property-structs 16 | import ocdb/utils/generator-utils 17 | import ocdb/utils/checks 18 | 19 | pcb-landpattern switch-lp : 20 | val padx = 11.0 - 7.2 ; 3.8 21 | val padloc = ( 7.2 / 2.0) + (padx / 2.0) 22 | pad p[1] : smd-pad(padx, 1.0) at loc(-1.0 * padloc, 2.25, 0.0) 23 | pad p[2] : smd-pad(padx, 1.0) at loc(-1.0 * padloc, -2.25, 0.0) 24 | pad p[3] : smd-pad(padx, 1.0) at loc(padloc, -2.25, 0.0) 25 | pad p[4] : smd-pad(padx, 1.0) at loc(padloc, 2.25, 0.0) 26 | 27 | layer(Courtyard(Top)) = Rectangle((2.0 * padloc) + padx + 0.5, 6.4) 28 | layer(Silkscreen("f-silk", Top)) = LineRectangle(6.0, 6.0) 29 | ref-label() 30 | 31 | public pcb-component component : 32 | port p : pin[[1 through 4]] 33 | datasheet = "https://datasheet.lcsc.com/lcsc/1811082113_Korean-Hroparts-Elec-K2-1102SP-C4SC-04_C127509.pdf" 34 | manufacturer = "Korean Hroparts Elec" 35 | description = "Top Actuated 50mA @ 12VDC Round Button SPST 6*6mm Tactile Switches ROHS" 36 | mpn = "K2-1102SP-C4SC-04" 37 | reference-prefix = "S" 38 | val sym = spst(2, 2) 39 | symbol = sym(p[1] => sym.p[1], p[2] => sym.t[1], p[3] => sym.t[2], p[4] => sym.p[2]) 40 | val land = switch-lp 41 | landpattern = land(p[1] => land.p[1], p[2] => land.p[2], p[3] => land.p[3], p[4] => land.p[4]) 42 | property(self.rated-temperature) = min-max(-20.0, 70.0) 43 | -------------------------------------------------------------------------------- /components/korean-hroparts-elec/TYPE-C-31-M-23.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/korean-hroparts-elec/TYPE-C-31-M-23: 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/box-symbol 11 | import ocdb/utils/bundles 12 | import ocdb/utils/generic-components 13 | import ocdb/utils/generator-utils 14 | import ocdb/utils/property-structs 15 | 16 | public pcb-module module (configuration:USB-C-ConfigurationChannel|False): 17 | port usb-c : usb-c-connector 18 | port SHIELD 19 | ;public inst conn : ocdb/components/korean-hroparts-elec/TYPE-C-31-M-12/component 20 | public inst conn : database-part(["mpn" => "TYPE-C-31-M-23", "manufacturer" => "Korean Hroparts Elec"]) 21 | place(conn) at loc(0.0, 0.0) on Top 22 | net (SHIELD usb-c.shield conn.SHELL0 conn.SHELL1 conn.SHELL2 conn.SHELL3) 23 | net (usb-c.data[1].N conn.D-0) 24 | net (usb-c.data[2].N conn.D-1) 25 | net (usb-c.data[1].P conn.D+0) 26 | net (usb-c.data[2].P conn.D+1) 27 | net (usb-c.vbus.gnd conn.GND0 conn.GND1) 28 | net (usb-c.vbus.vdd conn.VBUS0 conn.VBUS1) 29 | net (usb-c.cc[1] conn.CC1) 30 | net (usb-c.cc[2] conn.CC2) 31 | net (usb-c.sbu[1] conn.SBU1) 32 | net (usb-c.sbu[2] conn.SBU2) 33 | 34 | match(configuration:USB-C-ConfigurationChannel) : ocdb/utils/generator-utils/usb-c-configuration-channel(usb-c, configuration) 35 | -------------------------------------------------------------------------------- /components/kyocera/KC2520B.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/kyocera/KC2520B : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/symbols 11 | import ocdb/utils/box-symbol 12 | import ocdb/utils/bundles 13 | import ocdb/utils/generator-utils 14 | import ocdb/utils/generic-components 15 | 16 | ; 17 | freq: 40.0e6 18 | 19 | public pcb-component component (freq:Double): 20 | manufacturer = "Kyocera" 21 | name = "KC2520B-C1" 22 | mpn = 23 | switch(freq) : 24 | 40.0e6 : "KC252040.0000C10E00" 25 | else : 26 | fatal("Unsupported or unconfirmed frequency: %_ MHz" % [freq * 1.0e-6]) 27 | description = "MHz XO (Standard) CMOS Oscillator 1.6V ~ 3.63V Standby (Power Down) 4-SMD, No Lead" 28 | reference-prefix = "X" 29 | pin-properties : 30 | [pin:Ref | pads:Int ... | side:Dir ] 31 | [nINH | 1 | Left ] 32 | [GND | 2 | Right ] 33 | [OUT | 3 | Left ] 34 | [VCC | 4 | Right ] 35 | 36 | make-box-symbol() 37 | assign-landpattern(XTAL-2520) 38 | 39 | pcb-landpattern XTAL-2520 : 40 | for (i in 0 to 4, l in grid-locs(C, 2, 2, 1.85, 1.45)) do : 41 | pad p[i + 1] : smd-pad(1.05, 0.95) at loc(0.0, 0.0) * l 42 | layer(Courtyard(Top)) = Rectangle(2.5, 2.0) 43 | ref-label() 44 | 45 | ; 46 | freq: 40.0e6 47 | 48 | public pcb-module module (freq:Double) : 49 | port gnd 50 | port clkout 51 | port vcc 52 | 53 | inst xtal : ocdb/components/kyocera/KC2520B/component(freq) 54 | net (gnd xtal.GND) 55 | net (clkout, xtal.OUT) 56 | net (vcc, xtal.VCC) 57 | cap-strap(gnd, vcc, 10.0e-9) 58 | -------------------------------------------------------------------------------- /components/laird/LI0805H151R-10.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/laird/LI0805H151R-10 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "Laird" 19 | description = "FERRITE BEAD 150 OHM 0805 1LN" 20 | mpn = "LI0805H151R-10" 21 | 22 | port p : pin[[1 2]] 23 | 24 | val sym = inductor-sym() 25 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2]) 26 | val pkg = ipc-two-pin-landpattern("0805") 27 | landpattern = pkg(p[1] => pkg.p[1], p[2] => pkg.p[2]) 28 | 29 | public pcb-module module : 30 | inst i : component 31 | -------------------------------------------------------------------------------- /components/marki/MMIQ-0205HSM-2.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/marki/MMIQ-0205HSM-2: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | 16 | public pcb-component component : 17 | name = "MMIQ-0205HSM-2" 18 | manufacturer = "Marki Microwave" 19 | mpn = "MMIQ-0205HSM-2" 20 | description = "MMIC Double-Balanced I/Q Mixer" 21 | pin-properties : 22 | [pin:Ref | pads:Int ... | side:Dir] 23 | [rf | 4 | Left] 24 | [if-i | 29 | Right] 25 | [lo | 22 | Right] 26 | [if-q | 12 | Right] 27 | [gnd | 1 2 3 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 30 31 32 33 | Down] 28 | make-box-symbol() 29 | assign-landpattern(qfn-landpattern(0.5, 4.9, 32, 0.3, 0.4, [3.5, 3.5])) 30 | 31 | public pcb-module module : 32 | inst i : component 33 | -------------------------------------------------------------------------------- /components/microchip/MCP7381x.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/microchip/MCP7381x : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "Microchip" 19 | mpn = "MCP73812" 20 | description = "IC LI-ION/LI-POLY CTRLR SOT23-5" 21 | 22 | pin-properties : 23 | [pin:Ref | pads:Int ... | side:Dir ] 24 | [CE | 1 | Left ] 25 | [VSS | 2 | Down ] 26 | [VBAT | 3 | Right ] 27 | [VDD | 4 | Up ] 28 | [PROG | 5 | Left ] 29 | 30 | make-box-symbol() 31 | assign-landpattern(SOT95P280X145-5N) 32 | 33 | public pcb-module module (chrg-rate:Double): 34 | port power : power 35 | port ce 36 | port gnd 37 | port vbat 38 | 39 | inst mgr : ocdb/components/microchip/MCP7381x/component 40 | net (power.vdd, mgr.VDD) 41 | net (power.gnd, gnd, mgr.VSS) 42 | 43 | val r = 1000.0 / chrg-rate 44 | if r > 20.0e3 : 45 | println(" MCP73812 charge current %_ below suggested range" % [chrg-rate]) 46 | else if r < 2.0e3 : 47 | println(" MCP73812 charge current %_ above suggested range" % [chrg-rate]) 48 | res-strap(mgr.PROG, gnd, closest-std-val(r, 1.0)) 49 | 50 | cap-strap(mgr.VDD, gnd, 1.0e-6) 51 | cap-strap(mgr.VBAT, gnd, 1.0e-6) 52 | 53 | public pcb-module module () : 54 | inst i : module(1000.0 / 10.0e3) 55 | -------------------------------------------------------------------------------- /components/murata/BLM18HE152SN1D.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/murata/BLM18HE152SN1D : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "Murata" 19 | description = "Ferrite Beads 0603 1500ohms" 20 | mpn = "BLM18HE152SN1D" 21 | 22 | port p : pin[[1 2]] 23 | 24 | val sym = inductor-sym() 25 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2]) 26 | val pkg = ipc-two-pin-landpattern("0603") 27 | landpattern = pkg(p[1] => pkg.p[1], p[2] => pkg.p[2]) 28 | 29 | public pcb-module module : 30 | inst i : component 31 | -------------------------------------------------------------------------------- /components/murata/LQM2HPN2R2MG0L.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/murata/LQM2HPN2R2MG0L : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "Murata" 19 | description = "2.2µH Shielded Molded Inductor 1.3A 80mOhm Max " 20 | mpn = "LQM2HPN2R2MG0L" 21 | 22 | port p : pin[[1 2]] 23 | val pkg = ipc-two-pin-landpattern("1206") 24 | landpattern = pkg(p[1] => pkg.p[1], p[2] => pkg.p[2]) 25 | val sym = inductor-sym() 26 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2]) 27 | reference-prefix = "L" 28 | 29 | public pcb-module module : 30 | inst i : component 31 | -------------------------------------------------------------------------------- /components/murata/MM5829-2700R.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/murata/MM5829-2700R : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/symbol-utils 13 | import ocdb/utils/box-symbol 14 | import ocdb/utils/bundles 15 | import ocdb/utils/generator-utils 16 | import ocdb/utils/generic-components 17 | 18 | pcb-landpattern jsc-landpattern : 19 | pad p[1] : smd-pad(0.5, 0.55) at loc(0.0, (- 0.925)) 20 | pad g[1] : smd-pad(0.4, 0.55) at loc(0.0, 0.925) 21 | pad g[2] : smd-pad(0.65, 1.7) at loc((- 0.775), 0.0) 22 | pad g[3] : smd-pad(0.65, 1.7) at loc(0.775, 0.0) 23 | 24 | layer(Courtyard(Top)) = Rectangle(1.8, 2.0) 25 | layer(Silkscreen("f-silk", Top)) = LineRectangle(1.8, 2.0) 26 | ref-label() 27 | 28 | pcb-symbol jsc-symbol : 29 | unit-circle([0.0, 0.0], 1.25) 30 | unit-circle([0.0, 0.0], 0.25) 31 | unit-rectangle(3.0, 3.0) 32 | unit-line([[0.0, 0.0], [0.0, (- 2.0)]]) 33 | pin p[1] at unit-point(0.0, (- 2.0)) 34 | pin g[1] at unit-point(1.5, (- 1.5)) 35 | 36 | public pcb-component component : 37 | manufacturer = "Murata" 38 | description = "JSC Connector" 39 | mpn = "MM5829-2700" 40 | 41 | port p : pin[[1]] 42 | port g : pin[[1]] 43 | 44 | symbol = jsc-symbol(p[1] => jsc-symbol.p[1], g[1] => jsc-symbol.g[1]) 45 | landpattern = jsc-landpattern(p[1] => jsc-landpattern.p[1], g[1] => jsc-landpattern.g[1]) 46 | 47 | public pcb-module module : 48 | inst i : component 49 | -------------------------------------------------------------------------------- /components/murata/NCP03WF104F05RL.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/murata/NCP03WF104F05RL : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | import ocdb/utils/property-structs 17 | 18 | public pcb-component component : 19 | manufacturer = "Murata" 20 | description = "THERM NTC 100KOHM 4250K 0201" 21 | mpn = "NCP03WF104F05RL" 22 | 23 | port p : pin[[1 2]] 24 | 25 | val sym = resistor-sym(ResistorTherm) 26 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2]) 27 | val pkg = ipc-two-pin-landpattern("0201") 28 | landpattern = pkg(p[1] => pkg.p[1], p[2] => pkg.p[2]) 29 | 30 | property(self.rated-voltage) = 5.0 31 | 32 | property(self.nominal-resistance) = 100.0e3 ; ohms @ nominal-temperature 33 | property(self.nominal-temperature) = 25 ; in C degrees 34 | 35 | property(self.rt-curve) = [[-40.0 3000000.0] [0.0 350000.0] [25.0 100000.0] [50.0 33000.0] [100.0 5500.0] [125.0 2600.0]] ; PWL temperature/resistance pairs 36 | property(self.temp-error) = [[-40.0 0.6] [25.0 0.2] [125.0 1.6]] ; PWL temperature error in degrees C versus temperature 37 | 38 | property(self.rated-temperature) = min-max(-40.0, 125.0) 39 | 40 | public pcb-module module : 41 | public inst i : component 42 | 43 | ; 44 | ; inst ntc : ocdb/components/murata/NCP03WF104F05RL 45 | ; to calculate the resistance of the thermistor at a given temperature: 46 | ; val res = PWL(property(ntc.i.rt-curve))[temperature] 47 | ; to calculate the temperature error band at an operating temperature: 48 | ; assuming that you need the toleranced value 49 | ; val err = PWL(property(ntc.i.temp-error))[temperature] 50 | ; val temperr = min-max(-1.0 * err, 1.0 * err) 51 | ; -------------------------------------------------------------------------------- /components/nexperia/BC846.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/nexperia/BC846 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "Nexperia" 19 | description = "65 V, 100 mA NPN general-purpose transistors" 20 | mpn = "BC846" 21 | 22 | port b 23 | port e 24 | port c 25 | 26 | val pkg = SOT23() 27 | val sym = bjt-sym() 28 | landpattern = pkg(b => pkg.p[1], e => pkg.p[2], c => pkg.p[3]) 29 | symbol = sym(b => sym.b, e => sym.e, c => sym.c) 30 | 31 | public pcb-module module : 32 | inst c : component 33 | -------------------------------------------------------------------------------- /components/nexperia/PESD1CAN.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/nexperia/PESD1CAN : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "Nexperia" 19 | mpn = "PESD1CAN-U" 20 | description = "TVS DIODE 24V 50V SC70-3" 21 | pin-properties : 22 | [pin:Ref | pads:Int ... | side:Dir] 23 | [c[1] | 1 | Left ] 24 | [c[2] | 2 | Left ] 25 | [common | 3 | Right ] 26 | 27 | make-box-symbol() 28 | assign-landpattern(SC-70-3) 29 | reference-prefix = "D" 30 | 31 | public pcb-module module : 32 | inst c : component 33 | -------------------------------------------------------------------------------- /components/nexperia/PUSB3FR4.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/nexperia/PUSB3FR4 : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/box-symbol 8 | 9 | pcb-pad rect-smd-pad : 10 | type = SMD 11 | shape = Rectangle(0.250013, 0.68001) 12 | layer(Paste(Top)) = Rectangle(0.250013, 0.68001) 13 | layer(SolderMask(Top)) = Rectangle(0.250013, 0.68001) 14 | 15 | public pcb-landpattern C294620 : 16 | pad p[1] : rect-smd-pad at loc(-1.0, -0.434989) on Top 17 | pad p[2] : rect-smd-pad at loc(-0.499873, -0.434989) on Top 18 | pad p[3] : rect-smd-pad at loc(0.0, -0.434989) on Top 19 | pad p[4] : rect-smd-pad at loc(0.500127, -0.434989) on Top 20 | pad p[5] : rect-smd-pad at loc(1.0, -0.434989) on Top 21 | pad p[6] : rect-smd-pad at loc(1.0, 0.434963) on Top 22 | pad p[7] : rect-smd-pad at loc(0.500127, 0.434963) on Top 23 | pad p[8] : rect-smd-pad at loc(0.0, 0.434963) on Top 24 | pad p[9] : rect-smd-pad at loc(-0.499873, 0.434963) on Top 25 | pad p[10] : rect-smd-pad at loc(-1.0, 0.434963) on Top 26 | 27 | layer(Silkscreen("F-SilkS", Top)) = Text(">REF", 1.0, C, loc(0.0, 2.016015), "", TrueTypeFont) 28 | layer(Silkscreen("F-SilkS", Top)) = Polyline(0.15, [Arc(-1.016002, -1.397142, 0.0635000000000001, 0.0, 360.0)]) 29 | 30 | public pcb-component component : 31 | port CH : pin[[1 2 3 4]] 32 | mpn = "PUSB3FR4" 33 | manufacturer = "Nexperia" 34 | pin-properties : 35 | [pin:Ref | pads:Ref ... | side:Dir | electrical-type:String] 36 | [CH[1] | p[1] p[10] | Left | "Unspecified"] 37 | [CH[2] | p[2] p[9] | Left | "Unspecified"] 38 | [GND | p[3] p[8] | Left | "Unspecified"] 39 | [CH[3] | p[4] p[7] | Left | "Unspecified"] 40 | [CH[4] | p[5] p[6] | Left | "Unspecified"] 41 | 42 | assign-landpattern(C294620) 43 | make-box-symbol() 44 | 45 | property(self.datasheet) = "https://datasheet.lcsc.com/lcsc/1810081417_Nexperia-PUSB3FR4_C294620.pdf" 46 | -------------------------------------------------------------------------------- /components/on-semiconductor/BAS21LT1G.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/on-semiconductor/BAS21LT1G : 3 | import core 4 | import collections 5 | import math 6 | import jitx/commands 7 | import ocdb/utils/defaults 8 | 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/symbols 11 | import ocdb/utils/box-symbol 12 | import ocdb/utils/bundles 13 | import ocdb/utils/generator-utils 14 | import ocdb/utils/generic-components 15 | 16 | public pcb-component component : 17 | manufacturer = "ON Semiconductor" 18 | description = "High Voltage Switching Diode - SOT23" 19 | mpn = "BAS21LT1G" 20 | 21 | port a 22 | port c 23 | 24 | val pkg = SOT23() 25 | val sym = diode-sym() 26 | landpattern = pkg(a => pkg.p[1], c => pkg.p[3]) 27 | symbol = sym(a => sym.a, c => sym.c) 28 | 29 | public pcb-module module : 30 | inst c : component 31 | -------------------------------------------------------------------------------- /components/on-semiconductor/FDN352AP.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/on-semiconductor/FDN352AP : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "ON Semiconductor" 19 | description = "MOSFET P-CH 30V 1.3A SSOT-3" 20 | mpn = "FDN352AP" 21 | 22 | port g 23 | port d 24 | port s 25 | 26 | val pkg = SOT23() 27 | val sym = fet-sym(FETPType, FETEnhancement, false) 28 | landpattern = pkg(g => pkg.p[1], s => pkg.p[2], d => pkg.p[3]) 29 | symbol = sym(g => sym.g, d => sym.d, s => sym.s) 30 | reference-prefix = "Q" 31 | 32 | public pcb-module module : 33 | inst c : component 34 | -------------------------------------------------------------------------------- /components/on-semiconductor/MBR0520L.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/on-semiconductor/MBR0520L : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "ON Semiconductor" 19 | description = "DIODE SCHOTTKY 20V 500MA SOD123" 20 | mpn = "MBR0520L" 21 | 22 | port a 23 | port c 24 | val pkg = two-pin-polarized-landpattern(4.15, 2.39, 1.02, 4.15, 1.8) 25 | val sym = diode-sym(DiodeSchottky) 26 | landpattern = pkg(a => pkg.a, c => pkg.c) 27 | symbol = sym(a => sym.a, c => sym.c) 28 | reference-prefix = "D" 29 | 30 | public pcb-module module : 31 | inst c : component 32 | -------------------------------------------------------------------------------- /components/on-semiconductor/NCP30x.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/on-semiconductor/NCP30x : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | ; 18 | v-mon: 1.8 19 | 20 | public pcb-component component (v-mon:Double): 21 | manufacturer = "ON Semiconductor" 22 | description = "0.5uW 1.8V Reset supervisor" 23 | mpn = 24 | switch(v-mon) : 25 | 1.8: "NCP300LSN18T1G" 26 | 3.3: "NCP300LSN33T1G" 27 | else: 28 | fatal("unsupported v-mon arg for NCP30x: %_. Supported values are 1.8 and 3.3." % [v-mon]) 29 | 30 | pin-properties : 31 | [pin:Ref | pads:Int ... | side:Dir] 32 | [input | 1 | Left] 33 | [output | 2 | Right] 34 | [gnd | 3 | Down] 35 | 36 | make-box-symbol() 37 | assign-landpattern(SOT95P280X145-5N) 38 | 39 | -------------------------------------------------------------------------------- /components/on-semiconductor/NSR0240HT1G.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/on-semiconductor/NSR0240HT1G : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "ON Semiconductor" 19 | description = "DIODE SCHOTTKY 40V 250MA SOD323 " 20 | mpn = "NSR0240HT1G" 21 | 22 | port a 23 | port c 24 | val pkg = two-pin-landpattern(2.85, 1.60, 0.83, 3.05, 1.03) 25 | val sym = diode-sym(DiodeSchottky) 26 | landpattern = pkg(a => pkg.p[1], c => pkg.p[2]) 27 | symbol = sym(a => sym.a, c => sym.c) 28 | reference-prefix = "D" 29 | 30 | public pcb-module module : 31 | inst c : component 32 | -------------------------------------------------------------------------------- /components/phoenix/combicon-mc.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/phoenix/combicon-mc : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | ; 17 | n: 2 18 | 19 | public pcb-component component (n:Int): 20 | name = "Phoenix screw terminal" 21 | manufacturer = "Phoenix" 22 | mpn = 23 | switch(n) : 24 | 2 : "1803277" 25 | 3 : "1803280" 26 | 4 : "1803293" 27 | 5 : "1803303" 28 | 6 : "1803316" 29 | 7 : "1803329" 30 | 8 : "1803332" 31 | 9 : "1803345" 32 | 10 : "1803358" 33 | 11 : "1803361" 34 | 12 : "1803374" 35 | 13 : "1803387" 36 | 14 : "1803390" 37 | 15 : "1803400" 38 | 16 : "1803413" 39 | 18 : "1841297" 40 | 20 : "1841271" 41 | else : 42 | fatal("Incorrect n-pin for Phoenix Connector %_" % [n]) 43 | 44 | pin-properties : 45 | [pin:Ref | pads:Int ... | side:Dir] 46 | for i in 1 through n do : 47 | [p[i] | i | Left] 48 | 49 | make-box-symbol() 50 | assign-landpattern(phoenix-combicon-mc-pkg(n)) 51 | reference-prefix = "J" 52 | 53 | 54 | pcb-landpattern phoenix-combicon-mc-pkg (n:Int) : 55 | val a = 3.81 * to-double(n - 1) 56 | val x0 = a / -2.0 57 | val y0 = 8.0 58 | 59 | for (i in 0 to n, pose in row-locs(W, n, 3.81)) do : 60 | pad p[i + 1] : pth-pad(0.6) at loc(x0, y0) * pose 61 | 62 | val width = a + 5.2 63 | 64 | layer(Courtyard(Top)) = Rectangle(width, 9.2, loc(0.0, 9.2 / 2.0)) 65 | layer(Courtyard(Bottom)) = Rectangle(a + 2.0, 2.0, loc(0.0, y0)) 66 | ; layer(board-edge = line(0.0, point(width / -2.0, 0.0), point(width / 2.0, 0.0)) 67 | 68 | ref-label() -------------------------------------------------------------------------------- /components/pomona/1581.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/pomona/1581 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | import ocdb/utils/property-structs 15 | 16 | public pcb-component component (color:String) : 17 | port p 18 | manufacturer = "Pomona" 19 | name = "1581" 20 | mpn = switch(color) : 21 | "black" : "1581-0" 22 | "red" : "1581-2" 23 | "blue" : "1581-6" 24 | landpattern = pomona-banana-pkg(p => pomona-banana-pkg.p) 25 | symbol = hole-sym(p => hole-sym.p[1]) 26 | reference-prefix = "J" 27 | property(self.rated-temperature) = min-max(-40.0, 115.0) 28 | 29 | pcb-landpattern pomona-banana-pkg : 30 | val drill-r = 0.28 * 25.4 / 2.0 31 | val pad-r = 0.5 * 25.4 / 2.0 32 | 33 | pad p : pth-pad(drill-r, pad-r) at loc(0.0, 0.0) 34 | 35 | layer(Courtyard(Top)) = Rectangle((pad-r * 2.0), (pad-r * 2.0)) 36 | layer(Courtyard(Bottom)) = Rectangle((pad-r * 2.0), (pad-r * 2.0)) 37 | ref-label() 38 | 39 | public pcb-module module : 40 | inst c : component("red") 41 | -------------------------------------------------------------------------------- /components/pulse-electronics/P1167_183NLT.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/pulse-electronics/P1167_183NLT : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "Pulse Electronics Power" 19 | description = "18µH Shielded Wirewound Inductor 1.5A 73mOhm Max Nonstandard" 20 | mpn = "P1167.183NLT" 21 | port p : pin[[1 2]] 22 | val pkg = two-pin-landpattern(7.29, 5.00, 2.11, 7.69, 2.51) 23 | val sym = inductor-sym() 24 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2]) 25 | landpattern = pkg(p[1] => pkg.p[1], p[2] => pkg.p[2]) 26 | reference-prefix = "L" 27 | 28 | public pcb-module module : 29 | inst c : component 30 | -------------------------------------------------------------------------------- /components/q-n-j/CR2032-BS-6-1.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/q-n-j/CR2032-BS-6-1 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | 9 | import ocdb/utils/defaults 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/symbol-utils 13 | import ocdb/utils/generic-components 14 | 15 | import ocdb/utils/bundles 16 | import ocdb/utils/box-symbol 17 | import ocdb/utils/property-structs 18 | import ocdb/utils/generator-utils 19 | import ocdb/utils/checks 20 | 21 | pcb-landpattern CR2032-BS-6-1-landpattern : 22 | 23 | pad p[1] : smd-pad(4.2, 3.0) at loc(0.000, 14.500) 24 | pad p[2] : smd-pad(4.2, 3.0) at loc(0.000, -14.500) 25 | 26 | layer(Silkscreen("f-silk", Top)) = Line(0.12, [ Point(0.0, 17.75), Point(0.0, 16.75) ]) 27 | layer(Silkscreen("f-silk", Top)) = Line(0.12, [ Point(-0.5, 17.25), Point(0.5, 17.25) ]) 28 | layer(Courtyard(Top)) = Rectangle(16.0, 32.0) 29 | ref-label() 30 | 31 | 32 | public pcb-component component (capacity : Double) : ; capacity is in mAh 33 | port power : power 34 | 35 | manufacturer = "Q&J" 36 | description = "SMD Battery Box/Battery Holders ROHS" 37 | mpn = "CR2032-BS-6-1" 38 | reference-prefix = "B" 39 | ; public pcb-landpattern two-pin-landpattern (Z:Double, G:Double, X:Double, w:Double, h:Double): 40 | ; from IPC-SM-782 spec 41 | ; Z - width between outer pad edges 42 | ; G - width between inner pad edges 43 | ; X - pad height 44 | ; w, h - width and height of courtyard in mm 45 | ;val pkg = two-pin-landpattern(32.0, 26.0, 4.2, 32.0, 16.0) 46 | val pkg = CR2032-BS-6-1-landpattern 47 | val sym = header-symbol(2,1) 48 | symbol = sym(power.vdd => sym.p[1], power.gnd => sym.p[2]) 49 | landpattern = pkg(power.vdd => pkg.p[1], power.gnd => pkg.p[2]) 50 | property(self.rated-temperature) = min-max(-20.0, 70.0) 51 | property(self.LCSC) = "C70377" 52 | datasheet = "https://datasheet.lcsc.com/lcsc/1811061923_Q-J-CR2032-BS-6-1_C70377.pdf" 53 | ; setup the output voltage 54 | val voltage = typ(3.0) 55 | property(self.power.vdd.power-supply-pin) = PowerSupplyPin(voltage, capacity / 1000.0) ; for a 1C battery 56 | property(self.power.vdd.voltage) = voltage -------------------------------------------------------------------------------- /components/samtec/FTSH-105-01-D-RA.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/samtec/FTSH-105-01-D-RA : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "Samtec" 19 | mpn = "FTSH-105-01-L-D-RA" 20 | description = "Connector Header Through Hole, Right Angle 10 position 0.050in (1.27mm)" 21 | 22 | pin-properties : 23 | [pin:Ref | pads:Int ... | side:Dir ] 24 | for i in 1 through 10 by 2 do : 25 | [p[i] | i | Left] 26 | [p[i + 1] | (i + 1) | Right] 27 | 28 | make-box-symbol() 29 | assign-landpattern(FTSH-105-01-L-D-RA-pkg) 30 | 31 | pcb-landpattern FTSH-105-01-L-D-RA-pkg : 32 | for (l in grid-locs(C, 2, 5, 1.27, 1.27), i in [2 4 6 8 10 1 3 5 7 9]) do : 33 | pad p[i] : pth-pad(0.36) at loc(0.0, 0.0) * l 34 | layer(Courtyard(Top)) = Rectangle(6.85, 2.89) 35 | ref-label() 36 | -------------------------------------------------------------------------------- /components/samtec/FTSH-105-01-DV.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/samtec/FTSH-105-01-DV : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/box-symbol 9 | import ocdb/utils/bundles 10 | import ocdb/utils/defaults 11 | import ocdb/utils/generator-utils 12 | import ocdb/utils/generic-components 13 | import ocdb/utils/landpatterns 14 | import ocdb/utils/module-utils 15 | import ocdb/utils/symbols 16 | 17 | public pcb-component component : 18 | manufacturer = "Samtec" 19 | mpn = "FTSH-105-01-L-DV-K" 20 | description = "Connector Header Surface Mount 10 position 0.050 (1.27mm)" 21 | 22 | pin-properties : 23 | [pin:Ref | pads:Int ... | side:Dir ] 24 | for i in 1 through 10 by 2 do : 25 | [p[i] | i | Left] 26 | [p[i + 1] | (i + 1) | Right] 27 | 28 | make-box-symbol() 29 | assign-landpattern(FTSH-105-01-L-DV-pkg) 30 | 31 | pcb-landpattern FTSH-105-01-L-DV-pkg : 32 | for (l in grid-locs(C, 2, 5, 1.27, 4.07), i in [2 4 6 8 10 1 3 5 7 9]) do : 33 | pad p[i] : smd-pad(0.74, 2.79) at loc(0.0, 0.0) * l 34 | layer(Courtyard(Top)) = Rectangle(6.85, 7.36) 35 | ref-label() 36 | 37 | public pcb-module module : 38 | make-10-pin-debug-connector-module(component) 39 | -------------------------------------------------------------------------------- /components/semtech/1N4148W.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/semtech/1N4148W : 3 | import core 4 | import collections 5 | import math 6 | import jitx/commands 7 | import ocdb/utils/defaults 8 | 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/symbols 11 | import ocdb/utils/box-symbol 12 | import ocdb/utils/bundles 13 | import ocdb/utils/generator-utils 14 | import ocdb/utils/generic-components 15 | 16 | public pcb-component component : 17 | port a 18 | port c 19 | manufacturer = "Semtech" 20 | description = "DIODE GEN PURP 100V 300MA SOD123" 21 | mpn = "1N4148W" 22 | reference-prefix = "D" 23 | val sym = diode-sym() 24 | symbol = sym(a => sym.a, c => sym.c) 25 | val land = d-sod-123 26 | landpattern = land(a => land.a, c => land.c) 27 | -------------------------------------------------------------------------------- /components/si-labs/Si862x.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/si-labs/Si862x: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | ; Start with one. TODO: Add the rest of the family 18 | public pcb-component component (num-vdd2-in:Int): 19 | manufacturer = "Silicon Labs" 20 | description = "Quad channel Digital isolator" 21 | mpn = to-string("SI862%_BB-B-IS" % [num-vdd2-in]) 22 | if num-vdd2-in < 0 or num-vdd2-in > 1: 23 | fatal("Unsupported number of VDD2 inputs: %_ for Si862x" % [num-vdd2-in]) 24 | 25 | pin-properties : 26 | [pin:Ref | pads:Int ... | side:Dir] 27 | [VDD1 | 1 | Left ] 28 | [GND1 | 4 | Left ] 29 | [VDD2 | 8 | Right ] 30 | [GND2 | 5 | Right ] 31 | for i in 1 through 2 do : 32 | [A[i] | 1 + i | Left ] 33 | [B[i] | 8 - i | Right ] 34 | 35 | make-box-symbol() 36 | assign-landpattern(soic127p-landpattern(8)) 37 | 38 | public pcb-module module (num-vdd2-in:Int) : 39 | port vdd1 : power 40 | port vdd2 : power 41 | val num-vdd1-in = 2 - num-vdd2-in 42 | port vdd1-in : pin[num-vdd1-in] 43 | port vdd2-out : pin[num-vdd1-in] 44 | port vdd2-in : pin[num-vdd2-in] 45 | port vdd1-out : pin[num-vdd2-in] 46 | 47 | inst iso : ocdb/components/si-labs/Si862x/component(num-vdd2-in) 48 | 49 | cap-strap(iso.VDD1, iso.GND1, 0.1e-6) 50 | cap-strap(iso.VDD2, iso.GND2, 0.1e-6) 51 | 52 | net (iso.GND1 vdd1.gnd) 53 | net (iso.GND2 vdd2.gnd) 54 | net (iso.VDD1 vdd1.vdd) 55 | net (iso.VDD2 vdd2.vdd) 56 | 57 | for i in 0 to num-vdd1-in do : 58 | net (iso.A[i + 1], vdd1-in[i]) 59 | net (iso.B[i + 1], vdd2-out[i]) 60 | for i in 0 to num-vdd2-in do : 61 | net (iso.B[i + 1 + num-vdd1-in], vdd2-in[i]) 62 | net (iso.A[i + 1 + num-vdd1-in], vdd1-out[i]) 63 | 64 | public pcb-module mod : 65 | inst m : module(1) 66 | -------------------------------------------------------------------------------- /components/soberton/GT-111P.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/soberton/GT-111P : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | pcb-landpattern buzzer-pkg : 18 | pad high : pth-pad(0.4) at loc(0.0, (- 3.25)) 19 | pad low : pth-pad(0.4) at loc(0.0, 3.25) 20 | 21 | layer(Courtyard(Top)) = Circle(6.0) 22 | layer(Silkscreen("f-silk", Top)) = Circle(6.1) 23 | ref-label() 24 | 25 | public pcb-component component : 26 | manufacturer = "Soberton" 27 | description = "AUDIO MAGNETIC XDCR 1-4V TH" 28 | mpn = "GT-111P" 29 | 30 | port high 31 | port low 32 | 33 | symbol = speaker-symbol(high => speaker-symbol.high, low => speaker-symbol.low) 34 | landpattern = buzzer-pkg(high => buzzer-pkg.high, low => buzzer-pkg.low) 35 | 36 | public pcb-module module : 37 | inst c : component 38 | -------------------------------------------------------------------------------- /components/st-microelectronics/USBLC6-2SC6.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/st-microelectronics/USBLC6-2SC6 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/bundles 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/generator-utils 12 | import ocdb/utils/generic-components 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | 16 | public pcb-component component : 17 | manufacturer = "STMicroelectronics" 18 | mpn = "USBLC6-2SC6" 19 | pin-properties : 20 | [pin:Ref | pads:Int ... | side:Dir] 21 | [i[0] | 1 | Left] 22 | [o[0] | 6 | Right] 23 | [i[1] | 3 | Left] 24 | [o[1] | 4 | Right] 25 | [gnd | 2 | Down] 26 | [vbus | 5 | Up] 27 | make-box-symbol() 28 | assign-landpattern(SOT95P280X145-6N) -------------------------------------------------------------------------------- /components/sunlord/GZ2012D601TF.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/sunlord/GZ2012D601TF : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | 9 | import ocdb/utils/defaults 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/symbol-utils 13 | import ocdb/utils/generic-components 14 | 15 | import ocdb/utils/bundles 16 | import ocdb/utils/box-symbol 17 | import ocdb/utils/property-structs 18 | import ocdb/utils/generator-utils 19 | import ocdb/utils/checks 20 | 21 | public pcb-component component : 22 | port p : pin[1 through 2] 23 | ; JLCPCB Part # C1017 24 | datasheet = "https://datasheet.lcsc.com/lcsc/1811141711_Sunlord-GZ2012D601TF_C1017.pdf" 25 | manufacturer = "Sunlord" 26 | description = "600Ω @ 100MHz 1 500mA 300mΩ 0805 Ferrite Beads ROHS" 27 | mpn = "GZ2012D601TF" 28 | reference-prefix = "FB" 29 | ; public pcb-landpattern two-pin-landpattern (Z:Double, G:Double, X:Double, w:Double, h:Double): 30 | ; from IPC-SM-782 spec 31 | ; Z - width between outer pad edges 32 | ; G - width between inner pad edges 33 | ; X - pad height 34 | ; w, h - width and height of courtyard in mm 35 | val pkg = two-pin-landpattern(2.0, 1.0, 1.25, 2.75, 2.0) 36 | val sym = inductor-sym() 37 | landpattern = pkg(p[1] => pkg.p[1], p[2] => pkg.p[2]) 38 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2]) 39 | property(self.rated-temperature) = min-max(-40.0, 85.0) 40 | property(self.power-supply-component) = true -------------------------------------------------------------------------------- /components/sunlord/SWPA6045S1R8NT.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/sunlord/SWPA6045S1R8NT : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | 9 | import ocdb/utils/defaults 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/symbol-utils 13 | import ocdb/utils/generic-components 14 | 15 | import ocdb/utils/bundles 16 | import ocdb/utils/box-symbol 17 | import ocdb/utils/property-structs 18 | import ocdb/utils/generator-utils 19 | import ocdb/utils/checks 20 | 21 | public pcb-component component : 22 | port p : pin[1 through 2] 23 | ; JLCPCB Part # C361639 24 | datasheet = "https://datasheet.lcsc.com/lcsc/2110100030_Sunlord-SWPA6045S1R8NT_C361639.pdf" 25 | manufacturer = "Sunlord" 26 | description = "4.95A 1.8uH ±30% 12mΩ SMD Power Inductors ROHS" 27 | mpn = "SWPA6045S1R8NT" 28 | reference-prefix = "L" 29 | ; public pcb-landpattern two-pin-landpattern (Z:Double, G:Double, X:Double, w:Double, h:Double): 30 | ; from IPC-SM-782 spec 31 | ; Z - width between outer pad edges 32 | ; G - width between inner pad edges 33 | ; X - pad height 34 | ; w, h - width and height of courtyard in mm 35 | val pkg = two-pin-landpattern(6.0, 2.90, 4.9, 6.5, 6.5) 36 | val sym = inductor-sym() 37 | landpattern = pkg(p[1] => pkg.p[1], p[2] => pkg.p[2]) 38 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2]) 39 | property(self.rated-temperature) = min-max(-40.0, 85.0) 40 | property(self.power-supply-component) = true -------------------------------------------------------------------------------- /components/tag-connect/TC2030-IDC-NL.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/tag-connect/TC2030-IDC-NL : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | import ocdb/utils/property-structs 18 | import ocdb/utils/checks 19 | 20 | ; NOTE PINOUT ORDER DIFFERENT THAN 10-PIN 21 | ; Datasheet showing pinout: https://www.tag-connect.com/wp-content/uploads/bsk-pdf-manager/2019/12/TC2030-IDC-NL-Datasheet-Rev-B.pdf 22 | 23 | pcb-landpattern TC2030-IDC-NL-footprint : 24 | ; landing pads 25 | for (l in grid-locs(2, 3, 1.27, 1.27), i in [2 4 6 1 3 5]) do : 26 | pad p[i] : testpoint-pad(0.787) at l 27 | 28 | ; alignment holes 29 | layer(Cutout()) = Circle((- 2.54), 0.0, 0.4955) 30 | layer(Cutout()) = Circle(2.54, 1.016, 0.4955) 31 | layer(Cutout()) = Circle(2.54, (- 1.016), 0.4955) 32 | 33 | layer(Courtyard(Top)) = Rectangle(6.08, 3.032 ) 34 | ref-label() 35 | 36 | public pcb-component component : 37 | description = "Insertion point for TC-2030-NL connector" 38 | datasheet = "https://www.tag-connect.com/wp-content/uploads/bsk-pdf-manager/2019/12/TC2030-IDC-NL-Datasheet-Rev-B.pdf" 39 | manufacturer = "Tag-Connect" 40 | mpn = "TC2030-IDC-NL" 41 | port p: pin[1 through 6] 42 | 43 | val sym = header-symbol(6, 2) 44 | symbol = sym(for i in 1 through 6 do : p[i] => sym.p[i]) 45 | landpattern = TC2030-IDC-NL-footprint(for i in 1 through 6 do : p[i] => TC2030-IDC-NL-footprint.p[i]) 46 | reference-prefix = "J" 47 | 48 | supports swd-swo() : 49 | swd-swo().swdio => self.p[2] 50 | swd-swo().swdclk => self.p[4] 51 | swd-swo().swo => self.p[6] 52 | 53 | supports power: 54 | power.vdd => self.p[1] 55 | power.gnd => self.p[5] 56 | 57 | supports reset: 58 | reset.reset => self.p[3] 59 | -------------------------------------------------------------------------------- /components/tdk/MPZ1608.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/tdk/MPZ1608 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component (imp:Double) : 18 | manufacturer = "TDK" 19 | name = "MPZ1608" 20 | mpn = switch(imp) : ; Impedance (Ohms) at 100 MHz 21 | 470.0 : "MPZ1608B471ATA00" 22 | else : fatal("Unsupported or unconfirmed part variant: %_ H" % [imp]) 23 | description = "Ferrite bead - 0603" 24 | 25 | port p : pin[[1 2]] 26 | 27 | val sym = inductor-sym(InductorFerriteCore) 28 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2]) 29 | val land = ipc-two-pin-landpattern("0603") 30 | landpattern = land(p[1] => land.p[1], p[2] => land.p[2]) 31 | reference-prefix = "L" 32 | -------------------------------------------------------------------------------- /components/te-connectivity/1825910-6.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/te-connectivity/1825910-6 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "TE Connectivity" 19 | mpn = "1825910-6" 20 | description = "Tactile Switch SPST-NO Top Actuated Through Hole" 21 | 22 | pin-properties : 23 | [pin:Ref | pads:Int ... | side:Dir ] 24 | [P | 1, 2 | Left ] 25 | [T | 3, 4 | Right ] 26 | 27 | make-box-symbol() 28 | assign-landpattern(switch-pkg) 29 | 30 | pcb-landpattern switch-pkg : 31 | for (i in 0 to 4, l in grid-locs(C, 2, 2, 6.5, 4.5)) do : 32 | pad p[i + 1] : pth-pad(1.4, 1.15) at loc(0.0, 0.0) * l 33 | layer(Courtyard(Top)) = Rectangle(7.8, 6.0) 34 | ref-label() -------------------------------------------------------------------------------- /components/te-connectivity/2102735-1.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/te-connectivity/2102735-1 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | 16 | public pcb-component component: 17 | name = "2102735-1" 18 | manufacturer = "TE" 19 | mpn = "2102735-1" 20 | 21 | defn pin-name (r:Int, c:Int) : 22 | val letter = red-alph-letter(r) 23 | Ref(letter)[c + 1] 24 | pin-properties : 25 | [pin:Ref | pads:Ref ... | side:Dir | bank:Int] 26 | for c in 0 to 8 do : 27 | for r in 0 to 7 do : 28 | [(pin-name(r,c)) | (pin-name(r,c)) | Right | c] 29 | reference-prefix = "P" 30 | 31 | make-box-symbol() 32 | assign-landpattern(te-2102735-1-pkg) 33 | property(self.rated-temperature) = min-max(-55.0, 105.0) 34 | 35 | pcb-landpattern te-2102735-1-pkg : 36 | 37 | defn make-pad (r:Int, c:Int) : 38 | val x = ((to-double(8) - 1.0) / -2.0 + to-double(c)) * -1.8 39 | val y = ((to-double(7) - 1.0) / 2.0 - to-double(r)) * -1.35 40 | val letter = red-alph-letter(r) 41 | val name = Ref(letter)[c + 1] 42 | 43 | ;fab-note : "PLATED THROUGH HOLE PER TE 114-13056, FIGURE 4" 44 | pad (name) : pth-pad(0.55 / 2.0, 0.92 / 2.0) at loc(x,y) 45 | 46 | for c in 0 to 8 do : 47 | for r in 0 to 7 do : 48 | make-pad(r,c) 49 | 50 | val post = Circle(0.56 / 2.0) 51 | layer(Cutout()) = loc(3.5 * 1.8, 4.0 * 1.35) * post 52 | layer(Cutout()) = loc(-0.5 * 1.8, 4.0 * 1.35) * post 53 | 54 | layer(Courtyard(Top)) = Rectangle(16.08, 11.81, loc(0.9, 0.0)) 55 | layer(Silkscreen("f-silk", Top)) = LineRectangle(16.08, 11.81, 0.9, 0.0) 56 | layer(BoardEdge()) = Line(0.0, [Point(1.0, -3.0 * 1.35 - 1.5), Point(-1.0, -3.0 * 1.35 - 1.5)]) 57 | ref-label() 58 | 59 | public pcb-module module : 60 | inst c : component 61 | -------------------------------------------------------------------------------- /components/te-connectivity/2102736-1.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/te-connectivity/2102736-1: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | 16 | public pcb-component component : 17 | name = "2102736-1" 18 | manufacturer = "TE" 19 | mpn = "2102736-1" 20 | 21 | defn pin-name (r:Int, c:Int) : 22 | val letter = red-alph-letter(r) 23 | Ref(letter)[c + 1] 24 | pin-properties : 25 | [pin:Ref | pads:Ref ... | side:Dir | bank:Int] 26 | for c in 0 to 16 do : 27 | for r in 0 to 7 do : 28 | [(pin-name(r,c)) | (pin-name(r,c)) | Right | c] 29 | reference-prefix = "P" 30 | make-box-symbol() 31 | assign-landpattern(te-2102736-1-pkg) 32 | property(self.rated-temperature) = min-max(-55.0, 105.0) 33 | 34 | pcb-landpattern te-2102736-1-pkg : 35 | 36 | defn make-pad (r:Int, c:Int) : 37 | val x = ((to-double(16) - 1.0) / -2.0 + to-double(c)) * -1.8 38 | val y = ((to-double(7) - 1.0) / 2.0 - to-double(r)) * -1.35 39 | val letter = red-alph-letter(r) 40 | val name = Ref(letter)[c + 1] 41 | 42 | ;fab-note : "PLATED THROUGH HOLE PER TE 114-13056, FIGURE 4" 43 | pad (name) : pth-pad(0.55 / 2.0, 0.92 / 2.0) at loc(x,y) 44 | 45 | for c in 0 to 16 do : 46 | for r in 0 to 7 do : 47 | make-pad(r,c) 48 | 49 | val post = Circle(0.56 / 2.0) 50 | layer(Cutout()) = loc(7.5 * 1.8, 4.0 * 1.35) * post 51 | layer(Cutout()) = loc(3.5 * 1.8, 4.0 * 1.35) * post 52 | layer(Cutout()) = loc(-0.5 * 1.8, 4.0 * 1.35) * post 53 | layer(Cutout()) = loc(-4.5 * 1.8, 4.0 * 1.35) * post 54 | 55 | layer(Courtyard(Top)) = Rectangle(28.68, 11.81) 56 | layer(Silkscreen("f-silk", Top)) = LineRectangle(28.68, 11.81) 57 | layer(BoardEdge()) = Line(0.0, [Point(1.0, -3.0 * 1.35 - 1.5), Point(-1.0, -3.0 * 1.35 - 1.5)]) 58 | ref-label() 59 | 60 | public pcb-module module : 61 | inst c : component 62 | -------------------------------------------------------------------------------- /components/te-connectivity/2102771-1.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/te-connectivity/2102771-1: 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | import ocdb/utils/property-structs 16 | 17 | public pcb-component component : 18 | name = "2102771-1" 19 | manufacturer = "TE" 20 | mpn = "2102771-1" 21 | 22 | defn pin-name (r:Int, c:Int) : 23 | val letter = red-alph-letter(r) 24 | Ref(letter)[c + 1] 25 | pin-properties : 26 | [pin:Ref | pads:Ref ... | side:Dir | bank:Int] 27 | for c in 0 to 16 do : 28 | for r in 0 to 7 do : 29 | [(pin-name(r, c)) | (pin-name(r, c)) | Right | c] 30 | reference-prefix = "P" 31 | make-box-symbol() 32 | assign-landpattern(te-2102771-1-pkg) 33 | property(self.rated-temperature) = min-max(-55.0, 105.0) 34 | 35 | pcb-landpattern te-2102771-1-pkg : 36 | 37 | defn make-pad (r:Int, c:Int) : 38 | val x = ((to-double(16) - 1.0) / -2.0 + to-double(c)) * -1.8 39 | val y = ((to-double(7) - 1.0) / 2.0 - to-double(r)) * -1.35 40 | val letter = red-alph-letter(r) 41 | val name = Ref(letter)[c + 1] 42 | 43 | ;fab-note : "PLATED THROUGH HOLE PER TE 114-13056, FIGURE 4" 44 | pad (name) : pth-pad(0.55 / 2.0, 0.92 / 2.0) at loc(x, y) 45 | 46 | for c in 0 to 16 do : 47 | for r in 0 to 7 do : 48 | make-pad(r, c) 49 | 50 | val post = Circle(0.56 / 2.0) 51 | layer(Cutout()) = loc(7.5 * 1.8, 4.0 * 1.35) * post 52 | layer(Cutout()) = loc(3.5 * 1.8, 4.0 * 1.35) * post 53 | layer(Cutout()) = loc(-0.5 * 1.8, 4.0 * 1.35) * post 54 | layer(Cutout()) = loc(-4.5 * 1.8, 4.0 * 1.35) * post 55 | 56 | layer(Courtyard(Top)) = Rectangle(28.68, 11.81) 57 | layer(Silkscreen("f-silk", Top)) = LineRectangle(28.68, 11.81) 58 | layer(BoardEdge()) = Line(0.0, [Point(1.0, -3.0 * 1.35 - 1.5), Point(-1.0, -3.0 * 1.35 - 1.5)]) 59 | ref-label() 60 | 61 | public pcb-module module : 62 | inst c : component 63 | -------------------------------------------------------------------------------- /components/te-connectivity/2102772-1.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/te-connectivity/2102772-1 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | import ocdb/utils/property-structs 16 | 17 | public pcb-component component: 18 | name = "2102772-1" 19 | manufacturer = "TE" 20 | mpn = "2102772-1" 21 | 22 | defn pin-name (r:Int, c:Int) : 23 | val letter = red-alph-letter(r) 24 | Ref(letter)[c + 1] 25 | pin-properties : 26 | [pin:Ref | pads:Ref ... | side:Dir | bank:Int] 27 | for c in 0 to 8 do : 28 | for r in 0 to 7 do : 29 | [(pin-name(r, c)) | (pin-name(r, c)) | Right | c] 30 | reference-prefix = "P" 31 | 32 | make-box-symbol() 33 | assign-landpattern(te-2102772-1-pkg) 34 | 35 | property(self.rated-temperature) = min-max(-55.0, 105.0) 36 | 37 | 38 | pcb-landpattern te-2102772-1-pkg : 39 | 40 | defn make-pad (r:Int, c:Int) : 41 | val x = ((to-double(8) - 1.0) / -2.0 + to-double(c)) * -1.8 42 | val y = ((to-double(7) - 1.0) / 2.0 - to-double(r)) * -1.35 43 | val letter = red-alph-letter(r) 44 | val name = Ref(letter)[c + 1] 45 | 46 | ;fab-note : "PLATED THROUGH HOLE PER TE 114-13056, FIGURE 4" 47 | pad (name) : pth-pad(0.55 / 2.0, 0.92 / 2.0) at loc(x, y) 48 | 49 | for c in 0 to 8 do : 50 | for r in 0 to 7 do : 51 | make-pad(r, c) 52 | 53 | val post = Circle(0.56 / 2.0) 54 | layer(Cutout()) = loc(3.5 * 1.8, 4.0 * 1.35) * post 55 | layer(Cutout()) = loc(-0.5 * 1.8, 4.0 * 1.35) * post 56 | 57 | layer(Courtyard(Top)) = Rectangle(16.08, 11.81, loc(0.9, 0.0)) 58 | layer(Silkscreen("f-silk", Top)) = LineRectangle(16.08, 11.81, 0.9, 0.0) 59 | layer(BoardEdge()) = Line(0.0, [Point(1.0, -3.0 * 1.35 - 1.5), Point(-1.0, -3.0 * 1.35 - 1.5)]) 60 | ref-label() 61 | 62 | public pcb-module module : 63 | inst c : component 64 | -------------------------------------------------------------------------------- /components/te-connectivity/RC.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/te-connectivity/RC : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/bundles 13 | import ocdb/utils/generator-utils 14 | import ocdb/utils/generic-components 15 | import ocdb/utils/property-structs 16 | 17 | pcb-landpattern rc-landpattern : 18 | pad p : smd-pad(1.95, 1.1) at loc(0.0, 0.0) 19 | layer(Courtyard(Top)) = Rectangle(1.95, 1.1) 20 | ref-label() 21 | 22 | public pcb-component component : 23 | manufacturer = "TE Connectivity" 24 | description = "0603 Size SMD test loop" 25 | reference-prefix = "TP" 26 | mpn = "RCU-0C" 27 | port p 28 | landpattern = rc-landpattern(p => rc-landpattern.p) 29 | symbol = test-point-sym(p => test-point-sym.p) 30 | property(self.rated-temperature) = min-max(-55.0, 125.0) 31 | -------------------------------------------------------------------------------- /components/texas-instruments/BQ27441-G1.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/texas-instruments/BQ27441-G1 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "Texas Instruments" 19 | mpn = "BQ27441-G1" 20 | description = "System-Side Impedance Track™ Fuel Gauge" 21 | 22 | port i2c : i2c 23 | pin-properties : 24 | [pin:Ref | pads:Int ... | side:Dir ] 25 | [BAT | 6 | Left ] 26 | [BIN | 10 | Right ] 27 | [GPOUT | 12 | Right ] 28 | [NC | 4, 9, 11 | Left ] 29 | [i2c.scl | 2 | Right ] 30 | [i2c.sda | 1 | Right ] 31 | [SRN | 7 | Left ] 32 | [SRP | 8 | Left ] 33 | [VDD | 5 | Right ] 34 | [VSS | 3 | Left ] 35 | [TP | 13 | Left ] 36 | 37 | make-box-symbol() 38 | assign-landpattern(dfn-landpattern(12, 0.4, [0.2, 0.85], -1.975, [4.0, 2.5], [2.45, 1.95])) 39 | 40 | 41 | public pcb-module module : 42 | inst ic : ocdb/components/texas-instruments/BQ27441-G1/component 43 | port gpout 44 | port gnd 45 | port batt-in 46 | port batt-out 47 | port i2c-node : i2c 48 | 49 | net (i2c-node, ic.i2c) 50 | 51 | net (gnd, ic.TP, ic.VSS) 52 | net (batt-in, ic.SRP, ic.BAT) 53 | net (batt-out, ic.SRN) 54 | net (gpout, ic.GPOUT) 55 | 56 | res-strap(batt-in, batt-out, 1.0e-2) 57 | res-strap(batt-in, ic.GPOUT, 10.0e3) 58 | cap-strap(ic.VDD, gnd, 0.47e-6) -------------------------------------------------------------------------------- /components/texas-instruments/ISO1540.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/texas-instruments/ISO1540 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | 16 | public pcb-component component : 17 | name = "ISO1540DR" 18 | manufacturer = "Texas Instruments" 19 | mpn = "ISO1540DR" 20 | description = "2.5-kVrms isolated bidirectional clock, bidirectional I2C isolator" 21 | port p: i2c[[1 2]] 22 | pin-properties : 23 | [pin:Ref | pads:Int ... | side:Dir] 24 | [GND1 | 4 | Down ] 25 | [GND2 | 5 | Down ] 26 | [p[1].scl | 3 | Left ] 27 | [p[2].scl | 6 | Right ] 28 | [p[1].sda | 2 | Left ] 29 | [p[2].sda | 7 | Right ] 30 | [VCC1 | 1 | Up ] 31 | [VCC2 | 8 | Up ] 32 | make-box-symbol() 33 | assign-landpattern(soic127p-landpattern(8)) 34 | -------------------------------------------------------------------------------- /components/texas-instruments/SN6501.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/texas-instruments/SN6501 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "Texas Instruments" 19 | mpn = "SN6501DBVT" 20 | description = "Transformer Driver PMIC SOT-23-5" 21 | pin-properties : 22 | [pin:Ref | pads:Int ... | side:Dir] 23 | [D[2] | 3 | Right ] 24 | [D[1] | 1 | Right ] 25 | [VCC | 2 | Up ] 26 | [GND | 4 5 | Down ] 27 | 28 | make-box-symbol() 29 | assign-landpattern(SOT95P280X145-5N) 30 | 31 | ; Module set up for isolated 1:1 voltage levels, 2.5kv isolation 32 | public pcb-module module: 33 | ; Set up ports 34 | port vin: power 35 | port vout: power 36 | inst drv : ocdb/components/texas-instruments/SN6501/component 37 | 38 | cap-strap(drv.VCC, vin.gnd, 1.0e-6) 39 | net (vin.gnd, drv.GND) 40 | cap-strap(vout.vdd, vout.gnd, 1.0e-6) 41 | inst xfrmr : ocdb/components/wurth/760390012/component 42 | inst d : ocdb/components/on-semiconductor/MBR0520L/component[2] 43 | net (drv.D[2] xfrmr.p[1]) 44 | net (drv.D[1] xfrmr.p[3]) 45 | net (vin.vdd drv.VCC xfrmr.p[2]) 46 | net (d[0].a xfrmr.p[4]) 47 | net (d[1].a xfrmr.p[6]) 48 | net (xfrmr.p[5] vout.gnd) 49 | net (d[0].c d[1].c vout.vdd) 50 | -------------------------------------------------------------------------------- /components/texas-instruments/TLV743P.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/texas-instruments/TLV743P : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/generator-utils 11 | import ocdb/utils/generic-components 12 | import ocdb/utils/bundles 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | import ocdb/utils/property-structs 16 | 17 | public pcb-component component (v-out:Double) : 18 | port en 19 | port gnd 20 | port in 21 | port out 22 | port nc 23 | name = "TLV743P" 24 | manufacturer = "Texas Instruments" 25 | description = "TLV743P 300-mA, Low-Dropout Regulator" 26 | val [code spice-code] = switch(v-out) : 27 | 1.5 : ["15" "TLV74315P"] 28 | 1.8 : ["15" "TLV74318P"] 29 | 2.5 : ["25" "TLV74325P"] 30 | 3.3 : ["33" "TLV74333P"] 31 | mpn = to-string("TLV743%_P" % [code]) 32 | pin-properties : 33 | [pin:Ref | pads:Int ... | side:Dir] 34 | [gnd | 2 | Down ] 35 | [in | 1 | Left ] 36 | [en | 3 | Left ] 37 | [out | 5 | Right ] 38 | [nc | 4 | Down ] 39 | make-box-symbol() 40 | assign-landpattern(SOT95P280X145-5N) 41 | 42 | property(out.power-supply-pin) = PowerSupplyPin(typ(v-out), 0.3) 43 | property(in.power-pin) = PowerPin(min-max(1.4, 5.5)) 44 | 45 | ; spice: 46 | ; "[X] " 47 | 48 | public pcb-module module (v-out:Double) : 49 | port vin 50 | port vout 51 | port gnd 52 | port en 53 | inst ps : ocdb/components/texas-instruments/TLV743P/component(v-out) 54 | cap-strap(gnd, ps.in, 1.0e-6) 55 | cap-strap(gnd, ps.out, 1.0e-6) 56 | net (vin, ps.in) 57 | net (vout, ps.out) 58 | net (gnd, ps.gnd) 59 | net (en, ps.en) 60 | 61 | public pcb-module mod : 62 | inst m : module(3.3) 63 | -------------------------------------------------------------------------------- /components/texas-instruments/TPD1E10B06.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/texas-instruments/TPD1E10B06 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | pcb-landpattern dpy-landpattern : 18 | for (l in grid-locs(1, 2, 1.0, 0.0), i in [1 2]) do : 19 | pad p[i] : smd-pad(0.6, 0.5) at l 20 | 21 | layer(Courtyard(Top)) = Rectangle(1.6, 0.8) 22 | layer(Silkscreen("f-silk", Top)) = LineRectangle(1.6, 0.8) 23 | ref-label() 24 | 25 | public pcb-component component : 26 | manufacturer = "Texas Instruments" 27 | mpn = "TPD1E10B06DYPT" 28 | description = "Single-Channel ESD Protection Diode in 0402 Package" 29 | 30 | port p : pin[[1 2]] 31 | landpattern = dpy-landpattern(p[1] => dpy-landpattern.p[1], p[2] => dpy-landpattern.p[2]) 32 | symbol = diode-tvs(p[1] => diode-tvs.a, p[2] => diode-tvs.c) 33 | 34 | public pcb-module module : 35 | inst c : component 36 | -------------------------------------------------------------------------------- /components/texas-instruments/TPD3S0x4.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/texas-instruments/TPD3S0x4 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/bundles 13 | import ocdb/utils/generator-utils 14 | import ocdb/utils/generic-components 15 | import ocdb/utils/box-symbol 16 | import ocdb/utils/property-structs 17 | 18 | public pcb-component component : 19 | manufacturer = "Texas Instruments" 20 | mpn = "TPD3S014DBVR" 21 | description = "USB power and data protection" 22 | pin-properties : 23 | [pin:Ref | pads:Int ... | side:Dir | generic-pin:GenericPin] 24 | [GND | 2 | Down | -] 25 | [IN | 3 | Left | GenericPin(min-max(-0.3, 6.0), 2.0e3)] 26 | [OUT | 4 | Right | GenericPin(min-max(-0.3, 6.0), 2.0e3)] 27 | [EN | 1 | Left | GenericPin(min-max(-0.3, 6.0), 2.0e3)] 28 | [D1 | 5 | Right | GenericPin(min-max(-0.3, 6.0), 12.0e3)] 29 | [D2 | 6 | Right | GenericPin(min-max(-0.3, 6.0), 12.0e3)] 30 | assign-landpattern(SOT95P280X145-6N) 31 | make-box-symbol() 32 | property(self.IN.power-pin) = PowerPin(min-max(4.5, 5.5)) 33 | property(self.rated-temperature) = min-max(-40.0, 85.0) 34 | 35 | 36 | public pcb-module module : 37 | port usb-in : usb-2 38 | port usb-out : usb-2 39 | port en 40 | 41 | public inst tpd : ocdb/components/texas-instruments/TPD3S0x4/component 42 | net (usb-in.vbus.vdd tpd.IN) 43 | net (usb-in.vbus.gnd tpd.GND usb-out.vbus.gnd) 44 | net (usb-out.vbus.vdd tpd.OUT) 45 | net (usb-in.data.P tpd.D1 usb-out.data.P) 46 | net (usb-in.data.N tpd.D2 usb-out.data.N) 47 | net (usb-in.id usb-out.id) 48 | net (tpd.EN en) 49 | cap-strap(tpd.IN, tpd.GND, 0.1e-6) 50 | cap-strap(tpd.OUT, tpd.GND, 10.0e-6) 51 | 52 | schematic-group(self) = TPD3S0x4 53 | -------------------------------------------------------------------------------- /components/texas-instruments/TPS27081A.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/texas-instruments/TPS27081A : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | pcb-landpattern sot23-landpattern : 18 | for (l in grid-locs(3, 2, 2.7, 0.95), i in [1 6 2 5 3 4]) do : 19 | pad p[i] : smd-pad(1.1, 0.6) at l 20 | 21 | layer(Courtyard(Top)) = Rectangle(3.8, 2.5) 22 | layer(Silkscreen("f-silk", Top)) = LineRectangle(2.9, 2.5) 23 | ref-label() 24 | 25 | public pcb-component component : 26 | manufacturer = "Texas Instruments" 27 | mpn = "TPS27081ADDCR" 28 | description = "1.2-V to 8-V, 3-A PFET High-Side Load Switch With Level Shift and Adjustable Slew Rate Control" 29 | 30 | pin-properties : 31 | [pin:Ref | pads:Int ... | side:Dir] 32 | [ON_OFF | 5 | Left ] 33 | [R1_C1 | 6 | Left ] 34 | [R2 | 1 | Right ] 35 | [VIN | 4 | Left ] 36 | [VOUT | 2, 3 | Right ] 37 | 38 | make-box-symbol() 39 | assign-landpattern(sot23-landpattern) 40 | 41 | public pcb-module module : 42 | inst c : component 43 | -------------------------------------------------------------------------------- /components/texas-instruments/TPS610986.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/texas-instruments/TPS610986 : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | public pcb-component component : 18 | manufacturer = "Texas Instruments" 19 | mpn = "TPS610986DSE" 20 | description = "Ultra-Low Quiescent Current Synchronous Boost with Integrated LDO/Load Switch" 21 | 22 | pin-properties : 23 | [pin:Ref | pads:Int ... | side:Dir] 24 | [VMAIN | 1 | Left ] 25 | [SW | 2 | Left ] 26 | [VIN | 3 | Left ] 27 | [MODE | 4 | Right ] 28 | [VSUB | 5 | Right ] 29 | [GND | 6 | Right ] 30 | 31 | make-box-symbol() 32 | assign-landpattern(dfn-landpattern(6, 0.5, [0.25 0.5], 0.5, [1.5 1.5])) 33 | 34 | public pcb-module module : 35 | port gnd 36 | port vbat 37 | port v-boost 38 | port v-sw 39 | port sw 40 | 41 | inst boost : ocdb/components/texas-instruments/TPS610986/component 42 | net (gnd, boost.GND) 43 | ; decoupling caps 44 | cap-strap(gnd, boost.VIN, 0.1e-6) 45 | cap-strap(gnd, boost.VSUB, 10.0e-6) 46 | cap-strap(gnd, boost.VMAIN, 10.0e-6) 47 | inst r : chip-resistor(390.0) 48 | inst l : smd-inductor(["inductance" => 4.7e-6, "min-current-saturation" => 0.9]) 49 | 50 | net (l.p[1], boost.SW) 51 | net (vbat, l.p[2], r.p[1]) 52 | net (r.p[2], boost.VIN) 53 | cap-strap(l.p[2], gnd, 10.0e-6) 54 | 55 | net (v-boost, boost.VMAIN) 56 | net (v-sw, boost.VSUB) 57 | net (sw, boost.MODE) 58 | -------------------------------------------------------------------------------- /components/toshiba/DF2B6M4ASL-L3F.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/toshiba/DF2B6M4ASL-L3F : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/landpatterns 10 | import ocdb/utils/symbols 11 | import ocdb/utils/symbol-utils 12 | import ocdb/utils/generic-components 13 | import ocdb/utils/box-symbol 14 | import ocdb/utils/bundles 15 | import ocdb/utils/design-vars 16 | import ocdb/utils/property-structs 17 | import ocdb/utils/checks 18 | import ocdb/utils/generator-utils 19 | 20 | pcb-landpattern DF2B6M4ASL-L3F-lp : 21 | val pad-shape = smd-pad(0.21, 0.32) 22 | pad p[1] : pad-shape at loc(-0.2, 0.0, 0.0) 23 | pad p[2] : pad-shape at loc( 0.2, 0.0, 0.0) 24 | 25 | layer(Silkscreen("F-SilkS", Top)) = Line(0.2, [ Point(-0.4, 0.3), Point(-0.4, 0.3) ]) 26 | layer(Courtyard(Top)) = Rectangle(0.9, 0.6) 27 | ref-label() 28 | 29 | public pcb-component component : 30 | name = "BI-DIRECTIONAL SINGLE ESD PROTEC" 31 | manufacturer = "Toshiba" 32 | mpn = "DF2B6M4ASL,L3F" 33 | reference-prefix = "D" 34 | pin-properties : 35 | [pin:Ref | pads:Ref ... | side:Dir| generic-pin:GenericPin | power-pin:PowerPin ] 36 | [p[1] | a | Left | - | - ] 37 | [p[2] | c | Right | - | - ] 38 | 39 | val Z = 0.21 + 0.5 40 | val G = 0.4 - 0.21 41 | val X = 0.32 42 | assign-landpattern(two-pin-polarized-landpattern(Z, G, X, 0.32, 0.62)) 43 | make-box-symbol() 44 | -------------------------------------------------------------------------------- /components/unisonic/U74LVC1G125G-AL5-R.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/unisonic/U74LVC1G125G-AL5-R : 3 | 4 | import core 5 | import collections 6 | import math 7 | 8 | import jitx 9 | import jitx/commands 10 | 11 | import ocdb/utils/defaults 12 | import ocdb/utils/landpatterns 13 | import ocdb/utils/symbols 14 | import ocdb/utils/symbol-utils 15 | import ocdb/utils/generic-components 16 | 17 | import ocdb/utils/bundles 18 | import ocdb/utils/box-symbol 19 | import ocdb/utils/property-structs 20 | import ocdb/utils/generator-utils 21 | import ocdb/utils/checks 22 | import ocdb/utils/land-protrusions 23 | 24 | public pcb-component component : 25 | port nOE 26 | port A 27 | port GND 28 | port Y 29 | port Vcc 30 | 31 | name = "U74LVC1G125G-AL5-R" 32 | manufacturer = "UTC(Unisonic Tech)" 33 | description = "Buffers 3-State Outputs SOT-353 74 Series ROHS" 34 | reference-prefix = "U" 35 | mpn = "U74LVC1G125G-AL5-R" 36 | 37 | val generic-props = GenericPin(min-max(-0.3, 3.6), 1500.0) 38 | pin-properties : 39 | [pin:Ref | pads:Int ... | side:Dir| generic-pin:GenericPin] 40 | [nOE | 1 | Left | generic-props ] 41 | [A | 2 | Left | generic-props ] 42 | [GND | 3 | Down | generic-props ] 43 | [Y | 4 | Right | generic-props ] 44 | [Vcc | 5 | Up | generic-props ] 45 | 46 | make-box-symbol() 47 | assign-landpattern(SOT-353) 48 | property(self.rated-temperature) = min-max(-40.0, 85.0) 49 | 50 | public pcb-module module : 51 | port supply : power 52 | port A 53 | port Y 54 | port nOE 55 | 56 | inst U1 : ocdb/components/unisonic/U74LVC1G125G-AL5-R/component 57 | net (supply.gnd U1.GND) 58 | net (supply.vdd U1.Vcc) 59 | bypass-cap-strap(supply.vdd, supply.gnd, 1.000e-6) 60 | net (A U1.A) 61 | net (Y U1.Y) 62 | net (nOE U1.nOE) -------------------------------------------------------------------------------- /components/windbond/W25Q128JVSIQ.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/windbond/W25Q128JVSIQ : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | 9 | import ocdb/utils/defaults 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/symbol-utils 13 | import ocdb/utils/generic-components 14 | 15 | import ocdb/utils/box-symbol 16 | import ocdb/utils/bundles 17 | 18 | 19 | public pcb-component component : 20 | port spi:spi-peripheral() 21 | pin-properties : 22 | [pin:Ref | pads:Int ... | side:Dir] 23 | [nWP | 3 | Left ] 24 | [nHOLD | 7 | Left ] 25 | [spi.cs | 1 | Left ] 26 | [spi.sdo | 2 | Left ] 27 | [spi.sdi | 5 | Left ] 28 | [GND | 4 | Down ] 29 | [spi.sck | 6 | Left ] 30 | [VCC | 8 | Up ] 31 | 32 | make-box-symbol() 33 | assign-landpattern(soic127p-landpattern(8)) 34 | 35 | mpn = "W25Q128JVSIQ" 36 | manufacturer = "Winbond Electronics" 37 | description = "FLASH - NOR Memory IC SPI - Quad I/O, QPI, DTR 133MHz 8-SOIC" 38 | 39 | public pcb-module module: 40 | port power : power 41 | port spi: spi-peripheral() 42 | port wp 43 | port hold 44 | 45 | inst flash : ocdb/components/windbond/W25Q128JVSIQ/component 46 | cap-strap(flash.VCC, flash.GND, 0.1e-6) 47 | net (power.vdd, flash.VCC) 48 | net (power.gnd, flash.GND) 49 | net (spi, flash.spi) 50 | net (wp, flash.nWP) 51 | net (hold, flash.nHOLD) 52 | -------------------------------------------------------------------------------- /components/wurth/691412320002M.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/wurth/691412320002M : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/symbols 12 | import ocdb/utils/box-symbol 13 | import ocdb/utils/bundles 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | 17 | pcb-landpattern header-landpattern : 18 | val offset = loc(0.595, 1.2) 19 | pad p[1] : pth-pad(1.0) at loc(1.905, 2.5) * offset 20 | pad p[2] : pth-pad(1.0) at loc((- 1.905), (- 2.5)) * offset 21 | layer(Courtyard(Top)) = Rectangle(9.12, 12.0) 22 | ref-label() 23 | 24 | public pcb-component component : 25 | manufacturer = "Wurth Elektronik" 26 | mpn = "691412320002M" 27 | description = "TERM BLOCK 2POS 45DEG 3.81MM PCB" 28 | 29 | port p : pin[[1 2]] 30 | val pkg = header-landpattern 31 | val sym = header-symbol(2) 32 | landpattern = pkg(p[1] => pkg.p[1], p[2] => pkg.p[2]) 33 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2]) 34 | 35 | public pcb-module module : 36 | inst c : component 37 | -------------------------------------------------------------------------------- /components/xkb/TS-1187A-C-C-B.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/xkb/TS-1187A-C-C-B : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/bundles 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/generator-utils 12 | import ocdb/utils/generic-components 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | 16 | pcb-landpattern TS-1187A-C-C-B-pkg : 17 | pad p[1] : smd-pad(1.0, 0.7) at loc(-3.0, 1.85) 18 | pad p[2] : smd-pad(1.0, 0.7) at loc(3.0, 1.85) 19 | pad p[3] : smd-pad(1.0, 0.7) at loc(-3.0, -1.85) 20 | pad p[4] : smd-pad(1.0, 0.7) at loc(3.0, -1.85) 21 | layer(Courtyard(Top)) = Rectangle(7.0, 5.1) 22 | layer(Silkscreen("pol", Top)) = Circle(-3.75, 1.85, 0.1) 23 | layer(Silkscreen("f-silk", Top)) = Line(0.127, [ Point(-2.55, 2.55), Point(2.55, 2.55) ]) 24 | layer(Silkscreen("f-silk", Top)) = Line(0.127, [ Point(-2.55, -2.55), Point(2.55, -2.55) ]) 25 | ref-label() 26 | 27 | pcb-component xkb-TS-1187A-C-C-B : 28 | pin-properties : 29 | [pin:Ref | pads:Int ... ] 30 | [p | 1 2 ] 31 | [t | 3 4 ] 32 | make-box-symbol() 33 | assign-landpattern(TS-1187A-C-C-B-pkg) 34 | 35 | manufacturer = "XKB Enterprise" 36 | mpn = "TS-1187A-C-C-B" 37 | description = "SPST Vertical Round Button 260gf SMD,5.1x5.1x1.7mm Tactile Switches" -------------------------------------------------------------------------------- /components/yangxing-tech/X322516MLB4SI.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/components/yangxing-tech/X322516MLB4SI : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/bundles 10 | import ocdb/utils/landpatterns 11 | import ocdb/utils/generator-utils 12 | import ocdb/utils/generic-components 13 | import ocdb/utils/symbols 14 | import ocdb/utils/box-symbol 15 | 16 | pcb-landpattern yt-X322516MLB4SI-pkg : 17 | pad p[1] : smd-pad(1.4, 1.15) at loc(-1.1, -0.8, 0.0) 18 | pad g[1] : smd-pad(1.4, 1.15) at loc(1.1, -0.8, 0.0) 19 | pad p[2] : smd-pad(1.4, 1.15) at loc(1.1, 0.8, 0.0) 20 | pad g[2] : smd-pad(1.4, 1.15) at loc(-1.1, 0.8, 0.0) 21 | layer(Courtyard(Top)) = Rectangle(4.2, 3.4) 22 | layer(Silkscreen("pol", Top)) = Circle(-2.1, -1.0, 0.1) 23 | ref-label() 24 | 25 | public pcb-component component : 26 | port p : pin[[1 2]] 27 | port gnd 28 | mpn = "X322516MLB4SI" 29 | manufacturer = "Yangxing Tech" 30 | val sym = crystal-sym(2) 31 | val lp = yt-X322516MLB4SI-pkg 32 | symbol = sym(p[1] => sym.p[1], p[2] => sym.p[2], gnd => sym.gnd) 33 | landpattern = lp(p[1] => lp.p[1], p[2] => lp.p[2], gnd => lp.g[1], gnd => lp.g[2]) 34 | reference-prefix = "X" 35 | 36 | property(self.load-capacitance) = 9.0e-12 37 | -------------------------------------------------------------------------------- /deprecated-tests/esir2-harness.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(esir2) 2 | defpackage ocdb/tests/esir2-harness : 3 | import core 4 | import collections 5 | import math 6 | import esir2 7 | import esir2/repl-lib 8 | import ocdb/tests/default-harness 9 | import ocdb/utils/generic-components 10 | import ocdb/utils/generator-utils 11 | 12 | val module = ocdb/components/microsemi/A2F200M3F-FGG256I/module 13 | 14 | make-default-board(module, 4, Rectangle(30.0, 18.0)) 15 | export-kicad("esir2-ocdb-harness", [`preplaced => false, 16 | `gen-board => true, 17 | `paper => ISO-A4, 18 | `gen-schematic => true]) 19 | -------------------------------------------------------------------------------- /deprecated-tests/rc-network.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(esir) 2 | defpackage ocdb/rc-network : 3 | import core 4 | import collections 5 | import math 6 | import esir 7 | import esir/utils 8 | import esir/gen 9 | import ocdb/tests/default-harness 10 | import ocdb/utils/box-symbol 11 | import ocdb/pinspec 12 | import esir/repl-lib 13 | pcb-component battery : 14 | port pos 15 | port neg 16 | ; spice: 17 | ; "[V] PULSE(0 5 0 0 0 1 1 0)" 18 | pcb-component resistor: 19 | port a 20 | port b 21 | ; spice: 22 | ; "[R] 550" 23 | pcb-component capacitor: 24 | port pos 25 | port neg 26 | ; spice: 27 | ; "[C] 470u" 28 | 29 | pcb-module main: 30 | inst bat: battery 31 | inst res: resistor 32 | inst cap: capacitor 33 | net (bat.pos, res.a) 34 | net (res.b, cap.pos) 35 | net gnd (cap.neg, bat.neg) 36 | pcb-design main-design: 37 | module = main 38 | -------------------------------------------------------------------------------- /deprecated-tests/simple-boxes.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(esir) 2 | defpackage ocdb/tests/test-simple-boxes : 3 | import core 4 | import collections 5 | import esir 6 | import esir/gen 7 | import ocdb/utils/box-symbol 8 | import ocdb/tests/default-harness 9 | 10 | pcb-component box2 : 11 | port a 12 | port b 13 | make-box-symbol $ [ 14 | Left => a 15 | Right => b] 16 | 17 | pcb-component chip : 18 | port p : pin[20] 19 | make-box-symbol $ [ 20 | Left => p[0 to 5] 21 | Right => p[5 to 10] 22 | Up => p[10 to 15] 23 | Down => p[15 to 20]] 24 | 25 | pcb-module main : 26 | inst b1 : box2[4] 27 | inst b2 : box2[4] 28 | inst c : chip 29 | for i in 0 to length(b1) do : 30 | net (c.p[0], b1[i].a) 31 | net (b1[i].b, c.p[1]) 32 | for i in 0 to length(b2) do : 33 | net (c.p[6], b2[i].a) 34 | net (b2[i].b, c.p[7]) 35 | 36 | pcb-design main-design : 37 | module = main 38 | board = {default-board(4, 10.0, 10.0)} 39 | -------------------------------------------------------------------------------- /deprecated-tests/stanza.proj: -------------------------------------------------------------------------------- 1 | package ocdb/tests/test-pinspec defined-in "test-pinspec.stanza" 2 | package ocdb/tests/test-simple-boxes defined-in "simple-boxes.stanza" 3 | package ocdb/tests/default-harness defined-in "default-harness.stanza" 4 | package ocdb/tests/test-emodel-sym defined-in "test-emodel-sym.stanza" 5 | package ocdb/tests/test-bom defined-in "test-bom.stanza" 6 | package ocdb/tests/test-user-checks defined-in "test-user-checks.stanza" 7 | package ocdb/tests/test-box-symbol defined-in "test-box-symbol.stanza" 8 | package ocdb/tests/test-powergen defined-in "test-powergen.stanza" 9 | package ocdb/tests/test-refdb defined-in "test-refdb.stanza" -------------------------------------------------------------------------------- /deprecated-tests/test-blank.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(esir) 2 | defpackage ocdb/tutorial : 3 | import core 4 | import collections 5 | import math 6 | import esir 7 | import esir/utils 8 | import esir/gen 9 | import ocdb/tests/default-harness 10 | import esir/repl-lib 11 | import ocdb/utils/generator-utils 12 | import jitpcb/visualizer 13 | 14 | pcb-module my-design : 15 | inst r : example-resistor 16 | inst t : {ocdb/components/wurth/691412320002M/component} 17 | 18 | val main-design = default-board(my-design, 4, 100.0, 75.0) 19 | 20 | view(ocdb/components/wurth/691412320002M/component) 21 | ;view(main-design) -------------------------------------------------------------------------------- /deprecated-tests/test-bom.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(esir) 2 | defpackage ocdb/tests/test-bom : 3 | import core 4 | import collections 5 | import esir 6 | import ocdb/utils/box-symbol 7 | import ocdb/tests/default-harness 8 | 9 | pcb-package mypackage : 10 | unique pcb-pad square : 11 | type = SMD 12 | shape = Rectangle(0.1, 0.1, loc(0.0, 0.0)) 13 | for i in 1 through 10 do : 14 | pad a[i] : {square} at loc(to-double(i) * 0.2, 0.0) 15 | for i in 1 through 10 do : 16 | pad b[i] : {square} at loc(to-double(i) * 0.2, 2.0) 17 | 18 | pcb-component mycomponent : 19 | port A : pin[10] 20 | port B : pin[10] 21 | make-box-symbol $ [ 22 | Left => A[0 to 10] 23 | Right => B[0 to 10]] 24 | package = mypackage( 25 | for i in 0 to 10 do : 26 | A[i] => a[i + 1] 27 | for i in 0 to 10 do : 28 | B[i] => b[i + 1]) 29 | manufacturer = "TE Connectivity Potter & Brumfield Relays" 30 | mpn = "V23105A5001A201" 31 | 32 | pcb-component mycomponent2 : 33 | port A : pin[10] 34 | port B : pin[10] 35 | package = mypackage( 36 | for i in 0 to 10 do : 37 | A[i] => a[i + 1] 38 | for i in 0 to 10 do : 39 | B[i] => b[i + 1]) 40 | make-box-symbol $ [ 41 | BoxBank $ [ 42 | Left => A[0 to 4] 43 | Right => B[0 to 4]] 44 | BoxBank $ [ 45 | Left => A[4 to 10] 46 | Right => B[4 to 10]]] 47 | 48 | pcb-package smallp : 49 | unique pcb-pad square : 50 | type = SMD 51 | shape = Rectangle(0.1, 0.1) 52 | pad a : {square} at loc(-1.0, 0.0) 53 | pad b : {square} at loc(1.0, 0.0) 54 | external-names = ["0402"] 55 | 56 | pcb-component myresistor : 57 | port a 58 | port b 59 | emodel = Resistor(10.0) 60 | package = smallp(a => a, b => b) 61 | 62 | pcb-module main : 63 | inst c1 : mycomponent 64 | inst c2 : mycomponent2 65 | package(c1) at loc(0.0, 0.0) on Top 66 | ;package(c2) at loc(0.0, 0.0) on Top 67 | net (c1.A[0], c2.A[1]) 68 | inst r : myresistor 69 | 70 | pcb-design main-design : 71 | module = main 72 | rules = default-rules 73 | board = {default-board(4, 10.0, 10.0)} -------------------------------------------------------------------------------- /deprecated-tests/test-box-symbol.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(esir) 2 | defpackage ocdb/tests/test-box-symbol : 3 | import core 4 | import collections 5 | import esir 6 | import ocdb/utils/box-symbol 7 | import ocdb/tests/default-harness 8 | 9 | pcb-package mypackage : 10 | unique pcb-pad square : 11 | type = SMD 12 | shape = Rectangle(0.1, 0.1, loc(0.0, 0.0)) 13 | for i in 1 through 11 do : 14 | pad a[i] : {square} at loc(to-double(i) * 0.2, 0.0) 15 | for i in 1 through 11 do : 16 | pad b[i] : {square} at loc(to-double(i) * 0.2, 2.0) 17 | 18 | pcb-component mycomponent : 19 | port A : pin[10] 20 | port B : pin[10] 21 | mpn = "Box-13V" 22 | make-box-symbol $ [ 23 | Left => A[0 to 10] 24 | Right => B[0 to 10]] 25 | package = mypackage( 26 | for i in 0 to 10 do : 27 | A[i] => a[i + 1] 28 | A[0] => a[11] 29 | for i in 0 to 10 do : 30 | B[i] => b[i + 1] 31 | B[0] => b[11]) 32 | 33 | pcb-component mycomponent2 : 34 | port A : pin[10] 35 | port B : pin[10] 36 | mpn = "Box-13V2NXP" 37 | package = mypackage( 38 | for i in 0 to 10 do : 39 | A[i] => a[i + 1] 40 | for i in 0 to 10 do : 41 | B[i] => b[i + 1]) 42 | make-box-symbol $ [ 43 | BoxBank $ [ 44 | Left => A[0 to 4] 45 | Right => B[0 to 4]] 46 | BoxBank $ [ 47 | Left => A[4 to 10] 48 | Right => B[4 to 10]]] 49 | 50 | pcb-module main : 51 | inst c1 : mycomponent 52 | inst c2 : mycomponent2 53 | package(c1) at loc(0.0, 0.0) on Top 54 | ;package(c2) at loc(0.0, 0.0) on Top 55 | net (c1.A[0], c2.A[1]) 56 | 57 | pcb-design main-design : 58 | module = main 59 | rules = default-rules 60 | board = {default-board(4, 10.0, 10.0)} -------------------------------------------------------------------------------- /deprecated-tests/test-emodel-sym.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(esir) 2 | defpackage ocdb/tests/test-emodel-sym : 3 | import core 4 | import collections 5 | import esir 6 | import ocdb/utils/box-symbol 7 | import ocdb/tests/default-harness 8 | 9 | pcb-symbol mysymbol : 10 | pin a at Point(-1.0, 0.0) 11 | pin b at Point(1.0, 0.0) 12 | draw("foreground") = Circle(1.0) 13 | draw("foreground") = Text(">VALUE", 0.7, W, loc(2.0, 0.0)) 14 | draw("foreground") = Text(">REF", 0.7, W, loc(2.0, 2.0)) 15 | 16 | pcb-component mycomponent : 17 | port a 18 | port b 19 | mpn = "Box-13V" 20 | symbol = mysymbol(a => a, b => b) 21 | 22 | pcb-module main : 23 | inst c1 : mycomponent 24 | emodel(c1) = Resistor(10.0) 25 | 26 | pcb-design main-design : 27 | module = main 28 | rules = default-rules 29 | board = {default-board(4, 10.0, 10.0)} -------------------------------------------------------------------------------- /deprecated-tests/test-node-removal.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(esir) 2 | defpackage ocdb/tests/test-node-removal : 3 | import core 4 | import collections 5 | import esir 6 | import ocdb/tests/default-harness 7 | 8 | pcb-bundle simple-b : 9 | port p 10 | 11 | pcb-component mycomponent : 12 | port a 13 | port b 14 | supports simple-b : 15 | p => a 16 | supports simple-b : 17 | p => b 18 | ; spice: "APIN " 19 | ; spice: "BPIN " 20 | ; spice: "NET " 21 | 22 | pcb-module mymodule : 23 | port a 24 | port b 25 | ; spice: "MNET " 26 | inst c : mycomponent 27 | net (a, c.a) 28 | 29 | pcb-module mymodule2 : 30 | port a 31 | port b 32 | 33 | pcb-module main : 34 | inst c1 : mycomponent 35 | inst c2 : mycomponent 36 | net gnd (c1.a) 37 | net na (c1.a, c1.b) 38 | net nb (c2.a, c2.b) 39 | require a:simple-b from c1 40 | require b:simple-b from c2 41 | net (a, b) 42 | 43 | pcb-module main2 : 44 | inst m : mymodule 45 | inst m2 : mymodule2 46 | ; spice: "CONNECT_PIN " 47 | ; spice: "CONNECT_MODULE " 48 | net gnd (m2.a, m2.b) 49 | 50 | pcb-design main-design : 51 | module = main 52 | rules = default-rules 53 | board = {default-board(4, 10.0, 10.0)} 54 | 55 | ;val esir = repl-lib/assign-concrete-pins() 56 | ;match(esir:Collection) : 57 | ; do(println, esir) -------------------------------------------------------------------------------- /deprecated-tests/test-simple-package.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(esir) 2 | defpackage ocdb/tests/test-simple-package : 3 | import core 4 | import collections 5 | import esir 6 | import ocdb/tests/default-harness 7 | import ocdb/utils/box-symbol 8 | 9 | pcb-package mypackage : 10 | unique pcb-pad square : 11 | type = SMD 12 | shape = Rectangle(0.1, 0.1) 13 | for i in 1 through 10 do : 14 | val x = to-double(i) * 0.2 15 | if i % 2 == 0 : 16 | pad a[i] : {square} at loc(x, 0.0) 17 | else : 18 | pad a[i] : {square} at loc(x, 0.0) on Bottom 19 | 20 | pcb-component mycomponent : 21 | port A : pin[{1 through 10}] 22 | package = mypackage( 23 | for i in 1 through 10 do : 24 | A[i] => a[i]) 25 | make-box-symbol $ [ 26 | Left => A[1 through 5] 27 | Right => A[6 through 10]] 28 | 29 | pcb-module main : 30 | inst c : mycomponent 31 | package(c) at loc(0.0, 0.0) on Top 32 | 33 | pcb-design main-design : 34 | module = main 35 | rules = default-rules 36 | board = {default-board(4, 10.0, 10.0)} -------------------------------------------------------------------------------- /deprecated-tests/test-user-checks.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(esir) 2 | defpackage ocdb/tests/test-user-checks : 3 | import core 4 | import collections 5 | import esir 6 | import esir/gen 7 | import ocdb/tests/default-harness 8 | 9 | pcb-component mycomponent : 10 | port A : pin[10] 11 | port B : pin[10] 12 | for p in ports(A) do : 13 | properties({p}) : 14 | voltage => 1.0 15 | for p in ports(B) do : 16 | properties({p}) : 17 | voltage => 2.0 18 | 19 | pcb-component mycomponent2 : 20 | port A : pin[10] 21 | port B : pin[10] 22 | for p in ports(A) do : 23 | properties({p}) : 24 | voltage => 3.0 25 | for p in ports(B) do : 26 | properties({p}) : 27 | voltage => 4.0 28 | 29 | for i in 0 to 5 do : 30 | check voltage-levels(A[i], 1.0, 5.0) 31 | for i in 0 to 5 do : 32 | check voltage-levels(B[i], 1.0, 5.0) 33 | 34 | pcb-check voltage-levels (p:Ref, min:Double, max:Double) : 35 | #CHECK(has-property?(p.voltage)) 36 | #CHECK(property(p.voltage) >= min) 37 | #CHECK(property(p.voltage) <= max) 38 | 39 | pcb-module main : 40 | inst c1 : mycomponent2 41 | inst c2 : mycomponent2 42 | inst c3 : mycomponent2 43 | 44 | pcb-design main-design : 45 | module = main 46 | board = {default-board(4, 10.0, 10.0)} -------------------------------------------------------------------------------- /derating/space-derating.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/space-derating : 2 | import core 3 | import collections 4 | 5 | 6 | ; need to update this with better data: 7 | ; https://forum.digikey.com/t/understanding-ceramic-capacitor-temp-coefficients/727 8 | 9 | public var DESIGN-TEMPERATURE:Double = 0.0 10 | 11 | ; RESISTOR DERATING PARAMETERS 12 | public var DERATE-RESISTOR-POWER = 0.6 13 | public var DERATE-INDUCTOR-POWER = 0.6 14 | 15 | ; CAPACITOR DERATING PARAMETERS (fake) 16 | ; Temperature-dependant PWL derating on peak voltage 17 | public var DERATE-CAPACITOR-MLCC-VPK-NOM = [[85.0 0.6] [125.0 0.4]] 18 | public var DERATE-CAPACITOR-MLCC-VPK-WC = [[85.0 0.45] [125.0 0.25]] 19 | ; Maximum allowed temperature 20 | public var DERATE-CAPACITOR-MLCC-TEMP = 120.0 21 | 22 | ; Derating on maximum voltage 23 | public var DERATE-CAPACITOR-MICA-VPK = 0.6 24 | ; Maximum allowed temperature 25 | public var DERATE-CAPACITOR-MICA-TEMP = 100.0 26 | 27 | ; Derating on maximum voltage 28 | public var DERATE-CAPACITOR-ETANTPOLY-VPK = 0.55 29 | ; Maximum allowed temperature 30 | public var DERATE-CAPACITOR-ETANTPOLY-TEMP = 100.0 31 | 32 | ; Temperature-dependant PWL derating on peak voltage 33 | public var DERATE-CAPACITOR-ETANTMNO2-VPK-WC = [[22.0 0.8] [85.0 0.6] [125.0 0.15]] 34 | public var DERATE-CAPACITOR-ETANTMNO2-VPK-NOM = [[22.0 0.75] [85.0 0.55]] 35 | ; Derating on maximum voltage for high surge current 36 | public var DERATE-CAPACITOR-ETANTMNO2-VPK = 0.45 37 | ; Maximum allowed temperature 38 | public var DERATE-CAPACITOR-ETANTMNO2-TEMP-WC = 120.0 39 | public var DERATE-CAPACITOR-ETANTMNO2-TEMP-NOM = 80.0 40 | -------------------------------------------------------------------------------- /designs/class-a.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/designs/class-a : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import ocdb/utils/defaults 8 | import jitx/commands 9 | import ocdb/utils/checks 10 | 11 | import ocdb/utils/bundles 12 | import ocdb/utils/generic-components 13 | import ocdb/utils/landpatterns 14 | import ocdb/utils/box-symbol 15 | 16 | pcb-module class-a-amplifier (r-set:Double) : 17 | port vin:power 18 | port in 19 | port out 20 | inst r1 : chip-resistor(110.0e3) 21 | inst r2 : chip-resistor(10.0e3) 22 | inst r3 : chip-resistor(10.0e3) 23 | inst r4 : chip-resistor(r-set) 24 | 25 | inst c : ceramic-cap(0.1e-6) 26 | 27 | inst bjt : ocdb/components/nexperia/PMBT3904/component 28 | 29 | net (vin.vdd r1.p[1] r3.p[1]) 30 | net (bjt.c r3.p[2]) 31 | net (bjt.b r1.p[2] c.p[2] r2.p[1]) 32 | net (bjt.e r4.p[1]) 33 | net (in c.p[1]) 34 | net (vin.gnd r2.p[2] r4.p[2]) 35 | 36 | pcb-component power-connector (v-out:Double) : 37 | port src:power 38 | ; spice: 39 | ; "[V] " 40 | 41 | description = "Power connector" 42 | mpn = "2X1-pin-header" 43 | pin-properties : 44 | [pin:Ref | pads:Int ... ] 45 | [src.vdd | 1 ] 46 | [src.gnd | 2 ] 47 | 48 | assign-landpattern(pin-header-pkg(2, 1, 2.54, 2.54)) 49 | make-box-symbol() 50 | 51 | pcb-module demo : 52 | 53 | inst power : power-connector(20.0) 54 | inst amp : class-a-amplifier(2.0e3) 55 | inst j : pin-header(5) 56 | net gnd (power.src.gnd, j.p[1]) 57 | net (power.src, amp.vin) 58 | net vdd (power.src.vdd, j.p[2]) 59 | 60 | ; spice: 61 | ; "[Vi] {amp.in} {power.src.gnd} SIN(0 1 1k 0 0)" 62 | 63 | ; spice: 64 | ; ".temp 80.0" 65 | ; ".tran 0.01ms 5m" 66 | 67 | set-current-design("output-class-a") 68 | 69 | make-default-board(demo, 4, Rectangle(30.0, 20.0)) 70 | 71 | ;Export design to Kicad 72 | ; export-netlist(checks.gnd, "hello-world.cir") 73 | export-cad() 74 | 75 | ; export-netlist(demo.gnd, "ClassA.cir") 76 | -------------------------------------------------------------------------------- /designs/example-designs.md: -------------------------------------------------------------------------------- 1 | # Example Designs in OCDB 2 | 3 | # Designs 4 | | Design Name | Design Description | Concept Used | 5 | |-------------------------------|--------------------------------- |-------------------- | 6 | | `ble-mote.stanza` | Wireless sensor node: ESP32 + sensors | require stmts, bundles, placed components, copper pours | 7 | | `can-stm32.stanza` | CAN bus connector with STM32 | require stmts, bundles | | 8 | | `class-a.stanza` | Simple class A bipolar amp | | | 9 | | `doc-examples.stanza` | Component search | component search | 10 | | `ethernet-fmc.stanza` | FPGA + ethernet connector with LVDS | require stmts, bundles | 11 | | `grid-resistors.stanza` | Simple programmatic resistor implementation | | 12 | | `lp-examples.stanza` | Standard 2 pin land pattern exploration | | 13 | | `mcu.stanza` | STM32 microcontroller implementation | component search | 14 | | `power-monitor.stanza` | FPGA with LVDS connections + power monitor | bus termination | 15 | | `power-state-demo.stanza` | simple example of using power state properties | design properties | 16 | | `smd-landpatterns.stanza` | Intro to soldermask defined BGA land patterns || 17 | | `test-component-checks.stanza`| Intro to component creation and usage | component creation | 18 | | `tutorial.stanza` | Tutorial code (from quickstart guides) | | 19 | | `usb-accel.stanza` | STM32 + Accel + USB | require stmts | 20 | | `usb-light.stanza` | Programmatic placement of components and wiring | Placed components, copper traces| 21 | | `voltage-divider.stanza` | Simple example of using circuit generators | circuit generators | -------------------------------------------------------------------------------- /designs/grid-resistors.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/designs/grid-resistors : 3 | import core 4 | 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/defaults 8 | import ocdb/utils/generic-components 9 | 10 | val board-shape = RoundedRectangle(10.0, 10.0, 0.5) 11 | 12 | pcb-module series-resistor : 13 | port a 14 | port b 15 | 16 | inst r1 : chip-resistor(1.0e3) 17 | inst r2 : chip-resistor(1.0e2) 18 | 19 | net (a r1.p[1]) 20 | net (b r1.p[2]) 21 | net (r1.p[2] r2.p[1]) 22 | 23 | pcb-module series-resistors (n: Int) : 24 | port a 25 | port b 26 | 27 | var previous-pin = a 28 | for idx in 1 through n do : 29 | inst r : chip-resistor(to-double(idx) * 1.0e3) 30 | net (previous-pin r.p[1]) 31 | 32 | previous-pin = r.p[2] 33 | 34 | net (previous-pin b) 35 | 36 | pcb-module grid-resistors (s-count: Int, p-count: Int) : 37 | port a 38 | port b 39 | 40 | for _ in 0 to p-count do : 41 | inst s : series-resistors(s-count) 42 | net (a s.a) 43 | net (b s.b) 44 | 45 | defn run-design (circuit: Instantiable) : 46 | set-current-design("output-grid-resistors") 47 | make-default-board(circuit, 2, board-shape) 48 | 49 | view-board() 50 | view-schematic() 51 | 52 | run-design(grid-resistors(3, 4)) 53 | -------------------------------------------------------------------------------- /designs/mcu.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/designs/mcu : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/defaults 8 | import ocdb/utils/generic-components 9 | import ocdb/utils/bundles 10 | import ocdb/utils/design-vars 11 | import ocdb/utils/micro-controllers 12 | 13 | set-current-design("output-mcu") 14 | 15 | val BOARD-SHAPE = RoundedRectangle(25.0, 25.0, 0.25) 16 | DESIGN-QUANTITY = 0 17 | OPTIMIZE-FOR = ["area"] 18 | 19 | val mcu-parameters = ["series" => "STM32F4" "mpn" => "STM32F410RBI6"] ; "mpn" => "STM32F410TBY6"] 20 | val module-parameters = [`debug-interface => jtag()] 21 | 22 | pcb-module mcu-design (mcu:Instantiable): 23 | inst stm32 : mcu 24 | require leds : gpio[3] from stm32.mcu 25 | require usart : usart([UART-RX UART-TX])[3] from stm32.mcu 26 | require spi : spi-controller()[3] from stm32.mcu 27 | require i2s : i2s() from stm32.mcu 28 | ; require i2c : i2c[3] from stm32.mcu 29 | 30 | add-mounting-holes(BOARD-SHAPE, [2, 3]) 31 | 32 | val best-mcu = find-micro-controller(mcu-parameters, module-parameters, mcu-design) 33 | 34 | match(value?(best-mcu)): 35 | (mcu:Instantiable): 36 | make-default-board(mcu-design(mcu), 4, BOARD-SHAPE) 37 | ; view-board() 38 | view-schematic() 39 | (_:False) : println("No mcu fits this design.") 40 | -------------------------------------------------------------------------------- /designs/run-checks/checked-design.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/designs/run-checks/checked-design : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/checks 8 | import ocdb/utils/defaults 9 | import ocdb/manufacturers/rules 10 | import ocdb/manufacturers/stackups 11 | import ocdb/utils/generator-utils 12 | import ocdb/utils/property-structs 13 | import ocdb/designs/run-checks/capacitors 14 | import ocdb/designs/run-checks/digital-io 15 | import ocdb/designs/run-checks/inductors 16 | import ocdb/designs/run-checks/resistors 17 | 18 | pcb-module main-module : 19 | inst rs: resistors 20 | inst cs: capacitors 21 | inst ls: inductors 22 | inst io: digital-io 23 | 24 | net VDD (rs.power.vdd, ls.power.vdd, cs.power.vdd) 25 | net GND (rs.power.gnd, ls.power.gnd, cs.power.gnd, io.power.gnd) 26 | 27 | inst tp : ocdb/components/keystone/500xx/component("yellow") 28 | property(tp.p.power-supply-pin) = PowerSupplyPin(typ(5.0), 0.1) 29 | net PS-VDD (tp.p io.power.vdd) 30 | 31 | property(VDD.voltage) = typ(5.0) 32 | property(PS-VDD.voltage) = typ(5.0) 33 | property(GND.voltage) = typ(0.0) 34 | check-design(self) 35 | 36 | val brd-outline = Rectangle(50.0, 50.0) 37 | pcb-board B : 38 | stackup = jlcpcb-jlc2313 39 | boundary = brd-outline 40 | signal-boundary = brd-outline 41 | 42 | defn main () : 43 | set-current-design("output-checked-design") 44 | set-board(B) 45 | set-rules(jlcpcb-rules) 46 | set-main-module(main-module) 47 | run-final-passes(main-module) 48 | run-checks("checks.txt") 49 | 50 | main() 51 | -------------------------------------------------------------------------------- /designs/smd-landpatterns.stanza: -------------------------------------------------------------------------------- 1 | ; Demonstration of transforming landpatterns to use soldermask-defined pads 2 | #use-added-syntax(jitx) 3 | defpackage ocdb/designs/smd-landpatterns : 4 | import core 5 | import collections 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/box-symbol 10 | import ocdb/utils/landpatterns 11 | 12 | ; A BGA package with 100 pins 13 | pcb-landpattern my-landpattern: 14 | make-bga-pkg( 15 | 1.0, ; pitch:Double, 16 | 0.5; pad-diam:Double, 17 | [4, 4]; n-pads:[Int Int], 18 | [5.0, 5.0]; courtyard:[Double Double], 19 | false ; omit-pads:Tuple|False 20 | ) 21 | ref-label() 22 | 23 | pcb-component my-component (smd?:True|False): 24 | ; ocdb/landpatterns/soldermask-defined is a transformation on pads and landpatterns 25 | ; to convert into "soldermask defined" pads (SMD) where the soldermask opening is smaller 26 | ; than the copper layer beneath them. 27 | val lp = soldermask-defined(my-landpattern) when smd? else my-landpattern 28 | assign-landpattern(lp) 29 | make-box-symbol() 30 | 31 | pcb-module main-module: 32 | inst smd-cmp: my-component(true) 33 | inst nsmd-cmp: my-component(false) 34 | 35 | set-current-design("output-smd-landpatterns") 36 | 37 | make-default-board(main-module, 4, Rectangle(10.0, 10.0)) 38 | view-board() 39 | -------------------------------------------------------------------------------- /designs/stanza.proj: -------------------------------------------------------------------------------- 1 | include "../stanza.proj" 2 | -------------------------------------------------------------------------------- /designs/usb-accel.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/designs/usb-accel : 3 | 4 | import core 5 | import collections 6 | import math 7 | import jitx 8 | import jitx/commands 9 | 10 | import ocdb/utils/bundles 11 | import ocdb/utils/connects 12 | import ocdb/utils/defaults 13 | import ocdb/utils/design-vars 14 | import ocdb/utils/generator-utils 15 | import ocdb/utils/generic-components 16 | import ocdb/utils/property-structs 17 | import ocdb/utils/checks 18 | import ocdb/utils/micro-controllers 19 | 20 | val BOARD-SHAPE = RoundedRectangle(50.0, 50.0, 0.25) 21 | pcb-module accel: 22 | port power : power 23 | inst accel : ocdb/components/st-microelectronics/LIS3DH/module 24 | inst mcu : ocdb/components/st-microelectronics/STM32F105VBH6/module([]) 25 | require intrpts:gpio[2] from mcu.mcu 26 | inst usb : micro-usb-connector 27 | inst ldo : ocdb/components/diodes-incorporated/AP2112/module 28 | require spi1:spi-controller() from mcu.mcu 29 | connect-spi(mcu.mcu, spi1, [accel.spi]) 30 | net (intrpts[0].gpio accel.int[1]) 31 | net (intrpts[1].gpio accel.int[2]) 32 | 33 | ; Create a protected power and data interface for USB-2 34 | net gnd (mcu.power.gnd usb.usb-2.vbus.gnd power.gnd) 35 | val protected-usb = ocdb/modules/protection/esd-clamp(usb.usb-2, gnd) as JITXObject 36 | net P5V0 (ldo.vin.vdd ldo.en mcu.mcu.PA[9] usb.usb-2.vbus.vdd) 37 | net (mcu.mcu.PA[11] usb.usb-2.data.N) 38 | net (mcu.mcu.PA[12] usb.usb-2.data.P) 39 | net P3V3 (ldo.vout.vdd accel.power.vdd mcu.power.vdd power.vdd) 40 | net (gnd accel.power.gnd) 41 | symbol(P5V0) = ocdb/utils/symbols/supply-sym 42 | symbol(P3V3) = ocdb/utils/symbols/supply-sym 43 | symbol(gnd) = ocdb/utils/symbols/ground-sym 44 | 45 | set-current-design("output-usb-accel") 46 | 47 | make-default-board(accel, 4, BOARD-SHAPE) 48 | view-board() 49 | view-schematic() -------------------------------------------------------------------------------- /designs/voltage-divider.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/designs/voltage-divider : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/checks 10 | import ocdb/modules/passive-circuits 11 | import ocdb/utils/bundles 12 | import ocdb/utils/landpatterns 13 | import ocdb/utils/generator-utils 14 | import ocdb/utils/generic-components 15 | import ocdb/utils/design-vars 16 | 17 | OPERATING-TEMPERATURE = min-max(0.0, 40.0) 18 | 19 | pcb-module demo : 20 | 21 | inst fmc : ocdb/components/samtec/ASP-134488-01/component 22 | net gnd (fmc.gnd) 23 | 24 | ; Add voltage property to vadj pin 25 | property(fmc.vadj.voltage) = min-typ-max(4.95 5.0 5.05) 26 | 27 | ; Create a voltage divider to output a 0.5V that stays within 0.4925 < V < 0.5175. Target current : 1mA, use 0.5% resistors 28 | make-voltage-divider(fmc.vadj, fmc.la03-n, gnd, min-typ-max(0.4925 0.5 0.5175) 1.0e-3, 0.5) 29 | 30 | ; Same as above, but solve for a resistor tolerance that passes checks 31 | make-voltage-divider(fmc.vadj, fmc.la04-n, gnd, min-typ-max(0.4925 0.5 0.5175) 1.0e-3) 32 | 33 | ; Same as above, but solve for a resistor tolerance that passes checks, and use default for divider current 34 | make-voltage-divider(fmc.vadj, fmc.la05-n, gnd, min-typ-max(0.4925 0.5 0.5175)) 35 | 36 | make-default-board(demo, 4, Rectangle(32.0, 12.0)) 37 | 38 | 39 | ; Export design to open JITX ESIR format, and checks to a text file 40 | ; export-xml("vdiv.xml" [`lowered => true `check-log => "v-div-checks.txt"]) 41 | -------------------------------------------------------------------------------- /doc/generated-tests.md: -------------------------------------------------------------------------------- 1 | # Generated macro validity testing on pull requests 2 | 3 | Search for public `pcb-*` macros with 0 or 1 argument of primitive type and make a deftest for each with `print-def` to evaluate them. 4 | Tests for `pcb-module` are not run in this v1 because they can require access to the online part database and take longer to run. 5 | 6 | If no annotation is present, default values used are: 7 | ``` 8 | TYPE_SAMPLE = { 9 | "Char": '"c"', 10 | "String": '"hello world"', 11 | "Byte": '1Y', 12 | "Int": '1', 13 | "Long": '1L', 14 | "Float": '1.0F', 15 | "Double": '1.0', 16 | "True|False": 'true' 17 | } 18 | ``` 19 | 20 | The syntax to specify the value to test a macro on is exemplified by: 21 | ``` 22 | ; 23 | n-pins: value1 value2 value3 24 | 25 | public pcb-component component (n-pins:Int) : 26 | ``` 27 | In this example 3 tests will be generated: 28 | ``` 29 | deftest test-ocdb_amphenol_minitek127_component: 30 | print-def(ocdb/components/amphenol/minitek127/component(value1)) 31 | 32 | deftest test-ocdb_amphenol_minitek127_component: 33 | print-def(ocdb/components/amphenol/minitek127/component(value2)) 34 | 35 | deftest test-ocdb_amphenol_minitek127_component: 36 | print-def(ocdb/components/amphenol/minitek127/component(value3)) 37 | ``` 38 | 39 | To use a random even integer between 2 and 100 use: 40 | ``` 41 | ; 42 | n: even positive 43 | 44 | public pcb-landpattern soic127p-landpattern (n:Int) : 45 | ``` 46 | 47 | To skip a test do: 48 | ``` 49 | ;skip 50 | n-pins: value1 value2 value3 51 | 52 | public pcb-component component (n-pins:Int) : 53 | ``` 54 | or 55 | ``` 56 | ;skip 57 | public pcb-component component : 58 | ``` 59 | -------------------------------------------------------------------------------- /scripts/gen-components-file.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -eu 2 | echo "defpackage ocdb/components :" > components.stanza 3 | grep -rh 'defpackage ocdb/components/.*\s*:' components |\ 4 | sed 's/://g' |\ 5 | sort -k 2 |\ 6 | sed 's/defpackage/ import/g' >> components.stanza 7 | -------------------------------------------------------------------------------- /scripts/gen-ocdb-app.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/gen-app : 2 | import core 3 | 4 | val preamble = \ 5 | defpackage fig-app : 6 | import core 7 | import collections 8 | import math 9 | import jitx 10 | import jitx/gen 11 | import jitx/commands 12 | import ocdb/utils/defaults 13 | import ocdb/utils/landpatterns 14 | import ocdb/utils/generic-components 15 | import jitx/visualizer 16 | 17 | 18 | val epilogue = \ 19 | 20 | 21 | defn main () : 22 | val args = command-line-arguments() 23 | fatal("Wrong number of arguments %_ usage: gen-ocdb-app url svg code" % [args]) when length(args) != 4 24 | val filename = to-string("/tmp/stanza-fig-gen-%_.stanza" % [current-time-ms()]) 25 | val url-string = args[1] 26 | val svg-string = args[2] 27 | val code-string = args[3] 28 | ; val filename = "output.stanza" 29 | ; val string = \ 30 | ; println("hello world") 31 | ; 32 | val string = to-string("%_\nval URL = \"%_\"\n\n%_%_" % [preamble, url-string, code-string, epilogue]) 33 | spit(filename, string) 34 | call-system("stanza" ["stanza" "run" filename]) 35 | delete-file(filename) 36 | 37 | main() 38 | -------------------------------------------------------------------------------- /scripts/ocdb-gen.stanza: -------------------------------------------------------------------------------- 1 | ; script used to generate ocdb.stanza 2 | defpackage ocdb/gen : 3 | import core 4 | import collections 5 | 6 | val ignored-paths = [ 7 | ".git", 8 | ".github", 9 | "designs", 10 | "doc", 11 | "tests", 12 | "deprecated-tests", 13 | "style-guide" 14 | "ocdb.stanza" 15 | "scripts" 16 | ] 17 | 18 | defn package-names (path) -> Seq : 19 | generate: 20 | for file in dir-files(path) do: 21 | ; println("Checking: %~" % [file]) 22 | if not (contains?(ignored-paths, file)) : 23 | val next-path = to-string("%_/%_" % [path, file]) 24 | match(file-type(next-path)) : 25 | (_:DirectoryType): 26 | for pkg in package-names(next-path) do : 27 | yield(pkg) 28 | (_:?) : 29 | if suffix?(next-path, ".stanza"): 30 | ; println("extracting from %_ ..." % [next-path]) 31 | for line in filter(prefix?{_, "defpackage"}, split(slurp(next-path), "\n")) do: 32 | val yielded = replace{_, ":", ""} $ replace(line, "defpackage ", "") 33 | if yielded != "fig-app ": ; tiny hack 34 | yield(yielded) 35 | 36 | ; get current paths 37 | val sbuf = StringBuffer() 38 | println(sbuf, "defpackage ocdb :") 39 | do(println{IndentedStream(sbuf), "import %_" % [_]}, lazy-qsort $ package-names(resolve-path("."))) 40 | println(to-string(sbuf)) 41 | -------------------------------------------------------------------------------- /slm.toml: -------------------------------------------------------------------------------- 1 | name = "ocdb" 2 | version = "3.33.0" 3 | [dependencies] 4 | -------------------------------------------------------------------------------- /stanza.proj: -------------------------------------------------------------------------------- 1 | ;==================================== 2 | ;============ Utilities ============= 3 | ;==================================== 4 | packages ocdb/utils/* defined-in "utils" 5 | packages ocdb/manufacturers/* defined-in "manufacturers" 6 | 7 | ;==================================== 8 | ;============= Scripts ============= 9 | ;==================================== 10 | packages ocdb/scripts/* defined-in "scripts" 11 | 12 | ;==================================== 13 | ;======== Circuit libraries ========= 14 | ;==================================== 15 | packages ocdb/modules/* defined-in "modules" 16 | 17 | ;==================================== 18 | ;========= Component models ========= 19 | ;==================================== 20 | packages ocdb/components/* defined-in "components" 21 | packages ocdb/artwork/* defined-in "artwork" 22 | 23 | ;==================================== 24 | ;====== Derating parameters ========= 25 | ;==================================== 26 | package ocdb/space-derating defined-in "derating/space-derating.stanza" 27 | 28 | 29 | package ocdb defined-in "ocdb.stanza" 30 | packages ocdb/tests/* defined-in "tests" 31 | packages ocdb/designs/* defined-in "designs" 32 | 33 | build ocdb : 34 | inputs: ocdb 35 | pkg: "../build/pkgs" 36 | 37 | build-test ocdb-tests : 38 | inputs: ocdb/tests/all 39 | pkg: "../build/tests/pkgs" 40 | o: "../build/bin/test-ocdb" 41 | 42 | -------------------------------------------------------------------------------- /style-guide/fig/style-guide-01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JITx-Inc/open-components-database/3c819958fc0c76eeac4e60c1a99a070a550cb771/style-guide/fig/style-guide-01.png -------------------------------------------------------------------------------- /style-guide/fig/style-guide-02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JITx-Inc/open-components-database/3c819958fc0c76eeac4e60c1a99a070a550cb771/style-guide/fig/style-guide-02.png -------------------------------------------------------------------------------- /tests/all.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/tests/all : 2 | import ocdb/tests/bundle-connects 3 | import ocdb/tests/bom-related 4 | import ocdb/tests/checks 5 | import ocdb/tests/connects 6 | import ocdb/tests/default-component 7 | import ocdb/tests/design 8 | import ocdb/tests/landpattern-generators 9 | import ocdb/tests/landpatterns 10 | import ocdb/tests/microcontroller 11 | import ocdb/tests/naming-conventions 12 | import ocdb/tests/pads 13 | import ocdb/tests/part-query 14 | import ocdb/tests/pin-properties-index-field 15 | import ocdb/tests/pth-pads 16 | import ocdb/tests/relative-voltages 17 | import ocdb/tests/stm-pin-parsing 18 | ; segfault ; import ocdb/tests/stm32-mcu-props 19 | import ocdb/tests/symbols 20 | import ocdb/tests/tag-connects 21 | import ocdb/tests/terminations 22 | import ocdb/tests/th-landpatterns -------------------------------------------------------------------------------- /tests/bom-related.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx, tests) 2 | defpackage ocdb/tests/bom-related : 3 | import core 4 | import jitx 5 | import jitx/commands 6 | import ocdb/utils/generator-utils 7 | 8 | defn capture-output ( func : () -> ?T ) -> String : 9 | val buf = StringBuffer(128) 10 | val result:T = with-output-stream(buf, func) 11 | to-string(buf) 12 | 13 | deftest(ocdb, bom-related) test-do-not-populate : 14 | 15 | pcb-module child: 16 | inst J20: ocdb/components/tag-connect/TC2050-IDC/module 17 | inst J21: ocdb/components/tag-connect/TC2050-IDC/module 18 | 19 | pcb-module UUT: 20 | inst J10: ocdb/components/tag-connect/TC2050-IDC/module 21 | inst J11: ocdb/components/tag-connect/TC2050-IDC/module 22 | inst JA1 : ocdb/components/tag-connect/TC2050-IDC/module[4] 23 | inst UUTkid : child 24 | 25 | pcb-module M1: 26 | inst J1 : ocdb/components/tag-connect/TC2050-IDC/module 27 | inst J2 : ocdb/components/tag-connect/TC2050-IDC/module 28 | 29 | inst J3: ocdb/components/tag-connect/TC2050-IDC/module 30 | inst J4: ocdb/components/tag-connect/TC2050-IDC/module 31 | inst J5: ocdb/components/tag-connect/TC2050-IDC/module 32 | 33 | inst MU : UUT 34 | 35 | dnp(J1) 36 | dnp([J3, J4, J5]) 37 | ; - I expect this to recursive set dnp for all 38 | ; children and grandchildren. 39 | dnp(MU) 40 | 41 | print-def(M1) 42 | -------------------------------------------------------------------------------- /tests/checks.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(tests, jitx) 2 | defpackage ocdb/tests/checks : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/checks 10 | import ocdb/utils/generator-utils 11 | 12 | import ocdb/utils/generic-components 13 | import ocdb/manufacturers/stackups 14 | import ocdb/manufacturers/rules 15 | import ocdb/utils/symbols 16 | 17 | pcb-module checks : 18 | ; Design goes here 19 | inst c1 : ceramic-cap(1.0e-6) 20 | inst c2 : tantalum-cap(1.0e-6) 21 | inst c3 : gen-cap-cmp(1.0e-6) 22 | inst c4 : gen-tant-cap-cmp(1.0e-6) 23 | 24 | inst r1 : chip-resistor(1.0e3) 25 | inst r2 : gen-res-cmp(1.0e3) 26 | 27 | inst i1 : smd-inductor(4.7e-6) 28 | inst i2 : gen-ind-cmp(4.7e-6) 29 | inst d1 : gen-led-cmp("0603") 30 | 31 | net gnd () 32 | net single-pin1 () 33 | net single-pin2 () 34 | net single-pin3 () 35 | res-strap(gnd, single-pin1, 10.0e3) 36 | cap-strap(gnd, single-pin2, 10.0e-9) 37 | ind-strap(gnd, single-pin3, 2.2e-6) 38 | 39 | net (gnd c1.p[1] c2.c c3.p[1] c4.c r1.p[1] r2.p[1] d1.c) 40 | 41 | #EXPECT(connected?([c1.p[1] c2.c c3.p[1] c4.c r1.p[1] r2.p[1] d1.c])) 42 | #EXPECT(connected?(c1.p[2]) == false) 43 | #EXPECT(connected?(c2.a) == false) 44 | #EXPECT(connected?(c3.p[2]) == false) 45 | #EXPECT(connected?(c4.a) == false) 46 | #EXPECT(connected?(r1.p[2]) == false) 47 | #EXPECT(connected?(r2.p[2]) == false) 48 | #EXPECT(connected?(d1.a) == false) 49 | 50 | val brd-outline = Rectangle(50.0, 50.0) 51 | pcb-board B : 52 | stackup = sierra-circuits-6-layer-62-mil 53 | boundary = brd-outline 54 | signal-boundary = brd-outline 55 | 56 | deftest(ocdb, checks) test-checks-in-design : 57 | set-main-module(checks) 58 | set-board(B) 59 | set-rules(sierra-adv-rules) 60 | -------------------------------------------------------------------------------- /tests/connects.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx, tests) 2 | defpackage ocdb/tests/connects : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/connects 8 | import ocdb/utils/bundles 9 | 10 | defn expect-fatal (body:() -> ?): 11 | var caught? = false 12 | execute-with-error-handler( 13 | body, 14 | fn (e): caught? = true 15 | ) 16 | #EXPECT(caught?) 17 | 18 | deftest(ocdb, connects) test-connect-i2c-isolation: 19 | pcb-module M1: 20 | port p: i2c[[1, 2]] 21 | connect-i2c-isolation(p[1], p[2]) 22 | 23 | pcb-module M2: 24 | port p: i2c[[1, 2]] 25 | connect-i2c-isolation(p[1], p[2], M1) 26 | 27 | pcb-module M3: 28 | port x: i2c 29 | port y: gpio 30 | var caught? = false 31 | within expect-fatal(): 32 | connect-i2c-isolation(x, y) 33 | 34 | for mod in [M1, M2, M3] do: 35 | print-def(mod) 36 | 37 | deftest(ocdb, connects) test-connect-phy: 38 | pcb-module M1: 39 | port x: rgmii 40 | port y: ethernet-1000 41 | connect-phy(x, y) 42 | pcb-module M2: 43 | port x: rgmii 44 | port y: gpio 45 | within expect-fatal(): 46 | connect-phy(x, y) 47 | pcb-module M3: 48 | port x: gpio 49 | port y: ethernet-1000 50 | within expect-fatal(): 51 | connect-phy(x, y) 52 | for mod in [M1, M2, M3] do: 53 | print-def(mod) 54 | 55 | deftest(ocdb, connects) test-connect-ft2332: 56 | pcb-module M1: 57 | port x: usb-2 58 | port y: uart([UART-DTR, UART-RTS, UART-RX, UART-TX]) 59 | connect-ft232(x, y) 60 | 61 | pcb-module M2: 62 | port x: usb-2 63 | port y: gpio 64 | within expect-fatal(): 65 | connect-ft232(x, y) 66 | 67 | pcb-module M3: 68 | port x: gpio 69 | port y: uart([UART-DTR, UART-RTS, UART-RX, UART-TX]) 70 | within expect-fatal(): 71 | connect-ft232(x, y) 72 | 73 | for mod in [M1, M2, M3] do: 74 | print-def(mod) 75 | -------------------------------------------------------------------------------- /tests/default-component.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(tests, jitx) 2 | defpackage ocdb/tests/default-component : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/defaults 8 | import ocdb/utils/landpatterns 9 | import ocdb/components/st-microelectronics/landpatterns 10 | 11 | defn test (lp:LandPattern): 12 | val component = default-component(lp) 13 | val pins = to-tuple(pins(component)) 14 | val pads = to-tuple(pads(lp)) 15 | #EXPECT(length(pins) == length(pads)) 16 | 17 | deftest(odcb, default-component) test-default-component-one-pin : 18 | test(testpad(1.0)) 19 | 20 | deftest(odcb, default-component) test-default-component-even : 21 | test(UFBGA100) 22 | 23 | deftest(odcb, default-component) test-default-component-odd : 24 | test(UFBGA121) 25 | -------------------------------------------------------------------------------- /tests/design.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx, tests) 2 | defpackage ocdb/tests/design : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import jitx/check-api 8 | import ocdb/utils/defaults 9 | import ocdb/utils/checks 10 | 11 | public defn test-design (case:String, 12 | main-module:Instantiable 13 | num-layers:Int, 14 | board-shape:Shape, 15 | rules:Rules) : 16 | val name = to-string $ "test-board-%_" % [case] 17 | pcb-module main-module* : 18 | inst m:main-module 19 | check-design(self) 20 | 21 | deftest(ocdb, design, long) (name) : 22 | set-current-design(name) 23 | set-board(default-board(num-layers, board-shape)) 24 | set-main-module(main-module*) 25 | set-rules(rules) 26 | val result = run-checks(to-string $ "%_.checks.txt" % [name]) 27 | #ASSERT(num-failed(result) == 0) 28 | -------------------------------------------------------------------------------- /tests/landpattern-generators.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(tests, jitx) 2 | defpackage ocdb/tests/landpattern-generators : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/landpatterns 8 | import ocdb/components/st-microelectronics/landpatterns 9 | import ocdb/utils/defaults 10 | import ocdb/manufacturers/rules 11 | import ocdb/tests/design 12 | 13 | deftest bga-pad-names : 14 | val s = "ABCDEFGHJKLMNPRTUVWY" 15 | val pin-names = BGAPadNames(length(s), length(s), false) 16 | for (ch in s, r in 0 to false) do: 17 | #EXPECT(pin-names[r, 0] == Ref(to-string(ch))[1]) 18 | 19 | defn find-silkscreen (x, name) : 20 | for layer in layers(x) find : 21 | val spec = specifier(layer) 22 | match(spec:Silkscreen): 23 | /name(spec) == name 24 | 25 | defn test-landpattern-in-design (lp:LandPattern) : 26 | pcb-module module : 27 | inst i: default-component(lp) 28 | test-design(name(lp), module, 4, Rectangle(20.0, 20.0), sierra-adv-rules) 29 | 30 | defn basic-landpattern-test (lp:LandPattern, expect-pol?:True) : 31 | val name = to-string $ "basic-landpattern-test-%_" % [name(lp)] 32 | deftest(ocdb, landpattern) (name) : 33 | ; check that it has a courtyard 34 | val courtyard = find({specifier(_) is Courtyard}, layers(lp)) 35 | #EXPECT(courtyard is-not False) 36 | 37 | ; check that there is an indicator, if necessary 38 | if expect-pol?: 39 | #EXPECT(find-silkscreen(lp, "pol") is-not False) 40 | 41 | ; check that the reference label exists 42 | val ref-label = find-silkscreen(lp, "values") 43 | #EXPECT(ref-label is-not False) 44 | 45 | for landpattern in STM32-LAND-PATTERNS do : 46 | basic-landpattern-test(landpattern, true) 47 | test-landpattern-in-design(landpattern) 48 | 49 | deftest(ocdb, landpattern) sot : 50 | pcb-module main-module : 51 | inst c1 : ocdb/utils/defaults/default-component(SOT23-3) 52 | inst c2 : ocdb/utils/defaults/default-component(TO-236) 53 | inst c3 : ocdb/utils/defaults/default-component(SOT23()) 54 | 55 | make-default-board(main-module, 4, Rectangle(10.0, 10.0)) 56 | view(TO-236) 57 | -------------------------------------------------------------------------------- /tests/naming-conventions.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(tests, jitx) 2 | defpackage ocdb/tests/naming-conventions : 3 | import core 4 | import collections 5 | import ocdb/utils/landpatterns 6 | import jitx 7 | 8 | deftest(ocdb, naming-conventions) test-bga-naming : 9 | val pad-names = BGAPadNames(30, 30, false) 10 | #EXPECT(pad-names[0, 0]== IndexRef(Ref("A"), 1)) 11 | #EXPECT(pad-names[8, 6]== IndexRef(Ref("J"), 7)) 12 | #EXPECT(pad-names[20, 4] == IndexRef(Ref("AA"), 5)) 13 | #EXPECT(pad-names[21, 3] == IndexRef(Ref("AB"), 4)) 14 | 15 | deftest(ocdb, naming-conventions) test-bga-naming-stress : 16 | for row in 0 to 1000 do: 17 | red-alph-letter(row) -------------------------------------------------------------------------------- /tests/pads.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx, tests) 2 | defpackage ocdb/tests/pads : 3 | import core 4 | import collections 5 | import math 6 | import jitx 7 | import jitx/commands 8 | import ocdb/utils/defaults 9 | import ocdb/utils/symbols 10 | import ocdb/utils/box-symbol 11 | import ocdb/utils/landpatterns 12 | import ocdb/utils/bundles 13 | import ocdb/utils/generator-utils 14 | import ocdb/utils/generic-components 15 | 16 | pcb-landpattern lp (n:Int) : 17 | for i in 0 to n by 6 do : 18 | val d = to-double(i) * 2.0 19 | val drill = 0.5 20 | val x = 1.0 21 | val y = 2.0 22 | pad p[i] : pth-pad(drill / 2., x / 2.) at loc(d, d) 23 | pad p[i + 1] : oval-pth-pad(drill, x, y) at loc(d + 2.0, d + 2.0) 24 | pad p[i + 2] : rect-pth-pad(drill, x, y) at loc(d + 4.0, d + 4.0) 25 | pad p[i + 3] : round-rect-pth-pad(drill, x, y, 0.25) at loc(d + 6.0, d + 6.0) 26 | pad p[i + 4] : dshape-pth-pad(drill, x, y, y, 0.5) at loc(d + 8.0, d + 8.0) 27 | pad p[i + 5] : chamfered-rect-pth-pad(drill, x, y, y, 0.5) at loc(d + 10.0, d + 10.0) 28 | ref-label() 29 | 30 | pcb-symbol sym (n:Int) : 31 | for i in 0 to n do : 32 | val d = to-double(i) * 2.54 33 | pin p[i] at Point(d, d) 34 | 35 | pcb-component ldo-9000-sym (n:Int) : 36 | name = "AP2112" 37 | manufacturer = "Diodes Incorporated" 38 | description = "600-mA, Low-Dropout Regulator" 39 | mpn = "AP2112K-3.3TRG1" 40 | reference-prefix = "A" 41 | 42 | port p : pin[n] 43 | 44 | val sym = sym(n) 45 | val lp = lp(n) 46 | symbol = sym(for i in 0 to n do : p[i] => sym.p[i]) 47 | landpattern = lp(for i in 0 to n do : p[i] => lp.p[i]) 48 | 49 | pcb-module ldo : 50 | val num-pins = 6 51 | public inst l : ldo-9000-sym(num-pins)[4] 52 | 53 | ocdb/tests/design/test-design("pads-pin-design", ldo, 4, Rectangle(10.0, 10.0), default-rules) 54 | -------------------------------------------------------------------------------- /tests/pin-properties-index-field.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx, tests) 2 | defpackage ocdb/tests/pin-properties-index-field : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/box-symbol 8 | import ocdb/utils/landpatterns 9 | 10 | deftest(ocdb, pin-properties-index-field) test-pin-properties-index-field : 11 | set-default-rules(ocdb/utils/defaults/default-rules) 12 | 13 | pcb-landpattern SO4N : 14 | make-n-pin-soic-landpattern(4, 1.27, 15 | tol(6.0, 0.2), tol(3.9, 0.1), 16 | tol(4.9, 0.1), min-typ-max(0.4, 1.04, 1.27), 17 | min-typ-max(0.28, 0.38, 0.48), 18 | false) 19 | 20 | pcb-component mycomponent : 21 | pin-properties : 22 | [pin:Ref | pads:Int ...] 23 | [a.x | 1 ] 24 | [a.y | 2 ] 25 | [b.y | 3 ] 26 | [b.x | 4 ] 27 | make-box-symbol() 28 | assign-landpattern(SO4N) 29 | 30 | #EXPECT(property(mycomponent.a.x.pin-properties-row-index) == 0) 31 | #EXPECT(property(mycomponent.a.y.pin-properties-row-index) == 1) 32 | #EXPECT(property(mycomponent.b.y.pin-properties-row-index) == 2) 33 | #EXPECT(property(mycomponent.b.x.pin-properties-row-index) == 3) 34 | -------------------------------------------------------------------------------- /tests/pth-pads.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx, tests) 2 | defpackage ocdb/tests/pth-pads : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/landpatterns 8 | import ocdb/utils/defaults 9 | import ocdb/utils/box-symbol 10 | 11 | deftest(ocdb, path-pads, design) pth-pad-hole-radius: 12 | pcb-landpattern test-landpattern: 13 | val radius = 0.5 14 | val width = 2.0 15 | val length = 2.0 16 | 17 | val generators = [ 18 | oval-pth-pad, 19 | rect-pth-pad, 20 | fn (r:Double, w:Double, h:Double): 21 | round-rect-pth-pad(r, w, h, 0.5), 22 | fn (r:Double, w:Double, h:Double): 23 | chamfered-rect-pth-pad(r, w, h, 0.5), 24 | fn (r:Double, w:Double, h:Double): 25 | general-round-rect-pth-pad(r, w, h, [0.25, 0.35, 0.45, 0.5]) 26 | fn (r:Double, w:Double, h:Double): 27 | general-round-rect-pth-pad(r, w, h, 0.5, CornerModifierAll) 28 | fn (r:Double, w:Double, h:Double): 29 | general-chamfered-rect-pth-pad(r, w, h, [0.25, 0.35, 0.45, 0.5]) 30 | fn (r:Double, w:Double, h:Double): 31 | general-chamfered-rect-pth-pad(r, w, h, 0.5, CornerModifierAll) 32 | ] 33 | for (gen in generators, i in 1 to false) do: 34 | val ref = IndexRef(Ref("p"), i) 35 | val def = gen(radius, width, length) 36 | pad (ref): def at loc(0.0, to-double(i) * length + 0.5 * length) 37 | 38 | val cutout = find!({specifier(_) is Cutout}, layers(def)) 39 | #ASSERT(shape(cutout) is Capsule) 40 | val hole-shape = shape(cutout) as Capsule 41 | #EXPECT(/width(hole-shape) == 2.0 * radius) 42 | #EXPECT(/height(hole-shape) == 2.0 * radius) 43 | 44 | pcb-component test-component: 45 | port p: pin[[1]] 46 | make-box-symbol() 47 | val lp = test-landpattern 48 | landpattern = 49 | lp(p[1] => lp.p[1]) 50 | 51 | pcb-module main-module: 52 | inst i: test-component 53 | place(i) on Top 54 | 55 | make-default-board(main-module, 4, Rectangle(10.0, 50.0)) 56 | -------------------------------------------------------------------------------- /tests/tag-connects.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx, tests) 2 | defpackage ocdb/tests/tag-connects : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/defaults 8 | import ocdb/components/tag-connect/TC2050-IDC 9 | import ocdb/components/tag-connect/TC2050-IDC-NL 10 | import ocdb/components/samtec/FTSH-105-01-DV 11 | 12 | public pcb-module my-design : 13 | inst J1: ocdb/components/tag-connect/TC2050-IDC/module 14 | inst J2: ocdb/components/tag-connect/TC2050-IDC-NL/module 15 | inst J3: ocdb/components/samtec/FTSH-105-01-DV/module 16 | 17 | defn main () : 18 | evaluate(my-design) 19 | 20 | deftest(ocdb, tag-connects) test-tag-connects-compile : 21 | main() 22 | -------------------------------------------------------------------------------- /tests/th-landpatterns.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx, tests) 2 | defpackage ocdb/tests/th-landpatterns : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/landpatterns 8 | import ocdb/utils/defaults 9 | import ocdb/utils/box-symbol 10 | 11 | set-rules(default-rules) 12 | public pcb-component radial (r:String, p?:True|False): 13 | reference-prefix = r 14 | pcb-landpattern lp: 15 | make-two-pin-radial-landpattern( 16 | tol(5.0, 0.5), 17 | 2.0, 18 | tol(0.5, 0.0) 19 | p? 20 | ) 21 | if p?: 22 | port a 23 | port c 24 | landpattern = lp(a => lp.a, c => lp.c) 25 | else: 26 | port p: pin[[1 2]] 27 | landpattern = lp(p[1] => lp.p[1], p[2] => lp.p[2]) 28 | make-box-symbol() 29 | 30 | public pcb-component axial (r:String, p?:True|False): 31 | reference-prefix = r 32 | port p: pin[[1 2]] 33 | pcb-landpattern lp: 34 | make-two-pin-axial-landpattern( 35 | tol(6.5, 0.0), 36 | tol(2.5, 0.0), 37 | 0.5, 38 | tol(0.58, 0.05), 39 | p? 40 | ) 41 | if p?: 42 | landpattern = lp( 43 | p[1] => lp.a 44 | p[2] => lp.c 45 | ) 46 | else: 47 | landpattern = lp( 48 | p[1] => lp.p[1] 49 | p[2] => lp.p[2] 50 | ) 51 | make-box-symbol() 52 | 53 | public pcb-module th-landpatterns: 54 | inst r: axial("R", false) 55 | inst d: axial("D", true) 56 | inst c: radial("C", true) 57 | inst u: radial("U", false) 58 | 59 | place(c) at loc(-6.0, 5.0) on Top 60 | place(u) at loc(-6.0, -5.0) on Top 61 | place(r) at loc(0.0, 0.0) on Top 62 | place(d) at loc(5.0, 0.0) on Top 63 | 64 | deftest(ocdb, th-landpatterns, design) test-th-landpatterns-in-design : 65 | make-default-board(th-landpatterns, 4, Rectangle(20.0, 20.0)) 66 | view-board() 67 | -------------------------------------------------------------------------------- /utils/box-symbol.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/utils/box-symbol : 2 | forward jitx/parts/legacy-ocdb-symbols 3 | -------------------------------------------------------------------------------- /utils/bundles.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/utils/bundles : 2 | forward jitx/parts/legacy-ocdb-misc 3 | -------------------------------------------------------------------------------- /utils/calculate-connected.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/calculate-connected : 3 | import core 4 | import collections 5 | import jitx 6 | 7 | ; [TODO] nets, refs, top-level-ref 8 | 9 | val NET-TABLE = HashTable() 10 | var CALCULATE-CONNECTED:True|False = false 11 | 12 | public defn calculate-connected () : 13 | false 14 | ; inside pcb-module : 15 | ; for (n in nets(self), i in 0 to false) do : 16 | ; ; println("Register %_ as connected" % [refs(n)]) 17 | ; if length(refs(n)) > 1 : 18 | ; for r in refs(n) do : 19 | ; NET-TABLE[r] = i 20 | ; CALCULATE-CONNECTED = true 21 | 22 | public defn connected-table-calculated? () : 23 | CALCULATE-CONNECTED 24 | 25 | public defn connected? (input-r:JITXObject) : 26 | false 27 | ; val r = top-level-ref(input-r) 28 | ; key?(NET-TABLE, r) 29 | 30 | public defn connected? (input-a:JITXObject, input-b:JITXObject) : 31 | false 32 | ; val a = top-level-ref(input-a) 33 | ; val b = top-level-ref(input-b) 34 | ; val neta = get?(NET-TABLE, a) 35 | ; val netb = get?(NET-TABLE, b) 36 | ; val result = 37 | ; match(neta:Int, netb:Int) : 38 | ; neta == netb 39 | ; ; println("Connected?(%_ (%_), %_ (%_)) = %_" % [input-a, a, input-b, b, result]) 40 | ; result 41 | -------------------------------------------------------------------------------- /utils/connections.stanza: -------------------------------------------------------------------------------- 1 | ; TODO replace Connections struct in jitx/utils/netlist-checks/utils; 2 | #use-added-syntax(jitx) 3 | defpackage ocdb/utils/connections : 4 | import core 5 | import collections 6 | import jitx 7 | import jitx/commands 8 | import lang-utils 9 | 10 | ; TODO put in jitx/commands 11 | defn do-not-place? (obj:JITXObject) : 12 | has-property?(obj.DNP) and 13 | property(obj.DNP) is True 14 | 15 | doc:"A GlobalNet is a list of pins that are connected together." 16 | public defstruct GlobalNet <: Hashable&Equalable : 17 | pins:Tuple 18 | with : 19 | printer => true 20 | 21 | defmethod hash (g:GlobalNet) : 22 | val objs = qsort(to-string{ref(_)}, pins(g)) 23 | hash(objs) 24 | 25 | defmethod equal? (a:GlobalNet, b:GlobalNet) : 26 | val pins-a = map(to-string{ref(_)}, pins(a)) 27 | val pins-b = map(to-string{ref(_)}, pins(b)) 28 | set-equal?(pins-a, pins-b) 29 | 30 | doc: "A GlobalNetList is a list of all the GlobalNets in a module \ 31 | and its submodules." 32 | public defstruct GlobalNetList : 33 | nets:Tuple 34 | with : 35 | printer => true 36 | 37 | doc: "Create a GlobalNetlist from a module." 38 | public defn GlobalNetList (module:JITXObject) : 39 | val visited = HashSet(unsafe-hash, equal?) 40 | 41 | val components = 42 | for component in component-instances(module) filter : 43 | not do-not-populate?(component) 44 | 45 | val nets = to-tuple $ 46 | for component in components seq-cat : 47 | for pin in filter-by(pins(component)) seq? : 48 | if not visited[pin] and not no-connect?(pin) : 49 | val connections = to-tuple(cat([pin], connected-pins(pin))) 50 | do(add{visited, _}, connections) 51 | One(GlobalNet(connections)) 52 | else : 53 | None() 54 | 55 | GlobalNetList(nets) 56 | 57 | doc: "Return pins that are not connected to any other pins." 58 | public defn unconnected-pins (netlist:GlobalNetList) -> Tuple : 59 | to-tuple $ 60 | for net in nets(netlist) seq? : 61 | if length(pins(net)) == 1 : One(pins(net)[0]) 62 | else : None() 63 | -------------------------------------------------------------------------------- /utils/db-parts.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/utils/db-parts : 2 | forward jitx/parts/legacy-ocdb-structures 3 | -------------------------------------------------------------------------------- /utils/design-vars.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/utils/design-vars: 2 | forward jitx/parts/legacy-ocdb-design-vars 3 | -------------------------------------------------------------------------------- /utils/fonts.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/utils/fonts : 2 | forward jitx/parts/legacy-ocdb-misc 3 | -------------------------------------------------------------------------------- /utils/land-protrusions.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/utils/land-protrusions: 2 | forward jitx/parts/legacy-ocdb-landpatterns 3 | -------------------------------------------------------------------------------- /utils/landpatterns.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/utils/landpatterns : 2 | forward jitx/parts/legacy-ocdb-landpatterns 3 | -------------------------------------------------------------------------------- /utils/module-utils.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/utils/module-utils : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/bundles 8 | 9 | ; Create a 10 pin debug connector module that supports JTAG and SWD 10 | public defn make-10-pin-debug-connector-module (component:Instantiable) : 11 | inside pcb-module : 12 | ; the connecting component 13 | public inst conn: component 14 | 15 | ; the bundles we support out of the module 16 | val power-bundle = power 17 | val reset-bundle = reset 18 | val swd-bundle = swd-swo() 19 | val jtag-bundle = jtag() 20 | 21 | ; the module's i/o ports 22 | port jtag : jtag-bundle 23 | port swd : swd-bundle 24 | port power : power-bundle 25 | port reset : reset-bundle 26 | 27 | ; hook up power 28 | net (power.vdd, conn.p[1]) 29 | net (power.gnd, conn.p[3], conn.p[5], conn.p[7], conn.p[9]) 30 | supports power-bundle : 31 | power-bundle.vdd => power.vdd 32 | power-bundle.gnd => power.gnd 33 | 34 | ; hook up jtag 35 | net (jtag.tms, conn.p[2]) 36 | net (jtag.tck, conn.p[4]) 37 | net (jtag.tdo, conn.p[6]) 38 | net (jtag.tdi, conn.p[8]) 39 | net (jtag.trstn, conn.p[10]) 40 | 41 | supports jtag-bundle : 42 | jtag-bundle.tms => jtag.tms 43 | jtag-bundle.tck => jtag.tck 44 | jtag-bundle.tdo => jtag.tdo 45 | jtag-bundle.tdi => jtag.tdi 46 | jtag-bundle.trstn => jtag.trstn 47 | 48 | ; Note: this will not be used if JTAG is used with trstn 49 | net (reset.reset, conn.p[10]) 50 | supports reset-bundle : 51 | reset-bundle.reset => reset.reset 52 | 53 | net (swd.swdio, conn.p[2]) 54 | net (swd.swdclk, conn.p[4]) 55 | net (swd.swo, conn.p[6]) 56 | 57 | supports swd-bundle : 58 | swd-bundle.swdio => swd.swdio 59 | swd-bundle.swdclk => swd.swdclk 60 | swd-bundle.swo => swd.swo 61 | 62 | -------------------------------------------------------------------------------- /utils/netlist-checks/all.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/utils/netlist-checks/all : 2 | import core 3 | import collections 4 | import jitx 5 | import ocdb/utils/connections 6 | import ocdb/utils/netlist-checks/utils 7 | import ocdb/utils/netlist-checks/io-checks 8 | import ocdb/utils/netlist-checks/power-states 9 | import ocdb/utils/netlist-checks/single-pin-nets 10 | 11 | public defn check-netlist (root-module:JITXObject) : 12 | val netlist = GlobalNetList(root-module) 13 | check-io(root-module, netlist) 14 | 15 | ; Todo: re-add once supported 16 | ; check-power-states(root-module, netlist) 17 | -------------------------------------------------------------------------------- /utils/netlist-checks/single-pin-nets.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/utils/netlist-checks/single-pin-nets : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/netlist-checks/utils 8 | 9 | val NAME = "Single Pin Net Checks" 10 | val DESCRIPTION = "Nets have more than one pin" 11 | 12 | public defn check-single-pin-nets (module:JITXObject, connections:Connections) : 13 | inside pcb-module : 14 | for group in connected-groups(connections) do : 15 | check single-pin-net(group) 16 | 17 | pcb-check single-pin-net (group:Tuple) : 18 | #CHECK( condition = length(group) > 1 19 | name = NAME 20 | category = CATEGORY 21 | description = DESCRIPTION 22 | subcheck-description = "The net containing %, has more than one pin" % [map(context, group)] 23 | fail-message = "%_ is the only pin on a net." % [context(group[0])] 24 | pass-message = "%, are on the same net." % [map(context, group)] 25 | locators = group ) 26 | -------------------------------------------------------------------------------- /utils/parts.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/utils/parts : 2 | forward jitx/parts/legacy-ocdb-structures 3 | -------------------------------------------------------------------------------- /utils/passive-checks/utils.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/utils/passive-checks/utils : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | 8 | doc:"Helper to create a context string for an object being checked." 9 | public defn context (c:JITXObject) : 10 | "%_" % [ref(c)] 11 | 12 | doc:"Category used by passive component checks." 13 | public val CATEGORY = "Component Checks" 14 | 15 | doc:"Make sure that a component has the correct properties." 16 | public defn check-has-properties (name:String, 17 | thing:JITXObject, 18 | properties:Tuple) : 19 | val missing = 20 | for prop in properties seq? : 21 | match(get-property?(thing, prop)) : 22 | (one:One) : None() 23 | (none:None) : One(prop) 24 | 25 | val condition = empty?(missing) 26 | val pass = "%_ has properties: %," % [context(thing), properties] 27 | val fail = "%_ is missing properties: %," % [context(thing), missing] 28 | 29 | #CHECK( condition = condition 30 | name = name 31 | locators = [thing, originating-instantiable(thing)] 32 | description = "%_ data consistency" % [context(thing)] 33 | category = "%_ (Data)" % [CATEGORY] 34 | subcheck-description = "%_ has properties %," % [context(thing), properties] 35 | info-message = fail 36 | pass-message = pass ) 37 | 38 | 39 | doc:"Helper to check if a component has a property." 40 | public defn has-prop-msg (condition: () -> Maybe, 41 | instance: JITXObject, 42 | prop: Symbol) : 43 | val context = context(instance) 44 | val [pass?, info-msg] = 45 | match(condition()) : 46 | (one:One) : 47 | if value(one) : 48 | [true, "%_ is has property `%_`" % [context, prop]] 49 | else : 50 | [false, "%_ is missing property `%_`" % [context, prop]] 51 | (n:None) : 52 | [true, "%_ does not require property `%_`" % [context, prop]] 53 | [pass?, "Component has property `%_`" % [prop] info-msg] 54 | -------------------------------------------------------------------------------- /utils/pin-checks/all.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/utils/pin-checks/all : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/pin-checks/utils 8 | import ocdb/utils/pin-checks/generic-pin-checks 9 | import ocdb/utils/pin-checks/power-pin-checks 10 | import ocdb/utils/pin-checks/reset-pin-checks 11 | 12 | 13 | doc: "Check the pins of an instance." 14 | public defn check-pins (instance:JITXObject) : 15 | for pin in pins(instance) do : 16 | check-generic-pin(pin) when has-property?(pin.generic-pin) 17 | check-power-pin(pin) when has-property?(pin.power-pin) 18 | ; check-power-supply-pin(pin) when has-property?(pin.power-supply-pin) 19 | check-reset-pin(pin) when has-property?(pin.reset-pin) 20 | 21 | -------------------------------------------------------------------------------- /utils/pin-checks/generic-pin-checks.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/utils/pin-checks/generic-pin-checks : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/emodels 7 | import jitx/commands 8 | import ocdb/utils/property-structs 9 | import ocdb/utils/pin-checks/utils 10 | 11 | val NAME = "Generic Pin Checks" 12 | val DESCRIPTION = "Check voltage on generic pins" 13 | 14 | doc: "Check a generic pin" 15 | public defn check-generic-pin (p:JITXObject) : 16 | inside pcb-module : 17 | check generic-pin(p) 18 | 19 | pcb-check generic-pin (p:JITXObject) : 20 | val g-props = property(p.generic-pin) 21 | if (connected?(p)) : 22 | #CHECK( 23 | condition = has-property?(p.voltage) 24 | name = context(p) 25 | category = "Generic pin checks (Data)" 26 | description = DESCRIPTION 27 | subcheck-description = "Verify the generic pin has a voltage property attached" 28 | pass-message = "Pin %_ has the voltage property (%_V) attached" % 29 | [context(p), property(p.voltage)], 30 | info-message = "Pin %_ does not have the voltage property attached" % 31 | [context(p)], 32 | locators = [p] 33 | ) 34 | 35 | #CHECK( 36 | condition = in-range?(max-voltage(g-props), property(p.voltage)), 37 | name = context(p) 38 | category = "Generic pin checks" 39 | description = DESCRIPTION 40 | subcheck-description = "Verify the max voltage on a generic pin is within its allowable range", 41 | pass-message = "voltage %_V on pin %_ is within the recommended operating range %_V" 42 | % [property(p.voltage), context(p), max-voltage(g-props)], 43 | fail-message = "voltage %_V on pin %_ is outside the recommended operating range %_V" 44 | % [property(p.voltage), context(p), max-voltage(g-props)], 45 | locators = [p] 46 | ) 47 | 48 | -------------------------------------------------------------------------------- /utils/pin-checks/reset-pin-checks.stanza: -------------------------------------------------------------------------------- 1 | #use-added-syntax(jitx) 2 | defpackage ocdb/utils/pin-checks/reset-pin-checks : 3 | import core 4 | import collections 5 | import jitx 6 | import jitx/commands 7 | import ocdb/utils/property-structs 8 | import ocdb/utils/pin-checks/utils 9 | 10 | val NAME = "Reset Pin Checks" 11 | val DESCRIPTION = "Check reset pin properties" 12 | 13 | public defn check-reset-pin (p:JITXObject) : 14 | inside pcb-module : 15 | check reset-pin(p) 16 | 17 | pcb-check reset-pin (p:JITXObject) : 18 | val p-props = property(p.reset-pin) 19 | #CHECK( 20 | condition = p-props is ResetPin 21 | name = NAME 22 | category = CATEGORY 23 | description = DESCRIPTION 24 | subcheck-description = "Verify the reset pin has the ResetPin property attached", 25 | pass-message = "Reset pin %_ has the correct reset-pin type property attached" % [ref(p)], 26 | fail-message = "Reset pin %_ does not have the correct reset-pin type property attached" % [ref(p)], 27 | locators = [p] 28 | ) 29 | ; Improve this to check togglability 30 | #CHECK( 31 | condition = connected?(p), 32 | name = NAME 33 | category = CATEGORY 34 | description = DESCRIPTION 35 | subcheck-description = "Verify the reset pin is connected", 36 | pass-message = "Reset pin %_ is connected" % [ref(p)], 37 | fail-message = "Reset pin %_ is not connected" % [ref(p)], 38 | locators = [p] 39 | ) 40 | -------------------------------------------------------------------------------- /utils/pin-checks/utils.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/utils/pin-checks/utils : 2 | import core 3 | import collections 4 | import jitx 5 | import jitx/commands 6 | 7 | public val CATEGORY = "Component Checks" 8 | 9 | public defn context (p:JITXObject) : 10 | "%_" % [ 11 | ref(p) 12 | ] 13 | 14 | -------------------------------------------------------------------------------- /utils/propagation.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/utils/propagation : 2 | import core 3 | 4 | public var PROPAGATION-FINISHED : True|False = false 5 | -------------------------------------------------------------------------------- /utils/symbol-utils.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/utils/symbol-utils : 2 | forward jitx/parts/legacy-ocdb-symbols 3 | -------------------------------------------------------------------------------- /utils/symbols.stanza: -------------------------------------------------------------------------------- 1 | defpackage ocdb/utils/symbols : 2 | forward jitx/parts/legacy-ocdb-symbols 3 | --------------------------------------------------------------------------------