├── docs ├── docs │ ├── peripheral.md │ ├── reference.md │ ├── soc.en.md │ ├── peripheral.en.md │ ├── reference.en.md │ ├── soc.md │ ├── documents │ │ ├── vcd.pdf │ │ ├── core.pdf │ │ ├── risco5_datapath.pdf │ │ ├── uart_state_machine.pdf │ │ └── risco5_state_machine.pdf │ ├── imgs │ │ ├── risco5.jpeg │ │ ├── esquematico.png │ │ ├── risco5_datapath.jpg │ │ ├── risco5_datapath.png │ │ ├── uart_state_machine.png │ │ └── risco5_state_machine.png │ ├── index.en.md │ ├── index.md │ ├── about.en.md │ ├── about.md │ ├── contributing.en.md │ ├── contributing.md │ ├── get_started.en.md │ ├── get_started.md │ ├── core.en.md │ └── core.md ├── requirements.txt ├── mkdocs.yml └── README.md ├── software ├── memory │ ├── auipc.hex │ ├── csrr.hex │ ├── lui.hex │ ├── csrrwi.hex │ ├── addi.hex │ ├── andi.hex │ ├── div.hex │ ├── lb.hex │ ├── mul.hex │ ├── ori.hex │ ├── rem.hex │ ├── rem2.hex │ ├── csrrw.hex │ ├── fpga_test.hex │ ├── teste_gpio.hex │ ├── csrrci.hex │ ├── csrrsi.hex │ ├── jal.hex │ ├── sb.hex │ ├── sh.hex │ ├── slli.hex │ ├── slt.hex │ ├── slti.hex │ ├── srli.hex │ ├── add.hex │ ├── lh.hex │ ├── lw2.hex │ ├── sll.hex │ ├── srl.hex │ ├── sub.hex │ ├── and.hex │ ├── beq3.hex │ ├── beq4.hex │ ├── bge.hex │ ├── bge2.hex │ ├── bgeu.hex │ ├── bgeu2.hex │ ├── blt.hex │ ├── blt2.hex │ ├── bltu.hex │ ├── bltu2.hex │ ├── bne.hex │ ├── bne2.hex │ ├── csrrc.hex │ ├── csrrs.hex │ ├── jalr2.hex │ ├── loop.hex │ ├── or.hex │ ├── sw.hex │ ├── xor.hex │ ├── xori.hex │ ├── la.hex │ ├── jalr.hex │ ├── teste_uart_fpga.hex │ ├── lw.hex │ ├── sra.hex │ ├── forloop.hex │ ├── unaligned_sw.hex │ ├── loop2.hex │ ├── srai.hex │ ├── function.hex │ ├── teste_pwm.hex │ ├── teste_pwm2.hex │ ├── loop3.hex │ ├── sltiu.hex │ ├── sltu.hex │ ├── teste_led.hex │ ├── beq.hex │ ├── beq2.hex │ ├── teste_uart_tx.hex │ ├── loop_2.hex │ ├── teste_gpio_fpga.hex │ ├── fpga_test_2.hex │ ├── unaligned_lw.hex │ ├── teste_gpio_fpga2.hex │ ├── fpga_test_4.hex │ ├── fpga_test_3.hex │ ├── fibonacci.hex │ └── program.hex ├── code │ ├── auipc.S │ ├── csrr.S │ ├── lui.S │ ├── csrrwi.S │ ├── div.S │ ├── mul.s │ ├── rem.S │ ├── rem2.S │ ├── csrrw.S │ ├── teste_lw.S │ ├── andi.S │ ├── ori.S │ ├── teste_gpio.S │ ├── csrrci.S │ ├── csrrsi.S │ ├── lb.S │ ├── jal.S │ ├── csrrc.S │ ├── csrrs.S │ ├── la.S │ ├── or.S │ ├── xori.S │ ├── and.S │ ├── sb.S │ ├── sh.S │ ├── xor.S │ ├── lh.S │ ├── bge.S │ ├── blt.S │ ├── bne.S │ ├── lw2.S │ ├── slli.S │ ├── slt.S │ ├── slti.S │ ├── srli.S │ ├── beq3.S │ ├── beq4.S │ ├── bge2.S │ ├── bgeu.S │ ├── bgeu2.S │ ├── blt2.S │ ├── bltu.S │ ├── bltu2.S │ ├── bne2.S │ ├── jalr2.S │ ├── addi.S │ ├── unaligned_sw.S │ ├── loop.S │ ├── teste_uart_fpga.S │ ├── sll.S │ ├── srl.S │ ├── jalr.S │ ├── teste_pwm.S │ ├── teste_pwm2.S │ ├── sub.S │ ├── add.S │ ├── sw.S │ ├── fpga_test.S │ ├── loop2.S │ ├── sra.S │ ├── function.S │ ├── srai.S │ ├── lw.S │ ├── loop3.S │ ├── forloop.S │ ├── beq.S │ ├── beq2.S │ ├── sltu.S │ ├── memory_vector.s │ ├── sltiu.S │ ├── teste_led.S │ ├── loop_2.S │ ├── teste_uart_tx.S │ ├── unaligned_lw.S │ ├── fpga_test_2.S │ ├── fibonacci.S │ ├── teste_gpio_fpga.S │ ├── teste_gpio_fpga2.S │ ├── fpga_test_4.S │ └── fpga_test_3.S ├── firmware │ ├── lib │ │ ├── conversion.h │ │ ├── uart.h │ │ ├── risco5.h │ │ └── gpio.h │ ├── src │ │ ├── pwm.c │ │ ├── gpio.s │ │ └── conversion.s │ ├── utils │ │ └── link.ld │ ├── compile.sh │ ├── main.c │ └── Makefile ├── generate_mem.sh ├── compile_all.sh └── LICENSE ├── fpga ├── cyclone10gx │ ├── .gitignore │ ├── pinout.sdc │ ├── main.v │ ├── makefile │ ├── create_project.tcl │ ├── cyclone10_gx.qpf │ └── cyclone10_gx.qsf ├── tangnano20k │ ├── top.sdc │ ├── Makefile │ ├── pinout.cst │ ├── main.v │ ├── run.tcl │ ├── tangnano20k.gprj │ └── tangnano20k.gprj.user ├── de1soc │ ├── .gitignore │ ├── makefile │ ├── pinout.sdc │ ├── main.v │ ├── de1soc.qpf │ └── create_project.tcl ├── digilent_arty │ ├── .gitignore │ ├── Makefile │ ├── main.v │ ├── run.tcl │ └── program.hex ├── nexys4_ddr │ ├── .gitignore │ ├── Makefile │ ├── main.v │ └── run.tcl ├── xilinx_vc709 │ ├── .gitignore │ ├── flash.tcl │ ├── Makefile │ ├── main.v │ └── run.tcl ├── colorlight_i9 │ ├── main.v │ ├── Makefile │ └── pinout.lpf └── tangnano20k_yosys │ ├── main.v │ ├── pinout.cst │ └── Makefile ├── src ├── peripheral │ ├── config.vh │ ├── gpio.v │ ├── leds.v │ ├── pwm.v │ ├── fifo.v │ ├── memory.v │ ├── gpios.v │ └── bus.v └── core │ ├── config.vh │ ├── pc.v │ ├── mux.v │ ├── immediate_generator.v │ ├── alu_control.v │ ├── alu.v │ └── registers.v ├── tests ├── fifo_test.v ├── immediate_generator_test.v ├── reset_test.v ├── mux_test.v ├── soc_test.v ├── clk_divider.v ├── gpio_test.v ├── registers_test.v ├── core_test.v ├── pc_test.v └── alu_test.v ├── .gitattributes ├── run_test.sh ├── .github ├── FUNDING.yml └── workflows │ └── static.yml ├── debug ├── debug.v ├── reset.v └── clk_divider.v ├── LICENSE-MIT ├── .gitignore ├── CONTRIBUTING.md ├── README_pt.md └── README.md /docs/docs/peripheral.md: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /docs/docs/reference.md: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /docs/docs/soc.en.md: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /docs/docs/peripheral.en.md: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /docs/docs/reference.en.md: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /software/memory/auipc.hex: -------------------------------------------------------------------------------- 1 | 12345097 2 | -------------------------------------------------------------------------------- /software/memory/csrr.hex: -------------------------------------------------------------------------------- 1 | f12025f3 2 | -------------------------------------------------------------------------------- /software/memory/lui.hex: -------------------------------------------------------------------------------- 1 | 123450b7 2 | -------------------------------------------------------------------------------- /docs/docs/soc.md: -------------------------------------------------------------------------------- 1 | # Risco-5 Processor SoC -------------------------------------------------------------------------------- /software/memory/csrrwi.hex: -------------------------------------------------------------------------------- 1 | 3422d5f3 2 | 34202673 3 | -------------------------------------------------------------------------------- /software/memory/addi.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 00c586b3 4 | -------------------------------------------------------------------------------- /software/memory/andi.hex: -------------------------------------------------------------------------------- 1 | 00500513 2 | 00557493 3 | 00357413 4 | -------------------------------------------------------------------------------- /software/memory/div.hex: -------------------------------------------------------------------------------- 1 | 01400513 2 | 00a00593 3 | 02b54633 4 | -------------------------------------------------------------------------------- /software/memory/lb.hex: -------------------------------------------------------------------------------- 1 | 7ff00593 2 | 02b02423 3 | 02800603 4 | -------------------------------------------------------------------------------- /software/memory/mul.hex: -------------------------------------------------------------------------------- 1 | 00a00513 2 | 01400593 3 | 02b50633 4 | -------------------------------------------------------------------------------- /software/memory/ori.hex: -------------------------------------------------------------------------------- 1 | 00500513 2 | 00556493 3 | 00356413 4 | -------------------------------------------------------------------------------- /software/memory/rem.hex: -------------------------------------------------------------------------------- 1 | 00500513 2 | 00200593 3 | 02b56633 4 | -------------------------------------------------------------------------------- /software/memory/rem2.hex: -------------------------------------------------------------------------------- 1 | 00400513 2 | 00200593 3 | 02b56633 4 | -------------------------------------------------------------------------------- /software/memory/csrrw.hex: -------------------------------------------------------------------------------- 1 | 00500513 2 | 342515f3 3 | 34202673 4 | -------------------------------------------------------------------------------- /software/memory/fpga_test.hex: -------------------------------------------------------------------------------- 1 | 7ff00113 2 | 00f11113 3 | 00900793 4 | -------------------------------------------------------------------------------- /fpga/cyclone10gx/.gitignore: -------------------------------------------------------------------------------- 1 | dni/ 2 | build/ 3 | qdb/ 4 | tmp-clearbox/ -------------------------------------------------------------------------------- /software/memory/teste_gpio.hex: -------------------------------------------------------------------------------- 1 | c0000537 2 | 01f00593 3 | 00b52023 4 | -------------------------------------------------------------------------------- /software/memory/csrrci.hex: -------------------------------------------------------------------------------- 1 | 3422f5f3 2 | 34202673 3 | 3421f5f3 4 | 34202773 5 | -------------------------------------------------------------------------------- /software/memory/csrrsi.hex: -------------------------------------------------------------------------------- 1 | 3422e5f3 2 | 34202673 3 | 3421e5f3 4 | 34202773 5 | -------------------------------------------------------------------------------- /software/memory/jal.hex: -------------------------------------------------------------------------------- 1 | 00300693 2 | 008000ef 3 | 00500713 4 | 00a00793 5 | -------------------------------------------------------------------------------- /software/memory/sb.hex: -------------------------------------------------------------------------------- 1 | 7ff00593 2 | 00b585b3 3 | 02b00823 4 | 03002603 5 | -------------------------------------------------------------------------------- /software/memory/sh.hex: -------------------------------------------------------------------------------- 1 | 7ff00593 2 | 00659593 3 | 02b01823 4 | 03002603 5 | -------------------------------------------------------------------------------- /software/memory/slli.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 00159713 4 | 00161793 5 | -------------------------------------------------------------------------------- /software/memory/slt.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 00c5a6b3 4 | 00b62733 5 | -------------------------------------------------------------------------------- /software/memory/slti.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 0055a693 4 | 01762713 5 | -------------------------------------------------------------------------------- /software/memory/srli.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 0015d693 4 | 00165713 5 | -------------------------------------------------------------------------------- /fpga/tangnano20k/top.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk -period 37.037 [get_ports {clk}] -------------------------------------------------------------------------------- /software/code/auipc.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | auipc x1, 0x12345 5 | -------------------------------------------------------------------------------- /software/code/csrr.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | csrr a1, marchid; 5 | -------------------------------------------------------------------------------- /software/code/lui.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | lui x1, 0x12345 5 | -------------------------------------------------------------------------------- /software/memory/add.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 00c586b3 4 | 00c68733 5 | 00b707b3 6 | -------------------------------------------------------------------------------- /software/memory/lh.hex: -------------------------------------------------------------------------------- 1 | 7ff00593 2 | 00b585b3 3 | 00559593 4 | 02b02423 5 | 02801603 6 | -------------------------------------------------------------------------------- /software/memory/lw2.hex: -------------------------------------------------------------------------------- 1 | 7ff00593 2 | 00b585b3 3 | 00559593 4 | 02b02423 5 | 02802603 6 | -------------------------------------------------------------------------------- /software/memory/sll.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 00100693 4 | 00d59733 5 | 00d617b3 6 | -------------------------------------------------------------------------------- /software/memory/srl.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 00100793 4 | 00f5d6b3 5 | 00f65733 6 | -------------------------------------------------------------------------------- /software/memory/sub.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 40b606b3 4 | 40c68733 5 | 40b707b3 6 | -------------------------------------------------------------------------------- /fpga/de1soc/.gitignore: -------------------------------------------------------------------------------- 1 | dni/ 2 | build/ 3 | qdb/ 4 | tmp-clearbox/ 5 | db/ 6 | incremental_db/ -------------------------------------------------------------------------------- /docs/docs/documents/vcd.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JN513/Risco-5/HEAD/docs/docs/documents/vcd.pdf -------------------------------------------------------------------------------- /docs/docs/imgs/risco5.jpeg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JN513/Risco-5/HEAD/docs/docs/imgs/risco5.jpeg -------------------------------------------------------------------------------- /software/memory/and.hex: -------------------------------------------------------------------------------- 1 | 00500513 2 | 00300593 3 | 00b50633 4 | 00a574b3 5 | 00b57433 6 | 00b676b3 7 | -------------------------------------------------------------------------------- /software/memory/beq3.hex: -------------------------------------------------------------------------------- 1 | 00100093 2 | 00200113 3 | 00108463 4 | 00a00193 5 | 00f00213 6 | 00220233 7 | -------------------------------------------------------------------------------- /software/memory/beq4.hex: -------------------------------------------------------------------------------- 1 | 00100093 2 | 00200113 3 | 00208463 4 | 00a00193 5 | 00f00213 6 | 00220233 7 | -------------------------------------------------------------------------------- /software/memory/bge.hex: -------------------------------------------------------------------------------- 1 | 00100093 2 | 00200113 3 | 0020d463 4 | 00a00193 5 | 00f00213 6 | 00220233 7 | -------------------------------------------------------------------------------- /software/memory/bge2.hex: -------------------------------------------------------------------------------- 1 | 00100093 2 | 00200113 3 | 00115463 4 | 00a00193 5 | 00f00213 6 | 00220233 7 | -------------------------------------------------------------------------------- /software/memory/bgeu.hex: -------------------------------------------------------------------------------- 1 | 00100093 2 | 00200113 3 | 0020f463 4 | 00a00193 5 | 00f00213 6 | 00220233 7 | -------------------------------------------------------------------------------- /software/memory/bgeu2.hex: -------------------------------------------------------------------------------- 1 | 00100093 2 | 00200113 3 | 00117463 4 | 00a00193 5 | 00f00213 6 | 00220233 7 | -------------------------------------------------------------------------------- /software/memory/blt.hex: -------------------------------------------------------------------------------- 1 | 00100093 2 | 00200113 3 | 0020c463 4 | 00a00193 5 | 00f00213 6 | 00220233 7 | -------------------------------------------------------------------------------- /software/memory/blt2.hex: -------------------------------------------------------------------------------- 1 | 00100093 2 | 00200113 3 | 00114463 4 | 00a00193 5 | 00f00213 6 | 00220233 7 | -------------------------------------------------------------------------------- /software/memory/bltu.hex: -------------------------------------------------------------------------------- 1 | 00100093 2 | 00200113 3 | 0020e463 4 | 00a00193 5 | 00f00213 6 | 00220233 7 | -------------------------------------------------------------------------------- /software/memory/bltu2.hex: -------------------------------------------------------------------------------- 1 | 00100093 2 | 00200113 3 | 00116463 4 | 00a00193 5 | 00f00213 6 | 00220233 7 | -------------------------------------------------------------------------------- /software/memory/bne.hex: -------------------------------------------------------------------------------- 1 | 00100093 2 | 00200113 3 | 00111463 4 | 00a00193 5 | 00f00213 6 | 00220233 7 | -------------------------------------------------------------------------------- /software/memory/bne2.hex: -------------------------------------------------------------------------------- 1 | 00100093 2 | 00200113 3 | 00109463 4 | 00a00193 5 | 00f00213 6 | 00220233 7 | -------------------------------------------------------------------------------- /software/memory/csrrc.hex: -------------------------------------------------------------------------------- 1 | 00500513 2 | 00300693 3 | 342535f3 4 | 34202673 5 | 3426b5f3 6 | 34202773 7 | -------------------------------------------------------------------------------- /software/memory/csrrs.hex: -------------------------------------------------------------------------------- 1 | 00500513 2 | 00300693 3 | 342525f3 4 | 34202673 5 | 3426a5f3 6 | 34202773 7 | -------------------------------------------------------------------------------- /software/memory/jalr2.hex: -------------------------------------------------------------------------------- 1 | 00300693 2 | 00d686b3 3 | 008000ef 4 | 00700713 5 | 00a00793 6 | 00008067 7 | -------------------------------------------------------------------------------- /software/memory/loop.hex: -------------------------------------------------------------------------------- 1 | 00a00113 2 | 00000263 3 | 00178793 4 | 00278463 5 | fef78ce3 6 | 00500193 7 | -------------------------------------------------------------------------------- /software/memory/or.hex: -------------------------------------------------------------------------------- 1 | 00500513 2 | 00300593 3 | 00b50633 4 | 00a564b3 5 | 00b56433 6 | 00b666b3 7 | -------------------------------------------------------------------------------- /software/memory/sw.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 00c586b3 4 | 02d02423 5 | 02c02623 6 | 02b02823 7 | -------------------------------------------------------------------------------- /software/memory/xor.hex: -------------------------------------------------------------------------------- 1 | 00500513 2 | 00300593 3 | 00b50633 4 | 00a544b3 5 | 00b54433 6 | 00b646b3 7 | -------------------------------------------------------------------------------- /software/memory/xori.hex: -------------------------------------------------------------------------------- 1 | 00500513 2 | 00300593 3 | 00b50633 4 | 00754493 5 | 00654413 6 | 00564693 7 | -------------------------------------------------------------------------------- /src/peripheral/config.vh: -------------------------------------------------------------------------------- 1 | `define UART_ENABLE 1 2 | //`define GPIO_ENABLE 1 3 | //`define LED_ENABLE 1 -------------------------------------------------------------------------------- /docs/docs/documents/core.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JN513/Risco-5/HEAD/docs/docs/documents/core.pdf -------------------------------------------------------------------------------- /docs/docs/imgs/esquematico.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JN513/Risco-5/HEAD/docs/docs/imgs/esquematico.png -------------------------------------------------------------------------------- /software/code/csrrwi.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | csrrwi a1, mcause, 5; 5 | csrr a2, mcause; 6 | -------------------------------------------------------------------------------- /software/memory/la.hex: -------------------------------------------------------------------------------- 1 | 00a00513 2 | 00000597 3 | 01058593 4 | 000580e7 5 | 00500693 6 | 00400613 7 | 00008067 8 | -------------------------------------------------------------------------------- /docs/docs/imgs/risco5_datapath.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JN513/Risco-5/HEAD/docs/docs/imgs/risco5_datapath.jpg -------------------------------------------------------------------------------- /docs/docs/imgs/risco5_datapath.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JN513/Risco-5/HEAD/docs/docs/imgs/risco5_datapath.png -------------------------------------------------------------------------------- /docs/docs/imgs/uart_state_machine.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JN513/Risco-5/HEAD/docs/docs/imgs/uart_state_machine.png -------------------------------------------------------------------------------- /software/code/div.S: -------------------------------------------------------------------------------- 1 | .globl _start 2 | 3 | _start: 4 | li a0, 20; 5 | li a1, 10; 6 | 7 | div a2, a0, a1; 8 | -------------------------------------------------------------------------------- /software/code/mul.s: -------------------------------------------------------------------------------- 1 | .globl _start 2 | 3 | _start: 4 | li a0, 10; 5 | li a1, 20; 6 | 7 | mul a2, a0, a1; 8 | -------------------------------------------------------------------------------- /software/code/rem.S: -------------------------------------------------------------------------------- 1 | .globl _start 2 | 3 | _start: 4 | li a0, 5; 5 | li a1, 2; 6 | 7 | rem a2, a0, a1; 8 | -------------------------------------------------------------------------------- /software/code/rem2.S: -------------------------------------------------------------------------------- 1 | .globl _start 2 | 3 | _start: 4 | li a0, 4; 5 | li a1, 2; 6 | 7 | rem a2, a0, a1; 8 | -------------------------------------------------------------------------------- /src/core/config.vh: -------------------------------------------------------------------------------- 1 | `define MDU_ENABLE 1 2 | `define UNALIGNED_ENABLE 1 3 | `define CSR_ENABLE 1 4 | //`define RV32E 1 5 | -------------------------------------------------------------------------------- /docs/docs/documents/risco5_datapath.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JN513/Risco-5/HEAD/docs/docs/documents/risco5_datapath.pdf -------------------------------------------------------------------------------- /docs/docs/imgs/risco5_state_machine.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JN513/Risco-5/HEAD/docs/docs/imgs/risco5_state_machine.png -------------------------------------------------------------------------------- /software/memory/jalr.hex: -------------------------------------------------------------------------------- 1 | 00300693 2 | 00d686b3 3 | 00000097 4 | 01008093 5 | 00008667 6 | 00700713 7 | 00a00793 8 | 00008067 9 | -------------------------------------------------------------------------------- /software/memory/teste_uart_fpga.hex: -------------------------------------------------------------------------------- 1 | 80000437 2 | 00442283 3 | 00028463 4 | ff9ff06f 5 | 00042283 6 | 00542023 7 | fedff06f 8 | -------------------------------------------------------------------------------- /docs/docs/documents/uart_state_machine.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JN513/Risco-5/HEAD/docs/docs/documents/uart_state_machine.pdf -------------------------------------------------------------------------------- /software/code/csrrw.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | li a0, 5; 5 | csrrw a1, mcause, a0; 6 | csrr a2, mcause; 7 | -------------------------------------------------------------------------------- /docs/docs/documents/risco5_state_machine.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JN513/Risco-5/HEAD/docs/docs/documents/risco5_state_machine.pdf -------------------------------------------------------------------------------- /software/code/teste_lw.S: -------------------------------------------------------------------------------- 1 | .text 2 | 3 | .global _start 4 | 5 | _start: 6 | lw a0, var 7 | 8 | .data 9 | var: .word 50; 10 | -------------------------------------------------------------------------------- /software/code/andi.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x10, zero, 5; 5 | 6 | andi x9, x10, 5; 7 | andi x8, x10, 3; 8 | -------------------------------------------------------------------------------- /software/code/ori.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x10, zero, 5; 5 | 6 | ori x9, x10, 5; 7 | ori x8, x10, 3; 8 | -------------------------------------------------------------------------------- /software/code/teste_gpio.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | li a0, 0xC0000000 5 | li a1, 0x0000001F 6 | 7 | sw a1, 0(a0) 8 | -------------------------------------------------------------------------------- /fpga/digilent_arty/.gitignore: -------------------------------------------------------------------------------- 1 | digilent_arty.cache/ 2 | digilent_arty.hw/ 3 | digilent_arty.ip_user_files/ 4 | .Xil/ 5 | report/ 6 | vivado_*.backup.* -------------------------------------------------------------------------------- /fpga/nexys4_ddr/.gitignore: -------------------------------------------------------------------------------- 1 | digilent_arty.cache/ 2 | digilent_arty.hw/ 3 | digilent_arty.ip_user_files/ 4 | .Xil/ 5 | report/ 6 | vivado_*.backup.* -------------------------------------------------------------------------------- /software/memory/lw.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 00c586b3 4 | 02d02423 5 | 02c02623 6 | 02b02823 7 | 02802583 8 | 02c02683 9 | 03002603 10 | -------------------------------------------------------------------------------- /software/memory/sra.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 00100793 4 | 40f5d6b3 5 | 40f65733 6 | ffe00813 7 | 40f858b3 8 | c1800813 9 | 40f852b3 10 | -------------------------------------------------------------------------------- /software/memory/forloop.hex: -------------------------------------------------------------------------------- 1 | 004000ef 2 | 00000293 3 | 00000313 4 | 06400393 5 | 0072d863 6 | 00530333 7 | 00128293 8 | ff5ff06f 9 | 00008067 10 | -------------------------------------------------------------------------------- /software/memory/unaligned_sw.hex: -------------------------------------------------------------------------------- 1 | 88888537 2 | fff50513 3 | fff00593 4 | 88889637 5 | 88860613 6 | 06b02223 7 | 06b02423 8 | 06c023a3 9 | 00500693 10 | -------------------------------------------------------------------------------- /software/code/csrrci.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | csrrc a1, mcause, 5; 5 | csrr a2, mcause; 6 | csrrc a1, mcause, 3; 7 | csrr a4, mcause; 8 | -------------------------------------------------------------------------------- /software/code/csrrsi.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | csrrsi a1, mcause, 5; 5 | csrr a2, mcause; 6 | csrrsi a1, mcause, 3; 7 | csrr a4, mcause; 8 | -------------------------------------------------------------------------------- /software/memory/loop2.hex: -------------------------------------------------------------------------------- 1 | 01400093 2 | 00a00113 3 | 000001b3 4 | 00118193 5 | 00208863 6 | 00208093 7 | 00310113 8 | ff1ff06f 9 | 00500213 10 | 00008067 11 | -------------------------------------------------------------------------------- /software/memory/srai.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 00c58833 4 | 4015d693 5 | 40165713 6 | 00500793 7 | ffe00813 8 | 40185893 9 | ffc00813 10 | 40185293 11 | -------------------------------------------------------------------------------- /software/memory/function.hex: -------------------------------------------------------------------------------- 1 | 00c000ef 2 | 00a50533 3 | 00008067 4 | 00100513 5 | ff5ff0ef 6 | 00a00513 7 | fedff0ef 8 | 00500513 9 | fe5ff0ef 10 | 00008067 11 | -------------------------------------------------------------------------------- /software/code/lb.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 2047 # Carrega o primeiro número (2047) em a1 5 | 6 | sw a1, 40(zero) 7 | lb a2, 40(zero) 8 | -------------------------------------------------------------------------------- /software/memory/teste_pwm.hex: -------------------------------------------------------------------------------- 1 | c0000537 2 | 00000593 3 | 00b52023 4 | 00f00593 5 | 00b52423 6 | 000065b7 7 | 1a858593 8 | 00b52623 9 | 000035b7 10 | ee058593 11 | 00b52823 12 | -------------------------------------------------------------------------------- /software/memory/teste_pwm2.hex: -------------------------------------------------------------------------------- 1 | c0000537 2 | 00000593 3 | 00b52023 4 | 00000593 5 | 00b52423 6 | 000065b7 7 | 1a858593 8 | 00b52623 9 | 000035b7 10 | ee058593 11 | 00b52823 12 | -------------------------------------------------------------------------------- /tests/fifo_test.v: -------------------------------------------------------------------------------- 1 | module fifo_tb (); 2 | 3 | reg clk, reset; 4 | 5 | initial begin 6 | clk = 1'b0; 7 | reset = 1'b0; 8 | end 9 | 10 | always #1 clk = ~clk; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /software/code/jal.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a3, zero, 3; 5 | 6 | jal subrotina 7 | 8 | addi a4, zero, 5; 9 | 10 | 11 | subrotina: 12 | addi a5, zero, 10; 13 | -------------------------------------------------------------------------------- /software/memory/loop3.hex: -------------------------------------------------------------------------------- 1 | 03f00293 2 | 7ff00713 3 | 00e70733 4 | 00270713 5 | 0040006f 6 | 000001b3 7 | 0040006f 8 | 00118193 9 | 00372023 10 | 00518463 11 | ff5ff06f 12 | 00500213 13 | fe5ff06f 14 | -------------------------------------------------------------------------------- /software/memory/sltiu.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 00f5b693 4 | 00a63713 5 | fff00793 6 | 00001837 7 | dff80813 8 | 00000513 9 | 0007b893 10 | 80083293 11 | 00053313 12 | 0007b393 13 | 80053e13 14 | -------------------------------------------------------------------------------- /software/memory/sltu.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 00c5b6b3 4 | 00b63733 5 | fff00793 6 | e0000837 7 | fff80813 8 | 00000513 9 | 0107b8b3 10 | 00f832b3 11 | 00a53333 12 | 00a7b3b3 13 | 00f53e33 14 | -------------------------------------------------------------------------------- /software/code/csrrc.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | li a0, 5; 5 | li a3, 3; 6 | csrrc a1, mcause, a0; 7 | csrr a2, mcause; 8 | csrrc a1, mcause, a3; 9 | csrr a4, mcause; 10 | -------------------------------------------------------------------------------- /software/code/csrrs.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | li a0, 5; 5 | li a3, 3; 6 | csrrs a1, mcause, a0; 7 | csrr a2, mcause; 8 | csrrs a1, mcause, a3; 9 | csrr a4, mcause; 10 | -------------------------------------------------------------------------------- /software/firmware/lib/conversion.h: -------------------------------------------------------------------------------- 1 | #ifndef __CONVERSION_H__ 2 | #define __CONVERSION_H__ 3 | 4 | int atoi (const char *str); 5 | char *itoa ( int value, char *str, int base ); 6 | 7 | #endif // !__CONVERSION_H__ -------------------------------------------------------------------------------- /software/code/la.S: -------------------------------------------------------------------------------- 1 | .text 2 | .global _start; 3 | 4 | _start: 5 | li a0, 10; 6 | la a1, desvio; 7 | 8 | jalr ra, a1, 0; 9 | 10 | li a3, 5; 11 | 12 | desvio: 13 | li a2, 4; 14 | ret; 15 | -------------------------------------------------------------------------------- /software/memory/teste_led.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 00c586b3 4 | 40000737 5 | 04d02223 6 | 04c02423 7 | 04b02623 8 | 00d72023 9 | 04402583 10 | 04802683 11 | 04c02603 12 | 04402783 13 | 04802803 14 | 04c02883 15 | -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | *.v linguist-language=verilog 2 | *.S linguist-language=assembly 3 | *.s lingujson-language=assembly 4 | *.sv linguist-language=systemverilog 5 | *.svh linguist-language=systemverilog 6 | *.md linguist-language=markdown -------------------------------------------------------------------------------- /software/code/or.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x10, zero, 5; 5 | addi x11, zero, 3; 6 | add x12, x10, x11; 7 | 8 | or x9, x10, x10; 9 | or x8, x10, x11; 10 | or x13, x12, x11; 11 | -------------------------------------------------------------------------------- /software/code/xori.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x10, zero, 5; 5 | addi x11, zero, 3; 6 | add x12, x10, x11; 7 | 8 | xori x9, x10, 7; 9 | xori x8, x10, 6; 10 | xori x13, x12, 5; 11 | -------------------------------------------------------------------------------- /software/firmware/src/pwm.c: -------------------------------------------------------------------------------- 1 | #include "../lib/gpio.h" 2 | 3 | int get_pwm_period(int freq) { 4 | return CLK_FREQ / freq; 5 | } 6 | 7 | int get_pwm_duty_cycle(int period, int duty) { 8 | return period * duty / 65536; 9 | } -------------------------------------------------------------------------------- /tests/immediate_generator_test.v: -------------------------------------------------------------------------------- 1 | module immediate_generator_tb (); 2 | 3 | reg clk, reset; 4 | 5 | initial begin 6 | clk = 1'b0; 7 | reset = 1'b0; 8 | end 9 | 10 | always #1 clk = ~clk; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /software/code/and.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x10, zero, 5; 5 | addi x11, zero, 3; 6 | add x12, x10, x11; 7 | 8 | and x9, x10, x10; 9 | and x8, x10, x11; 10 | and x13, x12, x11; 11 | -------------------------------------------------------------------------------- /software/code/sb.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 2047 # Carrega o primeiro número (2047) em a1 5 | 6 | add a1, a1, a1 7 | 8 | sb a1, 48(zero) 9 | 10 | lw a2, 48(zero) 11 | 12 | -------------------------------------------------------------------------------- /software/code/sh.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 2047 # Carrega o primeiro número (2047) em a1 5 | 6 | slli a1, a1, 6 7 | 8 | sh a1, 48(zero) 9 | 10 | lw a2, 48(zero) 11 | 12 | -------------------------------------------------------------------------------- /software/code/xor.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x10, zero, 5; 5 | addi x11, zero, 3; 6 | add x12, x10, x11; 7 | 8 | xor x9, x10, x10; 9 | xor x8, x10, x11; 10 | xor x13, x12, x11; 11 | -------------------------------------------------------------------------------- /software/memory/beq.hex: -------------------------------------------------------------------------------- 1 | 00100613 2 | 00100493 3 | 02960663 4 | 00500693 5 | 00d60733 6 | 00e62023 7 | 00062703 8 | 40c685b3 9 | 01900513 10 | ff150513 11 | 00d677b3 12 | 00d667b3 13 | 06400513 14 | 01100813 15 | 01187813 16 | -------------------------------------------------------------------------------- /software/memory/beq2.hex: -------------------------------------------------------------------------------- 1 | 00100613 2 | 00200493 3 | 02960663 4 | 00500693 5 | 00d60733 6 | 00e62023 7 | 00062703 8 | 40c685b3 9 | 01900513 10 | ff150513 11 | 00d677b3 12 | 00d667b3 13 | 06400513 14 | 01100813 15 | 01187813 16 | -------------------------------------------------------------------------------- /software/code/lh.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 2047 # Carrega o primeiro número (2047) em a1 5 | add a1, a1, a1 6 | 7 | slli a1, a1, 5 8 | 9 | sw a1, 40(zero) 10 | lh a2, 40(zero) 11 | -------------------------------------------------------------------------------- /software/code/bge.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x1, zero, 1 5 | addi x2, zero, 2 6 | 7 | bge x1, x2, desvio 8 | 9 | addi x3, zero, 10 10 | 11 | desvio: 12 | addi x4, zero, 15 13 | add x4, x4, x2 14 | -------------------------------------------------------------------------------- /software/code/blt.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x1, zero, 1 5 | addi x2, zero, 2 6 | 7 | blt x1, x2, desvio 8 | 9 | addi x3, zero, 10 10 | 11 | desvio: 12 | addi x4, zero, 15 13 | add x4, x4, x2 14 | -------------------------------------------------------------------------------- /software/code/bne.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x1, zero, 1 5 | addi x2, zero, 2 6 | 7 | bne x2, x1, desvio 8 | 9 | addi x3, zero, 10 10 | 11 | desvio: 12 | addi x4, zero, 15 13 | add x4, x4, x2 14 | -------------------------------------------------------------------------------- /software/code/lw2.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 2047 # Carrega o primeiro número (2047) em a1 5 | add a1, a1, a1 6 | 7 | slli a1, a1, 5 8 | 9 | sw a1, 40(zero) 10 | lw a2, 40(zero) 11 | -------------------------------------------------------------------------------- /software/code/slli.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | 7 | slli a4, a1, 1 8 | slli a5, a2, 1 9 | -------------------------------------------------------------------------------- /software/code/slt.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | 7 | slt a3, a1, a2 8 | slt a4, a2, a1 9 | -------------------------------------------------------------------------------- /software/code/slti.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | 7 | slti a3, a1, 5 8 | slti a4, a2, 23 9 | -------------------------------------------------------------------------------- /software/code/srli.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | 7 | srli a3, a1, 1 8 | srli a4, a2, 1 9 | -------------------------------------------------------------------------------- /software/code/beq3.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x1, zero, 1 5 | addi x2, zero, 2 6 | 7 | beq x1, x1, desvio 8 | 9 | addi x3, zero, 10 10 | 11 | desvio: 12 | addi x4, zero, 15 13 | add x4, x4, x2 14 | -------------------------------------------------------------------------------- /software/code/beq4.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x1, zero, 1 5 | addi x2, zero, 2 6 | 7 | beq x1, x2, desvio 8 | 9 | addi x3, zero, 10 10 | 11 | desvio: 12 | addi x4, zero, 15 13 | add x4, x4, x2 14 | -------------------------------------------------------------------------------- /software/code/bge2.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x1, zero, 1 5 | addi x2, zero, 2 6 | 7 | bge x2, x1, desvio 8 | 9 | addi x3, zero, 10 10 | 11 | desvio: 12 | addi x4, zero, 15 13 | add x4, x4, x2 14 | -------------------------------------------------------------------------------- /software/code/bgeu.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x1, zero, 1 5 | addi x2, zero, 2 6 | 7 | bgeu x1, x2, desvio 8 | 9 | addi x3, zero, 10 10 | 11 | desvio: 12 | addi x4, zero, 15 13 | add x4, x4, x2 14 | -------------------------------------------------------------------------------- /software/code/bgeu2.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x1, zero, 1 5 | addi x2, zero, 2 6 | 7 | bgeu x2, x1, desvio 8 | 9 | addi x3, zero, 10 10 | 11 | desvio: 12 | addi x4, zero, 15 13 | add x4, x4, x2 14 | -------------------------------------------------------------------------------- /software/code/blt2.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x1, zero, 1 5 | addi x2, zero, 2 6 | 7 | blt x2, x1, desvio 8 | 9 | addi x3, zero, 10 10 | 11 | desvio: 12 | addi x4, zero, 15 13 | add x4, x4, x2 14 | -------------------------------------------------------------------------------- /software/code/bltu.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x1, zero, 1 5 | addi x2, zero, 2 6 | 7 | bltu x1, x2, desvio 8 | 9 | addi x3, zero, 10 10 | 11 | desvio: 12 | addi x4, zero, 15 13 | add x4, x4, x2 14 | -------------------------------------------------------------------------------- /software/code/bltu2.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x1, zero, 1 5 | addi x2, zero, 2 6 | 7 | bltu x2, x1, desvio 8 | 9 | addi x3, zero, 10 10 | 11 | desvio: 12 | addi x4, zero, 15 13 | add x4, x4, x2 14 | -------------------------------------------------------------------------------- /software/code/bne2.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x1, zero, 1 5 | addi x2, zero, 2 6 | 7 | bne x1, x1, desvio 8 | 9 | addi x3, zero, 10 10 | 11 | desvio: 12 | addi x4, zero, 15 13 | add x4, x4, x2 14 | -------------------------------------------------------------------------------- /software/memory/teste_uart_tx.hex: -------------------------------------------------------------------------------- 1 | 00a00593 2 | 01400613 3 | 00c586b3 4 | 80000737 5 | 04900313 6 | 04d02223 7 | 04c02423 8 | 04b02623 9 | 00672023 10 | 04402583 11 | 04802683 12 | 04c02603 13 | 04402783 14 | 04802803 15 | 04c02883 16 | 0000006f 17 | -------------------------------------------------------------------------------- /software/code/jalr2.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a3, zero, 3; 5 | add a3, a3, a3; 6 | 7 | jal ra, subrotina; 8 | 9 | addi a4, zero, 7; 10 | 11 | subrotina: 12 | addi a5, zero, 10; 13 | jalr zero, ra, 0; 14 | -------------------------------------------------------------------------------- /software/memory/loop_2.hex: -------------------------------------------------------------------------------- 1 | 7ff00113 2 | 0ff00213 3 | 7d000513 4 | 3e850513 5 | 04c00813 6 | 00f11113 7 | 00000263 8 | 000007b3 9 | 000001b3 10 | 00000263 11 | 00178793 12 | 7d052803 13 | fe4786e3 14 | 00000263 15 | 00118193 16 | fe2186e3 17 | fe000ce3 18 | -------------------------------------------------------------------------------- /fpga/xilinx_vc709/.gitignore: -------------------------------------------------------------------------------- 1 | digilent_arty.cache/ 2 | digilent_arty.hw/ 3 | digilent_arty.ip_user_files/ 4 | .Xil/ 5 | report/ 6 | vivado_*.backup.* 7 | virtex_* 8 | usage_statistics_webtalk.xml 9 | usage_statistics_webtalk.html 10 | tight_setup_hold_pins.txt 11 | -------------------------------------------------------------------------------- /software/code/addi.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | 7 | add a3, a1, a2 # Soma a1 e a2, armazena o resultado em a3 8 | -------------------------------------------------------------------------------- /software/code/unaligned_sw.S: -------------------------------------------------------------------------------- 1 | .text 2 | .global _start 3 | 4 | _start: 5 | li a0, 0x88887FFF 6 | li a1, 0xFFFFFFFF 7 | li a2, 0x88888888 8 | 9 | sw a1, 100(zero) 10 | sw a1, 104(zero) 11 | sw a2, 103(zero) 12 | 13 | li a3, 5 14 | -------------------------------------------------------------------------------- /software/code/loop.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x2, zero, 10; 5 | beq zero, zero, loop; 6 | 7 | loop: 8 | addi x15, x15, 1; 9 | 10 | beq x15, x2, end; 11 | 12 | beq x15, x15, loop; 13 | 14 | end: 15 | addi x3, zero, 5; 16 | -------------------------------------------------------------------------------- /software/code/teste_uart_fpga.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | li s0, 0x80000000; 5 | 6 | loop: 7 | lw t0, 4(s0); 8 | 9 | beqz t0, read; 10 | 11 | j loop; 12 | 13 | read: 14 | lw t0, 0(s0); 15 | sw t0, 0(s0); 16 | 17 | j loop; 18 | -------------------------------------------------------------------------------- /software/code/sll.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | addi a3, zero, 1 7 | 8 | sll a4, a1, a3 9 | sll a5, a2, a3 10 | -------------------------------------------------------------------------------- /software/code/srl.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | addi a5, zero, 1 7 | 8 | srl a3, a1, a5 9 | srl a4, a2, a5 10 | -------------------------------------------------------------------------------- /software/code/jalr.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a3, zero, 3; 5 | add a3, a3, a3; 6 | 7 | la x1, subrotina; 8 | 9 | jalr a2, x1, 0; 10 | 11 | addi a4, zero, 7; 12 | 13 | subrotina: 14 | addi a5, zero, 10; 15 | jalr zero, ra, 0; 16 | -------------------------------------------------------------------------------- /software/memory/teste_gpio_fpga.hex: -------------------------------------------------------------------------------- 1 | c0000437 2 | 800004b7 3 | 00000913 4 | 00100513 5 | 00200593 6 | 00400613 7 | 00800693 8 | 01000713 9 | 02000793 10 | 04000813 11 | 08000893 12 | 0f000293 13 | 00542023 14 | 00a96933 15 | 00b96933 16 | 00c96933 17 | 00d96933 18 | 01242223 19 | 01242223 20 | -------------------------------------------------------------------------------- /software/memory/fpga_test_2.hex: -------------------------------------------------------------------------------- 1 | 0ff00413 2 | 400004b7 3 | 002dc937 4 | 6c090913 5 | 00000293 6 | 00000313 7 | 00128293 8 | 0054a023 9 | 00c000ef 10 | 00828e63 11 | ff1ff06f 12 | 00000313 13 | 00130313 14 | 01230463 15 | ff9ff06f 16 | 00008067 17 | 00000293 18 | 0084a023 19 | fe5ff0ef 20 | fcdff06f 21 | -------------------------------------------------------------------------------- /fpga/tangnano20k/Makefile: -------------------------------------------------------------------------------- 1 | all: ./impl/pnr/project.fs 2 | 3 | ./impl/pnr/project.fs: buildFolder 4 | gw_sh run.tcl 5 | buildFolder: 6 | mkdir -p build 7 | 8 | clean: 9 | rm -rf build 10 | 11 | load: 12 | openFPGALoader -b tangnano20k ./impl/pnr/project.fs 13 | 14 | run_all: ./impl/pnr/project.fs load -------------------------------------------------------------------------------- /software/code/teste_pwm.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | li a0, 0xC0000000 5 | li a1, 0x00000000 6 | 7 | sw a1, 0(a0) 8 | 9 | li a1, 0x0000000F 10 | sw a1, 8(a0) 11 | 12 | li a1, 25000 13 | 14 | sw a1, 0xC(a0) 15 | 16 | li a1, 12000 17 | 18 | sw a1, 0x10(a0) 19 | -------------------------------------------------------------------------------- /software/code/teste_pwm2.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | li a0, 0xC0000000 5 | li a1, 0x00000000 6 | 7 | sw a1, 0(a0) 8 | 9 | li a1, 0x00000000 10 | sw a1, 8(a0) 11 | 12 | li a1, 25000 13 | 14 | sw a1, 0xC(a0) 15 | 16 | li a1, 12000 17 | 18 | sw a1, 0x10(a0) 19 | -------------------------------------------------------------------------------- /software/code/sub.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | 7 | sub a3, a2, a1 # Soma a1 e a2, armazena o resultado em a3 8 | sub a4, a3, a2 9 | sub a5, a4, a1 10 | -------------------------------------------------------------------------------- /software/code/add.S: -------------------------------------------------------------------------------- 1 | .text 2 | .global _start 3 | 4 | _start: 5 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 6 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 7 | 8 | add a3, a1, a2 # Soma a1 e a2, armazena o resultado em a3 9 | add a4, a3, a2 10 | add a5, a4, a1 11 | -------------------------------------------------------------------------------- /software/code/sw.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | 7 | add a3, a1, a2 # Soma a1 e a2, armazena o resultado em a3 8 | sw a3, 40(zero) 9 | sw a2, 44(zero) 10 | sw a1, 48(zero) 11 | 12 | -------------------------------------------------------------------------------- /software/code/fpga_test.S: -------------------------------------------------------------------------------- 1 | .text 2 | .global _start; 3 | 4 | _start: 5 | addi x2, zero, 2047; 6 | slli x2, x2, 15; 7 | 8 | addi x15, zero, 9; 9 | 10 | # beq x1, x1, loop; 11 | # 12 | #loop: 13 | # addi x15, zero, 1; 14 | # 15 | # beq x1, x1, time; 16 | # 17 | #time: 18 | # addi x3, zero, x1; 19 | # 20 | # blt x3, x3, time; 21 | -------------------------------------------------------------------------------- /fpga/de1soc/makefile: -------------------------------------------------------------------------------- 1 | ifndef QUARTUS_PATH 2 | QUARTUS_PATH="" 3 | endif 4 | 5 | all: 6 | $(QUARTUS_PATH)quartus_sh --flow compile de1soc 7 | 8 | load: 9 | $(QUARTUS_PATH)quartus_pgm -a -o "p;build/de1soc.sof" 10 | 11 | create_project: 12 | $(QUARTUS_PATH)quartus_sh -t create_project.tcl 13 | 14 | clean: 15 | rm -rf build/* 16 | 17 | run_all: all load -------------------------------------------------------------------------------- /software/memory/unaligned_lw.hex: -------------------------------------------------------------------------------- 1 | 88888537 2 | fff50513 3 | fff00593 4 | 88889637 5 | 88860613 6 | 06b02223 7 | 06c02423 8 | 06a02623 9 | 06502683 10 | 06602703 11 | 06702783 12 | 06501803 13 | 06601883 14 | 06701903 15 | 06500983 16 | 06600a03 17 | 06700a83 18 | 06505b03 19 | 06605b83 20 | 06705c03 21 | 06504c83 22 | 06604d03 23 | 06704d83 24 | 06c01e03 25 | 06d00e83 26 | -------------------------------------------------------------------------------- /software/code/loop2.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x1, zero, 20; 5 | addi x2, zero, 10; 6 | add x3, zero, zero; 7 | 8 | loop: 9 | addi x3, x3, 1; # x3 = x3 + 1 10 | 11 | beq x1, x2, fim; # if t0 == t1 then fim 12 | addi x1, x1, 2 13 | addi x2, x2, 3 14 | j loop 15 | 16 | fim: 17 | addi x4, zero, 5 18 | jr ra; 19 | -------------------------------------------------------------------------------- /software/code/sra.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | addi a5, zero, 1 7 | 8 | sra a3, a1, a5 9 | sra a4, a2, a5 10 | 11 | li a6, -2; 12 | 13 | sra a7, a6, a5 14 | 15 | li a6, -1000; 16 | sra t0, a6, a5 17 | -------------------------------------------------------------------------------- /fpga/xilinx_vc709/flash.tcl: -------------------------------------------------------------------------------- 1 | # Inicializar o hardware 2 | open_hw 3 | connect_hw_server 4 | 5 | #current_hw_target [get_hw_targets */210203A7C2EE*] 6 | 7 | open_hw_target 8 | 9 | # Programar a FPGA com o bitstream 10 | set_property PROGRAM.FILE ./build/out.bit [current_hw_device] 11 | program_hw_devices [current_hw_device] 12 | 13 | # Fechar conexões e projeto 14 | close_hw_target 15 | close_hw -------------------------------------------------------------------------------- /software/firmware/utils/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH("riscv") 2 | ENTRY(_start) 3 | 4 | MEMORY{ 5 | RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x08000 6 | } 7 | SECTIONS { 8 | . = 0x00000000; 9 | .text : { *(.text) } > RAM 10 | . = ALIGN (2); 11 | .data : { *(.data) } > RAM 12 | .bss : { *(.bss) } > RAM 13 | .heap : { *(.heap) } > RAM 14 | .stack : { *(.stack) } > RAM 15 | } -------------------------------------------------------------------------------- /software/code/function.S: -------------------------------------------------------------------------------- 1 | .text 2 | .global _start 3 | 4 | _start: 5 | jal main 6 | 7 | # Função que recebe um valor em a0 e retorna o dobro em a0 8 | # O nome da função é "dobro" 9 | dobro: 10 | add a0, a0, a0 11 | ret 12 | 13 | main: 14 | li a0, 1 15 | call dobro # a0 = 2 16 | li a0, 10 17 | call dobro # a0 = 20 18 | li a0, 5 19 | call dobro # a0 = 10 20 | ret 21 | -------------------------------------------------------------------------------- /software/code/srai.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | 7 | add a6, a1, a2 8 | 9 | srai a3, a1, 1 10 | srai a4, a2, 1 11 | 12 | addi a5, zero, 5 13 | 14 | li a6, -2 15 | 16 | srai a7, a6, 1 17 | li a6, -4 18 | 19 | srai t0, a6, 1 20 | -------------------------------------------------------------------------------- /software/memory/teste_gpio_fpga2.hex: -------------------------------------------------------------------------------- 1 | c0000437 2 | 800004b7 3 | 00000913 4 | 3e800a93 5 | 00100513 6 | 00200593 7 | 00400613 8 | 00800693 9 | 01000713 10 | 02000793 11 | 04000813 12 | 08000893 13 | 0f000293 14 | 00542023 15 | 00a96933 16 | 00b96933 17 | 00c96933 18 | 00d96933 19 | 01242223 20 | 00042303 21 | 00431313 22 | 00642223 23 | 008000ef 24 | ff1ff06f 25 | 00000393 26 | 00138393 27 | 01538463 28 | ff9ff06f 29 | 00008067 30 | -------------------------------------------------------------------------------- /software/code/lw.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | 7 | add a3, a1, a2 # Soma a1 e a2, armazena o resultado em a3 8 | 9 | sw a3, 40(zero) 10 | sw a2, 44(zero) 11 | sw a1, 48(zero) 12 | 13 | lw a1, 40(zero) 14 | lw a3, 44(zero) 15 | lw a2, 48(zero) 16 | -------------------------------------------------------------------------------- /src/peripheral/gpio.v: -------------------------------------------------------------------------------- 1 | `include "config.vh" 2 | 3 | `ifdef GPIO_ENABLE 4 | 5 | module GPIO ( 6 | inout wire gpio, 7 | input wire data_in, 8 | input wire direction, 9 | output wire data_out 10 | ); 11 | 12 | assign data_out = (gpio & direction) | (data_in & ~direction); // direction == 1 -> input, direction == 0 -> output 13 | assign gpio = (direction == 1'b1) ? 1'bz : data_in; 14 | 15 | endmodule 16 | 17 | `endif -------------------------------------------------------------------------------- /tests/reset_test.v: -------------------------------------------------------------------------------- 1 | module reset_tb (); 2 | 3 | reg clk; 4 | wire reset, resetn; 5 | 6 | always #1 clk = ~clk; 7 | 8 | ResetBootSystem #( 9 | .CYCLES(20) 10 | ) Reset( 11 | .clk(clk), 12 | .reset_o(reset), 13 | .resetn_o(resetn) 14 | ); 15 | 16 | initial begin 17 | $dumpfile("build/reset.vcd"); 18 | $dumpvars; 19 | 20 | clk = 1'b0; 21 | 22 | #60 23 | 24 | $finish; 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /fpga/cyclone10gx/pinout.sdc: -------------------------------------------------------------------------------- 1 | # inform Quartus that the clk port brings a 50MHz clock into our design so 2 | # that timing closure on our design can be analyzed 3 | create_clock -name clk -period "50MHz" [get_ports clk] 4 | # inform Quartus that the LED output port has no critical timing requirements 5 | # it’s a single output port driving an LED, there are no timing relationships 6 | # that are critical for this 7 | set_false_path -from * -to [get_ports LED] -------------------------------------------------------------------------------- /fpga/nexys4_ddr/Makefile: -------------------------------------------------------------------------------- 1 | ifndef VIVADO_PATH 2 | VIVADO=vivado 3 | else 4 | VIVADO=$(VIVADO_PATH)/vivado 5 | endif 6 | 7 | all: ./build/out.bit 8 | 9 | ./build/out.bit: buildFolder 10 | $(VIVADO) -mode batch -nolog -nojournal -source run.tcl 11 | buildFolder: 12 | mkdir -p build 13 | 14 | clean: 15 | rm -rf build 16 | rm clockInfo.txt 17 | 18 | load: 19 | openFPGALoader -b nexys_a7_100 ./build/out.bit 20 | 21 | run_all: ./build/out.bit load -------------------------------------------------------------------------------- /fpga/digilent_arty/Makefile: -------------------------------------------------------------------------------- 1 | ifndef VIVADO_PATH 2 | VIVADO=vivado 3 | else 4 | VIVADO=$(VIVADO_PATH)/vivado 5 | endif 6 | 7 | all: ./build/out.bit 8 | 9 | ./build/out.bit: buildFolder 10 | $(VIVADO) -mode batch -nolog -nojournal -source run.tcl 11 | buildFolder: 12 | mkdir -p build 13 | 14 | clean: 15 | rm -rf build 16 | rm clockInfo.txt 17 | 18 | load: 19 | openFPGALoader -b arty_a7_100t ./build/out.bit 20 | 21 | run_all: ./build/out.bit load -------------------------------------------------------------------------------- /software/code/loop3.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x5, zero, 63; 5 | addi a4, zero, 2047 6 | add a4, a4, a4 7 | addi a4, a4, 2 8 | 9 | j reset; 10 | 11 | reset: 12 | add x3, zero, zero; 13 | j loop; 14 | 15 | loop: 16 | addi x3, x3, 1; # x3 = x3 + 1 17 | sw x3, 0(a4) 18 | 19 | beq x3, x5, fim; # if t0 == t1 then fim 20 | j loop; 21 | 22 | fim: 23 | addi x4, zero, 5 24 | j reset; 25 | -------------------------------------------------------------------------------- /software/code/forloop.S: -------------------------------------------------------------------------------- 1 | .text 2 | .global _start 3 | 4 | _start: 5 | call main 6 | 7 | main: 8 | addi t0, zero, 0 # i 9 | addi t1, zero, 0 # a 10 | addi t2, zero, 100 # constante 100 para limite do for 11 | 12 | for: 13 | bge t0, t2, fim # i >= 100 ? vá para o fim 14 | add t1, t1, t0 # a += i 15 | addi t0, t0, 1 # i++ 16 | j for # vá para o início do loop 17 | 18 | fim: 19 | jr ra # retorne 20 | -------------------------------------------------------------------------------- /software/memory/fpga_test_4.hex: -------------------------------------------------------------------------------- 1 | 80000437 2 | 400004b7 3 | 04a00913 4 | 00000293 5 | 00000313 6 | 00000e13 7 | 0ff00993 8 | 00200a13 9 | 000c3ab7 10 | 500a8a93 11 | 00528293 12 | 0054a023 13 | 00c000ef 14 | 0132de63 15 | ff1ff06f 16 | 00000313 17 | 00130313 18 | 01530463 19 | ff9ff06f 20 | 00008067 21 | 00000293 22 | 0134a023 23 | 00c0006f 24 | fe1ff0ef 25 | fc9ff06f 26 | 00000e13 27 | 01242023 28 | fd1ff0ef 29 | 00442e83 30 | 000e8463 31 | fb1ff06f 32 | 00042903 33 | 012a2023 34 | fa5ff06f 35 | -------------------------------------------------------------------------------- /tests/mux_test.v: -------------------------------------------------------------------------------- 1 | module mux_tb(); 2 | 3 | reg [31:0] MUX_A, MUX_B; 4 | reg MUX_Option; 5 | wire [31:0] MUX_S; 6 | 7 | MUX MUX( 8 | .A(MUX_A), 9 | .B(MUX_B), 10 | .S(MUX_S), 11 | .option(MUX_Option) 12 | ); 13 | 14 | initial begin 15 | MUX_A = 5; 16 | MUX_B = 3; 17 | MUX_Option = 0; 18 | 19 | #1 20 | 21 | $display("Estado ", MUX_S); 22 | MUX_Option = 1; 23 | 24 | #1 25 | $display("Estado ", MUX_S); 26 | 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /software/code/beq.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x12, zero, 1; 5 | addi x9, zero, 1; 6 | 7 | beq x12, x9, desvio; 8 | 9 | addi x13, zero, 5; 10 | add x14, x12, x13; 11 | sw x14, 0(x12); 12 | lw x14, 0(x12); 13 | sub x11, x13, x12; 14 | addi x10, zero, 25; 15 | addi x10, x10, -15; 16 | and x15, x12, x13; 17 | or x15, x12, x13; 18 | addi x10, zero, 100; 19 | 20 | desvio: 21 | addi x16, zero, 17; 22 | andi x16, x16, 17; 23 | -------------------------------------------------------------------------------- /software/code/beq2.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x12, zero, 1; 5 | addi x9, zero, 2; 6 | 7 | beq x12, x9, desvio; 8 | 9 | addi x13, zero, 5; 10 | add x14, x12, x13; 11 | sw x14, 0(x12); 12 | lw x14, 0(x12); 13 | sub x11, x13, x12; 14 | addi x10, zero, 25; 15 | addi x10, x10, -15; 16 | and x15, x12, x13; 17 | or x15, x12, x13; 18 | addi x10, zero, 100; 19 | 20 | desvio: 21 | addi x16, zero, 17; 22 | andi x16, x16, 17; 23 | -------------------------------------------------------------------------------- /software/code/sltu.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | 7 | sltu a3, a1, a2 # 1 8 | sltu a4, a2, a1 # 0 9 | 10 | li a5, 0xFFFFFFFF 11 | li a6, 0xDFFFFFFF 12 | li a0, 0x00000000 13 | 14 | sltu a7, a5, a6 # 0 rs1 < rs2 15 | sltu t0, a6, a5 # 1 16 | sltu t1, a0, a0 # 0 17 | sltu t2, a5, a0 # 0 18 | sltu t3, a0, a5 # 1 19 | -------------------------------------------------------------------------------- /software/code/memory_vector.s: -------------------------------------------------------------------------------- 1 | .text 2 | 3 | .global _start 4 | 5 | _start: 6 | la a0, numbers 7 | addi a2, a0, 40 8 | li a1, 10 9 | 10 | store: 11 | beq a2, a0, mid 12 | 13 | sw a1, 0(a0) 14 | 15 | addi a0, a0, 4 16 | addi a1, a1, 1 17 | 18 | j store 19 | 20 | mid: 21 | la a0, numbers 22 | 23 | load: 24 | beq a2, a0, stop 25 | 26 | lw a1, 0(a0) 27 | 28 | addi a0, a0, 4 29 | 30 | j load 31 | 32 | stop: 33 | li ra, 5 34 | 35 | .data 36 | numbers: .skip 40; 37 | -------------------------------------------------------------------------------- /software/code/sltiu.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | 7 | sltiu a3, a1, 15 # rs1 < imm 8 | sltiu a4, a2, 10 # rs2 < imm 9 | 10 | li a5, 0xFFFFFFFF 11 | li a6, 0x00000DFF 12 | li a0, 0x00000000 13 | 14 | sltiu a7, a5, 00000000 # 0 rs1 < imm 15 | sltiu t0, a6, -2048 # 1 16 | sltiu t1, a0, 0 # 0 17 | sltiu t2, a5, 0 # 0 18 | sltiu t3, a0, -2048 # 1 19 | -------------------------------------------------------------------------------- /fpga/de1soc/pinout.sdc: -------------------------------------------------------------------------------- 1 | # inform Quartus that the clk port brings a 50MHz clock into our design so 2 | # that timing closure on our design can be analyzed 3 | create_clock -name clk -period "50MHz" [get_ports clk] 4 | # inform Quartus that the LED output port has no critical timing requirements 5 | # it’s a single output port driving an LED, there are no timing relationships 6 | # that are critical for this 7 | set_false_path -from * -to [get_ports led[*]] 8 | set_false_path -from * -to [get_ports sw[*]] 9 | set_false_path -from * -to [get_ports btn[*]] 10 | -------------------------------------------------------------------------------- /src/core/pc.v: -------------------------------------------------------------------------------- 1 | module PC #( 2 | parameter BOOT_ADDRESS=32'h00000000 3 | )( 4 | input wire clk, 5 | input wire load, 6 | input wire reset, 7 | input wire [31:0] Input, 8 | output reg [31:0] Output 9 | ); 10 | 11 | initial begin 12 | Output = BOOT_ADDRESS; 13 | end 14 | 15 | always @(posedge clk) begin 16 | if(reset == 1'b1) begin 17 | Output <= BOOT_ADDRESS; 18 | end else begin 19 | if(load == 1'b1) begin 20 | Output <= Input; 21 | end 22 | end 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /software/code/teste_led.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | 7 | add a3, a1, a2 # Soma a1 e a2, armazena o resultado em a3 8 | li a4, 0x40000000; 9 | 10 | sw a3, 68(zero) 11 | sw a2, 72(zero) 12 | sw a1, 76(zero) 13 | sw a3, 0(a4) 14 | 15 | lw a1, 68(zero) 16 | lw a3, 72(zero) 17 | lw a2, 76(zero) 18 | 19 | lw a5, 68(zero) 20 | lw a6, 72(zero) 21 | lw a7, 76(zero) 22 | -------------------------------------------------------------------------------- /run_test.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/bash 2 | 3 | mkdir -p build 4 | 5 | # Verifica se um argumento foi passado, caso contrário executa read 6 | if [ -z "$1" ]; then 7 | echo "Digite o nome do teste:" 8 | read nome_do_teste 9 | else 10 | nome_do_teste=$1 11 | fi 12 | 13 | cp software/memory/$nome_do_teste.hex software/memory/generic.hex 14 | 15 | iverilog -o build/soc_test.o -s soc_tb -I src/core -I src/peripheral src/core/*.v src/peripheral/*.v tests/soc_test.v 16 | vvp build/soc_test.o 17 | 18 | rm software/memory/generic.hex 19 | 20 | echo "Teste $nome_do_teste, executado" -------------------------------------------------------------------------------- /software/memory/fpga_test_3.hex: -------------------------------------------------------------------------------- 1 | 03f00793 2 | 024000ef 3 | 028000ef 4 | 0ff00a13 5 | 7d000993 6 | 013989b3 7 | 00899993 8 | 00000813 9 | 00500893 10 | 0380006f 11 | 40000737 12 | 00008067 13 | 80000637 14 | 00008067 15 | 04a00313 16 | 00662023 17 | 00008067 18 | 01472023 19 | 00000813 20 | 030000ef 21 | 02c000ef 22 | 028000ef 23 | 038000ef 24 | 000006b3 25 | 00180813 26 | fd5ff0ef 27 | fd180ee3 28 | 024000ef 29 | 00128293 30 | ff32cee3 31 | 00008067 32 | 00008913 33 | 00000293 34 | fedff0ef 35 | 00090093 36 | 00008067 37 | 00168693 38 | 00d72023 39 | fe5ff0ef 40 | 00f68463 41 | ff1ff0ef 42 | fb9ff0ef 43 | -------------------------------------------------------------------------------- /software/code/loop_2.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi x2, x0, 2047; 5 | addi x4, x0, 255; 6 | addi x10, x0, 2000; 7 | addi x10, x10, 1000; 8 | addi x16, x0, 76; 9 | slli x2, x2, 15; 10 | 11 | beq x0, x0, reset; 12 | 13 | reset: 14 | add x15, x0, x0; # x15 = x0 + x0 15 | add x3, x0, x0; 16 | 17 | beq x0, x0, loop; 18 | 19 | loop: 20 | addi x15, x15, 1; 21 | lw x16, 2000(x10); 22 | 23 | beq x15, x4, reset; 24 | 25 | beq x0, x0, time; 26 | 27 | 28 | time: 29 | addi x3, x3, 1; 30 | 31 | beq x3, x2, loop; 32 | 33 | beq x0, x0, time; 34 | 35 | -------------------------------------------------------------------------------- /software/code/teste_uart_tx.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi a1, zero, 10 # Carrega o primeiro número (10) em a1 5 | addi a2, zero, 20 # Carrega o segundo número (20) em a2 6 | 7 | add a3, a1, a2 # Soma a1 e a2, armazena o resultado em a3 8 | li a4, 0x80000000 9 | 10 | li t1, 73; 11 | 12 | sw a3, 68(zero) 13 | sw a2, 72(zero) 14 | sw a1, 76(zero) 15 | sw t1, 0(a4) 16 | 17 | lw a1, 68(zero) 18 | lw a3, 72(zero) 19 | lw a2, 76(zero) 20 | 21 | lw a5, 68(zero) 22 | lw a6, 72(zero) 23 | lw a7, 76(zero) 24 | 25 | loop: 26 | j loop; 27 | -------------------------------------------------------------------------------- /docs/requirements.txt: -------------------------------------------------------------------------------- 1 | Babel==2.14.0 2 | certifi==2024.2.2 3 | charset-normalizer==3.3.2 4 | click==8.1.7 5 | colorama==0.4.6 6 | ghp-import==2.1.0 7 | idna==3.6 8 | Jinja2==3.1.3 9 | Markdown==3.5.2 10 | MarkupSafe==2.1.5 11 | mergedeep==1.3.4 12 | mkdocs==1.5.3 13 | mkdocs-material==9.5.12 14 | mkdocs-material-extensions==1.3.1 15 | packaging==23.2 16 | paginate==0.5.6 17 | pathspec==0.12.1 18 | platformdirs==4.2.0 19 | Pygments==2.17.2 20 | pymdown-extensions==10.7.1 21 | python-dateutil==2.9.0.post0 22 | PyYAML==6.0.1 23 | pyyaml_env_tag==0.1 24 | regex==2023.12.25 25 | requests==2.31.0 26 | six==1.16.0 27 | urllib3==2.2.1 28 | watchdog==4.0.0 29 | -------------------------------------------------------------------------------- /software/generate_mem.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/bash 2 | 3 | mkdir -p build 4 | 5 | # Verifica se um argumento foi passado, caso contrário executa read 6 | if [ -z "$1" ]; then 7 | echo "Digite o nome do teste:" 8 | read nome_do_teste 9 | else 10 | nome_do_teste=$1 11 | fi 12 | 13 | riscv32-unknown-elf-as -march=rv32izicsr code/$nome_do_teste.S -o build/$nome_do_teste.o 14 | riscv32-unknown-elf-ld build/$nome_do_teste.o -o build/$nome_do_teste.elf 15 | riscv32-unknown-elf-objcopy -O binary build/$nome_do_teste.elf build/$nome_do_teste.bin 16 | hexdump -v -e '1/4 "%08x" "\n"' build/$nome_do_teste.bin > memory/$nome_do_teste.hex 17 | 18 | echo "Teste $nome_do_teste, compilado" -------------------------------------------------------------------------------- /software/firmware/compile.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/zsh 2 | 3 | mkdir -p build 4 | 5 | echo "Digite o nome do teste:" 6 | read nome_do_teste 7 | 8 | riscv32-unknown-elf-gcc -march=rv32id -std=gnu99 -mabi=ilp32 -Wall $nome_do_teste.c \ 9 | -nostartfiles -nostdinc -nostdlib -mstrict-align -S -T link.ld 10 | riscv32-unknown-elf-as -march=rv32i $nome_do_teste.s -o build/$nome_do_teste.o 11 | riscv32-unknown-elf-ld build/$nome_do_teste.o -o build/$nome_do_teste.elf -T link.ld 12 | riscv32-unknown-elf-objcopy -O binary build/$nome_do_teste.elf build/$nome_do_teste.bin 13 | hexdump -v -e '1/4 "%08x" "\n"' build/$nome_do_teste.bin > memory/$nome_do_teste.hex 14 | 15 | echo "Teste $nome_do_teste, compilado" -------------------------------------------------------------------------------- /software/firmware/lib/uart.h: -------------------------------------------------------------------------------- 1 | #ifndef __UART_H__ 2 | #define __UART_H__ 3 | 4 | #define UART_BASE_ADDR 0x80000000 5 | 6 | #define UART_READ_DATA_IMEDIATE 0x00000000 7 | #define UART_READ_RX_EMPTY_IMEDIATE 0x00000004 8 | #define UART_READ_TX_EMPTY_IMEDIATE 0x00000008 9 | #define UART_READ_RX_FULL_IMEDIATE 0x0000000C 10 | #define UART_READ_TX_FULL_IMEDIATE 0x00000010 11 | 12 | int uart_rx_empty(); 13 | int uart_tx_empty(); 14 | int uart_rx_full(); 15 | int uart_tx_full(); 16 | char uart_read(); 17 | void uart_write(char data); 18 | 19 | int uart_read_string(char *data, int size); 20 | void uart_write_string(char *data); 21 | void uart_write_int(int data); 22 | 23 | #endif // !__UART_H__ -------------------------------------------------------------------------------- /src/core/mux.v: -------------------------------------------------------------------------------- 1 | module MUX ( 2 | input wire [2:0] option, 3 | input wire [31:0] A, 4 | input wire [31:0] B, 5 | input wire [31:0] C, 6 | input wire [31:0] D, 7 | input wire [31:0] E, 8 | input wire [31:0] F, 9 | input wire [31:0] G, 10 | input wire [31:0] H, 11 | output reg [31:0] S 12 | ); 13 | 14 | always @(*) begin 15 | case (option) 16 | 3'b000: S = A; 17 | 3'b001: S = B; 18 | 3'b010: S = C; 19 | 3'b011: S = D; 20 | 3'b100: S = E; 21 | 3'b101: S = F; 22 | 3'b110: S = G; 23 | 3'b111: S = H; 24 | default: S = A; // Caso padrão 25 | endcase 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /software/memory/fibonacci.hex: -------------------------------------------------------------------------------- 1 | 080000ef 2 | fe010113 3 | 00112e23 4 | 00812c23 5 | 00912a23 6 | 02010413 7 | fea42623 8 | fec42703 9 | 00100793 10 | 00f70863 11 | fec42703 12 | 00200793 13 | 00f71663 14 | 00100793 15 | 0300006f 16 | fec42783 17 | fff78793 18 | 00078513 19 | fbdff0ef 20 | 00050493 21 | fec42783 22 | 00278793 23 | 00078513 24 | fa9ff0ef 25 | 00050793 26 | 00f487b3 27 | 00078513 28 | 01c12083 29 | 01812403 30 | 01412483 31 | 02010113 32 | 00008067 33 | fe010113 34 | 00112e23 35 | 00812c23 36 | 02010413 37 | 000017b7 38 | fef42623 39 | 00500513 40 | f69ff0ef 41 | fea42423 42 | fec42783 43 | fe842703 44 | 00e7a023 45 | 00000793 46 | 00078513 47 | 01c12083 48 | 01812403 49 | 02010113 50 | -------------------------------------------------------------------------------- /fpga/cyclone10gx/main.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input wire clk, // 50mhz clock 3 | output wire LED 4 | ); 5 | 6 | wire reset_o; 7 | wire [7:0] led; 8 | 9 | assign LED = led[0]; 10 | 11 | ResetBootSystem #( 12 | .CYCLES(20) 13 | ) ResetBootSystem( 14 | .clk(clk), 15 | .reset_o(reset_o) 16 | ); 17 | 18 | Risco_5_SOC #( 19 | .CLOCK_FREQ(50000000), 20 | .BIT_RATE(115200), 21 | .MEMORY_SIZE(2048), 22 | .MEMORY_FILE("../../software/memory/teste_uart_fpga.hex"), 23 | .GPIO_WIDHT(6), 24 | .UART_BUFFER_SIZE(16) 25 | ) SOC( 26 | .clk(clk), 27 | .reset(reset_o), 28 | .leds(led), 29 | .rx(), 30 | .tx(), 31 | .gpios() 32 | ); 33 | 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /software/code/unaligned_lw.S: -------------------------------------------------------------------------------- 1 | .text 2 | .global _start 3 | 4 | _start: 5 | li a0, 0x88887FFF 6 | li a1, 0xFFFFFFFF 7 | li a2, 0x88888888 8 | 9 | sw a1, 100(zero) 10 | sw a2, 104(zero) 11 | sw a0, 108(zero) 12 | 13 | lw a3, 101(zero) 14 | lw a4, 102(zero) 15 | lw a5, 103(zero) 16 | 17 | lh a6, 101(zero) 18 | lh a7, 102(zero) 19 | lh s2, 103(zero) 20 | 21 | lb s3, 101(zero) 22 | lb s4, 102(zero) 23 | lb s5, 103(zero) 24 | 25 | lhu s6, 101(zero) 26 | lhu s7, 102(zero) 27 | lhu s8, 103(zero) 28 | 29 | lbu s9, 101(zero) 30 | lbu s10, 102(zero) 31 | lbu s11, 103(zero) 32 | 33 | lh t3, 108(zero) 34 | lb t4, 109(zero) 35 | -------------------------------------------------------------------------------- /software/code/fpga_test_2.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | addi s0, zero, 255 5 | li s1, 0x40000000; 6 | li s2, 3000000 7 | 8 | addi t0, zero, 0 9 | addi t1, zero, 0 10 | 11 | loop: 12 | addi t0, t0, 1 13 | 14 | sw t0, 0(s1) 15 | 16 | call delay; # call delay 17 | 18 | beq t0, s0, reset; # if t0 == s0 reset 19 | 20 | j loop; # jump to loop 21 | 22 | delay: 23 | li t1, 0; 24 | delay_loop: 25 | addi t1, t1, 1; 26 | 27 | beq t1, s2, fim; # if t1 == s2 fim 28 | 29 | j delay_loop; # jump to delay 30 | 31 | fim: 32 | ret 33 | 34 | reset: 35 | li t0, 0; 36 | 37 | sw s0, 0(s1) 38 | 39 | call delay; # call loop 40 | 41 | j loop; # jump to loop 42 | -------------------------------------------------------------------------------- /fpga/colorlight_i9/main.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input wire clk, 3 | input wire reset, 4 | input wire rx, 5 | output wire tx, 6 | output wire [7:0]led, 7 | inout [5:0]gpios 8 | ); 9 | 10 | wire reset_o; 11 | 12 | ResetBootSystem #( 13 | .CYCLES(20) 14 | ) ResetBootSystem( 15 | .clk(clk), 16 | .reset_o(reset_o) 17 | ); 18 | 19 | Risco_5_SOC #( 20 | .CLOCK_FREQ(25000000), 21 | .BIT_RATE(115200), 22 | .MEMORY_SIZE(4096), 23 | .MEMORY_FILE("../../software/memory/teste_led.hex"), 24 | .GPIO_WIDHT(6), 25 | .UART_BUFFER_SIZE(16) 26 | ) SOC( 27 | .clk(clk), 28 | .reset(reset_o), 29 | .leds(led), 30 | .rx(rx), 31 | .tx(tx), 32 | .gpios(gpios) 33 | ); 34 | 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /fpga/xilinx_vc709/Makefile: -------------------------------------------------------------------------------- 1 | ifndef VIVADO_PATH 2 | VIVADO=vivado 3 | else 4 | VIVADO=$(VIVADO_PATH)/vivado 5 | endif 6 | 7 | all: ./build/out.bit 8 | 9 | ./build/out.bit: buildFolder 10 | @echo "Building the Design..." 11 | $(VIVADO) -mode batch -nolog -nojournal -source run.tcl 12 | buildFolder: 13 | @echo "Creating the build folder..." 14 | mkdir -p build 15 | 16 | clean: 17 | @echo "Cleaning the build folder..." 18 | rm -rf build 19 | 20 | # openFPGALoader funciona apenas na versão nightly, a versão estavel atual não suporta a vc709 ainda 21 | load: 22 | @echo "Flashing the FPGA..." 23 | openFPGALoader -b vc709 ./build/out.bit 24 | #$(VIVADO_PATH)/vivado -mode batch -nolog -nojournal -source flash.tcl 25 | 26 | run_all: ./build/out.bit load -------------------------------------------------------------------------------- /software/firmware/lib/risco5.h: -------------------------------------------------------------------------------- 1 | #ifndef __RISCO_5_H__ 2 | #define __RISCO_5_H__ 3 | 4 | #define MEM_SIZE 0x00008004 5 | #define STACK_INIT MEM_SIZE - 4 6 | #define FRAME_POINTER 0X00004000 7 | 8 | #define NOP_TIME 5 // 4 cycles 9 | #define CLK_FREQ 50000000 // 50 MHz 10 | #define MS_TO_CYCLES 50000 // 1MS 11 | #define NUM_NOPS_TO_MS 12500 // 1MS 12 | 13 | 14 | void *memset (void *dest, register int val, register int len); 15 | void *memcpy (void *out, const void *in, int length); 16 | int strlen(const char *str); 17 | char *strcpy(char *destination, const char *source); 18 | int strcmp(const char *str1, const char *str2); 19 | char *strcat(char *destination, const char *source); 20 | 21 | void delay_ms(int time); 22 | 23 | 24 | #endif // __RISCO_5_H__ -------------------------------------------------------------------------------- /fpga/tangnano20k_yosys/main.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input wire clk, 3 | input wire reset, 4 | input wire rx, 5 | output wire tx, 6 | output wire [5:0] led, 7 | inout [4:0]gpios 8 | ); 9 | 10 | wire reset_o; 11 | wire [7:0] leds; 12 | 13 | ResetBootSystem #( 14 | .CYCLES(20) 15 | ) ResetBootSystem( 16 | .clk(clk), 17 | .reset_o(reset_o) 18 | ); 19 | 20 | assign led = leds [5:0]; 21 | 22 | Risco_5_SOC #( 23 | .CLOCK_FREQ(27000000), 24 | .BIT_RATE(9600), 25 | .MEMORY_SIZE(2048), 26 | .MEMORY_FILE("../../software/memory/fpga_test_3.hex"), 27 | .GPIO_WIDHT(5) 28 | ) SOC( 29 | .clk(clk), 30 | .reset(reset_o), 31 | .leds(leds), 32 | .rx(rx), 33 | .tx(tx), 34 | .gpios(gpios) 35 | ); 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /fpga/tangnano20k/pinout.cst: -------------------------------------------------------------------------------- 1 | IO_LOC "clk" 4; 2 | IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP; 3 | 4 | IO_LOC "reset" 88; 5 | IO_PORT "reset" IO_TYPE=LVCMOS33; 6 | 7 | IO_LOC "tx" 69; 8 | IO_PORT "tx" IO_TYPE=LVCMOS33 PULL_MODE=UP; 9 | 10 | IO_LOC "rx" 70; 11 | IO_PORT "rx" IO_TYPE=LVCMOS33 PULL_MODE=UP; 12 | 13 | IO_LOC "led[0]" 20; 14 | IO_PORT "led[0]" DRIVE=8 IO_TYPE=LVCMOS33; 15 | 16 | IO_LOC "led[1]" 19; 17 | IO_PORT "led[1]" DRIVE=8 IO_TYPE=LVCMOS33; 18 | 19 | IO_LOC "led[2]" 18; 20 | IO_PORT "led[2]" DRIVE=8 IO_TYPE=LVCMOS33; 21 | 22 | IO_LOC "led[3]" 17; 23 | IO_PORT "led[3]" DRIVE=8 IO_TYPE=LVCMOS33; 24 | 25 | IO_LOC "led[4]" 16; 26 | IO_PORT "led[4]" DRIVE=8 IO_TYPE=LVCMOS33; 27 | 28 | IO_LOC "led[5]" 15; 29 | IO_PORT "led[5]" DRIVE=8 IO_TYPE=LVCMOS33; 30 | -------------------------------------------------------------------------------- /fpga/tangnano20k_yosys/pinout.cst: -------------------------------------------------------------------------------- 1 | IO_LOC "clk" 4; 2 | IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP; 3 | 4 | IO_LOC "reset" 88; 5 | IO_PORT "reset" IO_TYPE=LVCMOS33; 6 | 7 | IO_LOC "tx" 69; 8 | IO_PORT "tx" IO_TYPE=LVCMOS33 PULL_MODE=UP; 9 | 10 | IO_LOC "rx" 70; 11 | IO_PORT "rx" IO_TYPE=LVCMOS33 PULL_MODE=UP; 12 | 13 | IO_LOC "led[0]" 20; 14 | IO_PORT "led[0]" DRIVE=8 IO_TYPE=LVCMOS33; 15 | 16 | IO_LOC "led[1]" 19; 17 | IO_PORT "led[1]" DRIVE=8 IO_TYPE=LVCMOS33; 18 | 19 | IO_LOC "led[2]" 18; 20 | IO_PORT "led[2]" DRIVE=8 IO_TYPE=LVCMOS33; 21 | 22 | IO_LOC "led[3]" 17; 23 | IO_PORT "led[3]" DRIVE=8 IO_TYPE=LVCMOS33; 24 | 25 | IO_LOC "led[4]" 16; 26 | IO_PORT "led[4]" DRIVE=8 IO_TYPE=LVCMOS33; 27 | 28 | IO_LOC "led[5]" 15; 29 | IO_PORT "led[5]" DRIVE=8 IO_TYPE=LVCMOS33; 30 | -------------------------------------------------------------------------------- /fpga/tangnano20k/main.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input wire clk, 3 | input wire reset, 4 | input wire rx, 5 | output wire tx, 6 | output wire [5:0] led, 7 | inout [4:0]gpios 8 | ); 9 | 10 | wire reset_o; 11 | wire [7:0] leds; 12 | 13 | ResetBootSystem #( 14 | .CYCLES(20) 15 | ) ResetBootSystem( 16 | .clk(clk), 17 | .reset_o(reset_o) 18 | ); 19 | 20 | assign led = leds [5:0]; 21 | 22 | Risco_5_SOC #( 23 | .CLOCK_FREQ(27000000), 24 | .BIT_RATE(115200), 25 | .MEMORY_SIZE(2048), 26 | .MEMORY_FILE("../../software/memory/teste_uart_fpga.hex"), 27 | .GPIO_WIDHT(5), 28 | .UART_BUFFER_SIZE(16) 29 | ) SOC( 30 | .clk(clk), 31 | .reset(reset_o), 32 | .leds(leds), 33 | .rx(rx), 34 | .tx(tx), 35 | .gpios(gpios) 36 | ); 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /src/peripheral/leds.v: -------------------------------------------------------------------------------- 1 | `include "config.vh" 2 | 3 | `ifdef LED_ENABLE 4 | 5 | module LEDs ( 6 | input wire clk, 7 | input wire reset, 8 | input wire read, 9 | input wire write, 10 | input wire [31:0] address, 11 | input wire [31:0] write_data, 12 | output wire [31:0] read_data, 13 | output wire response, 14 | output wire [7:0] leds 15 | ); 16 | 17 | assign response = read | write; 18 | 19 | reg [31:0] data; 20 | 21 | initial begin 22 | data = 0; 23 | end 24 | 25 | assign read_data = (read == 1'b1) ? data : 32'h00000000; 26 | 27 | always @(posedge clk ) begin 28 | if(reset == 1'b1) begin 29 | data <= 1'b0; 30 | end else if(write) begin 31 | data <= write_data; 32 | end 33 | end 34 | 35 | assign leds = ~data[7:0]; 36 | 37 | endmodule 38 | 39 | `endif -------------------------------------------------------------------------------- /src/peripheral/pwm.v: -------------------------------------------------------------------------------- 1 | `include "config.vh" 2 | 3 | `ifdef GPIO_ENABLE 4 | 5 | module PWM ( 6 | input wire clk, 7 | input wire reset, 8 | input wire [15:0] duty_cycle, // duty cycle = period * duty_cycle / 65536 9 | input wire [15:0] period, // clk_freq / pwm_freq = period 10 | output reg pwm_out 11 | ); 12 | 13 | reg [31:0] counter; 14 | 15 | always @(posedge clk) begin 16 | if (reset) begin 17 | counter <= 0; 18 | 19 | end else begin 20 | if(counter < period - 1'b1) begin 21 | counter <= counter + 1'b1; 22 | end else begin 23 | counter <= 0; 24 | end 25 | end 26 | 27 | if (counter < duty_cycle) begin 28 | pwm_out <= 1; 29 | end else begin 30 | pwm_out <= 0; 31 | end 32 | end 33 | 34 | endmodule 35 | 36 | `endif -------------------------------------------------------------------------------- /fpga/de1soc/main.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input wire clk, // 50mhz clock 3 | input wire [3:0] btn, 4 | input wire [9:0] sw, 5 | input wire uart_rx, 6 | output wire uart_tx, 7 | output wire [9:0] led 8 | ); 9 | 10 | wire reset_o; 11 | 12 | wire [7:0]leds; 13 | 14 | assign led = {leds, 2'b01}; 15 | 16 | ResetBootSystem #( 17 | .CYCLES(20) 18 | ) ResetBootSystem( 19 | .clk(clk), 20 | .reset_o(reset_o) 21 | ); 22 | 23 | Risco_5_SOC #( 24 | .CLOCK_FREQ(50000000), 25 | .BIT_RATE(115200), 26 | .MEMORY_SIZE(2048), 27 | .MEMORY_FILE("../../software/memory/teste_uart_fpga.hex"), 28 | .GPIO_WIDHT(6), 29 | .UART_BUFFER_SIZE(16) 30 | ) SOC( 31 | .clk(clk), 32 | .reset(reset_o), 33 | .leds(leds), 34 | .rx(), 35 | .tx(), 36 | .gpios() 37 | ); 38 | 39 | 40 | endmodule -------------------------------------------------------------------------------- /tests/soc_test.v: -------------------------------------------------------------------------------- 1 | module soc_tb(); 2 | 3 | reg clk, reset; 4 | wire rx, tx; 5 | wire [7:0] gpios; 6 | wire [7:0] led; 7 | 8 | reg [3:0] data = 4'b1010; 9 | 10 | assign gpios[7:4] = data; 11 | 12 | always #1 clk = ~clk; 13 | 14 | Risco_5_SOC #( 15 | .CLOCK_FREQ(25000000), 16 | .BIT_RATE(115200), 17 | .MEMORY_SIZE(32772), 18 | .MEMORY_FILE("software/memory/generic.hex"), 19 | .GPIO_WIDHT(8), 20 | .UART_BUFFER_SIZE(16) 21 | ) SOC( 22 | .clk(clk), 23 | .reset(reset), 24 | .leds(led), 25 | .rx(rx), 26 | .tx(tx), 27 | .gpios(gpios) 28 | ); 29 | 30 | initial begin 31 | $dumpfile("build/soc.vcd"); 32 | $dumpvars; 33 | 34 | clk = 1'b0; 35 | reset = 1'b1; 36 | #6 37 | reset = 1'b0; 38 | //#560 39 | 40 | #3600 41 | 42 | $finish; 43 | end 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /docs/docs/index.en.md: -------------------------------------------------------------------------------- 1 | # Risco 5 Documentation 2 | 3 |

4 | Processor Logo 5 |

6 | 7 | ## Risco 5 8 | 9 | Risco 5 is an open-source processor core that implements the RV32I/E[M] instruction set of the RISC-V architecture. It was developed for academic use and as the main core in small SoCs. The project focuses on facilitating integration and usage, offering a simplified and efficient architecture for various applications. 10 | 11 | ## Available Resources 12 | 13 | ### Risco-5 Core 14 | 15 | A RISC-V processor core implementing the RV32I/E[M] of RISC-V. 16 | 17 | ### Risco-5 SoC 18 | 19 | An SoC with the Risco-5 core containing memory and peripherals such as GPIOs and UART. 20 | 21 | ### Risco-5 Tests 22 | 23 | Tests written in RISC-V assembly for validating the Risco 5. -------------------------------------------------------------------------------- /fpga/tangnano20k_yosys/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: ./build/out.fs 3 | 4 | ./build/out.fs: ./build/out_pnr.json 5 | gowin_pack -d GW2AR-LV18QN88C8/I7 ./build/out_pnr.json -o ./build/out.fs 6 | 7 | ./build/out_pnr.json: ./build/out.json 8 | nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json \ 9 | --cst pinout.cst --device GW2AR-LV18QN88C8/I7 --lpf-allow-unconstrained 10 | 11 | ./build/out.json: main.v pinout.cst buildFolder 12 | yosys -p " \ 13 | read_verilog main.v; \ 14 | read_verilog ../../debug/reset.v; \ 15 | read_verilog ../../src/core/*.v; \ 16 | read_verilog ../../src/peripheral/*.v; \ 17 | synth_gowin -json ./build/out.json -abc9 \ 18 | " 19 | 20 | buildFolder: 21 | mkdir -p build 22 | 23 | clean: 24 | rm -rf build 25 | 26 | load: 27 | openFPGALoader -b tangnano20k ./build/out.fs 28 | 29 | run_all: ./build/out.fs load -------------------------------------------------------------------------------- /.github/FUNDING.yml: -------------------------------------------------------------------------------- 1 | # These are supported funding model platforms 2 | 3 | github: [JN513] # Replace with up to 4 GitHub Sponsors-enabled usernames e.g., [user1, user2] 4 | patreon: JN513 # Replace with a single Patreon username 5 | open_collective: # Replace with a single Open Collective username 6 | ko_fi: # Replace with a single Ko-fi username 7 | tidelift: # Replace with a single Tidelift platform-name/package-name e.g., npm/babel 8 | community_bridge: # Replace with a single Community Bridge project-name e.g., cloud-foundry 9 | liberapay: # Replace with a single Liberapay username 10 | issuehunt: # Replace with a single IssueHunt username 11 | otechie: # Replace with a single Otechie username 12 | lfx_crowdfunding: # Replace with a single LFX Crowdfunding project-name e.g., cloud-foundry 13 | custom: # Replace with up to 4 custom sponsorship URLs e.g., ['link1', 'link2'] 14 | -------------------------------------------------------------------------------- /docs/docs/index.md: -------------------------------------------------------------------------------- 1 | # Documentação do Risco 5 2 | 3 |

4 | Logo do processador 5 |

6 | 7 | ## O Risco 5 8 | 9 | O Risco 5 é um núcleo de processador de código aberto que implementa o conjunto de instruções RV32I/E[M] da arquitetura RISC-V. Foi desenvolvido para uso acadêmico e como o núcleo principal em pequenos SoCs. O projeto tem como foco facilitar a integração e utilização, oferecendo uma arquitetura simplificada e eficiente para diversas aplicações. 10 | 11 | ## Recursos Disponíveis 12 | 13 | ### Risco-5 Core 14 | 15 | Um núcleo de processador RISC-V com a implementação RV32I/E[M] do RISC-V. 16 | 17 | ### Risco-5 SoC 18 | 19 | Um SoC com o núcleo Risco-5 contendo memória e periféricos como GPIOs e UART. 20 | 21 | ### Risco-5 Testes 22 | 23 | Testes escritos em assembly RISC-V para validação do Risco 5. -------------------------------------------------------------------------------- /fpga/cyclone10gx/makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME = cyclone10_gx 2 | OUTPUT_DIR = build 3 | TOP_FILE = main.v 4 | 5 | #all: blink.v 6 | # quartus_syn blink 7 | # quartus_fit blink 8 | # quartus_asm blink 9 | 10 | all: ./$(OUTPUT_DIR)/$(PROJECT_NAME).sof 11 | 12 | ./$(OUTPUT_DIR)/$(PROJECT_NAME).sof: ./$(OUTPUT_DIR)/$(PROJECT_NAME).fit.finalize.rpt 13 | $(QUARTUS_PATH)quartus_asm $(PROJECT_NAME) 14 | 15 | ./$(OUTPUT_DIR)/$(PROJECT_NAME).fit.finalize.rpt: ./$(OUTPUT_DIR)/$(PROJECT_NAME).syn.rpt 16 | $(QUARTUS_PATH)quartus_fit $(PROJECT_NAME) 17 | 18 | ./$(OUTPUT_DIR)/$(PROJECT_NAME).syn.rpt: $(PROJECT_NAME).qsf $(TOP_FILE) 19 | $(QUARTUS_PATH)quartus_syn $(PROJECT_NAME) 20 | 21 | load: 22 | $(QUARTUS_PATH)quartus_pgm -a -o "p;$(OUTPUT_DIR)/$(PROJECT_NAME).sof" 23 | 24 | #flash: 25 | # quartus_pgm -a -o "p;build/blink.sof" 26 | 27 | 28 | clean: 29 | rm -rf $(OUTPUT_DIR) 30 | 31 | run_all: all load -------------------------------------------------------------------------------- /software/firmware/main.c: -------------------------------------------------------------------------------- 1 | #include "lib/risco5.h" 2 | #include "lib/uart.h" 3 | #include "lib/gpio.h" 4 | 5 | void send_string(char *str){ 6 | int len = strlen(str); 7 | 8 | for (int i = 0; i < len; i++) 9 | { 10 | uart_write(str[i]); 11 | delay_ms(1); 12 | } 13 | } 14 | 15 | int main(){ 16 | send_string("Hello World!\n\0"); 17 | //config_gpio_direction(0x00000000); 18 | set_led_value(0x000000CC); 19 | config_gpio_as_pwm(0x00000003); 20 | 21 | set_pwm_period(50000, 0x00000000); 22 | 23 | int duty_cicle = 20000; 24 | 25 | set_pwm_duty_cycle(duty_cicle, 0x00000000); 26 | /* 27 | while (1) 28 | { 29 | duty_cicle += 1000; 30 | if(duty_cicle > 45000){ 31 | duty_cicle = 0; 32 | } 33 | 34 | delay_ms(1000); 35 | 36 | set_pwm_duty_cycle(duty_cicle, 0x00000000); 37 | } 38 | */ 39 | return 0; 40 | } -------------------------------------------------------------------------------- /fpga/colorlight_i9/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: ./build/out.bit 3 | 4 | ./build/out.bit: ./build/out.config 5 | ecppack --compress --input ./build/out.config --bit ./build/out.bit 6 | 7 | ./build/out.config: ./build/out.json 8 | nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k \ 9 | --lpf pinout.lpf --textcfg ./build/out.config --package CABGA381 \ 10 | --speed 6 --lpf-allow-unconstrained --report ./build/report_timing.json \ 11 | --detailed-timing-report 12 | 13 | ./build/out.json: main.v pinout.lpf buildFolder 14 | yosys -p " \ 15 | read_verilog main.v; \ 16 | read_verilog ../../debug/reset.v; \ 17 | read_verilog ../../src/core/*.v; \ 18 | read_verilog ../../src/peripheral/*.v; \ 19 | synth_ecp5 -json ./build/out.json -abc9 \ 20 | " 21 | 22 | buildFolder: 23 | mkdir -p build 24 | 25 | clean: 26 | rm -rf build 27 | 28 | load: 29 | openFPGALoader -b colorlight-i9 ./build/out.bit 30 | 31 | run_all: ./build/out.bit load -------------------------------------------------------------------------------- /software/code/fibonacci.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | call main; 5 | 6 | fibonacci: 7 | addi sp,sp,-32 8 | sw ra,28(sp) 9 | sw s0,24(sp) 10 | sw s1,20(sp) 11 | addi s0,sp,32 12 | sw a0,-20(s0) 13 | lw a4,-20(s0) 14 | li a5,1 15 | beq a4,a5,.L2 16 | lw a4,-20(s0) 17 | li a5,2 18 | bne a4,a5,.L3 19 | .L2: 20 | li a5,1 21 | j .L4 22 | .L3: 23 | lw a5,-20(s0) 24 | addi a5,a5,-1 25 | mv a0,a5 26 | call fibonacci 27 | mv s1,a0 28 | lw a5,-20(s0) 29 | addi a5,a5,2 30 | mv a0,a5 31 | call fibonacci 32 | mv a5,a0 33 | add a5,s1,a5 34 | .L4: 35 | mv a0,a5 36 | lw ra,28(sp) 37 | lw s0,24(sp) 38 | lw s1,20(sp) 39 | addi sp,sp,32 40 | jr ra 41 | main: 42 | addi sp,sp,-32 43 | sw ra,28(sp) 44 | sw s0,24(sp) 45 | addi s0,sp,32 46 | li a5,4096 47 | sw a5,-20(s0) 48 | li a0,5 49 | call fibonacci 50 | sw a0,-24(s0) 51 | lw a5,-20(s0) 52 | lw a4,-24(s0) 53 | sw a4,0(a5) 54 | li a5,0 55 | mv a0,a5 56 | lw ra,28(sp) 57 | lw s0,24(sp) 58 | addi sp,sp,32 59 | -------------------------------------------------------------------------------- /fpga/cyclone10gx/create_project.tcl: -------------------------------------------------------------------------------- 1 | project_new cyclone10_gx -overwrite 2 | 3 | set_global_assignment -name FAMILY "Cyclone 10 GX" 4 | set_global_assignment -name TOP_LEVEL_ENTITY top 5 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 23.1.0 6 | set_global_assignment -name LAST_QUARTUS_VERSION "23.1.0 Pro Edition" 7 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY build 8 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 9 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 10 | set_global_assignment -name DEVICE 10CX220YF780E5G 11 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 12 | set_global_assignment -name VERILOG_FILE main.v 13 | 14 | set_location_assignment PIN_J23 -to clk 15 | set_location_assignment PIN_AF6 -to led 16 | 17 | set_instance_assignment -name IO_STANDARD "1.8 V" -to led -entity top 18 | set_instance_assignment -name IO_STANDARD "1.8 V" -to clk -entity top 19 | 20 | set_global_assignment -name SDC_FILE pinout.sdc 21 | 22 | #project close -------------------------------------------------------------------------------- /software/firmware/lib/gpio.h: -------------------------------------------------------------------------------- 1 | #ifndef __GPIO_H__ 2 | #define __GPIO_H__ 3 | 4 | #define LED_BASE_ADDR 0x40000000 5 | #define GPIO_BASE_ADDR 0xC0000000 6 | 7 | #define GPIO_WRITE_DIRECTION_IMEDIATE 0x00000000 8 | #define GPIO_WRITE_DATA_IMEDIATE 0x00000004 9 | #define GPIO_PWM_CONFIG_IMEDIATE 0x00000008 10 | #define GPIO_PWM_PERIOD_CONFIG_IMEDIATE 0x0000000C 11 | #define GPIO_PWM_DUTY_CYCLE_CONFIG_IMEDIATE 0x00000010 12 | 13 | #define CLK_FREQ 50000000 14 | #define MAX_PWM_FREQ 65535 15 | #define MAX_PWM_DUTY_CYCLE 65535 16 | 17 | void config_gpio_direction(int direction); 18 | void gpio_write_data(int data); 19 | int gpio_read_data(); 20 | 21 | void set_led_value(int value); 22 | 23 | int get_pwm_period(int freq); 24 | int get_pwm_duty_cycle(int period, int duty); 25 | 26 | void set_pwm_period(int period, int id); 27 | void set_pwm_duty_cycle(int duty_cycle, int id); 28 | 29 | void config_gpio_as_pwm(int gpio_mask); 30 | 31 | #endif // !__GPIO_H__ -------------------------------------------------------------------------------- /fpga/nexys4_ddr/main.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input wire clk, 3 | input wire CPU_RESETN, 4 | input wire rx, 5 | output wire tx, 6 | output wire [7:0]LED, 7 | inout [7:0]gpio 8 | ); 9 | 10 | wire reset_o, reset_in; 11 | wire [7:0] led; 12 | reg clk_o, reset_bousing; 13 | 14 | assign LED = ~led; 15 | assign reset_in = reset_o | reset_bousing; 16 | 17 | initial begin 18 | clk_o = 1'b0; 19 | reset_bousing = 1'b0; 20 | end 21 | 22 | ResetBootSystem #( 23 | .CYCLES(20) 24 | ) ResetBootSystem( 25 | .clk(clk_o), 26 | .reset_o(reset_o) 27 | ); 28 | 29 | Risco_5_SOC #( 30 | .CLOCK_FREQ(50000000), 31 | .BIT_RATE(115200), 32 | .MEMORY_SIZE(2048), 33 | .MEMORY_FILE("../../software/memory/teste_uart_fpga.hex"), 34 | .GPIO_WIDHT(8), 35 | .UART_BUFFER_SIZE(16) 36 | ) SOC( 37 | .clk(clk_o), 38 | .reset(reset_in), 39 | .leds(led), 40 | .rx(rx), 41 | .tx(tx), 42 | .gpios(gpio) 43 | ); 44 | 45 | always @(posedge clk) begin 46 | clk_o = ~clk_o; 47 | reset_bousing <= CPU_RESETN; 48 | end 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /software/compile_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | diretorio="code" 4 | march="rv32imzicsr" 5 | 6 | mkdir -p build 7 | 8 | # Verifica se o diretório existe 9 | if [ -d "$diretorio" ]; then 10 | # Loop pelos arquivos no diretório 11 | for arquivo in "$diretorio"/*; do 12 | # Verifica se é um arquivo regular 13 | if [ -f "$arquivo" ]; then 14 | echo "Compilando $arquivo" # Faça o que desejar com o arquivo 15 | nome_sem_extensao=$(basename "$arquivo" | sed 's/\.[^.]*$//') 16 | 17 | riscv32-unknown-elf-as -march=$march $arquivo -o build/$nome_sem_extensao.o 18 | riscv32-unknown-elf-ld build/$nome_sem_extensao.o -o build/$nome_sem_extensao.elf 19 | riscv32-unknown-elf-objcopy -O binary build/$nome_sem_extensao.elf build/$nome_sem_extensao.bin 20 | hexdump -v -e '1/4 "%08x" "\n"' build/$nome_sem_extensao.bin > memory/$nome_sem_extensao.hex 21 | 22 | echo "$arquivo compilado" # Faça o que desejar com o arquivo 23 | fi 24 | done 25 | else 26 | echo "O diretório não existe." 27 | fi 28 | -------------------------------------------------------------------------------- /software/code/teste_gpio_fpga.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | li s0, 0xC0000000 # GPIO base address 5 | li s1, 0x80000000 # UART base address 6 | li s2, 0 # gpio values 7 | 8 | li a0, 0x00000001 # GPIO 0 MASK 9 | li a1, 0x00000002 # GPIO 1 MASK 10 | li a2, 0x00000004 # GPIO 2 MASK 11 | li a3, 0x00000008 # GPIO 3 MASK 12 | li a4, 0x00000010 # GPIO 4 MASK 13 | li a5, 0x00000020 # GPIO 5 MASK 14 | li a6, 0x00000040 # GPIO 6 MASK 15 | li a7, 0x00000080 # GPIO 7 MASK 16 | 17 | li t0, 0x000000F0 # Direction for GPIO 0-3 as output and 4-7 as input 18 | 19 | sw t0, 0(s0) # Set direction for GPIO 0-3 as output and 4-7 as input 20 | 21 | or s2, s2, a0 # Set GPIO 0 high 22 | or s2, s2, a1 # Set GPIO 1 high 23 | or s2, s2, a2 # Set GPIO 2 high 24 | or s2, s2, a3 # Set GPIO 3 high 25 | 26 | sw s2, 4(s0) # Set GPIO 0-3 high 27 | 28 | #xor s2, s2, a0 # Set GPIO 0 low 29 | #xor s2, s2, a1 # Set GPIO 1 low 30 | #xor s2, s2, a2 # Set GPIO 2 low 31 | #xor s2, s2, a3 # Set GPIO 3 low 32 | 33 | sw s2, 4(s0) # Set GPIO 0-3 high 34 | -------------------------------------------------------------------------------- /fpga/digilent_arty/main.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input wire clk, 3 | input wire reset, 4 | input wire rx, 5 | output wire tx, 6 | output wire [3:0]led, 7 | //inout [5:0]gpios 8 | inout [13:0]ck_io 9 | ); 10 | 11 | wire reset_o, reset_in; 12 | wire [7:0] leds; 13 | reg clk_o, reset_bousing; 14 | 15 | assign led = ~leds[3:0]; 16 | assign reset_in = reset_o | reset_bousing; 17 | 18 | initial begin 19 | clk_o = 1'b0; 20 | reset_bousing = 1'b0; 21 | end 22 | 23 | 24 | ResetBootSystem #( 25 | .CYCLES(20) 26 | ) ResetBootSystem( 27 | .clk(clk_o), 28 | .reset_o(reset_o) 29 | ); 30 | 31 | Risco_5_SOC #( 32 | .CLOCK_FREQ(50000000), 33 | .BIT_RATE(115200), 34 | .MEMORY_SIZE(32772), 35 | .MEMORY_FILE("../../software/memory/fpga_test_2.hex"), 36 | .GPIO_WIDHT(8), 37 | .UART_BUFFER_SIZE(16) 38 | ) SOC( 39 | .clk(clk_o), 40 | .reset(reset_in), 41 | .leds(leds), 42 | .rx(rx), 43 | .tx(tx), 44 | .gpios(ck_io) 45 | ); 46 | 47 | always @(posedge clk) begin 48 | clk_o = ~clk_o; 49 | reset_bousing <= reset; 50 | end 51 | 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /debug/debug.v: -------------------------------------------------------------------------------- 1 | module Debug #( 2 | parameter INITIAL_ADDRESS = 32'h0000FFFF, 3 | parameter COUNTER_BITS = 32, 4 | parameter BUS_WIDHT = 32 5 | )( 6 | input wire clk, 7 | input wire reset, 8 | input wire tx, 9 | output wire rx, 10 | output wire clk_o, 11 | output reg [BUS_WIDHT - 1:0] output_a, 12 | output reg [BUS_WIDHT - 1:0] output_b, 13 | output reg [BUS_WIDHT - 1:0] output_c, 14 | output reg [BUS_WIDHT - 1:0] output_d, 15 | 16 | input wire [BUS_WIDHT - 1:0] input_y, 17 | input wire [BUS_WIDHT - 1:0] input_z 18 | ); 19 | 20 | reg option, out_enable, pulse; 21 | reg [COUNTER_BITS-1 : 0] divider; 22 | 23 | initial begin 24 | option = 1'b0; 25 | out_enable = 1'b0; 26 | pulse = 1'b0; 27 | divider = 32'h0; 28 | end 29 | 30 | ClkDivider #( 31 | .COUNTER_BITS(COUNTER_BITS) 32 | ) ClkDivider( 33 | .clk(clk), 34 | .reset(reset), 35 | .option(option), 36 | .out_enable(out_enable), 37 | .divider(divider), 38 | .pulse(pulse), 39 | .clk_o(clk_o) 40 | ); 41 | 42 | always @(posedge clk ) begin 43 | 44 | end 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /LICENSE-MIT: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2024 Julio Nunes Avelar 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /software/LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2024 Julio Nunes Avelar 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /fpga/tangnano20k/run.tcl: -------------------------------------------------------------------------------- 1 | set_device -name GW2AR-18C GW2AR-LV18QN88C8/I7 2 | add_file pinout.cst 3 | add_file top.sdc 4 | add_file main.v 5 | add_file ../../debug/reset.v 6 | add_file ../../src/core/alu_control.v 7 | add_file ../../src/core/alu.v 8 | add_file ../../src/core/control_unit.v 9 | add_file ../../src/core/core.v 10 | add_file ../../src/core/immediate_generator.v 11 | add_file ../../src/core/mux.v 12 | add_file ../../src/core/pc.v 13 | add_file ../../src/core/registers.v 14 | add_file ../../src/core/csr_unit.v 15 | add_file ../../src/core/mdu.v 16 | add_file ../../src/peripheral/bus.v 17 | add_file ../../src/peripheral/gpio.v 18 | add_file ../../src/peripheral/gpios.v 19 | add_file ../../src/peripheral/leds.v 20 | add_file ../../src/peripheral/memory.v 21 | add_file ../../src/peripheral/soc.v 22 | add_file ../../src/peripheral/uart_rx.v 23 | add_file ../../src/peripheral/uart_tx.v 24 | add_file ../../src/peripheral/uart.v 25 | add_file ../../src/peripheral/fifo.v 26 | add_file ../../src/peripheral/pwm.v 27 | 28 | set_option -use_mspi_as_gpio 1 29 | set_option -use_sspi_as_gpio 1 30 | set_option -use_ready_as_gpio 1 31 | set_option -use_done_as_gpio 1 32 | set_option -rw_check_on_ram 1 33 | run all -------------------------------------------------------------------------------- /fpga/digilent_arty/run.tcl: -------------------------------------------------------------------------------- 1 | read_verilog "main.v" 2 | read_verilog ../../debug/reset.v 3 | read_verilog ../../src/core/alu_control.v 4 | read_verilog ../../src/core/alu.v 5 | read_verilog ../../src/core/control_unit.v 6 | read_verilog ../../src/core/core.v 7 | read_verilog ../../src/core/immediate_generator.v 8 | read_verilog ../../src/core/mux.v 9 | read_verilog ../../src/core/pc.v 10 | read_verilog ../../src/core/registers.v 11 | read_verilog ../../src/core/csr_unit.v 12 | read_verilog ../../src/core/mdu.v 13 | read_verilog ../../src/peripheral/pwm.v 14 | read_verilog ../../src/peripheral/bus.v 15 | read_verilog ../../src/peripheral/gpio.v 16 | read_verilog ../../src/peripheral/gpios.v 17 | read_verilog ../../src/peripheral/leds.v 18 | read_verilog ../../src/peripheral/memory.v 19 | read_verilog ../../src/peripheral/soc.v 20 | read_verilog ../../src/peripheral/uart_rx.v 21 | read_verilog ../../src/peripheral/uart_tx.v 22 | read_verilog ../../src/peripheral/uart.v 23 | read_verilog ../../src/peripheral/fifo.v 24 | 25 | read_xdc "digilent_arty.xdc" 26 | 27 | # synth 28 | synth_design -top "top" -part "xc7a100tcsg324-1" 29 | 30 | # place and route 31 | opt_design 32 | place_design 33 | route_design 34 | 35 | # write bitstream 36 | write_bitstream -force "./build/out.bit" -------------------------------------------------------------------------------- /tests/clk_divider.v: -------------------------------------------------------------------------------- 1 | module clk_divider_tb (); 2 | 3 | parameter COUNTER_BITS = 32; 4 | parameter PULSE_BITS = 32; 5 | 6 | wire clk_o; 7 | reg option, out_enable, clk, reset, write_pulse; 8 | reg [COUNTER_BITS - 1 : 0] divider; 9 | reg [PULSE_BITS - 1 : 0] pulse; 10 | 11 | initial begin 12 | $dumpfile("build/clk_divider.vcd"); 13 | $dumpvars; 14 | 15 | clk = 0; 16 | reset = 0; 17 | option = 1'b0; 18 | out_enable = 1'b1; 19 | pulse = 32'd0; 20 | divider = 32'd0; 21 | write_pulse = 1'b0; 22 | 23 | #2 24 | reset = 1'b1; 25 | #2 26 | reset = 1'b0; 27 | 28 | #2 29 | 30 | out_enable = 1'b0; 31 | 32 | #2 33 | 34 | out_enable = 1'b1; 35 | 36 | #2 37 | 38 | pulse = 32'd8; 39 | 40 | #16 41 | 42 | write_pulse = 1'b1; 43 | 44 | #2 45 | 46 | write_pulse = 1'b0; 47 | 48 | #2 49 | 50 | 51 | #40 52 | 53 | $finish; 54 | end 55 | 56 | always #1 clk = ~clk; 57 | 58 | ClkDivider #( 59 | .COUNTER_BITS(COUNTER_BITS), 60 | .PULSE_BITS(PULSE_BITS) 61 | ) ClkDivider( 62 | .clk(clk), 63 | .reset(reset), 64 | .option(option), 65 | .write_pulse(write_pulse), 66 | .out_enable(out_enable), 67 | .divider(divider), 68 | .pulse(pulse), 69 | .clk_o(clk_o) 70 | ); 71 | 72 | endmodule -------------------------------------------------------------------------------- /software/code/teste_gpio_fpga2.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | li s0, 0xC0000000 # GPIO base address 5 | li s1, 0x80000000 # UART base address 6 | li s2, 0 # gpio values 7 | li s5, 1000 # delay value 8 | 9 | li a0, 0x00000001 # GPIO 0 MASK 10 | li a1, 0x00000002 # GPIO 1 MASK 11 | li a2, 0x00000004 # GPIO 2 MASK 12 | li a3, 0x00000008 # GPIO 3 MASK 13 | li a4, 0x00000010 # GPIO 4 MASK 14 | li a5, 0x00000020 # GPIO 5 MASK 15 | li a6, 0x00000040 # GPIO 6 MASK 16 | li a7, 0x00000080 # GPIO 7 MASK 17 | 18 | li t0, 0x000000F0 # Direction for GPIO 0-3 as output and 4-7 as input 19 | 20 | sw t0, 0(s0) # Set direction for GPIO 0-3 as output and 4-7 as input 21 | 22 | or s2, s2, a0 # Set GPIO 0 high 23 | or s2, s2, a1 # Set GPIO 1 high 24 | or s2, s2, a2 # Set GPIO 2 high 25 | or s2, s2, a3 # Set GPIO 3 high 26 | 27 | sw s2, 4(s0) # Set GPIO 0-3 high 28 | 29 | loop: 30 | lw t1, 0(s0) # Read GPIO 4-7 31 | 32 | # shift left 33 | slli t1, t1, 4 34 | 35 | sw t1, 4(s0) # Write GPIO 0-3 36 | 37 | call delay; 38 | 39 | j loop; 40 | 41 | delay: 42 | li t2, 0; 43 | delay_loop: 44 | addi t2, t2, 1; 45 | 46 | beq t2, s5, fim; # if t1 == s5 fim 47 | 48 | j delay_loop; # jump to delay 49 | 50 | fim: 51 | ret 52 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.fs 2 | impl/ 3 | x.* 4 | build/ 5 | rascunho.v 6 | fpga/digilent_arty/vivado_131673.backup.jou 7 | fpga/digilent_arty/vivado_131673.backup.log 8 | fpga/digilent_arty/vivado.jou 9 | fpga/digilent_arty/vivado.log 10 | fpga/digilent_arty/digilent_arty_timing_synth.rpt 11 | fpga/digilent_arty/digilent_arty_route.dcp 12 | fpga/digilent_arty/clockInfo.txt 13 | fpga/digilent_arty/digilent_arty_place.dcp 14 | env/ 15 | fpga/digilent_arty/tight_setup_hold_pins.txt 16 | fpga/nexys4_ddr/clockInfo.txt 17 | fpga/nexys4_ddr/digilent_nexys4ddr_utilization_place.rpt 18 | fpga/nexys4_ddr/digilent_nexys4ddr_utilization_hierarchical_place.rpt 19 | fpga/nexys4_ddr/digilent_nexys4ddr_io.rpt 20 | fpga/nexys4_ddr/digilent_nexys4ddr_control_sets.rpt 21 | fpga/nexys4_ddr/digilent_nexys4ddr_clock_utilization.rpt 22 | fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt 23 | fpga/nexys4_ddr/digilent_nexys4ddr_power.rpt 24 | fpga/nexys4_ddr/digilent_nexys4ddr_route_status.rpt 25 | fpga/nexys4_ddr/digilent_nexys4ddr_timing.rpt 26 | site/ 27 | fpga/xilinx_vc709/usage_statistics_webtalk.xml 28 | fpga/xilinx_vc709/usage_statistics_webtalk.html 29 | fpga/xilinx_vc709/tight_setup_hold_pins.txt 30 | fpga/xilinx_vc709/webtalk.log 31 | fpga/xilinx_vc709/webtalk.jou 32 | *.backup.log 33 | *.backup.jou 34 | rascunho/ 35 | .vscode/settings.json 36 | fpga/de1soc/c5_pin_model_dump.txt 37 | -------------------------------------------------------------------------------- /software/code/fpga_test_4.S: -------------------------------------------------------------------------------- 1 | 2 | .global _start 3 | 4 | _start: 5 | li s0, 0x80000000 # endereço da UART 6 | li s1, 0x40000000; # endereço dos leds 7 | 8 | li s2, 74 # 'J' 9 | 10 | li t0, 0; 11 | li t1, 0; 12 | li t3, 0; 13 | 14 | li s3, 255; # Numero a ser contado nos leds 15 | li s4, 2; # numero de vezes que precisa contar para mandar algo na uart 16 | li s5, 800000; # delay 17 | 18 | loop: 19 | addi t0, t0, 5; # incrementa t0 20 | 21 | sw t0, 0(s1) 22 | 23 | call delay; # call delay 24 | 25 | bge t0, s3, reset; # if t0 == s3 reset 26 | 27 | j loop; # jump to loop 28 | 29 | delay: 30 | li t1, 0; 31 | delay_loop: 32 | addi t1, t1, 1; 33 | 34 | beq t1, s5, fim; # if t1 == s5 fim 35 | 36 | j delay_loop; # jump to delay 37 | 38 | fim: 39 | ret 40 | 41 | reset: 42 | #addi t3, t3, 1; 43 | li t0, 0; 44 | 45 | sw s3, 0(s1); 46 | 47 | #beq t3, s4, send_uart; # if t3 == s4 send_uart 48 | j send_uart; 49 | 50 | call delay; # call loop 51 | 52 | j loop; # jump to loop 53 | 54 | send_uart: 55 | li t3, 0; 56 | 57 | sw s2, 0(s0); 58 | 59 | call delay; 60 | 61 | lw t4, 4(s0); 62 | 63 | beqz t4, read_uart; 64 | 65 | j loop; 66 | 67 | read_uart: 68 | lw s2, 0(s0); 69 | 70 | sw s2, 0(s4); 71 | 72 | j loop; 73 | -------------------------------------------------------------------------------- /src/peripheral/fifo.v: -------------------------------------------------------------------------------- 1 | `include "config.vh" 2 | `ifdef UART_ENABLE 3 | 4 | module FIFO #( 5 | parameter DEPTH = 8, 6 | parameter WIDTH = 8 7 | ) ( 8 | input wire clk, 9 | input wire reset, 10 | input wire write, 11 | input wire read, 12 | input wire [WIDTH-1:0] write_data, 13 | output wire full, 14 | output wire empty, 15 | output wire [WIDTH-1:0] read_data 16 | ); 17 | 18 | reg [5:0] counter; 19 | reg [WIDTH-1:0] memory[DEPTH-1:0]; 20 | reg [5:0] read_ptr; 21 | reg [5:0] write_ptr; 22 | 23 | assign read_data = memory[read_ptr]; 24 | 25 | initial begin 26 | counter = 6'd0; 27 | read_ptr = 6'd0; 28 | write_ptr = 6'd0; 29 | end 30 | 31 | always @(posedge clk) begin 32 | if(reset == 1'b1) begin 33 | counter <= 6'd0; 34 | read_ptr <= 6'd0; 35 | write_ptr <= 6'd0; 36 | end else begin 37 | if (write && full == 1'b0) begin 38 | counter <= counter + 1'b1; 39 | memory[write_ptr] <= write_data; 40 | write_ptr <= (write_ptr == DEPTH-1) ? 6'd0 : write_ptr + 1'b1; 41 | end else if (read && empty == 1'b0) begin 42 | counter <= counter - 1'b1; 43 | read_ptr <= (read_ptr == DEPTH-1) ? 'd0 : read_ptr + 1'b1; 44 | end 45 | end 46 | end 47 | 48 | assign full = (counter == DEPTH) ? 1'b1 : 1'b0; 49 | assign empty = (counter == 0) ? 1'b1 : 1'b0; 50 | 51 | endmodule 52 | 53 | `endif -------------------------------------------------------------------------------- /fpga/de1soc/de1soc.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2024 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition 22 | # Date created = 15:54:56 July 30, 2024 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "23.1" 27 | DATE = "15:54:56 July 30, 2024" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "de1soc" 32 | -------------------------------------------------------------------------------- /.github/workflows/static.yml: -------------------------------------------------------------------------------- 1 | # Simple workflow for deploying static content to GitHub Pages 2 | name: Deploy static content to Pages 3 | 4 | on: 5 | # Runs on pushes targeting the default branch 6 | push: 7 | branches: ["gh-pages"] 8 | 9 | # Allows you to run this workflow manually from the Actions tab 10 | workflow_dispatch: 11 | 12 | # Sets permissions of the GITHUB_TOKEN to allow deployment to GitHub Pages 13 | permissions: 14 | contents: read 15 | pages: write 16 | id-token: write 17 | 18 | # Allow only one concurrent deployment, skipping runs queued between the run in-progress and latest queued. 19 | # However, do NOT cancel in-progress runs as we want to allow these production deployments to complete. 20 | concurrency: 21 | group: "pages" 22 | cancel-in-progress: false 23 | 24 | jobs: 25 | # Single deploy job since we're just deploying 26 | deploy: 27 | environment: 28 | name: github-pages 29 | url: ${{ steps.deployment.outputs.page_url }} 30 | runs-on: ubuntu-latest 31 | steps: 32 | - name: Checkout 33 | uses: actions/checkout@v4 34 | - name: Setup Pages 35 | uses: actions/configure-pages@v4 36 | - name: Upload artifact 37 | uses: actions/upload-pages-artifact@v3 38 | with: 39 | # Upload entire repository 40 | path: 'docs/risco5-docs/site' 41 | - name: Deploy to GitHub Pages 42 | id: deployment 43 | uses: actions/deploy-pages@v4 44 | -------------------------------------------------------------------------------- /software/code/fpga_test_3.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | 3 | _start: 4 | li a5, 63; 5 | 6 | call gera_endereco; 7 | call gera_endereco_uart; 8 | 9 | #Valor todos os leds acessos 10 | li s4, 255; 11 | # valor final do loop 12 | li s3, 2000; 13 | add s3, s3, s3; 14 | 15 | slli s3, s3, 8; 16 | 17 | li a6, 0; 18 | li a7, 5; 19 | 20 | j reset; 21 | 22 | gera_endereco: 23 | # Calcula o endereço dos leds 24 | li a4, 0x40000000; 25 | ret; 26 | 27 | gera_endereco_uart: 28 | # Calcula o endereço da UART 29 | li a2, 0x80000000; 30 | ret; 31 | 32 | send_uart_data: 33 | # Envia dados pela uart 34 | li t1, 74; 35 | sw t1, 0(a2) 36 | 37 | ret; 38 | 39 | show_all: 40 | sw s4, 0(a4); 41 | li a6, 0; 42 | 43 | call delay; 44 | call delay; 45 | call delay; 46 | 47 | call loop; 48 | 49 | reset: 50 | add a3, zero, zero; 51 | addi a6, a6, 1; 52 | 53 | call send_uart_data; 54 | 55 | beq a6, a7, show_all; 56 | 57 | call loop; 58 | 59 | count: 60 | addi t0, t0, 1; 61 | 62 | blt t0, s3, count; 63 | 64 | ret; 65 | 66 | delay: 67 | mv s2, ra; 68 | li t0, 0; 69 | 70 | call count; 71 | 72 | mv ra, s2; 73 | 74 | ret; 75 | 76 | loop: 77 | addi a3, a3, 1; # a3 = a3 + 1 78 | sw a3, 0(a4) 79 | call delay 80 | 81 | beq a3, a5, fim; # if a2 == a3 then fim 82 | call loop; 83 | 84 | fim: 85 | call reset; 86 | -------------------------------------------------------------------------------- /debug/reset.v: -------------------------------------------------------------------------------- 1 | module ResetBootSystem #( 2 | parameter CYCLES = 20 3 | ) ( 4 | input wire clk, 5 | output reg reset_o, 6 | output wire resetn_o 7 | ); 8 | 9 | assign resetn_o = ~reset_o; 10 | 11 | reg [1:0] state; 12 | reg [5:0] counter; 13 | 14 | localparam INIT = 2'b00; 15 | localparam RESET_COUNTER = 2'b01; 16 | localparam IDLE = 2'b10; 17 | 18 | initial begin 19 | state = 2'b01; 20 | reset_o = 2'b0; 21 | counter = 6'h00; 22 | end 23 | 24 | always @(posedge clk ) begin 25 | case (state) 26 | INIT: begin 27 | reset_o <= 1'b1; 28 | state <= RESET_COUNTER; 29 | counter <= 6'h00; 30 | end 31 | 32 | RESET_COUNTER: begin 33 | if(reset_o == 1'b0) begin 34 | state <= INIT; 35 | end else begin 36 | if(counter < CYCLES) begin 37 | counter <= counter + 1; 38 | end else if(counter == CYCLES) begin 39 | counter <= 0; 40 | state <= IDLE; 41 | end else begin 42 | state <= INIT; 43 | end 44 | end 45 | end 46 | 47 | IDLE: begin 48 | if(counter != 0) begin 49 | state <= INIT; 50 | end else begin 51 | reset_o <= 1'b0; 52 | end 53 | end 54 | 55 | default: state <= INIT; 56 | endcase 57 | end 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /fpga/cyclone10gx/cyclone10_gx.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2024 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the Intel FPGA Software License Subscription Agreements 16 | # on the Quartus Prime software download page. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 24.1.0 Build 115 03/21/2024 SC Pro Edition 22 | # Date created = 11:07:47 June 18, 2024 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "24.1" 27 | DATE = "11:07:47 June 18, 2024" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "cyclone10_gx" 32 | -------------------------------------------------------------------------------- /tests/gpio_test.v: -------------------------------------------------------------------------------- 1 | module gpio_tb (); 2 | 3 | reg clk, reset, read, write, 4 | pin1, pin2, pin3; 5 | wire [4:0] gpios; 6 | reg [31:0] address, write_data; 7 | wire [31:0] read_data; 8 | 9 | always #1 clk = ~clk; 10 | 11 | GPIOS #( 12 | .WIDHT(5) 13 | ) GPIOS( 14 | .clk(clk), 15 | .reset(reset), 16 | .read(read), 17 | .write(write), 18 | .address(address), 19 | .write_data(write_data), 20 | .read_data(read_data), 21 | .gpio(gpios) 22 | ); 23 | 24 | assign gpios[4] = pin3; 25 | assign gpios[2] = pin2; 26 | assign gpios[0] = pin1; 27 | 28 | initial begin 29 | $dumpfile("build/gpio.vcd"); 30 | $dumpvars; 31 | 32 | clk = 1'b0; 33 | reset = 1'b1; 34 | address = 32'h00000000; 35 | write_data = 32'h00000000; 36 | pin1 = 1'b0; 37 | pin2 = 1'b0; 38 | pin3 = 1'b0; 39 | write = 1'b0; 40 | read = 1'b0; 41 | 42 | #5 43 | 44 | reset = 1'b0; 45 | 46 | #2 47 | 48 | write_data = 32'b00000000000000000000000000010101; 49 | write = 1'b1; 50 | 51 | #2 52 | write = 1'b0; 53 | 54 | #4 55 | 56 | write_data = 32'b10000000000000000000000000011111; 57 | write = 1'b1; 58 | 59 | #2 60 | 61 | write = 1'b0; 62 | 63 | #4 64 | 65 | pin1 = 1'b1; 66 | pin3 = 1'b1; 67 | 68 | #2 69 | 70 | write_data = 32'b10000000000000000000000000000000; 71 | write = 1'b1; 72 | 73 | #2 74 | 75 | write = 1'b0; 76 | 77 | #4 78 | 79 | $finish; 80 | end 81 | 82 | endmodule 83 | -------------------------------------------------------------------------------- /fpga/colorlight_i9/pinout.lpf: -------------------------------------------------------------------------------- 1 | LOCATE COMP "rx" SITE "H18"; 2 | IOBUF PORT "rx" IO_TYPE=LVCMOS33; 3 | 4 | LOCATE COMP "tx" SITE "J17"; 5 | IOBUF PORT "tx" IO_TYPE=LVCMOS33; 6 | 7 | LOCATE COMP "reset" SITE "H4"; 8 | IOBUF PORT "reset" IO_TYPE=LVCMOS33; 9 | 10 | LOCATE COMP "led[7]" SITE "J16"; 11 | IOBUF PORT "led[7]" IO_TYPE=LVCMOS33; 12 | 13 | LOCATE COMP "led[6]" SITE "L5"; 14 | IOBUF PORT "led[6]" IO_TYPE=LVCMOS33; 15 | 16 | LOCATE COMP "led[5]" SITE "M4"; 17 | IOBUF PORT "led[5]" IO_TYPE=LVCMOS33; 18 | 19 | LOCATE COMP "led[4]" SITE "R3"; 20 | IOBUF PORT "led[4]" IO_TYPE=LVCMOS33; 21 | 22 | LOCATE COMP "led[3]" SITE "J18"; 23 | IOBUF PORT "led[3]" IO_TYPE=LVCMOS33; 24 | 25 | LOCATE COMP "led[2]" SITE "P16"; 26 | IOBUF PORT "led[2]" IO_TYPE=LVCMOS33; 27 | 28 | LOCATE COMP "led[1]" SITE "L4"; 29 | IOBUF PORT "led[1]" IO_TYPE=LVCMOS33; 30 | 31 | LOCATE COMP "led[0]" SITE "N4"; 32 | IOBUF PORT "led[0]" IO_TYPE=LVCMOS33; 33 | 34 | LOCATE COMP "gpios[0]" SITE "R1"; 35 | IOBUF PORT "gpios[0]" IO_TYPE=LVCMOS33; 36 | 37 | LOCATE COMP "gpios[1]" SITE "U1"; 38 | IOBUF PORT "gpios[1]" IO_TYPE=LVCMOS33; 39 | 40 | LOCATE COMP "gpios[2]" SITE "W1"; 41 | IOBUF PORT "gpios[2]" IO_TYPE=LVCMOS33; 42 | 43 | LOCATE COMP "gpios[3]" SITE "M1"; 44 | IOBUF PORT "gpios[3]" IO_TYPE=LVCMOS33; 45 | 46 | LOCATE COMP "gpios[4]" SITE "T1"; 47 | IOBUF PORT "gpios[4]" IO_TYPE=LVCMOS33; 48 | 49 | LOCATE COMP "gpios[5]" SITE "Y2"; 50 | IOBUF PORT "gpios[5]" IO_TYPE=LVCMOS33; 51 | 52 | LOCATE COMP "clk" SITE "P3"; 53 | IOBUF PORT "clk" IO_TYPE=LVCMOS33; 54 | FREQUENCY PORT "clk" 25.0 MHz; 55 | -------------------------------------------------------------------------------- /fpga/xilinx_vc709/main.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module top( 4 | input wire clk_ref_p, 5 | input wire clk_ref_n, 6 | input wire button_center, 7 | input wire RxD, 8 | output wire TxD, 9 | inout [7:0] gpio_switch, 10 | output wire [7:0]led 11 | ); 12 | 13 | wire reset_o, reset_in; 14 | reg clk_o, reset_bousing; 15 | 16 | assign reset_in = reset_o | reset_bousing; 17 | 18 | initial begin 19 | clk_o = 1'b0; 20 | reset_bousing = 1'b0; 21 | end 22 | 23 | 24 | wire clk_ref; // Sinal de clock single-ended 25 | 26 | // Instância do buffer diferencial 27 | IBUFDS #( 28 | .DIFF_TERM("FALSE"), // Habilita ou desabilita o terminador diferencial 29 | .IBUF_LOW_PWR("TRUE"), // Ativa o modo de baixa potência 30 | .IOSTANDARD("DIFF_SSTL15") 31 | ) ibufds_inst ( 32 | .O(clk_ref), // Clock single-ended de saída 33 | .I(clk_ref_p), // Entrada diferencial positiva 34 | .IB(clk_ref_n) // Entrada diferencial negativa 35 | ); 36 | 37 | ResetBootSystem #( 38 | .CYCLES(20) 39 | ) ResetBootSystem( 40 | .clk(clk_o), 41 | .reset_o(reset_o) 42 | ); 43 | 44 | Risco_5_SOC #( 45 | .CLOCK_FREQ(100000000), 46 | .BIT_RATE(115200), 47 | .MEMORY_SIZE(8192), 48 | .MEMORY_FILE("../../software/memory/fpga_test_2.hex"), 49 | .GPIO_WIDHT(8), 50 | .UART_BUFFER_SIZE(16) 51 | ) SOC( 52 | .clk(clk_o), 53 | .reset(reset_in), 54 | .leds(led), 55 | .rx(RxD), 56 | .tx(TxD), 57 | .gpios() 58 | ); 59 | 60 | always @(posedge clk_ref) begin 61 | clk_o = ~clk_o; 62 | reset_bousing <= button_center; 63 | end 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /tests/registers_test.v: -------------------------------------------------------------------------------- 1 | module registers_tb (); 2 | 3 | wire [31:0] read_data_1, read_data_2; 4 | reg [31:0] write_data; 5 | reg [4:0] read_reg_1, read_reg_2, write_reg; 6 | reg clk, reg_write; 7 | integer i; 8 | 9 | always #1 clk = ~clk; 10 | 11 | Registers Registers( 12 | .clk(clk), 13 | .regWrite(reg_write), 14 | .writeData(write_data), 15 | .readData1(read_data_1), 16 | .readData2(read_data_2), 17 | .writeRegister(write_reg), 18 | .readRegister1(read_reg_1), 19 | .readRegister2(read_reg_2) 20 | ); 21 | 22 | initial begin 23 | $dumpfile("build/registers.vcd"); 24 | $dumpvars; 25 | 26 | clk = 0; 27 | read_reg_1 = 0; 28 | read_reg_2 = 32'h1; 29 | 30 | #2 31 | 32 | $display("lendo estado inicial de dois registradores"); 33 | 34 | if(read_data_1 == 32'h00000000) begin 35 | $display("reg 1 correto"); 36 | end 37 | 38 | if(read_data_2 == 32'h00000000) begin 39 | $display("reg 2 correto"); 40 | end 41 | 42 | $display("Escrevendo nos registradores"); 43 | 44 | for(i = 0; i < 32; i = i + 1) begin 45 | write_reg = i; 46 | write_data = i; 47 | 48 | #1 49 | 50 | reg_write = 1'b1; 51 | 52 | #1 53 | 54 | reg_write = 1'b0; 55 | end 56 | 57 | $display("Lendo registradores"); 58 | 59 | for(i = 0; i < 32; i = i + 1) begin 60 | read_reg_1 = i; 61 | 62 | #1 63 | 64 | if(read_data_1 == i) begin 65 | $display("Resultado %d correto", i); 66 | end else begin 67 | $display("Resultado %d incorreto", i); 68 | end 69 | end 70 | 71 | $finish; 72 | end 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /fpga/xilinx_vc709/run.tcl: -------------------------------------------------------------------------------- 1 | read_verilog "main.v" 2 | read_verilog ../../debug/reset.v 3 | read_verilog ../../src/core/alu_control.v 4 | read_verilog ../../src/core/alu.v 5 | read_verilog ../../src/core/control_unit.v 6 | read_verilog ../../src/core/core.v 7 | read_verilog ../../src/core/immediate_generator.v 8 | read_verilog ../../src/core/mux.v 9 | read_verilog ../../src/core/pc.v 10 | read_verilog ../../src/core/registers.v 11 | read_verilog ../../src/core/csr_unit.v 12 | read_verilog ../../src/core/mdu.v 13 | read_verilog ../../src/peripheral/bus.v 14 | read_verilog ../../src/peripheral/gpio.v 15 | read_verilog ../../src/peripheral/gpios.v 16 | read_verilog ../../src/peripheral/leds.v 17 | read_verilog ../../src/peripheral/memory.v 18 | read_verilog ../../src/peripheral/soc.v 19 | read_verilog ../../src/peripheral/uart_rx.v 20 | read_verilog ../../src/peripheral/uart_tx.v 21 | read_verilog ../../src/peripheral/uart.v 22 | read_verilog ../../src/peripheral/fifo.v 23 | read_verilog ../../src/peripheral/pwm.v 24 | 25 | read_xdc "pinout.xdc" 26 | set_property PROCESSING_ORDER EARLY [get_files pinout.xdc] 27 | 28 | # synth 29 | synth_design -top "top" -part "xc7vx690tffg1761-2" 30 | 31 | # place and route 32 | opt_design 33 | place_design 34 | 35 | report_utilization -hierarchical -file virtex_utilization_hierarchical_place.rpt 36 | report_utilization -file virtex_utilization_place.rpt 37 | report_io -file virtex_io.rpt 38 | report_control_sets -verbose -file virtex_control_sets.rpt 39 | report_clock_utilization -file virtex_clock_utilization.rpt 40 | 41 | route_design 42 | 43 | report_timing_summary -no_header -no_detailed_paths 44 | report_route_status -file virtex_route_status.rpt 45 | report_drc -file virtex_drc.rpt 46 | report_timing_summary -datasheet -max_paths 10 -file virtex_timing.rpt 47 | report_power -file virtex_power.rpt 48 | 49 | # write bitstream 50 | write_bitstream -force "./build/out.bit" 51 | 52 | exit -------------------------------------------------------------------------------- /docs/mkdocs.yml: -------------------------------------------------------------------------------- 1 | site_name: Risco 5 2 | site_author: Julio Nunes Avelar 3 | site_description: Multi-cycle RISC-V processor with RV32I[M] implementation, built during a few days off. 4 | repo_name: Risco-5 5 | repo_url: https://github.com/JN513/Risco-5 6 | site_url: https://jn513.github.io/Risco-5/ 7 | copyright: CC BY-SA 4.0 - Julio Nunes Avelar 8 | nav: 9 | - Home: index.md 10 | - Get Started: get_started.md 11 | - Core: core.md 12 | - SoC: soc.md 13 | - About: about.md 14 | - Contributing: contributing.md 15 | theme: 16 | name: material 17 | #language: pt-BR 18 | logo: imgs/risco5.jpeg 19 | favicon: imgs/risco5.jpeg 20 | highlightjs: true 21 | features: 22 | - toc.integrate 23 | - navigation.tabs 24 | - navigation.expand 25 | #- navigation.instant 26 | #- navigation.instant.progress 27 | - content.code.copy 28 | - content.code.select 29 | palette: 30 | # Palette toggle for light mode 31 | - media: "(prefers-color-scheme: light)" 32 | scheme: default 33 | toggle: 34 | icon: material/brightness-7 35 | name: Switch to dark mode 36 | 37 | # Palette toggle for dark mode 38 | - media: "(prefers-color-scheme: dark)" 39 | scheme: slate 40 | primary: black 41 | toggle: 42 | icon: material/brightness-4 43 | name: Switch to light mode 44 | plugins: 45 | #- pdf-export 46 | #- offline 47 | - search: 48 | lang: 49 | - en 50 | - pt 51 | - i18n: 52 | languages: 53 | - locale: pt 54 | name: Português 55 | default: true 56 | - locale: en 57 | name: English 58 | extra: 59 | social: 60 | - icon: fontawesome/brands/gitlab 61 | link: https://gitlab.com/jn513 62 | - icon: fontawesome/brands/github 63 | link: https://github.com/JN513/Risco-5 64 | 65 | markdown_extensions: 66 | - attr_list 67 | - md_in_html -------------------------------------------------------------------------------- /fpga/nexys4_ddr/run.tcl: -------------------------------------------------------------------------------- 1 | read_verilog "main.v" 2 | read_verilog ../../debug/reset.v 3 | read_verilog ../../src/core/alu_control.v 4 | read_verilog ../../src/core/alu.v 5 | read_verilog ../../src/core/control_unit.v 6 | read_verilog ../../src/core/core.v 7 | read_verilog ../../src/core/immediate_generator.v 8 | read_verilog ../../src/core/mux.v 9 | read_verilog ../../src/core/pc.v 10 | read_verilog ../../src/core/registers.v 11 | read_verilog ../../src/core/csr_unit.v 12 | read_verilog ../../src/core/mdu.v 13 | read_verilog ../../src/peripheral/bus.v 14 | read_verilog ../../src/peripheral/gpio.v 15 | read_verilog ../../src/peripheral/gpios.v 16 | read_verilog ../../src/peripheral/leds.v 17 | read_verilog ../../src/peripheral/memory.v 18 | read_verilog ../../src/peripheral/soc.v 19 | read_verilog ../../src/peripheral/uart_rx.v 20 | read_verilog ../../src/peripheral/uart_tx.v 21 | read_verilog ../../src/peripheral/uart.v 22 | read_verilog ../../src/peripheral/fifo.v 23 | read_verilog ../../src/peripheral/pwm.v 24 | 25 | read_xdc "digilent_nexys4_ddr.xdc" 26 | set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4_ddr.xdc] 27 | 28 | # synth 29 | synth_design -top "top" -part "xc7a100tcsg324-1" 30 | 31 | # place and route 32 | opt_design 33 | place_design 34 | 35 | report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt 36 | report_utilization -file digilent_nexys4ddr_utilization_place.rpt 37 | report_io -file digilent_nexys4ddr_io.rpt 38 | report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt 39 | report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt 40 | 41 | route_design 42 | 43 | report_timing_summary -no_header -no_detailed_paths 44 | report_route_status -file digilent_nexys4ddr_route_status.rpt 45 | report_drc -file digilent_nexys4ddr_drc.rpt 46 | report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt 47 | report_power -file digilent_nexys4ddr_power.rpt 48 | 49 | # write bitstream 50 | write_bitstream -force "./build/out.bit" -------------------------------------------------------------------------------- /tests/core_test.v: -------------------------------------------------------------------------------- 1 | module core_tb(); 2 | 3 | reg clk, reset; 4 | wire memory_read, memory_write, slave_read, slave_write, 5 | slave1_read, slave1_write; 6 | wire [31:0] address, write_data, read_data, 7 | slave_address, slave_write_data, slave_read_data, 8 | slave1_address, slave1_write_data, slave1_read_data; 9 | 10 | always #1 clk = ~clk; 11 | 12 | Core #( 13 | .BOOT_ADDRESS(32'h00000000) 14 | ) Core( 15 | .clk(clk), 16 | .reset(reset), 17 | .memory_read(memory_read), 18 | .memory_write(memory_write), 19 | .write_data(write_data), 20 | .read_data(read_data), 21 | .address(address) 22 | ); 23 | 24 | Memory #( 25 | .MEMORY_FILE("software/memory/lw.hex"), 26 | .MEMORY_SIZE(4096) 27 | ) Memory( 28 | .clk(clk), 29 | .reset(reset), 30 | .memory_read(slave_read), 31 | .memory_write(slave_write), 32 | .write_data(slave_write_data), 33 | .read_data(slave_read_data), 34 | .address(slave_address) 35 | ); 36 | 37 | BUS Bus( 38 | .read(memory_read), 39 | .write(memory_write), 40 | .write_data(write_data), 41 | .read_data(read_data), 42 | .address(address), 43 | 44 | .slave_0_read(slave_read), 45 | .slave_0_write(slave_write), 46 | .slave_0_read_data(slave_read_data), 47 | .slave_0_address(slave_address), 48 | .slave_0_write_data(slave_write_data), 49 | 50 | .slave_1_read(slave1_read), 51 | .slave_1_write(slave1_write), 52 | .slave_1_read_data(slave1_read_data), 53 | .slave_1_address(slave1_address), 54 | .slave_1_write_data(slave1_write_data) 55 | ); 56 | 57 | LEDs Leds( 58 | .clk(clk), 59 | .reset(reset), 60 | .read(slave1_read), 61 | .write(slave1_write), 62 | .write_data(slave1_write_data), 63 | .read_data(slave1_read_data), 64 | .address(slave1_address) 65 | ); 66 | 67 | initial begin 68 | $dumpfile("build/core.vcd"); 69 | $dumpvars; 70 | 71 | clk = 1'b0; 72 | reset = 1'b1; 73 | #6 74 | reset = 1'b0; 75 | #120 76 | 77 | $finish; 78 | end 79 | 80 | endmodule 81 | -------------------------------------------------------------------------------- /src/peripheral/memory.v: -------------------------------------------------------------------------------- 1 | module Memory #( 2 | parameter MEMORY_FILE = "", 3 | parameter MEMORY_SIZE = 4096 4 | )( 5 | input wire clk, 6 | input wire reset, 7 | input wire memory_read, 8 | input wire memory_write, 9 | input wire [2:0] option, 10 | input wire [31:0] address, 11 | input wire [31:0] write_data, 12 | output reg memory_response, 13 | output reg [31:0] read_data 14 | ); 15 | 16 | reg [31:0] memory [(MEMORY_SIZE/4)-1: 0]; 17 | wire [31:0] buffer; 18 | `ifdef __ICARUS__ 19 | integer i; 20 | `endif 21 | 22 | //assign memory_response = memory_read | memory_write; 23 | 24 | assign buffer = memory[{2'b00, address[31:2]}]; 25 | 26 | initial begin 27 | memory_response = 1'b0; 28 | `ifdef __ICARUS__ 29 | for (i = 0; i < (MEMORY_SIZE/4)-1; i = i + 1) begin 30 | memory[i] = 32'h00000000; 31 | end 32 | `endif 33 | 34 | if(MEMORY_FILE != "") begin 35 | $readmemh(MEMORY_FILE, memory, 0, (MEMORY_SIZE/4) - 1); 36 | end 37 | end 38 | 39 | always @(posedge clk ) begin 40 | memory_response <= 1'b0; 41 | 42 | if(memory_read | memory_write) begin 43 | memory_response <= 1'b1; 44 | end 45 | end 46 | 47 | always @(posedge clk) begin 48 | if(memory_write == 1'b1) begin 49 | if(option[0] == 1'b1) begin 50 | memory[{2'b00, address[31:2]}] <= {buffer[31:16], write_data[15:0]}; 51 | end else if(option[1] == 1'b1) begin 52 | memory[{2'b00, address[31:2]}] <= write_data; 53 | end else begin 54 | memory[{2'b00, address[31:2]}] <= {buffer[31:8], write_data[7:0]};; 55 | end 56 | end 57 | end 58 | 59 | always @(*) begin 60 | case (option) 61 | 3'b000: read_data = {{24{buffer[7]}}, buffer[7:0]}; 62 | 3'b001: read_data = {{16{buffer[15]}}, buffer[15:0]}; 63 | 3'b100: read_data = {24'h000000 ,buffer[7:0]}; 64 | 3'b101: read_data = {16'h0000 ,buffer[15:0]}; 65 | 3'b010: read_data = buffer; 66 | default: read_data = buffer; 67 | endcase 68 | end 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /fpga/tangnano20k/tangnano20k.gprj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 5 6 | gw2ar18c-011 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /software/firmware/Makefile: -------------------------------------------------------------------------------- 1 | # header file path: ./lib/risco5.h 2 | # src file path: ./src/risco5.c 3 | # main file path: ./main.c 4 | # makefile path: ./Makefile 5 | 6 | # make order: .C -> .S -> .o -> .elf -> .bin -> .hex 7 | 8 | # makefile 9 | # 1. define the compiler and the flags 10 | # 2. define the source files 11 | # 3. define the object files 12 | # 4. define the target file 13 | # 5. define the rules to make the target file 14 | 15 | COMPILER=riscv32-unknown-elf- 16 | 17 | CC=$(COMPILER)gcc 18 | AS=$(COMPILER)as 19 | LD=$(COMPILER)ld 20 | OBJCOPY=$(COMPILER)objcopy 21 | HEXDUMP=hexdump 22 | OBJDUMP=$(COMPILER)objdump 23 | MARCH=rv32imzicsr 24 | 25 | all: buildFolder build/program.hex 26 | 27 | build/program.hex: build/program.bin 28 | $(HEXDUMP) -v -e '1/4 "%08x\n"' build/program.bin > build/program.hex 29 | 30 | build/program.bin: build/program.s 31 | $(OBJCOPY) -O binary build/program.elf build/program.bin 32 | 33 | build/program.s: build/program.elf 34 | $(OBJDUMP) -d build/program.elf > build/program.s 35 | 36 | build/program.elf: build/main.o build/risco5_lib.o build/uart.o build/gpio.o build/conversion.o build/pwm.o 37 | $(LD) -o build/program.elf build/risco5_lib.o build/uart.o build/conversion.o build/pwm.o build/gpio.o build/main.o -T utils/link.ld 38 | 39 | build/main.o: main.c 40 | $(CC) -march=$(MARCH) -mabi=ilp32 -Wall -c main.c -o build/main.o \ 41 | -nostartfiles -nostdinc -nostdlib -mstrict-align 42 | 43 | build/pwm.o: src/pwm.c 44 | $(CC) -march=$(MARCH) -mabi=ilp32 -Wall -c src/pwm.c -o build/pwm.o \ 45 | -nostartfiles -nostdinc -nostdlib -mstrict-align 46 | 47 | build/risco5_lib.o: src/risco5_lib.s 48 | $(AS) -march=$(MARCH) -mabi=ilp32 src/risco5_lib.s -o build/risco5_lib.o 49 | 50 | build/uart.o: src/uart.s 51 | $(AS) -march=$(MARCH) -mabi=ilp32 src/uart.s -o build/uart.o 52 | 53 | build/gpio.o: src/gpio.s 54 | $(AS) -march=$(MARCH) -mabi=ilp32 src/gpio.s -o build/gpio.o 55 | 56 | build/conversion.o: src/conversion.s 57 | $(AS) -march=$(MARCH) -mabi=ilp32 src/conversion.s -o build/conversion.o 58 | 59 | buildFolder: 60 | mkdir -p build 61 | 62 | clean: 63 | rm -f build/*.o build/*.elf build/*.bin build/*.hex build/*.s 64 | -------------------------------------------------------------------------------- /src/core/immediate_generator.v: -------------------------------------------------------------------------------- 1 | module Immediate_Generator ( 2 | input wire [31:0] instruction, 3 | output reg [31:0] immediate 4 | ); 5 | 6 | 7 | localparam LW_OPCODE = 7'b0000011; 8 | localparam SW_OPCODE = 7'b0100011; 9 | localparam JAL_OPCODE = 7'b1101111; 10 | localparam LUI_OPCODE = 7'b0110111; 11 | localparam CSR_OPCODE = 7'b1110011; 12 | localparam JALR_OPCODE = 7'b1100111; 13 | localparam AUIPC_OPCODE = 7'b0010111; 14 | localparam BRANCH_OPCODE = 7'b1100011; 15 | localparam IMMEDIATE_OPCODE = 7'b0010011; 16 | 17 | 18 | always @(*) begin 19 | case (instruction[6:0]) 20 | BRANCH_OPCODE: // SB type 21 | immediate = {{19{instruction[31]}}, instruction[31], instruction[7], instruction[30:25], instruction[11:8], 1'b0}; 22 | JAL_OPCODE: // UJ type JAL 23 | immediate = {{11{instruction[31]}}, instruction[31], instruction[19:12], instruction[20], instruction[30:21], 1'b0}; 24 | AUIPC_OPCODE: // AUIPC U type 25 | immediate = {instruction[31:12], 12'h000}; 26 | LUI_OPCODE: // LUI U type 27 | immediate = {instruction[31:12], 12'h000}; 28 | LW_OPCODE: // lw instruction 29 | immediate = {{20{instruction[31]}}, instruction[31:20]}; 30 | IMMEDIATE_OPCODE: // I type instruction 31 | case (instruction[14:12]) 32 | 3'b001: immediate = {{27{instruction[24]}}, instruction[24:20]}; 33 | 3'b011: immediate = {20'h00000, instruction[31:20]}; 34 | 3'b101: immediate = {{27'h0000000}, instruction[24:20]}; 35 | default: immediate = {{20{instruction[31]}}, instruction[31:20]}; 36 | endcase 37 | JALR_OPCODE: // I type instruction JALR 38 | immediate = {{20{instruction[31]}}, instruction[31:20]}; 39 | CSR_OPCODE: // I type instruction CSR 40 | immediate = {20'h00000, instruction[31:20]}; 41 | SW_OPCODE: // sw instruction (S type) 42 | immediate = {{20{instruction[31]}}, instruction[31:25], instruction[11:7]}; 43 | default: immediate = 32'h00000000; 44 | endcase 45 | end 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /src/peripheral/gpios.v: -------------------------------------------------------------------------------- 1 | `include "config.vh" 2 | `ifdef GPIO_ENABLE 3 | 4 | module GPIOS #( 5 | parameter WIDHT = 20 6 | ) ( 7 | input wire clk, 8 | input wire reset, 9 | input wire read, 10 | input wire write, 11 | input wire [31:0] address, 12 | input wire [31:0] write_data, 13 | output wire [31:0] read_data, 14 | output wire response, 15 | inout [WIDHT - 1:0] gpios 16 | ); 17 | 18 | assign response = read | write; 19 | reg [WIDHT - 1:0] gpio_direction, gpio_value; 20 | wire [WIDHT -1:0] gpio_out; 21 | wire [1:0] pwm_out; 22 | reg [1:0] is_pwm; 23 | 24 | reg [15:0] duty_cycle[1:0]; 25 | reg [15:0] period[1:0]; 26 | 27 | initial begin 28 | is_pwm = 2'b00; 29 | end 30 | 31 | localparam SET_DIRECTION = 8'h00; 32 | localparam WRITE_DATA = 8'h04; 33 | localparam CONFIG_PWM = 8'h08; 34 | localparam CONFIG_PERIOD = 8'h0C; 35 | localparam CONFIG_DUTY_CYCLE = 8'h10; 36 | 37 | assign read_data = (read == 1'b1) ? gpio_out : 32'h00000000; 38 | 39 | GPIO Gpios[WIDHT - 1:0]( 40 | .gpio(gpios), 41 | .direction({gpio_direction[WIDHT - 1: 2], gpio_direction[1:0] & ~is_pwm}), 42 | .data_in({gpio_value[WIDHT - 1: 2], 43 | (gpio_value[1:0] & ~is_pwm) | (pwm_out[1:0] & is_pwm)}), 44 | .data_out(gpio_out) 45 | ); 46 | 47 | PWM Pwm0( 48 | .clk(clk), 49 | .reset(reset), 50 | .duty_cycle(duty_cycle[0]), 51 | .period(period[0]), 52 | .pwm_out(pwm_out[0]) 53 | ); 54 | 55 | PWM Pwm1( 56 | .clk(clk), 57 | .reset(reset), 58 | .duty_cycle(duty_cycle[1]), 59 | .period(period[1]), 60 | .pwm_out(pwm_out[1]) 61 | ); 62 | 63 | always @(posedge clk) begin 64 | if(reset) begin 65 | gpio_direction <= 32'h00000000; 66 | gpio_value <= 32'h00000000; 67 | end else if(write) begin 68 | case (address[7:0]) 69 | SET_DIRECTION: gpio_direction <= write_data[WIDHT - 1: 0]; 70 | WRITE_DATA: gpio_value <= write_data[WIDHT - 1: 0]; 71 | CONFIG_PWM: is_pwm <= write_data[1:0]; 72 | CONFIG_PERIOD: period[write_data[16]] <= write_data[15:0]; 73 | CONFIG_DUTY_CYCLE: duty_cycle[write_data[16]] <= write_data[15:0]; 74 | endcase 75 | end 76 | end 77 | 78 | endmodule 79 | 80 | `endif -------------------------------------------------------------------------------- /debug/clk_divider.v: -------------------------------------------------------------------------------- 1 | module ClkDivider #( 2 | parameter COUNTER_BITS = 32, 3 | parameter PULSE_BITS = 32 4 | )( 5 | input wire clk, 6 | input wire reset, 7 | input wire write_pulse, 8 | input wire option, // 0 - pulse, 1 - auto 9 | input wire out_enable, // 0 not, 1 - yes 10 | input wire [COUNTER_BITS - 1:0] divider, 11 | input wire [PULSE_BITS - 1:0] pulse, 12 | output wire clk_o 13 | ); 14 | 15 | wire clk_o_pulse; 16 | reg clk_o_auto; 17 | reg [COUNTER_BITS - 1:0] clk_counter; 18 | reg [PULSE_BITS - 1:0] pulse_counter; 19 | 20 | assign clk_o = (out_enable == 1'b1) ? (option == 1'b0) ? 21 | clk_o_pulse : clk_o_auto : 1'b0; // multiplexador da saida 22 | 23 | assign clk_o_pulse = (pulse_counter != 32'd0) 24 | ? clk : 1'b0; // liga a saida ao clock enquanto o 25 | // contador de pulsos for maior do que 0 26 | 27 | initial begin 28 | clk_counter = 32'd0; 29 | clk_o_auto = 1'b0; 30 | pulse_counter = 32'd0; 31 | end 32 | 33 | always @(posedge clk ) begin 34 | if(reset == 1'b1) begin 35 | clk_counter <= 32'd0; 36 | clk_o_auto <= 32'd0; 37 | end else begin 38 | if(clk_counter == 0) begin // Gera a parte alta do ciclo de clock de saida 39 | clk_o_auto <= 1'b1; 40 | clk_counter <= clk_counter + 1'b1; 41 | end else if(clk_counter == {1'b0, divider[COUNTER_BITS-1:1]}) begin // Inverte a saida do clock para a parte baixa 42 | clk_o_auto <= 1'b0; 43 | clk_counter <= clk_counter + 1'b1; 44 | end else begin 45 | clk_counter <= clk_counter + 1'b1; // inclementa o contador 46 | end 47 | 48 | if(clk_counter >= divider - 1) begin // para o caso em especifico em que a divisão e por 2 49 | clk_counter <= 32'd0; 50 | end 51 | end 52 | end 53 | 54 | always @(posedge clk ) begin 55 | if(reset == 1'b1) begin 56 | pulse_counter <= 32'd0; 57 | end else begin 58 | if(write_pulse == 1'b1) begin 59 | pulse_counter <= pulse; 60 | end 61 | 62 | if(pulse_counter > 32'd0) begin 63 | pulse_counter <= pulse_counter - 1'b1; 64 | end 65 | end 66 | end 67 | 68 | endmodule -------------------------------------------------------------------------------- /docs/docs/about.en.md: -------------------------------------------------------------------------------- 1 | # About Risco-5 2 | 3 |

4 | Processor Logo 5 |

6 | 7 | ## Project Origin 8 | 9 | The project began as a summer project aimed at developing a [RISC-V](https://riscv.org/) core for learning purposes. Initially, a single-cycle version, named Pequeno Risco-5, was developed. The project quickly evolved into a multi-cycle version shortly after its inception. 10 | 11 | This project was encouraged by Professor [Rodolfo Azevedo](https://www.ic.unicamp.br/~rodolfo/) from the [Institute of Computing](https://www.ic.unicamp.br/) at [UNICAMP](http://www.unicamp.br/), who suggested the construction of a single-cycle RISC-V processor and later a multi-cycle RISC-V. He also provided the first FPGAs used for testing and assisted with technical questions. 12 | 13 | ## Name 14 | 15 | The name Risco-5 is a play on the name RISC-V, the architecture it implements, but it can also suggest something risky. 16 | 17 | ## Risco-5 Family: 18 | 19 | - Baby RISCO 5 - RV32E optimized to TinyTapeout: [https://github.com/JN513/Baby-Risco-5](https://github.com/JN513/Baby-Risco-5) 20 | - Pequeno RISCO 5 - RV32I single cycle implementation (ARCHIVED): [https://github.com/JN513/Pequeno-Risco-5/](https://github.com/JN513/Pequeno-Risco-5/) 21 | - RISCO 5 - RV32I/E[M]: [https://github.com/JN513/Risco-5](https://github.com/JN513/Risco-5) 22 | - Grande RISCO 5 - RV32I Implementation with pipeline: [https://github.com/JN513/Grande-Risco-5](https://github.com/JN513/Grande-Risco-5) 23 | - RISCO 5 Bodybuilder - RV64I: Still in speculative phase 24 | - RISCO 5S - RV32IM Simulator writing in C language: [https://github.com/JN513/Risco-5S](https://github.com/JN513/Risco-5S) 25 | 26 | ## Developer 27 | 28 | Risco-5 was designed by [Julio Nunes Avelar](https://github.com/JN513) and is available for free use under the licenses listed below. 29 | 30 | Logo author: [Mateus Luck](https://www.instagram.com/mateusluck/) 31 | 32 | ## Licenses 33 | 34 | Hardware License: [CERN-OHL-P-2.0](https://github.com/JN513/Risco-5/blob/main/LICENSE) 35 | 36 | Software License: [MIT](https://github.com/JN513/Risco-5/blob/main/software/LICENSE-MIT) 37 | 38 | Documentation License: [CC BY-SA 4.0](https://github.com/JN513/Risco-5/blob/main/LICENSE-CC) -------------------------------------------------------------------------------- /src/core/alu_control.v: -------------------------------------------------------------------------------- 1 | module ALU_Control ( 2 | input wire is_immediate, 3 | input wire [1:0] aluop_in, 4 | input wire [6:0] func7, 5 | input wire [2:0] func3, 6 | output reg [3:0] aluop_out 7 | ); 8 | 9 | always @(*) begin 10 | aluop_out <= 4'b0010; 11 | case (aluop_in) 12 | 2'b00: 13 | aluop_out <= 4'b0010; 14 | 15 | 2'b01: begin 16 | case (func3) 17 | 3'b000: //beq 18 | aluop_out <= 4'b0110; // SUB 19 | 3'b100: // blt 20 | aluop_out <= 4'b1011; // precisa arrumar - Maior Igual 21 | 3'b110: // bltu 22 | aluop_out <= 4'b1101; // precisa arrumar - Maior Igual 23 | 3'b101: // bge 24 | aluop_out <= 4'b0111; // SLT 25 | 3'b111: // bgeu 26 | aluop_out <= 4'b1111; 27 | 3'b001: // bne 28 | aluop_out <= 4'b1110; // Igualdade 29 | default: aluop_out <= 4'b0110; 30 | endcase 31 | end 32 | 33 | 2'b10: begin 34 | case (func3) 35 | 3'b000: // addi, add e sub 36 | if(is_immediate == 1'b0 && func7[5] == 1'b1) 37 | aluop_out <= 4'b0110; 38 | else 39 | aluop_out <= 4'b0010; 40 | 3'b001: // slli e sll 41 | aluop_out <= 4'b1000; 42 | 3'b010: // slti e slt 43 | aluop_out <= 4'b0111; 44 | 3'b011: // sltiu e sltu 45 | aluop_out <= 4'b1111; 46 | 3'b100: // xori e xor 47 | aluop_out <= 4'b1010; 48 | 3'b101: // srai, srli e sra, srl 49 | if(func7[5] == 1'b1) 50 | aluop_out <= 4'b0011; 51 | else 52 | aluop_out <= 4'b1001; 53 | 3'b110: // ori e or 54 | aluop_out <= 4'b0001; 55 | 3'b111: // andi e and 56 | aluop_out <= 4'b0000; 57 | default: aluop_out <= 4'b0010; 58 | endcase 59 | end 60 | endcase 61 | end 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /docs/docs/about.md: -------------------------------------------------------------------------------- 1 | # Sobre o Risco-5 2 | 3 |

4 | Processor Logo 5 |

6 | 7 | 8 | ## Origem do projeto 9 | 10 | O projeto teve início a partir de um projeto de férias cujo objetivo era desenvolver um core [RISC-V](https://riscv.org/) para fins de aprendizado, inicialmente foi desenvolvida uma versão monocilo, denominada Pequeno Risco-5. O projeto evoluiu rapidamente para uma versão multiciclo pouco tempo depois de seu início. 11 | 12 | Esse projeto foi incentivado pelo professor [Rodolfo Azevedo](https://www.ic.unicamp.br/~rodolfo/), do [Instituto de Computação](https://www.ic.unicamp.br/) da [UNICAMP](http://www.unicamp.br/), que sugeriu a construção de um processador RISC-V monociclo e posteriormente um RISC-V multiciclo. Ele também forneceu as primeiras FPGAs utilizadas para testes e auxiliou com dúvidas técnicas. 13 | 14 | ## Nome 15 | 16 | O nome Risco-5 vem de uma piada com o nome RISC-V, a arquitetura que ele implementa, mas também pode remeter a algo arriscado. 17 | 18 | ## Família Risco-5: 19 | 20 | - Baby Risco 5 - RV32E Implementação otimizada para o TinyTapeout: [https://github.com/JN513/Baby-Risco-5](https://github.com/JN513/Baby-Risco-5) 21 | - Pequeno Risco 5 - RV32I Implementação de ciclo único (Arquivada): [https://github.com/JN513/Pequeno-Risco-5/](https://github.com/JN513/Pequeno-Risco-5/) 22 | - Risco 5 - RV32I/E[M]: [https://github.com/JN513/Risco-5](https://github.com/JN513/Risco-5) 23 | - Grande Risco 5 - RV32I: [https://github.com/JN513/Grande-Risco-5](https://github.com/JN513/Grande-Risco-5) 24 | - Risco 5 Bodybuilder - RV64IMA: Ainda em fase especulativa 25 | - RISCO 5S - RV32IM Simulador escrito com a linguagem C: [https://github.com/JN513/Risco-5S](https://github.com/JN513/Risco-5S) 26 | 27 | ## Desenvolvedor 28 | 29 | O Risco-5 foi projetado por [Julio Nunes Avelar](https://github.com/JN513) e está disponível para uso livre sob as licenças listadas abaixo. 30 | 31 | Autor da logo: [Mateus luck](https://www.instagram.com/mateusluck/) 32 | 33 | ## Licenças 34 | 35 | Licença de Hardware: [CERN-OHL-P-2.0](https://github.com/JN513/Risco-5/blob/main/LICENSE) 36 | 37 | Licença de Software: [MIT](https://github.com/JN513/Risco-5/blob/main/software/LICENSE-MIT) 38 | 39 | Licença da Documentação: [CC BY-SA 4.0](https://github.com/JN513/Risco-5/blob/main/LICENSE-CC) -------------------------------------------------------------------------------- /src/core/alu.v: -------------------------------------------------------------------------------- 1 | module Alu ( 2 | input wire [3:0] operation, 3 | input wire [31:0] ALU_in_X, 4 | input wire [31:0] ALU_in_Y, 5 | output reg [31:0] ALU_out_S, 6 | output wire ZR 7 | ); 8 | 9 | localparam AND = 4'b0000; 10 | localparam OR = 4'b0001; 11 | localparam SUM = 4'b0010; 12 | localparam SUB = 4'b0110; 13 | localparam SLT = 4'b0111; 14 | localparam NOR = 4'b1100; 15 | localparam XOR = 4'b1010; 16 | localparam EQUAL = 4'b1110; 17 | localparam SHIFT_LEFT = 4'b1000; 18 | localparam SHIFT_RIGHT = 4'b1001; 19 | localparam GREATER_EQUAL = 4'b1011; 20 | localparam SHIFT_RIGHT_A = 4'b0011; 21 | localparam GREATER_EQUAL_U = 4'b1101; 22 | localparam SLT_U = 4'b1111; 23 | 24 | assign ZR = ~( |ALU_out_S ); 25 | 26 | always @(*) begin 27 | case(operation) 28 | AND: // AND 29 | ALU_out_S <= ALU_in_X & ALU_in_Y; 30 | OR: // OR 31 | ALU_out_S <= ALU_in_X | ALU_in_Y; 32 | SUM: // Adição 33 | ALU_out_S <= ALU_in_X + ALU_in_Y; 34 | SUB: // Subtração 35 | ALU_out_S <= ALU_in_X - ALU_in_Y; 36 | SLT: // SLT 37 | ALU_out_S <= (ALU_in_X < ALU_in_Y) ? 32'h1 : 32'h0; 38 | SLT_U: // SLT 39 | ALU_out_S <= ($unsigned(ALU_in_X) < $unsigned(ALU_in_Y)) ? 32'h1 : 32'h0; 40 | NOR: // NOR 41 | ALU_out_S <= ~(ALU_in_X | ALU_in_Y); 42 | XOR: // XOR (OU exclusivo) 43 | ALU_out_S <= ALU_in_X ^ ALU_in_Y; 44 | EQUAL: // Igualdade 45 | ALU_out_S <= ALU_in_X == ALU_in_Y; 46 | SHIFT_LEFT: // Shift Left (deslocamento à esquerda) 47 | ALU_out_S <= ALU_in_X << ALU_in_Y[4:0]; 48 | SHIFT_RIGHT: // Shift Right (deslocamento à direita) 49 | ALU_out_S <= ALU_in_X >> ALU_in_Y[4:0]; 50 | SHIFT_RIGHT_A: // Shift Right Arithmetic (deslocamento à direita) 51 | ALU_out_S <= ALU_in_X >>> ALU_in_Y[4:0]; 52 | GREATER_EQUAL: // Maior igual 53 | ALU_out_S <= (ALU_in_X >= ALU_in_Y) ? 32'h1 : 32'h0; 54 | GREATER_EQUAL_U: // Maior igual 55 | ALU_out_S <= ($unsigned(ALU_in_X) >= $unsigned(ALU_in_Y)) ? 32'h1 : 32'h0; 56 | default: ALU_out_S <= ALU_in_X ; // Operação padrão 57 | endcase 58 | end 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /tests/pc_test.v: -------------------------------------------------------------------------------- 1 | module pc_tb(); 2 | 3 | reg clk, pc_load, reset; 4 | 5 | always #1 clk = ~clk; 6 | wire [31:0] pc_output; 7 | reg [31:0] pc_input; 8 | 9 | PC PC( 10 | .clk(clk), 11 | .reset(reset), 12 | .Input(pc_input), 13 | .Output(pc_output), 14 | .load(pc_load), 15 | ); 16 | 17 | initial begin 18 | $dumpfile("build/pc.vcd"); 19 | $dumpvars 20 | 21 | clk = 0; 22 | reset = 0; 23 | pc_load = 0; 24 | 25 | #2 26 | 27 | $display("Estado inicial %d", pc_output); 28 | 29 | if(pc_output == 0) begin 30 | $display("Resultado correto"); 31 | end else begin 32 | $display("Resultado incorreto"); 33 | end 34 | 35 | #2 36 | 37 | $display("Estado %d", pc_output); 38 | 39 | if(pc_output == 1) begin 40 | $display("Resultado correto"); 41 | end else begin 42 | $display("Resultado incorreto"); 43 | end 44 | 45 | #2 46 | 47 | $display("Estado %d", pc_output); 48 | 49 | if(pc_output == 1) begin 50 | $display("Resultado correto"); 51 | end else begin 52 | $display("Resultado incorreto"); 53 | end 54 | 55 | #2 56 | 57 | $display("Estado %d", pc_output); 58 | 59 | if(pc_output == 2) begin 60 | $display("Resultado correto"); 61 | end else begin 62 | $display("Resultado incorreto"); 63 | end 64 | 65 | #4 66 | 67 | pc_load = 1; 68 | pc_input = 47; 69 | 70 | #2 71 | 72 | pc_load = 0; 73 | 74 | $display("Estado %d", pc_output); 75 | pc_inclement = 1; 76 | 77 | if(pc_output == 47) begin 78 | $display("Resultado correto"); 79 | end else begin 80 | $display("Resultado incorreto"); 81 | end 82 | 83 | #2 84 | 85 | $display("Estado %d", pc_output); 86 | pc_inclement = 0; 87 | reset = 1; 88 | 89 | if(pc_output == 48) begin 90 | $display("Resultado correto"); 91 | end else begin 92 | $display("Resultado incorreto"); 93 | end 94 | 95 | #2 96 | $display("Estado %d", pc_output); 97 | reset = 0; 98 | 99 | if(pc_output == 0) begin 100 | $display("Resultado correto"); 101 | end else begin 102 | $display("Resultado incorreto"); 103 | end 104 | 105 | $finish; 106 | end 107 | 108 | endmodule 109 | -------------------------------------------------------------------------------- /docs/docs/contributing.en.md: -------------------------------------------------------------------------------- 1 | # Contributing to the Project 2 | 3 | Thank you for considering contributing to the Project! We are happy to welcome contributions from anyone interested in improving this project. Before you start, please read this guide to understand how you can contribute effectively. 4 | 5 | ## How to Contribute 6 | 7 | 1. **Fork the Repository**: First, fork this repository to your own account. 8 | 9 | 2. **Clone the Repository**: Clone the forked repository to your local development environment. 10 | 11 | ```bash 12 | git clone https://github.com/JN513/Risco-5.git 13 | ``` 14 | 15 | 3. **Create a Branch**: Create a branch for your contribution. Be sure to choose a descriptive name. 16 | 17 | ```bash 18 | git checkout -b my-contribution 19 | ``` 20 | 21 | 4. **Make Changes**: Make the necessary changes to the code. 22 | 23 | 5. **Test Changes**: Ensure that your changes do not cause issues in the project. Run relevant tests if applicable. 24 | 25 | 6. **Commit and Push**: Commit your changes and push them to your forked repository. 26 | 27 | ```bash 28 | git commit -m "Added a new feature" 29 | git push origin my-contribution 30 | ``` 31 | 32 | 7. **Create a Pull Request**: Open a Pull Request (PR) to the main branch of the original project. Be sure to clearly describe the changes you made and provide relevant information. 33 | 34 | 8. **Review and Discussion**: The project team will review your PR and may request changes or clarifications. Be prepared to collaborate and adjust your code as needed. 35 | 36 | 9. **Approval and Merge**: After a successful review and approval by the team, your PR will be merged into the main project. 37 | 38 | 10. **Celebrate**: Congratulations! Your contribution has been successfully merged. 39 | 40 | ## Contribution Guidelines 41 | 42 | - Follow the project's coding standards. 43 | - Keep commit messages clear and concise. 44 | - Avoid making too many changes in a single PR. 45 | - If you are adding a new feature, consider including appropriate tests. 46 | 47 | ## Communication 48 | 49 | - If you have questions or need help, create an issue in this repository. 50 | - We appreciate your contribution to making the Project better! 51 | 52 | ## License 53 | 54 | By contributing to this project, you agree that your contributions will be licensed under the same license as the project. Read the [license](https://github.com/JN513/Risco-5/blob/main/LICENSE) for more details. -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | # Contributing to the Project 2 | 3 | Thank you for considering contributing to the Project! We are happy to welcome contributions from anyone interested in improving this project. Before you start, please read this guide to understand how you can contribute effectively. 4 | 5 | ## How to Contribute 6 | 7 | 1. **Fork the Repository**: First, fork this repository to your own account. 8 | 9 | 2. **Clone the Repository**: Clone the forked repository to your local development environment. 10 | 11 | ```bash 12 | git clone https://github.com/JN513/Risco-5.git 13 | ``` 14 | 15 | 3. **Create a Branch**: Create a branch for your contribution. Be sure to choose a descriptive name. 16 | 17 | ```bash 18 | git checkout -b my-contribution 19 | ``` 20 | 21 | 4. **Make Changes**: Make the necessary changes to the code. 22 | 23 | 5. **Test Changes**: Ensure that your changes do not cause issues in the project. Run relevant tests if applicable. 24 | 25 | 6. **Commit and Push**: Commit your changes and push them to your forked repository. 26 | 27 | ```bash 28 | git commit -m "Added a new feature" 29 | git push origin my-contribution 30 | ``` 31 | 32 | 7. **Create a Pull Request**: Open a Pull Request (PR) to the main branch of the original project. Be sure to clearly describe the changes you made and provide relevant information. 33 | 34 | 8. **Review and Discussion**: The project team will review your PR and may request changes or clarifications. Be prepared to collaborate and adjust your code as needed. 35 | 36 | 9. **Approval and Merge**: After a successful review and approval by the team, your PR will be merged into the main project. 37 | 38 | 10. **Celebrate**: Congratulations! Your contribution has been successfully merged. 39 | 40 | ## Contribution Guidelines 41 | 42 | - Follow the project's coding standards. 43 | - Keep commit messages clear and concise. 44 | - Avoid making too many changes in a single PR. 45 | - If you are adding a new feature, consider including appropriate tests. 46 | 47 | ## Communication 48 | 49 | - If you have questions or need help, create an issue in this repository. 50 | - We appreciate your contribution to making the Project better! 51 | 52 | ## License 53 | 54 | By contributing to this project, you agree that your contributions will be licensed under the same license as the project. Read the [license](https://github.com/JN513/Risco-5/blob/main/LICENSE) for more details. -------------------------------------------------------------------------------- /src/core/registers.v: -------------------------------------------------------------------------------- 1 | `include "config.vh" 2 | module Registers ( 3 | input wire clk, 4 | input wire reset, 5 | input wire regWrite, 6 | input wire [4:0] readRegister1, 7 | input wire [4:0] readRegister2, 8 | input wire [4:0] writeRegister, 9 | input wire [31:0] writeData, 10 | output wire [31:0] readData1, 11 | output wire [31:0] readData2, 12 | output wire [31:0] readDataRD 13 | ); 14 | 15 | `ifdef RV32E 16 | reg [31:0] registers[0:15]; 17 | `else 18 | reg [31:0] registers[0:31]; 19 | `endif 20 | 21 | initial begin 22 | registers[0] = 32'h00000000; 23 | end 24 | 25 | assign readData1 = registers[readRegister1]; 26 | assign readData2 = registers[readRegister2]; 27 | `ifdef UNALIGNED_ENABLE 28 | assign readDataRD = registers[writeRegister]; 29 | `else 30 | assign readDataRD = 32'h0; 31 | `endif 32 | 33 | always @(posedge clk) begin 34 | if(reset == 1'b1) begin 35 | registers[0] <= 32'd0; 36 | end else if (regWrite == 1'b1) begin 37 | registers[writeRegister] <= writeData; 38 | end else begin 39 | registers[0] <= 32'h00000000; 40 | end 41 | end 42 | 43 | `ifdef __ICARUS__ 44 | wire [31:0] register1 = registers[1]; 45 | wire [31:0] register2 = registers[2]; 46 | wire [31:0] register3 = registers[3]; 47 | wire [31:0] register4 = registers[4]; 48 | wire [31:0] register5 = registers[5]; 49 | wire [31:0] register6 = registers[6]; 50 | wire [31:0] register7 = registers[7]; 51 | wire [31:0] register8 = registers[8]; 52 | wire [31:0] register9 = registers[9]; 53 | wire [31:0] register10 = registers[10]; 54 | wire [31:0] register11 = registers[11]; 55 | wire [31:0] register12 = registers[12]; 56 | wire [31:0] register13 = registers[13]; 57 | wire [31:0] register14 = registers[14]; 58 | wire [31:0] register15 = registers[15]; 59 | wire [31:0] register16 = registers[16]; 60 | wire [31:0] register17 = registers[17]; 61 | wire [31:0] register18 = registers[18]; 62 | wire [31:0] register19 = registers[19]; 63 | wire [31:0] register20 = registers[20]; 64 | wire [31:0] register21 = registers[21]; 65 | wire [31:0] register22 = registers[22]; 66 | wire [31:0] register23 = registers[23]; 67 | wire [31:0] register24 = registers[24]; 68 | wire [31:0] register25 = registers[25]; 69 | wire [31:0] register26 = registers[26]; 70 | wire [31:0] register27 = registers[27]; 71 | wire [31:0] register28 = registers[28]; 72 | wire [31:0] register29 = registers[29]; 73 | wire [31:0] register30 = registers[30]; 74 | wire [31:0] register31 = registers[31]; 75 | 76 | `endif 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /docs/docs/contributing.md: -------------------------------------------------------------------------------- 1 | # Contribuindo para o Projeto 2 | 3 | Obrigado por considerar contribuir para o Projeto! Estamos felizes em receber contribuições de qualquer pessoa interessada em melhorar este projeto. Antes de começar, por favor, leia este guia para entender como você pode contribuir de forma eficaz. 4 | 5 | ## Como Contribuir 6 | 7 | 1. **Fork do Repositório**: Primeiro, faça um fork deste repositório para a sua própria conta. 8 | 9 | 2. **Clone o Repositório**: Clone o repositório forkado para o seu ambiente de desenvolvimento local. 10 | 11 | ```bash 12 | git clone https://github.com/JN513/Risco-5.git 13 | ``` 14 | 15 | 3. **Crie uma Branch**: Crie uma branch para a sua contribuição. Certifique-se de escolher um nome descritivo. 16 | 17 | ```bash 18 | git checkout -b minha-contribuicao 19 | ``` 20 | 21 | 4. **Faça as Mudanças**: Faça as mudanças necessárias no código. 22 | 23 | 5. **Teste as Mudanças**: Certifique-se de que as suas alterações não causam problemas no projeto. Execute testes relevantes, se aplicável. 24 | 25 | 6. **Commit e Push**: Faça commit das suas mudanças e envie-as para o seu repositório forkado. 26 | 27 | ```bash 28 | git commit -m "Adicionei uma nova funcionalidade" 29 | git push origin minha-contribuicao 30 | ``` 31 | 32 | 7. **Crie um Pull Request**: Abra um Pull Request (PR) para a branch principal do projeto original. Certifique-se de descrever claramente as mudanças que você fez e forneça informações relevantes. 33 | 34 | 8. **Revisão e Discussão**: A equipe do projeto revisará o seu PR e poderá solicitar mudanças ou esclarecimentos. Esteja disposto a colaborar e ajustar o seu código conforme necessário. 35 | 36 | 9. **Aprovação e Mesclagem**: Após a revisão bem-sucedida e a aprovação da equipe, o seu PR será mesclado no projeto principal. 37 | 38 | 10. **Celebração**: Parabéns! Sua contribuição foi mesclada com sucesso. 39 | 40 | ## Diretrizes para Contribuições 41 | 42 | - Siga os padrões de codificação do projeto. 43 | - Mantenha mensagens de commit claras e concisas. 44 | - Evite fazer muitas alterações em um único PR. 45 | \*Se você estiver adicionando uma nova funcionalidade, considere incluir testes apropriados. 46 | 47 | ## Comunicação 48 | 49 | - Se você tiver dúvidas ou precisar de ajuda, crie uma issue nno repositório. 50 | - Agradecemos a sua contribuição para tornar o Projeto melhor! 51 | 52 | ## Licença 53 | 54 | Ao contribuir para este projeto, você concorda que suas contribuições serão licenciadas sob a mesma licença do projeto. Leia a [licença](hhttps://github.com/JN513/Risco-5/blob/main/LICENSE) para mais detalhes. -------------------------------------------------------------------------------- /docs/docs/get_started.en.md: -------------------------------------------------------------------------------- 1 | # Getting Started with Risco-5 2 | 3 | ## Tests / Simulation 4 | 5 | The "tests" directory contains some tests for the project modules. These tests were developed to be used with [Iverilog](https://steveicarus.github.io/iverilog/). To run the tests, simply use Iverilog and VVP as shown in the example below: 6 | 7 | ```bash 8 | iverilog -o build/core_test.o -s core_tb src/core/* src/peripheral/memory.v tests/core_test.v 9 | vvp build/core_test.o 10 | ``` 11 | 12 | To facilitate running the tests, you can use the "run_test" script available at the root of the project. When running this script, it will prompt for the name of the test and the name of one of the assembly test files available in the "software/code/" directory. As a result, a "soc.vcd" file will be generated in "build/" which can be analyzed using GTKWave. 13 | 14 | ### Requirements: 15 | 16 | - Iverilog 17 | - GTKWave 18 | 19 | These dependencies can be obtained through the [oss cad suite](https://github.com/YosysHQ/oss-cad-suite-build) or can be installed individually. 20 | 21 | ## FPGA 22 | 23 | The project supports testing on several FPGAs, listed below: 24 | 25 | - Colorlight i9 - ECP5 45F 26 | - Digilent Arty A7 100t 27 | - Digilent Nexys 4 DDR 28 | - Tangnano 20k 29 | - AMD/Xilinx VC709 Connectivity Kit 30 | 31 | Examples are available in the "FPGA" directory. For Sipeed FPGAs (Tangnano 9k and 20k), the examples were developed using the Gowin IDE. For Lattice/ColorLight FPGAs, the examples were developed using Yosys + NextPNR and can be synthesized and programmed using the makefile available in the directories. For Xilinx FPGAs, Vivado was used, and the examples can also be utilized using the makefile available in the directory. 32 | 33 | ### Requirements 34 | 35 | - AMD/Xilinx: 36 | - Vivado 37 | - openFPGALoader 38 | - Lattice/Colorlight: 39 | - Yosys 40 | - Nextpnr-ECP5 41 | - ecppack 42 | - openFPGALoader 43 | - Gowin/Sipeed: 44 | - Gowin EDA 45 | - openFPGALoader 46 | 47 | - General: 48 | - Pyserial or VSCode Serial or Minicom or other software capable of using serial 49 | 50 | ### Running the Test on FPGA 51 | 52 | Navigate to the "fpga/???" directory, with "???" being the name of the FPGA to be used, and run the command "make". This will perform the project synthesis. To load the bitstream onto the board, use "make flash". If you want to do everything at once, use "make run_all". 53 | 54 | #### FPGA Feedback 55 | 56 | If everything goes well, the FPGA LEDs will start blinking in a counting rhythm, and an ASCII character will begin to be sent over the serial connection. The serial operates at a standard baud rate of 115200 bps. -------------------------------------------------------------------------------- /docs/docs/get_started.md: -------------------------------------------------------------------------------- 1 | # Iniciando com o Risco-5 2 | 3 | ## Testes / Simulação 4 | 5 | O diretório "testes" contém alguns testes para os módulos do projeto. Esses testes foram desenvolvidos para serem utilizados com o [Iverilog](https://steveicarus.github.io/iverilog/). Para executar os testes, basta utilizar o Iverilog e o VVP, como mostrado no exemplo abaixo: 6 | 7 | ```bash 8 | iverilog -o build/core_test.o -s core_tb src/core/* src/peripheral/memory.v tests/core_test.v 9 | vvp build/core_test.o 10 | ``` 11 | 12 | Para facilitar a execução dos testes, é possível utilizar o script "run_test" disponível na raiz do projeto. Ao executar esse script, ele solicitará o nome do teste e o nome de um dos arquivos de teste em assembly disponíveis no diretório "software/code/". Como resultado, será gerado um arquivo "soc.vcd" em "build/" que pode ser analisado através do GTKWave. 13 | 14 | ### Requisitos: 15 | 16 | - Iverilog 17 | - GTKWave 18 | 19 | Essas dependências podem ser obtidas através do [oss cad suite](https://github.com/YosysHQ/oss-cad-suite-build) ou podem ser instaladas manualmente de forma individual. 20 | 21 | ## FPGA 22 | 23 | O projeto oferece suporte a testes em algumas FPGAs, listadas abaixo: 24 | 25 | - Colorlight i9 - ECP5 45F 26 | - Digilent Arty A7 100t 27 | - Digilent Nexys 4 DDR 28 | - Tangnano 20k 29 | - AMD/Xilinx VC709 Connectivity Kit 30 | 31 | Os exemplos estão disponíveis no diretório "FPGA". Para as FPGAs Sipeed (Tangnano 9k e 20k), os exemplos foram desenvolvidos utilizando a IDE Gowin. Para as FPGAs Lattice/ColorLight, os exemplos foram desenvolvidos utilizando o Yosys + NextPNR e podem ser sintetizados e programados utilizando o makefile disponível nos diretórios. Para as FPGAs Xilinx, foi utilizado o Vivado, e os exemplos podem ser utilizados também utilizando o makefile disponível no diretório. 32 | 33 | ### Requisitos 34 | 35 | - AMD/Xilinx: 36 | Vivado 37 | openFPGALoader 38 | - Lattice/Colorlight: 39 | Yosys 40 | Nextpnr-ECP5 41 | ecppack 42 | openFPGALoader 43 | - Gowin/Sipeed: 44 | Gowin EDA 45 | openFPGALoader 46 | 47 | - Geral: 48 | Pyserial ou VSCode Serial ou Minicom ou outro software capaz de utilizar serial 49 | 50 | ### Executando o Teste na FPGA 51 | 52 | Acesse o diretório "fpga/???" com "???" sendo o nome da FPGA a ser utilizada, e execute o comando "make". Com isso, a síntese do projeto será realizada. Para carregar o bitstream para a placa, utilize "make flash". Caso queira executar tudo de uma vez, use "make run_all". 53 | 54 | #### Feedback da FPGA 55 | 56 | Se tudo ocorrer bem, os LEDs da FPGA começarão a piscar em um ritmo de contagem, e na serial começará a ser enviado um caractere ASCII. A serial opera com um baudrate padrão de 115200 bps. -------------------------------------------------------------------------------- /fpga/tangnano20k/tangnano20k.gprj.user: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 1.0 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 000000ff00000001fd0000000200000000000001f30000033cfc0200000001fc000000340000033c0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000077c000000f1fc0100000001fc000000000000077c0000000000fffffffaffffffff0100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000000000000000000005830000033c00000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000afffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000183ffffffff0000000000000000 24 | 25 | -------------------------------------------------------------------------------- /src/peripheral/bus.v: -------------------------------------------------------------------------------- 1 | module BUS ( 2 | // master connection 3 | input wire read, 4 | input wire write, 5 | input wire [31:0] address, 6 | input wire [31:0] write_data, 7 | output wire [31:0] read_data, 8 | output wire response, 9 | 10 | // slave 0 signal 11 | output wire slave_0_read, 12 | output wire slave_0_write, 13 | input wire [31:0] slave_0_read_data, 14 | output wire [31:0] slave_0_address, 15 | output wire [31:0] slave_0_write_data, 16 | input wire slave_0_response, 17 | 18 | // slave 1 signal 19 | output wire slave_1_read, 20 | output wire slave_1_write, 21 | input wire [31:0] slave_1_read_data, 22 | output wire [31:0] slave_1_address, 23 | output wire [31:0] slave_1_write_data, 24 | input wire slave_1_response, 25 | 26 | // slave 2 signal 27 | output wire slave_2_read, 28 | output wire slave_2_write, 29 | input wire [31:0] slave_2_read_data, 30 | output wire [31:0] slave_2_address, 31 | output wire [31:0] slave_2_write_data, 32 | input wire slave_2_response, 33 | 34 | // slave 3 signal 35 | output wire slave_3_read, 36 | output wire slave_3_write, 37 | input wire [31:0] slave_3_read_data, 38 | output wire [31:0] slave_3_address, 39 | output wire [31:0] slave_3_write_data, 40 | input wire slave_3_response 41 | ); 42 | 43 | localparam DEVICE0 = 3'd0; // 00 44 | localparam DEVICE1 = 3'd1; // 01 45 | localparam DEVICE2 = 3'd2; // 10 46 | localparam DEVICE3 = 3'd3; // 11 47 | 48 | assign slave_0_read = (address[31:30] == 2'b00) ? read : 1'b0; 49 | assign slave_0_write = (address[31:30] == 2'b00) ? write : 1'b0; 50 | assign slave_0_write_data = write_data; 51 | assign slave_0_address = address; 52 | 53 | assign slave_1_read = (address[31:30] == 2'b01) ? read : 1'b0; 54 | assign slave_1_write = (address[31:30] == 2'b01) ? write : 1'b0; 55 | assign slave_1_write_data = write_data; 56 | assign slave_1_address = address; 57 | 58 | assign slave_2_read = (address[31:30] == 2'b10) ? read : 1'b0; 59 | assign slave_2_write = (address[31:30] == 2'b10) ? write : 1'b0; 60 | assign slave_2_write_data = write_data; 61 | assign slave_2_address = address; 62 | 63 | assign slave_3_read = (address[31:30] == 2'b11) ? read : 1'b0; 64 | assign slave_3_write = (address[31:30] == 2'b11) ? write : 1'b0; 65 | assign slave_3_write_data = write_data; 66 | assign slave_3_address = address; 67 | 68 | assign read_data = (address[31:30] == 2'b00) ? slave_0_read_data : 69 | (address[31:30] == 2'b01) ? slave_1_read_data : (address[31:30] == 2'b10) ? 70 | slave_2_read_data : slave_3_read_data; 71 | 72 | assign response = (address[31:30] == 2'b00) ? slave_0_response : 73 | (address[31:30] == 2'b01) ? slave_1_response : (address[31:30] == 2'b10) ? 74 | slave_2_response : slave_3_response; 75 | 76 | endmodule 77 | -------------------------------------------------------------------------------- /software/firmware/src/gpio.s: -------------------------------------------------------------------------------- 1 | # Declarações globais das funções 2 | .globl gpio_write_direction 3 | .globl gpio_write_data 4 | .globl gpio_read_data 5 | 6 | .globl set_led_value 7 | 8 | .globl set_pwm_period 9 | .globl set_pwm_duty_cycle 10 | .globl config_gpio_as_pwm 11 | 12 | # Função para configurar a direção GPIO 13 | config_gpio_direction: 14 | li t1, 0xC0000000 # Carrega o endereço do registrador de direção GPIO em t1 15 | sw a0, 0(t1) # Armazena o valor de a0 (argumento) no endereço t1 (configuração de direção GPIO) 16 | 17 | ret # Retorna da função 18 | 19 | # Função para escrever dados em GPIO 20 | gpio_write_data: 21 | li t1, 0xC0000004 # Carrega o endereço do registrador de escrita de dados GPIO em t1 22 | sw a0, 0(t1) # Armazena o valor de a0 (argumento) no endereço t1 (escrita de dados GPIO) 23 | 24 | ret # Retorna da função 25 | 26 | # Função para ler dados de GPIO 27 | gpio_read_data: 28 | li t1, 0xC0000000 # Carrega o endereço do registrador de leitura de dados GPIO em t1 29 | lw a0, 0(t1) # Carrega o valor do registrador t1 para a0 (retorno da leitura de dados GPIO) 30 | 31 | ret # Retorna da função 32 | 33 | # Função para definir o valor de um LED 34 | set_led_value: 35 | li t1, 0x40000000 # Carrega o endereço do registrador de controle de LED em t1 36 | sw a0, 0(t1) # Armazena o valor de a0 (argumento) no endereço t1 (controle de LED) 37 | 38 | ret # Retorna da função 39 | 40 | # Função para definir o período do PWM 41 | set_pwm_period: 42 | li t1, 0xC000000C # Carrega o endereço do registrador de período do PWM em t1 43 | slli a1, a1, 16 # Desloca o valor de a1 (argumento) 16 bits para a esquerda 44 | or a0, a0, a1 # Combina os valores de a0 e a1 45 | sw a0, 0(t1) # Armazena o valor de a0 (argumento) no endereço t1 (configuração do período do PWM) 46 | 47 | ret # Retorna da função 48 | 49 | # Função para definir o ciclo de trabalho (duty cycle) do PWM 50 | set_pwm_duty_cycle: 51 | li t1, 0xC0000010 # Carrega o endereço do registrador de ciclo de trabalho do PWM em t1 52 | slli a1, a1, 16 # Desloca o valor de a1 (argumento) 16 bits para a esquerda 53 | or a0, a0, a1 # Combina os valores de a0 e a1 54 | sw a0, 0(t1) # Armazena o valor de a0 (argumento) no endereço t1 (configuração do ciclo de trabalho do PWM) 55 | 56 | ret # Retorna da função 57 | 58 | # Função para habilitar/desabilitar o PWM 59 | config_gpio_as_pwm: 60 | li t1, 0xC0000008 # Carrega o endereço do registrador de controle de habilitação do PWM em t1 61 | sw a0, 0(t1) # Armazena o valor de a0 (argumento) no endereço t1 (controle de habilitação do PWM) 62 | 63 | ret # Retorna da função 64 | -------------------------------------------------------------------------------- /README_pt.md: -------------------------------------------------------------------------------- 1 | # RISCO 5 2 | 3 |

4 | Logo do processador 5 |

6 | 7 | Processador multi-ciclo [RISC-V](https://riscv.org/) com implementação RV32I/E[M], desenvolvido durante alguns dias de folga. 8 | 9 | - **Don't speak portuguese? [click here](https://github.com/JN513/Risco-5/blob/main/README.md)** 10 | 11 | ## Processor CI 12 | 13 | [![Build Status](https://processorci.ic.unicamp.br/jenkins/buildStatus/icon?job=Risco-5)](https://processorci.ic.unicamp.br/jenkins/blue/organizations/jenkins/Risco-5/activity) 14 | 15 | ## Implementação 16 | 17 | O processador foi implementado usando Verilog HDL e possui uma implementação multi-ciclo sem pipeline. 18 | 19 | ## Software 20 | 21 | O diretório `software` contém exemplos e testes escritos em Assembly, juntamente com seus respectivos arquivos de memória. Além disso, há um script disponível para converter código Assembly em arquivos de memória. O firmware oficial do processador também está disponível no diretório `software/firmware`. 22 | 23 | ## Testes 24 | 25 | O diretório `tests` inclui diversos testes construídos utilizando o [Iverilog](https://steveicarus.github.io/iverilog/). Todos os testes neste diretório são compatíveis com o Iverilog. 26 | 27 | ## Família Risco 5: 28 | 29 | - Baby Risco 5 - RV32E Implementação otimizada para o TinyTapeout: [https://github.com/JN513/Baby-Risco-5](https://github.com/JN513/Baby-Risco-5) 30 | - Pequeno Risco 5 - RV32I Implementação de ciclo único (Arquivada): [https://github.com/JN513/Pequeno-Risco-5/](https://github.com/JN513/Pequeno-Risco-5/) 31 | - Risco 5 - RV32I/E[M]: [https://github.com/JN513/Risco-5](https://github.com/JN513/Risco-5) 32 | - Grande Risco 5 - RV32I: [https://github.com/JN513/Grande-Risco-5](https://github.com/JN513/Grande-Risco-5) 33 | - Risco 5 Bodybuilder - RV64IMA: Ainda em fase especulativa 34 | - RISCO 5S - RV32IM Simulador escrito com a linguagem C: [https://github.com/JN513/Risco-5S](https://github.com/JN513/Risco-5S) 35 | 36 | ## Dúvidas e Sugestões 37 | 38 | A documentação oficial está disponível em: [https://jn513.github.io/Risco-5/](https://jn513.github.io/Risco-5/). Se tiver alguma dúvida ou sugestão, sinta-se à vontade para utilizar a seção de [ISSUES](https://github.com/JN513/Risco-5/issues) no GitHub. Contribuições são bem-vindas e todos os [Pull requests](https://github.com/JN513/Risco-5/pulls) serão revisados e, se possível, mesclados. 39 | 40 | ## Contribuição 41 | 42 | Se deseja contribuir com o projeto, sinta-se à vontade para fazê-lo. O arquivo [CONTRIBUTING.md](https://github.com/JN513/Risco-5/blob/main/CONTRIBUTING.md) contém as instruções necessárias. 43 | 44 | ## Licença 45 | 46 | Este projeto é licenciado sob a licença [CERN-OHL-P-2.0](https://github.com/JN513/Risco-5/blob/main/LICENSE), que concede total liberdade para uso. O software é licenciado sob a [Licença MIT](https://github.com/JN513/Risco-5/blob/main/LICENSE-MIT), e a documentação sob [CC BY-SA 4.0](https://github.com/JN513/Risco-5/blob/main/LICENSE-CC). 47 | 48 | Autor da logo: [Mateus Luck](https://www.instagram.com/mateusluck/) -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # RISCO 5 2 | 3 |

4 | Processor logo 5 |

6 | 7 | Multi-cycle processor [RISC-V](https://riscv.org/) with RV32I/E[M] implementation, developed during some days off. 8 | 9 | - **Não fala Inglês? [clique aqui](https://github.com/JN513/Risco-5/blob/main/README_pt.md)** 10 | 11 | ## Project Official Language 12 | 13 | The official language adopted by the project is Brazilian Portuguese; therefore, most of the documentation and commits are in this language. 14 | 15 | ## Processor CI 16 | 17 | [![Build Status](https://processorci.ic.unicamp.br/jenkins/buildStatus/icon?job=Risco-5)](https://processorci.ic.unicamp.br/jenkins/blue/organizations/jenkins/Risco-5/activity) 18 | 19 | ## Implementation 20 | 21 | The processor was implemented using Verilog HDL and features a multi-cycle implementation without pipelining. 22 | 23 | ## Software 24 | 25 | The `software` directory contains examples and tests written in Assembly, along with their respective memory files. Additionally, there's a script available to convert Assembly code into memory files. The official processor firmware is also available in the `software/firmware` directory. 26 | 27 | ## Tests 28 | 29 | The `tests` directory includes various tests built using [Iverilog](https://steveicarus.github.io/iverilog/). All tests in this directory are compatible with Iverilog. 30 | 31 | ## RISCO 5 Family: 32 | 33 | - Baby RISCO 5 - RV32E optimized to TinyTapeout: [https://github.com/JN513/Baby-Risco-5](https://github.com/JN513/Baby-Risco-5) 34 | - Pequeno RISCO 5 - RV32I single cycle implementation (ARCHIVED): [https://github.com/JN513/Pequeno-Risco-5/](https://github.com/JN513/Pequeno-Risco-5/) 35 | - RISCO 5 - RV32I/E[M]: [https://github.com/JN513/Risco-5](https://github.com/JN513/Risco-5) 36 | - Grande RISCO 5 - RV32I Implementation with pipeline: [https://github.com/JN513/Grande-Risco-5](https://github.com/JN513/Grande-Risco-5) 37 | - RISCO 5 Bodybuilder - RV64I: Still in speculative phase 38 | - RISCO 5S - RV32IM Simulator writing in C language: [https://github.com/JN513/Risco-5S](https://github.com/JN513/Risco-5S) 39 | 40 | ## Questions and Suggestions 41 | 42 | The official documentation is available at: [https://jn513.github.io/Risco-5/](https://jn513.github.io/Risco-5/). If you have any questions or suggestions, feel free to use the [ISSUES](https://github.com/JN513/Risco-5/issues) section on GitHub. Contributions are welcome, and all [Pull requests](https://github.com/JN513/Risco-5/pulls) will be reviewed and merged if possible. 43 | 44 | ## Contribution 45 | 46 | If you'd like to contribute to the project, please feel free to do so. The [CONTRIBUTING.md](https://github.com/JN513/Risco-5/blob/main/CONTRIBUTING.md) file contains the necessary instructions. 47 | 48 | ## License 49 | 50 | This project is licensed under the [CERN-OHL-P-2.0 license](https://github.com/JN513/Risco-5/blob/main/LICENSE), which grants full freedom for use. The software is licensed under the [MIT License](https://github.com/JN513/Risco-5/blob/main/LICENSE-MIT), and the documentation under [CC BY-SA 4.0](https://github.com/JN513/Risco-5/blob/main/LICENSE-CC). 51 | 52 | Logo author: [Mateus Luck](https://www.instagram.com/mateusluck/) 53 | -------------------------------------------------------------------------------- /docs/README.md: -------------------------------------------------------------------------------- 1 | # Documentação Risco 5 2 | 3 |

4 | Logo do processador 5 |

6 | 7 | Autor: Julio Nunes Avelar 8 | 9 | Autor da logo: [Mateus luck](https://www.instagram.com/mateusluck/) 10 | 11 | Licença Hardware: [CERN-OHL-P-2.0](https://github.com/JN513/Risco-5/blob/main/LICENSE) 12 | 13 | Licença Software: [MIT](https://github.com/JN513/Risco-5/blob/main/software/LICENSE-MIT) 14 | 15 | Licença Documentação: [CC BY-SA 4.0](https://github.com/JN513/Risco-5/blob/main/LICENSE-CC) 16 | 17 | Sinais e pinagem dos módulos: [signals.md](signals.md) 18 | 19 | Lista de instruções suportadas: [instructions.md](instructions.md) 20 | 21 | ## Familia Risco 5: 22 | 23 | - Baby Risco 5 - RV16I: Ainda especulativo 24 | - Pequeno Risco 5 - RV32I: [https://github.com/JN513/Pequeno-Risco-5/](https://github.com/JN513/Pequeno-Risco-5/) 25 | - Risco 5 - RV32I: [https://github.com/JN513/Risco-5](https://github.com/JN513/Risco-5) 26 | - Grande Risco 5 - [https://github.com/JN513/Grande-Risco-5](https://github.com/JN513/Grande-Risco-5) 27 | - Risco 5 bodybuilder - RV64I: Ainda especulativo 28 | 29 | ## Testes 30 | 31 | O diretório testes possui alguns testes para os módulos do projeto. Os testes foram feitos para serem utilizados para o [Iverilog](https://steveicarus.github.io/iverilog/), para executar os testes basta utilizar o iverilog e o vpp, como no exemplo abaixo: 32 | 33 | ```bash 34 | iverilog -o build/core_test.o -s core_tb src/core/* src/peripheral/memory.v tests/core_test.v 35 | vvp build/core_test.o 36 | ``` 37 | 38 | ## Software 39 | 40 | O diretório software possui pelo menos um exemplo em assembly para cada instrução suportada, além disso possui um arquivo de memória para cada exemplo. Na raiz do diretório está disponível um script para conversão de assembly em arquivo de memória, o mesmo pode ser utilizado como no exemplo abaixo: 41 | 42 | ```bash 43 | ./generate_mem.sh 44 | >addi 45 | ``` 46 | 47 | ## FPGA 48 | 49 | O projeto oferece suporte a teste em algumas FPGAs, sendo elas: 50 | 51 | - Colorlight i9 - ECP5 45F 52 | - Digilent Arty A7 100t 53 | - Digilent Nexys 4 DDR 54 | - Tangnano 20k 55 | - AMD/Xilinx VC709 Connectivity Kit 56 | 57 | Os exemplos estão disponíveis no diretório FPGA. Para FPGAs sipeed (Tangnano 9k e 20k) os exemplos foram feitos utilizando a IDE gowin, e para as FPGA Lattice/ColorLight os exemplos foram feitos utilizando o Yosys + NextPNR e podem ser sintetizados e flashado utilizando o makefile disponível nos diretórios, para as FPGAs Xilinx foi utilizado o Vivado e os exemplos podem ser utilizados também usando o Makefile disponível no diretório. 58 | 59 | ## Maquina de estados da unidade de controle e Esquemático 60 | 61 | **Versão PDF dos diagramas** 62 | [Maquina de estados da unidade de controle](docs/documents/risco5_state_machine.pdf) 63 | [Esquemático do processador](docs/documents/risco5_datapath.pdf) 64 | 65 | #### Maquina de estados da unidade de controle 66 | 67 | ![Maquina de estados da unidade de controle](docs/imgs/risco5_state_machine.png) 68 | 69 | #### Esquemático do processador 70 | 71 | **Esquemático atual** 72 | ![Esquemático atual do processador](docs/imgs/risco5_datapath.png) 73 | 74 | **Esquemático Inicial** 75 | ![Esquemático antigo do processador](docs/imgs/esquematico.png) 76 | 77 | ## Debug 78 | -------------------------------------------------------------------------------- /fpga/de1soc/create_project.tcl: -------------------------------------------------------------------------------- 1 | set proj_name "de1soc" 2 | set proj_dir [pwd] 3 | 4 | # Cria um novo projeto 5 | project_new -overwrite $proj_name -revision $proj_name 6 | 7 | # Configurações do projeto 8 | set_global_assignment -name FAMILY "Cyclone V" 9 | set_global_assignment -name DEVICE 5CSEMA5F31C6 10 | set_global_assignment -name TOP_LEVEL_ENTITY top 11 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY build 12 | 13 | # Adiciona arquivos Verilog ao projeto 14 | set_global_assignment -name VERILOG_FILE $proj_dir/main.v 15 | 16 | set_global_assignment -name VERILOG_FILE ../../src/core/core.v 17 | set_global_assignment -name VERILOG_FILE ../../src/core/alu_control.v 18 | set_global_assignment -name VERILOG_FILE ../../src/core/alu.v 19 | set_global_assignment -name VERILOG_FILE ../../src/core/control_unit.v 20 | set_global_assignment -name VERILOG_FILE ../../src/core/csr_unit.v 21 | set_global_assignment -name VERILOG_FILE ../../src/core/immediate_generator.v 22 | set_global_assignment -name VERILOG_FILE ../../src/core/mdu.v 23 | set_global_assignment -name VERILOG_FILE ../../src/core/mux.v 24 | set_global_assignment -name VERILOG_FILE ../../src/core/pc.v 25 | set_global_assignment -name VERILOG_FILE ../../src/core/registers.v 26 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/bus.v 27 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/fifo.v 28 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/gpio.v 29 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/gpios.v 30 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/leds.v 31 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/memory.v 32 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/soc.v 33 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/uart_rx.v 34 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/uart_tx.v 35 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/uart.v 36 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/pwm.v 37 | set_global_assignment -name VERILOG_FILE ../../debug/reset.v 38 | 39 | # Atribuições de pinos 40 | set_location_assignment PIN_AF14 -to clk 41 | set_location_assignment PIN_V16 -to led[0] 42 | set_location_assignment PIN_W16 -to led[1] 43 | set_location_assignment PIN_V17 -to led[2] 44 | set_location_assignment PIN_V18 -to led[3] 45 | set_location_assignment PIN_W17 -to led[4] 46 | set_location_assignment PIN_W19 -to led[5] 47 | set_location_assignment PIN_Y19 -to led[6] 48 | set_location_assignment PIN_W20 -to led[7] 49 | set_location_assignment PIN_W21 -to led[8] 50 | set_location_assignment PIN_Y21 -to led[9] 51 | 52 | set_location_assignment PIN_AB12 -to sw[0] 53 | set_location_assignment PIN_AC12 -to sw[1] 54 | set_location_assignment PIN_AF9 -to sw[2] 55 | set_location_assignment PIN_AF10 -to sw[3] 56 | set_location_assignment PIN_AD11 -to sw[4] 57 | set_location_assignment PIN_AD12 -to sw[5] 58 | set_location_assignment PIN_AE11 -to sw[6] 59 | set_location_assignment PIN_AC9 -to sw[7] 60 | set_location_assignment PIN_AD10 -to sw[8] 61 | set_location_assignment PIN_AE12 -to sw[9] 62 | 63 | set_location_assignment PIN_AA14 -to btn[0] 64 | set_location_assignment PIN_AA15 -to btn[1] 65 | set_location_assignment PIN_W15 -to btn[2] 66 | set_location_assignment PIN_Y16 -to btn[3] 67 | 68 | #set_location_assignment PIN_B25 -to uart_tx 69 | #set_location_assignment PIN_C25 -to uart_rx 70 | 71 | set_global_assignment -name SDC_FILE pinout.sdc -------------------------------------------------------------------------------- /docs/docs/core.en.md: -------------------------------------------------------------------------------- 1 | # Risco-5 Processor Core 2 | 3 | ## Introduction 4 | 5 | Risco-5 is a 32-bit RISC-V core that implements the basic instruction set of the RISC-V RV32I/E[M]. Risco-5 is a multi-cycle, in-order processor without a pipeline. It was designed to be simple and easy to use, making it useful in various systems. 6 | 7 | ## Source Files 8 | 9 | The Risco-5 files are available in the "core/" folder within the "src/" directory, with the top module located in the core.v file. 10 | 11 | ## Parameters 12 | 13 | | Name | Size | Description | 14 | |--------------|---------|--------------------| 15 | | BOOT_ADDRESS | 32 bits | Boot address | 16 | 17 | ## Signals 18 | 19 | | Name | Direction | Size | Description | 20 | |-------------------|-----------|---------|-------------------------------------------------------------------| 21 | | clk | input | 1 bit | Clock signal | 22 | | halt | input | 1 bit | Halts the processor execution | 23 | | reset | input | 1 bit | Reset signal | 24 | | memory_response | input | 1 bit | Memory bus response; the core waits until it is 1 | 25 | | memory_read | output | 1 bit | Enables memory read | 26 | | memory_write | output | 1 bit | Enables memory write | 27 | | write_data | output | 32 bits | Values exiting the core | 28 | | read_data | input | 32 bits | Values coming from memory | 29 | | address | output | 32 bits | Memory address | 30 | | option | output | 3 bits | Format to be read from memory | 31 | 32 | ## Instance Example 33 | 34 | Below is an example of how to instantiate the Risco-5 core in a Verilog module: 35 | 36 | ```verilog 37 | Core #( 38 | .BOOT_ADDRESS(32'h00000000) // Boot address - 32 bits 39 | ) Core_inst ( 40 | /* control */ 41 | .clk(clk), // Clock signal - 1 bit 42 | .halt(halt), // Halts the processor execution - 1 bit 43 | .reset(reset), // Reset signal - 1 bit 44 | /* Data */ 45 | .memory_response(memory_response), // Memory bus response, the core waits until it is 1 - 1 bit 46 | .memory_read(memory_read), // Enables memory read - 1 bit 47 | .memory_write(memory_write), // Enables memory write - 1 bit 48 | .write_data(write_data), // Values exiting the core - 32 bits 49 | .read_data(read_data), // Values coming from memory - 32 bits 50 | .address(address), // Memory address - 32 bits 51 | .option(option) // Format to be read from memory - 3 bits 52 | ); 53 | ``` 54 | 55 | ## Control Unit State Machine and Schematic 56 | 57 | **PDF Version of the Diagrams** 58 | [Control Unit State Machine](documents/risco5_state_machine.pdf) 59 | 60 | 61 | [Processor Schematic](documents/risco5_datapath.pdf) 62 | 63 | #### Control Unit State Machine 64 | 65 | ![Control Unit State Machine](imgs/risco5_state_machine.png) 66 | 67 | #### Processor Schematic 68 | 69 | **Current Schematic** 70 | ![Current Processor Schematic](imgs/risco5_datapath.png) 71 | 72 | **Initial Schematic** 73 | ![Old Processor Schematic](imgs/esquematico.png) -------------------------------------------------------------------------------- /docs/docs/core.md: -------------------------------------------------------------------------------- 1 | # Risco-5 Processor Core 2 | 3 | ## Introdução 4 | 5 | O Risco-5 é um core RISC-V de 32 bits que implementa o conjunto de instruções básicas do RISC-V RV32I/E[M]. O Risco-5 é um processador multiciclo, com execução em ordem e sem pipeline. Foi projetado para ser simples e de fácil utilização, sendo útil nos mais diversos sistemas. 6 | 7 | ## Arquivos Fonte 8 | 9 | Os arquivos do Risco-5 estão disponíveis na pasta "core/" dentro da pasta "src/", com o top model estando disponível no arquivo core.v. 10 | 11 | ## Parâmetros 12 | 13 | | Nome | Tamanho | Descrição | 14 | |----------------|---------|------------------------| 15 | | BOOT_ADDRESS | 32 bits | Endereço de boot | 16 | 17 | ## Sinais 18 | 19 | | Nome | Direção | Tamanho | Descrição | 20 | |---------------------|---------|---------|----------------------------------------------------------------------| 21 | | clk | input | 1 bit | Sinal de clock | 22 | | halt | input | 1 bit | Para a execução do processador | 23 | | reset | input | 1 bit | Sinal de reset | 24 | | memory_response | input | 1 bit | Resposta do barramento de memória; o core espera até que seja 1 | 25 | | memory_read | output | 1 bit | Habilita leitura na memória | 26 | | memory_write | output | 1 bit | Habilita escrita na memória | 27 | | write_data | output | 32 bits | Valores saindo do core | 28 | | read_data | input | 32 bits | Valores vindos da memória | 29 | | address | output | 32 bits | Endereço de memória | 30 | | option | output | 3 bits | Formato a ser lido da memória | 31 | 32 | ## Exemplo de Instância 33 | 34 | A seguir está um exemplo de como instanciar o core Risco-5 em um módulo Verilog: 35 | 36 | ```verilog 37 | Core #( 38 | .BOOT_ADDRESS(32'h00000000) // Endereço de boot - 32 bits 39 | ) Core_inst ( 40 | /* controle */ 41 | .clk(clk), // Sinal de clock - 1 bit 42 | .halt(halt), // Para a execução do processador - 1 bit 43 | .reset(reset), // Sinal de reset - 1 bit 44 | /* Dados */ 45 | .memory_response(memory_response), // Resposta do barramento de memória, o core espera até que seja 1 - 1 bit 46 | .memory_read(memory_read), // Habilita leitura na memória - 1 bit 47 | .memory_write(memory_write), // Habilita escrita na memória - 1 bit 48 | .write_data(write_data), // Valores saindo do core - 32 bits 49 | .read_data(read_data), // Valores vindo da memória - 32 bits 50 | .address(address), // Endereço de memória - 32 bits 51 | .option(option) // Formato a ser lido da memória - 3 bits 52 | ); 53 | ``` 54 | ## Maquina de estados da unidade de controle e Esquemático 55 | 56 | **Versão PDF dos diagramas** 57 | [Maquina de estados da unidade de controle](documents/risco5_state_machine.pdf) 58 | 59 | 60 | [Esquemático do processador](documents/risco5_datapath.pdf) 61 | 62 | #### Maquina de estados da unidade de controle 63 | 64 | ![Maquina de estados da unidade de controle](imgs/risco5_state_machine.png) 65 | 66 | #### Esquemático do processador 67 | 68 | **Esquemático atual** 69 | ![Esquemático atual do processador](imgs/risco5_datapath.png) 70 | 71 | **Esquemático Inicial** 72 | ![Esquemático antigo do processador](imgs/esquematico.png) 73 | -------------------------------------------------------------------------------- /fpga/cyclone10gx/cyclone10_gx.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2024 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the Intel FPGA Software License Subscription Agreements 16 | # on the Quartus Prime software download page. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 24.1.0 Build 115 03/21/2024 SC Pro Edition 22 | # Date created = 11:07:47 June 18, 2024 23 | # 24 | # -------------------------------------------------------------------------- # 25 | set_global_assignment -name TOP_LEVEL_ENTITY top 26 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 23.1.0 27 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:07:47 JUNE 18, 2024" 28 | set_global_assignment -name LAST_QUARTUS_VERSION "23.1.0 Pro Edition" 29 | set_global_assignment -name FAMILY "Cyclone 10 GX" 30 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY build 31 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 32 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 33 | set_global_assignment -name DEVICE 10CX220YF780E5G 34 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 35 | set_global_assignment -name VERILOG_FILE main.v 36 | set_global_assignment -name VERILOG_FILE ../../src/core/core.v 37 | set_global_assignment -name VERILOG_FILE ../../src/core/alu_control.v 38 | set_global_assignment -name VERILOG_FILE ../../src/core/alu.v 39 | set_global_assignment -name VERILOG_FILE ../../src/core/control_unit.v 40 | set_global_assignment -name VERILOG_FILE ../../src/core/csr_unit.v 41 | set_global_assignment -name VERILOG_FILE ../../src/core/immediate_generator.v 42 | set_global_assignment -name VERILOG_FILE ../../src/core/mdu.v 43 | set_global_assignment -name VERILOG_FILE ../../src/core/mux.v 44 | set_global_assignment -name VERILOG_FILE ../../src/core/pc.v 45 | set_global_assignment -name VERILOG_FILE ../../src/core/registers.v 46 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/bus.v 47 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/fifo.v 48 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/gpio.v 49 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/gpios.v 50 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/leds.v 51 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/memory.v 52 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/soc.v 53 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/uart_rx.v 54 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/uart_tx.v 55 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/uart.v 56 | set_global_assignment -name VERILOG_FILE ../../src/peripheral/pwm.v 57 | set_global_assignment -name VERILOG_FILE ../../debug/reset.v 58 | set_location_assignment PIN_J23 -to clk 59 | set_location_assignment PIN_AF6 -to led 60 | set_instance_assignment -name IO_STANDARD "1.8 V" -to led -entity top 61 | set_instance_assignment -name IO_STANDARD "1.8 V" -to clk -entity top 62 | set_global_assignment -name SDC_FILE pinout.sdc 63 | -------------------------------------------------------------------------------- /tests/alu_test.v: -------------------------------------------------------------------------------- 1 | module alu_tb(); 2 | 3 | reg [31:0] input_A, input_B; 4 | wire [31:0] res; 5 | reg [3:0] operation; 6 | reg clk; 7 | wire zr; 8 | 9 | 10 | ALU u1( 11 | .operation(operation), 12 | .ALU_in_X(input_A), 13 | .ALU_in_Y(input_B), 14 | .ALU_out_S(res), 15 | .ZR(zr) 16 | ); 17 | 18 | initial begin 19 | $dumpfile("build/alu.vcd"); 20 | $dumpvars; 21 | clk = 0; 22 | operation = 4'b0000; 23 | 24 | #10 25 | 26 | $display("Teste soma: \n"); 27 | 28 | input_A = 32'd2565; 29 | input_B = 32'd1560; 30 | operation = 4'b0010; 31 | 32 | #1 33 | 34 | $display("resultado %d", res); 35 | if(res == 32'd4125) begin 36 | $display("Correto"); 37 | end else begin 38 | $display("Incorreto"); 39 | end 40 | 41 | #1 42 | 43 | $display("\nTeste AND: \n"); 44 | 45 | input_A = 32'd2565; 46 | input_B = 32'd1560; 47 | operation = 4'b0000; 48 | 49 | #1 50 | 51 | $display("primeiro: %b", input_A); 52 | $display("segundo: %b", input_B); 53 | $display("resultado %b", res); 54 | 55 | if(res == 32'b00000000000000000000001000000000) begin 56 | $display("Correto"); 57 | end else begin 58 | $display("Incorreto"); 59 | end 60 | 61 | #1 62 | 63 | $display("Teste subtração: \n"); 64 | 65 | input_A = 32'd2565; 66 | input_B = 32'd1560; 67 | operation = 4'b0110; 68 | 69 | #1 70 | 71 | $display("resultado %d", res); 72 | if(res == 32'd1005) begin 73 | $display("Correto"); 74 | end else begin 75 | $display("Incorreto"); 76 | end 77 | 78 | #1 79 | 80 | $display("Teste subtração 2: \n"); 81 | 82 | input_A = 32'd2565; 83 | input_B = -3560; 84 | operation = 4'b0110; 85 | 86 | #1 87 | 88 | $display("resultado %d", res); 89 | if(res == 32'd6125) begin 90 | $display("Correto"); 91 | end else begin 92 | $display("Incorreto"); 93 | end 94 | 95 | #1 96 | 97 | $display("Teste subtração 3: \n"); 98 | 99 | input_A = 32'd2565; 100 | input_B = 32'd3560; 101 | operation = 4'b0110; 102 | 103 | #1 104 | 105 | $display("resultado %d", res); 106 | if(res == 32'd4294966301) begin 107 | $display("Correto"); 108 | end else begin 109 | $display("Incorreto"); 110 | end 111 | 112 | #1 113 | 114 | $display("\nTeste OR: \n"); 115 | 116 | input_A = 32'd2565; 117 | input_B = 32'd1560; 118 | operation = 4'b0001; 119 | 120 | #1 121 | 122 | $display("primeiro: %b", input_A); 123 | $display("segundo: %b", input_B); 124 | $display("resultado %b", res); 125 | 126 | if(res == 32'b00000000000000000000111000011101) begin 127 | $display("Correto"); 128 | end else begin 129 | $display("Incorreto"); 130 | end 131 | 132 | #1 133 | 134 | $display("\nTeste NOR: \n"); 135 | 136 | input_A = 32'd2565; 137 | input_B = 32'd1560; 138 | operation = 4'b1100; 139 | 140 | #1 141 | 142 | $display("primeiro: %b", input_A); 143 | $display("segundo: %b", input_B); 144 | $display("resultado %b", res); 145 | 146 | if(res == 32'b11111111111111111111000111100010) begin 147 | $display("Correto"); 148 | end else begin 149 | $display("Incorreto"); 150 | end 151 | 152 | #1 153 | 154 | $display("\nTeste SLT: \n"); 155 | 156 | input_A = 32'd2565; 157 | input_B = 32'd1560; 158 | operation = 4'b0111; 159 | 160 | #1 161 | 162 | $display("primeiro: %b", input_A); 163 | $display("segundo: %b", input_B); 164 | $display("resultado %b", res); 165 | 166 | if(res == 32'h0) begin 167 | $display("Correto"); 168 | end else begin 169 | $display("Incorreto"); 170 | end 171 | 172 | end 173 | 174 | endmodule 175 | -------------------------------------------------------------------------------- /software/firmware/src/conversion.s: -------------------------------------------------------------------------------- 1 | .globl atoi 2 | .globl itoa 3 | 4 | atoi: # recebe a string a ser convertida e retorna um inteiro - int atoi (const char *str); 5 | addi t0, zero, 0 # t0 = 0 (resultado) 6 | addi t1, zero, 0 # t1 = 0 (sinal: 0 = positivo, 1 = negativo) 7 | addi t2, zero, 0 # t2 = 0 (índice da string) 8 | addi t5, zero, 10 # t5 = 10 (multiplicador para conversão de caractere para dígito) 9 | 10 | atoi_loop: 11 | lbu t3, 0(a0) # Carregar o byte atual da string 12 | 13 | beqz t3, atoi_done # Se caractere nulo, terminar 14 | 15 | # Ignorar espaços em branco 16 | li t4, 32 # Código ASCII para espaço 17 | beq t3, t4, atoi_skip 18 | 19 | # Verificar o sinal 20 | li t4, 45 # Código ASCII para '-' 21 | beq t3, t4, atoi_negative 22 | li t4, 43 # Código ASCII para '+' 23 | beq t3, t4, atoi_skip 24 | 25 | # Verificar se é um dígito 26 | li t4, 48 # Código ASCII para '0' 27 | blt t3, t4, atoi_done # Se menor que '0', terminar 28 | li t4, 57 # Código ASCII para '9' 29 | bgt t3, t4, atoi_done # Se maior que '9', terminar 30 | 31 | # Converter caractere para dígito e atualizar resultado 32 | li t4, 48 33 | sub t3, t3, t4 # t3 = t3 - '0' 34 | mul t0, t0, t5 # resultado = resultado * 10 35 | add t0, t0, t3 # resultado = resultado + (t3 - '0') 36 | 37 | atoi_skip: 38 | addi a0, a0, 1 # Avançar para o próximo caractere 39 | j atoi_loop 40 | 41 | atoi_negative: 42 | addi t1, zero, 1 # Definir sinal como negativo 43 | j atoi_skip 44 | 45 | atoi_done: 46 | # Aplicar sinal negativo se necessário 47 | beq t1, zero, atoi_return 48 | sub t0, zero, t0 # resultado = -resultado 49 | 50 | atoi_return: 51 | mv a0, t0 # Retornar resultado em a0 52 | ret 53 | 54 | itoa: # recebe um inteiro, o buffer a ser escrito e a base para conversão - char *itoa ( int value, char *str, int base ); 55 | addi sp, sp, -4 # Reservar espaço na pilha 56 | sw a1, 0(sp) # Salvar ponteiro para string 57 | 58 | # Inicializar variáveis 59 | addi t1, zero, 0 # t1 = 0 (sinal: 0 = positivo, 1 = negativo) 60 | addi t6, zero, 10 # t6 = 10 (verificador se numero ou letra) 61 | 62 | # Verificar o sinal 63 | blt a0, zero, itoa_negative 64 | j itoa_abs_done 65 | 66 | itoa_negative: 67 | addi t1, zero, 1 # t1 = 1 (negativo) 68 | neg a0, a0 # t3 = -t3 69 | 70 | itoa_abs_done: 71 | mv t2, a0 # t2 = valor absoluto 72 | 73 | itoa_convert_loop: 74 | beqz t2, itoa_convert_done # Se valor for zero, terminar 75 | 76 | rem t3, t2, a2 # t3 = t2 % base 77 | div t2, t2, a2 # t2 = t2 / base 78 | 79 | blt t3, t6, itoa_convert_number 80 | 81 | addi t3, t3, 87 # t3 = t3 + 87 (correção para letras) 82 | 83 | j itoa_convert_store 84 | 85 | itoa_convert_number: 86 | addi t3, t3, 48 # t3 = t3 + '0' 87 | 88 | itoa_convert_store: 89 | sb t3, 0(a1) # Armazenar caractere na string 90 | addi a1, a1, 1 # Avançar para o próximo caractere 91 | j itoa_convert_loop 92 | 93 | itoa_convert_done: 94 | beq t1, zero, itoa_finish # Se positivo, retornar 95 | li t3, 45 # t3 = '-' 96 | sb t3, 0(a1) # Adicionar sinal negativo 97 | addi a1, a1, 1 # Avançar para o próximo caractere 98 | sb zero, 0(a1) # Adicionar terminador nulo 99 | addi a1, a1, -1 # Avançar para o próximo caractere 100 | 101 | itoa_finish: 102 | lw t6, 0(sp) # ponteiro inicial da string 103 | 104 | itoa_invert_loop: 105 | lbu t4, 0(a1); 106 | lbu t5, 0(t6); 107 | 108 | sb t5, 0(a1); 109 | sb t4, 0(t6); 110 | 111 | addi a1, a1, -1; 112 | addi t6, t6, 1; 113 | 114 | bge t6, a1, itoa_return; 115 | j itoa_invert_loop; 116 | 117 | itoa_return: 118 | lw a0, 0(sp) # Restaurar ponteiro para string 119 | addi sp, sp, 44 # Liberar espaço na pilha 120 | 121 | ret 122 | -------------------------------------------------------------------------------- /software/memory/program.hex: -------------------------------------------------------------------------------- 1 | 00008137 2 | 00000293 3 | 00004437 4 | 3e0000ef 5 | 12c000ef 6 | 00000293 7 | 00054303 8 | 00030863 9 | 00128293 10 | 00150513 11 | ff1ff06f 12 | 00028513 13 | 00008067 14 | 00050293 15 | 0005c303 16 | 00030a63 17 | 00650023 18 | 00150513 19 | 00158593 20 | fedff06f 21 | 00050023 22 | 00008067 23 | 00054283 24 | 0005c303 25 | 00629c63 26 | 00028e63 27 | 02030063 28 | 00150513 29 | 00158593 30 | fe5ff06f 31 | 40628533 32 | 0100006f 33 | fff00513 34 | 0080006f 35 | 00100513 36 | 00008067 37 | 00050293 38 | 00054303 39 | 00030663 40 | 00150513 41 | ff5ff06f 42 | 0005c303 43 | 00650023 44 | 00030863 45 | 00150513 46 | 00158593 47 | fedff06f 48 | 00028513 49 | 00008067 50 | 00050293 51 | 00000393 52 | 0005a303 53 | 00652023 54 | 00138393 55 | 00d38863 56 | 00150513 57 | 00158593 58 | fe9ff06f 59 | 00028513 60 | 00008067 61 | 00050293 62 | 00000393 63 | 00b52023 64 | 00138393 65 | 00c38663 66 | 00150513 67 | ff1ff06f 68 | 00028513 69 | 00008067 70 | 00000293 71 | 00001337 72 | 04730313 73 | 00a2dc63 74 | 00128293 75 | 00000393 76 | 00138393 77 | fe63d8e3 78 | ff9ff06f 79 | 00008067 80 | 0000006f 81 | 80000337 82 | 00430313 83 | 00032503 84 | 00008067 85 | 80000337 86 | 00830313 87 | 00032503 88 | 00008067 89 | 80000337 90 | 00c30313 91 | 00032503 92 | 00008067 93 | 80000337 94 | 01030313 95 | 00032503 96 | 00008067 97 | 80000337 98 | 00032503 99 | 00008067 100 | 80000337 101 | 00a32023 102 | 00008067 103 | 80000337 104 | 00a00293 105 | 00000393 106 | 00032e03 107 | 01c52023 108 | 00150513 109 | 00138393 110 | 005e0663 111 | 00b38463 112 | fe9ff06f 113 | 00038513 114 | 00008067 115 | 80000337 116 | 800003b7 117 | 01038393 118 | 00a00293 119 | 0003ae03 120 | fe0e1ee3 121 | 00052e03 122 | 01c32023 123 | 00150513 124 | 005e0663 125 | 000e0463 126 | fe5ff06f 127 | 00008067 128 | 00000293 129 | 00000313 130 | 00000393 131 | 00a00f13 132 | 00054e03 133 | 040e0663 134 | 02000e93 135 | 03de0a63 136 | 02d00e93 137 | 03de0a63 138 | 02b00e93 139 | 03de0263 140 | 03000e93 141 | 03de4663 142 | 03900e93 143 | 03cec263 144 | 03000e93 145 | 41de0e33 146 | 03e282b3 147 | 01c282b3 148 | 00150513 149 | fbdff06f 150 | 00100313 151 | ff5ff06f 152 | 00030463 153 | 405002b3 154 | 00028513 155 | 00008067 156 | ffc10113 157 | 00b12023 158 | 00000313 159 | 00a00f93 160 | 00054463 161 | 00c0006f 162 | 00100313 163 | 40a00533 164 | 00050393 165 | 02038463 166 | 02c3ee33 167 | 02c3c3b3 168 | 01fe4663 169 | 057e0e13 170 | 0080006f 171 | 030e0e13 172 | 01c58023 173 | 00158593 174 | fddff06f 175 | 00030c63 176 | 02d00e13 177 | 01c58023 178 | 00158593 179 | 00058023 180 | fff58593 181 | 00012f83 182 | 0005ce83 183 | 000fcf03 184 | 01e58023 185 | 01df8023 186 | fff58593 187 | 001f8f93 188 | 00bfd463 189 | fe5ff06f 190 | 00012503 191 | 02c10113 192 | 00008067 193 | fe010113 194 | 00812e23 195 | 02010413 196 | fea42623 197 | 017d87b7 198 | 84078713 199 | fec42783 200 | 02f747b3 201 | 00078513 202 | 01c12403 203 | 02010113 204 | 00008067 205 | fe010113 206 | 00812e23 207 | 02010413 208 | fea42623 209 | feb42423 210 | fec42703 211 | fe842783 212 | 02f707b3 213 | 41f7d693 214 | 00010737 215 | fff70713 216 | 00e6f733 217 | 00f707b3 218 | 4107d793 219 | 00078513 220 | 01c12403 221 | 02010113 222 | 00008067 223 | c0000337 224 | 00a32023 225 | 00008067 226 | c0000337 227 | 00430313 228 | 00a32023 229 | 00008067 230 | c0000337 231 | 00032503 232 | 00008067 233 | 40000337 234 | 00a32023 235 | 00008067 236 | c0000337 237 | 00c30313 238 | 01059593 239 | 00b56533 240 | 00a32023 241 | 00008067 242 | c0000337 243 | 01030313 244 | 01059593 245 | 00b56533 246 | 00a32023 247 | 00008067 248 | c0000337 249 | 00830313 250 | 00a32023 251 | 00008067 252 | fe010113 253 | 00112e23 254 | 00812c23 255 | 02010413 256 | 0cc00513 257 | fa1ff0ef 258 | 00300513 259 | fd5ff0ef 260 | 3e800513 261 | ef1ff0ef 262 | fea42623 263 | 00000593 264 | fec42503 265 | f8dff0ef 266 | 0000a7b7 267 | c4078593 268 | fec42503 269 | f01ff0ef 270 | fea42423 271 | 00000593 272 | fe842503 273 | f85ff0ef 274 | 00000793 275 | 00078513 276 | 01c12083 277 | 01812403 278 | 02010113 279 | 00008067 280 | -------------------------------------------------------------------------------- /fpga/digilent_arty/program.hex: -------------------------------------------------------------------------------- 1 | 00008137 2 | 00000293 3 | 00004437 4 | 3e0000ef 5 | 12c000ef 6 | 00000293 7 | 00054303 8 | 00030863 9 | 00128293 10 | 00150513 11 | ff1ff06f 12 | 00028513 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