├── .atom-build.yaml ├── .gitignore ├── README.md ├── thermo.c ├── stm8l.h ├── thermo.hex ├── LICENSE └── STM8L052C6.h /.atom-build.yaml: -------------------------------------------------------------------------------- 1 | cmd: "./build.sh" 2 | name: "Build with sdcc" 3 | sh: true, 4 | atomCommandName: builder:sdccbuild 5 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Object files 5 | *.o 6 | *.ko 7 | *.obj 8 | *.elf 9 | 10 | # Linker output 11 | *.ilk 12 | *.map 13 | *.exp 14 | 15 | # Precompiled Headers 16 | *.gch 17 | *.pch 18 | 19 | # Libraries 20 | *.lib 21 | *.a 22 | *.la 23 | *.lo 24 | 25 | # Shared objects (inc. Windows DLLs) 26 | *.dll 27 | *.so 28 | *.so.* 29 | *.dylib 30 | 31 | # Executables 32 | *.exe 33 | *.out 34 | *.app 35 | *.i*86 36 | *.x86_64 37 | #*.hex 38 | 39 | # Debug files 40 | *.dSYM/ 41 | *.su 42 | *.idb 43 | *.pdb 44 | 45 | # Kernel Module Compile Results 46 | *.mod* 47 | *.cmd 48 | .tmp_versions/ 49 | modules.order 50 | Module.symvers 51 | Mkfile.old 52 | dkms.conf 53 | 54 | 55 | # SDCC Output 56 | *.asm 57 | *.cdb 58 | #*.hex 59 | *.lk 60 | *.lst 61 | *.map 62 | *.rel 63 | *.rst 64 | *.sym 65 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Model-N Thermostat Firmware 2 | STM8 Firmware replacement for the popular Model N radiator thermostats (sold under the eQ-3 eqiva brand). It provides a UART interface through the MP1(PA3) and MP2(PA2) pads on the board, intended to be controlled from an additional controller/system. For example an ESP8266 or ESP32 to provide WLAN and Bluetooth 4.0 connectivity. 3 | The stock LCD and buttons are not implemented (so far). 4 | 5 | ### Build 6 | SDCC is recommended for compiling the code. It can be executed with the correct arguments through the `build.sh` script. A build config is also included to conveniently use the Atom Editor with build plugin. 7 | 8 | ### Flashing 9 | Connect a ST-Link V2 to corresponding PRG1 (SWIM) pads on the board. Then flash the `thermo.hex` onto the STM8L052C6. 10 | Important Note: stm8flash requires to specify stm8l152c6 as part instead of stm8l052c6 for it to work, so use: `stm8flash -c stlinkv2 -p stm8l152c6 -w thermo.hex` 11 | 12 | ### UART interface 13 | (coming soon) 14 | 15 | ### Credits 16 | Schematic (thanks!): https://www.mikrocontroller.net/topic/359741 17 | -------------------------------------------------------------------------------- /thermo.c: -------------------------------------------------------------------------------- 1 | #include "STM8L052C6.h" 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | #define UART_BUFFER_SIZE 32 9 | 10 | #define MP1 (1 << 2) 11 | 12 | #define MOTO_E7 (1 << 7) 13 | #define MOTO_E6 (1 << 6) 14 | #define SEN_C3 (1 << 3) 15 | #define MOTO_C4 (1 << 4) 16 | #define MOTO_C7 (1 << 7) 17 | 18 | 19 | uint16_t count = 0; 20 | uint8_t uartBufferPos = 0; 21 | char uartBuffer[UART_BUFFER_SIZE]; 22 | bool motorDir = false; 23 | volatile uint32_t tim2_millis = 0; 24 | 25 | uint32_t millis() { 26 | return tim2_millis; 27 | } 28 | 29 | void delay_ms(uint32_t ms) { 30 | uint32_t start = millis(); 31 | while ((millis() - start) < ms); 32 | } 33 | 34 | void initTIM2() { 35 | // 16000 ticks 36 | TIM2_ARRH = 0x3E; 37 | TIM2_ARRL = 0x80; 38 | //TIM2_PSCR = 0b010; 39 | 40 | TIM2_IER |= 0x1; // Update interrupt 41 | TIM2_CR1 = 0x1; // enable timer 42 | } 43 | 44 | 45 | void initMotor() { 46 | // 1. H-Bridge 47 | PE_DDR |= MOTO_E7 | MOTO_E6; 48 | PE_CR1 |= MOTO_E7 | MOTO_E6; 49 | PE_ODR |= MOTO_E7 | MOTO_E6; 50 | 51 | // 2. H-Bridge 52 | PC_DDR |= MOTO_C4 | MOTO_C7; 53 | PC_CR1 |= MOTO_C4 | MOTO_C7; 54 | PC_ODR |= MOTO_C4 | MOTO_C7; 55 | 56 | } 57 | 58 | void setMotor(bool st1, bool st2) { 59 | if (st1) { 60 | PE_ODR &= ~MOTO_E7 & ~MOTO_E6; // 3.3V 61 | } else { 62 | PE_ODR |= MOTO_E7 | MOTO_E6; // 0V 63 | } 64 | if (st2) { 65 | PC_ODR &= ~MOTO_C4 & ~MOTO_C7; // 3.3V 66 | } else { 67 | PC_ODR |= MOTO_C4 | MOTO_C7; // 0V 68 | } 69 | 70 | } 71 | 72 | 73 | void initUSART() { 74 | SYSCFG_RMPCR1 |= 0x10; // TX: PA2, RX: PA3 75 | PA_DDR |= MP1; 76 | PA_CR1 |= MP1; 77 | 78 | USART1_CR2 = USART_CR2_TEN | USART_CR2_REN | USART_CR2_RIEN; // Transmit, receive, interrrupt enable 79 | USART1_CR3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit 80 | USART1_BRR1 = 0x11; USART1_BRR2 = 0x6; // 57600 baud (use 8 B for 115200) 81 | } 82 | 83 | int uartWrite(const char *str) { 84 | char i; 85 | for(i = 0; i < strlen(str); i++) { 86 | while(!(USART1_SR & USART_SR_TXE)); 87 | USART1_DR = str[i]; 88 | } 89 | return(i); // Bytes sent 90 | } 91 | 92 | void putchar(unsigned char data) { 93 | USART1_DR = data; 94 | while (!(USART1_SR & USART_SR_TC)); 95 | } 96 | 97 | char uartRead() { 98 | if(USART1_SR & USART_SR_RXNE) { 99 | return USART1_DR; 100 | } else { 101 | return '\0'; 102 | } 103 | } 104 | 105 | void clearUartBuffer() { 106 | uartBufferPos = 0; 107 | memset(uartBuffer,0,UART_BUFFER_SIZE); 108 | } 109 | 110 | 111 | void initADC() { 112 | ADC1_SQR1 |= ADC1_SQR1_DMAOFF; // disable DMA 113 | ADC1_SQR4 |= (1 << 5); // Select ADC 5 (PC3) 114 | ADC1_CR1 |= ADC1_CR1_ADON; // wake up 115 | // ADC1_CR1 &= ~ADC1_CR1_ADON; // off 116 | } 117 | 118 | uint16_t readADC() { 119 | uint8_t adcH, adcL; 120 | ADC1_CR1 |= ADC1_CR1_START; // start 121 | while (!(ADC1_SR & ADC1_SR_EOC)); 122 | adcH = ADC1_DRH; 123 | adcL = ADC1_DRL; 124 | //ADC1_CSR &= ~(1 << ADC1_CSR_EOC); // Clear EOC flag 125 | return (adcL | (adcH << 8)); 126 | } 127 | 128 | 129 | void initClock() { 130 | CLK_CKDIVR = 0; // Set the frequency to 16 MHz 131 | CLK_PCKENR1 = 0xFF; // Enable peripherals 132 | CLK_PCKENR2 = 0xFF; 133 | } 134 | 135 | 136 | int main() { 137 | initClock(); 138 | 139 | initTIM2(); 140 | 141 | enableInterrupts() 142 | 143 | initADC(); 144 | 145 | initUSART(); 146 | 147 | initMotor(); 148 | 149 | printf("Thermostat: Startup complete\n"); 150 | 151 | while(true) { 152 | uint16_t adc, t; 153 | 154 | delay_ms(1000); 155 | 156 | if (uartBuffer[0] == 'b') { 157 | motorDir = false; 158 | memmove(uartBuffer, uartBuffer+1, strlen(uartBuffer)); 159 | count = atoi(uartBuffer); 160 | } else if (uartBuffer[0] == 'f') { 161 | motorDir = true; 162 | memmove(uartBuffer, uartBuffer+1, strlen(uartBuffer)); 163 | count = atoi(uartBuffer); 164 | } 165 | clearUartBuffer(); 166 | 167 | adc = readADC(); 168 | t = tim2_millis/100; 169 | printf("ADC value: %d, Time: %u\n", readADC(), (uint16_t)(millis()/100)); 170 | 171 | if (count > 0) { 172 | printf("Running %s for %d.%d sec\n", (motorDir? "forward" : "backward"), count/10, count%10); 173 | setMotor(motorDir, !motorDir); 174 | count--; 175 | } else { 176 | setMotor(0, 0); 177 | } 178 | } 179 | } 180 | 181 | #define UART_RECV_ISR 28 182 | #define TIM2_OVF_ISR 19 183 | 184 | void uart_isr() __interrupt(UART_RECV_ISR) { 185 | uint8_t i; 186 | uartBufferPos %= UART_BUFFER_SIZE-1; 187 | for(i = uartBufferPos; i < UART_BUFFER_SIZE; i++) { 188 | uartBuffer[i] = uartRead(); 189 | } 190 | uartBufferPos++; 191 | } 192 | 193 | void tim2_isr() __interrupt(TIM2_OVF_ISR) { 194 | TIM2_SR1 = 0; 195 | tim2_millis++; 196 | } 197 | -------------------------------------------------------------------------------- /stm8l.h: -------------------------------------------------------------------------------- 1 | 2 | //#include "compiler.h" 3 | #define _SFR_(mem_addr, name) (#define name (*(volatile uint8_t *)(0x5000 + (mem_addr)))) 4 | 5 | /* GPIO */ 6 | #define PA_ODR *(unsigned char*)0x5000 7 | #define PA_IDR *(unsigned char*)0x5001 8 | #define PA_DDR *(unsigned char*)0x5002 9 | #define PA_CR1 *(unsigned char*)0x5003 10 | #define PA_CR2 *(unsigned char*)0x5004 11 | 12 | #define PB_ODR *(unsigned char*)0x5005 13 | #define PB_IDR *(unsigned char*)0x5006 14 | #define PB_DDR *(unsigned char*)0x5007 15 | #define PB_CR1 *(unsigned char*)0x5008 16 | #define PB_CR2 *(unsigned char*)0x5009 17 | 18 | #define PC_ODR *(unsigned char*)0x500A 19 | #define PC_IDR *(unsigned char*)0x500B 20 | #define PC_DDR *(unsigned char*)0x500C 21 | #define PC_CR1 *(unsigned char*)0x500D 22 | #define PC_CR2 *(unsigned char*)0x500E 23 | 24 | #define PD_ODR *(unsigned char*)0x500F 25 | #define PD_IDR *(unsigned char*)0x5010 26 | #define PD_DDR *(unsigned char*)0x5011 27 | #define PD_CR1 *(unsigned char*)0x5012 28 | #define PD_CR2 *(unsigned char*)0x5013 29 | 30 | #define PE_ODR *(unsigned char*)0x5014 31 | #define PE_IDR *(unsigned char*)0x5015 32 | #define PE_DDR *(unsigned char*)0x5016 33 | #define PE_CR1 *(unsigned char*)0x5017 34 | #define PE_CR2 *(unsigned char*)0x5018 35 | 36 | #define PF_ODR *(unsigned char*)0x5019 37 | #define PF_IDR *(unsigned char*)0x501A 38 | #define PF_DDR *(unsigned char*)0x501B 39 | #define PF_CR1 *(unsigned char*)0x501C 40 | #define PF_CR2 *(unsigned char*)0x501D 41 | 42 | /* CLOCK */ 43 | #define CLK_DIVR *(unsigned char*)0x50C0 44 | #define CLK_CRTCR *(unsigned char*)0x50C1 45 | #define CLK_ICKR *(unsigned char*)0x50C2 46 | #define CLK_PCKENR1 *(unsigned char*)0x50C3 47 | #define CLK_PCKENR2 *(unsigned char*)0x50C4 48 | #define CLK_CCOR *(unsigned char*)0x50C5 49 | #define CLK_ECKR *(unsigned char*)0x50C6 50 | #define CLK_SCSR *(unsigned char*)0x50C7 51 | #define CLK_SWR *(unsigned char*)0x50C8 52 | #define CLK_SWCR *(unsigned char*)0x50C9 53 | #define CLK_CSSR *(unsigned char*)0x50CA 54 | #define CLK_CBEEPR *(unsigned char*)0x50CB 55 | #define CLK_HSICALR *(unsigned char*)0x50CC 56 | #define CLK_HSITRIMR *(unsigned char*)0x50CD 57 | #define CLK_HSIUNLCKR *(unsigned char*)0x50CE 58 | #define CLK_REGCSR *(unsigned char*)0x50CF 59 | 60 | 61 | /* ------------------- USART ------------------- */ 62 | #define USART1_SR *(unsigned char*)0x5230 63 | #define USART1_DR *(unsigned char*)0x5231 64 | #define USART1_BRR1 *(unsigned char*)0x5232 65 | #define USART1_BRR2 *(unsigned char*)0x5233 66 | #define USART1_CR1 *(unsigned char*)0x5234 67 | #define USART1_CR2 *(unsigned char*)0x5235 68 | #define USART1_CR3 *(unsigned char*)0x5236 69 | #define USART1_CR4 *(unsigned char*)0x5237 70 | #define USART1_CR5 *(unsigned char*)0x5238 71 | #define USART1_GTR *(unsigned char*)0x5239 72 | #define USART1_PSCR *(unsigned char*)0x523A 73 | 74 | /* USART_CR1 bits */ 75 | #define USART_CR1_R8 (1 << 7) 76 | #define USART_CR1_T8 (1 << 6) 77 | #define USART_CR1_UARTD (1 << 5) 78 | #define USART_CR1_M (1 << 4) 79 | #define USART_CR1_WAKE (1 << 3) 80 | #define USART_CR1_PCEN (1 << 2) 81 | #define USART_CR1_PS (1 << 1) 82 | #define USART_CR1_PIEN (1 << 0) 83 | 84 | /* USART_CR2 bits */ 85 | #define USART_CR2_TIEN (1 << 7) 86 | #define USART_CR2_TCIEN (1 << 6) 87 | #define USART_CR2_RIEN (1 << 5) 88 | #define USART_CR2_ILIEN (1 << 4) 89 | #define USART_CR2_TEN (1 << 3) 90 | #define USART_CR2_REN (1 << 2) 91 | #define USART_CR2_RWU (1 << 1) 92 | #define USART_CR2_SBK (1 << 0) 93 | 94 | /* USART_CR3 bits */ 95 | #define USART_CR3_LINEN (1 << 6) 96 | #define USART_CR3_STOP2 (1 << 5) 97 | #define USART_CR3_STOP1 (1 << 4) 98 | #define USART_CR3_CLKEN (1 << 3) 99 | #define USART_CR3_CPOL (1 << 2) 100 | #define USART_CR3_CPHA (1 << 1) 101 | #define USART_CR3_LBCL (1 << 0) 102 | 103 | /* USART_SR bits */ 104 | #define USART_SR_TXE (1 << 7) 105 | #define USART_SR_TC (1 << 6) 106 | #define USART_SR_RXNE (1 << 5) 107 | #define USART_SR_IDLE (1 << 4) 108 | #define USART_SR_OR (1 << 3) 109 | #define USART_SR_NF (1 << 2) 110 | #define USART_SR_FE (1 << 1) 111 | #define USART_SR_PE (1 << 0) 112 | 113 | 114 | /* ------------------- TIMERS ------------------- */ 115 | #define TIM1_CR1 *(unsigned char*)0x52B0 116 | #define TIM1_CR2 *(unsigned char*)0x52B1 117 | #define TIM1_SMCR *(unsigned char*)0x52B2 118 | #define TIM1_ETR *(unsigned char*)0x52B3 119 | #define TIM1_DER *(unsigned char*)0x52B4 120 | #define TIM1_IER *(unsigned char*)0x52B5 121 | #define TIM1_SR1 *(unsigned char*)0x52B6 122 | #define TIM1_SR2 *(unsigned char*)0x52B7 123 | #define TIM1_EGR *(unsigned char*)0x52B8 124 | #define TIM1_CCMR1 *(unsigned char*)0x52B9 125 | #define TIM1_CCMR2 *(unsigned char*)0x52BA 126 | #define TIM1_CCMR3 *(unsigned char*)0x52BB 127 | #define TIM1_CCMR4 *(unsigned char*)0x52BC 128 | #define TIM1_CCER1 *(unsigned char*)0x52BD 129 | #define TIM1_CCER2 *(unsigned char*)0x52BE 130 | #define TIM1_CNTRH *(unsigned char*)0x52BF 131 | #define TIM1_CNTRL *(unsigned char*)0x52C0 132 | #define TIM1_PSCRH *(unsigned char*)0x52C1 133 | #define TIM1_PSCRL *(unsigned char*)0x52C2 134 | #define TIM1_ARRH *(unsigned char*)0x52C3 135 | #define TIM1_ARRL *(unsigned char*)0x52C4 136 | #define TIM1_RCR *(unsigned char*)0x52C5 137 | #define TIM1_CCR1H *(unsigned char*)0x52C6 138 | #define TIM1_CCR1L *(unsigned char*)0x52C7 139 | #define TIM1_CCR2H *(unsigned char*)0x52C8 140 | #define TIM1_CCR2L *(unsigned char*)0x52C9 141 | #define TIM1_CCR3H *(unsigned char*)0x52CA 142 | #define TIM1_CCR3L *(unsigned char*)0x52CB 143 | #define TIM1_CCR4H *(unsigned char*)0x52CC 144 | #define TIM1_CCR4L *(unsigned char*)0x52CD 145 | #define TIM1_BKR *(unsigned char*)0x52CE 146 | #define TIM1_DTR *(unsigned char*)0x52CF 147 | #define TIM1_OISR *(unsigned char*)0x52D0 148 | #define TIM1_DCR1 *(unsigned char*)0x52D1 149 | #define TIM1_DCR2 *(unsigned char*)0x52D2 150 | #define TIM1_DMA1R *(unsigned char*)0x52D3 151 | 152 | //#define SYSCFG_RMPCR1 _SFR_(0x509E) 153 | //_SFR_(0x509E,SYSCFG_RMPCR1) 154 | //SFR(SYSCFG_RMPCR1, 0x509E) 155 | __sfr __at (0xD0) PSW; 156 | 157 | /* TIM_IER bits */ 158 | #define TIM_IER_BIE (1 << 7) 159 | #define TIM_IER_TIE (1 << 6) 160 | #define TIM_IER_COMIE (1 << 5) 161 | #define TIM_IER_CC4IE (1 << 4) 162 | #define TIM_IER_CC3IE (1 << 3) 163 | #define TIM_IER_CC2IE (1 << 2) 164 | #define TIM_IER_CC1IE (1 << 1) 165 | #define TIM_IER_UIE (1 << 0) 166 | 167 | /* TIM_CR1 bits */ 168 | #define TIM_CR1_APRE (1 << 7) 169 | #define TIM_CR1_CMSH (1 << 6) 170 | #define TIM_CR1_CMSL (1 << 5) 171 | #define TIM_CR1_DIR (1 << 4) 172 | #define TIM_CR1_OPM (1 << 3) 173 | #define TIM_CR1_URS (1 << 2) 174 | #define TIM_CR1_UDIS (1 << 1) 175 | #define TIM_CR1_CEN (1 << 0) 176 | 177 | /* TIM_SR1 bits */ 178 | #define TIM_SR1_BIF (1 << 7) 179 | #define TIM_SR1_TIF (1 << 6) 180 | #define TIM_SR1_COMIF (1 << 5) 181 | #define TIM_SR1_CC4IF (1 << 4) 182 | #define TIM_SR1_CC3IF (1 << 3) 183 | #define TIM_SR1_CC2IF (1 << 2) 184 | #define TIM_SR1_CC1IF (1 << 1) 185 | #define TIM_SR1_UIF (1 << 0) 186 | 187 | -------------------------------------------------------------------------------- /thermo.hex: -------------------------------------------------------------------------------- 1 | :2080000082008083820000008200000082000000820000008200000082000000820000004D 2 | :20802000820000008200000082000000820000008200000082000000820000008200000030 3 | :208040008200000082000000820000008200000082000000820083E38200000082000000AA 4 | :20806000820000008200000082000000820000008200000082000000820083AC82000000C1 5 | :1D808300AE00202707724F00005A26F9AE00082709D68DE7D700205A26F7CC808040 6 | :03808000CC827F30 7 | :2080A000520C1E11891E11894B584B025F89CD862F5B081F0B1709AE50C0F6AE00014D2714 8 | :2080C00004584A26FC905F5D2A02905A8990891E0F891E0F89CD85755B081F0717055F1F7E 9 | :2080E000031F011E0313077B0212067B01120524151E031C00011F037B02A9006B027B0152 10 | :20810000A9006B0120DD5B0C81CE002790CE002581520CCD81091F031701CD81091F0B17E5 11 | :20812000091E0B72F0031F077B0A12026B067B091201881E0813127B07121184120F25DAC5 12 | :208140005B0C81353E525F35805260721052553501525081AE5016F6AAC0F7AE5017F6AA0A 13 | :20816000C0F7AE5014F6AAC0F7AE500CF6AA90F7AE500DF6AA90F7AE500AF6AA90F7810DBF 14 | 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:208D65005C1F871E87F64EA40F1EA4F720081E87F6A40F1EA4F71EA4F66B671EAB891EABC3 112 | :208D8500897B17887B6C88CD86AB5B061E505C1F5020B81650171C0D1B2603CC877B1E5026 113 | :208DA5007B616BA67BA60AA64D2603CC877B8916AD90894B201EAEFD5B03855C1F1C20E495 114 | :208DC5001EAB897B28881EACFD5B031E1C5C1F1CCC877B1E1C5BA6813C4E4F20464C4F4176 115 | :038DE500543E00F9 116 | :00000001FF 117 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | 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Use with the GNU Affero General Public License. 553 | 554 | Notwithstanding any other provision of this License, you have 555 | permission to link or combine any covered work with a work licensed 556 | under version 3 of the GNU Affero General Public License into a single 557 | combined work, and to convey the resulting work. The terms of this 558 | License will continue to apply to the part which is the covered work, 559 | but the special requirements of the GNU Affero General Public License, 560 | section 13, concerning interaction through a network will apply to the 561 | combination as such. 562 | 563 | 14. Revised Versions of this License. 564 | 565 | The Free Software Foundation may publish revised and/or new versions of 566 | the GNU General Public License from time to time. Such new versions will 567 | be similar in spirit to the present version, but may differ in detail to 568 | address new problems or concerns. 569 | 570 | Each version is given a distinguishing version number. If the 571 | Program specifies that a certain numbered version of the GNU General 572 | Public License "or any later version" applies to it, you have the 573 | option of following the terms and conditions either of that numbered 574 | version or of any later version published by the Free Software 575 | Foundation. If the Program does not specify a version number of the 576 | GNU General Public License, you may choose any version ever published 577 | by the Free Software Foundation. 578 | 579 | If the Program specifies that a proxy can decide which future 580 | versions of the GNU General Public License can be used, that proxy's 581 | public statement of acceptance of a version permanently authorizes you 582 | to choose that version for the Program. 583 | 584 | Later license versions may give you additional or different 585 | permissions. However, no additional obligations are imposed on any 586 | author or copyright holder as a result of your choosing to follow a 587 | later version. 588 | 589 | 15. Disclaimer of Warranty. 590 | 591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY 592 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT 593 | HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY 594 | OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, 595 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 596 | PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM 597 | IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF 598 | ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 599 | 600 | 16. Limitation of Liability. 601 | 602 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 603 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS 604 | THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY 605 | GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE 606 | USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF 607 | DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD 608 | PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), 609 | EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF 610 | SUCH DAMAGES. 611 | 612 | 17. Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /STM8L052C6.h: -------------------------------------------------------------------------------- 1 | /* STM8L052C6.h */ 2 | 3 | /* Copyright (c) 2003-2017 STMicroelectronics */ 4 | 5 | #ifndef __STM8L052C6__ 6 | #define __STM8L052C6__ 7 | 8 | /* STM8L052C6 */ 9 | 10 | /* functions */ 11 | #define enableInterrupts() {__asm__("rim\n");} // enable interrupts 12 | #define disableInterrupts() {__asm__("sim\n");} // disable interrupts 13 | #define iret() {__asm__("iret\n");} // Interrupt routine return 14 | #define pop_ccr() {__asm__("pop cc\n");} // Pop CCR from the stack 15 | #define push_ccr() {__asm__("push cc\n");}// Push CCR on the stack 16 | #define rim() {__asm__("rim\n");} // enable interrupts 17 | #define sim() {__asm__("sim\n");} // disable interrupts 18 | #define nop() {__asm__("nop\n");} // No Operation 19 | #define trap() {__asm__("trap\n");} // Trap (soft IT) 20 | #define wfi() {__asm__("wfi\n");} // Wait For Interrupt 21 | #define halt() {__asm__("halt\n");} // Halt 22 | 23 | /* Port A */ 24 | /*****************************************************************/ 25 | 26 | /* Port A data output latch register */ 27 | #define PA_ODR (*(volatile uint8_t *)0x5000) 28 | 29 | /* Port A input pin value register */ 30 | #define PA_IDR (*(volatile uint8_t *)0x5001) 31 | 32 | /* Port A data direction register */ 33 | #define PA_DDR (*(volatile uint8_t *)0x5002) 34 | 35 | /* Port A control register 1 */ 36 | #define PA_CR1 (*(volatile uint8_t *)0x5003) 37 | 38 | /* Port A control register 2 */ 39 | #define PA_CR2 (*(volatile uint8_t *)0x5004) 40 | 41 | /* Port B */ 42 | /*****************************************************************/ 43 | 44 | /* Port B data output latch register */ 45 | #define PB_ODR (*(volatile uint8_t *)0x5005) 46 | 47 | /* Port B input pin value register */ 48 | #define PB_IDR (*(volatile uint8_t *)0x5006) 49 | 50 | /* Port B data direction register */ 51 | #define PB_DDR (*(volatile uint8_t *)0x5007) 52 | 53 | /* Port B control register 1 */ 54 | #define PB_CR1 (*(volatile uint8_t *)0x5008) 55 | 56 | /* Port B control register 2 */ 57 | #define PB_CR2 (*(volatile uint8_t *)0x5009) 58 | 59 | /* Port C */ 60 | /*****************************************************************/ 61 | 62 | /* Port C data output latch register */ 63 | #define PC_ODR (*(volatile uint8_t *)0x500a) 64 | 65 | /* Port C input pin value register */ 66 | #define PC_IDR (*(volatile uint8_t *)0x500b) 67 | 68 | /* Port C data direction register */ 69 | #define PC_DDR (*(volatile uint8_t *)0x500c) 70 | 71 | /* Port C control register 1 */ 72 | #define PC_CR1 (*(volatile uint8_t *)0x500d) 73 | 74 | /* Port C control register 2 */ 75 | #define PC_CR2 (*(volatile uint8_t *)0x500e) 76 | 77 | /* Port D */ 78 | /*****************************************************************/ 79 | 80 | /* Port D data output latch register */ 81 | #define PD_ODR (*(volatile uint8_t *)0x500f) 82 | 83 | /* Port D input pin value register */ 84 | #define PD_IDR (*(volatile uint8_t *)0x5010) 85 | 86 | /* Port D data direction register */ 87 | #define PD_DDR (*(volatile uint8_t *)0x5011) 88 | 89 | /* Port D control register 1 */ 90 | #define PD_CR1 (*(volatile uint8_t *)0x5012) 91 | 92 | /* Port D control register 2 */ 93 | #define PD_CR2 (*(volatile uint8_t *)0x5013) 94 | 95 | /* Port E */ 96 | /*****************************************************************/ 97 | 98 | /* Port E data output latch register */ 99 | #define PE_ODR (*(volatile uint8_t *)0x5014) 100 | 101 | /* Port E input pin value register */ 102 | #define PE_IDR (*(volatile uint8_t *)0x5015) 103 | 104 | /* Port E data direction register */ 105 | #define PE_DDR (*(volatile uint8_t *)0x5016) 106 | 107 | /* Port E control register 1 */ 108 | #define PE_CR1 (*(volatile uint8_t *)0x5017) 109 | 110 | /* Port E control register 2 */ 111 | #define PE_CR2 (*(volatile uint8_t *)0x5018) 112 | 113 | /* Port F */ 114 | /*****************************************************************/ 115 | 116 | /* Port F data output latch register */ 117 | #define PF_ODR (*(volatile uint8_t *)0x5019) 118 | 119 | /* Port F input pin value register */ 120 | #define PF_IDR (*(volatile uint8_t *)0x501a) 121 | 122 | /* Port F data direction register */ 123 | #define PF_DDR (*(volatile uint8_t *)0x501b) 124 | 125 | /* Port F control register 1 */ 126 | #define PF_CR1 (*(volatile uint8_t *)0x501c) 127 | 128 | /* Port F control register 2 */ 129 | #define PF_CR2 (*(volatile uint8_t *)0x501d) 130 | 131 | /* Flash */ 132 | /*****************************************************************/ 133 | 134 | /* Flash control register 1 */ 135 | #define FLASH_CR1 (*(volatile uint8_t *)0x5050) 136 | 137 | /* Flash control register 2 */ 138 | #define FLASH_CR2 (*(volatile uint8_t *)0x5051) 139 | 140 | /* Flash Program memory unprotection register */ 141 | #define FLASH_PUKR (*(volatile uint8_t *)0x5052) 142 | 143 | /* Data EEPROM unprotection register */ 144 | #define FLASH_DUKR (*(volatile uint8_t *)0x5053) 145 | 146 | /* Flash in-application programming status register */ 147 | #define FLASH_IAPSR (*(volatile uint8_t *)0x5054) 148 | 149 | /* Direct memory access controller 1 (DMA1) */ 150 | /*****************************************************************/ 151 | 152 | /* DMA1 global configuration & status register */ 153 | #define DMA1_GCSR (*(volatile uint8_t *)0x5070) 154 | 155 | /* DMA1 global interrupt register 1 */ 156 | #define DMA1_GIR1 (*(volatile uint8_t *)0x5071) 157 | 158 | /* DMA1 channel 0 configuration register */ 159 | #define DMA1_C0CR (*(volatile uint8_t *)0x5075) 160 | 161 | /* DMA1 channel 0 status & priority register */ 162 | #define DMA1_C0SPR (*(volatile uint8_t *)0x5076) 163 | 164 | /* DMA1 number of data to transfer register (channel 0) */ 165 | #define DMA1_C0NDTR (*(volatile uint8_t *)0x5077) 166 | 167 | /* DMA peripheral address high register (channel 0) */ 168 | #define DMA1_C0PARH (*(volatile uint8_t *)0x5078) 169 | /* DMA peripheral address low register (channel 0) */ 170 | #define DMA1_C0PARL (*(volatile uint8_t *)0x5079) 171 | 172 | /* DMA memory address high register (channel 0) */ 173 | #define DMA1_C0M0ARH (*(volatile uint8_t *)0x507b) 174 | /* DMA memory address low register (channel 0) */ 175 | #define DMA1_C0M0ARL (*(volatile uint8_t *)0x507c) 176 | 177 | /* DMA1 channel 1 configuration register */ 178 | #define DMA1_C1CR (*(volatile uint8_t *)0x507f) 179 | 180 | /* DMA1 channel 1 status & priority register */ 181 | #define DMA1_C1SPR (*(volatile uint8_t *)0x5080) 182 | 183 | /* DMA1 number of data to transfer register (channel 1) */ 184 | #define DMA1_C1NDTR (*(volatile uint8_t *)0x5081) 185 | 186 | /* DMA peripheral address high register (channel 1) */ 187 | #define DMA1_C1PARH (*(volatile uint8_t *)0x5082) 188 | /* DMA peripheral address low register (channel 1) */ 189 | #define DMA1_C1PARL (*(volatile uint8_t *)0x5083) 190 | 191 | /* DMA memory address high register (channel 1) */ 192 | #define DMA1_C1M0ARH (*(volatile uint8_t *)0x5085) 193 | /* DMA memory address low register (channel 1) */ 194 | #define DMA1_C1M0ARL (*(volatile uint8_t *)0x5086) 195 | 196 | /* DMA1 channel 2 configuration register */ 197 | #define DMA1_C2CR (*(volatile uint8_t *)0x5089) 198 | 199 | /* DMA1 channel 2 status & priority register */ 200 | #define DMA1_C2SPR (*(volatile uint8_t *)0x508a) 201 | 202 | /* DMA1 number of data to transfer register (channel 2) */ 203 | #define DMA1_C2NDTR (*(volatile uint8_t *)0x508b) 204 | 205 | /* DMA peripheral address high register (channel 2) */ 206 | #define DMA1_C2PARH (*(volatile uint8_t *)0x508c) 207 | /* DMA peripheral address low register (channel 2) */ 208 | #define DMA1_C2PARL (*(volatile uint8_t *)0x508d) 209 | 210 | /* DMA memory address high register (channel 2) */ 211 | #define DMA1_C2M0ARH (*(volatile uint8_t *)0x508f) 212 | /* DMA memory address low register (channel 2) */ 213 | #define DMA1_C2M0ARL (*(volatile uint8_t *)0x5090) 214 | 215 | /* DMA1 channel 3 configuration register */ 216 | #define DMA1_C3CR (*(volatile uint8_t *)0x5093) 217 | 218 | /* DMA1 channel 3 status & priority register */ 219 | #define DMA1_C3SPR (*(volatile uint8_t *)0x5094) 220 | 221 | /* DMA1 number of data to transfer register (channel 3) */ 222 | #define DMA1_C3NDTR (*(volatile uint8_t *)0x5095) 223 | 224 | /* DMA1 peripheral address high register (channel 3) */ 225 | #define DMA1_C3PARH_C3M1ARH (*(volatile uint8_t *)0x5096) 226 | /* DMA1 peripheral address low register (channel 3) */ 227 | #define DMA1_C3PARL_C3M1ARL (*(volatile uint8_t *)0x5097) 228 | 229 | /* DMA memory address high register (channel 3) */ 230 | #define DMA1_C3M0ARH (*(volatile uint8_t *)0x5099) 231 | /* DMA memory address low register (channel 3) */ 232 | #define DMA1_C3M0ARL (*(volatile uint8_t *)0x509a) 233 | 234 | /* System configuration (SYSCFG) */ 235 | /*****************************************************************/ 236 | 237 | /* Remapping register 1 */ 238 | #define SYSCFG_RMPCR1 (*(volatile uint8_t *)0x509e) 239 | 240 | /* Remapping register 2 */ 241 | #define SYSCFG_RMPCR2 (*(volatile uint8_t *)0x509f) 242 | 243 | /* External Interrupt Control Register (ITC) */ 244 | /*****************************************************************/ 245 | 246 | /* External interrupt control register 1 */ 247 | #define EXTI_CR1 (*(volatile uint8_t *)0x50a0) 248 | 249 | /* External interrupt control register 2 */ 250 | #define EXTI_CR2 (*(volatile uint8_t *)0x50a1) 251 | 252 | /* External interrupt control register 3 */ 253 | #define EXTI_CR3 (*(volatile uint8_t *)0x50a2) 254 | 255 | /* External interrupt status register 1 */ 256 | #define EXTI_SR1 (*(volatile uint8_t *)0x50a3) 257 | 258 | /* External interrupt status register 2 */ 259 | #define EXTI_SR2 (*(volatile uint8_t *)0x50a4) 260 | 261 | /* External interrupt port select register */ 262 | #define EXTI_CONF (*(volatile uint8_t *)0x50a5) 263 | 264 | /* Wait For Event (WFE) */ 265 | /*****************************************************************/ 266 | 267 | /* WFE control register 1 */ 268 | #define WFE_CR1 (*(volatile uint8_t *)0x50a6) 269 | 270 | /* WFE control register 2 */ 271 | #define WFE_CR2 (*(volatile uint8_t *)0x50a7) 272 | 273 | /* WFE control register 3 */ 274 | #define WFE_CR3 (*(volatile uint8_t *)0x50a8) 275 | 276 | /* Reset (RST) */ 277 | /*****************************************************************/ 278 | 279 | /* Reset control register */ 280 | #define RST_CR (*(volatile uint8_t *)0x50b0) 281 | 282 | /* Reset status register */ 283 | #define RST_SR (*(volatile uint8_t *)0x50b1) 284 | 285 | /* Power control (PWR) */ 286 | /*****************************************************************/ 287 | 288 | /* Power control and status register 1 */ 289 | #define PWR_CSR1 (*(volatile uint8_t *)0x50b2) 290 | 291 | /* Power control and status register 2 */ 292 | #define PWR_CSR2 (*(volatile uint8_t *)0x50b3) 293 | 294 | /* Clock Control (CLK) */ 295 | /*****************************************************************/ 296 | 297 | /* System clock divider register */ 298 | #define CLK_CKDIVR (*(volatile uint8_t *)0x50c0) 299 | 300 | /* Clock RTC register */ 301 | #define CLK_CRTCR (*(volatile uint8_t *)0x50c1) 302 | 303 | /* Internal clock control register */ 304 | #define CLK_ICKCR (*(volatile uint8_t *)0x50c2) 305 | 306 | /* Peripheral clock gating register 1 */ 307 | #define CLK_PCKENR1 (*(volatile uint8_t *)0x50c3) 308 | 309 | /* Peripheral clock gating register 2 */ 310 | #define CLK_PCKENR2 (*(volatile uint8_t *)0x50c4) 311 | 312 | /* Configurable clock control register */ 313 | #define CLK_CCOR (*(volatile uint8_t *)0x50c5) 314 | 315 | /* External clock control register */ 316 | #define CLK_ECKCR (*(volatile uint8_t *)0x50c6) 317 | 318 | /* System clock status register */ 319 | #define CLK_SCSR (*(volatile uint8_t *)0x50c7) 320 | 321 | /* System clock switch register */ 322 | #define CLK_SWR (*(volatile uint8_t *)0x50c8) 323 | 324 | /* Clock switch control register */ 325 | #define CLK_SWCR (*(volatile uint8_t *)0x50c9) 326 | 327 | /* Clock security system register */ 328 | #define CLK_CSSR (*(volatile uint8_t *)0x50ca) 329 | 330 | /* Clock BEEP register */ 331 | #define CLK_CBEEPR (*(volatile uint8_t *)0x50cb) 332 | 333 | /* HSI calibration register */ 334 | #define CLK_HSICALR (*(volatile uint8_t *)0x50cc) 335 | 336 | /* HSI clock calibration trimming register */ 337 | #define CLK_HSITRIMR (*(volatile uint8_t *)0x50cd) 338 | 339 | /* HSI unlock register */ 340 | #define CLK_HSIUNLCKR (*(volatile uint8_t *)0x50ce) 341 | 342 | /* Main regulator control status register */ 343 | #define CLK_REGCSR (*(volatile uint8_t *)0x50cf) 344 | 345 | /* Window Watchdog (WWDG) */ 346 | /*****************************************************************/ 347 | 348 | /* WWDG Control Register */ 349 | #define WWDG_CR (*(volatile uint8_t *)0x50d3) 350 | 351 | /* WWDR Window Register */ 352 | #define WWDG_WR (*(volatile uint8_t *)0x50d4) 353 | 354 | /* Independent Watchdog (IWDG) */ 355 | /*****************************************************************/ 356 | 357 | /* IWDG Key Register */ 358 | #define IWDG_KR (*(volatile uint8_t *)0x50e0) 359 | 360 | /* IWDG Prescaler Register */ 361 | #define IWDG_PR (*(volatile uint8_t *)0x50e1) 362 | 363 | /* IWDG Reload Register */ 364 | #define IWDG_RLR (*(volatile uint8_t *)0x50e2) 365 | 366 | /* Beeper (BEEP) */ 367 | /*****************************************************************/ 368 | 369 | /* BEEP Control/Status Register 1 */ 370 | #define BEEP_CSR1 (*(volatile uint8_t *)0x50f0) 371 | 372 | /* BEEP Control/Status Register 2 */ 373 | #define BEEP_CSR2 (*(volatile uint8_t *)0x50f3) 374 | 375 | /* Real-time clock (RTC) */ 376 | /*****************************************************************/ 377 | 378 | /* Time Register 1 */ 379 | #define RTC_TR1 (*(volatile uint8_t *)0x5140) 380 | 381 | /* Time Register 2 */ 382 | #define RTC_TR2 (*(volatile uint8_t *)0x5141) 383 | 384 | /* Time Register 3 */ 385 | #define RTC_TR3 (*(volatile uint8_t *)0x5142) 386 | 387 | /* Date Register 1 */ 388 | #define RTC_DR1 (*(volatile uint8_t *)0x5144) 389 | 390 | /* Date Register 2 */ 391 | #define RTC_DR2 (*(volatile uint8_t *)0x5145) 392 | 393 | /* Date Register 3 */ 394 | #define RTC_DR3 (*(volatile uint8_t *)0x5146) 395 | 396 | /* Control Register 1 */ 397 | #define RTC_CR1 (*(volatile uint8_t *)0x5148) 398 | 399 | /* Control Register 2 */ 400 | #define RTC_CR2 (*(volatile uint8_t *)0x5149) 401 | 402 | /* Control Register 3 */ 403 | #define RTC_CR3 (*(volatile uint8_t *)0x514a) 404 | 405 | /* Initialization and Status Register 1 */ 406 | #define RTC_ISR1 (*(volatile uint8_t *)0x514c) 407 | 408 | /* Initialization and Status Register 2 */ 409 | #define RTC_ISR2 (*(volatile uint8_t *)0x514d) 410 | 411 | /* Synchronous Prescaler Register High */ 412 | #define RTC_SPRERH (*(volatile uint8_t *)0x5150) 413 | /* Synchronous Prescaler Register Low */ 414 | #define RTC_SPRERL (*(volatile uint8_t *)0x5151) 415 | 416 | /* Asynchronous Prescaler Register */ 417 | #define RTC_APRER (*(volatile uint8_t *)0x5152) 418 | 419 | /* Wakeup Timer Register High */ 420 | #define RTC_WUTRH (*(volatile uint8_t *)0x5154) 421 | /* Wakeup Timer Register Low */ 422 | #define RTC_WUTRL (*(volatile uint8_t *)0x5155) 423 | 424 | /* Write Protection Register */ 425 | #define RTC_WPR (*(volatile uint8_t *)0x5159) 426 | 427 | /* Alarm A Register 1 */ 428 | #define RTC_ALRMAR1 (*(volatile uint8_t *)0x515c) 429 | 430 | /* Alarm A Register 2 */ 431 | #define RTC_ALRMAR2 (*(volatile uint8_t *)0x515d) 432 | 433 | /* Alarm A Register 3 */ 434 | #define RTC_ALRMAR3 (*(volatile uint8_t *)0x515e) 435 | 436 | /* Alarm A Register 4 */ 437 | #define RTC_ALRMAR4 (*(volatile uint8_t *)0x515f) 438 | 439 | /* Serial Peripheral Interface 1 (SPI1) */ 440 | /*****************************************************************/ 441 | 442 | /* SPI1 Control Register 1 */ 443 | #define SPI1_CR1 (*(volatile uint8_t *)0x5200) 444 | 445 | /* SPI1 Control Register 2 */ 446 | #define SPI1_CR2 (*(volatile uint8_t *)0x5201) 447 | 448 | /* SPI1 Interrupt Control Register */ 449 | #define SPI1_ICR (*(volatile uint8_t *)0x5202) 450 | 451 | /* SPI1 Status Register */ 452 | #define SPI1_SR (*(volatile uint8_t *)0x5203) 453 | 454 | /* SPI1 Data Register */ 455 | #define SPI1_DR (*(volatile uint8_t *)0x5204) 456 | 457 | /* SPI1 CRC Polynomial Register */ 458 | #define SPI1_CRCPR (*(volatile uint8_t *)0x5205) 459 | 460 | /* SPI1 Rx CRC Register */ 461 | #define SPI1_RXCRCR (*(volatile uint8_t *)0x5206) 462 | 463 | /* SPI1 Tx CRC Register */ 464 | #define SPI1_TXCRCR (*(volatile uint8_t *)0x5207) 465 | 466 | /* I2C Bus Interface 1 (I2C1) */ 467 | /*****************************************************************/ 468 | 469 | /* I2C1 control register 1 */ 470 | #define I2C1_CR1 (*(volatile uint8_t *)0x5210) 471 | 472 | /* I2C1 control register 2 */ 473 | #define I2C1_CR2 (*(volatile uint8_t *)0x5211) 474 | 475 | /* I2C1 frequency register */ 476 | #define I2C1_FREQR (*(volatile uint8_t *)0x5212) 477 | 478 | /* I2C1 Own address register low */ 479 | #define I2C1_OARL (*(volatile uint8_t *)0x5213) 480 | 481 | /* I2C1 Own address register high */ 482 | #define I2C1_OARH (*(volatile uint8_t *)0x5214) 483 | 484 | /* I2C1 data register */ 485 | #define I2C1_DR (*(volatile uint8_t *)0x5216) 486 | 487 | /* I2C1 status register 1 */ 488 | #define I2C1_SR1 (*(volatile uint8_t *)0x5217) 489 | 490 | /* I2C1 status register 2 */ 491 | #define I2C1_SR2 (*(volatile uint8_t *)0x5218) 492 | 493 | /* I2C1 status register 3 */ 494 | #define I2C1_SR3 (*(volatile uint8_t *)0x5219) 495 | 496 | /* I2C1 interrupt control register */ 497 | #define I2C1_ITR (*(volatile uint8_t *)0x521a) 498 | 499 | /* I2C1 Clock control register low */ 500 | #define I2C1_CCRL (*(volatile uint8_t *)0x521b) 501 | 502 | /* I2C1 Clock control register high */ 503 | #define I2C1_CCRH (*(volatile uint8_t *)0x521c) 504 | 505 | /* I2C1 TRISE register */ 506 | #define I2C1_TRISER (*(volatile uint8_t *)0x521d) 507 | 508 | /* I2C1 packet error checking register */ 509 | #define I2C1_PECR (*(volatile uint8_t *)0x521e) 510 | 511 | /* Universal synch/asynch receiver transmitter 1 (USART1) */ 512 | /*****************************************************************/ 513 | 514 | /* USART1 Status Register */ 515 | #define USART1_SR (*(volatile uint8_t *)0x5230) 516 | 517 | /* USART1 Data Register */ 518 | #define USART1_DR (*(volatile uint8_t *)0x5231) 519 | 520 | /* USART1 Baud Rate Register 1 */ 521 | #define USART1_BRR1 (*(volatile uint8_t *)0x5232) 522 | 523 | /* USART1 Baud Rate Register 2 */ 524 | #define USART1_BRR2 (*(volatile uint8_t *)0x5233) 525 | 526 | /* USART1 Control Register 1 */ 527 | #define USART1_CR1 (*(volatile uint8_t *)0x5234) 528 | 529 | /* USART1 Control Register 2 */ 530 | #define USART1_CR2 (*(volatile uint8_t *)0x5235) 531 | 532 | /* USART1 Control Register 3 */ 533 | #define USART1_CR3 (*(volatile uint8_t *)0x5236) 534 | 535 | /* USART1 Control Register 4 */ 536 | #define USART1_CR4 (*(volatile uint8_t *)0x5237) 537 | 538 | /* USART1 Control Register 5 */ 539 | #define USART1_CR5 (*(volatile uint8_t *)0x5238) 540 | 541 | /* USART1 Guard time Register */ 542 | #define USART1_GTR (*(volatile uint8_t *)0x5239) 543 | 544 | /* USART1 Prescaler Register */ 545 | #define USART1_PSCR (*(volatile uint8_t *)0x523a) 546 | 547 | /* 16-Bit Timer 2 (TIM2) */ 548 | /*****************************************************************/ 549 | 550 | /* TIM2 Control register 1 */ 551 | #define TIM2_CR1 (*(volatile uint8_t *)0x5250) 552 | 553 | /* TIM2 Control register 2 */ 554 | #define TIM2_CR2 (*(volatile uint8_t *)0x5251) 555 | 556 | /* TIM2 Slave Mode Control register */ 557 | #define TIM2_SMCR (*(volatile uint8_t *)0x5252) 558 | 559 | /* TIM2 External trigger register */ 560 | #define TIM2_ETR (*(volatile uint8_t *)0x5253) 561 | 562 | /* TIM2 DMA request enable register */ 563 | #define TIM2_DER (*(volatile uint8_t *)0x5254) 564 | 565 | /* TIM2 Interrupt enable register */ 566 | #define TIM2_IER (*(volatile uint8_t *)0x5255) 567 | 568 | /* TIM2 Status register 1 */ 569 | #define TIM2_SR1 (*(volatile uint8_t *)0x5256) 570 | 571 | /* TIM2 Status register 2 */ 572 | #define TIM2_SR2 (*(volatile uint8_t *)0x5257) 573 | 574 | /* TIM2 Event Generation register */ 575 | #define TIM2_EGR (*(volatile uint8_t *)0x5258) 576 | 577 | /* TIM2 Capture/Compare mode register 1 */ 578 | #define TIM2_CCMR1 (*(volatile uint8_t *)0x5259) 579 | 580 | /* TIM2 Capture/Compare mode register 2 */ 581 | #define TIM2_CCMR2 (*(volatile uint8_t *)0x525a) 582 | 583 | /* TIM2 Capture/Compare enable register 1 */ 584 | #define TIM2_CCER1 (*(volatile uint8_t *)0x525b) 585 | 586 | /* TIM2 Counter High */ 587 | #define TIM2_CNTRH (*(volatile uint8_t *)0x525c) 588 | /* TIM2 Counter Low */ 589 | #define TIM2_CNTRL (*(volatile uint8_t *)0x525d) 590 | 591 | /* TIM2 Prescaler register */ 592 | #define TIM2_PSCR (*(volatile uint8_t *)0x525e) 593 | 594 | /* TIM2 Auto-Reload Register High */ 595 | #define TIM2_ARRH (*(volatile uint8_t *)0x525f) 596 | /* TIM2 Auto-Reload Register Low */ 597 | #define TIM2_ARRL (*(volatile uint8_t *)0x5260) 598 | 599 | /* TIM2 Capture/Compare Register 1 High */ 600 | #define TIM2_CCR1H (*(volatile uint8_t *)0x5261) 601 | /* TIM2 Capture/Compare Register 1 Low */ 602 | #define TIM2_CCR1L (*(volatile uint8_t *)0x5262) 603 | 604 | /* TIM2 Capture/Compare Register 2 High */ 605 | #define TIM2_CCR2H (*(volatile uint8_t *)0x5263) 606 | /* TIM2 Capture/Compare Register 2 Low */ 607 | #define TIM2_CCR2L (*(volatile uint8_t *)0x5264) 608 | 609 | /* TIM2 Break register */ 610 | #define TIM2_BKR (*(volatile uint8_t *)0x5265) 611 | 612 | /* TIM2 Output idle state register */ 613 | #define TIM2_OISR (*(volatile uint8_t *)0x5266) 614 | 615 | /* 16-Bit Timer 3 (TIM3) */ 616 | /*****************************************************************/ 617 | 618 | /* TIM3 Control register 1 */ 619 | #define TIM3_CR1 (*(volatile uint8_t *)0x5280) 620 | 621 | /* TIM3 Control register 2 */ 622 | #define TIM3_CR2 (*(volatile uint8_t *)0x5281) 623 | 624 | /* TIM3 Slave Mode Control register */ 625 | #define TIM3_SMCR (*(volatile uint8_t *)0x5282) 626 | 627 | /* TIM3 External trigger register */ 628 | #define TIM3_ETR (*(volatile uint8_t *)0x5283) 629 | 630 | /* TIM3 DMA request enable register */ 631 | #define TIM3_DER (*(volatile uint8_t *)0x5284) 632 | 633 | /* TIM3 Interrupt enable register */ 634 | #define TIM3_IER (*(volatile uint8_t *)0x5285) 635 | 636 | /* TIM3 Status register 1 */ 637 | #define TIM3_SR1 (*(volatile uint8_t *)0x5286) 638 | 639 | /* TIM3 Status register 2 */ 640 | #define TIM3_SR2 (*(volatile uint8_t *)0x5287) 641 | 642 | /* TIM3 Event Generation register */ 643 | #define TIM3_EGR (*(volatile uint8_t *)0x5288) 644 | 645 | /* TIM3 Capture/Compare mode register 1 */ 646 | #define TIM3_CCMR1 (*(volatile uint8_t *)0x5289) 647 | 648 | /* TIM3 Capture/Compare mode register 2 */ 649 | #define TIM3_CCMR2 (*(volatile uint8_t *)0x528a) 650 | 651 | /* TIM3 Capture/Compare enable register 1 */ 652 | #define TIM3_CCER1 (*(volatile uint8_t *)0x528b) 653 | 654 | /* TIM3 Counter High */ 655 | #define TIM3_CNTRH (*(volatile uint8_t *)0x528c) 656 | /* TIM3 Counter Low */ 657 | #define TIM3_CNTRL (*(volatile uint8_t *)0x528d) 658 | 659 | /* TIM3 Prescaler register */ 660 | #define TIM3_PSCR (*(volatile uint8_t *)0x528e) 661 | 662 | /* TIM3 Auto-Reload Register High */ 663 | #define TIM3_ARRH (*(volatile uint8_t *)0x528f) 664 | /* TIM3 Auto-Reload Register Low */ 665 | #define TIM3_ARRL (*(volatile uint8_t *)0x5290) 666 | 667 | /* TIM3 Capture/Compare Register 1 High */ 668 | #define TIM3_CCR1H (*(volatile uint8_t *)0x5291) 669 | /* TIM3 Capture/Compare Register 1 Low */ 670 | #define TIM3_CCR1L (*(volatile uint8_t *)0x5292) 671 | 672 | /* TIM3 Capture/Compare Register 2 High */ 673 | #define TIM3_CCR2H (*(volatile uint8_t *)0x5293) 674 | /* TIM3 Capture/Compare Register 2 Low */ 675 | #define TIM3_CCR2L (*(volatile uint8_t *)0x5294) 676 | 677 | /* TIM3 Break register */ 678 | #define TIM3_BKR (*(volatile uint8_t *)0x5295) 679 | 680 | /* TIM3 Output idle state register */ 681 | #define TIM3_OISR (*(volatile uint8_t *)0x5296) 682 | 683 | /* 16-Bit Timer 1 (TIM1) */ 684 | /*****************************************************************/ 685 | 686 | /* TIM1 Control register 1 */ 687 | #define TIM1_CR1 (*(volatile uint8_t *)0x52b0) 688 | 689 | /* TIM1 Control register 2 */ 690 | #define TIM1_CR2 (*(volatile uint8_t *)0x52b1) 691 | 692 | /* TIM1 Slave Mode Control register */ 693 | #define TIM1_SMCR (*(volatile uint8_t *)0x52b2) 694 | 695 | /* TIM1 external trigger register */ 696 | #define TIM1_ETR (*(volatile uint8_t *)0x52b3) 697 | 698 | /* TIM1 DMA request enable register */ 699 | #define TIM1_DER (*(volatile uint8_t *)0x52b4) 700 | 701 | /* TIM1 Interrupt enable register */ 702 | #define TIM1_IER (*(volatile uint8_t *)0x52b5) 703 | 704 | /* TIM1 Status register 1 */ 705 | #define TIM1_SR1 (*(volatile uint8_t *)0x52b6) 706 | 707 | /* TIM1 Status register 2 */ 708 | #define TIM1_SR2 (*(volatile uint8_t *)0x52b7) 709 | 710 | /* TIM1 Event Generation register */ 711 | #define TIM1_EGR (*(volatile uint8_t *)0x52b8) 712 | 713 | /* TIM1 Capture/Compare mode register 1 */ 714 | #define TIM1_CCMR1 (*(volatile uint8_t *)0x52b9) 715 | 716 | /* TIM1 Capture/Compare mode register 2 */ 717 | #define TIM1_CCMR2 (*(volatile uint8_t *)0x52ba) 718 | 719 | /* TIM1 Capture/Compare mode register 3 */ 720 | #define TIM1_CCMR3 (*(volatile uint8_t *)0x52bb) 721 | 722 | /* TIM1 Capture/Compare mode register 4 */ 723 | #define TIM1_CCMR4 (*(volatile uint8_t *)0x52bc) 724 | 725 | /* TIM1 Capture/Compare enable register 1 */ 726 | #define TIM1_CCER1 (*(volatile uint8_t *)0x52bd) 727 | 728 | /* TIM1 Capture/Compare enable register 2 */ 729 | #define TIM1_CCER2 (*(volatile uint8_t *)0x52be) 730 | 731 | /* TIM1 Counter High */ 732 | #define TIM1_CNTRH (*(volatile uint8_t *)0x52bf) 733 | /* TIM1 Counter Low */ 734 | #define TIM1_CNTRL (*(volatile uint8_t *)0x52c0) 735 | 736 | /* TIM1 Prescaler Register High */ 737 | #define TIM1_PSCRH (*(volatile uint8_t *)0x52c1) 738 | /* TIM1 Prescaler Register Low */ 739 | #define TIM1_PSCRL (*(volatile uint8_t *)0x52c2) 740 | 741 | /* TIM1 Auto-Reload Register High */ 742 | #define TIM1_ARRH (*(volatile uint8_t *)0x52c3) 743 | /* TIM1 Auto-Reload Register Low */ 744 | #define TIM1_ARRL (*(volatile uint8_t *)0x52c4) 745 | 746 | /* TIM1 Repetition counter register */ 747 | #define TIM1_RCR (*(volatile uint8_t *)0x52c5) 748 | 749 | /* TIM1 Capture/Compare Register 1 High */ 750 | #define TIM1_CCR1H (*(volatile uint8_t *)0x52c6) 751 | /* TIM1 Capture/Compare Register 1 Low */ 752 | #define TIM1_CCR1L (*(volatile uint8_t *)0x52c7) 753 | 754 | /* TIM1 Capture/Compare Register 2 High */ 755 | #define TIM1_CCR2H (*(volatile uint8_t *)0x52c8) 756 | /* TIM1 Capture/Compare Register 2 Low */ 757 | #define TIM1_CCR2L (*(volatile uint8_t *)0x52c9) 758 | 759 | /* TIM1 Capture/Compare Register 3 High */ 760 | #define TIM1_CCR3H (*(volatile uint8_t *)0x52ca) 761 | /* TIM1 Capture/Compare Register 3 Low */ 762 | #define TIM1_CCR3L (*(volatile uint8_t *)0x52cb) 763 | 764 | /* TIM1 Capture/Compare Register 4 High */ 765 | #define TIM1_CCR4H (*(volatile uint8_t *)0x52cc) 766 | /* TIM1 Capture/Compare Register 4 Low */ 767 | #define TIM1_CCR4L (*(volatile uint8_t *)0x52cd) 768 | 769 | /* TIM1 Break register */ 770 | #define TIM1_BKR (*(volatile uint8_t *)0x52ce) 771 | 772 | /* TIM1 Dead-time register */ 773 | #define TIM1_DTR (*(volatile uint8_t *)0x52cf) 774 | 775 | /* TIM1 Output idle state register */ 776 | #define TIM1_OISR (*(volatile uint8_t *)0x52d0) 777 | 778 | /* TIM1 DMA control register 1 */ 779 | #define TIM1_DCR1 (*(volatile uint8_t *)0x52d1) 780 | 781 | /* TIM1 DMA control register 2 */ 782 | #define TIM1_DCR2 (*(volatile uint8_t *)0x52d2) 783 | 784 | /* TIM1 DMA address for burst mode */ 785 | #define TIM1_DMAR (*(volatile uint8_t *)0x52d3) 786 | 787 | /* 8-Bit Timer 4 (TIM4) */ 788 | /*****************************************************************/ 789 | 790 | /* TIM4 Control Register 1 */ 791 | #define TIM4_CR1 (*(volatile uint8_t *)0x52e0) 792 | 793 | /* TIM4 Control Register 2 */ 794 | #define TIM4_CR2 (*(volatile uint8_t *)0x52e1) 795 | 796 | /* TIM4 Slave Mode Control Register */ 797 | #define TIM4_SMCR (*(volatile uint8_t *)0x52e2) 798 | 799 | /* TIM4 DMA request Enable Register */ 800 | #define TIM4_DER (*(volatile uint8_t *)0x52e3) 801 | 802 | /* TIM4 Interrupt Enable Register */ 803 | #define TIM4_IER (*(volatile uint8_t *)0x52e4) 804 | 805 | /* TIM4 Status Register 1 */ 806 | #define TIM4_SR1 (*(volatile uint8_t *)0x52e5) 807 | 808 | /* TIM4 Event Generation Register */ 809 | #define TIM4_EGR (*(volatile uint8_t *)0x52e6) 810 | 811 | /* TIM4 Counter */ 812 | #define TIM4_CNTR (*(volatile uint8_t *)0x52e7) 813 | 814 | /* TIM4 Prescaler Register */ 815 | #define TIM4_PSCR (*(volatile uint8_t *)0x52e8) 816 | 817 | /* TIM4 Auto-Reload Register */ 818 | #define TIM4_ARR (*(volatile uint8_t *)0x52e9) 819 | 820 | /* Infra Red Interface (IR) */ 821 | /*****************************************************************/ 822 | 823 | /* Infra-red control register */ 824 | #define IR_CR (*(volatile uint8_t *)0x52ff) 825 | 826 | /* Analog to digital converter 1 (ADC1) */ 827 | /*****************************************************************/ 828 | 829 | /* ADC1 Configuration register 1 */ 830 | #define ADC1_CR1 (*(volatile uint8_t *)0x5340) 831 | 832 | /* ADC1 Configuration register 2 */ 833 | #define ADC1_CR2 (*(volatile uint8_t *)0x5341) 834 | 835 | /* ADC1 Configuration register 3 */ 836 | #define ADC1_CR3 (*(volatile uint8_t *)0x5342) 837 | 838 | /* ADC1 status register */ 839 | #define ADC1_SR (*(volatile uint8_t *)0x5343) 840 | 841 | /* ADC Data Register High */ 842 | #define ADC1_DRH (*(volatile uint8_t *)0x5344) 843 | /* ADC Data Register Low */ 844 | #define ADC1_DRL (*(volatile uint8_t *)0x5345) 845 | 846 | /* ADC High Threshold Register High */ 847 | #define ADC1_HTRH (*(volatile uint8_t *)0x5346) 848 | /* ADC High Threshold Register Low */ 849 | #define ADC1_HTRL (*(volatile uint8_t *)0x5347) 850 | 851 | /* ADC Low Threshold Register High */ 852 | #define ADC1_LTRH (*(volatile uint8_t *)0x5348) 853 | /* ADC Low Threshold Register Low */ 854 | #define ADC1_LTRL (*(volatile uint8_t *)0x5349) 855 | 856 | /* ADC1 channel sequence 1 register */ 857 | #define ADC1_SQR1 (*(volatile uint8_t *)0x534a) 858 | 859 | /* ADC1 channel sequence 2 register */ 860 | #define ADC1_SQR2 (*(volatile uint8_t *)0x534b) 861 | 862 | /* ADC1 channel sequence 3 register */ 863 | #define ADC1_SQR3 (*(volatile uint8_t *)0x534c) 864 | 865 | /* ADC1 channel sequence 4 register */ 866 | #define ADC1_SQR4 (*(volatile uint8_t *)0x534d) 867 | 868 | /* ADC1 Trigger disable 1 */ 869 | #define ADC1_TRIGR1 (*(volatile uint8_t *)0x534e) 870 | 871 | /* ADC1 Trigger disable 2 */ 872 | #define ADC1_TRIGR2 (*(volatile uint8_t *)0x534f) 873 | 874 | /* ADC1 Trigger disable 3 */ 875 | #define ADC1_TRIGR3 (*(volatile uint8_t *)0x5350) 876 | 877 | /* ADC1 Trigger disable 4 */ 878 | #define ADC1_TRIGR4 (*(volatile uint8_t *)0x5351) 879 | 880 | /* LCD controller (LCD) */ 881 | /*****************************************************************/ 882 | 883 | /* LCD control register 1 */ 884 | #define LCD_CR1 (*(volatile uint8_t *)0x5400) 885 | 886 | /* LCD control register 2 */ 887 | #define LCD_CR2 (*(volatile uint8_t *)0x5401) 888 | 889 | /* LCD control register 3 */ 890 | #define LCD_CR3 (*(volatile uint8_t *)0x5402) 891 | 892 | /* LCD frequency selection register */ 893 | #define LCD_FRQ (*(volatile uint8_t *)0x5403) 894 | 895 | /* LCD Port mask register 0 */ 896 | #define LCD_PM0 (*(volatile uint8_t *)0x5404) 897 | 898 | /* LCD Port mask register 1 */ 899 | #define LCD_PM1 (*(volatile uint8_t *)0x5405) 900 | 901 | /* LCD Port mask register 2 */ 902 | #define LCD_PM2 (*(volatile uint8_t *)0x5406) 903 | 904 | /* LCD display memory 0 */ 905 | #define LCD_RAM0 (*(volatile uint8_t *)0x540c) 906 | 907 | /* LCD display memory 1 */ 908 | #define LCD_RAM1 (*(volatile uint8_t *)0x540d) 909 | 910 | /* LCD display memory 2 */ 911 | #define LCD_RAM2 (*(volatile uint8_t *)0x540e) 912 | 913 | /* LCD display memory 3 */ 914 | #define LCD_RAM3 (*(volatile uint8_t *)0x540f) 915 | 916 | /* LCD display memory 4 */ 917 | #define LCD_RAM4 (*(volatile uint8_t *)0x5410) 918 | 919 | /* LCD display memory 5 */ 920 | #define LCD_RAM5 (*(volatile uint8_t *)0x5411) 921 | 922 | /* LCD display memory 6 */ 923 | #define LCD_RAM6 (*(volatile uint8_t *)0x5412) 924 | 925 | /* LCD display memory 7 */ 926 | #define LCD_RAM7 (*(volatile uint8_t *)0x5413) 927 | 928 | /* LCD display memory 8 */ 929 | #define LCD_RAM8 (*(volatile uint8_t *)0x5414) 930 | 931 | /* LCD display memory 9 */ 932 | #define LCD_RAM9 (*(volatile uint8_t *)0x5415) 933 | 934 | /* LCD display memory 10 */ 935 | #define LCD_RAM10 (*(volatile uint8_t *)0x5416) 936 | 937 | /* LCD display memory 11 */ 938 | #define LCD_RAM11 (*(volatile uint8_t *)0x5417) 939 | 940 | /* LCD display memory 12 */ 941 | #define LCD_RAM12 (*(volatile uint8_t *)0x5418) 942 | 943 | /* LCD display memory 13 */ 944 | #define LCD_RAM13 (*(volatile uint8_t *)0x5419) 945 | 946 | /* Routing interface (RI) */ 947 | /*****************************************************************/ 948 | 949 | /* Timer input capture routing register 1 */ 950 | #define RI_ICR1 (*(volatile uint8_t *)0x5431) 951 | 952 | /* Timer input capture routing register 2 */ 953 | #define RI_ICR2 (*(volatile uint8_t *)0x5432) 954 | 955 | /* I/O input register 1 */ 956 | #define RI_IOIR1 (*(volatile uint8_t *)0x5433) 957 | 958 | /* I/O input register 2 */ 959 | #define RI_IOIR2 (*(volatile uint8_t *)0x5434) 960 | 961 | /* I/O input register 3 */ 962 | #define RI_IOIR3 (*(volatile uint8_t *)0x5435) 963 | 964 | /* I/O control mode register 1 */ 965 | #define RI_IOCMR1 (*(volatile uint8_t *)0x5436) 966 | 967 | /* I/O control mode register 2 */ 968 | #define RI_IOCMR2 (*(volatile uint8_t *)0x5437) 969 | 970 | /* I/O control mode register 3 */ 971 | #define RI_IOCMR3 (*(volatile uint8_t *)0x5438) 972 | 973 | /* I/O switch register 1 */ 974 | #define RI_IOSR1 (*(volatile uint8_t *)0x5439) 975 | 976 | /* I/O switch register 2 */ 977 | #define RI_IOSR2 (*(volatile uint8_t *)0x543a) 978 | 979 | /* I/O switch register 3 */ 980 | #define RI_IOSR3 (*(volatile uint8_t *)0x543b) 981 | 982 | /* I/O group control register */ 983 | #define RI_IOGCR (*(volatile uint8_t *)0x543c) 984 | 985 | /* Analog switch register 1 */ 986 | #define RI_ASCR1 (*(volatile uint8_t *)0x543d) 987 | 988 | /* Analog switch register 2 */ 989 | #define RI_ASCR2 (*(volatile uint8_t *)0x543e) 990 | 991 | /* Resistor control register */ 992 | #define RI_RCR (*(volatile uint8_t *)0x543f) 993 | 994 | // Custom bits 995 | #define USART_CR1_R8 (1 << 7) 996 | #define USART_CR1_T8 (1 << 6) 997 | #define USART_CR1_UARTD (1 << 5) 998 | #define USART_CR1_M (1 << 4) 999 | #define USART_CR1_WAKE (1 << 3) 1000 | #define USART_CR1_PCEN (1 << 2) 1001 | #define USART_CR1_PS (1 << 1) 1002 | #define USART_CR1_PIEN (1 << 0) 1003 | #define USART_CR2_TIEN (1 << 7) 1004 | #define USART_CR2_TCIEN (1 << 6) 1005 | #define USART_CR2_RIEN (1 << 5) 1006 | #define USART_CR2_ILIEN (1 << 4) 1007 | #define USART_CR2_TEN (1 << 3) 1008 | #define USART_CR2_REN (1 << 2) 1009 | #define USART_CR2_RWU (1 << 1) 1010 | #define USART_CR2_SBK (1 << 0) 1011 | #define USART_CR3_LINEN (1 << 6) 1012 | #define USART_CR3_STOP2 (1 << 5) 1013 | #define USART_CR3_STOP1 (1 << 4) 1014 | #define USART_CR3_CLKEN (1 << 3) 1015 | #define USART_CR3_CPOL (1 << 2) 1016 | #define USART_CR3_CPHA (1 << 1) 1017 | #define USART_CR3_LBCL (1 << 0) 1018 | #define USART_SR_TXE (1 << 7) 1019 | #define USART_SR_TC (1 << 6) 1020 | #define USART_SR_RXNE (1 << 5) 1021 | #define USART_SR_IDLE (1 << 4) 1022 | #define USART_SR_OR (1 << 3) 1023 | #define USART_SR_NF (1 << 2) 1024 | #define USART_SR_FE (1 << 1) 1025 | #define USART_SR_PE (1 << 0) 1026 | 1027 | #define TIM_IER_BIE (1 << 7) 1028 | #define TIM_IER_TIE (1 << 6) 1029 | #define TIM_IER_COMIE (1 << 5) 1030 | #define TIM_IER_CC4IE (1 << 4) 1031 | #define TIM_IER_CC3IE (1 << 3) 1032 | #define TIM_IER_CC2IE (1 << 2) 1033 | #define TIM_IER_CC1IE (1 << 1) 1034 | 1035 | #define TIM_IER_UIE (1 << 0) 1036 | #define TIM_CR1_APRE (1 << 7) 1037 | #define TIM_CR1_CMSH (1 << 6) 1038 | #define TIM_CR1_CMSL (1 << 5) 1039 | #define TIM_CR1_DIR (1 << 4) 1040 | #define TIM_CR1_OPM (1 << 3) 1041 | #define TIM_CR1_URS (1 << 2) 1042 | #define TIM_CR1_UDIS (1 << 1) 1043 | #define TIM_CR1_CEN (1 << 0) 1044 | 1045 | #define TIM_SR1_BIF (1 << 7) 1046 | #define TIM_SR1_TIF (1 << 6) 1047 | #define TIM_SR1_COMIF (1 << 5) 1048 | #define TIM_SR1_CC4IF (1 << 4) 1049 | #define TIM_SR1_CC3IF (1 << 3) 1050 | #define TIM_SR1_CC2IF (1 << 2) 1051 | #define TIM_SR1_CC1IF (1 << 1) 1052 | #define TIM_SR1_UIF (1 << 0) 1053 | 1054 | #define ADC1_CR1_OVERIE (1 << 7) 1055 | #define ADC1_CR1_RES1 (1 << 6) 1056 | #define ADC1_CR1_RES0 (1 << 5) 1057 | #define ADC1_CR1_AWDIE (1 << 4) 1058 | #define ADC1_CR1_EOCIE (1 << 3) 1059 | #define ADC1_CR1_CONT (1 << 2) 1060 | #define ADC1_CR1_START (1 << 1) 1061 | #define ADC1_CR1_ADON (1 << 0) 1062 | 1063 | #define ADC1_SR_OVER (1 << 2) 1064 | #define ADC1_SR_AWD (1 << 1) 1065 | #define ADC1_SR_EOC (1 << 0) 1066 | 1067 | #define ADC1_SQR1_DMAOFF (1 << 7) 1068 | 1069 | #endif /* __STM8L052C6__ */ 1070 | --------------------------------------------------------------------------------