├── Images ├── Bias.png ├── CSAmp.png ├── GmBias.png ├── OpAmp.png ├── CCLatch.png ├── DiffAmp.png ├── FlashADC.png ├── CCLatch_RPP.png ├── CMMFeedback.png ├── DiffAmp_RPP.png ├── InvAmp_RPP.png ├── MillerOpAmp.png ├── RALF_methodology.png └── Example │ ├── DiffAmp_circuit.png │ ├── DiffAmp_placement1.png │ ├── DiffAmp_placement2.png │ ├── DiffAmp_routing1.png │ └── DiffAmp_routing2.png ├── Magic ├── Layouts │ ├── DiffAmp.mag │ ├── R1.mag │ ├── nfet.mag │ ├── pfet.mag │ ├── TwoStageAmp_v0.mag │ ├── TwoStageAmp_v1.mag │ └── TwoStageAmp_v2.mag ├── __pycache__ │ ├── DRC.cpython-310.pyc │ ├── Cell.cpython-310.pyc │ ├── Magic.cpython-310.pyc │ ├── utils.cpython-310.pyc │ ├── MagicDie.cpython-310.pyc │ ├── __init__.cpython-310.pyc │ ├── MacroCell.cpython-310.pyc │ ├── MagicLayer.cpython-310.pyc │ ├── MagicParser.cpython-310.pyc │ ├── MagicTerminal.cpython-310.pyc │ └── MagicTerminal_utils.cpython-310.pyc ├── __init__.py └── Devices │ ├── init_devs.tcl │ ├── XM5.mag │ ├── XDP_XM1_XM2.mag │ └── XDL_XM3_XM4.mag ├── Network ├── Weights │ ├── ppo_actor.pth │ ├── ppo_critic.pth │ ├── ppo_actor.pth.orig │ ├── WireLengthModel.pth │ ├── ppo_critic.pth.orig │ └── D2RN_BatchNorm │ │ ├── ppo_actor.pth │ │ └── ppo_critic.pth ├── __pycache__ │ ├── __init__.cpython-310.pyc │ ├── D2RL_Actor.cpython-310.pyc │ ├── D2RL_Critic.cpython-310.pyc │ ├── GAT_Policy.cpython-310.pyc │ ├── GAT_D2RL_Actor.cpython-310.pyc │ └── GAT_D2RL_Critic.cpython-310.pyc ├── __init__.py ├── D2RL_Policy.py ├── GAT_Policy.py ├── D2RL_Critic.py ├── GAT_D2RL_Critic.py ├── D2RL_Actor.py └── GAT_D2RL_Actor.py ├── PDK ├── __pycache__ │ ├── PDK.cpython-310.pyc │ ├── Layers.cpython-310.pyc │ └── __init__.cpython-310.pyc ├── __init__.py └── layers.json ├── PPO ├── __pycache__ │ ├── utils.cpython-310.pyc │ ├── __init__.cpython-310.pyc │ ├── Placement_PPO.cpython-310.pyc │ └── Environment_Multiprocessing.cpython-310.pyc ├── __init__.py └── utils.py ├── PlacementCircuits ├── OpAmp_placement.pkl ├── DiffAmp_placement.pkl ├── FlashADC_placement.pkl ├── InvAmp_RLP_placement.pkl ├── InvAmp_RPP_placement.pkl ├── CCLatch_RLP_placement.pkl ├── CCLatch_RPP_placement.pkl ├── DiffAmp_RLP2_placement.pkl ├── DiffAmp_RLP_placement.pkl └── DiffAmp_RPP_placement.pkl ├── RTreeObstacles ├── global_obstacle.data └── global_obstacle.index ├── Rules ├── __pycache__ │ ├── Rule.cpython-310.pyc │ ├── utils.cpython-310.pyc │ ├── NetRules.cpython-310.pyc │ ├── RoutingRules.cpython-310.pyc │ └── PlacementRules.cpython-310.pyc ├── Rule.py └── NetRules.py ├── Environment ├── __pycache__ │ ├── RUDY.cpython-310.pyc │ ├── utils.cpython-310.pyc │ ├── __init__.cpython-310.pyc │ ├── Environment.cpython-310.pyc │ └── cell_sliding.cpython-310.pyc └── __init__.py ├── Routing_v2 ├── __pycache__ │ ├── Grid.cpython-310.pyc │ ├── Path.cpython-310.pyc │ ├── Pins.cpython-310.pyc │ ├── Route.cpython-310.pyc │ ├── utils.cpython-310.pyc │ ├── Router.cpython-310.pyc │ ├── Geometrics.cpython-310.pyc │ ├── Obstacles.cpython-310.pyc │ ├── Primitives.cpython-310.pyc │ ├── TileRouter.cpython-310.pyc │ ├── PlanningGraph.cpython-310.pyc │ └── WirePlanning.cpython-310.pyc ├── Graph.py └── Pins.py ├── Circuits ├── Examples │ ├── OpAmp │ │ ├── simulation │ │ │ ├── MillerOP.raw │ │ │ ├── MillerOpAmp_tb.raw │ │ │ ├── bsim4v5.out │ │ │ └── GmBias_tb.spice │ │ ├── Bias.sym │ │ ├── GmBias.sym │ │ ├── GmBiasP.sym │ │ ├── CSAmp.sym │ │ ├── OpAmp.sym │ │ ├── CMMFeedback.sym │ │ ├── DiffAmp.sym │ │ ├── GmBias_tb.sch │ │ ├── MillerOpAmp.sym │ │ ├── OpAmp.sch │ │ ├── CSAmp.sch │ │ ├── MillerOpAmp.sch │ │ ├── MillerOpAmp.spice │ │ └── Bias.sch │ ├── InvAmp │ │ ├── simulation │ │ │ └── MillerOpAmp_tb.raw │ │ ├── InvAmp.sym │ │ └── InvAmp.sch │ ├── Latch │ │ ├── CCLatch.sym │ │ ├── simulation │ │ │ └── CCLatch.spice │ │ ├── CCLatch_tb.spice │ │ └── CCLatch_tb.sch │ ├── CCLatch.spice │ └── DiffAmp.spice └── Primitives │ ├── RString │ ├── RString1.spice │ ├── RString2.spice │ ├── RString3.spice │ ├── RString4.spice │ └── RString.sch │ ├── DiffLoad │ ├── DiffLoad_sym.spice │ ├── DiffLoad_unsym.spice │ ├── DiffLoad_sym_Vs_Vb_connected.spice │ └── DiffLoad_unsym_Vs_Vb_connected copy.spice │ ├── CrossCoupledPair │ ├── CCP.spice │ ├── CCP_Vs2_Vs1_Vb_connected.spice │ ├── CCP_Vs2_Vs1_connected.spice │ └── CCP.sch │ └── DiffPair │ ├── DiffPair.spice │ └── DiffPair_Vs_Vb_connected.spice ├── lef_def_parser └── __pycache__ │ ├── util.cpython-310.pyc │ ├── def_util.cpython-310.pyc │ └── def_parser.cpython-310.pyc ├── SchematicCapture ├── __pycache__ │ ├── Net.cpython-310.pyc │ ├── Circuit.cpython-310.pyc │ ├── Devices.cpython-310.pyc │ ├── Netlist.cpython-310.pyc │ ├── Ports.cpython-310.pyc │ ├── RString.cpython-310.pyc │ ├── utils.cpython-310.pyc │ ├── __init__.cpython-310.pyc │ ├── Primitives.cpython-310.pyc │ └── NGSpiceParser.cpython-310.pyc └── __init__.py ├── rectangle_packing_solver ├── __pycache__ │ ├── solver.cpython-310.pyc │ ├── utils.cpython-310.pyc │ ├── __init__.cpython-310.pyc │ ├── floorplan.cpython-310.pyc │ ├── problem.cpython-310.pyc │ ├── solution.cpython-310.pyc │ ├── __version__.cpython-310.pyc │ ├── visualizer.cpython-310.pyc │ ├── cell_sliding.cpython-310.pyc │ └── sequence_pair.cpython-310.pyc ├── __version__.py ├── __init__.py ├── solution.py ├── floorplan.py ├── visualizer.py └── problem.py ├── rectangle_packing_placement ├── __pycache__ │ ├── utils.cpython-310.pyc │ ├── cell_sliding.cpython-310.pyc │ ├── placement_solver.cpython-310.pyc │ ├── placement_problem.cpython-310.pyc │ ├── placement_solution.cpython-310.pyc │ ├── placement_floorplan.cpython-310.pyc │ ├── placement_visualizer.cpython-310.pyc │ └── placement_sequence_pair.cpython-310.pyc ├── rectangle_packing_solver │ ├── __pycache__ │ │ ├── solver.cpython-310.pyc │ │ ├── __init__.cpython-310.pyc │ │ ├── problem.cpython-310.pyc │ │ ├── solution.cpython-310.pyc │ │ ├── __version__.cpython-310.pyc │ │ ├── floorplan.cpython-310.pyc │ │ ├── visualizer.cpython-310.pyc │ │ └── sequence_pair.cpython-310.pyc │ ├── __version__.py │ ├── __init__.py │ ├── floorplan.py │ ├── solution.py │ ├── problem.py │ └── visualizer.py ├── placement_solution.py ├── placement_problem.py └── placement_visualizer.py ├── requirements.txt ├── CITATION.cff ├── NetRules ├── net_rules.json ├── net_rules_CCLatch.json ├── net_rules_DiffAmp.json ├── net_rules_InvAmp.json └── net_rules_MillerOpAmpCMMFB.json ├── Logs ├── Routing │ ├── DiffAmp_RLP_wireplan_log.csv │ ├── DiffAmp_RPP_wireplan_log.csv │ ├── InvAmp_RLP_wireplan_log.csv │ └── CCLatch_RLP_wireplan_log.csv ├── Stats │ ├── InvAmpRPP │ │ ├── DiffAmp_RP_placement_stats.txt │ │ ├── GmBias_RP_placement_stats.txt │ │ ├── CSAmp_RP_placement_stats.txt │ │ ├── OpAmp_RP_placement_stats.txt │ │ ├── CMMFeedback_RP_placement_stats.txt │ │ ├── InvAmp_RPP_RP_placement_stats.txt │ │ ├── MillerOpAmp_RP_placement_stats.txt │ │ └── InvAmp_RPP_placement_stats.txt │ ├── CCLatchRPP │ │ ├── CCLatch_RPP_RP_placement_stats.txt │ │ └── CCLatch_RPP_placement_stats.txt │ ├── DiffAmpRPP │ │ ├── DiffAmp_RPP_RP_placement_stats.txt │ │ └── DiffAmp_RPP_routing_stats.txt │ ├── CCLatchRLP │ │ ├── CCLatch_RLP_routing_stats.txt │ │ └── CCLatch_RLP_RL_placement_stats.txt │ ├── DiffAmpRLP │ │ ├── DiffAmp_RLP_routing_stats.txt │ │ └── DiffAmp_RLP_RL_placement_stats.txt │ └── InvAmpRLP │ │ ├── CSAmp_RL_placement_stats.txt │ │ ├── GmBias_RL_placement_stats.txt │ │ ├── OpAmp_RL_placement_stats.txt │ │ ├── DiffAmp_RL_placement_stats.txt │ │ ├── InvAmp_RLP_RL_placement_stats.txt │ │ ├── CMMFeedback_RL_placement_stats.txt │ │ ├── MillerOpAmp_RL_placement_stats.txt │ │ ├── InvAmp_RLP_routing_stats.txt │ │ └── InvAmp_RLP_placement_stats.txt ├── plot_csv_logs.py └── plot_csv_logs_simanneal.py ├── lef_def_files └── MillerOpAmp.def ├── main_init_cells.py ├── main_place_circuit.py ├── main_place_route_circuit.py ├── CircuitCaptureEval.py └── main_routing.py /Images/Bias.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/Bias.png -------------------------------------------------------------------------------- /Images/CSAmp.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/CSAmp.png -------------------------------------------------------------------------------- /Images/GmBias.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/GmBias.png -------------------------------------------------------------------------------- /Images/OpAmp.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/OpAmp.png -------------------------------------------------------------------------------- /Magic/Layouts/DiffAmp.mag: -------------------------------------------------------------------------------- 1 | magic 2 | tech sky130A 3 | timestamp 0 4 | << end >> 5 | -------------------------------------------------------------------------------- /Images/CCLatch.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/CCLatch.png -------------------------------------------------------------------------------- /Images/DiffAmp.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/DiffAmp.png -------------------------------------------------------------------------------- /Images/FlashADC.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/FlashADC.png -------------------------------------------------------------------------------- /Images/CCLatch_RPP.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/CCLatch_RPP.png -------------------------------------------------------------------------------- /Images/CMMFeedback.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/CMMFeedback.png -------------------------------------------------------------------------------- /Images/DiffAmp_RPP.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/DiffAmp_RPP.png -------------------------------------------------------------------------------- /Images/InvAmp_RPP.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/InvAmp_RPP.png -------------------------------------------------------------------------------- /Images/MillerOpAmp.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/MillerOpAmp.png -------------------------------------------------------------------------------- /Images/RALF_methodology.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/RALF_methodology.png -------------------------------------------------------------------------------- /Network/Weights/ppo_actor.pth: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Network/Weights/ppo_actor.pth -------------------------------------------------------------------------------- /Network/Weights/ppo_critic.pth: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Network/Weights/ppo_critic.pth -------------------------------------------------------------------------------- /Images/Example/DiffAmp_circuit.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/Example/DiffAmp_circuit.png -------------------------------------------------------------------------------- /Network/Weights/ppo_actor.pth.orig: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Network/Weights/ppo_actor.pth.orig -------------------------------------------------------------------------------- /Images/Example/DiffAmp_placement1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/Example/DiffAmp_placement1.png -------------------------------------------------------------------------------- /Images/Example/DiffAmp_placement2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/Example/DiffAmp_placement2.png -------------------------------------------------------------------------------- /Images/Example/DiffAmp_routing1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/Example/DiffAmp_routing1.png -------------------------------------------------------------------------------- /Images/Example/DiffAmp_routing2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Images/Example/DiffAmp_routing2.png -------------------------------------------------------------------------------- /Magic/__pycache__/DRC.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Magic/__pycache__/DRC.cpython-310.pyc -------------------------------------------------------------------------------- /Network/Weights/WireLengthModel.pth: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Network/Weights/WireLengthModel.pth -------------------------------------------------------------------------------- /Network/Weights/ppo_critic.pth.orig: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Network/Weights/ppo_critic.pth.orig -------------------------------------------------------------------------------- /PDK/__pycache__/PDK.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PDK/__pycache__/PDK.cpython-310.pyc -------------------------------------------------------------------------------- /PPO/__pycache__/utils.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PPO/__pycache__/utils.cpython-310.pyc -------------------------------------------------------------------------------- /PlacementCircuits/OpAmp_placement.pkl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PlacementCircuits/OpAmp_placement.pkl -------------------------------------------------------------------------------- /RTreeObstacles/global_obstacle.data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/RTreeObstacles/global_obstacle.data -------------------------------------------------------------------------------- /RTreeObstacles/global_obstacle.index: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/RTreeObstacles/global_obstacle.index -------------------------------------------------------------------------------- /Magic/__pycache__/Cell.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Magic/__pycache__/Cell.cpython-310.pyc -------------------------------------------------------------------------------- /Magic/__pycache__/Magic.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Magic/__pycache__/Magic.cpython-310.pyc -------------------------------------------------------------------------------- /Magic/__pycache__/utils.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Magic/__pycache__/utils.cpython-310.pyc -------------------------------------------------------------------------------- /PDK/__pycache__/Layers.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PDK/__pycache__/Layers.cpython-310.pyc -------------------------------------------------------------------------------- /PlacementCircuits/DiffAmp_placement.pkl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PlacementCircuits/DiffAmp_placement.pkl -------------------------------------------------------------------------------- /Rules/__pycache__/Rule.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Rules/__pycache__/Rule.cpython-310.pyc -------------------------------------------------------------------------------- /Rules/__pycache__/utils.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Rules/__pycache__/utils.cpython-310.pyc -------------------------------------------------------------------------------- /Magic/__pycache__/MagicDie.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Magic/__pycache__/MagicDie.cpython-310.pyc -------------------------------------------------------------------------------- /Magic/__pycache__/__init__.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Magic/__pycache__/__init__.cpython-310.pyc -------------------------------------------------------------------------------- /PDK/__pycache__/__init__.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PDK/__pycache__/__init__.cpython-310.pyc -------------------------------------------------------------------------------- /PPO/__pycache__/__init__.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PPO/__pycache__/__init__.cpython-310.pyc -------------------------------------------------------------------------------- /PlacementCircuits/FlashADC_placement.pkl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PlacementCircuits/FlashADC_placement.pkl -------------------------------------------------------------------------------- /PlacementCircuits/InvAmp_RLP_placement.pkl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PlacementCircuits/InvAmp_RLP_placement.pkl -------------------------------------------------------------------------------- /PlacementCircuits/InvAmp_RPP_placement.pkl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PlacementCircuits/InvAmp_RPP_placement.pkl -------------------------------------------------------------------------------- /Rules/__pycache__/NetRules.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Rules/__pycache__/NetRules.cpython-310.pyc -------------------------------------------------------------------------------- /Environment/__pycache__/RUDY.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Environment/__pycache__/RUDY.cpython-310.pyc -------------------------------------------------------------------------------- /Magic/__pycache__/MacroCell.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Magic/__pycache__/MacroCell.cpython-310.pyc -------------------------------------------------------------------------------- /Magic/__pycache__/MagicLayer.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Magic/__pycache__/MagicLayer.cpython-310.pyc -------------------------------------------------------------------------------- /Network/Weights/D2RN_BatchNorm/ppo_actor.pth: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Network/Weights/D2RN_BatchNorm/ppo_actor.pth -------------------------------------------------------------------------------- /Network/__pycache__/__init__.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Network/__pycache__/__init__.cpython-310.pyc -------------------------------------------------------------------------------- /PlacementCircuits/CCLatch_RLP_placement.pkl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PlacementCircuits/CCLatch_RLP_placement.pkl -------------------------------------------------------------------------------- /PlacementCircuits/CCLatch_RPP_placement.pkl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PlacementCircuits/CCLatch_RPP_placement.pkl -------------------------------------------------------------------------------- /PlacementCircuits/DiffAmp_RLP2_placement.pkl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PlacementCircuits/DiffAmp_RLP2_placement.pkl -------------------------------------------------------------------------------- /PlacementCircuits/DiffAmp_RLP_placement.pkl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PlacementCircuits/DiffAmp_RLP_placement.pkl -------------------------------------------------------------------------------- /PlacementCircuits/DiffAmp_RPP_placement.pkl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PlacementCircuits/DiffAmp_RPP_placement.pkl -------------------------------------------------------------------------------- /Routing_v2/__pycache__/Grid.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Routing_v2/__pycache__/Grid.cpython-310.pyc -------------------------------------------------------------------------------- /Routing_v2/__pycache__/Path.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Routing_v2/__pycache__/Path.cpython-310.pyc -------------------------------------------------------------------------------- /Routing_v2/__pycache__/Pins.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Routing_v2/__pycache__/Pins.cpython-310.pyc -------------------------------------------------------------------------------- /Routing_v2/__pycache__/Route.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Routing_v2/__pycache__/Route.cpython-310.pyc -------------------------------------------------------------------------------- /Routing_v2/__pycache__/utils.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Routing_v2/__pycache__/utils.cpython-310.pyc -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/simulation/MillerOP.raw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Circuits/Examples/OpAmp/simulation/MillerOP.raw -------------------------------------------------------------------------------- /Environment/__pycache__/utils.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Environment/__pycache__/utils.cpython-310.pyc -------------------------------------------------------------------------------- /Magic/__pycache__/MagicParser.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Magic/__pycache__/MagicParser.cpython-310.pyc -------------------------------------------------------------------------------- /Magic/__pycache__/MagicTerminal.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Magic/__pycache__/MagicTerminal.cpython-310.pyc -------------------------------------------------------------------------------- /Network/Weights/D2RN_BatchNorm/ppo_critic.pth: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Network/Weights/D2RN_BatchNorm/ppo_critic.pth -------------------------------------------------------------------------------- /Network/__pycache__/D2RL_Actor.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Network/__pycache__/D2RL_Actor.cpython-310.pyc -------------------------------------------------------------------------------- /Network/__pycache__/D2RL_Critic.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Network/__pycache__/D2RL_Critic.cpython-310.pyc -------------------------------------------------------------------------------- /Network/__pycache__/GAT_Policy.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Network/__pycache__/GAT_Policy.cpython-310.pyc -------------------------------------------------------------------------------- /PPO/__pycache__/Placement_PPO.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PPO/__pycache__/Placement_PPO.cpython-310.pyc -------------------------------------------------------------------------------- /Routing_v2/__pycache__/Router.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Routing_v2/__pycache__/Router.cpython-310.pyc -------------------------------------------------------------------------------- /Rules/__pycache__/RoutingRules.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Rules/__pycache__/RoutingRules.cpython-310.pyc -------------------------------------------------------------------------------- /lef_def_parser/__pycache__/util.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/lef_def_parser/__pycache__/util.cpython-310.pyc -------------------------------------------------------------------------------- /Environment/__pycache__/__init__.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Environment/__pycache__/__init__.cpython-310.pyc -------------------------------------------------------------------------------- /Routing_v2/__pycache__/Geometrics.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Routing_v2/__pycache__/Geometrics.cpython-310.pyc -------------------------------------------------------------------------------- /Routing_v2/__pycache__/Obstacles.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Routing_v2/__pycache__/Obstacles.cpython-310.pyc -------------------------------------------------------------------------------- /Routing_v2/__pycache__/Primitives.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Routing_v2/__pycache__/Primitives.cpython-310.pyc -------------------------------------------------------------------------------- /Routing_v2/__pycache__/TileRouter.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Routing_v2/__pycache__/TileRouter.cpython-310.pyc -------------------------------------------------------------------------------- /Rules/__pycache__/PlacementRules.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Rules/__pycache__/PlacementRules.cpython-310.pyc -------------------------------------------------------------------------------- /SchematicCapture/__pycache__/Net.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/SchematicCapture/__pycache__/Net.cpython-310.pyc -------------------------------------------------------------------------------- /Environment/__pycache__/Environment.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Environment/__pycache__/Environment.cpython-310.pyc -------------------------------------------------------------------------------- /Environment/__pycache__/cell_sliding.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Environment/__pycache__/cell_sliding.cpython-310.pyc -------------------------------------------------------------------------------- /Network/__pycache__/GAT_D2RL_Actor.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Network/__pycache__/GAT_D2RL_Actor.cpython-310.pyc -------------------------------------------------------------------------------- /Network/__pycache__/GAT_D2RL_Critic.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Network/__pycache__/GAT_D2RL_Critic.cpython-310.pyc -------------------------------------------------------------------------------- /Routing_v2/__pycache__/PlanningGraph.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Routing_v2/__pycache__/PlanningGraph.cpython-310.pyc -------------------------------------------------------------------------------- /Routing_v2/__pycache__/WirePlanning.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Routing_v2/__pycache__/WirePlanning.cpython-310.pyc -------------------------------------------------------------------------------- /SchematicCapture/__pycache__/Circuit.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/SchematicCapture/__pycache__/Circuit.cpython-310.pyc -------------------------------------------------------------------------------- /SchematicCapture/__pycache__/Devices.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/SchematicCapture/__pycache__/Devices.cpython-310.pyc -------------------------------------------------------------------------------- /SchematicCapture/__pycache__/Netlist.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/SchematicCapture/__pycache__/Netlist.cpython-310.pyc -------------------------------------------------------------------------------- /SchematicCapture/__pycache__/Ports.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/SchematicCapture/__pycache__/Ports.cpython-310.pyc -------------------------------------------------------------------------------- /SchematicCapture/__pycache__/RString.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/SchematicCapture/__pycache__/RString.cpython-310.pyc -------------------------------------------------------------------------------- /SchematicCapture/__pycache__/utils.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/SchematicCapture/__pycache__/utils.cpython-310.pyc -------------------------------------------------------------------------------- /lef_def_parser/__pycache__/def_util.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/lef_def_parser/__pycache__/def_util.cpython-310.pyc -------------------------------------------------------------------------------- /Circuits/Examples/InvAmp/simulation/MillerOpAmp_tb.raw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Circuits/Examples/InvAmp/simulation/MillerOpAmp_tb.raw -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/simulation/MillerOpAmp_tb.raw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Circuits/Examples/OpAmp/simulation/MillerOpAmp_tb.raw -------------------------------------------------------------------------------- /Magic/__pycache__/MagicTerminal_utils.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/Magic/__pycache__/MagicTerminal_utils.cpython-310.pyc -------------------------------------------------------------------------------- /SchematicCapture/__pycache__/__init__.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/SchematicCapture/__pycache__/__init__.cpython-310.pyc -------------------------------------------------------------------------------- /lef_def_parser/__pycache__/def_parser.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/lef_def_parser/__pycache__/def_parser.cpython-310.pyc -------------------------------------------------------------------------------- /SchematicCapture/__pycache__/Primitives.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/SchematicCapture/__pycache__/Primitives.cpython-310.pyc -------------------------------------------------------------------------------- /PPO/__pycache__/Environment_Multiprocessing.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/PPO/__pycache__/Environment_Multiprocessing.cpython-310.pyc -------------------------------------------------------------------------------- /SchematicCapture/__pycache__/NGSpiceParser.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/SchematicCapture/__pycache__/NGSpiceParser.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_solver/__pycache__/solver.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_solver/__pycache__/solver.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_solver/__pycache__/utils.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_solver/__pycache__/utils.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/__pycache__/utils.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/__pycache__/utils.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_solver/__pycache__/__init__.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_solver/__pycache__/__init__.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_solver/__pycache__/floorplan.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_solver/__pycache__/floorplan.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_solver/__pycache__/problem.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_solver/__pycache__/problem.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_solver/__pycache__/solution.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_solver/__pycache__/solution.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_solver/__pycache__/__version__.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_solver/__pycache__/__version__.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_solver/__pycache__/visualizer.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_solver/__pycache__/visualizer.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_solver/__pycache__/cell_sliding.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_solver/__pycache__/cell_sliding.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_solver/__pycache__/sequence_pair.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_solver/__pycache__/sequence_pair.cpython-310.pyc -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/simulation/bsim4v5.out: -------------------------------------------------------------------------------- 1 | 2 | Checking parameters for BSIM 4.5 model x1.x1.x2.xm2:sky130_fd_pr__nfet_01v8__model.3 3 | Warning: Eta0 = -0.0339801 is negative. 4 | -------------------------------------------------------------------------------- /rectangle_packing_placement/__pycache__/cell_sliding.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/__pycache__/cell_sliding.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/__pycache__/placement_solver.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/__pycache__/placement_solver.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/__pycache__/placement_problem.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/__pycache__/placement_problem.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/__pycache__/placement_solution.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/__pycache__/placement_solution.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/__pycache__/placement_floorplan.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/__pycache__/placement_floorplan.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/__pycache__/placement_visualizer.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/__pycache__/placement_visualizer.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/__pycache__/placement_sequence_pair.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/__pycache__/placement_sequence_pair.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/rectangle_packing_solver/__pycache__/solver.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/rectangle_packing_solver/__pycache__/solver.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/rectangle_packing_solver/__pycache__/__init__.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/rectangle_packing_solver/__pycache__/__init__.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/rectangle_packing_solver/__pycache__/problem.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/rectangle_packing_solver/__pycache__/problem.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/rectangle_packing_solver/__pycache__/solution.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/rectangle_packing_solver/__pycache__/solution.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/rectangle_packing_solver/__pycache__/__version__.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/rectangle_packing_solver/__pycache__/__version__.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/rectangle_packing_solver/__pycache__/floorplan.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/rectangle_packing_solver/__pycache__/floorplan.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/rectangle_packing_solver/__pycache__/visualizer.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/rectangle_packing_solver/__pycache__/visualizer.cpython-310.pyc -------------------------------------------------------------------------------- /rectangle_packing_placement/rectangle_packing_solver/__pycache__/sequence_pair.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JakobRat/RALF/HEAD/rectangle_packing_placement/rectangle_packing_solver/__pycache__/sequence_pair.cpython-310.pyc -------------------------------------------------------------------------------- /requirements.txt: -------------------------------------------------------------------------------- 1 | matplotlib==3.5.1 2 | networkx==3.1 3 | numpy==1.25.1 4 | pandas==2.0.3 5 | prettytable==3.9.0 6 | pygame==2.5.0 7 | Rtree==1.0.1 8 | scikit_learn==1.3.0 9 | simanneal==0.5.0 10 | torch==2.0.1 11 | torch_geometric==2.3.1 12 | tqdm==4.65.0 13 | -------------------------------------------------------------------------------- /CITATION.cff: -------------------------------------------------------------------------------- 1 | cff-version: 1.2.0 2 | message: "If you use this software, please cite it as below." 3 | authors: 4 | - family-names: "Jakob" 5 | given-names: "Ratschenberger" 6 | orcid: "https://orcid.org/0000-0000-0000-0000" 7 | title: "RALF" 8 | version: 1.0.0 9 | doi: 10.5281/zenodo.1234 10 | date-released: 2023-11-15 11 | url: "https://github.com/JakobRat/RALF" 12 | -------------------------------------------------------------------------------- /NetRules/net_rules.json: -------------------------------------------------------------------------------- 1 | [ 2 | ["MinNetWireWidth", 3 | { 4 | "net" : "vmid", 5 | "min_width" : 20 6 | } 7 | ], 8 | ["Ports", 9 | { 10 | "nets" : ["Vss", "Vdd", "Vp", "Vn", "Vbp", "Vbn", "Vop","Von"] 11 | } 12 | ], 13 | ["PowerNets", 14 | { 15 | "nets" : ["Vdd", "Vss"] 16 | } 17 | ] 18 | ] -------------------------------------------------------------------------------- /Logs/Routing/DiffAmp_RLP_wireplan_log.csv: -------------------------------------------------------------------------------- 1 | ,penalty,crossing_nets,overflow 2 | 0,200.0,2,0.0 3 | 1,400.0,2,0.0 4 | 2,400.69,0,0.69 5 | 3,600.69,2,0.0 6 | 4,601.38,0,0.69 7 | 5,602.08,0,0.69 8 | 6,602.77,0,0.69 9 | 7,603.46,0,0.69 10 | 8,604.15,0,0.69 11 | 9,604.85,0,0.69 12 | 10,604.85,0,0.0 13 | 11,604.85,0,0.0 14 | 12,604.85,0,0.0 15 | 13,604.85,0,0.0 16 | 14,604.85,0,0.0 17 | -------------------------------------------------------------------------------- /Circuits/Primitives/RString/RString1.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/Primitives/RString/RString.sch 2 | **.subckt RString Vh VB Vmid Vl 3 | *.iopin Vh 4 | *.iopin VB 5 | *.iopin Vmid 6 | *.iopin Vl 7 | XR1 Vmid Vh VB sky130_fd_pr__res_xhigh_po_0p35 L=0.35 mult=1 m=1 8 | XR2 Vl Vmid VB sky130_fd_pr__res_xhigh_po_0p35 L=0.35 mult=1 m=1 9 | **.ends 10 | .end 11 | -------------------------------------------------------------------------------- /Circuits/Primitives/RString/RString2.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/Primitives/RString/RString.sch 2 | **.subckt RString Vh VB Vmid Vl 3 | *.iopin Vh 4 | *.iopin VB 5 | *.iopin Vmid 6 | *.iopin Vl 7 | XR1 Vmid Vh VB sky130_fd_pr__res_xhigh_po_0p35 L=0.35 mult=1 m=1 8 | XR2 Vmid Vl VB sky130_fd_pr__res_xhigh_po_0p35 L=0.35 mult=1 m=1 9 | **.ends 10 | .end 11 | -------------------------------------------------------------------------------- /Circuits/Primitives/RString/RString3.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/Primitives/RString/RString.sch 2 | **.subckt RString Vh VB Vmid Vl 3 | *.iopin Vh 4 | *.iopin VB 5 | *.iopin Vmid 6 | *.iopin Vl 7 | XR1 Vh Vmid VB sky130_fd_pr__res_xhigh_po_0p35 L=0.35 mult=1 m=1 8 | XR2 Vl Vmid VB sky130_fd_pr__res_xhigh_po_0p35 L=0.35 mult=1 m=1 9 | **.ends 10 | .end 11 | -------------------------------------------------------------------------------- /Circuits/Primitives/RString/RString4.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/Primitives/RString/RString.sch 2 | **.subckt RString Vh VB Vmid Vl 3 | *.iopin Vh 4 | *.iopin VB 5 | *.iopin Vmid 6 | *.iopin Vl 7 | XR1 Vh Vmid VB sky130_fd_pr__res_xhigh_po_0p35 L=0.35 mult=1 m=1 8 | XR2 Vmid Vl VB sky130_fd_pr__res_xhigh_po_0p35 L=0.35 mult=1 m=1 9 | **.ends 10 | .end 11 | -------------------------------------------------------------------------------- /Logs/Routing/DiffAmp_RPP_wireplan_log.csv: -------------------------------------------------------------------------------- 1 | ,penalty,crossing_nets,overflow 2 | 0,100.0,1,0 3 | 1,100.0,0,0 4 | 2,100.0,0,0 5 | 3,100.0,0,0 6 | 4,100.0,0,0 7 | 5,100.0,0,0 8 | 6,100.0,0,0 9 | 7,100.0,0,0 10 | 8,100.0,0,0 11 | 9,100.0,0,0 12 | 10,100.0,0,0 13 | 11,100.0,0,0 14 | 12,100.0,0,0 15 | 13,100.0,0,0 16 | 14,100.0,0,0 17 | 15,100.0,0,0 18 | 16,100.0,0,0 19 | 17,100.0,0,0 20 | 18,100.0,0,0 21 | 19,100.0,0,0 22 | -------------------------------------------------------------------------------- /Logs/Routing/InvAmp_RLP_wireplan_log.csv: -------------------------------------------------------------------------------- 1 | ,penalty,crossing_nets,overflow 2 | 0,1300.0,13,0 3 | 1,2100.0,8,0 4 | 2,2600.0,5,0 5 | 3,2700.0,1,0 6 | 4,2800.0,1,0 7 | 5,2900.0,1,0 8 | 6,3000.0,1,0 9 | 7,3100.0,1,0 10 | 8,3200.0,1,0 11 | 9,3200.0,0,0 12 | 10,3200.0,0,0 13 | 11,3200.0,0,0 14 | 12,3200.0,0,0 15 | 13,3200.0,0,0 16 | 14,3200.0,0,0 17 | 15,3200.0,0,0 18 | 16,3200.0,0,0 19 | 17,3200.0,0,0 20 | 18,3200.0,0,0 21 | 19,3200.0,0,0 22 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRPP/DiffAmp_RP_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------+----------+ 2 | | Name | Value | 3 | +----------------+----------+ 4 | | Circuit | DiffAmp | 5 | | Time taken [s] | 808 | 6 | | Placements | 250000 | 7 | | Total HPWL | 2148.0 | 8 | | Congestion | 10212.37 | 9 | | Total width | 737.0 | 10 | | Total height | 692.5 | 11 | | Area | 510372.5 | 12 | +----------------+----------+ 13 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRPP/GmBias_RP_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------+----------+ 2 | | Name | Value | 3 | +----------------+----------+ 4 | | Circuit | GmBias | 5 | | Time taken [s] | 1299 | 6 | | Placements | 250000 | 7 | | Total HPWL | 3839.0 | 8 | | Congestion | 51114.43 | 9 | | Total width | 821.5 | 10 | | Total height | 1217.0 | 11 | | Area | 999765.5 | 12 | +----------------+----------+ 13 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRPP/CSAmp_RP_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------+-----------+ 2 | | Name | Value | 3 | +----------------+-----------+ 4 | | Circuit | CSAmp | 5 | | Time taken [s] | 907 | 6 | | Placements | 250000 | 7 | | Total HPWL | 2592.0 | 8 | | Congestion | 0.0 | 9 | | Total width | 1384.0 | 10 | | Total height | 1179.0 | 11 | | Area | 1631736.0 | 12 | +----------------+-----------+ 13 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRPP/OpAmp_RP_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------+-----------+ 2 | | Name | Value | 3 | +----------------+-----------+ 4 | | Circuit | OpAmp | 5 | | Time taken [s] | 2136 | 6 | | Placements | 250000 | 7 | | Total HPWL | 21766.75 | 8 | | Congestion | 726675.04 | 9 | | Total width | 3318.0 | 10 | | Total height | 2857.75 | 11 | | Area | 9482014.5 | 12 | +----------------+-----------+ 13 | -------------------------------------------------------------------------------- /Logs/Routing/CCLatch_RLP_wireplan_log.csv: -------------------------------------------------------------------------------- 1 | ,penalty,crossing_nets,overflow 2 | 0,0.0,0,0.0 3 | 1,100.0,1,0.0 4 | 2,200.0,1,0.0 5 | 3,200.0,0,0.0 6 | 4,400.0,2,0.0 7 | 5,400.32,0,0.32 8 | 6,500.32,1,0.0 9 | 7,500.65,0,0.32 10 | 8,500.97,0,0.32 11 | 9,501.3,0,0.32 12 | 10,501.62,0,0.32 13 | 11,501.95,0,0.32 14 | 12,502.27,0,0.32 15 | 13,502.6,0,0.32 16 | 14,502.6,0,0.0 17 | 15,502.92,0,0.32 18 | 16,503.25,0,0.32 19 | 17,503.57,0,0.32 20 | 18,703.57,2,0.0 21 | 19,703.57,0,0.0 22 | -------------------------------------------------------------------------------- /Logs/Stats/CCLatchRPP/CCLatch_RPP_RP_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------+-------------+ 2 | | Name | Value | 3 | +----------------+-------------+ 4 | | Circuit | CCLatch_RPP | 5 | | Time taken [s] | 800 | 6 | | Placements | 250000 | 7 | | Total HPWL | 2629.0 | 8 | | Congestion | 19314.53 | 9 | | Total width | 904.0 | 10 | | Total height | 775.0 | 11 | | Area | 700600.0 | 12 | +----------------+-------------+ 13 | -------------------------------------------------------------------------------- /Logs/Stats/DiffAmpRPP/DiffAmp_RPP_RP_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------+-------------+ 2 | | Name | Value | 3 | +----------------+-------------+ 4 | | Circuit | DiffAmp_RPP | 5 | | Time taken [s] | 822 | 6 | | Placements | 250000 | 7 | | Total HPWL | 2148.0 | 8 | | Congestion | 10212.37 | 9 | | Total width | 737.0 | 10 | | Total height | 692.5 | 11 | | Area | 510372.5 | 12 | +----------------+-------------+ 13 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRPP/CMMFeedback_RP_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------+-------------+ 2 | | Name | Value | 3 | +----------------+-------------+ 4 | | Circuit | CMMFeedback | 5 | | Time taken [s] | 1470 | 6 | | Placements | 250000 | 7 | | Total HPWL | 4027.0 | 8 | | Congestion | 20066.19 | 9 | | Total width | 1640.5 | 10 | | Total height | 1114.5 | 11 | | Area | 1828337.25 | 12 | +----------------+-------------+ 13 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRPP/InvAmp_RPP_RP_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------+-------------+ 2 | | Name | Value | 3 | +----------------+-------------+ 4 | | Circuit | InvAmp_RPP | 5 | | Time taken [s] | 2074 | 6 | | Placements | 250000 | 7 | | Total HPWL | 22451.3 | 8 | | Congestion | 725501.6 | 9 | | Total width | 3390.76 | 10 | | Total height | 3318.5 | 11 | | Area | 11252237.06 | 12 | +----------------+-------------+ 13 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRPP/MillerOpAmp_RP_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------+-------------+ 2 | | Name | Value | 3 | +----------------+-------------+ 4 | | Circuit | MillerOpAmp | 5 | | Time taken [s] | 2001 | 6 | | Placements | 250000 | 7 | | Total HPWL | 12883.0 | 8 | | Congestion | 174655.06 | 9 | | Total width | 2502.0 | 10 | | Total height | 2076.5 | 11 | | Area | 5195403.0 | 12 | +----------------+-------------+ 13 | -------------------------------------------------------------------------------- /Logs/Stats/CCLatchRLP/CCLatch_RLP_routing_stats.txt: -------------------------------------------------------------------------------- 1 | +----------+--------+-------+ 2 | | Net name | Length | #Vias | 3 | +----------+--------+-------+ 4 | | outn | 806.0 | 5 | 5 | | out | 580.0 | 3 | 6 | | Vdd | 452.0 | 3 | 7 | | vmid | 424.0 | 3 | 8 | | Vss | 294.0 | 3 | 9 | | clk | 130.0 | 2 | 10 | | inn | 0 | 1 | 11 | | in | 0 | 1 | 12 | +----------+--------+-------+ 13 | | Total | 2686.0 | 21 | 14 | +----------+--------+-------+ 15 | -------------------------------------------------------------------------------- /Magic/Layouts/R1.mag: -------------------------------------------------------------------------------- 1 | magic 2 | tech sky130A 3 | magscale 1 2 4 | timestamp 1687621788 5 | << xpolycontact >> 6 | rect -35 100 35 532 7 | rect -35 -532 35 -100 8 | << xpolyres >> 9 | rect -35 -100 35 100 10 | << viali >> 11 | rect -19 117 19 514 12 | rect -19 -514 19 -117 13 | << metal1 >> 14 | rect -25 514 25 526 15 | rect -25 117 -19 514 16 | rect 19 117 25 514 17 | rect -25 105 25 117 18 | rect -25 -117 25 -105 19 | rect -25 -514 -19 -117 20 | rect 19 -514 25 -117 21 | rect -25 -526 25 -514 22 | << res0p35 >> 23 | rect -37 -102 37 102 24 | << end >> 25 | -------------------------------------------------------------------------------- /Logs/Stats/DiffAmpRLP/DiffAmp_RLP_routing_stats.txt: -------------------------------------------------------------------------------- 1 | +----------+--------+-------+ 2 | | Net name | Length | #Vias | 3 | +----------+--------+-------+ 4 | | Vdd | 660.0 | 5 | 5 | | Von | 406.0 | 2 | 6 | | Vop | 390.0 | 2 | 7 | | Vss | 222.0 | 3 | 8 | | vmid | 206.0 | 2 | 9 | | Vbp | 54.0 | 2 | 10 | | Vn | 0 | 1 | 11 | | Vp | 0 | 1 | 12 | | Vbn | 0 | 1 | 13 | +----------+--------+-------+ 14 | | Total | 1938.0 | 19 | 15 | +----------+--------+-------+ 16 | -------------------------------------------------------------------------------- /Logs/Stats/DiffAmpRPP/DiffAmp_RPP_routing_stats.txt: -------------------------------------------------------------------------------- 1 | +----------+--------+-------+ 2 | | Net name | Length | #Vias | 3 | +----------+--------+-------+ 4 | | Vss | 516.0 | 3 | 5 | | Vdd | 662.0 | 3 | 6 | | Vop | 410.0 | 2 | 7 | | Von | 300.0 | 2 | 8 | | vmid | 342.0 | 4 | 9 | | Vbp | 56.0 | 2 | 10 | | Vn | 0 | 1 | 11 | | Vp | 0 | 1 | 12 | | Vbn | 0 | 1 | 13 | +----------+--------+-------+ 14 | | Total | 2286.0 | 19 | 15 | +----------+--------+-------+ 16 | -------------------------------------------------------------------------------- /Circuits/Primitives/DiffLoad/DiffLoad_sym.spice: -------------------------------------------------------------------------------- 1 | XM1 Vd1 Vg Vs1 Vb sky130_fd_pr__pfet_01v8 L=0.35 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 2 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 3 | + sa=0 sb=0 sd=0 mult=1 m=1 4 | XM2 Vd2 Vg Vs2 Vb sky130_fd_pr__pfet_01v8 L=0.35 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 5 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 6 | + sa=0 sb=0 sd=0 mult=1 m=1 7 | .end -------------------------------------------------------------------------------- /Circuits/Primitives/DiffLoad/DiffLoad_unsym.spice: -------------------------------------------------------------------------------- 1 | XM1 Vg Vg Vb Vb sky130_fd_pr__pfet_01v8 L=0.35 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 2 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 3 | + sa=0 sb=0 sd=0 mult=1 m=1 4 | XM2 Vd2 Vg Vb Vb sky130_fd_pr__pfet_01v8 L=0.35 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 5 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 6 | + sa=0 sb=0 sd=0 mult=1 m=1 7 | .end -------------------------------------------------------------------------------- /Circuits/Primitives/DiffLoad/DiffLoad_sym_Vs_Vb_connected.spice: -------------------------------------------------------------------------------- 1 | XM1 Vd1 Vg Vb Vb sky130_fd_pr__pfet_01v8 L=0.35 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 2 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 3 | + sa=0 sb=0 sd=0 mult=1 m=1 4 | XM2 Vd2 Vg Vb Vb sky130_fd_pr__pfet_01v8 L=0.35 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 5 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 6 | + sa=0 sb=0 sd=0 mult=1 m=1 7 | .end -------------------------------------------------------------------------------- /Circuits/Primitives/DiffLoad/DiffLoad_unsym_Vs_Vb_connected copy.spice: -------------------------------------------------------------------------------- 1 | XM1 Vg Vg Vs1 Vb sky130_fd_pr__pfet_01v8 L=0.35 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 2 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 3 | + sa=0 sb=0 sd=0 mult=1 m=1 4 | XM2 Vd2 Vg Vs2 Vb sky130_fd_pr__pfet_01v8 L=0.35 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 5 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 6 | + sa=0 sb=0 sd=0 mult=1 m=1 7 | .end -------------------------------------------------------------------------------- /NetRules/net_rules_CCLatch.json: -------------------------------------------------------------------------------- 1 | [ 2 | ["MinNetWireWidth", 3 | { 4 | "net" : "vmid", 5 | "min_width" : 28 6 | } 7 | ], 8 | ["MinNetWireWidth", 9 | { 10 | "net" : "Vss", 11 | "min_width" : 28 12 | } 13 | ], 14 | ["MinNetWireWidth", 15 | { 16 | "net" : "Vdd", 17 | "min_width" : 28 18 | } 19 | ], 20 | ["Ports", 21 | { 22 | "nets" : ["Vss", "Vdd", "inn", "in", "outn", "out","clk"] 23 | } 24 | ], 25 | ["PowerNets", 26 | { 27 | "nets" : ["Vdd", "Vss"] 28 | } 29 | ] 30 | ] -------------------------------------------------------------------------------- /NetRules/net_rules_DiffAmp.json: -------------------------------------------------------------------------------- 1 | [ 2 | ["MinNetWireWidth", 3 | { 4 | "net" : "vmid", 5 | "min_width" : 28 6 | } 7 | ], 8 | ["MinNetWireWidth", 9 | { 10 | "net" : "Vss", 11 | "min_width" : 28 12 | } 13 | ], 14 | ["MinNetWireWidth", 15 | { 16 | "net" : "Vdd", 17 | "min_width" : 28 18 | } 19 | ], 20 | ["Ports", 21 | { 22 | "nets" : ["Vss", "Vdd", "Vp", "Vn", "Vbp", "Vbn", "Vop","Von"] 23 | } 24 | ], 25 | ["PowerNets", 26 | { 27 | "nets" : ["Vdd", "Vss"] 28 | } 29 | ] 30 | ] -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRLP/CSAmp_RL_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------------+-----------+ 2 | | Name | Value | 3 | +----------------------+-----------+ 4 | | Circuit | CSAmp | 5 | | Time taken [s] | 4486 | 6 | | Placements | 250000 | 7 | | Placements per batch | 100 | 8 | | Env. size | 4326x4326 | 9 | | Solution placement | 1 | 10 | | Total HPWL | 2661.0 | 11 | | Congestion | 0.0 | 12 | | Reward | -2661.0 | 13 | | Total width | 1179.0 | 14 | | Total height | 1384.0 | 15 | | Area | 1631736.0 | 16 | +----------------------+-----------+ 17 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRLP/GmBias_RL_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------------+-----------+ 2 | | Name | Value | 3 | +----------------------+-----------+ 4 | | Circuit | GmBias | 5 | | Time taken [s] | 5583 | 6 | | Placements | 250000 | 7 | | Placements per batch | 100 | 8 | | Env. size | 2623x2623 | 9 | | Solution placement | 227766 | 10 | | Total HPWL | 3831.0 | 11 | | Congestion | 50617.62 | 12 | | Reward | -4055.98 | 13 | | Total width | 1022.0 | 14 | | Total height | 840.5 | 15 | | Area | 858991.0 | 16 | +----------------------+-----------+ 17 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRLP/OpAmp_RL_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------------+-----------+ 2 | | Name | Value | 3 | +----------------------+-----------+ 4 | | Circuit | OpAmp | 5 | | Time taken [s] | 4266 | 6 | | Placements | 250000 | 7 | | Placements per batch | 100 | 8 | | Env. size | 5094x5094 | 9 | | Solution placement | 30877 | 10 | | Total HPWL | 22121.0 | 11 | | Congestion | 772928.87 | 12 | | Reward | -23000.16 | 13 | | Total width | 2707.0 | 14 | | Total height | 3628.5 | 15 | | Area | 9822349.5 | 16 | +----------------------+-----------+ 17 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRLP/DiffAmp_RL_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------------+-----------+ 2 | | Name | Value | 3 | +----------------------+-----------+ 4 | | Circuit | DiffAmp | 5 | | Time taken [s] | 3102 | 6 | | Placements | 250000 | 7 | | Placements per batch | 100 | 8 | | Env. size | 1558x1558 | 9 | | Solution placement | 130019 | 10 | | Total HPWL | 1939.0 | 11 | | Congestion | 4122.89 | 12 | | Reward | -2003.21 | 13 | | Total width | 854.0 | 14 | | Total height | 737.0 | 15 | | Area | 629398.0 | 16 | +----------------------+-----------+ 17 | -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/Bias.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2} 2 | K {type=subcircuit 3 | format="@name @pinlist @symname" 4 | template="name=x1" 5 | } 6 | 7 | T {@symname} -36 -6 0 0 0.3 0.3 {} 8 | T {@name} 135 -42 0 0 0.2 0.2 {} 9 | L 4 -130 -30 130 -30 {} 10 | L 4 -130 30 130 30 {} 11 | L 4 -130 -30 -130 30 {} 12 | L 4 130 -30 130 30 {} 13 | B 5 147.5 -22.5 152.5 -17.5 {name=Vdd dir=inout} 14 | L 7 130 -20 150 -20 {} 15 | T {Vdd} 125 -24 0 1 0.2 0.2 {} 16 | B 5 147.5 -2.5 152.5 2.5 {name=Vbias sig_type=std_logic dir=out} 17 | L 4 130 0 150 0 {} 18 | T {Vbias} 125 -4 0 1 0.2 0.2 {} 19 | B 5 147.5 17.5 152.5 22.5 {name=Vss dir=inout} 20 | L 7 130 20 150 20 {} 21 | T {Vss} 125 16 0 1 0.2 0.2 {} 22 | -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/GmBias.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2} 2 | K {type=subcircuit 3 | format="@name @pinlist @symname" 4 | template="name=x1" 5 | } 6 | 7 | T {@symname} -45 -6 0 0 0.3 0.3 {} 8 | T {@name} 135 -42 0 0 0.2 0.2 {} 9 | L 4 -130 -30 130 -30 {} 10 | L 4 -130 30 130 30 {} 11 | L 4 -130 -30 -130 30 {} 12 | L 4 130 -30 130 30 {} 13 | B 5 147.5 -22.5 152.5 -17.5 {name=Vdd dir=inout} 14 | L 7 130 -20 150 -20 {} 15 | T {Vdd} 125 -24 0 1 0.2 0.2 {} 16 | B 5 147.5 -2.5 152.5 2.5 {name=Vbias sig_type=std_logic dir=out} 17 | L 4 130 0 150 0 {} 18 | T {Vbias} 125 -4 0 1 0.2 0.2 {} 19 | B 5 147.5 17.5 152.5 22.5 {name=Vss dir=inout} 20 | L 7 130 20 150 20 {} 21 | T {Vss} 125 16 0 1 0.2 0.2 {} 22 | -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/GmBiasP.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2} 2 | K {type=subcircuit 3 | format="@name @pinlist @symname" 4 | template="name=x1" 5 | } 6 | T {@symname} -49.5 -6 0 0 0.3 0.3 {} 7 | T {@name} 135 -42 0 0 0.2 0.2 {} 8 | L 4 -130 -30 130 -30 {} 9 | L 4 -130 30 130 30 {} 10 | L 4 -130 -30 -130 30 {} 11 | L 4 130 -30 130 30 {} 12 | B 5 147.5 -22.5 152.5 -17.5 {name=Vdd dir=inout} 13 | L 7 130 -20 150 -20 {} 14 | T {Vdd} 125 -24 0 1 0.2 0.2 {} 15 | B 5 147.5 -2.5 152.5 2.5 {name=Vbias sig_type=std_logic dir=out} 16 | L 4 130 0 150 0 {} 17 | T {Vbias} 125 -4 0 1 0.2 0.2 {} 18 | B 5 147.5 17.5 152.5 22.5 {name=Vss dir=inout} 19 | L 7 130 20 150 20 {} 20 | T {Vss} 125 16 0 1 0.2 0.2 {} 21 | -------------------------------------------------------------------------------- /Logs/Stats/CCLatchRPP/CCLatch_RPP_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +------------+----------+------+ 2 | | Parameter | Value | Unit | 3 | +------------+----------+------+ 4 | | HPWL(vmid) | 4.33 | um | 5 | | HPWL(clk) | 1.3 | um | 6 | | HPWL(Vss) | 2.92 | um | 7 | | HPWL(outn) | 5.32 | um | 8 | | HPWL(out) | 7.9 | um | 9 | | HPWL(in) | 0.0 | um | 10 | | HPWL(inn) | 0.0 | um | 11 | | HPWL(Vdd) | 4.53 | um | 12 | | Total HPWL | 26.29 | um | 13 | | Congestion | 19314.53 | - | 14 | | Width | 9.04 | um | 15 | | Height | 7.75 | um | 16 | | Area | 70.06 | um2 | 17 | | #Cells | 3 | - | 18 | +------------+----------+------+ 19 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRLP/InvAmp_RLP_RL_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------------+------------+ 2 | | Name | Value | 3 | +----------------------+------------+ 4 | | Circuit | InvAmp_RLP | 5 | | Time taken [s] | 4222 | 6 | | Placements | 250000 | 7 | | Placements per batch | 100 | 8 | | Env. size | 5174x5174 | 9 | | Solution placement | 81939 | 10 | | Total HPWL | 20092.75 | 11 | | Congestion | 635917.49 | 12 | | Reward | -20890.19 | 13 | | Total width | 3628.5 | 14 | | Total height | 3480.0 | 15 | | Area | 12627180.0 | 16 | +----------------------+------------+ 17 | -------------------------------------------------------------------------------- /Logs/Stats/CCLatchRLP/CCLatch_RLP_RL_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------------+-------------+ 2 | | Name | Value | 3 | +----------------------+-------------+ 4 | | Circuit | CCLatch_RLP | 5 | | Time taken [s] | 4352 | 6 | | Placements | 250000 | 7 | | Placements per batch | 100 | 8 | | Env. size | 1495x1495 | 9 | | Solution placement | 108369 | 10 | | Total HPWL | 2619.0 | 11 | | Congestion | 19349.86 | 12 | | Reward | -2758.1 | 13 | | Total width | 1011.0 | 14 | | Total height | 735.0 | 15 | | Area | 743085.0 | 16 | +----------------------+-------------+ 17 | -------------------------------------------------------------------------------- /Logs/Stats/DiffAmpRLP/DiffAmp_RLP_RL_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------------+-------------+ 2 | | Name | Value | 3 | +----------------------+-------------+ 4 | | Circuit | DiffAmp_RLP | 5 | | Time taken [s] | 3099 | 6 | | Placements | 250000 | 7 | | Placements per batch | 100 | 8 | | Env. size | 1558x1558 | 9 | | Solution placement | 58486 | 10 | | Total HPWL | 1938.0 | 11 | | Congestion | 4122.89 | 12 | | Reward | -2002.21 | 13 | | Total width | 854.0 | 14 | | Total height | 737.0 | 15 | | Area | 629398.0 | 16 | +----------------------+-------------+ 17 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRLP/CMMFeedback_RL_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------------+-------------+ 2 | | Name | Value | 3 | +----------------------+-------------+ 4 | | Circuit | CMMFeedback | 5 | | Time taken [s] | 2388 | 6 | | Placements | 250000 | 7 | | Placements per batch | 100 | 8 | | Env. size | 1968x1968 | 9 | | Solution placement | 22701 | 10 | | Total HPWL | 4345.0 | 11 | | Congestion | 34319.64 | 12 | | Reward | -4530.26 | 13 | | Total width | 1685.0 | 14 | | Total height | 1114.0 | 15 | | Area | 1877090.0 | 16 | +----------------------+-------------+ 17 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRLP/MillerOpAmp_RL_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +----------------------+-------------+ 2 | | Name | Value | 3 | +----------------------+-------------+ 4 | | Circuit | MillerOpAmp | 5 | | Time taken [s] | 5984 | 6 | | Placements | 250000 | 7 | | Placements per batch | 100 | 8 | | Env. size | 4794x4794 | 9 | | Solution placement | 218931 | 10 | | Total HPWL | 13919.5 | 11 | | Congestion | 198670.92 | 12 | | Reward | -14365.23 | 13 | | Total width | 2387.5 | 14 | | Total height | 2281.0 | 15 | | Area | 5445887.5 | 16 | +----------------------+-------------+ 17 | -------------------------------------------------------------------------------- /NetRules/net_rules_InvAmp.json: -------------------------------------------------------------------------------- 1 | [ 2 | ["MinNetWireWidth", 3 | { 4 | "net" : "Von", 5 | "min_width" : 28 6 | } 7 | ], 8 | ["MinNetWireWidth", 9 | { 10 | "net" : "Vop", 11 | "min_width" : 28 12 | } 13 | ], 14 | ["MinNetWireWidth", 15 | { 16 | "net" : "VPWR", 17 | "min_width" : 28 18 | } 19 | ], 20 | ["MinNetWireWidth", 21 | { 22 | "net" : "VGND", 23 | "min_width" : 28 24 | } 25 | ], 26 | ["Ports", 27 | { 28 | "nets" : ["VGND", "VPWR", "Vip", "Vin", "Vocm", "Von", "Vop"] 29 | } 30 | ], 31 | ["PowerNets", 32 | { 33 | "nets" : ["VGND", "VPWR"] 34 | } 35 | ] 36 | ] -------------------------------------------------------------------------------- /NetRules/net_rules_MillerOpAmpCMMFB.json: -------------------------------------------------------------------------------- 1 | [ 2 | ["MinNetWireWidth", 3 | { 4 | "net" : "Von", 5 | "min_width" : 28 6 | } 7 | ], 8 | ["MinNetWireWidth", 9 | { 10 | "net" : "Vop", 11 | "min_width" : 28 12 | } 13 | ], 14 | ["MinNetWireWidth", 15 | { 16 | "net" : "VPWR", 17 | "min_width" : 28 18 | } 19 | ], 20 | ["MinNetWireWidth", 21 | { 22 | "net" : "VGND", 23 | "min_width" : 28 24 | } 25 | ], 26 | ["Ports", 27 | { 28 | "nets" : ["VGND", "VPWR", "Vip", "Vin", "Vocm", "Von", "Vop"] 29 | } 30 | ], 31 | ["PowerNets", 32 | { 33 | "nets" : ["VGND", "VPWR"] 34 | } 35 | ] 36 | ] -------------------------------------------------------------------------------- /rectangle_packing_solver/__version__.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Kotaro Terada 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | __version__ = "0.0.5" 16 | __version_info__ = tuple(int(i) if i.isdigit() else i for i in __version__.split(".")) 17 | -------------------------------------------------------------------------------- /Circuits/Primitives/CrossCoupledPair/CCP.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/CrossCoupledPair/CCP.sch 2 | **.subckt CCP Vd1 Vd2 Vs2 Vs1 Vb 3 | *.iopin Vd1 4 | *.iopin Vd2 5 | *.iopin Vs2 6 | *.iopin Vs1 7 | *.iopin Vb 8 | XM1 Vd1 Vd2 Vs1 Vb sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 9 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 10 | + sa=0 sb=0 sd=0 mult=1 m=1 11 | XM2 Vd2 Vd1 Vs2 Vb sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 12 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 13 | + sa=0 sb=0 sd=0 mult=1 m=1 14 | **.ends 15 | .end -------------------------------------------------------------------------------- /rectangle_packing_placement/rectangle_packing_solver/__version__.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Kotaro Terada 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | __version__ = "0.0.5" 16 | __version_info__ = tuple(int(i) if i.isdigit() else i for i in __version__.split(".")) 17 | -------------------------------------------------------------------------------- /Circuits/Primitives/DiffPair/DiffPair.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/DiffAmp/DiffPair.sch 2 | **.subckt DiffPair Vn Vp Vb Vs Vdn Vdp 3 | *.ipin Vn 4 | *.ipin Vp 5 | *.iopin Vb 6 | *.iopin Vs 7 | *.iopin Vdn 8 | *.iopin Vdp 9 | XM1 Vd1 Vg1 Vs Vb sky130_fd_pr__nfet_01v8 L=1 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 10 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 11 | + sa=0 sb=0 sd=0 mult=1 m=1 12 | XM2 Vd2 Vg2 Vs Vb sky130_fd_pr__nfet_01v8 L=1 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 13 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 14 | + sa=0 sb=0 sd=0 mult=1 m=1 15 | **.ends 16 | .end 17 | -------------------------------------------------------------------------------- /Circuits/Primitives/CrossCoupledPair/CCP_Vs2_Vs1_Vb_connected.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/CrossCoupledPair/CCP.sch 2 | **.subckt CCP Vd1 Vd2 Vs2 Vs1 Vb 3 | *.iopin Vd1 4 | *.iopin Vd2 5 | *.iopin Vs2 6 | *.iopin Vs1 7 | *.iopin Vb 8 | XM1 Vd1 Vd2 Vb Vb sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 9 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 10 | + sa=0 sb=0 sd=0 mult=1 m=1 11 | XM2 Vd2 Vd1 Vb Vb sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 12 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 13 | + sa=0 sb=0 sd=0 mult=1 m=1 14 | **.ends 15 | .end -------------------------------------------------------------------------------- /Circuits/Primitives/CrossCoupledPair/CCP_Vs2_Vs1_connected.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/CrossCoupledPair/CCP.sch 2 | **.subckt CCP Vd1 Vd2 Vs2 Vs1 Vb 3 | *.iopin Vd1 4 | *.iopin Vd2 5 | *.iopin Vs2 6 | *.iopin Vs1 7 | *.iopin Vb 8 | XM1 Vd1 Vd2 Vs Vb sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 9 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 10 | + sa=0 sb=0 sd=0 mult=1 m=1 11 | XM2 Vd2 Vd1 Vs Vb sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 12 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 13 | + sa=0 sb=0 sd=0 mult=1 m=1 14 | **.ends 15 | .end -------------------------------------------------------------------------------- /Circuits/Primitives/DiffPair/DiffPair_Vs_Vb_connected.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/DiffAmp/DiffPair.sch 2 | **.subckt DiffPair Vn Vp Vb Vs Vdn Vdp 3 | *.ipin Vn 4 | *.ipin Vp 5 | *.iopin Vb 6 | *.iopin Vs 7 | *.iopin Vdn 8 | *.iopin Vdp 9 | XM1 Vd1 Vg1 Vb Vb sky130_fd_pr__nfet_01v8 L=1 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 10 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 11 | + sa=0 sb=0 sd=0 mult=1 m=1 12 | XM2 Vd2 Vg2 Vb Vb sky130_fd_pr__nfet_01v8 L=1 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 13 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 14 | + sa=0 sb=0 sd=0 mult=1 m=1 15 | **.ends 16 | .end 17 | -------------------------------------------------------------------------------- /Circuits/Primitives/RString/RString.sch: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2 2 | } 3 | G {} 4 | K {} 5 | V {} 6 | S {} 7 | E {} 8 | N 20 -140 50 -140 { 9 | lab=VB} 10 | N 20 -140 20 -30 { 11 | lab=VB} 12 | N 20 -30 50 -30 { 13 | lab=VB} 14 | N 0 -90 20 -90 { 15 | lab=VB} 16 | N 70 -110 70 -60 { 17 | lab=Vmid} 18 | N 70 -80 100 -80 { 19 | lab=Vmid} 20 | N 70 -200 70 -170 { 21 | lab=Vh} 22 | N 70 0 70 30 { 23 | lab=Vl} 24 | C {devices/iopin.sym} 70 -200 3 0 {name=p1 lab=Vh} 25 | C {devices/iopin.sym} 0 -90 2 0 {name=p2 lab=VB} 26 | C {devices/iopin.sym} 100 -80 0 0 {name=p3 lab=Vmid} 27 | C {devices/iopin.sym} 70 30 1 0 {name=p4 lab=Vl} 28 | C {sky130_fd_pr/res_xhigh_po_0p35.sym} 70 -140 0 0 {name=R1 29 | L=0.35 30 | model=res_xhigh_po_0p35 31 | spiceprefix=X 32 | mult=1} 33 | C {sky130_fd_pr/res_xhigh_po_0p35.sym} 70 -30 0 0 {name=R2 34 | L=0.35 35 | model=res_xhigh_po_0p35 36 | spiceprefix=X 37 | mult=1} 38 | -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/CSAmp.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2} 2 | K {type=subcircuit 3 | format="@name @pinlist @symname" 4 | template="name=x1" 5 | } 6 | 7 | T {@symname} -40.5 -6 0 0 0.3 0.3 {} 8 | T {@name} 135 -42 0 0 0.2 0.2 {} 9 | L 4 -130 -30 130 -30 {} 10 | L 4 -130 30 130 30 {} 11 | L 4 -130 -30 -130 30 {} 12 | L 4 130 -30 130 30 {} 13 | B 5 147.5 -22.5 152.5 -17.5 {name=Vdd dir=inout} 14 | L 7 130 -20 150 -20 {} 15 | T {Vdd} 125 -24 0 1 0.2 0.2 {} 16 | B 5 -152.5 -22.5 -147.5 -17.5 {name=Vi dir=in} 17 | L 4 -150 -20 -130 -20 {} 18 | T {Vi} -125 -24 0 0 0.2 0.2 {} 19 | B 5 147.5 -2.5 152.5 2.5 {name=Vo dir=out} 20 | L 4 130 0 150 0 {} 21 | T {Vo} 125 -4 0 1 0.2 0.2 {} 22 | B 5 -152.5 -2.5 -147.5 2.5 {name=Vbn dir=in} 23 | L 4 -150 0 -130 0 {} 24 | T {Vbn} -125 -4 0 0 0.2 0.2 {} 25 | B 5 147.5 17.5 152.5 22.5 {name=Vss dir=inout} 26 | L 7 130 20 150 20 {} 27 | T {Vss} 125 16 0 1 0.2 0.2 {} 28 | -------------------------------------------------------------------------------- /Environment/__init__.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | -------------------------------------------------------------------------------- /Magic/__init__.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | -------------------------------------------------------------------------------- /Network/__init__.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | -------------------------------------------------------------------------------- /PDK/__init__.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | -------------------------------------------------------------------------------- /PPO/__init__.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | -------------------------------------------------------------------------------- /SchematicCapture/__init__.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | -------------------------------------------------------------------------------- /Magic/Devices/init_devs.tcl: -------------------------------------------------------------------------------- 1 | load XM5 -silent -quiet 2 | box 0 0 0 0 3 | ::sky130::sky130_fd_pr__nfet_01v8_draw {w 1.0 l 2 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 0 grc 0 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 full_metal 1 viasrc 0 viadrn 0 viagate 0 viagb 0 viagr 0 viagl 0 viagt 0} 4 | select cell XM5 5 | save XM5 6 | load XDP_XM1_XM2 -silent -quiet 7 | box 0 0 0 0 8 | ::sky130::sky130_fd_pr__nfet_01v8_draw {w 1.0 l 1 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 0 grc 0 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 full_metal 1 viasrc 0 viadrn 0 viagate 0 viagb 0 viagr 0 viagl 0 viagt 0} 9 | select cell XDP_XM1_XM2 10 | save XDP_XM1_XM2 11 | load XDL_XM3_XM4 -silent -quiet 12 | box 0 0 0 0 13 | ::sky130::sky130_fd_pr__pfet_01v8_draw {w 2.0 l 1 m 2 nf 1 diffcov 100 polycov 100 guard 1 glc 0 grc 0 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 full_metal 1 viasrc 0 viadrn 0 viagate 0 viagb 0 viagr 0 viagl 0 viagt 0} 14 | select cell XDL_XM3_XM4 15 | save XDL_XM3_XM4 16 | quit -noprompt 17 | -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/OpAmp.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2} 2 | K {type=subcircuit 3 | format="@name @pinlist @symname" 4 | template="name=x1" 5 | } 6 | 7 | T {@symname} -40.5 -6 0 0 0.3 0.3 {} 8 | T {@name} 135 -52 0 0 0.2 0.2 {} 9 | L 4 -130 -40 130 -40 {} 10 | L 4 -130 40 130 40 {} 11 | L 4 -130 -40 -130 40 {} 12 | L 4 130 -40 130 40 {} 13 | B 5 147.5 -32.5 152.5 -27.5 {name=VPWR dir=inout} 14 | L 7 130 -30 150 -30 {} 15 | T {VPWR} 125 -34 0 1 0.2 0.2 {} 16 | B 5 -152.5 -32.5 -147.5 -27.5 {name=Vocm dir=in} 17 | L 4 -150 -30 -130 -30 {} 18 | T {Vocm} -125 -34 0 0 0.2 0.2 {} 19 | B 5 147.5 -12.5 152.5 -7.5 {name=Vop dir=out} 20 | L 4 130 -10 150 -10 {} 21 | T {Vop} 125 -14 0 1 0.2 0.2 {} 22 | B 5 147.5 7.5 152.5 12.5 {name=Von dir=out} 23 | L 4 130 10 150 10 {} 24 | T {Von} 125 6 0 1 0.2 0.2 {} 25 | B 5 -152.5 -12.5 -147.5 -7.5 {name=Vp dir=in} 26 | L 4 -150 -10 -130 -10 {} 27 | T {Vp} -125 -14 0 0 0.2 0.2 {} 28 | B 5 -152.5 7.5 -147.5 12.5 {name=Vn dir=in} 29 | L 4 -150 10 -130 10 {} 30 | T {Vn} -125 6 0 0 0.2 0.2 {} 31 | B 5 147.5 27.5 152.5 32.5 {name=VGND dir=inout} 32 | L 7 130 30 150 30 {} 33 | T {VGND} 125 26 0 1 0.2 0.2 {} 34 | -------------------------------------------------------------------------------- /Circuits/Examples/InvAmp/InvAmp.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2} 2 | K {type=subcircuit 3 | format="@name @pinlist @symname" 4 | template="name=x1" 5 | } 6 | 7 | T {@symname} -45 -6 0 0 0.3 0.3 {} 8 | T {@name} 135 -52 0 0 0.2 0.2 {} 9 | L 4 -130 -40 130 -40 {} 10 | L 4 -130 40 130 40 {} 11 | L 4 -130 -40 -130 40 {} 12 | L 4 130 -40 130 40 {} 13 | B 5 147.5 -32.5 152.5 -27.5 {name=VPWR dir=inout} 14 | L 7 130 -30 150 -30 {} 15 | T {VPWR} 125 -34 0 1 0.2 0.2 {} 16 | B 5 -152.5 -32.5 -147.5 -27.5 {name=Vocm dir=in} 17 | L 4 -150 -30 -130 -30 {} 18 | T {Vocm} -125 -34 0 0 0.2 0.2 {} 19 | B 5 -152.5 -12.5 -147.5 -7.5 {name=Vin dir=in} 20 | L 4 -150 -10 -130 -10 {} 21 | T {Vin} -125 -14 0 0 0.2 0.2 {} 22 | B 5 147.5 -12.5 152.5 -7.5 {name=Vop dir=out} 23 | L 4 130 -10 150 -10 {} 24 | T {Vop} 125 -14 0 1 0.2 0.2 {} 25 | B 5 147.5 7.5 152.5 12.5 {name=Von dir=out} 26 | L 4 130 10 150 10 {} 27 | T {Von} 125 6 0 1 0.2 0.2 {} 28 | B 5 -152.5 7.5 -147.5 12.5 {name=Vip dir=in} 29 | L 4 -150 10 -130 10 {} 30 | T {Vip} -125 6 0 0 0.2 0.2 {} 31 | B 5 147.5 27.5 152.5 32.5 {name=VGND dir=inout} 32 | L 7 130 30 150 30 {} 33 | T {VGND} 125 26 0 1 0.2 0.2 {} 34 | -------------------------------------------------------------------------------- /Circuits/Examples/Latch/CCLatch.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2 2 | } 3 | G {} 4 | K {type=subcircuit 5 | format="@name @pinlist @symname" 6 | template="name=x1" 7 | } 8 | V {} 9 | S {} 10 | E {} 11 | L 4 -130 -40 130 -40 {} 12 | L 4 -130 40 130 40 {} 13 | L 4 -130 -40 -130 40 {} 14 | L 4 130 -40 130 40 {} 15 | L 4 130 -10 150 -10 {} 16 | L 4 130 10 150 10 {} 17 | L 4 -150 -20 -130 -20 {} 18 | L 4 -150 20 -130 20 {} 19 | L 4 -150 0 -130 0 {} 20 | L 7 0 -60 0 -40 {} 21 | L 7 0 40 0 60 {} 22 | B 5 -2.5 -62.5 2.5 -57.5 {name=Vdd dir=inout} 23 | B 5 147.5 -12.5 152.5 -7.5 {name=out dir=out} 24 | B 5 147.5 7.5 152.5 12.5 {name=outn dir=out} 25 | B 5 -152.5 -22.5 -147.5 -17.5 {name=in dir=in} 26 | B 5 -152.5 17.5 -147.5 22.5 {name=inn dir=in} 27 | B 5 -152.5 -2.5 -147.5 2.5 {name=clk dir=in} 28 | B 5 -2.5 57.5 2.5 62.5 {name=Vss dir=inout} 29 | T {@symname} -49.5 -6 0 0 0.3 0.3 {} 30 | T {@name} 135 -52 0 0 0.2 0.2 {} 31 | T {Vdd} 15 -34 0 1 0.2 0.2 {} 32 | T {out} 125 -14 0 1 0.2 0.2 {} 33 | T {outn} 125 6 0 1 0.2 0.2 {} 34 | T {in} -125 -24 0 0 0.2 0.2 {} 35 | T {inn} -125 16 0 0 0.2 0.2 {} 36 | T {clk} -125 -4 0 0 0.2 0.2 {} 37 | T {Vss} -6 35 2 1 0.2 0.2 {} 38 | -------------------------------------------------------------------------------- /rectangle_packing_solver/__init__.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Kotaro Terada 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | from .__version__ import __version__, __version_info__ 16 | 17 | # Classes 18 | from .floorplan import Floorplan 19 | from .problem import Problem 20 | from .sequence_pair import SequencePair 21 | from .solution import Solution 22 | 23 | # Solvers 24 | from .solver import Solver 25 | 26 | # Visualizers 27 | from .visualizer import Visualizer 28 | 29 | __all__ = [ 30 | "__version__", 31 | "__version_info__", 32 | "Floorplan", 33 | "Problem", 34 | "SequencePair", 35 | "Solution", 36 | "Solver", 37 | "Visualizer", 38 | ] 39 | -------------------------------------------------------------------------------- /Magic/Layouts/nfet.mag: -------------------------------------------------------------------------------- 1 | magic 2 | tech sky130A 3 | magscale 1 2 4 | timestamp 1687621782 5 | << error_p >> 6 | rect -29 83 29 89 7 | rect -29 49 -17 83 8 | rect -29 43 29 49 9 | << nmos >> 10 | rect -15 -73 15 11 11 | << ndiff >> 12 | rect -73 -1 -15 11 13 | rect -73 -61 -61 -1 14 | rect -27 -61 -15 -1 15 | rect -73 -73 -15 -61 16 | rect 15 -1 73 11 17 | rect 15 -61 27 -1 18 | rect 61 -61 73 -1 19 | rect 15 -73 73 -61 20 | << ndiffc >> 21 | rect -61 -61 -27 -1 22 | rect 27 -61 61 -1 23 | << poly >> 24 | rect -33 83 33 99 25 | rect -33 49 -17 83 26 | rect 17 49 33 83 27 | rect -33 33 33 49 28 | rect -15 11 15 33 29 | rect -15 -99 15 -73 30 | << polycont >> 31 | rect -17 49 17 83 32 | << locali >> 33 | rect -33 49 -17 83 34 | rect 17 49 33 83 35 | rect -61 -1 -27 15 36 | rect -61 -77 -27 -61 37 | rect 27 -1 61 15 38 | rect 27 -77 61 -61 39 | << viali >> 40 | rect -17 49 17 83 41 | rect -61 -61 -27 -1 42 | rect 27 -61 61 -1 43 | << metal1 >> 44 | rect -29 83 29 89 45 | rect -29 49 -17 83 46 | rect 17 49 29 83 47 | rect -29 43 29 49 48 | rect -67 -1 -21 11 49 | rect -67 -61 -61 -1 50 | rect -27 -61 -21 -1 51 | rect -67 -73 -21 -61 52 | rect 21 -1 67 11 53 | rect 21 -61 27 -1 54 | rect 61 -61 67 -1 55 | rect 21 -73 67 -61 56 | << end >> 57 | -------------------------------------------------------------------------------- /rectangle_packing_placement/rectangle_packing_solver/__init__.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Kotaro Terada 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | from .__version__ import __version__, __version_info__ 16 | 17 | # Classes 18 | from .floorplan import Floorplan 19 | from .problem import Problem 20 | from .sequence_pair import SequencePair 21 | from .solution import Solution 22 | 23 | # Solvers 24 | from .solver import Solver 25 | 26 | # Visualizers 27 | from .visualizer import Visualizer 28 | 29 | __all__ = [ 30 | "__version__", 31 | "__version_info__", 32 | "Floorplan", 33 | "Problem", 34 | "SequencePair", 35 | "Solution", 36 | "Solver", 37 | "Visualizer", 38 | ] 39 | -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/CMMFeedback.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2} 2 | K {type=subcircuit 3 | format="@name @pinlist @symname" 4 | template="name=x1" 5 | } 6 | 7 | T {@symname} -67.5 -6 0 0 0.3 0.3 {} 8 | T {@name} 135 -52 0 0 0.2 0.2 {} 9 | L 4 -130 -40 130 -40 {} 10 | L 4 -130 40 130 40 {} 11 | L 4 -130 -40 -130 40 {} 12 | L 4 130 -40 130 40 {} 13 | B 5 147.5 -32.5 152.5 -27.5 {name=Vdd dir=inout} 14 | L 7 130 -30 150 -30 {} 15 | T {Vdd} 125 -34 0 1 0.2 0.2 {} 16 | B 5 -152.5 -32.5 -147.5 -27.5 {name=Vcmref sig_type=std_logic dir=in} 17 | L 4 -150 -30 -130 -30 {} 18 | T {Vcmref} -125 -34 0 0 0.2 0.2 {} 19 | B 5 -152.5 -12.5 -147.5 -7.5 {name=Vp sig_type=std_logic dir=in} 20 | L 4 -150 -10 -130 -10 {} 21 | T {Vp} -125 -14 0 0 0.2 0.2 {} 22 | B 5 147.5 -12.5 152.5 -7.5 {name=Vout sig_type=std_logic dir=out} 23 | L 4 130 -10 150 -10 {} 24 | T {Vout} 125 -14 0 1 0.2 0.2 {} 25 | B 5 -152.5 7.5 -147.5 12.5 {name=Vn sig_type=std_logic dir=in} 26 | L 4 -150 10 -130 10 {} 27 | T {Vn} -125 6 0 0 0.2 0.2 {} 28 | B 5 -152.5 27.5 -147.5 32.5 {name=Vbdan sig_type=std_logic dir=in} 29 | L 4 -150 30 -130 30 {} 30 | T {Vbdan} -125 26 0 0 0.2 0.2 {} 31 | B 5 147.5 7.5 152.5 12.5 {name=Vss dir=inout} 32 | L 7 130 10 150 10 {} 33 | T {Vss} 125 6 0 1 0.2 0.2 {} 34 | -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/DiffAmp.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2} 2 | K {type=subcircuit 3 | format="@name @pinlist @symname" 4 | template="name=x1" 5 | } 6 | 7 | T {@symname} -49.5 -6 0 0 0.3 0.3 {} 8 | T {@name} 135 -52 0 0 0.2 0.2 {} 9 | L 4 -130 -40 130 -40 {} 10 | L 4 -130 40 130 40 {} 11 | L 4 -130 -40 -130 40 {} 12 | L 4 130 -40 130 40 {} 13 | B 5 147.5 -32.5 152.5 -27.5 {name=Vdd dir=inout} 14 | L 7 130 -30 150 -30 {} 15 | T {Vdd} 125 -34 0 1 0.2 0.2 {} 16 | B 5 -152.5 -32.5 -147.5 -27.5 {name=Vbp dir=in} 17 | L 4 -150 -30 -130 -30 {} 18 | T {Vbp} -125 -34 0 0 0.2 0.2 {} 19 | B 5 147.5 -12.5 152.5 -7.5 {name=Von dir=out} 20 | L 4 130 -10 150 -10 {} 21 | T {Von} 125 -14 0 1 0.2 0.2 {} 22 | B 5 147.5 7.5 152.5 12.5 {name=Vop dir=out} 23 | L 4 130 10 150 10 {} 24 | T {Vop} 125 6 0 1 0.2 0.2 {} 25 | B 5 -152.5 -12.5 -147.5 -7.5 {name=Vp dir=in} 26 | L 4 -150 -10 -130 -10 {} 27 | T {Vp} -125 -14 0 0 0.2 0.2 {} 28 | B 5 -152.5 7.5 -147.5 12.5 {name=Vn dir=in} 29 | L 4 -150 10 -130 10 {} 30 | T {Vn} -125 6 0 0 0.2 0.2 {} 31 | B 5 -152.5 27.5 -147.5 32.5 {name=Vbn dir=in} 32 | L 4 -150 30 -130 30 {} 33 | T {Vbn} -125 26 0 0 0.2 0.2 {} 34 | B 5 147.5 27.5 152.5 32.5 {name=Vss dir=inout} 35 | L 7 130 30 150 30 {} 36 | T {Vss} 125 26 0 1 0.2 0.2 {} 37 | -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/GmBias_tb.sch: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2 2 | } 3 | G {} 4 | K {} 5 | V {} 6 | S {} 7 | E {} 8 | N -450 -70 -450 0 { 9 | lab=GND} 10 | N -450 -190 -450 -130 { 11 | lab=VDD} 12 | N 0 -100 40 -100 { 13 | lab=VDD} 14 | N 0 -150 0 -100 { 15 | lab=VDD} 16 | N 0 -60 40 -60 { 17 | lab=GND} 18 | N 0 -60 -0 -20 { 19 | lab=GND} 20 | N -30 -80 40 -80 { 21 | lab=Vbias} 22 | C {/home/jakob/Documents/RALF/Circuits/Examples/MillerOpAmpCMMFB/GmBias.sym} 190 -80 0 1 {name=x1} 23 | C {devices/vsource.sym} -450 -100 0 0 {name=V3 value=1.8} 24 | C {devices/gnd.sym} -450 0 0 0 {name=l3 lab=GND} 25 | C {devices/vdd.sym} -450 -190 0 0 {name=l4 lab=VDD} 26 | C {devices/vdd.sym} 0 -150 0 0 {name=l1 lab=VDD} 27 | C {devices/gnd.sym} 0 -20 0 0 {name=l2 lab=GND} 28 | C {devices/lab_wire.sym} -30 -80 0 0 {name=p1 sig_type=std_logic lab=Vbias} 29 | C {devices/simulator_commands.sym} -460 -400 0 0 {name=COMMANDS 30 | simulator=ngspice 31 | only_toplevel=false 32 | value=" 33 | * ngspice commands 34 | .option savecurrents 35 | .save all 36 | .control 37 | op 38 | .endc 39 | "} 40 | C {devices/code_shown.sym} -270 -420 0 0 {name=ngspice 41 | only_toplevel=false 42 | format="tcleval( @value )" 43 | value= 44 | ".lib $::SKYWATER_MODELS/sky130.lib.spice tt 45 | "} 46 | -------------------------------------------------------------------------------- /Magic/Layouts/pfet.mag: -------------------------------------------------------------------------------- 1 | magic 2 | tech sky130A 3 | magscale 1 2 4 | timestamp 1687621785 5 | << error_p >> 6 | rect -29 87 29 93 7 | rect -29 53 -17 87 8 | rect -29 47 29 53 9 | << nwell >> 10 | rect -109 -140 109 106 11 | << pmos >> 12 | rect -15 -78 15 6 13 | << pdiff >> 14 | rect -73 -6 -15 6 15 | rect -73 -66 -61 -6 16 | rect -27 -66 -15 -6 17 | rect -73 -78 -15 -66 18 | rect 15 -6 73 6 19 | rect 15 -66 27 -6 20 | rect 61 -66 73 -6 21 | rect 15 -78 73 -66 22 | << pdiffc >> 23 | rect -61 -66 -27 -6 24 | rect 27 -66 61 -6 25 | << poly >> 26 | rect -33 87 33 103 27 | rect -33 53 -17 87 28 | rect 17 53 33 87 29 | rect -33 37 33 53 30 | rect -15 6 15 37 31 | rect -15 -104 15 -78 32 | << polycont >> 33 | rect -17 53 17 87 34 | << locali >> 35 | rect -33 53 -17 87 36 | rect 17 53 33 87 37 | rect -61 -6 -27 10 38 | rect -61 -82 -27 -66 39 | rect 27 -6 61 10 40 | rect 27 -82 61 -66 41 | << viali >> 42 | rect -17 53 17 87 43 | rect -61 -66 -27 -6 44 | rect 27 -66 61 -6 45 | << metal1 >> 46 | rect -29 87 29 93 47 | rect -29 53 -17 87 48 | rect 17 53 29 87 49 | rect -29 47 29 53 50 | rect -67 -6 -21 6 51 | rect -67 -66 -61 -6 52 | rect -27 -66 -21 -6 53 | rect -67 -78 -21 -66 54 | rect 21 -6 67 6 55 | rect 21 -66 27 -6 56 | rect 61 -66 67 -6 57 | rect 21 -78 67 -66 58 | << end >> 59 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRLP/InvAmp_RLP_routing_stats.txt: -------------------------------------------------------------------------------- 1 | +----------+---------+-------+ 2 | | Net name | Length | #Vias | 3 | +----------+---------+-------+ 4 | | VGND | 12642.0 | 43 | 5 | | vbias | 6763.0 | 19 | 6 | | VPWR | 7525.0 | 31 | 7 | | Von | 5319.0 | 16 | 8 | | Vop | 6464.5 | 15 | 9 | | vcmfb | 2494.0 | 4 | 10 | | von1 | 2580.0 | 10 | 11 | | vop1 | 1822.0 | 10 | 12 | | v1 | 1643.0 | 12 | 13 | | vn | 1510.0 | 5 | 14 | | vp | 837.0 | 7 | 15 | | vdts | 64.0 | 4 | 16 | | vcmi | 726.0 | 5 | 17 | | net5 | 84.0 | 2 | 18 | | net3 | 84.0 | 2 | 19 | | net1 | 208.0 | 2 | 20 | | vmid | 208.0 | 2 | 21 | | v2 | 82.0 | 2 | 22 | | net8 | 82.0 | 2 | 23 | | vmid | 208.0 | 2 | 24 | | Vip | 0 | 1 | 25 | | v1 | 84.0 | 2 | 26 | | Vin | 0 | 1 | 27 | | net6 | 82.0 | 2 | 28 | | net7 | 84.0 | 2 | 29 | | net4 | 82.0 | 2 | 30 | | net2 | 82 | 2 | 31 | | net1 | 84.0 | 2 | 32 | | Vocm | 0 | 1 | 33 | +----------+---------+-------+ 34 | | Total | 51843.5 | 210 | 35 | +----------+---------+-------+ 36 | -------------------------------------------------------------------------------- /Magic/Devices/XM5.mag: -------------------------------------------------------------------------------- 1 | magic 2 | tech sky130A 3 | magscale 1 2 4 | timestamp 1703146904 5 | << checkpaint >> 6 | rect -1656 -1539 1656 1539 7 | << pwell >> 8 | rect -396 -279 396 279 9 | << nmos >> 10 | rect -200 -131 200 69 11 | << ndiff >> 12 | rect -258 57 -200 69 13 | rect -258 -119 -246 57 14 | rect -212 -119 -200 57 15 | rect -258 -131 -200 -119 16 | rect 200 57 258 69 17 | rect 200 -119 212 57 18 | rect 246 -119 258 57 19 | rect 200 -131 258 -119 20 | << ndiffc >> 21 | rect -246 -119 -212 57 22 | rect 212 -119 246 57 23 | << psubdiff >> 24 | rect -360 209 360 243 25 | rect -360 -209 -326 209 26 | rect 326 -209 360 209 27 | rect -360 -243 -264 -209 28 | rect 264 -243 360 -209 29 | << psubdiffcont >> 30 | rect -264 -243 264 -209 31 | << poly >> 32 | rect -200 141 200 157 33 | rect -200 107 -184 141 34 | rect 184 107 200 141 35 | rect -200 69 200 107 36 | rect -200 -157 200 -131 37 | << polycont >> 38 | rect -184 107 184 141 39 | << locali >> 40 | rect -360 209 360 243 41 | rect -360 -209 -326 209 42 | rect -200 107 -184 141 43 | rect 184 107 200 141 44 | rect -246 57 -212 73 45 | rect -246 -135 -212 -119 46 | rect 212 57 246 73 47 | rect 212 -135 246 -119 48 | rect 326 -209 360 209 49 | rect -360 -243 -264 -209 50 | rect 264 -243 360 -209 51 | << properties >> 52 | string FIXED_BBOX -343 -226 343 226 53 | << end >> 54 | -------------------------------------------------------------------------------- /Network/D2RL_Policy.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | import torch.nn as nn 21 | 22 | class D2RL_Policy(nn.Module): 23 | def __init__(self, actor, critic) -> None: 24 | super().__init__() 25 | self.actor = actor 26 | self.critic = critic 27 | 28 | def forward(self, data): 29 | action_pred = self.actor(data) 30 | value_pred = self.critic(data) 31 | 32 | return action_pred, value_pred 33 | -------------------------------------------------------------------------------- /Network/GAT_Policy.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | import torch.nn as nn 21 | 22 | class GAT_Policy(nn.Module): 23 | def __init__(self, actor, critic) -> None: 24 | super().__init__() 25 | self.actor = actor 26 | self.critic = critic 27 | 28 | def forward(self, data): 29 | action_pred = self.actor(data) 30 | value_pred = self.critic(data) 31 | 32 | return action_pred, value_pred 33 | -------------------------------------------------------------------------------- /lef_def_files/MillerOpAmp.def: -------------------------------------------------------------------------------- 1 | VERSION 5.7 ; 2 | NAMESCASESENSITIVE ON ; 3 | DIVIDERCHAR "/" ; 4 | BUSBITCHARS "()" ; 5 | DESIGN MillerOpAmp ; 6 | TECHNOLOGY sky130A ; 7 | UNITS DISTANCE MICRONS 1000 ; 8 | DIEAREA ( -5 -1265 ) ( 23000 15170 ) ; 9 | 10 | 11 | 12 | PINS 8 ; 13 | - Vp + NET Vp 14 | + PORT 15 | + LAYER met4 ( -305 -420 ) ( 305 420 ) + PLACED ( 11525 14740 ) N ; 16 | - Vn + NET Vn 17 | + PORT 18 | + LAYER met4 ( -305 -420 ) ( 305 420 ) + PLACED ( 12755 14740 ) N ; 19 | - Vbias1 + NET Vbias1 20 | + PORT 21 | + LAYER met4 ( -420 -305 ) ( 420 305 ) + PLACED ( 22550 11395 ) N ; 22 | - Vbias2 + NET Vbias2 23 | + PORT 24 | + LAYER met4 ( -420 -305 ) ( 420 305 ) + PLACED ( 22580 9325 ) N ; 25 | - VGND + NET VGND 26 | + PORT 27 | + LAYER met4 ( -305 -420 ) ( 305 420 ) + PLACED ( 16035 14720 ) N ; 28 | - VPWR + NET VPWR 29 | + PORT 30 | + LAYER met4 ( -305 -420 ) ( 305 420 ) + PLACED ( 6345 14750 ) N ; 31 | - Von + NET Von 32 | + PORT 33 | + LAYER met4 ( -420 -305 ) ( 420 305 ) + PLACED ( 22420 5955 ) N ; 34 | - Vop + NET Vop 35 | + PORT 36 | + LAYER met4 ( -420 -305 ) ( 420 305 ) + PLACED ( 22370 475 ) N ; 37 | END PINS 38 | 39 | END DESIGN 40 | 41 | -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/MillerOpAmp.sym: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2} 2 | K {type=subcircuit 3 | format="@name @pinlist @symname" 4 | template="name=x1" 5 | } 6 | 7 | T {@symname} -67.5 -6 0 0 0.3 0.3 {} 8 | T {@name} 135 -62 0 0 0.2 0.2 {} 9 | L 4 -130 -50 130 -50 {} 10 | L 4 -130 50 130 50 {} 11 | L 4 -130 -50 -130 50 {} 12 | L 4 130 -50 130 50 {} 13 | B 5 147.5 -42.5 152.5 -37.5 {name=VPWR dir=inout} 14 | L 7 130 -40 150 -40 {} 15 | T {VPWR} 125 -44 0 1 0.2 0.2 {} 16 | B 5 147.5 -22.5 152.5 -17.5 {name=Von dir=out} 17 | L 4 130 -20 150 -20 {} 18 | T {Von} 125 -24 0 1 0.2 0.2 {} 19 | B 5 -152.5 -42.5 -147.5 -37.5 {name=Vbdap dir=in} 20 | L 4 -150 -40 -130 -40 {} 21 | T {Vbdap} -125 -44 0 0 0.2 0.2 {} 22 | B 5 -152.5 -22.5 -147.5 -17.5 {name=Vp dir=in} 23 | L 4 -150 -20 -130 -20 {} 24 | T {Vp} -125 -24 0 0 0.2 0.2 {} 25 | B 5 -152.5 -2.5 -147.5 2.5 {name=Vn dir=in} 26 | L 4 -150 0 -130 0 {} 27 | T {Vn} -125 -4 0 0 0.2 0.2 {} 28 | B 5 -152.5 17.5 -147.5 22.5 {name=Vbdan dir=in} 29 | L 4 -150 20 -130 20 {} 30 | T {Vbdan} -125 16 0 0 0.2 0.2 {} 31 | B 5 -152.5 37.5 -147.5 42.5 {name=Vbcsn dir=in} 32 | L 4 -150 40 -130 40 {} 33 | T {Vbcsn} -125 36 0 0 0.2 0.2 {} 34 | B 5 147.5 -2.5 152.5 2.5 {name=Vop dir=out} 35 | L 4 130 0 150 0 {} 36 | T {Vop} 125 -4 0 1 0.2 0.2 {} 37 | B 5 147.5 17.5 152.5 22.5 {name=VGND dir=inout} 38 | L 7 130 20 150 20 {} 39 | T {VGND} 125 16 0 1 0.2 0.2 {} 40 | -------------------------------------------------------------------------------- /Magic/Layouts/TwoStageAmp_v0.mag: -------------------------------------------------------------------------------- 1 | magic 2 | tech sky130A 3 | magscale 1 2 4 | timestamp 1690294290 5 | << checkpaint >> 6 | rect 1479 3717 4837 4477 7 | rect -1679 2718 4837 3717 8 | rect -1679 1679 5239 2718 9 | rect -3717 -1198 5239 1679 10 | rect -3717 -1679 4837 -1198 11 | rect -1679 -2957 4837 -1679 12 | rect -1679 -3717 1679 -2957 13 | use XM1 XM1_0 ../Devices/DiffPair 14 | timestamp 1690289632 15 | transform 0 -1 1191 1 0 -348 16 | box -296 -510 296 510 17 | use XM2 XM2_0 ../Devices/DiffPair 18 | timestamp 1690289632 19 | transform 0 -1 1191 1 0 244 20 | box -296 -510 296 510 21 | use XM3 XM3_0 ../Devices/DiffAmp 22 | timestamp 1690289632 23 | transform 0 -1 1191 1 0 1352 24 | box -812 -410 812 410 25 | use XM4 XM4_0 ../Devices/Curr_Biasing 26 | timestamp 1690289633 27 | transform -1 0 1897 0 -1 1352 28 | box -296 -310 296 310 29 | use XM5 XM5_0 ../Devices/CMS_Amp 30 | timestamp 1690289631 31 | transform 0 1 3158 -1 0 760 32 | box -2457 -419 2457 419 33 | use XM6 XM6_0 ../Devices/PMOS_Load 34 | timestamp 1690289633 35 | transform 0 1 2220 -1 0 244 36 | box -296 -519 296 519 37 | use XM7 XM7_0 ../Devices/PMOS_Load 38 | timestamp 1690289633 39 | transform 0 1 2220 -1 0 -348 40 | box -296 -519 296 519 41 | use XR3 XR3_0 ../Devices/Curr_Biasing 42 | timestamp 1690289633 43 | transform -1 0 2394 0 -1 1352 44 | box -201 -633 201 633 45 | use XR4 XR4_0 ../Devices/CMS_Amp 46 | timestamp 1690289631 47 | transform 1 0 3778 0 1 760 48 | box -201 -698 201 698 49 | << end >> 50 | -------------------------------------------------------------------------------- /rectangle_packing_placement/rectangle_packing_solver/floorplan.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Kotaro Terada 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | from typing import Dict, List, Tuple, Union 16 | 17 | 18 | class Floorplan: 19 | """ 20 | A class to represent a rectangle packing floorplan. 21 | """ 22 | 23 | def __init__(self, positions: List[Dict], bounding_box: Tuple, area: Union[int, float] = -1.0) -> None: 24 | self.positions = positions 25 | self.bounding_box = bounding_box 26 | if 0 < area: 27 | self.area = area 28 | else: 29 | self.area = bounding_box[0] * bounding_box[1] 30 | 31 | def __repr__(self) -> str: 32 | s = "Floorplan({" 33 | s += "'positions': " + str(self.positions) + ", " 34 | s += "'bounding_box': " + str(self.bounding_box) + ", " 35 | s += "'area': " + str(self.area) + "})" 36 | 37 | return s 38 | -------------------------------------------------------------------------------- /Circuits/Examples/CCLatch.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/RALF/Circuits/Examples/Latch/CCLatch.sch 2 | **.subckt CCLatch Vdd Vss in inn clk outn out 3 | *.iopin Vdd 4 | *.iopin Vss 5 | *.ipin in 6 | *.ipin inn 7 | *.ipin clk 8 | *.opin outn 9 | *.opin out 10 | XM1 outn in vmid Vss sky130_fd_pr__nfet_01v8 L=1 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 11 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 12 | + sa=0 sb=0 sd=0 mult=1 m=1 13 | XM2 out inn vmid Vss sky130_fd_pr__nfet_01v8 L=1 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 14 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 15 | + sa=0 sb=0 sd=0 mult=1 m=1 16 | XM3 outn out Vdd Vdd sky130_fd_pr__pfet_01v8 L=1 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 17 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 18 | + sa=0 sb=0 sd=0 mult=1 m=1 19 | XM4 out outn Vdd Vdd sky130_fd_pr__pfet_01v8 L=1 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 20 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 21 | + sa=0 sb=0 sd=0 mult=1 m=1 22 | XM5 vmid clk Vss Vss sky130_fd_pr__nfet_01v8 L=1 W=6 nf=2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 23 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 24 | + sa=0 sb=0 sd=0 mult=1 m=1 25 | **.ends 26 | .end -------------------------------------------------------------------------------- /rectangle_packing_placement/rectangle_packing_solver/solution.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Kotaro Terada 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | from .floorplan import Floorplan 16 | from .sequence_pair import SequencePair 17 | 18 | 19 | class Solution: 20 | """ 21 | A class to represent a rectangle packing solution. 22 | """ 23 | 24 | def __init__(self, sequence_pair: SequencePair, floorplan: Floorplan) -> None: 25 | 26 | if not isinstance(sequence_pair, SequencePair): 27 | raise TypeError("Invalid argument: 'sequence_pair' must be an instance of SequencePair.") 28 | 29 | if not isinstance(floorplan, Floorplan): 30 | raise TypeError("Invalid argument: 'floorplan' must be an instance of Floorplan.") 31 | 32 | self.sequence_pair = sequence_pair 33 | self.floorplan = floorplan 34 | 35 | def __repr__(self) -> str: 36 | s = "Solution({" 37 | s += "'sequence_pair': " + str(self.sequence_pair) + ", " 38 | s += "'floorplan': " + str(self.floorplan) + "})" 39 | 40 | return s 41 | -------------------------------------------------------------------------------- /Circuits/Examples/DiffAmp.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/RALF/Circuits/Examples/OpAmp/DiffAmp.sch 2 | **.subckt DiffAmp Vdd Vss Vp Vn Vbn Vbp Vop Von 3 | *.iopin Vdd 4 | *.iopin Vss 5 | *.ipin Vp 6 | *.ipin Vn 7 | *.ipin Vbn 8 | *.ipin Vbp 9 | *.opin Vop 10 | *.opin Von 11 | XM1 Vop Vp vmid Vss sky130_fd_pr__nfet_01v8 L=1 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 12 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 13 | + sa=0 sb=0 sd=0 mult=1 m=1 14 | XM2 Von Vn vmid Vss sky130_fd_pr__nfet_01v8 L=1 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 15 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 16 | + sa=0 sb=0 sd=0 mult=1 m=1 17 | XM3 Vop Vbp Vdd Vdd sky130_fd_pr__pfet_01v8 L=1 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 18 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 19 | + sa=0 sb=0 sd=0 mult=1 m=1 20 | XM4 Von Vbp Vdd Vdd sky130_fd_pr__pfet_01v8 L=1 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 21 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 22 | + sa=0 sb=0 sd=0 mult=1 m=1 23 | XM5 vmid Vbn Vss Vss sky130_fd_pr__nfet_01v8 L=2 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 24 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 25 | + sa=0 sb=0 sd=0 mult=1 m=1 26 | **.ends 27 | .end 28 | -------------------------------------------------------------------------------- /Circuits/Examples/Latch/simulation/CCLatch.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/RALF/Circuits/Examples/Latch/CCLatch.sch 2 | **.subckt CCLatch Vdd Vss in inn clk outn out 3 | *.iopin Vdd 4 | *.iopin Vss 5 | *.ipin in 6 | *.ipin inn 7 | *.ipin clk 8 | *.opin outn 9 | *.opin out 10 | XM1 outn in vmid Vss sky130_fd_pr__nfet_01v8 L=1 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 11 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 12 | + sa=0 sb=0 sd=0 mult=1 m=1 13 | XM2 out inn vmid Vss sky130_fd_pr__nfet_01v8 L=1 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 14 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 15 | + sa=0 sb=0 sd=0 mult=1 m=1 16 | XM3 outn out Vdd Vdd sky130_fd_pr__pfet_01v8 L=1 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 17 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 18 | + sa=0 sb=0 sd=0 mult=1 m=1 19 | XM4 out outn Vdd Vdd sky130_fd_pr__pfet_01v8 L=1 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 20 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 21 | + sa=0 sb=0 sd=0 mult=1 m=1 22 | XM5 vmid clk Vss Vss sky130_fd_pr__nfet_01v8 L=1 W=6 nf=2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 23 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 24 | + sa=0 sb=0 sd=0 mult=1 m=1 25 | **.ends 26 | .end 27 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRLP/InvAmp_RLP_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +------------------+-----------+------+ 2 | | Parameter | Value | Unit | 3 | +------------------+-----------+------+ 4 | | HPWL(vmid_x2_x1) | 2.08 | um | 5 | | HPWL(vbias_) | 51.44 | um | 6 | | HPWL(VGND) | 57.81 | um | 7 | | HPWL(vdts_x1) | 5.54 | um | 8 | | HPWL(vcmfb_) | 22.51 | um | 9 | | HPWL(Vocm) | 0.0 | um | 10 | | HPWL(vcmi_x1) | 7.08 | um | 11 | | HPWL(VPWR) | 41.18 | um | 12 | | HPWL(Von) | 42.52 | um | 13 | | HPWL(net1_x1) | 2.08 | um | 14 | | HPWL(net2_x1) | 0.82 | um | 15 | | HPWL(net3_x1) | 0.84 | um | 16 | | HPWL(net4_x1) | 0.82 | um | 17 | | HPWL(net8_x1) | 0.82 | um | 18 | | HPWL(net7_x1) | 0.84 | um | 19 | | HPWL(net6_x1) | 0.82 | um | 20 | | HPWL(net5_x1) | 0.84 | um | 21 | | HPWL(Vop) | 37.49 | um | 22 | | HPWL(v1_x1) | 9.01 | um | 23 | | HPWL(von1_x1) | 22.22 | um | 24 | | HPWL(vop1_x1) | 16.89 | um | 25 | | HPWL(vmid_x1_x1) | 2.08 | um | 26 | | HPWL(vp) | 6.48 | um | 27 | | HPWL(vn) | 13.78 | um | 28 | | HPWL(Vin) | 0.0 | um | 29 | | HPWL(v1) | 0.83 | um | 30 | | HPWL(v2) | 0.83 | um | 31 | | HPWL(Vip) | 0.0 | um | 32 | | Total HPWL | 347.65 | um | 33 | | Congestion | 1463852.3 | - | 34 | | Width | 36.28 | um | 35 | | Height | 34.8 | um | 36 | | Area | 1262.54 | um2 | 37 | | #Cells | 24 | - | 38 | +------------------+-----------+------+ 39 | -------------------------------------------------------------------------------- /Magic/Devices/XDP_XM1_XM2.mag: -------------------------------------------------------------------------------- 1 | magic 2 | tech sky130A 3 | magscale 1 2 4 | timestamp 1703146904 5 | << checkpaint >> 6 | rect -1685 -1539 1685 1539 7 | << pwell >> 8 | rect -425 -279 425 279 9 | << nmos >> 10 | rect -229 -131 -29 69 11 | rect 29 -131 229 69 12 | << ndiff >> 13 | rect -287 57 -229 69 14 | rect -287 -119 -275 57 15 | rect -241 -119 -229 57 16 | rect -287 -131 -229 -119 17 | rect -29 57 29 69 18 | rect -29 -119 -17 57 19 | rect 17 -119 29 57 20 | rect -29 -131 29 -119 21 | rect 229 57 287 69 22 | rect 229 -119 241 57 23 | rect 275 -119 287 57 24 | rect 229 -131 287 -119 25 | << ndiffc >> 26 | rect -275 -119 -241 57 27 | rect -17 -119 17 57 28 | rect 241 -119 275 57 29 | << psubdiff >> 30 | rect -389 209 389 243 31 | rect -389 -209 -355 209 32 | rect 355 -209 389 209 33 | rect -389 -243 -293 -209 34 | rect 293 -243 389 -209 35 | << psubdiffcont >> 36 | rect -293 -243 293 -209 37 | << poly >> 38 | rect -229 141 -29 157 39 | rect -229 107 -213 141 40 | rect -45 107 -29 141 41 | rect -229 69 -29 107 42 | rect 29 141 229 157 43 | rect 29 107 45 141 44 | rect 213 107 229 141 45 | rect 29 69 229 107 46 | rect -229 -157 -29 -131 47 | rect 29 -157 229 -131 48 | << polycont >> 49 | rect -213 107 -45 141 50 | rect 45 107 213 141 51 | << locali >> 52 | rect -389 209 389 243 53 | rect -389 -209 -355 209 54 | rect -229 107 -213 141 55 | rect -45 107 -29 141 56 | rect 29 107 45 141 57 | rect 213 107 229 141 58 | rect -275 57 -241 73 59 | rect -275 -135 -241 -119 60 | rect -17 57 17 73 61 | rect -17 -135 17 -119 62 | rect 241 57 275 73 63 | rect 241 -135 275 -119 64 | rect 355 -209 389 209 65 | rect -389 -243 -293 -209 66 | rect 293 -243 389 -209 67 | << properties >> 68 | string FIXED_BBOX -372 -226 372 226 69 | << end >> 70 | -------------------------------------------------------------------------------- /Logs/Stats/InvAmpRPP/InvAmp_RPP_placement_stats.txt: -------------------------------------------------------------------------------- 1 | +------------------+------------+------+ 2 | | Parameter | Value | Unit | 3 | +------------------+------------+------+ 4 | | HPWL(vmid_x2_x1) | 3.41 | um | 5 | | HPWL(vbias_) | 43.77 | um | 6 | | HPWL(VGND) | 58.88 | um | 7 | | HPWL(vdts_x1) | 4.58 | um | 8 | | HPWL(vcmfb_) | 11.03 | um | 9 | | HPWL(Vocm) | 0.0 | um | 10 | | HPWL(vcmi_x1) | 4.7 | um | 11 | | HPWL(VPWR) | 35.74 | um | 12 | | HPWL(Von) | 31.87 | um | 13 | | HPWL(net1_x1) | 1.86 | um | 14 | | HPWL(net2_x1) | 0.82 | um | 15 | | HPWL(net3_x1) | 0.84 | um | 16 | | HPWL(net4_x1) | 0.82 | um | 17 | | HPWL(net8_x1) | 0.82 | um | 18 | | HPWL(net7_x1) | 0.84 | um | 19 | | HPWL(net6_x1) | 0.82 | um | 20 | | HPWL(net5_x1) | 0.84 | um | 21 | | HPWL(Vop) | 54.24 | um | 22 | | HPWL(v1_x1) | 10.34 | um | 23 | | HPWL(von1_x1) | 16.4 | um | 24 | | HPWL(vop1_x1) | 15.06 | um | 25 | | HPWL(vmid_x1_x1) | 3.41 | um | 26 | | HPWL(vp) | 18.26 | um | 27 | | HPWL(vn) | 23.86 | um | 28 | | HPWL(Vin) | 0.0 | um | 29 | | HPWL(v1) | 0.83 | um | 30 | | HPWL(v2) | 0.83 | um | 31 | | HPWL(Vip) | 0.0 | um | 32 | | Total HPWL | 344.89 | um | 33 | | Congestion | 1434463.37 | - | 34 | | Width | 33.91 | um | 35 | | Height | 33.18 | um | 36 | | Area | 1125.13 | um2 | 37 | | #Cells | 24 | - | 38 | +------------------+------------+------+ 39 | -------------------------------------------------------------------------------- /main_init_cells.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # Script to initialize the cells of a circuit in Magic. 4 | # 5 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 6 | # Johannes Kepler University, Institute for Integrated Circuits 7 | # 8 | # Licensed under the Apache License, Version 2.0 (the "License"); 9 | # you may not use this file except in compliance with the License. 10 | # You may obtain a copy of the License at 11 | # 12 | # http://www.apache.org/licenses/LICENSE-2.0 13 | # 14 | # Unless required by applicable law or agreed to in writing, software 15 | # distributed under the License is distributed on an "AS IS" BASIS, 16 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 17 | # See the License for the specific language governing permissions and 18 | # limitations under the License. 19 | # SPDX-License-Identifier: Apache-2.0 20 | # ======================================================================== 21 | 22 | from __future__ import annotations 23 | from typing import TYPE_CHECKING 24 | if TYPE_CHECKING: 25 | from Magic.MagicDie import MagicDie 26 | 27 | 28 | from Magic.utils import instantiate_circuit 29 | import pickle 30 | 31 | ######################################################################### 32 | 33 | CIRCUIT_NAME = "DiffAmp" #Name of the circuit 34 | 35 | ######################################################################### 36 | 37 | #load the placed circuit 38 | file = open(f"PlacementCircuits/{CIRCUIT_NAME}_placement.pkl", 'rb') 39 | die : MagicDie 40 | die = pickle.load(file) 41 | file.close() 42 | 43 | #get the placed circuit 44 | circuit = die.circuit 45 | 46 | #instantiate the circuit cells in magic 47 | instantiate_circuit(circuit,"Magic/Devices") 48 | 49 | -------------------------------------------------------------------------------- /rectangle_packing_solver/solution.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Kotaro Terada 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | from .floorplan import Floorplan 16 | from .sequence_pair import SequencePair 17 | from .problem import Problem 18 | 19 | class Solution: 20 | """ 21 | A class to represent a rectangle packing solution. 22 | """ 23 | 24 | def __init__(self, sequence_pair: SequencePair, floorplan: Floorplan, problem : Problem) -> None: 25 | 26 | if not isinstance(sequence_pair, SequencePair): 27 | raise TypeError("Invalid argument: 'sequence_pair' must be an instance of SequencePair.") 28 | 29 | if not isinstance(floorplan, Floorplan): 30 | raise TypeError("Invalid argument: 'floorplan' must be an instance of Floorplan.") 31 | 32 | if not isinstance(problem, Problem): 33 | raise TypeError("Invalid argument: 'problem' must be an instance of Problem.") 34 | 35 | self.sequence_pair = sequence_pair 36 | self.floorplan = floorplan 37 | self.problem = problem 38 | 39 | def __repr__(self) -> str: 40 | s = "Solution({" 41 | s += "'sequence_pair': " + str(self.sequence_pair) + ", " 42 | s += "'floorplan': " + str(self.floorplan) + "})" 43 | 44 | return s 45 | -------------------------------------------------------------------------------- /Circuits/Primitives/CrossCoupledPair/CCP.sch: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2 2 | } 3 | G {} 4 | K {} 5 | V {} 6 | S {} 7 | E {} 8 | N 110 -30 140 -30 { 9 | lab=Vd2} 10 | N 140 -60 140 -30 { 11 | lab=Vd2} 12 | N 170 -30 190 -30 { 13 | lab=Vd1} 14 | N 170 -60 170 -30 { 15 | lab=Vd1} 16 | N 140 -60 170 -80 { 17 | lab=Vd2} 18 | N 170 -80 230 -80 { 19 | lab=Vd2} 20 | N 140 -80 170 -60 { 21 | lab=Vd1} 22 | N 70 -80 140 -80 { 23 | lab=Vd1} 24 | N 230 -70 230 -60 { 25 | lab=Vd2} 26 | N 70 -70 70 -60 { 27 | lab=Vd1} 28 | N 70 -80 70 -70 { 29 | lab=Vd1} 30 | N 70 -110 70 -80 { 31 | lab=Vd1} 32 | N 230 -80 230 -70 { 33 | lab=Vd2} 34 | N 230 -110 230 -80 { 35 | lab=Vd2} 36 | N 70 0 70 20 { 37 | lab=Vs1} 38 | N 70 20 70 30 { 39 | lab=Vs1} 40 | N 230 0 230 30 { 41 | lab=Vs2} 42 | N 0 -30 70 -30 { 43 | lab=Vb} 44 | N 230 -30 300 -30 { 45 | lab=xxx} 46 | C {sky130_fd_pr/nfet_01v8.sym} 90 -30 0 1 {name=M1 47 | L=0.15 48 | W=2 49 | nf=1 50 | mult=1 51 | ad="'int((nf+1)/2) * W/nf * 0.29'" 52 | pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" 53 | as="'int((nf+2)/2) * W/nf * 0.29'" 54 | ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" 55 | nrd="'0.29 / W'" nrs="'0.29 / W'" 56 | sa=0 sb=0 sd=0 57 | model=nfet_01v8 58 | spiceprefix=X 59 | } 60 | C {sky130_fd_pr/nfet_01v8.sym} 210 -30 0 0 {name=M2 61 | L=0.15 62 | W=2 63 | nf=1 64 | mult=1 65 | ad="'int((nf+1)/2) * W/nf * 0.29'" 66 | pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" 67 | as="'int((nf+2)/2) * W/nf * 0.29'" 68 | ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" 69 | nrd="'0.29 / W'" nrs="'0.29 / W'" 70 | sa=0 sb=0 sd=0 71 | model=nfet_01v8 72 | spiceprefix=X 73 | } 74 | C {devices/iopin.sym} 70 -110 3 0 {name=p1 lab=Vd1} 75 | C {devices/iopin.sym} 230 -110 3 0 {name=p2 lab=Vd2} 76 | C {devices/iopin.sym} 230 30 1 0 {name=p3 lab=Vs2} 77 | C {devices/iopin.sym} 70 30 1 0 {name=p4 lab=Vs1} 78 | C {devices/iopin.sym} 0 -30 2 0 {name=p5 lab=Vb} 79 | C {devices/lab_wire.sym} 300 -30 0 1 {name=p6 sig_type=std_logic lab=Vb} 80 | -------------------------------------------------------------------------------- /Magic/Layouts/TwoStageAmp_v1.mag: -------------------------------------------------------------------------------- 1 | magic 2 | tech sky130A 3 | magscale 1 2 4 | timestamp 1690709672 5 | << checkpaint >> 6 | rect 208 7747 3130 7888 7 | rect 208 6476 7568 7747 8 | rect -1872 3717 7568 6476 9 | rect -3479 3479 7568 3717 10 | rect -3717 313 7568 3479 11 | rect -3717 -1544 6132 313 12 | rect -3717 -1867 5540 -1544 13 | rect -3717 -2648 5138 -1867 14 | rect -3717 -3479 3717 -2648 15 | rect -3479 -3717 3479 -3479 16 | rect -1461 -3858 1461 -3717 17 | use XC1_xCMS XC1_xCMS_0 ../Devices/CMS_Amp 18 | timestamp 1690621426 19 | transform 0 -1 428 1 0 4030 20 | box -1186 -1040 1186 1040 21 | use XM1_xDiffPair_xDiffAmp XM1_xDiffPair_xDiffAmp_0 ../Devices/DiffPair 22 | timestamp 1690621428 23 | transform 0 1 2518 -1 0 318 24 | box -296 -510 296 510 25 | use XM2_xDiffPair_xDiffAmp XM2_xDiffPair_xDiffAmp_0 ../Devices/DiffPair 26 | timestamp 1690621428 27 | transform 0 1 2518 -1 0 -274 28 | box -296 -510 296 510 29 | use XM3_xDiffAmp XM3_xDiffAmp_0 ../Devices/DiffAmp 30 | timestamp 1690621427 31 | transform 1 0 3453 0 1 22 32 | box -425 -1410 425 1410 33 | use XM4_xBias_xDiffAmp XM4_xBias_xDiffAmp_0 ../Devices/Curr_Biasing 34 | timestamp 1690621428 35 | transform -1 0 4576 0 -1 26 36 | box -296 -310 296 310 37 | use XM5_xCMS XM5_xCMS_0 ../Devices/CMS_Amp 38 | timestamp 1690621426 39 | transform 0 -1 4089 1 0 4030 40 | box -2457 -2219 2457 2219 41 | use XM6_xLoad_xDiffAmp XM6_xLoad_xDiffAmp_0 ../Devices/PMOS_Load 42 | timestamp 1690621429 43 | transform 1 0 1120 0 1 22 44 | box -296 -719 296 719 45 | use XM7_xLoad_xDiffAmp XM7_xLoad_xDiffAmp_0 ../Devices/PMOS_Load 46 | timestamp 1690621429 47 | transform 1 0 1712 0 1 22 48 | box -296 -719 296 719 49 | use XR3_xBias_xDiffAmp XR3_xBias_xDiffAmp_0 ../Devices/Curr_Biasing 50 | timestamp 1690621428 51 | transform -1 0 4079 0 -1 26 52 | box -201 -633 201 633 53 | use XR4_xCMS XR4_xCMS_0 ../Devices/CMS_Amp 54 | timestamp 1690621426 55 | transform 1 0 1669 0 1 4030 56 | box -201 -2598 201 2598 57 | << end >> 58 | -------------------------------------------------------------------------------- /Magic/Layouts/TwoStageAmp_v2.mag: -------------------------------------------------------------------------------- 1 | magic 2 | tech sky130A 3 | magscale 1 2 4 | timestamp 1690717263 5 | << checkpaint >> 6 | rect -1046 4035 1876 4176 7 | rect -1046 3858 6314 4035 8 | rect -1461 3717 6314 3858 9 | rect -3479 3479 6314 3717 10 | rect -3717 2764 6314 3479 11 | rect -3717 2608 8394 2764 12 | rect -3866 -762 8394 2608 13 | rect -3717 -2128 8394 -762 14 | rect -3717 -3399 6314 -2128 15 | rect -3717 -3479 3717 -3399 16 | rect -3479 -3717 3479 -3479 17 | rect -1461 -3858 1461 -3717 18 | use XC1 XC1_0 ../Devices/TwoStageDiffAmp 19 | timestamp 1690710088 20 | transform 0 1 6094 -1 0 318 21 | box -1186 -1040 1186 1040 22 | use XM1_xDiffPair_xDiffAmp XM1_xDiffPair_xDiffAmp_0 ../Devices/DiffPair 23 | timestamp 1690710089 24 | transform -1 0 -900 0 -1 -12 25 | box -296 -510 296 510 26 | use XM1_xLoad_xDiffAmp XM1_xLoad_xDiffAmp_0 ../Devices/PMOS_Load 27 | timestamp 1690710090 28 | transform 0 -1 -1196 1 0 -818 29 | box -296 -719 296 719 30 | use XM2_xDiffPair_xDiffAmp XM2_xDiffPair_xDiffAmp_0 ../Devices/DiffPair 31 | timestamp 1690710089 32 | transform -1 0 -1492 0 -1 -12 33 | box -296 -510 296 510 34 | use XM2_xLoad_xDiffAmp XM2_xLoad_xDiffAmp_0 ../Devices/PMOS_Load 35 | timestamp 1690710090 36 | transform 0 -1 -1196 1 0 -1410 37 | box -296 -719 296 719 38 | use XM3_xDiffAmp XM3_xDiffAmp_0 ../Devices/DiffAmp 39 | timestamp 1690710089 40 | transform 0 -1 -1196 1 0 923 41 | box -425 -1410 425 1410 42 | use XM4_xBias_xDiffAmp XM4_xBias_xDiffAmp_0 ../Devices/Curr_Biasing 43 | timestamp 1690710090 44 | transform 0 -1 -1196 1 0 1644 45 | box -296 -310 296 310 46 | use XM5_xCMS XM5_xCMS_0 ../Devices/CMS_Amp 47 | timestamp 1690710088 48 | transform 0 -1 2835 1 0 318 49 | box -2457 -2219 2457 2219 50 | use XR3_xBias_xDiffAmp XR3_xBias_xDiffAmp_0 ../Devices/Curr_Biasing 51 | timestamp 1690710090 52 | transform 0 -1 -1196 1 0 2141 53 | box -201 -633 201 633 54 | use XR4_xCMS XR4_xCMS_0 ../Devices/CMS_Amp 55 | timestamp 1690710088 56 | transform 1 0 415 0 1 318 57 | box -201 -2598 201 2598 58 | << end >> 59 | -------------------------------------------------------------------------------- /Rules/Rule.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | from __future__ import annotations 21 | 22 | import abc 23 | 24 | class Rule(metaclass = abc.ABCMeta): 25 | """Class to represent a rule. 26 | """ 27 | @abc.abstractmethod 28 | def __init__(self, *, name : str) -> None: 29 | self._name = name 30 | 31 | 32 | def __repr__(self) -> str: 33 | cname = self.__class__.__name__ 34 | return f"{cname}(name={self._name})" 35 | 36 | def __eq__(self, __value: object) -> bool: 37 | """Rules are equal if they have the same name. 38 | 39 | Args: 40 | __value (object): Object to be compared. 41 | 42 | Returns: 43 | bool: True if object is a rule, and have the same name. 44 | """ 45 | return (isinstance(__value, Rule)) and (self._name == __value._name) 46 | 47 | def __hash__(self) -> int: 48 | return hash(self._name) 49 | 50 | @property 51 | def name(self) -> str: 52 | """Get the name of the rule. 53 | 54 | Returns: 55 | str: Name of the rule. 56 | """ 57 | return self._name -------------------------------------------------------------------------------- /rectangle_packing_placement/placement_solution.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | from __future__ import annotations 21 | from typing import TYPE_CHECKING 22 | 23 | if TYPE_CHECKING: 24 | from rectangle_packing_placement.placement_floorplan import PlacementFloorplan 25 | from rectangle_packing_placement.placement_problem import PlacementProblem 26 | from rectangle_packing_placement.rectangle_packing_solver.sequence_pair import SequencePair 27 | 28 | from rectangle_packing_placement.rectangle_packing_solver.solution import Solution 29 | 30 | 31 | class PlacementSolution(Solution): 32 | """Class to store a placement solution. 33 | """ 34 | def __init__(self, sequence_pair: SequencePair, floorplan: PlacementFloorplan, problem : PlacementProblem) -> None: 35 | super().__init__(sequence_pair, floorplan) 36 | self.problem = problem 37 | 38 | def __repr__(self) -> str: 39 | s = "PlacementSolution({" 40 | s += "'sequence_pair': " + str(self.sequence_pair) + ", " 41 | s += "'floorplan': " + str(self.floorplan) + ", " 42 | s += "'problem': " + str(self.problem) + "})" 43 | 44 | return s -------------------------------------------------------------------------------- /Logs/plot_csv_logs.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | import pandas as pd 21 | import matplotlib.pyplot as plt 22 | import glob 23 | 24 | from pathlib import Path 25 | import numpy as np 26 | 27 | path = Path('./Logs') 28 | 29 | csv_files = list(path.glob('*.csv')) 30 | 31 | dataframes = {} 32 | 33 | for file in csv_files: 34 | if file.name.endswith("_training_log.csv"): 35 | dataframes[file.name[:-len("_training_log.csv")]] = pd.read_csv(file, index_col=0) 36 | 37 | 38 | for (k,v) in dataframes.items(): 39 | fig, axes = plt.subplots(2, 1, figsize=(12,4),sharex=True) 40 | fig.suptitle(k) 41 | it = list(v.index.values) 42 | avg_rews = np.array(v["avg_rews"]) 43 | std_rews = np.array(v["std_rews"]) 44 | 45 | axes[0].plot(it, avg_rews, color='k') 46 | axes[0].fill_between(it, avg_rews-2*std_rews, avg_rews+2*std_rews, color='b', alpha=0.2) 47 | axes[0].set_ylabel('Average return') 48 | 49 | axes[1].plot(it, np.array(v["avg_actor_loss"]), label="Average actor loss") 50 | axes[1].plot(it, np.array(v["avg_critic_loss"]), label="Average critic loss") 51 | axes[1].legend() 52 | 53 | plt.xlabel("Iteration") 54 | plt.show() -------------------------------------------------------------------------------- /main_place_circuit.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # Script to place a already placed circuit in Magic. 4 | # 5 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 6 | # Johannes Kepler University, Institute for Integrated Circuits 7 | # 8 | # Licensed under the Apache License, Version 2.0 (the "License"); 9 | # you may not use this file except in compliance with the License. 10 | # You may obtain a copy of the License at 11 | # 12 | # http://www.apache.org/licenses/LICENSE-2.0 13 | # 14 | # Unless required by applicable law or agreed to in writing, software 15 | # distributed under the License is distributed on an "AS IS" BASIS, 16 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 17 | # See the License for the specific language governing permissions and 18 | # limitations under the License. 19 | # SPDX-License-Identifier: Apache-2.0 20 | # ======================================================================== 21 | 22 | from __future__ import annotations 23 | from typing import TYPE_CHECKING 24 | if TYPE_CHECKING: 25 | from Magic.MagicDie import MagicDie 26 | 27 | import pickle 28 | from Magic.utils import place_circuit, instantiate_circuit 29 | import os 30 | 31 | ########################################################################### 32 | 33 | CIRCUIT_NAME = "DiffAmp" #Name of the circuit 34 | START_MAGIC = True #If True, Magic will be started, with the loaded placement 35 | 36 | ########################################################################### 37 | 38 | #load the placed circuit 39 | file = open(f"PlacementCircuits/{CIRCUIT_NAME}_placement.pkl", 'rb') 40 | die : MagicDie 41 | die = pickle.load(file) 42 | file.close() 43 | 44 | #get the placed circuit 45 | circuit = die.circuit 46 | 47 | #instantiate the circuit-devices in Magic 48 | instantiate_circuit(circuit, path='Magic/Devices') 49 | 50 | #place the circuit 51 | place_circuit(CIRCUIT_NAME, circuit, debug=False) 52 | 53 | if START_MAGIC: 54 | os.system(f'magic Magic/Placement/{CIRCUIT_NAME}.mag') 55 | -------------------------------------------------------------------------------- /Routing_v2/Graph.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | from __future__ import annotations 21 | import typing 22 | 23 | class Graph: 24 | def __init__(self) -> None: 25 | self._adjacency = {} 26 | 27 | def add_node(self, node): 28 | if isinstance(node, typing.Hashable): 29 | if not (node in self._adjacency): 30 | self._adjacency[node] = [] 31 | else: 32 | raise ValueError("A node must be hashable!") 33 | 34 | def add_edge(self, node1, node2): 35 | if isinstance(node1, typing.Hashable) and isinstance(node2, typing.Hashable): 36 | self.add_node(node1) 37 | self.add_node(node2) 38 | if not (node2 in self._adjacency[node1]): 39 | self._adjacency[node1].append(node2) 40 | 41 | if not (node1 in self._adjacency[node2]): 42 | self._adjacency[node2].append(node1) 43 | 44 | @property 45 | def adjacency(self) -> dict: 46 | return self._adjacency 47 | 48 | def get_neighbors(self, node) -> list: 49 | try: 50 | return self._adjacency[node] 51 | except: 52 | raise ValueError(f"Node {node} not in graph!") 53 | 54 | @property 55 | def nodes(self) -> list: 56 | return list(self._adjacency.keys()) 57 | 58 | -------------------------------------------------------------------------------- /Magic/Devices/XDL_XM3_XM4.mag: -------------------------------------------------------------------------------- 1 | magic 2 | tech sky130A 3 | magscale 1 2 4 | timestamp 1703146904 5 | << checkpaint >> 6 | rect -1556 -1997 1556 1997 7 | << nwell >> 8 | rect -296 -737 296 737 9 | << pmos >> 10 | rect -100 118 100 518 11 | rect -100 -518 100 -118 12 | << pdiff >> 13 | rect -158 506 -100 518 14 | rect -158 130 -146 506 15 | rect -112 130 -100 506 16 | rect -158 118 -100 130 17 | rect 100 506 158 518 18 | rect 100 130 112 506 19 | rect 146 130 158 506 20 | rect 100 118 158 130 21 | rect -158 -130 -100 -118 22 | rect -158 -506 -146 -130 23 | rect -112 -506 -100 -130 24 | rect -158 -518 -100 -506 25 | rect 100 -130 158 -118 26 | rect 100 -506 112 -130 27 | rect 146 -506 158 -130 28 | rect 100 -518 158 -506 29 | << pdiffc >> 30 | rect -146 130 -112 506 31 | rect 112 130 146 506 32 | rect -146 -506 -112 -130 33 | rect 112 -506 146 -130 34 | << nsubdiff >> 35 | rect -260 667 260 701 36 | rect -260 -667 -226 667 37 | rect 226 -667 260 667 38 | rect -260 -701 -164 -667 39 | rect 164 -701 260 -667 40 | << nsubdiffcont >> 41 | rect -164 -701 164 -667 42 | << poly >> 43 | rect -100 599 100 615 44 | rect -100 565 -84 599 45 | rect 84 565 100 599 46 | rect -100 518 100 565 47 | rect -100 71 100 118 48 | rect -100 37 -84 71 49 | rect 84 37 100 71 50 | rect -100 21 100 37 51 | rect -100 -37 100 -21 52 | rect -100 -71 -84 -37 53 | rect 84 -71 100 -37 54 | rect -100 -118 100 -71 55 | rect -100 -565 100 -518 56 | rect -100 -599 -84 -565 57 | rect 84 -599 100 -565 58 | rect -100 -615 100 -599 59 | << polycont >> 60 | rect -84 565 84 599 61 | rect -84 37 84 71 62 | rect -84 -71 84 -37 63 | rect -84 -599 84 -565 64 | << locali >> 65 | rect -260 667 260 701 66 | rect -260 -667 -226 667 67 | rect -100 565 -84 599 68 | rect 84 565 100 599 69 | rect -146 506 -112 522 70 | rect -146 114 -112 130 71 | rect 112 506 146 522 72 | rect 112 114 146 130 73 | rect -100 37 -84 71 74 | rect 84 37 100 71 75 | rect -100 -71 -84 -37 76 | rect 84 -71 100 -37 77 | rect -146 -130 -112 -114 78 | rect -146 -522 -112 -506 79 | rect 112 -130 146 -114 80 | rect 112 -522 146 -506 81 | rect -100 -599 -84 -565 82 | rect 84 -599 100 -565 83 | rect 226 -667 260 667 84 | rect -260 -701 -164 -667 85 | rect 164 -701 260 -667 86 | << properties >> 87 | string FIXED_BBOX -243 -684 243 684 88 | << end >> 89 | -------------------------------------------------------------------------------- /rectangle_packing_placement/rectangle_packing_solver/problem.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Kotaro Terada 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | from typing import Dict, List, Tuple, Union 16 | 17 | 18 | class Problem: 19 | """ 20 | A class to represent a rectangle packing problem. 21 | """ 22 | 23 | def __init__(self, rectangles: List[Union[Dict, List, Tuple]]) -> None: 24 | self.rectangles = [] 25 | self.n = 0 26 | 27 | if not isinstance(rectangles, list): 28 | raise TypeError("Invalid argument: 'rectangles' must be a list.") 29 | 30 | for r in rectangles: 31 | if isinstance(r, (list, tuple)): 32 | self.rectangles.append( 33 | { 34 | "id": self.n, 35 | "width": r[0], 36 | "height": r[1], 37 | "rotatable": r[2] if len(r) >= 3 else False, 38 | } 39 | ) 40 | elif isinstance(r, dict): 41 | self.rectangles.append( 42 | { 43 | "id": self.n, 44 | "width": r["width"], 45 | "height": r["height"], 46 | "rotatable": r["rotatable"] if "rotatable" in r else False, 47 | } 48 | ) 49 | else: 50 | raise TypeError("A rectangle must be a list, tuple, or dict.") 51 | 52 | self.n += 1 53 | 54 | def __repr__(self) -> str: 55 | s = "Problem({" 56 | s += "'n': " + str(self.n) + ", " 57 | s += "'rectangles': " + str(self.rectangles) + "})" 58 | 59 | return s 60 | -------------------------------------------------------------------------------- /Logs/plot_csv_logs_simanneal.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | import pandas as pd 21 | import matplotlib.pyplot as plt 22 | import glob 23 | 24 | from pathlib import Path 25 | import numpy as np 26 | 27 | path = Path('./Logs') 28 | 29 | csv_files = list(path.glob('*.csv')) 30 | 31 | dataframes = {} 32 | 33 | for file in csv_files: 34 | if file.name.endswith("_simanneal_log.csv"): 35 | dataframes[file.name[:-len("_simanneal_log.csv")]] = pd.read_csv(file, index_col=0) 36 | 37 | 38 | for (k,v) in dataframes.items(): 39 | fig, axes = plt.subplots(2,1, figsize=(12,4)) 40 | fig.suptitle(k) 41 | it = list(v.index.values) 42 | step = np.array(v["step"]) 43 | i_start = np.where(step==0)[0][-1]+1 44 | step = step[i_start:] 45 | energy = np.array(v["E"]) 46 | energy = energy[i_start:] 47 | 48 | energy_avg = np.mean(np.reshape(energy, (energy.shape[0]//100, 100)),axis=1) 49 | energy_std = np.std(np.reshape(energy, (energy.shape[0]//100, 100)),axis=1) 50 | axes[0].plot(step, energy, color='k') 51 | axes[0].set_ylabel('Energy') 52 | axes[0].set_xlabel('Step') 53 | 54 | axes[1].plot(np.arange(1,energy_avg.shape[0]+1), energy_avg, color='k') 55 | axes[1].fill_between(np.arange(1,energy_avg.shape[0]+1), energy_avg-energy_std, energy_avg+energy_std, color='b', alpha=0.2) 56 | axes[1].set_ylabel('Average energy') 57 | plt.show() -------------------------------------------------------------------------------- /Routing_v2/Pins.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | from __future__ import annotations 21 | from typing import TYPE_CHECKING 22 | if TYPE_CHECKING: 23 | from Magic.MagicTerminal import MagicPin 24 | from Magic.MagicDie import MagicDiePin 25 | from SchematicCapture.Net import Net 26 | 27 | from Routing_v2.Grid import global_grid 28 | 29 | class GlobalPins: 30 | """Class to store pins of multiple routes. 31 | """ 32 | def __init__(self) -> None: 33 | self._pins = {} 34 | 35 | def add_pin(self, pin : MagicPin|MagicDiePin, net : Net): 36 | """Add a pin to the global pins. 37 | 38 | Args: 39 | pin (MagicPin | MagicDiePin): Pin to be added. 40 | net (Net): Net to which the pin belongs. 41 | """ 42 | 43 | if net in self._pins: 44 | self._pins[net].append(pin) 45 | else: 46 | self._pins[net] = [pin] 47 | 48 | #update grid lines for the pins 49 | global_grid.setup_grid_for_pins(self.get_all_pins()) 50 | 51 | def get_all_pins(self) -> list[MagicPin|MagicDiePin]: 52 | """Get a list of all pins. 53 | 54 | Returns: 55 | list[MagicPin|MagicDiePin]: List of pins. 56 | """ 57 | pins = [] 58 | for net, pin_list in self._pins.items(): 59 | pins.extend(pin_list) 60 | 61 | return pins 62 | 63 | global_pins = GlobalPins() -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/simulation/GmBias_tb.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/RALF/Circuits/Examples/MillerOpAmpCMMFB/GmBias_tb.sch 2 | **.subckt GmBias_tb 3 | x1 VDD Vbias GND GmBias 4 | V3 VDD GND 1.8 5 | .save i(v3) 6 | **** begin user architecture code 7 | 8 | 9 | 10 | * ngspice commands 11 | .option savecurrents 12 | .save all 13 | .control 14 | op 15 | .endc 16 | 17 | 18 | 19 | .lib /home/jakob/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice tt 20 | 21 | **** end user architecture code 22 | **.ends 23 | 24 | * expanding symbol: /home/jakob/Documents/RALF/Circuits/Examples/MillerOpAmpCMMFB/GmBias.sym # of 25 | *+ pins=3 26 | ** sym_path: /home/jakob/Documents/RALF/Circuits/Examples/MillerOpAmpCMMFB/GmBias.sym 27 | ** sch_path: /home/jakob/Documents/RALF/Circuits/Examples/MillerOpAmpCMMFB/GmBias.sch 28 | .subckt GmBias Vdd Vbias Vss 29 | *.opin Vbias 30 | *.iopin Vss 31 | *.iopin Vdd 32 | XM6 Vbias Vbias Vss Vss sky130_fd_pr__nfet_01v8 L=2 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 33 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 34 | + sa=0 sb=0 sd=0 mult=1 m=1 35 | XM2 net1 net1 Vdd Vdd sky130_fd_pr__pfet_01v8 L=1 W=4 nf=2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 36 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 37 | + sa=0 sb=0 sd=0 mult=1 m=1 38 | XM1 Vbias net1 Vdd Vdd sky130_fd_pr__pfet_01v8 L=1 W=4 nf=2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 39 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 40 | + sa=0 sb=0 sd=0 mult=1 m=1 41 | XM3 net1 Vbias net2 Vss sky130_fd_pr__nfet_01v8 L=2 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 42 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 43 | + sa=0 sb=0 sd=0 mult=1 m=1 44 | XR6 Vss net2 Vss sky130_fd_pr__res_xhigh_po_0p35 L=1 mult=1 m=1 45 | XM4 net1 net1 Vbias Vss sky130_fd_pr__nfet_01v8 L=2 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 46 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 47 | + sa=0 sb=0 sd=0 mult=1 m=1 48 | .ends 49 | 50 | .GLOBAL GND 51 | .GLOBAL VDD 52 | .end 53 | -------------------------------------------------------------------------------- /Circuits/Examples/Latch/CCLatch_tb.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/RALF/Circuits/Examples/Latch/CCLatch_tb.sch 2 | **.subckt CCLatch_tb 3 | x1 VDD out outn in inn clk GND CCLatch 4 | V1 VDD GND 1.8 5 | .save i(v1) 6 | V2 clk GND PULSE(0 1.8 50n 0.1n 0.1n 50ns 100ns 10) 7 | .save i(v2) 8 | V3 in GND PULSE(0 1.8 40ns 0.1n 0.1n 70ns 200ns 5) 9 | .save i(v3) 10 | E1 net1 GND in GND -1 11 | V4 inn net1 1.8 12 | .save i(v4) 13 | **** begin user architecture code 14 | 15 | 16 | 17 | * ngspice commands 18 | .option savecurrents 19 | .save all 20 | .control 21 | tran 10ns 1000ns 22 | .endc 23 | 24 | 25 | 26 | .lib /home/jakob/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice tt 27 | 28 | **** end user architecture code 29 | **.ends 30 | 31 | * expanding symbol: /home/jakob/Documents/RALF/Circuits/Examples/Latch/CCLatch.sym # of pins=7 32 | ** sym_path: /home/jakob/Documents/RALF/Circuits/Examples/Latch/CCLatch.sym 33 | ** sch_path: /home/jakob/Documents/RALF/Circuits/Examples/Latch/CCLatch.sch 34 | .subckt CCLatch Vdd out outn in inn clk Vss 35 | *.iopin Vdd 36 | *.iopin Vss 37 | *.ipin in 38 | *.ipin inn 39 | *.ipin clk 40 | *.opin outn 41 | *.opin out 42 | XM1 outn in Vmid Vss sky130_fd_pr__nfet_01v8 L=1 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 43 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 44 | + sa=0 sb=0 sd=0 mult=1 m=1 45 | XM2 out inn Vmid Vss sky130_fd_pr__nfet_01v8 L=1 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 46 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 47 | + sa=0 sb=0 sd=0 mult=1 m=1 48 | XM3 outn out Vdd Vdd sky130_fd_pr__pfet_01v8 L=1 W=2 nf=2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 49 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 50 | + sa=0 sb=0 sd=0 mult=1 m=1 51 | XM4 out outn Vdd Vdd sky130_fd_pr__pfet_01v8 L=1 W=2 nf=2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 52 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 53 | + sa=0 sb=0 sd=0 mult=1 m=1 54 | XM5 Vmid clk Vss Vss sky130_fd_pr__nfet_01v8 L=2 W=10 nf=5 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 55 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 56 | + sa=0 sb=0 sd=0 mult=1 m=1 57 | .ends 58 | 59 | .GLOBAL VDD 60 | .GLOBAL GND 61 | .end 62 | -------------------------------------------------------------------------------- /main_place_route_circuit.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # Script to place and route a circuit in Magic. 4 | # 5 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 6 | # Johannes Kepler University, Institute for Integrated Circuits 7 | # 8 | # Licensed under the Apache License, Version 2.0 (the "License"); 9 | # you may not use this file except in compliance with the License. 10 | # You may obtain a copy of the License at 11 | # 12 | # http://www.apache.org/licenses/LICENSE-2.0 13 | # 14 | # Unless required by applicable law or agreed to in writing, software 15 | # distributed under the License is distributed on an "AS IS" BASIS, 16 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 17 | # See the License for the specific language governing permissions and 18 | # limitations under the License. 19 | # SPDX-License-Identifier: Apache-2.0 20 | # ======================================================================== 21 | 22 | from __future__ import annotations 23 | from typing import TYPE_CHECKING 24 | if TYPE_CHECKING: 25 | from Magic.MagicDie import MagicDie 26 | 27 | import pickle 28 | from Magic.utils import place_circuit, instantiate_circuit 29 | import os 30 | 31 | ############################################################### 32 | 33 | CIRCUIT_NAME = "DiffAmp" #Name of the circuit 34 | 35 | ############################################################### 36 | 37 | #load the placed circuit 38 | file = open(f"PlacementCircuits/{CIRCUIT_NAME}_placement.pkl", 'rb') 39 | die : MagicDie 40 | die = pickle.load(file) 41 | file.close() 42 | 43 | #get the placed circuit 44 | circuit = die.circuit 45 | 46 | #instantiate the circuit-devices in Magic 47 | instantiate_circuit(circuit, path='Magic/Devices') 48 | 49 | #place the circuit 50 | place_circuit(CIRCUIT_NAME, circuit, debug=False) 51 | 52 | #open the routing file 53 | if os.path.isfile(f'Magic/Routing/{CIRCUIT_NAME}_routing.tcl'): 54 | routing_file = open(f'Magic/Routing/{CIRCUIT_NAME}_routing.tcl', 'r') 55 | commands = [line for line in routing_file] 56 | routing_file.close() 57 | commands.insert(0, f"load Magic/Placement/{CIRCUIT_NAME}.mag\n") 58 | routing_file = open(f'Magic/Routing/{CIRCUIT_NAME}_routing_temp.tcl', 'w') 59 | for l in commands: 60 | routing_file.write(l) 61 | routing_file.close() 62 | else: 63 | raise FileNotFoundError("Routing file not found!") 64 | 65 | os.system(f'magic -nowrapper Magic/Routing/{CIRCUIT_NAME}_routing_temp.tcl') 66 | os.remove(f'Magic/Routing/{CIRCUIT_NAME}_routing_temp.tcl') 67 | -------------------------------------------------------------------------------- /Network/D2RL_Critic.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | import torch 21 | from torch_geometric.nn import SAGEConv, MeanAggregation 22 | from torch_geometric.nn.norm import BatchNorm 23 | import torch.nn.functional as F 24 | 25 | class D2RL_Critic(torch.nn.Module): 26 | def __init__(self): 27 | super().__init__() 28 | 29 | self.conv1 = SAGEConv(-1, 16) 30 | self.norm1 = BatchNorm(16) 31 | self.conv2 = SAGEConv(16, 16) 32 | self.mean_aggr = MeanAggregation() 33 | 34 | 35 | self.norm_lin1 = torch.nn.BatchNorm1d(16) 36 | self.lin_1 = torch.nn.Linear(16, 16) 37 | self.norm_lin2 = torch.nn.BatchNorm1d(32) 38 | self.lin_2 = torch.nn.Linear(32, 16) 39 | self.norm_lin3 = torch.nn.BatchNorm1d(32) 40 | self.lin_3 = torch.nn.Linear(32, 16) 41 | 42 | self.linear = torch.nn.Linear(16, 1) 43 | 44 | def forward(self, data): 45 | 46 | x = data.x 47 | edge_index = data.edge_index 48 | batch = data.batch 49 | 50 | x = self.conv1(x, edge_index) 51 | x = F.relu(x) 52 | x = self.norm1(x) 53 | x = self.conv2(x, edge_index) 54 | x = F.relu(x) 55 | x_encoded = self.mean_aggr(x, batch) 56 | x = self.norm_lin1(x_encoded) 57 | x = self.lin_1(x) 58 | x = F.relu(x) 59 | x = self.norm_lin2(torch.concatenate([x, x_encoded], dim=1)) 60 | x = self.lin_2(x) 61 | x = F.relu(x) 62 | x = self.norm_lin3(torch.concatenate([x, x_encoded], dim=1)) 63 | x = self.lin_3(x) 64 | x = F.relu(x) 65 | 66 | x = self.linear(x) 67 | 68 | return x 69 | -------------------------------------------------------------------------------- /rectangle_packing_placement/placement_problem.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | from __future__ import annotations 21 | from typing import TYPE_CHECKING 22 | if TYPE_CHECKING: 23 | from SchematicCapture.Circuit import Circuit 24 | from SchematicCapture.Devices import Device 25 | 26 | from rectangle_packing_placement.rectangle_packing_solver.problem import Problem 27 | from Environment.RUDY import RUDY 28 | from PDK.PDK import global_pdk 29 | 30 | class PlacementProblem(Problem): 31 | """Class to setup a placement problem. 32 | """ 33 | def __init__(self, circuit : Circuit) -> None: 34 | """Init the problem. 35 | 36 | Args: 37 | circuit (Circuit): Circuit of the problem. 38 | """ 39 | #store the circuit 40 | self.circuit = circuit 41 | 42 | #setup RUDY of the PDK, for 43 | #wire-density estimation 44 | self.rudy = RUDY(global_pdk) 45 | 46 | #store a map between rectangles and devices 47 | self._rectangle_device_map = {} 48 | 49 | #setup the rectangles of the problem 50 | rectangles = [] 51 | n_id = 0 52 | device : Device 53 | for name, device in circuit.devices.items(): 54 | cell = device.cell 55 | rectangles.append([cell.width, cell.height, 1]) 56 | self._rectangle_device_map[n_id] = name 57 | n_id += 1 58 | 59 | #setup the rectangle packing problem 60 | super().__init__(rectangles) 61 | 62 | def id_to_device(self, id : int) -> str: 63 | """Maps rectangle id to the device name. 64 | 65 | Args: 66 | id (int): Rectangle id. 67 | 68 | Returns: 69 | str: Name of the corresponding device. 70 | """ 71 | return self._rectangle_device_map[id] -------------------------------------------------------------------------------- /Circuits/Examples/Latch/CCLatch_tb.sch: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2 2 | } 3 | G {} 4 | K {} 5 | V {} 6 | S {} 7 | E {} 8 | N -560 -20 -560 0 { 9 | lab=GND} 10 | N -560 -100 -560 -80 { 11 | lab=VDD} 12 | N -450 -20 -450 0 { 13 | lab=GND} 14 | N -450 -100 -450 -80 { 15 | lab=clk} 16 | N 250 -110 320 -110 { 17 | lab=clk} 18 | N 180 -130 320 -130 { 19 | lab=in} 20 | N 180 -90 320 -90 { 21 | lab=inn} 22 | N 620 -120 660 -120 { 23 | lab=out} 24 | N 620 -100 660 -100 { 25 | lab=outn} 26 | N -190 -20 -190 0 { 27 | lab=GND} 28 | N -190 -100 -190 -80 { 29 | lab=in} 30 | N -10 -20 -10 0 { 31 | lab=GND} 32 | N -60 -30 -50 -30 { 33 | lab=GND} 34 | N -60 -30 -60 -10 { 35 | lab=GND} 36 | N -60 -10 -10 -10 { 37 | lab=GND} 38 | N -60 -70 -50 -70 { 39 | lab=in} 40 | N -60 -90 -60 -70 { 41 | lab=in} 42 | N -190 -90 -60 -90 { 43 | lab=in} 44 | N -10 -100 -10 -80 { 45 | lab=#net1} 46 | N -10 -180 -10 -160 { 47 | lab=inn} 48 | C {/home/jakob/Documents/RALF/Circuits/Examples/Latch/CCLatch.sym} 470 -110 0 0 {name=x1} 49 | C {devices/vsource.sym} -560 -50 0 0 {name=V1 value=1.8} 50 | C {devices/vdd.sym} -560 -100 0 0 {name=l1 lab=VDD} 51 | C {devices/vdd.sym} 470 -170 0 0 {name=l2 lab=VDD} 52 | C {devices/gnd.sym} -560 0 0 0 {name=l3 lab=GND} 53 | C {devices/gnd.sym} 470 -50 0 0 {name=l4 lab=GND} 54 | C {devices/vsource.sym} -450 -50 0 0 {name=V2 value="PULSE(0 1.8 5n 0.1n 0.1n 5ns 10ns 10)"} 55 | C {devices/gnd.sym} -450 0 0 0 {name=l6 lab=GND} 56 | C {devices/lab_wire.sym} -450 -100 0 0 {name=p1 sig_type=std_logic lab=clk} 57 | C {devices/lab_wire.sym} 250 -110 0 0 {name=p2 sig_type=std_logic lab=clk} 58 | C {devices/vsource.sym} -190 -50 0 0 {name=V3 value="PULSE(0 1.8 2.5ns 0.1n 0.1n 5ns 20ns 5)"} 59 | C {devices/gnd.sym} -190 0 0 0 {name=l5 lab=GND} 60 | C {devices/lab_wire.sym} -190 -100 0 0 {name=p3 sig_type=std_logic lab=in} 61 | C {devices/vcvs.sym} -10 -50 0 0 {name=E1 value=-1} 62 | C {devices/gnd.sym} -10 0 0 0 {name=l7 lab=GND} 63 | C {devices/lab_wire.sym} -10 -180 0 0 {name=p4 sig_type=std_logic lab=inn} 64 | C {devices/lab_wire.sym} 180 -130 0 0 {name=p5 sig_type=std_logic lab=in} 65 | C {devices/lab_wire.sym} 180 -90 0 0 {name=p6 sig_type=std_logic lab=inn} 66 | C {devices/lab_wire.sym} 660 -120 0 1 {name=p7 sig_type=std_logic lab=out} 67 | C {devices/lab_wire.sym} 660 -100 0 1 {name=p8 sig_type=std_logic lab=outn} 68 | C {devices/vsource.sym} -10 -130 0 0 {name=V4 value=1.8} 69 | C {devices/simulator_commands.sym} -190 -520 0 0 {name=COMMANDS 70 | simulator=ngspice 71 | only_toplevel=false 72 | value=" 73 | * ngspice commands 74 | .option savecurrents 75 | .save all 76 | .control 77 | tran 1ns 100ns 78 | .endc 79 | "} 80 | C {devices/code_shown.sym} 0 -540 0 0 {name=ngspice 81 | only_toplevel=false 82 | format="tcleval( @value )" 83 | value= 84 | ".lib $::SKYWATER_MODELS/sky130.lib.spice tt 85 | "} 86 | -------------------------------------------------------------------------------- /Network/GAT_D2RL_Critic.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | import torch 21 | from torch_geometric.nn import GATConv, MeanAggregation 22 | from torch_geometric.nn.norm import BatchNorm 23 | import torch.nn.functional as F 24 | 25 | class GAT_D2RL_Critic(torch.nn.Module): 26 | def __init__(self): 27 | super().__init__() 28 | 29 | self.graph_embedding = GATConv(-1, 16, edge_dim=2) 30 | self.norm1 = BatchNorm(16) 31 | self.graph_embedding2 = GATConv(16, 16, edge_dim=2) 32 | self.mean_aggr = MeanAggregation() 33 | 34 | self.norm_lin1 = torch.nn.BatchNorm1d(16) 35 | self.lin_1 = torch.nn.Linear(16, 16) 36 | self.norm_lin2 = torch.nn.BatchNorm1d(32) 37 | self.lin_2 = torch.nn.Linear(32, 16) 38 | self.norm_lin3 = torch.nn.BatchNorm1d(32) 39 | self.lin_3 = torch.nn.Linear(32, 16) 40 | 41 | self.linear = torch.nn.Linear(16, 1) 42 | 43 | def forward(self, data): 44 | 45 | x = data.x 46 | edge_index = data.edge_index 47 | edge_attr = data.edge_attr 48 | batch = data.batch 49 | 50 | x_encoded = self.graph_embedding(x, edge_index, edge_attr=edge_attr) 51 | x_encoded = F.relu(x_encoded) 52 | x_encoded = self.norm1(x_encoded) 53 | x_encoded = self.graph_embedding2(x_encoded, edge_index, edge_attr=edge_attr) 54 | x_encoded = F.relu(x_encoded) 55 | x_encoded = self.mean_aggr(x_encoded, batch) 56 | 57 | x = self.norm_lin1(x_encoded) 58 | x = self.lin_1(x) 59 | x = F.relu(x) 60 | x = self.norm_lin2(torch.concatenate([x, x_encoded], dim=1)) 61 | x = self.lin_2(x) 62 | x = F.relu(x) 63 | x = self.norm_lin3(torch.concatenate([x, x_encoded], dim=1)) 64 | x = self.lin_3(x) 65 | x = F.relu(x) 66 | 67 | return self.linear(x) 68 | -------------------------------------------------------------------------------- /Network/D2RL_Actor.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | import torch 21 | from torch_geometric.nn import SAGEConv, MeanAggregation 22 | from torch_geometric.nn.norm import BatchNorm 23 | import torch.nn.functional as F 24 | 25 | 26 | class D2RL_Actor(torch.nn.Module): 27 | def __init__(self, out_dim_x, out_dim_y): 28 | super().__init__() 29 | 30 | self.conv1 = SAGEConv(-1, 16) 31 | self.norm1 = BatchNorm(16) 32 | self.conv2 = SAGEConv(16, 16) 33 | self.mean_aggr = MeanAggregation() 34 | 35 | 36 | self.norm_lin1 = torch.nn.BatchNorm1d(16) 37 | self.lin_1 = torch.nn.Linear(16, 16) 38 | self.norm_lin2 = torch.nn.BatchNorm1d(32) 39 | self.lin_2 = torch.nn.Linear(32, 16) 40 | self.norm_lin3 = torch.nn.BatchNorm1d(32) 41 | self.lin_3 = torch.nn.Linear(32, 16) 42 | 43 | 44 | self.linear_x = torch.nn.Linear(16, out_dim_x) 45 | self.linear_y = torch.nn.Linear(16, out_dim_y) 46 | self.linear_rot = torch.nn.Linear(16, 4) 47 | 48 | def forward(self, data): 49 | 50 | x = data.x 51 | edge_index = data.edge_index 52 | batch = data.batch 53 | 54 | x = self.conv1(x, edge_index) 55 | x = F.relu(x) 56 | x = self.norm1(x) 57 | x = self.conv2(x, edge_index) 58 | x = F.relu(x) 59 | x_encoded = self.mean_aggr(x, batch) 60 | x = self.norm_lin1(x_encoded) 61 | x = self.lin_1(x) 62 | x = F.relu(x) 63 | x = self.norm_lin2(torch.concatenate([x, x_encoded], dim=1)) 64 | x = self.lin_2(x) 65 | x = F.relu(x) 66 | x = self.norm_lin3(torch.concatenate([x, x_encoded], dim=1)) 67 | x = self.lin_3(x) 68 | x = F.relu(x) 69 | 70 | y = self.linear_y(x) 71 | xx = self.linear_x(x) 72 | 73 | y = F.softmax(y, dim=1) 74 | xx = F.softmax(xx, dim=1) 75 | rot = self.linear_rot(x) 76 | rot = F.softmax(rot, dim=1) 77 | 78 | 79 | return xx, y, rot 80 | -------------------------------------------------------------------------------- /PDK/layers.json: -------------------------------------------------------------------------------- 1 | { 2 | "ScaleFactor":10, 3 | "device_layers":["nwell","dnwell", "mimcap"], 4 | "layer_stack":["li","m1","m2","m3","m4","m5"], 5 | "via_stack":["mcon","via1","via2","via3","via4"], 6 | "aliases":{ 7 | "li" : ["li1", "locali"], 8 | "m1" : ["met1", "metal1"], 9 | "m2" : ["met2", "metal2"], 10 | "m3" : ["met3", "metal3"], 11 | "m4" : ["met4", "metal4"], 12 | "m5" : ["met5", "metal5"] 13 | }, 14 | "via_map":{ 15 | "lim1": "mcon", 16 | "m1li": "mcon", 17 | "m1m2": "via1", 18 | "m2m1": "via1", 19 | "m2m3": "via2", 20 | "m3m2": "via2", 21 | "m3m4": "via3", 22 | "m4m3": "via3", 23 | "m4m5": "via4", 24 | "m5m4": "via4" 25 | }, 26 | "li": 27 | { 28 | "Width": 180, 29 | "Space": 180, 30 | "MinArea": 57600, 31 | "Resistivity": 125 32 | } 33 | , 34 | "mcon": 35 | { 36 | "Stack": ["li", "m1"], 37 | "Space": 190, 38 | "Width": 180, 39 | "min_enclosure": 60, 40 | "Resistivity": 11925 41 | } 42 | , 43 | "m1": 44 | { 45 | "Width": 140, 46 | "Space": 140, 47 | "MinArea": 90000, 48 | "Resistivity": 125 49 | } 50 | , 51 | "via1": 52 | { 53 | "Stack": ["m1", "m2"], 54 | "Space": 170, 55 | "Width": 260, 56 | "min_enclosure": 60, 57 | "Resistivity": 12150 58 | } 59 | , 60 | "m2": 61 | { 62 | "Width": 140, 63 | "Space": 140, 64 | "MinArea": 67600, 65 | "Resistivity": 125 66 | } 67 | , 68 | "via2": 69 | { 70 | "Stack": ["m2", "m3"], 71 | "Space": 200, 72 | "Width": 280, 73 | "min_enclosure": 80, 74 | "Resistivity": 14322 75 | } 76 | , 77 | "m3": 78 | { 79 | "Width": 300, 80 | "Space": 400, 81 | "MinArea": 250000, 82 | "Resistivity": 47 83 | } 84 | , 85 | "via3": 86 | { 87 | "Stack": ["m3", "m4"], 88 | "Space": 200, 89 | "Width": 320, 90 | "min_enclosure": 80, 91 | "Resistivity": 13299 92 | } 93 | , 94 | "m4": 95 | { 96 | "Width": 300, 97 | "Space": 400, 98 | "MinArea": 250000, 99 | "Resistivity": 47 100 | } 101 | , 102 | "via4": 103 | { 104 | "Stack": ["m4", "m5"], 105 | "Space": 800, 106 | "Width": 1180, 107 | "min_enclosure": 320, 108 | "Resistivity": 1919 109 | } 110 | , 111 | "m5": 112 | { 113 | "Width": 1600, 114 | "Space": 1600, 115 | "MinArea": 4000000, 116 | "Resistivity": 29 117 | } 118 | , 119 | "nwell": 120 | { 121 | "Width": 840, 122 | "Space": 1270 123 | } 124 | , 125 | "dnwell": 126 | { 127 | "Width": 3000, 128 | "Space": 6300 129 | } 130 | , 131 | "mimcap": 132 | { 133 | "Width": 2000, 134 | "Space": 1200 135 | } 136 | } 137 | -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/OpAmp.sch: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2 2 | } 3 | G {} 4 | K {} 5 | V {} 6 | S {} 7 | E {} 8 | N 260 -390 350 -390 { 9 | lab=Vp} 10 | N 260 -370 350 -370 { 11 | lab=Vn} 12 | N 310 -350 350 -350 { 13 | lab=vbias} 14 | N 650 -410 680 -410 { 15 | lab=VPWR} 16 | N 320 -410 350 -410 { 17 | lab=vcmfb} 18 | N 310 -350 310 -330 { 19 | lab=vbias} 20 | N 310 -330 350 -330 { 21 | lab=vbias} 22 | N 650 -350 680 -350 { 23 | lab=VGND} 24 | N 270 -330 310 -330 { 25 | lab=vbias} 26 | N 650 -370 710 -370 { 27 | lab=Vop} 28 | N 710 -370 710 -240 { 29 | lab=Vop} 30 | N 710 -240 710 -220 { 31 | lab=Vop} 32 | N 650 -220 710 -220 { 33 | lab=Vop} 34 | N 650 -390 690 -390 { 35 | lab=Von} 36 | N 690 -390 690 -240 { 37 | lab=Von} 38 | N 650 -240 690 -240 { 39 | lab=Von} 40 | N 690 -390 750 -390 { 41 | lab=Von} 42 | N 710 -370 750 -370 { 43 | lab=Vop} 44 | N 300 -240 350 -240 { 45 | lab=vcmfb} 46 | N 270 -110 350 -110 { 47 | lab=vbias} 48 | N 260 -300 670 -300 { 49 | lab=Vocm} 50 | N 670 -300 670 -260 { 51 | lab=Vocm} 52 | N 650 -260 670 -260 { 53 | lab=Vocm} 54 | N 260 -460 310 -460 { 55 | lab=VPWR} 56 | N 310 -460 680 -460 { 57 | lab=VPWR} 58 | N 680 -460 680 -410 { 59 | lab=VPWR} 60 | N 330 -90 350 -90 { 61 | lab=VGND} 62 | N 650 -200 680 -200 { 63 | lab=vbias} 64 | N 680 -350 730 -350 { 65 | lab=VGND} 66 | N 730 -350 730 -60 { 67 | lab=VGND} 68 | N 330 -60 730 -60 { 69 | lab=VGND} 70 | N 330 -220 350 -220 { 71 | lab=VGND} 72 | N 330 -220 330 -90 { 73 | lab=VGND} 74 | N 310 -260 350 -260 { 75 | lab=VPWR} 76 | N 310 -260 310 -130 { 77 | lab=VPWR} 78 | N 310 -130 350 -130 { 79 | lab=VPWR} 80 | N 330 -90 330 -60 { 81 | lab=VGND} 82 | N 260 -60 330 -60 { 83 | lab=VGND} 84 | N 270 -190 310 -190 { 85 | lab=VPWR} 86 | N 270 -240 300 -240 {} 87 | C {devices/lab_wire.sym} 270 -240 0 0 {name=p2 sig_type=std_logic lab=vcmfb} 88 | C {devices/opin.sym} 750 -390 0 0 {name=p3 lab=Von} 89 | C {devices/opin.sym} 750 -370 0 0 {name=p4 lab=Vop} 90 | C {devices/ipin.sym} 260 -300 0 0 {name=p6 lab=Vocm} 91 | C {devices/ipin.sym} 260 -390 0 0 {name=p7 lab=Vp} 92 | C {devices/ipin.sym} 260 -370 0 0 {name=p8 lab=Vn} 93 | C {devices/iopin.sym} 260 -460 0 1 {name=p9 lab=VPWR} 94 | C {devices/iopin.sym} 260 -60 2 0 {name=p10 lab=VGND} 95 | C {devices/lab_wire.sym} 320 -410 0 0 {name=p1 sig_type=std_logic lab=vcmfb} 96 | C {devices/title.sym} 160 0 0 0 {name=l1 author="Jakob Ratschenberger"} 97 | C {/home/jakob/Documents/RALF/Circuits/Examples/OpAmp/CMMFeedback.sym} 500 -230 0 1 {name=x2} 98 | C {/home/jakob/Documents/RALF/Circuits/Examples/OpAmp/GmBias.sym} 500 -110 0 1 {name=x3} 99 | C {/home/jakob/Documents/RALF/Circuits/Examples/OpAmp/MillerOpAmp.sym} 500 -370 0 0 {name=x1} 100 | C {devices/lab_wire.sym} 270 -330 0 0 {name=p11 sig_type=std_logic lab=vbias} 101 | C {devices/lab_wire.sym} 680 -200 0 1 {name=p12 sig_type=std_logic lab=vbias} 102 | C {devices/lab_wire.sym} 270 -110 0 0 {name=p13 sig_type=std_logic lab=vbias} 103 | C {devices/lab_wire.sym} 270 -190 0 0 {name=p14 sig_type=std_logic lab=VPWR} 104 | -------------------------------------------------------------------------------- /rectangle_packing_placement/placement_visualizer.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Kotaro Terada 2 | # 3 | # Copyright 2023 Jakob Ratschenberger 4 | # 5 | # Modifications: 6 | # - Added text to rectangles for the placement task 7 | # 8 | # 9 | # Licensed under the Apache License, Version 2.0 (the "License"); 10 | # you may not use this file except in compliance with the License. 11 | # You may obtain a copy of the License at 12 | # 13 | # http://www.apache.org/licenses/LICENSE-2.0 14 | # 15 | # Unless required by applicable law or agreed to in writing, software 16 | # distributed under the License is distributed on an "AS IS" BASIS, 17 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 18 | # See the License for the specific language governing permissions and 19 | # limitations under the License. 20 | 21 | 22 | from __future__ import annotations 23 | from typing import TYPE_CHECKING 24 | 25 | from rectangle_packing_placement.placement_solution import PlacementSolution 26 | 27 | from rectangle_packing_placement.rectangle_packing_solver.visualizer import Visualizer 28 | import matplotlib.patches as patches 29 | from matplotlib import pylab as plt 30 | 31 | class PlacementVisualizer(Visualizer): 32 | def visualize(self, solution: PlacementSolution, path: str = "floorplan.png", title: str = "Floorplan") -> None: 33 | if not isinstance(solution, PlacementSolution): 34 | raise TypeError("Invalid argument: 'solution' must be an instance of PlacementSolution.") 35 | 36 | positions = solution.floorplan.positions 37 | bounding_box = solution.floorplan.bounding_box 38 | problem = solution.problem 39 | 40 | # Figure settings 41 | bb_width = bounding_box[0] 42 | bb_height = bounding_box[1] 43 | fig = plt.figure(figsize=(10, 10 * bb_height / bb_width + 0.5)) 44 | ax = plt.axes() 45 | ax.set_aspect("equal") 46 | plt.xlim([0, bb_width]) 47 | plt.ylim([0, bb_height]) 48 | plt.xlabel("X") 49 | plt.ylabel("Y") 50 | plt.title(title) 51 | 52 | # Plot every rectangle 53 | for i, rectangle in enumerate(positions): 54 | color, fontcolor = self.get_color(i) 55 | r = patches.Rectangle( 56 | xy=(rectangle["x"], rectangle["y"]), 57 | width=rectangle["width"], 58 | height=rectangle["height"], 59 | edgecolor="#000000", 60 | facecolor=color, 61 | alpha=1.0, 62 | fill=True, 63 | ) 64 | ax.add_patch(r) 65 | 66 | # Add text label 67 | centering_offset = 0.011 68 | center_x = rectangle["x"] + rectangle["width"] / 2 - bb_width * centering_offset 69 | center_y = rectangle["y"] + rectangle["height"] / 2 - bb_height * centering_offset 70 | ax.text(x=center_x, y=center_y, s=problem.id_to_device(rectangle["id"]), fontsize=18, color=fontcolor) 71 | 72 | # Output 73 | if path is None: 74 | plt.show() 75 | else: 76 | fig.savefig(path) 77 | 78 | plt.close() -------------------------------------------------------------------------------- /Network/GAT_D2RL_Actor.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | import torch 21 | from torch_geometric.nn import GATConv, MeanAggregation 22 | from torch_geometric.nn.norm import BatchNorm 23 | import torch.nn.functional as F 24 | 25 | 26 | class GAT_D2RL_Actor(torch.nn.Module): 27 | def __init__(self, out_dim_x, out_dim_y): 28 | super().__init__() 29 | 30 | self.graph_embedding = GATConv(-1, 16, edge_dim=2) 31 | self.norm1 = BatchNorm(16) 32 | self.graph_embedding2 = GATConv(16, 16, edge_dim=2) 33 | self.mean_aggr = MeanAggregation() 34 | 35 | self.norm_lin1 = torch.nn.BatchNorm1d(16) 36 | self.lin_1 = torch.nn.Linear(16, 16) 37 | self.norm_lin2 = torch.nn.BatchNorm1d(32) 38 | self.lin_2 = torch.nn.Linear(32, 16) 39 | self.norm_lin3 = torch.nn.BatchNorm1d(32) 40 | self.lin_3 = torch.nn.Linear(32, 16) 41 | 42 | 43 | self.linear_x = torch.nn.Linear(16, out_dim_x) 44 | self.linear_y = torch.nn.Linear(16, out_dim_y) 45 | self.linear_rot = torch.nn.Linear(16, 4) 46 | 47 | def forward(self, data): 48 | 49 | x = data.x 50 | edge_index = data.edge_index 51 | edge_attr = data.edge_attr 52 | batch = data.batch 53 | 54 | x_encoded = self.graph_embedding(x, edge_index, edge_attr=edge_attr) 55 | x_encoded = F.relu(x_encoded) 56 | x_encoded = self.norm1(x_encoded) 57 | x_encoded = self.graph_embedding2(x_encoded, edge_index, edge_attr=edge_attr) 58 | x_encoded = F.relu(x_encoded) 59 | x_encoded = self.mean_aggr(x_encoded, batch) 60 | 61 | x = self.norm_lin1(x_encoded) 62 | x = self.lin_1(x) 63 | x = F.relu(x) 64 | x = self.norm_lin2(torch.concatenate([x, x_encoded], dim=1)) 65 | x = self.lin_2(x) 66 | x = F.relu(x) 67 | x = self.norm_lin3(torch.concatenate([x, x_encoded], dim=1)) 68 | x = self.lin_3(x) 69 | x = F.relu(x) 70 | 71 | y = self.linear_y(x) 72 | y = F.softmax(y, dim=1) 73 | xx = self.linear_x(x) 74 | xx = F.softmax(xx, dim=1) 75 | rot = self.linear_rot(x) 76 | rot = F.softmax(rot, dim=1) 77 | 78 | return xx, y, rot 79 | -------------------------------------------------------------------------------- /CircuitCaptureEval.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # Script to evaluate the circuit capturing process. 4 | # 5 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 6 | # Johannes Kepler University, Institute for Integrated Circuits 7 | # 8 | # Licensed under the Apache License, Version 2.0 (the "License"); 9 | # you may not use this file except in compliance with the License. 10 | # You may obtain a copy of the License at 11 | # 12 | # http://www.apache.org/licenses/LICENSE-2.0 13 | # 14 | # Unless required by applicable law or agreed to in writing, software 15 | # distributed under the License is distributed on an "AS IS" BASIS, 16 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 17 | # See the License for the specific language governing permissions and 18 | # limitations under the License. 19 | # SPDX-License-Identifier: Apache-2.0 20 | # ======================================================================== 21 | 22 | from SchematicCapture.utils import setup_circuit, include_primitives_hierarchical, get_top_down_topology 23 | from SchematicCapture.RString import include_RStrings_hierarchical 24 | 25 | import matplotlib.pyplot as plt 26 | import networkx as nx 27 | 28 | 29 | #global variables to control the placement 30 | CIRCUIT_FILE = "Circuits/Examples/CCLatch.spice" #Input spice-netlist 31 | CIRCUIT_NAME = "CCLatch" #Name of the circuit 32 | NET_RULES_FILE = None#"NetRules/net_rules.json" #Net-rules definition file 33 | 34 | 35 | #setup the circuit 36 | C = setup_circuit(CIRCUIT_FILE, CIRCUIT_NAME, [], net_rules_file=NET_RULES_FILE) 37 | 38 | topology = get_top_down_topology(C) 39 | 40 | #topology = [(1, C)] 41 | circuit_graphs = [(c, c.get_bipartite_graph()) for t,c in topology] 42 | 43 | #include primitive compositions into the circuit 44 | include_primitives_hierarchical(C) 45 | include_RStrings_hierarchical(C) 46 | 47 | prim_graphs = [(c, c.get_bipartite_graph()) for t,c in topology] 48 | 49 | mygreen = (80/255,160/255,80/255) 50 | myblue = (80/255,80/255,160/255) 51 | 52 | for (circuit, graph) in circuit_graphs: 53 | node_colors = [] 54 | for node_name, node in graph.nodes.items(): 55 | if 'Device' in node: 56 | node_colors.append(myblue) 57 | else: 58 | node_colors.append(mygreen) 59 | 60 | top = nx.bipartite.sets(graph)[0] 61 | pos = nx.bipartite_layout(graph, top, align="horizontal", scale=-0.5) 62 | nx.draw(graph, pos, with_labels=True, node_size=1000, node_color=node_colors, linewidths=5, font_size=10) 63 | plt.savefig(f"{circuit.name}_circ_graph.svg") 64 | plt.show() 65 | 66 | for (circuit, graph) in prim_graphs: 67 | node_colors = [] 68 | for node_name, node in graph.nodes.items(): 69 | if 'Device' in node: 70 | node_colors.append(myblue) 71 | else: 72 | node_colors.append(mygreen) 73 | 74 | top = nx.bipartite.sets(graph)[0] 75 | pos = nx.bipartite_layout(graph, top, align="horizontal", scale=-0.5) 76 | nx.draw(graph, pos, with_labels=True, node_size=1000, node_color=node_colors, linewidths=5, font_size=10) 77 | plt.savefig(f"{circuit.name}_prim_graph.svg") 78 | plt.show() 79 | 80 | -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/CSAmp.sch: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2 2 | } 3 | G {} 4 | K {} 5 | V {} 6 | S {} 7 | E {} 8 | N 540 -370 540 -210 { 9 | lab=Vo} 10 | N 540 -470 540 -430 { 11 | lab=Vdd} 12 | N 400 -400 500 -400 { 13 | lab=Vi} 14 | N 540 -400 620 -400 { 15 | lab=Vdd} 16 | N 620 -450 620 -400 { 17 | lab=Vdd} 18 | N 540 -450 620 -450 { 19 | lab=Vdd} 20 | N 540 -150 540 -90 { 21 | lab=Vss} 22 | N 540 -180 620 -180 { 23 | lab=Vss} 24 | N 620 -180 620 -120 { 25 | lab=Vss} 26 | N 540 -120 620 -120 { 27 | lab=Vss} 28 | N 400 -180 500 -180 { 29 | lab=Vbn} 30 | N 540 -290 720 -290 { 31 | lab=Vo} 32 | N 700 -360 780 -360 { 33 | lab=Vdd} 34 | N 780 -410 780 -360 { 35 | lab=Vdd} 36 | N 700 -410 780 -410 { 37 | lab=Vdd} 38 | N 700 -410 700 -390 { 39 | lab=Vdd} 40 | N 700 -450 700 -410 { 41 | lab=Vdd} 42 | N 620 -450 700 -450 { 43 | lab=Vdd} 44 | N 480 -360 660 -360 { 45 | lab=Vi} 46 | N 480 -400 480 -360 { 47 | lab=Vi} 48 | N 700 -330 700 -290 { 49 | lab=Vo} 50 | N 700 -220 780 -220 { 51 | lab=Vss} 52 | N 780 -220 780 -160 { 53 | lab=Vss} 54 | N 700 -160 780 -160 { 55 | lab=Vss} 56 | N 700 -190 700 -160 { 57 | lab=Vss} 58 | N 700 -160 700 -120 { 59 | lab=Vss} 60 | N 620 -120 700 -120 { 61 | lab=Vss} 62 | N 480 -220 660 -220 { 63 | lab=Vbn} 64 | N 480 -220 480 -180 { 65 | lab=Vbn} 66 | N 700 -290 700 -250 { 67 | lab=Vo} 68 | C {sky130_fd_pr/pfet_01v8.sym} 520 -400 0 0 {name=M1 69 | L=1 70 | W=8 71 | nf=1 72 | mult=1 73 | ad="'int((nf+1)/2) * W/nf * 0.29'" 74 | pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" 75 | as="'int((nf+2)/2) * W/nf * 0.29'" 76 | ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" 77 | nrd="'0.29 / W'" nrs="'0.29 / W'" 78 | sa=0 sb=0 sd=0 79 | model=pfet_01v8 80 | spiceprefix=X 81 | } 82 | C {sky130_fd_pr/nfet_01v8.sym} 520 -180 0 0 {name=M2 83 | L=2 84 | W=10 85 | nf=1 86 | mult=1 87 | ad="'int((nf+1)/2) * W/nf * 0.29'" 88 | pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" 89 | as="'int((nf+2)/2) * W/nf * 0.29'" 90 | ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" 91 | nrd="'0.29 / W'" nrs="'0.29 / W'" 92 | sa=0 sb=0 sd=0 93 | model=nfet_01v8 94 | spiceprefix=X 95 | } 96 | C {devices/ipin.sym} 400 -180 0 0 {name=p5 lab=Vbn} 97 | C {devices/ipin.sym} 400 -400 0 0 {name=p3 lab=Vi} 98 | C {devices/iopin.sym} 540 -470 3 0 {name=p1 lab=Vdd} 99 | C {devices/iopin.sym} 540 -90 3 1 {name=p2 lab=Vss} 100 | C {devices/opin.sym} 720 -290 0 0 {name=p7 lab=Vo} 101 | C {devices/title.sym} 160 0 0 0 {name=l1 author="Jakob Ratschenberger"} 102 | C {sky130_fd_pr/pfet_01v8.sym} 680 -360 0 0 {name=M3 103 | L=1 104 | W=8 105 | nf=1 106 | mult=1 107 | ad="'int((nf+1)/2) * W/nf * 0.29'" 108 | pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" 109 | as="'int((nf+2)/2) * W/nf * 0.29'" 110 | ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" 111 | nrd="'0.29 / W'" nrs="'0.29 / W'" 112 | sa=0 sb=0 sd=0 113 | model=pfet_01v8 114 | spiceprefix=X 115 | } 116 | C {sky130_fd_pr/nfet_01v8.sym} 680 -220 0 0 {name=M4 117 | L=2 118 | W=10 119 | nf=1 120 | mult=1 121 | ad="'int((nf+1)/2) * W/nf * 0.29'" 122 | pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" 123 | as="'int((nf+2)/2) * W/nf * 0.29'" 124 | ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" 125 | nrd="'0.29 / W'" nrs="'0.29 / W'" 126 | sa=0 sb=0 sd=0 127 | model=nfet_01v8 128 | spiceprefix=X 129 | } 130 | -------------------------------------------------------------------------------- /PPO/utils.py: -------------------------------------------------------------------------------- 1 | # MIT License 2 | # 3 | # Copyright (c) 2022 Eric Yang Yu 4 | # 5 | # Copyright (c) 2023 Jakob Ratschenberger 6 | # 7 | # Modifications: 8 | # - Modified train() to use a placement-environment and to define the total number of placements 9 | # 10 | # Permission is hereby granted, free of charge, to any person obtaining a copy 11 | # of this software and associated documentation files (the "Software"), to deal 12 | # in the Software without restriction, including without limitation the rights 13 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 | # copies of the Software, and to permit persons to whom the Software is 15 | # furnished to do so, subject to the following conditions: 16 | # 17 | # The above copyright notice and this permission notice shall be included in all 18 | # copies or substantial portions of the Software. 19 | # 20 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 23 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 26 | # SOFTWARE. 27 | 28 | from __future__ import annotations 29 | from typing import TYPE_CHECKING 30 | if TYPE_CHECKING: 31 | from Environment.Environment import Placement 32 | 33 | import matplotlib.pyplot as plt 34 | import torch 35 | import sys 36 | import numpy as np 37 | 38 | from PPO.Placement_PPO import Placement_PPO 39 | from Network.D2RL_Actor import D2RL_Actor 40 | 41 | 42 | def train(env : Placement, hyperparameters : dict, actor_model : str = '', critic_model : str = '', total_placements=200e6): 43 | """Train a policy network to learn placing cells. 44 | 45 | Args: 46 | env (Placement): Placement environment. 47 | hyperparameters (dict): Hyperparameters of the PPO algorithm. 48 | actor_model (str, optional): Weights-file of the actor-model. Defaults to ''. 49 | critic_model (str, optional): Weights-file of the critic-model. Defaults to '': 50 | total_placements (int, optional): Number of total-placements which shall be performed. Defaults to 200e6. 51 | """ 52 | print(f"Training", flush=True) 53 | #setup a model to train the policy 54 | model = Placement_PPO(env, hyperparameters) 55 | 56 | if actor_model != '' and critic_model != '': 57 | print(f"Loading in {actor_model} and {critic_model}...", flush=True) 58 | model.actor.load_state_dict(torch.load(actor_model)) 59 | model.critic.load_state_dict(torch.load(critic_model)) 60 | print(f"Successfully loaded.", flush=True) 61 | elif actor_model != '' or critic_model != '': # Don't train from scratch if user accidentally forgets actor/critic model 62 | print(f"Error: Either specify both actor/critic models or none at all. We don't want to accidentally override anything!") 63 | sys.exit(0) 64 | else: 65 | print(f"Training from scratch.", flush=True) 66 | 67 | #learn to place 68 | model.learn(total_placements=total_placements) 69 | -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/MillerOpAmp.sch: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2 2 | } 3 | G {} 4 | K {} 5 | V {} 6 | S {} 7 | E {} 8 | N 1010 -500 1070 -500 { 9 | lab=Von} 10 | N 1010 -320 1060 -320 { 11 | lab=Vop} 12 | N 170 -440 270 -440 { 13 | lab=Vp} 14 | N 170 -420 270 -420 { 15 | lab=Vn} 16 | N 170 -400 270 -400 { 17 | lab=Vbdan} 18 | N 290 -280 290 -220 { 19 | lab=von1} 20 | N 290 -160 290 -100 { 21 | lab=Von} 22 | N 470 -280 470 -220 { 23 | lab=vop1} 24 | N 470 -160 470 -100 { 25 | lab=Vop} 26 | N 170 -80 260 -80 { 27 | lab=VGND} 28 | N 250 -460 270 -460 { 29 | lab=Vbdap} 30 | N 170 -460 250 -460 { 31 | lab=Vbdap} 32 | N 570 -440 650 -440 { 33 | lab=von1} 34 | N 650 -520 650 -440 { 35 | lab=von1} 36 | N 650 -520 710 -520 { 37 | lab=von1} 38 | N 570 -420 650 -420 { 39 | lab=vop1} 40 | N 650 -420 650 -340 { 41 | lab=vop1} 42 | N 650 -340 710 -340 { 43 | lab=vop1} 44 | N 690 -500 710 -500 { 45 | lab=Vbcsn} 46 | N 690 -500 690 -320 { 47 | lab=Vbcsn} 48 | N 690 -320 710 -320 { 49 | lab=Vbcsn} 50 | N 170 -320 690 -320 { 51 | lab=Vbcsn} 52 | N 170 -580 590 -580 { 53 | lab=VPWR} 54 | N 590 -580 590 -460 { 55 | lab=VPWR} 56 | N 570 -460 590 -460 { 57 | lab=VPWR} 58 | N 590 -580 1030 -580 { 59 | lab=VPWR} 60 | N 1030 -580 1030 -520 { 61 | lab=VPWR} 62 | N 1010 -520 1030 -520 { 63 | lab=VPWR} 64 | N 1030 -520 1030 -340 { 65 | lab=VPWR} 66 | N 1010 -340 1030 -340 { 67 | lab=VPWR} 68 | N 260 -80 1020 -80 { 69 | lab=VGND} 70 | N 1020 -300 1020 -80 { 71 | lab=VGND} 72 | N 1010 -300 1020 -300 { 73 | lab=VGND} 74 | N 1020 -480 1020 -300 { 75 | lab=VGND} 76 | N 1010 -480 1020 -480 { 77 | lab=VGND} 78 | N 570 -400 590 -400 { 79 | lab=VGND} 80 | N 590 -400 590 -80 { 81 | lab=VGND} 82 | N 1060 -320 1070 -320 { 83 | lab=Vop} 84 | C {sky130_fd_pr/cap_mim_m3_1.sym} 290 -190 0 0 {name=C1 model=cap_mim_m3_1 W=4 L=4 MF=1 spiceprefix=X} 85 | C {sky130_fd_pr/cap_mim_m3_1.sym} 470 -190 0 0 {name=C2 model=cap_mim_m3_1 W=4 L=4 MF=1 spiceprefix=X} 86 | C {devices/opin.sym} 1070 -500 0 0 {name=p1 lab=Von} 87 | C {devices/opin.sym} 1070 -320 0 0 {name=p2 lab=Vop} 88 | C {devices/lab_wire.sym} 650 -520 0 0 {name=p3 sig_type=std_logic lab=von1} 89 | C {devices/lab_wire.sym} 290 -280 0 0 {name=p5 sig_type=std_logic lab=von1} 90 | C {devices/lab_wire.sym} 470 -280 0 0 {name=p6 sig_type=std_logic lab=vop1} 91 | C {devices/lab_wire.sym} 470 -100 0 0 {name=p7 sig_type=std_logic lab=Vop} 92 | C {devices/lab_wire.sym} 290 -100 0 0 {name=p8 sig_type=std_logic lab=Von} 93 | C {devices/ipin.sym} 170 -320 0 0 {name=p9 lab=Vbcsn} 94 | C {devices/ipin.sym} 170 -440 0 0 {name=p10 lab=Vp} 95 | C {devices/ipin.sym} 170 -420 0 0 {name=p11 lab=Vn} 96 | C {devices/ipin.sym} 170 -400 0 0 {name=p12 lab=Vbdan} 97 | C {devices/iopin.sym} 170 -580 2 0 {name=p13 lab=VPWR} 98 | C {devices/iopin.sym} 170 -80 2 0 {name=p14 lab=VGND} 99 | C {devices/ipin.sym} 170 -460 0 0 {name=p15 lab=Vbdap} 100 | C {devices/lab_wire.sym} 650 -340 0 0 {name=p16 sig_type=std_logic lab=vop1} 101 | C {devices/title.sym} 160 0 0 0 {name=l1 author="Jakob Ratschenberger"} 102 | C {/home/jakob/Documents/RALF/Circuits/Examples/OpAmp/DiffAmp.sym} 420 -430 0 0 {name=x1} 103 | C {/home/jakob/Documents/RALF/Circuits/Examples/OpAmp/CSAmp.sym} 860 -500 0 0 {name=x2} 104 | C {/home/jakob/Documents/RALF/Circuits/Examples/OpAmp/CSAmp.sym} 860 -320 0 0 {name=x3} 105 | -------------------------------------------------------------------------------- /rectangle_packing_solver/floorplan.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Kotaro Terada 2 | # 3 | # Copyright 2023 Jakob Ratschenberger 4 | # 5 | # Modifications: 6 | # - Modified __init__() to get the floorplan of a placed circuit 7 | # - Modified __repr__() to show the HPWL 8 | # 9 | # Licensed under the Apache License, Version 2.0 (the "License"); 10 | # you may not use this file except in compliance with the License. 11 | # You may obtain a copy of the License at 12 | # 13 | # http://www.apache.org/licenses/LICENSE-2.0 14 | # 15 | # Unless required by applicable law or agreed to in writing, software 16 | # distributed under the License is distributed on an "AS IS" BASIS, 17 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 18 | # See the License for the specific language governing permissions and 19 | # limitations under the License. 20 | 21 | from __future__ import annotations 22 | from typing import Dict, List, Tuple, Union, TYPE_CHECKING 23 | 24 | if TYPE_CHECKING: 25 | from SchematicCapture.Devices import Device 26 | from SchematicCapture.Net import Net 27 | 28 | from .cell_sliding import cell_slide3 29 | from .problem import Problem 30 | 31 | class Floorplan: 32 | """ 33 | A class to represent a rectangle packing floorplan. 34 | """ 35 | 36 | def __init__(self, positions: List[Dict], bounding_box: Tuple, problem : Problem, area: Union[int, float] = -1.0) -> None: 37 | self.positions = positions 38 | self.problem = problem 39 | 40 | circuit = problem.circuit 41 | rudy = problem.rudy 42 | 43 | #place the devices of the circuit 44 | for pos in positions: 45 | device_name = self.problem.id_to_device(pos['id']) 46 | device : Device 47 | device = circuit.devices[device_name] 48 | x = pos['x'] 49 | y = pos['y'] 50 | w = pos["width"] 51 | h = pos["height"] 52 | r = pos["rotation"] 53 | device.cell.reset_place() 54 | device.cell.place((x+w//2, y+h//2), (r%4)*90) 55 | 56 | #slide the cells, such that there are no violated placement-rules 57 | cell_list = [device.cell for device in circuit.devices.values()] 58 | cell_slide3(cells=cell_list) 59 | 60 | self.bounding_box = bounding_box 61 | if 0 < area: 62 | self.area = area 63 | else: 64 | self.area = bounding_box[0] * bounding_box[1] 65 | 66 | #calculate the HPWL of the placement 67 | self.HPWL = 0 68 | for net_name, net in circuit._nets.items(): 69 | net : Net 70 | self.HPWL += net.HPWL() 71 | 72 | #calculate the estimated congestion of the placement 73 | self.congestion = 0 74 | rudy.clear_nets() 75 | for net in circuit._nets.values(): 76 | rudy.add_net(net) 77 | 78 | self.congestion = rudy.congestion() 79 | 80 | def __repr__(self) -> str: 81 | s = "Floorplan({" 82 | s += "'positions': " + str(self.positions) + ", " 83 | s += "'bounding_box': " + str(self.bounding_box) + ", " 84 | s += "'area': " + str(self.area) + ", " 85 | s += "'HPWL: '" + str(round(self.HPWL,2)) + ", " 86 | s += "'congestion: '" + str(round(self.congestion,2)) + "})" 87 | 88 | return s 89 | -------------------------------------------------------------------------------- /Rules/NetRules.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 4 | # Johannes Kepler University, Institute for Integrated Circuits 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # SPDX-License-Identifier: Apache-2.0 18 | # ======================================================================== 19 | 20 | from __future__ import annotations 21 | 22 | from typing import TYPE_CHECKING 23 | 24 | from SchematicCapture.Net import Net 25 | 26 | if TYPE_CHECKING: 27 | from Magic.Cell import Cell 28 | from Magic.MacroCell import MacroCell 29 | from PDK.Layers import Layer 30 | from SchematicCapture.Net import Net 31 | from Magic.MagicLayer import Rectangle 32 | 33 | import abc 34 | from Rules.Rule import Rule 35 | 36 | 37 | class NetRule(Rule, metaclass = abc.ABCMeta): 38 | """ 39 | A NetRule gets applied on a specific net. E.g. minimum wire-width of an net. 40 | """ 41 | def __init__(self, *, net : Net, name: str) -> None: 42 | super().__init__(name=name) 43 | self._net = net 44 | self._net.add_rule(self) #add the rule to the net 45 | 46 | @property 47 | def net(self) -> Net: 48 | """Get the net of the rule. 49 | 50 | Returns: 51 | Net: Net of the rule. 52 | """ 53 | return self._net 54 | 55 | class MinNetWireWidth(NetRule): 56 | """Define a minimum wire-width for a net. 57 | """ 58 | def __init__(self, *, net: Net, min_width : float) -> None: 59 | name = f"{self.__class__.__name__}({net.name}, {round(min_width,2)})" 60 | super().__init__(net=net, name=name) 61 | self._min_width = min_width 62 | 63 | @property 64 | def min_width(self) -> float: 65 | """Get the minimum width of the net. 66 | 67 | Returns: 68 | float: Minimum width of the net. 69 | """ 70 | return self._min_width 71 | 72 | class Port(NetRule): 73 | """Set a net as a port. 74 | """ 75 | def __init__(self, *, net: Net) -> None: 76 | name = f"{self.__class__.__name__}({net.name})" 77 | super().__init__(net=net, name=name) 78 | 79 | class Ports: 80 | """Set for multiple nets ports. 81 | """ 82 | def __init__(self, *, nets: list[Net]) -> None: 83 | for net in nets: 84 | Port(net=net) 85 | 86 | class PowerNet(NetRule): 87 | """Define a net as a power net. E.g. Vdd, Vss, VGND, ... 88 | """ 89 | def __init__(self, *, net: Net) -> None: 90 | name = f"{self.__class__.__name__}({net.name})" 91 | super().__init__(net=net, name=name) 92 | 93 | class PowerNets: 94 | """Define multiple nets as power nets. 95 | """ 96 | def __init__(self, *, nets: list[Net]) -> None: 97 | for net in nets: 98 | PowerNet(net=net) -------------------------------------------------------------------------------- /rectangle_packing_placement/rectangle_packing_solver/visualizer.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Kotaro Terada 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | from typing import Tuple 16 | 17 | import matplotlib.patches as patches 18 | from matplotlib import pylab as plt 19 | 20 | from .solution import Solution 21 | 22 | 23 | class Visualizer: 24 | """ 25 | A floorplan visualizer. 26 | """ 27 | 28 | def __init__(self) -> None: 29 | # Default font size is 12 30 | plt.rcParams["font.size"] = 14 31 | 32 | def visualize(self, solution: Solution, path: str = "floorplan.png", title: str = "Floorplan") -> None: 33 | if not isinstance(solution, Solution): 34 | raise TypeError("Invalid argument: 'solution' must be an instance of Solution.") 35 | 36 | positions = solution.floorplan.positions 37 | bounding_box = solution.floorplan.bounding_box 38 | 39 | # Figure settings 40 | bb_width = bounding_box[0] 41 | bb_height = bounding_box[1] 42 | fig = plt.figure(figsize=(10, 10 * bb_height / bb_width + 0.5)) 43 | ax = plt.axes() 44 | ax.set_aspect("equal") 45 | plt.xlim([0, bb_width]) 46 | plt.ylim([0, bb_height]) 47 | plt.xlabel("X") 48 | plt.ylabel("Y") 49 | plt.title(title) 50 | 51 | # Plot every rectangle 52 | for i, rectangle in enumerate(positions): 53 | color, fontcolor = self.get_color(i) 54 | r = patches.Rectangle( 55 | xy=(rectangle["x"], rectangle["y"]), 56 | width=rectangle["width"], 57 | height=rectangle["height"], 58 | edgecolor="#000000", 59 | facecolor=color, 60 | alpha=1.0, 61 | fill=True, 62 | ) 63 | ax.add_patch(r) 64 | 65 | # Add text label 66 | centering_offset = 0.011 67 | center_x = rectangle["x"] + rectangle["width"] / 2 - bb_width * centering_offset 68 | center_y = rectangle["y"] + rectangle["height"] / 2 - bb_height * centering_offset 69 | ax.text(x=center_x, y=center_y, s=rectangle["id"], fontsize=18, color=fontcolor) 70 | 71 | # Output 72 | if path is None: 73 | plt.show() 74 | else: 75 | fig.savefig(path) 76 | 77 | plt.close() 78 | 79 | @classmethod 80 | def get_color(cls, i: int = 0) -> Tuple[str, str]: 81 | """ 82 | Gets rectangle face color (and its font color) from matplotlib cmap. 83 | """ 84 | cmap = plt.get_cmap("tab10") 85 | color = cmap(i % cmap.N) 86 | brightness = max(color[0], color[1], color[2]) 87 | 88 | if 0.85 < brightness: 89 | fontcolor = "#000000" 90 | else: 91 | fontcolor = "#ffffff" 92 | 93 | return (color, fontcolor) 94 | -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/MillerOpAmp.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/MillerOpAmp/MillerOpAmp.sch 2 | **.subckt MillerOpAmp Von Vop Vbias2 Vp Vn Vbias1 VPWR VGND 3 | *.opin Von 4 | *.opin Vop 5 | *.ipin Vbias2 6 | *.ipin Vp 7 | *.ipin Vn 8 | *.ipin Vbias1 9 | *.iopin VPWR 10 | *.iopin VGND 11 | x1 VPWR Vbias2 Von1 Vop1 Vp Vn Vbias1 VGND DiffAmp 12 | x2 VPWR Von1 Von Vbias1 VGND CSAmp 13 | x3 VPWR Vop1 Vop Vbias1 VGND CSAmp 14 | XC1 Von1 Von sky130_fd_pr__cap_mim_m3_1 W=5 L=5 MF=1 m=1 15 | XC2 Vop1 Vop sky130_fd_pr__cap_mim_m3_1 W=5 L=5 MF=1 m=1 16 | **.ends 17 | 18 | * expanding symbol: 19 | *+ /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/MillerOpAmp/DiffAmp.sym # of pins=8 20 | ** sym_path: /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/MillerOpAmp/DiffAmp.sym 21 | ** sch_path: /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/MillerOpAmp/DiffAmp.sch 22 | .subckt DiffAmp Vdd Vbias2 Von Vop Vp Vn Vbias1 Vss 23 | *.iopin Vdd 24 | *.iopin Vss 25 | *.ipin Vp 26 | *.ipin Vn 27 | *.ipin Vbias1 28 | *.ipin Vbias2 29 | *.opin Vop 30 | *.opin Von 31 | XM1 Vop Vp Vmid Vss sky130_fd_pr__nfet_01v8 L=1 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 32 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 33 | + sa=0 sb=0 sd=0 mult=1 m=1 34 | XM2 Von Vn Vmid Vss sky130_fd_pr__nfet_01v8 L=1 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 35 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 36 | + sa=0 sb=0 sd=0 mult=1 m=1 37 | XM3 Vop Vbias2 Vdd Vdd sky130_fd_pr__pfet_01v8 L=1 W=2 nf=2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 38 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 39 | + sa=0 sb=0 sd=0 mult=1 m=1 40 | XM4 Von Vbias2 Vdd Vdd sky130_fd_pr__pfet_01v8 L=1 W=2 nf=2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 41 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 42 | + sa=0 sb=0 sd=0 mult=1 m=1 43 | XM5 Vmid Vbias1 Vss Vss sky130_fd_pr__nfet_01v8 L=2 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 44 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 45 | + sa=0 sb=0 sd=0 mult=1 m=1 46 | .ends 47 | 48 | 49 | * expanding symbol: 50 | *+ /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/MillerOpAmp/CSAmp.sym # of pins=5 51 | ** sym_path: /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/MillerOpAmp/CSAmp.sym 52 | ** sch_path: /home/jakob/Documents/AutomatedLayoutGeneration/Circuits/MillerOpAmp/CSAmp.sch 53 | .subckt CSAmp Vdd Vi Vo Vbias1 Vss 54 | *.ipin Vbias1 55 | *.ipin Vi 56 | *.iopin Vdd 57 | *.iopin Vss 58 | *.opin Vo 59 | XM1 Vo Vi Vdd Vdd sky130_fd_pr__pfet_01v8 L=1 W=4 nf=2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 60 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 61 | + sa=0 sb=0 sd=0 mult=1 m=1 62 | XM2 Vo Vbias1 Vss Vss sky130_fd_pr__nfet_01v8 L=2 W=8 nf=4 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' 63 | + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' 64 | + sa=0 sb=0 sd=0 mult=1 m=1 65 | .ends 66 | 67 | .end -------------------------------------------------------------------------------- /rectangle_packing_solver/visualizer.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Kotaro Terada 2 | # 3 | # Licensed under the Apache License, Version 2.0 (the "License"); 4 | # you may not use this file except in compliance with the License. 5 | # You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | # Unless required by applicable law or agreed to in writing, software 10 | # distributed under the License is distributed on an "AS IS" BASIS, 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | # See the License for the specific language governing permissions and 13 | # limitations under the License. 14 | 15 | from typing import Tuple 16 | 17 | import matplotlib.patches as patches 18 | from matplotlib import pylab as plt 19 | 20 | from .solution import Solution 21 | 22 | 23 | class Visualizer: 24 | """ 25 | A floorplan visualizer. 26 | """ 27 | 28 | def __init__(self) -> None: 29 | # Default font size is 12 30 | plt.rcParams["font.size"] = 14 31 | 32 | def visualize(self, solution: Solution, path: str = "floorplan.png", title: str = "Floorplan") -> None: 33 | if not isinstance(solution, Solution): 34 | raise TypeError("Invalid argument: 'solution' must be an instance of Solution.") 35 | 36 | positions = solution.floorplan.positions 37 | bounding_box = solution.floorplan.bounding_box 38 | problem = solution.problem 39 | 40 | # Figure settings 41 | bb_width = bounding_box[0] 42 | bb_height = bounding_box[1] 43 | fig = plt.figure(figsize=(10, 10 * bb_height / bb_width + 0.5)) 44 | ax = plt.axes() 45 | ax.set_aspect("equal") 46 | plt.xlim([0, bb_width]) 47 | plt.ylim([0, bb_height]) 48 | plt.xlabel("X") 49 | plt.ylabel("Y") 50 | plt.title(title) 51 | 52 | # Plot every rectangle 53 | for i, rectangle in enumerate(positions): 54 | color, fontcolor = self.get_color(i) 55 | r = patches.Rectangle( 56 | xy=(rectangle["x"], rectangle["y"]), 57 | width=rectangle["width"], 58 | height=rectangle["height"], 59 | edgecolor="#000000", 60 | facecolor=color, 61 | alpha=1.0, 62 | fill=True, 63 | ) 64 | ax.add_patch(r) 65 | 66 | # Add text label 67 | centering_offset = 0.011 68 | center_x = rectangle["x"] + rectangle["width"] / 2 - bb_width * centering_offset 69 | center_y = rectangle["y"] + rectangle["height"] / 2 - bb_height * centering_offset 70 | ax.text(x=center_x, y=center_y, s=problem.id_to_device(rectangle["id"]), fontsize=18, color=fontcolor) 71 | 72 | # Output 73 | if path is None: 74 | plt.show() 75 | else: 76 | fig.savefig(path) 77 | 78 | plt.close() 79 | 80 | @classmethod 81 | def get_color(cls, i: int = 0) -> Tuple[str, str]: 82 | """ 83 | Gets rectangle face color (and its font color) from matplotlib cmap. 84 | """ 85 | cmap = plt.get_cmap("tab10") 86 | color = cmap(i % cmap.N) 87 | brightness = max(color[0], color[1], color[2]) 88 | 89 | if 0.85 < brightness: 90 | fontcolor = "#000000" 91 | else: 92 | fontcolor = "#ffffff" 93 | 94 | return (color, fontcolor) 95 | -------------------------------------------------------------------------------- /Circuits/Examples/OpAmp/Bias.sch: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2 2 | } 3 | G {} 4 | K {} 5 | V {} 6 | S {} 7 | E {} 8 | N 40 -50 40 0 { 9 | lab=Vss} 10 | N 40 -80 110 -80 { 11 | lab=Vss} 12 | N 110 -80 110 -20 { 13 | lab=Vss} 14 | N 40 -20 110 -20 { 15 | lab=Vss} 16 | N 40 -160 40 -110 { 17 | lab=Vbias} 18 | N -70 -80 0 -80 { 19 | lab=Vbias} 20 | N -70 -140 -70 -80 { 21 | lab=Vbias} 22 | N -70 -140 40 -140 { 23 | lab=Vbias} 24 | N 40 -520 40 -460 { 25 | lab=Vdd} 26 | N 40 -400 40 -370 { 27 | lab=VbiasP} 28 | N -20 -430 0 -430 { 29 | lab=VbiasP} 30 | N -20 -430 -20 -380 { 31 | lab=VbiasP} 32 | N -20 -380 40 -380 { 33 | lab=VbiasP} 34 | N 40 -430 80 -430 { 35 | lab=Vdd} 36 | N 80 -490 80 -430 { 37 | lab=Vdd} 38 | N 40 -490 80 -490 { 39 | lab=Vdd} 40 | N 40 -310 40 -270 { 41 | lab=VbiasP} 42 | N 40 -210 40 -160 { 43 | lab=Vbias} 44 | N 40 -370 40 -310 { 45 | lab=VbiasP} 46 | N 210 -330 230 -330 { 47 | lab=#net1} 48 | N 290 -330 320 -330 { 49 | lab=#net2} 50 | N 380 -330 400 -330 { 51 | lab=#net3} 52 | N 460 -330 480 -330 { 53 | lab=#net4} 54 | N 540 -330 580 -330 { 55 | lab=Vbias} 56 | N 120 -330 150 -330 { 57 | lab=VbiasP} 58 | N 180 -380 180 -350 { 59 | lab=Vss} 60 | N 180 -380 510 -380 { 61 | lab=Vss} 62 | N 510 -380 510 -350 { 63 | lab=Vss} 64 | N 430 -380 430 -350 { 65 | lab=Vss} 66 | N 350 -380 350 -350 { 67 | lab=Vss} 68 | N 260 -380 260 -350 { 69 | lab=Vss} 70 | N 350 -400 350 -380 { 71 | lab=Vss} 72 | N 40 -170 240 -170 { 73 | lab=Vbias} 74 | C {sky130_fd_pr/nfet_01v8.sym} 20 -80 0 0 {name=M6 75 | L=2 76 | W=1 77 | nf=1 78 | mult=1 79 | ad="'int((nf+1)/2) * W/nf * 0.29'" 80 | pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" 81 | as="'int((nf+2)/2) * W/nf * 0.29'" 82 | ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" 83 | nrd="'0.29 / W'" nrs="'0.29 / W'" 84 | sa=0 sb=0 sd=0 85 | model=nfet_01v8 86 | spiceprefix=X 87 | } 88 | C {devices/lab_wire.sym} 40 -210 0 0 {name=p5 sig_type=std_logic lab=Vbias} 89 | C {sky130_fd_pr/pfet_01v8.sym} 20 -430 0 0 {name=M2 90 | L=2 91 | W=1 92 | nf=1 93 | mult=1 94 | ad="'int((nf+1)/2) * W/nf * 0.29'" 95 | pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" 96 | as="'int((nf+2)/2) * W/nf * 0.29'" 97 | ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" 98 | nrd="'0.29 / W'" nrs="'0.29 / W'" 99 | sa=0 sb=0 sd=0 100 | model=pfet_01v8 101 | spiceprefix=X 102 | } 103 | C {devices/lab_wire.sym} 40 -270 0 0 {name=p18 sig_type=std_logic lab=VbiasP} 104 | C {sky130_fd_pr/res_xhigh_po_0p35.sym} 180 -330 1 0 {name=R1 105 | L=2 106 | model=res_xhigh_po_0p35 107 | spiceprefix=X 108 | mult=1} 109 | C {sky130_fd_pr/res_xhigh_po_0p35.sym} 260 -330 1 0 {name=R2 110 | L=2 111 | model=res_xhigh_po_0p35 112 | spiceprefix=X 113 | mult=1} 114 | C {sky130_fd_pr/res_xhigh_po_0p35.sym} 350 -330 1 0 {name=R3 115 | L=2 116 | model=res_xhigh_po_0p35 117 | spiceprefix=X 118 | mult=1} 119 | C {sky130_fd_pr/res_xhigh_po_0p35.sym} 430 -330 1 0 {name=R4 120 | L=2 121 | model=res_xhigh_po_0p35 122 | spiceprefix=X 123 | mult=1} 124 | C {sky130_fd_pr/res_xhigh_po_0p35.sym} 510 -330 1 0 {name=R5 125 | L=2 126 | model=res_xhigh_po_0p35 127 | spiceprefix=X 128 | mult=1} 129 | C {devices/lab_wire.sym} 120 -330 0 0 {name=p10 sig_type=std_logic lab=VbiasP} 130 | C {devices/lab_wire.sym} 580 -330 0 1 {name=p19 sig_type=std_logic lab=Vbias} 131 | C {devices/opin.sym} 240 -170 0 0 {name=p1 sig_type=std_logic lab=Vbias} 132 | C {devices/iopin.sym} 40 0 1 0 {name=p2 lab=Vss} 133 | C {devices/iopin.sym} 40 -520 3 0 {name=p3 lab=Vdd} 134 | C {devices/lab_wire.sym} 350 -400 0 1 {name=p4 sig_type=std_logic lab=Vss} 135 | -------------------------------------------------------------------------------- /main_routing.py: -------------------------------------------------------------------------------- 1 | # ======================================================================== 2 | # 3 | # Script to route a already placed circuit. 4 | # 5 | # SPDX-FileCopyrightText: 2023 Jakob Ratschenberger 6 | # Johannes Kepler University, Institute for Integrated Circuits 7 | # 8 | # Licensed under the Apache License, Version 2.0 (the "License"); 9 | # you may not use this file except in compliance with the License. 10 | # You may obtain a copy of the License at 11 | # 12 | # http://www.apache.org/licenses/LICENSE-2.0 13 | # 14 | # Unless required by applicable law or agreed to in writing, software 15 | # distributed under the License is distributed on an "AS IS" BASIS, 16 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 17 | # See the License for the specific language governing permissions and 18 | # limitations under the License. 19 | # SPDX-License-Identifier: Apache-2.0 20 | # ======================================================================== 21 | 22 | from __future__ import annotations 23 | from typing import TYPE_CHECKING 24 | if TYPE_CHECKING: 25 | from SchematicCapture.Circuit import Circuit 26 | from Magic.MagicDie import MagicDie 27 | 28 | import faulthandler 29 | faulthandler.enable() 30 | 31 | import pickle 32 | from Routing_v2.Obstacles import DieObstacles 33 | from Routing_v2.utils import route 34 | 35 | import time 36 | import matplotlib.pyplot as plt 37 | 38 | from PDK.PDK import global_pdk 39 | 40 | ######################################################################### 41 | 42 | CIRCUIT_NAME = "DiffAmp" #Name of the circuit 43 | 44 | PLAN_WIRES = True #If True, before detail-routing, wire-planning (global-routing) will be performed 45 | N_PLANNING_ITERATIONS = 15 #Number of wire-planning iterations 46 | GCELL_LENGTH = 150 #Length of a wire-planning cell (in units of lambda) 47 | LAYERS = ['m1','m2','m3','m4'] #Layers which will be used for wire-planning 48 | 49 | SHOW_STATS = True #If True, statistics of the routing will be printed 50 | DESTINATION_PATH = 'Magic/Routing/' #Destination path of the routing file 51 | PLOT_RESULT = False #If True, the result will be plotted 52 | LOG_WIREPLAN = False #If True, the stats of the wire-planning iterations will be logged to a csv file 53 | 54 | ######################################################################### 55 | 56 | 57 | #load the placed circuit 58 | file = open(f"PlacementCircuits/{CIRCUIT_NAME}_placement.pkl", 'rb') 59 | die : MagicDie 60 | die = pickle.load(file) 61 | file.close() 62 | 63 | #setup obstacles from the die 64 | die_obstacles = DieObstacles(die) 65 | 66 | #get the placed circuit 67 | circuit = die.circuit 68 | 69 | #setup a axis for plotting 70 | if PLOT_RESULT: 71 | fig, ax = plt.subplots(1) 72 | ax.set_aspect('equal') 73 | ax.plot() 74 | cm = plt.get_cmap('Set1') 75 | for layer in global_pdk.metal_layers.values(): 76 | color = cm(hash(layer)%9) 77 | ax.plot([], color=color, label=str(layer), linewidth=10, alpha=0.5) 78 | fig.legend(loc='right') 79 | else: 80 | ax = None 81 | 82 | start = time.time() 83 | #route the circuit 84 | route(circuit=circuit, routing_name=CIRCUIT_NAME, plan_wires=PLAN_WIRES, 85 | planning_iterations=N_PLANNING_ITERATIONS, gcell_length=GCELL_LENGTH, use_layers=LAYERS, 86 | destination_path=DESTINATION_PATH, show_stats=SHOW_STATS, ax=ax, log_wireplan=LOG_WIREPLAN) 87 | 88 | print(f"Took {round((time.time()-start)*1e3,2)}ms") 89 | 90 | if PLOT_RESULT: 91 | plt.show() -------------------------------------------------------------------------------- /Circuits/Examples/InvAmp/InvAmp.sch: -------------------------------------------------------------------------------- 1 | v {xschem version=3.4.1 file_version=1.2 2 | } 3 | G {} 4 | K {} 5 | V {} 6 | S {} 7 | E {} 8 | N 440 -460 540 -460 { 9 | lab=vp} 10 | N 600 -460 640 -460 { 11 | lab=v1} 12 | N 700 -460 860 -460 { 13 | lab=Von} 14 | N 860 -460 860 -340 { 15 | lab=Von} 16 | N 600 -180 640 -180 { 17 | lab=v2} 18 | N 360 -260 440 -260 { 19 | lab=vn} 20 | N 440 -260 440 -180 { 21 | lab=vn} 22 | N 440 -180 540 -180 { 23 | lab=vn} 24 | N 440 -300 500 -300 { 25 | lab=vn} 26 | N 440 -300 440 -260 { 27 | lab=vn} 28 | N 360 -360 440 -360 { 29 | lab=vp} 30 | N 440 -360 440 -320 { 31 | lab=vp} 32 | N 440 -320 500 -320 { 33 | lab=vp} 34 | N 440 -460 440 -360 { 35 | lab=vp} 36 | N 800 -300 860 -300 { 37 | lab=Von} 38 | N 800 -320 840 -320 { 39 | lab=Vop} 40 | N 840 -320 840 -180 { 41 | lab=Vop} 42 | N 700 -180 840 -180 { 43 | lab=Vop} 44 | N 800 -280 820 -280 { 45 | lab=VGND} 46 | N 820 -280 820 -100 { 47 | lab=VGND} 48 | N 570 -200 670 -200 { 49 | lab=VGND} 50 | N 670 -200 820 -200 { 51 | lab=VGND} 52 | N 330 -340 330 -280 { 53 | lab=VGND} 54 | N 330 -310 370 -310 { 55 | lab=VGND} 56 | N 480 -340 500 -340 { 57 | lab=Vcmref} 58 | N 480 -520 480 -340 { 59 | lab=Vcmref} 60 | N 300 -520 480 -520 { 61 | lab=Vcmref} 62 | N 570 -440 670 -440 { 63 | lab=VGND} 64 | N 670 -440 820 -440 { 65 | lab=VGND} 66 | N 820 -440 820 -280 { 67 | lab=VGND} 68 | N 800 -580 800 -340 { 69 | lab=VPWR} 70 | N 300 -580 800 -580 { 71 | lab=VPWR} 72 | N 280 -360 300 -360 { 73 | lab=Vin} 74 | N 280 -260 300 -260 { 75 | lab=Vip} 76 | N 820 -100 820 -60 { 77 | lab=VGND} 78 | N 280 -60 820 -60 { 79 | lab=VGND} 80 | N 280 -520 300 -520 { 81 | lab=Vcmref} 82 | N 280 -580 300 -580 { 83 | lab=VPWR} 84 | N 840 -320 900 -320 { 85 | lab=Vop} 86 | N 860 -340 860 -300 { 87 | lab=Von} 88 | N 860 -300 900 -300 { 89 | lab=Von} 90 | C {/home/jakob/Documents/RALF/Circuits/Examples/OpAmp/OpAmp.sym} 650 -310 0 0 {name=x1} 91 | C {sky130_fd_pr/res_xhigh_po_0p35.sym} 330 -360 3 0 {name=R1 92 | L=1.75 93 | model=res_xhigh_po_0p35 94 | spiceprefix=X 95 | mult=1} 96 | C {sky130_fd_pr/res_xhigh_po_0p35.sym} 570 -460 3 0 {name=R2 97 | L=1.75 98 | model=res_xhigh_po_0p35 99 | spiceprefix=X 100 | mult=1} 101 | C {sky130_fd_pr/res_xhigh_po_0p35.sym} 670 -460 3 0 {name=R3 102 | L=1.75 103 | model=res_xhigh_po_0p35 104 | spiceprefix=X 105 | mult=1} 106 | C {sky130_fd_pr/res_xhigh_po_0p35.sym} 330 -260 1 0 {name=R4 107 | L=1.75 108 | model=res_xhigh_po_0p35 109 | spiceprefix=X 110 | mult=1} 111 | C {sky130_fd_pr/res_xhigh_po_0p35.sym} 670 -180 3 1 {name=R6 112 | L=1.75 113 | model=res_xhigh_po_0p35 114 | spiceprefix=X 115 | mult=1} 116 | C {sky130_fd_pr/res_xhigh_po_0p35.sym} 570 -180 3 1 {name=R5 117 | L=1.75 118 | model=res_xhigh_po_0p35 119 | spiceprefix=X 120 | mult=1} 121 | C {devices/iopin.sym} 280 -580 0 1 {name=p1 lab=VPWR} 122 | C {devices/iopin.sym} 280 -60 0 1 {name=p2 lab=VGND} 123 | C {devices/ipin.sym} 280 -520 0 0 {name=p3 lab=Vocm} 124 | C {devices/ipin.sym} 280 -360 0 0 {name=p4 lab=Vin} 125 | C {devices/ipin.sym} 280 -260 0 0 {name=p5 lab=Vip} 126 | C {devices/opin.sym} 900 -320 0 0 {name=p6 lab=Vop} 127 | C {devices/opin.sym} 900 -300 0 0 {name=p7 lab=Von} 128 | C {devices/title.sym} 160 0 0 0 {name=l1 author="Jakob Ratschenberger"} 129 | C {devices/lab_wire.sym} 370 -310 0 1 {name=p8 sig_type=std_logic lab=VGND} 130 | C {devices/lab_wire.sym} 440 -460 0 0 {name=p9 sig_type=std_logic lab=vp} 131 | C {devices/lab_wire.sym} 440 -180 0 0 {name=p10 sig_type=std_logic lab=vn} 132 | C {devices/lab_wire.sym} 630 -460 0 0 {name=p11 sig_type=std_logic lab=v1} 133 | C {devices/lab_wire.sym} 610 -180 2 0 {name=p12 sig_type=std_logic lab=v2} 134 | -------------------------------------------------------------------------------- /rectangle_packing_solver/problem.py: -------------------------------------------------------------------------------- 1 | # Copyright 2022 Kotaro Terada 2 | # 3 | # Copyright 2023 Jakob Ratschenger 4 | # 5 | # Modifications: 6 | # - Modified __init__() to setup a problem by a circuit. 7 | # - Added id_to_device() 8 | # 9 | # Licensed under the Apache License, Version 2.0 (the "License"); 10 | # you may not use this file except in compliance with the License. 11 | # You may obtain a copy of the License at 12 | # 13 | # http://www.apache.org/licenses/LICENSE-2.0 14 | # 15 | # Unless required by applicable law or agreed to in writing, software 16 | # distributed under the License is distributed on an "AS IS" BASIS, 17 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 18 | # See the License for the specific language governing permissions and 19 | # limitations under the License. 20 | 21 | from __future__ import annotations 22 | from typing import TYPE_CHECKING 23 | if TYPE_CHECKING: 24 | from SchematicCapture.Circuit import Circuit 25 | from SchematicCapture.Devices import Device 26 | 27 | from typing import Dict, List, Tuple, Union 28 | from Environment.RUDY import RUDY 29 | from PDK.PDK import global_pdk 30 | 31 | class Problem: 32 | """ 33 | A class to represent a rectangle packing problem. 34 | """ 35 | 36 | def __init__(self, circuit : Circuit) -> None: 37 | """Setup the problem. 38 | 39 | Args: 40 | circuit (Circuit): Circuit which shall be placed. 41 | """ 42 | self.circuit = circuit 43 | 44 | #setup RUDY of the PDK, for 45 | #wire-density estimation 46 | self.rudy = RUDY(global_pdk) 47 | 48 | #setup the rectangles of the problem 49 | rectangles = [] 50 | device : Device 51 | for name, device in circuit.devices.items(): 52 | cell = device.cell 53 | rectangles.append([cell.width, cell.height, 1, name]) 54 | 55 | self.rectangles = [] 56 | self.n = 0 57 | 58 | self._rectangle_device_map = {} 59 | if not isinstance(rectangles, list): 60 | raise TypeError("Invalid argument: 'rectangles' must be a list.") 61 | 62 | for r in rectangles: 63 | if isinstance(r, (list, tuple)): 64 | self.rectangles.append( 65 | { 66 | "id": self.n, 67 | "width": r[0], 68 | "height": r[1], 69 | "rotatable": r[2] if len(r) >= 3 else False, 70 | "device_id": r[3], 71 | } 72 | ) 73 | self._rectangle_device_map[self.n] = r[3] 74 | elif isinstance(r, dict): 75 | self.rectangles.append( 76 | { 77 | "id": self.n, 78 | "width": r["width"], 79 | "height": r["height"], 80 | "rotatable": r["rotatable"] if "rotatable" in r else False, 81 | "device_id": r["device_id"], 82 | } 83 | ) 84 | self._rectangle_device_map[self.n] = r["device_id"] 85 | else: 86 | raise TypeError("A rectangle must be a list, tuple, or dict.") 87 | 88 | 89 | self.n += 1 90 | 91 | def __repr__(self) -> str: 92 | s = "Problem({" 93 | s += "'n': " + str(self.n) + ", " 94 | s += "'rectangles': " + str(self.rectangles) + "})" 95 | 96 | return s 97 | 98 | def id_to_device(self, id : int): 99 | return self._rectangle_device_map[id] 100 | --------------------------------------------------------------------------------