├── README.md ├── blink01.qpf ├── blink01.qsf ├── blink01.qws ├── blink01.vhd ├── blink01.vhd.bak ├── blink01_nativelink_simulation.rpt ├── db ├── blink01.(0).cnf.cdb ├── blink01.(0).cnf.hdb ├── blink01.ace_cmp.bpm ├── blink01.ace_cmp.cdb ├── blink01.ace_cmp.hdb ├── blink01.asm.qmsg ├── blink01.asm.rdb ├── blink01.asm_labs.ddb ├── blink01.cbx.xml ├── blink01.cmp.bpm ├── blink01.cmp.cdb ├── blink01.cmp.hdb ├── blink01.cmp.idb ├── blink01.cmp.kpt ├── blink01.cmp.logdb ├── blink01.cmp.rdb ├── blink01.cmp0.ddb ├── blink01.cmp1.ddb ├── blink01.cmp2.ddb ├── blink01.cmp_merge.kpt ├── blink01.db_info ├── blink01.eco.cdb ├── blink01.eda.qmsg ├── blink01.fit.qmsg ├── blink01.hier_info ├── blink01.hif ├── blink01.ipinfo ├── blink01.lpc.html ├── blink01.lpc.rdb ├── blink01.lpc.txt ├── blink01.map.ammdb ├── blink01.map.bpm ├── blink01.map.cdb ├── blink01.map.hdb ├── blink01.map.kpt ├── blink01.map.logdb ├── blink01.map.qmsg ├── blink01.map.rdb ├── blink01.map_bb.cdb ├── blink01.map_bb.hdb ├── blink01.map_bb.logdb ├── blink01.pplq.rdb ├── blink01.pre_map.hdb ├── blink01.pti_db_list.ddb ├── blink01.root_partition.map.reg_db.cdb ├── blink01.routing.rdb ├── blink01.rtlv.hdb ├── blink01.rtlv_sg.cdb ├── blink01.rtlv_sg_swap.cdb ├── blink01.sgdiff.cdb ├── blink01.sgdiff.hdb ├── blink01.sld_design_entry.sci ├── blink01.sld_design_entry_dsc.sci ├── blink01.smart_action.txt ├── blink01.sta.qmsg ├── blink01.sta.rdb ├── blink01.sta_cmp.8_slow.tdb ├── blink01.syn_hier_info ├── blink01.tis_db_list.ddb ├── blink01.tmw_info ├── blink01.vpr.ammdb ├── logic_util_heursitic.dat └── prev_cmp_blink01.qmsg ├── incremental_db ├── README └── compiled_partitions │ ├── blink01.db_info │ ├── blink01.root_partition.cmp.ammdb │ ├── blink01.root_partition.cmp.cdb │ ├── blink01.root_partition.cmp.dfp │ ├── blink01.root_partition.cmp.hdb │ ├── blink01.root_partition.cmp.kpt │ ├── blink01.root_partition.cmp.logdb │ ├── blink01.root_partition.cmp.rcfdb │ ├── blink01.root_partition.map.cdb │ ├── blink01.root_partition.map.dpi │ ├── blink01.root_partition.map.hbdb.cdb │ ├── blink01.root_partition.map.hbdb.hb_info │ ├── blink01.root_partition.map.hbdb.hdb │ ├── blink01.root_partition.map.hbdb.sig │ ├── blink01.root_partition.map.hdb │ └── blink01.root_partition.map.kpt ├── output_files ├── blink01.asm.rpt ├── blink01.cdf ├── blink01.done ├── blink01.eda.rpt ├── blink01.fit.rpt ├── blink01.fit.smsg ├── blink01.fit.summary ├── blink01.flow.rpt ├── blink01.jdi ├── blink01.map.rpt ├── blink01.map.summary ├── blink01.pin ├── blink01.pof ├── blink01.rbf ├── blink01.sof ├── blink01.sta.rpt ├── blink01.sta.summary ├── output_file-2020-07-21.jic ├── output_file-2020-07-21.map ├── output_file.jic └── output_file.map └── simulation └── modelsim ├── blink01.sft ├── blink01.vho ├── blink01_fast.vho ├── blink01_modelsim.xrf ├── blink01_vhd.sdo └── blink01_vhd_fast.sdo /README.md: -------------------------------------------------------------------------------- 1 | # Blink for Altera Cyclone II EP2C5T144 Mini Development board 2 | 3 | This is a very tiny Quartus II project that shows the bare minimum configuration you need to be able to design FPGA logic programs, run them on the chip, and even store them in the on board EEPROM (If your board isn't the cheapest version that has no EPCS4 memory chip on the bottom of it). 4 | 5 | I'll write more here when I get a chance. Basically, you need a USB Blaster clone (I prefer the white cased one because it allows Device Discovery), and a little understanding of FPGAs and what exactly you're doing. 6 | 7 | There are some good tutorials around on the web but I'll throw what I can in here when I get the chance. 8 | 9 | ## Basic compile 10 | 11 | `ctrl-l` (that's an L) 12 | 13 | ## Basic pin assignment 14 | 15 | `Assignments -> Pin Planner` then change the `Location` field. Recompile after you change pin assignments 16 | 17 | ## Basic programming 18 | 19 | `Tools -> Programmer` then select you hardware, then press `Device Detect` OR (if device detect stalls for 30 seconds) just manually add the `EP2C5T144` device 20 | 21 | ## Programming directly to the config memory 22 | 23 | This is the pain in the butt. You need to convert the `.pom` output from your compile step to a `.jic` file first. Actually, all of this is described in: [https://www.altera.com/en_US/pdfs/literature/an/an370.pdf](https://www.altera.com/en_US/pdfs/literature/an/an370.pdf) 24 | 25 | 1. Open `File -> Convert Programming File` 26 | 2. Select `JTAG Indirect Configuration File (.jic)` from the `Programming file type:` select box 27 | 3. Select `EPCS4` in the `Configuration device:` select box 28 | 4. Provide a `File name:` for the output `.jic` file 29 | 5. In the `Input files to convert` list, highlight the `SOF Data` and select `Add File...` 30 | 6. Navigate to and select the `.sof` file generated when you compiled the design (eg. `blink01.sof`). Click `Open` 31 | 7. Again, in the `Input files to convert` list, highlight the `Flash Loader` and select `Add Device...` 32 | 8. Navigate through the list of devices to find your FPGA (eg. `Cyclone II` and `EP2C5`). Click `OK` to select that device and go back to the `Convert Programming File` window 33 | 9. Click `Generate` to convert the `.sof` input to a `.jic` file 34 | 35 | 36 | Now that you have a compiled `.jic` file, open the `Programmer` window, and select `View -> Show Device Tree` to show the details about what you're going to flash. 37 | 38 | 1. Click `Add File...` on th left hand side 39 | 2. Select your new `.jic` file 40 | 3. On the line listing your `.jic` file, check the `Program/Configure` box 41 | 4. Make sure only your new device configuration is listed. 42 | 5. Click `Start` to flash the `.jic` file to the `EPCS4` flash 43 | 6. Disconnect the USB-Blaster and power cycle the board. It should load your compiled design from the flash chip and start executing it. 44 | -------------------------------------------------------------------------------- /blink01.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 00:21:24 July 21, 2016 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.0" 26 | DATE = "00:21:24 July 21, 2016" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "blink01" 31 | -------------------------------------------------------------------------------- /blink01.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 21 | # Date created = 00:21:24 July 21, 2016 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # blink01_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone II" 40 | set_global_assignment -name DEVICE EP2C5T144C8 41 | set_global_assignment -name TOP_LEVEL_ENTITY blink01 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:21:24 JULY 21, 2016" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP 49 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 50 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 51 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" 52 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation 53 | set_global_assignment -name USE_CONFIGURATION_DEVICE ON 54 | set_global_assignment -name GENERATE_RBF_FILE ON 55 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" 56 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS" 57 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 58 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 59 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 60 | set_global_assignment -name VHDL_FILE blink01.vhd 61 | set_location_assignment PIN_17 -to clk 62 | set_location_assignment PIN_3 -to led0 63 | set_location_assignment PIN_7 -to led1 64 | set_location_assignment PIN_9 -to led2 65 | set_location_assignment PIN_144 -to sw0 66 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sw0 67 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" 68 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /blink01.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/blink01.qws -------------------------------------------------------------------------------- /blink01.vhd: -------------------------------------------------------------------------------- 1 | -- Start of the weird 'hello world' blink: 2 | 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | use ieee.numeric_std.all; 6 | 7 | entity blink01 is 8 | port ( 9 | clk : in std_logic; -- clock is on 17 10 | led0 : out std_logic; -- led on 3 11 | led1 : out std_logic; -- led on 7 12 | led2 : out std_logic; -- led on 9 13 | sw0 : in std_logic -- switch on 114 14 | ); 15 | end blink01; 16 | 17 | architecture rtl of blink01 is 18 | constant CLK_FREQ : integer := 50000000; 19 | constant BLINK_FREQ : integer := 1; 20 | constant CNT_MAX : integer := CLK_FREQ/BLINK_FREQ/2-1; 21 | 22 | signal cnt : unsigned(24 downto 0); 23 | signal blink : std_logic; 24 | 25 | begin 26 | 27 | process(clk, sw0) 28 | 29 | variable speed : integer range 0 to 1000; 30 | begin 31 | if rising_edge(clk) then 32 | 33 | if sw0='0' then 34 | speed := 100; 35 | led1 <= '1'; 36 | else 37 | speed := 0; 38 | led1 <= '0'; 39 | end if; 40 | 41 | if cnt=CNT_MAX then 42 | cnt <= (others => '0'); 43 | blink <= not blink; 44 | else 45 | cnt <= cnt + 1 + speed; 46 | end if; 47 | end if; 48 | 49 | end process; 50 | 51 | 52 | led0 <= blink; 53 | led2 <= not blink; 54 | 55 | end rtl; 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | -------------------------------------------------------------------------------- /blink01.vhd.bak: -------------------------------------------------------------------------------- 1 | -- these are comments 2 | -- 3 | 4 | -- This is the start of an "ENTITY" 5 | library ieee; -- This is important. basically tells the compiler we're onboard with ieee 6 | use ieee.std_logic_1164.all; 7 | ENTITY compare8 IS PORT( 8 | x, y: IN std_logic_vector(7 DOWNTO 0) ; -- two, 8 bit inputs, lsb 9 | res: OUT std_logic ); -- one binary output 10 | END compare8; 11 | 12 | -- Now we must define the actual "ARCHITECTURE" for this "ENTITY" 13 | -- This is how the entity actually works: 14 | ARCHITECTURE struct OF compare8 IS 15 | BEGIN 16 | res <= '1' WHEN (x = y) ELSE '0'; 17 | END struct; 18 | -- And that's it! Our very first, useless, 8bit compare function. 19 | 20 | -------------------------------------------------------------------------------- /blink01_nativelink_simulation.rpt: -------------------------------------------------------------------------------- 1 | Info: Start Nativelink Simulation process 2 | Info: NativeLink has detected VHDL design -- VHDL simulation models will be used 3 | 4 | ========= EDA Simulation Settings ===================== 5 | 6 | Sim Mode : RTL 7 | Family : cycloneii 8 | Quartus root : /media/jamis/8ac7fe17-57f8-471e-a11d-a93c793509c3/jamis/Desktop/my_root/Development/Circuits_MPUs/Altera_FPGA/13.0sp1/quartus/linux64/ 9 | Quartus sim root : /media/jamis/8ac7fe17-57f8-471e-a11d-a93c793509c3/jamis/Desktop/my_root/Development/Circuits_MPUs/Altera_FPGA/13.0sp1/quartus/eda/sim_lib 10 | Simulation Tool : modelsim-altera 11 | Simulation Language : vhdl 12 | Version : 93 13 | Simulation Mode : GUI 14 | Sim Output File : 15 | Sim SDF file : 16 | Sim dir : simulation/modelsim 17 | 18 | ======================================================= 19 | 20 | Info: Starting NativeLink simulation with ModelSim-Altera software 21 | Sourced NativeLink script /media/jamis/8ac7fe17-57f8-471e-a11d-a93c793509c3/jamis/Desktop/my_root/Development/Circuits_MPUs/Altera_FPGA/13.0sp1/quartus/common/tcl/internal/nativelink/modelsim.tcl 22 | Error: Can't launch ModelSim-Altera Simulation software -- make sure the software is properly installed and the environment variable LM_LICENSE_FILE or MGLS_LICENSE_FILE points to the correct license file. 23 | Error: NativeLink simulation flow was NOT successful 24 | 25 | 26 | 27 | ================The following additional information is provided to help identify the cause of error while running nativelink scripts================= 28 | Nativelink TCL script failed with errorCode: issued_nl_message 29 | Nativelink TCL script failed with errorInfo: Can't launch ModelSim-Altera Simulation software -- make sure the software is properly installed and the environment variable LM_LICENSE_FILE or MGLS_LICENSE_FILE points to the correct license file. 30 | while executing 31 | "error "$emsg" "" "issued_nl_message"" 32 | invoked from within 33 | "if [ catch {exec $vsim_cmd -version} version_str] { 34 | set emsg "Can't launch $tool Simulation software -- make sure the software is properly installed..." 35 | (procedure "launch_sim" line 89) 36 | invoked from within 37 | "launch_sim launch_args_hash" 38 | ("eval" body line 1) 39 | invoked from within 40 | "eval launch_sim launch_args_hash" 41 | invoked from within 42 | "if [ info exists ::errorCode ] { 43 | set savedCode $::errorCode 44 | set savedInfo $::errorInfo 45 | error $result $savedInfo $savedCode 46 | } else { 47 | ..." 48 | invoked from within 49 | "if [catch {eval launch_sim launch_args_hash} result ] { 50 | set status 1 51 | if [ info exists ::errorCode ] { 52 | set savedCode $::errorCode 53 | set sav..." 54 | (procedure "run_sim" line 78) 55 | invoked from within 56 | "run_sim run_sim_args_hash" 57 | invoked from within 58 | "if [ info exists ::errorCode ] { 59 | set savedCode $::errorCode 60 | set savedInfo $::errorInfo 61 | error "$result" $savedInfo $savedCode 62 | } else { 63 | er..." 64 | (procedure "run_eda_simulation_tool" line 330) 65 | invoked from within 66 | "run_eda_simulation_tool eda_opts_hash" 67 | -------------------------------------------------------------------------------- /db/blink01.(0).cnf.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.(0).cnf.cdb -------------------------------------------------------------------------------- /db/blink01.(0).cnf.hdb: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /db/blink01.cmp_merge.kpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.cmp_merge.kpt -------------------------------------------------------------------------------- /db/blink01.db_info: -------------------------------------------------------------------------------- 1 | Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 2 | Version_Index = 302049280 3 | Creation_Time = Tue Jul 21 02:33:22 2020 4 | -------------------------------------------------------------------------------- /db/blink01.eco.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.eco.cdb -------------------------------------------------------------------------------- /db/blink01.eda.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595326492504 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595326492504 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 21 03:14:52 2020 " "Processing started: Tue Jul 21 03:14:52 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595326492504 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595326492504 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off blink01 -c blink01 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off blink01 -c blink01" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595326492504 ""} 4 | { "Info" "IWSC_DONE_HDL_DUAL_SDO_GENERATION" "blink01.vho\", \"blink01_fast.vho blink01_vhd.sdo blink01_vhd_fast.sdo D:/temp-development/alteraProjects/blink01/simulation/modelsim/ simulation " "Generated files \"blink01.vho\", \"blink01_fast.vho\", \"blink01_vhd.sdo\" and \"blink01_vhd_fast.sdo\" in directory \"D:/temp-development/alteraProjects/blink01/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204026 "Generated files \"%1!s!\", \"%2!s!\" and \"%3!s!\" in directory \"%4!s!\" for EDA %5!s! tool" 0 0 "Quartus II" 0 -1 1595326492770 ""} 5 | { "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4519 " "Peak virtual memory: 4519 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595326492840 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 21 03:14:52 2020 " "Processing ended: Tue Jul 21 03:14:52 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595326492840 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595326492840 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595326492840 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595326492840 ""} 6 | -------------------------------------------------------------------------------- /db/blink01.fit.qmsg: -------------------------------------------------------------------------------- 1 | { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1595326487131 ""} 2 | { "Info" "IMPP_MPP_USER_DEVICE" "blink01 EP2C5T144C8 " "Selected device EP2C5T144C8 for design \"blink01\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595326487136 ""} 3 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595326487155 ""} 4 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595326487155 ""} 5 | { "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1595326487209 ""} 6 | { "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595326487217 ""} 7 | { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5T144I8 " "Device EP2C5T144I8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595326487355 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8T144C8 " "Device EP2C8T144C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595326487355 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8T144I8 " "Device EP2C8T144I8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595326487355 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595326487355 ""} 8 | { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/temp-development/alteraProjects/blink01/" { { 0 { 0 ""} 0 149 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1595326487356 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/temp-development/alteraProjects/blink01/" { { 0 { 0 ""} 0 150 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1595326487356 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS41p/nCEO~ 76 " "Pin ~LVDS41p/nCEO~ is reserved at location 76" { } { { "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~LVDS41p/nCEO~ } } } { "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~LVDS41p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/temp-development/alteraProjects/blink01/" { { 0 { 0 ""} 0 151 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1595326487356 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1595326487356 ""} 9 | { "Critical Warning" "WSTA_SDC_NOT_FOUND" "blink01.sdc " "Synopsys Design Constraints File file not found: 'blink01.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1595326487445 ""} 10 | { "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595326487445 ""} 11 | { "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1595326487447 ""} 12 | { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN 17 (CLK0, LVDSCLK0p, Input)) " "Automatically promoted node clk (placed in PIN 17 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1595326487450 ""} } { { "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clk } } } { "d:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "blink01.vhd" "" { Text "D:/temp-development/alteraProjects/blink01/blink01.vhd" 9 0 0 } } { "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/temp-development/alteraProjects/blink01/" { { 0 { 0 ""} 0 4 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1595326487450 ""} 13 | { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1595326487481 ""} 14 | { "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595326487481 ""} 15 | { "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595326487482 ""} 16 | { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1595326487482 ""} 17 | { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1595326487482 ""} 18 | { "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1595326487485 ""} 19 | { "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1595326487485 ""} 20 | { "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1595326487486 ""} 21 | { "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1595326487491 ""} 22 | { "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1595326487491 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595326487491 ""} 23 | { "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595326487494 ""} 24 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595326487752 ""} 25 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595326487783 ""} 26 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595326487787 ""} 27 | { "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595326487993 ""} 28 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595326487994 ""} 29 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595326488027 ""} 30 | { "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X13_Y14 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X13_Y14" { } { { "loc" "" { Generic "D:/temp-development/alteraProjects/blink01/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X13_Y14"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X13_Y14"} 0 0 14 15 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595326488248 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595326488248 ""} 31 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595326488308 ""} 32 | { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1595326488310 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1595326488310 ""} 33 | { "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.11 " "Total time spent on timing analysis during the Fitter is 0.11 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595326488313 ""} 34 | { "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1595326488314 ""} 35 | { "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "3 " "Found 3 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led0 0 " "Pin \"led0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1595326488316 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led1 0 " "Pin \"led1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1595326488316 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led2 0 " "Pin \"led2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1595326488316 ""} } { } 0 306006 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "Fitter" 0 -1 1595326488316 ""} 36 | { "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1595326488352 ""} 37 | { "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1595326488358 ""} 38 | { "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1595326488390 ""} 39 | { "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595326488466 ""} 40 | { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/temp-development/alteraProjects/blink01/output_files/blink01.fit.smsg " "Generated suppressed messages file D:/temp-development/alteraProjects/blink01/output_files/blink01.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595326488524 ""} 41 | { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4789 " "Peak virtual memory: 4789 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595326488663 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 21 03:14:48 2020 " "Processing ended: Tue Jul 21 03:14:48 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595326488663 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595326488663 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595326488663 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595326488663 ""} 42 | -------------------------------------------------------------------------------- /db/blink01.hier_info: -------------------------------------------------------------------------------- 1 | |blink01 2 | clk => blink.CLK 3 | clk => cnt[0].CLK 4 | clk => cnt[1].CLK 5 | clk => cnt[2].CLK 6 | clk => cnt[3].CLK 7 | clk => cnt[4].CLK 8 | clk => cnt[5].CLK 9 | clk => cnt[6].CLK 10 | clk => cnt[7].CLK 11 | clk => cnt[8].CLK 12 | clk => cnt[9].CLK 13 | clk => cnt[10].CLK 14 | clk => cnt[11].CLK 15 | clk => cnt[12].CLK 16 | clk => cnt[13].CLK 17 | clk => cnt[14].CLK 18 | clk => cnt[15].CLK 19 | clk => cnt[16].CLK 20 | clk => cnt[17].CLK 21 | clk => cnt[18].CLK 22 | clk => cnt[19].CLK 23 | clk => cnt[20].CLK 24 | clk => cnt[21].CLK 25 | clk => cnt[22].CLK 26 | clk => cnt[23].CLK 27 | clk => cnt[24].CLK 28 | clk => led1~reg0.CLK 29 | led0 <= blink.DB_MAX_OUTPUT_PORT_TYPE 30 | led1 <= led1~reg0.DB_MAX_OUTPUT_PORT_TYPE 31 | led2 <= blink.DB_MAX_OUTPUT_PORT_TYPE 32 | sw0 => Add1.IN21 33 | sw0 => Add1.IN22 34 | sw0 => Add1.IN23 35 | sw0 => led1~reg0.DATAIN 36 | 37 | 38 | -------------------------------------------------------------------------------- /db/blink01.hif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.hif -------------------------------------------------------------------------------- /db/blink01.ipinfo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.ipinfo -------------------------------------------------------------------------------- /db/blink01.lpc.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 |
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
19 | -------------------------------------------------------------------------------- /db/blink01.lpc.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.lpc.rdb -------------------------------------------------------------------------------- /db/blink01.lpc.txt: -------------------------------------------------------------------------------- 1 | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 2 | ; Legal Partition Candidates ; 3 | +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 4 | ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; 5 | +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 6 | -------------------------------------------------------------------------------- /db/blink01.map.ammdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.map.ammdb -------------------------------------------------------------------------------- /db/blink01.map.bpm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.map.bpm -------------------------------------------------------------------------------- /db/blink01.map.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.map.cdb -------------------------------------------------------------------------------- /db/blink01.map.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.map.hdb -------------------------------------------------------------------------------- /db/blink01.map.kpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.map.kpt -------------------------------------------------------------------------------- /db/blink01.map.logdb: -------------------------------------------------------------------------------- 1 | v1 2 | -------------------------------------------------------------------------------- /db/blink01.map.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595326484793 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595326484793 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 21 03:14:44 2020 " "Processing started: Tue Jul 21 03:14:44 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595326484793 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595326484793 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off blink01 -c blink01 " "Command: quartus_map --read_settings_files=on --write_settings_files=off blink01 -c blink01" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595326484793 ""} 4 | { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1595326485077 ""} 5 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "blink01.vhd 2 1 " "Found 2 design units, including 1 entities, in source file blink01.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 blink01-rtl " "Found design unit 1: blink01-rtl" { } { { "blink01.vhd" "" { Text "D:/temp-development/alteraProjects/blink01/blink01.vhd" 17 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595326485435 ""} { "Info" "ISGN_ENTITY_NAME" "1 blink01 " "Found entity 1: blink01" { } { { "blink01.vhd" "" { Text "D:/temp-development/alteraProjects/blink01/blink01.vhd" 7 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595326485435 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595326485435 ""} 6 | { "Info" "ISGN_START_ELABORATION_TOP" "blink01 " "Elaborating entity \"blink01\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595326485459 ""} 7 | { "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1595326485898 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1595326485898 ""} 8 | { "Info" "ICUT_CUT_TM_SUMMARY" "63 " "Implemented 63 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595326485959 ""} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Implemented 3 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595326485959 ""} { "Info" "ICUT_CUT_TM_LCELLS" "58 " "Implemented 58 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595326485959 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595326485959 ""} 9 | { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4622 " "Peak virtual memory: 4622 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595326485997 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 21 03:14:45 2020 " "Processing ended: Tue Jul 21 03:14:45 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595326485997 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595326485997 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595326485997 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595326485997 ""} 10 | -------------------------------------------------------------------------------- /db/blink01.map.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.map.rdb -------------------------------------------------------------------------------- /db/blink01.map_bb.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.map_bb.cdb -------------------------------------------------------------------------------- /db/blink01.map_bb.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.map_bb.hdb -------------------------------------------------------------------------------- /db/blink01.map_bb.logdb: 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-------------------------------------------------------------------------------- /db/blink01.sld_design_entry_dsc.sci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.sld_design_entry_dsc.sci -------------------------------------------------------------------------------- /db/blink01.smart_action.txt: -------------------------------------------------------------------------------- 1 | DONE 2 | -------------------------------------------------------------------------------- /db/blink01.sta.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595326491039 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491039 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 21 03:14:50 2020 " "Processing started: Tue Jul 21 03:14:50 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595326491039 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595326491039 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta blink01 -c blink01 " "Command: quartus_sta blink01 -c blink01" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595326491039 ""} 4 | { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595326491104 ""} 5 | { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1595326491205 ""} 6 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595326491226 ""} 7 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595326491226 ""} 8 | { "Critical Warning" "WSTA_SDC_NOT_FOUND" "blink01.sdc " "Synopsys Design Constraints File file not found: 'blink01.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1595326491293 ""} 9 | { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595326491294 ""} 10 | { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491294 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491294 ""} 11 | { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595326491295 ""} 12 | { "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1595326491302 ""} 13 | { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595326491307 ""} 14 | { "Info" "ISTA_WORST_CASE_SLACK" "setup -5.342 " "Worst-case setup slack is -5.342" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491314 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491314 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.342 -105.573 clk " " -5.342 -105.573 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491314 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595326491314 ""} 15 | { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.499 " "Worst-case hold slack is 0.499" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.499 0.000 clk " " 0.499 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491323 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595326491323 ""} 16 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595326491327 ""} 17 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595326491330 ""} 18 | { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.941 " "Worst-case minimum pulse width slack is -1.941" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491334 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491334 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.941 -42.009 clk " " -1.941 -42.009 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491334 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595326491334 ""} 19 | { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595326491368 ""} 20 | { "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1595326491369 ""} 21 | { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595326491376 ""} 22 | { "Info" "ISTA_WORST_CASE_SLACK" "setup -1.202 " "Worst-case setup slack is -1.202" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.202 -18.260 clk " " -1.202 -18.260 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491379 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595326491379 ""} 23 | { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.215 " "Worst-case hold slack is 0.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491385 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491385 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 clk " " 0.215 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491385 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595326491385 ""} 24 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595326491390 ""} 25 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595326491394 ""} 26 | { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -28.380 clk " " -1.380 -28.380 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326491397 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595326491397 ""} 27 | { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595326491438 ""} 28 | { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595326491469 ""} 29 | { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595326491469 ""} 30 | { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4529 " "Peak virtual memory: 4529 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595326491557 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 21 03:14:51 2020 " "Processing ended: Tue Jul 21 03:14:51 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595326491557 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595326491557 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595326491557 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595326491557 ""} 31 | -------------------------------------------------------------------------------- /db/blink01.sta.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.sta.rdb -------------------------------------------------------------------------------- /db/blink01.sta_cmp.8_slow.tdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.sta_cmp.8_slow.tdb -------------------------------------------------------------------------------- /db/blink01.syn_hier_info: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.syn_hier_info -------------------------------------------------------------------------------- /db/blink01.tis_db_list.ddb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.tis_db_list.ddb -------------------------------------------------------------------------------- /db/blink01.tmw_info: -------------------------------------------------------------------------------- 1 | start_full_compilation:s:00:00:09 2 | start_analysis_synthesis:s:00:00:02-start_full_compilation 3 | start_analysis_elaboration:s-start_full_compilation 4 | start_fitter:s:00:00:03-start_full_compilation 5 | start_assembler:s:00:00:01-start_full_compilation 6 | start_timing_analyzer:s:00:00:02-start_full_compilation 7 | start_eda_netlist_writer:s:00:00:01-start_full_compilation 8 | -------------------------------------------------------------------------------- /db/blink01.vpr.ammdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/db/blink01.vpr.ammdb -------------------------------------------------------------------------------- /db/logic_util_heursitic.dat: -------------------------------------------------------------------------------- 1 |  2 |  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFJKLMNOPQRSTUVY[\]^_klmno -------------------------------------------------------------------------------- /db/prev_cmp_blink01.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595326392706 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595326392706 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 21 03:13:12 2020 " "Processing started: Tue Jul 21 03:13:12 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595326392706 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595326392706 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off blink01 -c blink01 " "Command: quartus_map --read_settings_files=on --write_settings_files=off blink01 -c blink01" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595326392706 ""} 4 | { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1595326393000 ""} 5 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "blink01.vhd 2 1 " "Found 2 design units, including 1 entities, in source file blink01.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 blink01-rtl " "Found design unit 1: blink01-rtl" { } { { "blink01.vhd" "" { Text "D:/temp-development/alteraProjects/blink01/blink01.vhd" 17 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595326393373 ""} { "Info" "ISGN_ENTITY_NAME" "1 blink01 " "Found entity 1: blink01" { } { { "blink01.vhd" "" { Text "D:/temp-development/alteraProjects/blink01/blink01.vhd" 7 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595326393373 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595326393373 ""} 6 | { "Info" "ISGN_START_ELABORATION_TOP" "blink01 " "Elaborating entity \"blink01\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595326393397 ""} 7 | { "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1595326393853 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1595326393853 ""} 8 | { "Info" "ICUT_CUT_TM_SUMMARY" "62 " "Implemented 62 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595326393919 ""} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Implemented 3 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595326393919 ""} { "Info" "ICUT_CUT_TM_LCELLS" "57 " "Implemented 57 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595326393919 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595326393919 ""} 9 | { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4622 " "Peak virtual memory: 4622 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595326393974 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 21 03:13:13 2020 " "Processing ended: Tue Jul 21 03:13:13 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595326393974 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595326393974 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595326393974 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595326393974 ""} 10 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595326394966 ""} 11 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595326394966 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 21 03:13:14 2020 " "Processing started: Tue Jul 21 03:13:14 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595326394966 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1595326394966 ""} 12 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off blink01 -c blink01 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off blink01 -c blink01" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1595326394967 ""} 13 | { "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1595326395040 ""} 14 | { "Info" "0" "" "Project = blink01" { } { } 0 0 "Project = blink01" 0 0 "Fitter" 0 0 1595326395041 ""} 15 | { "Info" "0" "" "Revision = blink01" { } { } 0 0 "Revision = blink01" 0 0 "Fitter" 0 0 1595326395041 ""} 16 | { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1595326395111 ""} 17 | { "Info" "IMPP_MPP_USER_DEVICE" "blink01 EP2C5T144C8 " "Selected device EP2C5T144C8 for design \"blink01\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595326395116 ""} 18 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595326395135 ""} 19 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595326395135 ""} 20 | { "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1595326395186 ""} 21 | { "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595326395193 ""} 22 | { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5T144I8 " "Device EP2C5T144I8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595326395333 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8T144C8 " "Device EP2C8T144C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595326395333 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8T144I8 " "Device EP2C8T144I8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595326395333 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595326395333 ""} 23 | { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Pin ~ASDO~ is reserved at location 1" { } { { "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/temp-development/alteraProjects/blink01/" { { 0 { 0 ""} 0 147 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1595326395334 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Pin ~nCSO~ is reserved at location 2" { } { { "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/temp-development/alteraProjects/blink01/" { { 0 { 0 ""} 0 148 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1595326395334 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS41p/nCEO~ 76 " "Pin ~LVDS41p/nCEO~ is reserved at location 76" { } { { "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~LVDS41p/nCEO~ } } } { "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~LVDS41p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/temp-development/alteraProjects/blink01/" { { 0 { 0 ""} 0 149 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1595326395334 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1595326395334 ""} 24 | { "Critical Warning" "WSTA_SDC_NOT_FOUND" "blink01.sdc " "Synopsys Design Constraints File file not found: 'blink01.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1595326395416 ""} 25 | { "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595326395416 ""} 26 | { "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1595326395418 ""} 27 | { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN 17 (CLK0, LVDSCLK0p, Input)) " "Automatically promoted node clk (placed in PIN 17 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1595326395422 ""} } { { "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { clk } } } { "d:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "blink01.vhd" "" { Text "D:/temp-development/alteraProjects/blink01/blink01.vhd" 9 0 0 } } { "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/temp-development/alteraProjects/blink01/" { { 0 { 0 ""} 0 4 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1595326395422 ""} 28 | { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1595326395458 ""} 29 | { "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595326395459 ""} 30 | { "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595326395459 ""} 31 | { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1595326395460 ""} 32 | { "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1595326395460 ""} 33 | { "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1595326395462 ""} 34 | { "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1595326395462 ""} 35 | { "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1595326395462 ""} 36 | { "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1595326395468 ""} 37 | { "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1595326395468 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595326395468 ""} 38 | { "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595326395471 ""} 39 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595326395726 ""} 40 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595326395757 ""} 41 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595326395763 ""} 42 | { "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595326395961 ""} 43 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595326395962 ""} 44 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595326395998 ""} 45 | { "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X13_Y14 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X13_Y14" { } { { "loc" "" { Generic "D:/temp-development/alteraProjects/blink01/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X13_Y14"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X13_Y14"} 0 0 14 15 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595326396229 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595326396229 ""} 46 | { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595326396269 ""} 47 | { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1595326396270 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1595326396270 ""} 48 | { "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595326396273 ""} 49 | { "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1595326396275 ""} 50 | { "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "3 " "Found 3 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led0 0 " "Pin \"led0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1595326396277 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led1 0 " "Pin \"led1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1595326396277 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led2 0 " "Pin \"led2\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1595326396277 ""} } { } 0 306006 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "Fitter" 0 -1 1595326396277 ""} 51 | { "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1595326396316 ""} 52 | { "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1595326396322 ""} 53 | { "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1595326396355 ""} 54 | { "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595326396429 ""} 55 | { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/temp-development/alteraProjects/blink01/output_files/blink01.fit.smsg " "Generated suppressed messages file D:/temp-development/alteraProjects/blink01/output_files/blink01.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595326396490 ""} 56 | { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4793 " "Peak virtual memory: 4793 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595326396646 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 21 03:13:16 2020 " "Processing ended: Tue Jul 21 03:13:16 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595326396646 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595326396646 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595326396646 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595326396646 ""} 57 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1595326397572 ""} 58 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595326397572 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 21 03:13:17 2020 " "Processing started: Tue Jul 21 03:13:17 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595326397572 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595326397572 ""} 59 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off blink01 -c blink01 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off blink01 -c blink01" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595326397572 ""} 60 | { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595326397861 ""} 61 | { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595326397876 ""} 62 | { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4536 " "Peak virtual memory: 4536 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595326398093 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 21 03:13:18 2020 " "Processing ended: Tue Jul 21 03:13:18 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595326398093 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595326398093 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595326398093 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595326398093 ""} 63 | { "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1595326398682 ""} 64 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1595326399063 ""} 65 | { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399063 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 21 03:13:18 2020 " "Processing started: Tue Jul 21 03:13:18 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595326399063 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595326399063 ""} 66 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta blink01 -c blink01 " "Command: quartus_sta blink01 -c blink01" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595326399064 ""} 67 | { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595326399133 ""} 68 | { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1595326399236 ""} 69 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595326399257 ""} 70 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595326399257 ""} 71 | { "Critical Warning" "WSTA_SDC_NOT_FOUND" "blink01.sdc " "Synopsys Design Constraints File file not found: 'blink01.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1595326399331 ""} 72 | { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595326399331 ""} 73 | { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399331 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399331 ""} 74 | { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595326399332 ""} 75 | { "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1595326399339 ""} 76 | { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595326399344 ""} 77 | { "Info" "ISTA_WORST_CASE_SLACK" "setup -5.396 " "Worst-case setup slack is -5.396" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.396 -101.220 clk " " -5.396 -101.220 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399350 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595326399350 ""} 78 | { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.499 " "Worst-case hold slack is 0.499" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399354 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399354 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.499 0.000 clk " " 0.499 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399354 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595326399354 ""} 79 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595326399362 ""} 80 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595326399365 ""} 81 | { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.941 " "Worst-case minimum pulse width slack is -1.941" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399372 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399372 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.941 -42.009 clk " " -1.941 -42.009 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399372 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595326399372 ""} 82 | { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595326399403 ""} 83 | { "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1595326399404 ""} 84 | { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595326399411 ""} 85 | { "Info" "ISTA_WORST_CASE_SLACK" "setup -1.219 " "Worst-case setup slack is -1.219" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399414 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399414 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.219 -17.873 clk " " -1.219 -17.873 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399414 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595326399414 ""} 86 | { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.215 " "Worst-case hold slack is 0.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399421 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399421 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 clk " " 0.215 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399421 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595326399421 ""} 87 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595326399425 ""} 88 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595326399428 ""} 89 | { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -28.380 clk " " -1.380 -28.380 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595326399432 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595326399432 ""} 90 | { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595326399473 ""} 91 | { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595326399506 ""} 92 | { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595326399506 ""} 93 | { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4529 " "Peak virtual memory: 4529 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595326399593 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 21 03:13:19 2020 " "Processing ended: Tue Jul 21 03:13:19 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595326399593 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595326399593 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595326399593 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595326399593 ""} 94 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595326400529 ""} 95 | { "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595326400530 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 21 03:13:20 2020 " "Processing started: Tue Jul 21 03:13:20 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595326400530 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595326400530 ""} 96 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off blink01 -c blink01 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off blink01 -c blink01" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595326400530 ""} 97 | { "Info" "IWSC_DONE_HDL_DUAL_SDO_GENERATION" "blink01.vho\", \"blink01_fast.vho blink01_vhd.sdo blink01_vhd_fast.sdo D:/temp-development/alteraProjects/blink01/simulation/modelsim/ simulation " "Generated files \"blink01.vho\", \"blink01_fast.vho\", \"blink01_vhd.sdo\" and \"blink01_vhd_fast.sdo\" in directory \"D:/temp-development/alteraProjects/blink01/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204026 "Generated files \"%1!s!\", \"%2!s!\" and \"%3!s!\" in directory \"%4!s!\" for EDA %5!s! tool" 0 0 "Quartus II" 0 -1 1595326400797 ""} 98 | { "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4519 " "Peak virtual memory: 4519 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595326400844 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 21 03:13:20 2020 " "Processing ended: Tue Jul 21 03:13:20 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595326400844 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595326400844 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595326400844 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595326400844 ""} 99 | { "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 9 s " "Quartus II Full Compilation was successful. 0 errors, 9 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595326401447 ""} 100 | -------------------------------------------------------------------------------- /incremental_db/README: -------------------------------------------------------------------------------- 1 | This folder contains data for incremental compilation. 2 | 3 | The compiled_partitions sub-folder contains previous compilation results for each partition. 4 | As long as this folder is preserved, incremental compilation results from earlier compiles 5 | can be re-used. To perform a clean compilation from source files for all partitions, both 6 | the db and incremental_db folder should be removed. 7 | 8 | The imported_partitions sub-folder contains the last imported QXP for each imported partition. 9 | As long as this folder is preserved, imported partitions will be automatically re-imported 10 | when the db or incremental_db/compiled_partitions folders are removed. 11 | 12 | -------------------------------------------------------------------------------- /incremental_db/compiled_partitions/blink01.db_info: -------------------------------------------------------------------------------- 1 | Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 2 | Version_Index = 302049280 3 | Creation_Time = Thu Jul 21 00:45:46 2016 4 | -------------------------------------------------------------------------------- /incremental_db/compiled_partitions/blink01.root_partition.cmp.ammdb: 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/incremental_db/compiled_partitions/blink01.root_partition.map.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/incremental_db/compiled_partitions/blink01.root_partition.map.cdb -------------------------------------------------------------------------------- /incremental_db/compiled_partitions/blink01.root_partition.map.dpi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/incremental_db/compiled_partitions/blink01.root_partition.map.dpi -------------------------------------------------------------------------------- /incremental_db/compiled_partitions/blink01.root_partition.map.hbdb.cdb: -------------------------------------------------------------------------------- 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/incremental_db/compiled_partitions/blink01.root_partition.map.kpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/incremental_db/compiled_partitions/blink01.root_partition.map.kpt -------------------------------------------------------------------------------- /output_files/blink01.asm.rpt: -------------------------------------------------------------------------------- 1 | Assembler report for blink01 2 | Tue Jul 21 03:14:50 2020 3 | Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Assembler Summary 11 | 3. Assembler Settings 12 | 4. Assembler Generated Files 13 | 5. Assembler Device Options: D:/temp-development/alteraProjects/blink01/output_files/blink01.sof 14 | 6. Assembler Device Options: D:/temp-development/alteraProjects/blink01/output_files/blink01.pof 15 | 7. Assembler Device Options: D:/temp-development/alteraProjects/blink01/output_files/blink01.rbf 16 | 8. Assembler Messages 17 | 18 | 19 | 20 | ---------------- 21 | ; Legal Notice ; 22 | ---------------- 23 | Copyright (C) 1991-2013 Altera Corporation 24 | Your use of Altera Corporation's design tools, logic functions 25 | and other software and tools, and its AMPP partner logic 26 | functions, and any output files from any of the foregoing 27 | (including device programming or simulation files), and any 28 | associated documentation or information are expressly subject 29 | to the terms and conditions of the Altera Program License 30 | Subscription Agreement, Altera MegaCore Function License 31 | Agreement, or other applicable license agreement, including, 32 | without limitation, that your use is for the sole purpose of 33 | programming logic devices manufactured by Altera and sold by 34 | Altera or its authorized distributors. Please refer to the 35 | applicable agreement for further details. 36 | 37 | 38 | 39 | +---------------------------------------------------------------+ 40 | ; Assembler Summary ; 41 | +-----------------------+---------------------------------------+ 42 | ; Assembler Status ; Successful - Tue Jul 21 03:14:50 2020 ; 43 | ; Revision Name ; blink01 ; 44 | ; Top-level Entity Name ; blink01 ; 45 | ; Family ; Cyclone II ; 46 | ; Device ; EP2C5T144C8 ; 47 | +-----------------------+---------------------------------------+ 48 | 49 | 50 | +--------------------------------------------------------------------------------------------------------+ 51 | ; Assembler Settings ; 52 | +-----------------------------------------------------------------------------+----------+---------------+ 53 | ; Option ; Setting ; Default Value ; 54 | +-----------------------------------------------------------------------------+----------+---------------+ 55 | ; Generate Raw Binary File (.rbf) For Target Device ; On ; Off ; 56 | ; Use smart compilation ; Off ; Off ; 57 | ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; 58 | ; Enable compact report table ; Off ; Off ; 59 | ; Generate compressed bitstreams ; On ; On ; 60 | ; Compression mode ; Off ; Off ; 61 | ; Clock source for configuration device ; Internal ; Internal ; 62 | ; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; 63 | ; Divide clock frequency by ; 1 ; 1 ; 64 | ; Auto user code ; On ; On ; 65 | ; Use configuration device ; On ; On ; 66 | ; Configuration device ; Auto ; Auto ; 67 | ; Configuration device auto user code ; Off ; Off ; 68 | ; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; 69 | ; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; 70 | ; Hexadecimal Output File start address ; 0 ; 0 ; 71 | ; Hexadecimal Output File count direction ; Up ; Up ; 72 | ; Release clears before tri-states ; Off ; Off ; 73 | ; Auto-restart configuration after error ; On ; On ; 74 | ; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; 75 | ; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; 76 | ; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; 77 | ; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; 78 | ; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; 79 | +-----------------------------------------------------------------------------+----------+---------------+ 80 | 81 | 82 | +---------------------------------------------------------------------+ 83 | ; Assembler Generated Files ; 84 | +---------------------------------------------------------------------+ 85 | ; File Name ; 86 | +---------------------------------------------------------------------+ 87 | ; D:/temp-development/alteraProjects/blink01/output_files/blink01.sof ; 88 | ; D:/temp-development/alteraProjects/blink01/output_files/blink01.pof ; 89 | ; D:/temp-development/alteraProjects/blink01/output_files/blink01.rbf ; 90 | +---------------------------------------------------------------------+ 91 | 92 | 93 | +-----------------------------------------------------------------------------------------------+ 94 | ; Assembler Device Options: D:/temp-development/alteraProjects/blink01/output_files/blink01.sof ; 95 | +----------------+------------------------------------------------------------------------------+ 96 | ; Option ; Setting ; 97 | +----------------+------------------------------------------------------------------------------+ 98 | ; Device ; EP2C5T144C8 ; 99 | ; JTAG usercode ; 0x00078D69 ; 100 | ; Checksum ; 0x00078D69 ; 101 | +----------------+------------------------------------------------------------------------------+ 102 | 103 | 104 | +-----------------------------------------------------------------------------------------------+ 105 | ; Assembler Device Options: D:/temp-development/alteraProjects/blink01/output_files/blink01.pof ; 106 | +--------------------+--------------------------------------------------------------------------+ 107 | ; Option ; Setting ; 108 | +--------------------+--------------------------------------------------------------------------+ 109 | ; Device ; EPCS4 ; 110 | ; JTAG usercode ; 0x00000000 ; 111 | ; Checksum ; 0x07520626 ; 112 | ; Compression Ratio ; 3 ; 113 | +--------------------+--------------------------------------------------------------------------+ 114 | 115 | 116 | +-----------------------------------------------------------------------------------------------+ 117 | ; Assembler Device Options: D:/temp-development/alteraProjects/blink01/output_files/blink01.rbf ; 118 | +---------------------+-------------------------------------------------------------------------+ 119 | ; Option ; Setting ; 120 | +---------------------+-------------------------------------------------------------------------+ 121 | ; Raw Binary File ; ; 122 | ; Compression Ratio ; 3 ; 123 | +---------------------+-------------------------------------------------------------------------+ 124 | 125 | 126 | +--------------------+ 127 | ; Assembler Messages ; 128 | +--------------------+ 129 | Info: ******************************************************************* 130 | Info: Running Quartus II 64-Bit Assembler 131 | Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 132 | Info: Processing started: Tue Jul 21 03:14:49 2020 133 | Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off blink01 -c blink01 134 | Info (115031): Writing out detailed assembly data for power analysis 135 | Info (115030): Assembler is generating device programming files 136 | Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings 137 | Info: Peak virtual memory: 4536 megabytes 138 | Info: Processing ended: Tue Jul 21 03:14:50 2020 139 | Info: Elapsed time: 00:00:01 140 | Info: Total CPU time (on all processors): 00:00:01 141 | 142 | 143 | -------------------------------------------------------------------------------- /output_files/blink01.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(EP2C5) Path("D:/temp-development/alteraProjects/blink01/output_files/") File("output_file-2020-07-21.jic") MfrSpec(OpMask(1) SEC_Device(EPCS4) Child_OpMask(1 1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /output_files/blink01.done: -------------------------------------------------------------------------------- 1 | Tue Jul 21 03:14:53 2020 2 | -------------------------------------------------------------------------------- /output_files/blink01.eda.rpt: -------------------------------------------------------------------------------- 1 | EDA Netlist Writer report for blink01 2 | Tue Jul 21 03:14:52 2020 3 | Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. EDA Netlist Writer Summary 11 | 3. Simulation Settings 12 | 4. Simulation Generated Files 13 | 5. EDA Netlist Writer Messages 14 | 15 | 16 | 17 | ---------------- 18 | ; Legal Notice ; 19 | ---------------- 20 | Copyright (C) 1991-2013 Altera Corporation 21 | Your use of Altera Corporation's design tools, logic functions 22 | and other software and tools, and its AMPP partner logic 23 | functions, and any output files from any of the foregoing 24 | (including device programming or simulation files), and any 25 | associated documentation or information are expressly subject 26 | to the terms and conditions of the Altera Program License 27 | Subscription Agreement, Altera MegaCore Function License 28 | Agreement, or other applicable license agreement, including, 29 | without limitation, that your use is for the sole purpose of 30 | programming logic devices manufactured by Altera and sold by 31 | Altera or its authorized distributors. Please refer to the 32 | applicable agreement for further details. 33 | 34 | 35 | 36 | +-------------------------------------------------------------------+ 37 | ; EDA Netlist Writer Summary ; 38 | +---------------------------+---------------------------------------+ 39 | ; EDA Netlist Writer Status ; Successful - Tue Jul 21 03:14:52 2020 ; 40 | ; Revision Name ; blink01 ; 41 | ; Top-level Entity Name ; blink01 ; 42 | ; Family ; Cyclone II ; 43 | ; Simulation Files Creation ; Successful ; 44 | +---------------------------+---------------------------------------+ 45 | 46 | 47 | +----------------------------------------------------------------------------------------------------------------------------+ 48 | ; Simulation Settings ; 49 | +---------------------------------------------------------------------------------------------------+------------------------+ 50 | ; Option ; Setting ; 51 | +---------------------------------------------------------------------------------------------------+------------------------+ 52 | ; Tool Name ; ModelSim-Altera (VHDL) ; 53 | ; Generate netlist for functional simulation only ; Off ; 54 | ; Time scale ; 1 ps ; 55 | ; Truncate long hierarchy paths ; Off ; 56 | ; Map illegal HDL characters ; Off ; 57 | ; Flatten buses into individual nodes ; Off ; 58 | ; Maintain hierarchy ; Off ; 59 | ; Bring out device-wide set/reset signals as ports ; Off ; 60 | ; Enable glitch filtering ; Off ; 61 | ; Do not write top level VHDL entity ; Off ; 62 | ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; 63 | ; Architecture name in VHDL output netlist ; structure ; 64 | ; Generate third-party EDA tool command script for RTL functional simulation ; Off ; 65 | ; Generate third-party EDA tool command script for gate-level simulation ; Off ; 66 | +---------------------------------------------------------------------------------------------------+------------------------+ 67 | 68 | 69 | +-------------------------------------------------------------------------------------+ 70 | ; Simulation Generated Files ; 71 | +-------------------------------------------------------------------------------------+ 72 | ; Generated Files ; 73 | +-------------------------------------------------------------------------------------+ 74 | ; D:/temp-development/alteraProjects/blink01/simulation/modelsim/blink01.vho ; 75 | ; D:/temp-development/alteraProjects/blink01/simulation/modelsim/blink01_fast.vho ; 76 | ; D:/temp-development/alteraProjects/blink01/simulation/modelsim/blink01_vhd.sdo ; 77 | ; D:/temp-development/alteraProjects/blink01/simulation/modelsim/blink01_vhd_fast.sdo ; 78 | +-------------------------------------------------------------------------------------+ 79 | 80 | 81 | +-----------------------------+ 82 | ; EDA Netlist Writer Messages ; 83 | +-----------------------------+ 84 | Info: ******************************************************************* 85 | Info: Running Quartus II 64-Bit EDA Netlist Writer 86 | Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 87 | Info: Processing started: Tue Jul 21 03:14:52 2020 88 | Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off blink01 -c blink01 89 | Info (204026): Generated files "blink01.vho", "blink01_fast.vho", "blink01_vhd.sdo" and "blink01_vhd_fast.sdo" in directory "D:/temp-development/alteraProjects/blink01/simulation/modelsim/" for EDA simulation tool 90 | Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings 91 | Info: Peak virtual memory: 4519 megabytes 92 | Info: Processing ended: Tue Jul 21 03:14:52 2020 93 | Info: Elapsed time: 00:00:00 94 | Info: Total CPU time (on all processors): 00:00:00 95 | 96 | 97 | -------------------------------------------------------------------------------- /output_files/blink01.fit.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/output_files/blink01.fit.rpt -------------------------------------------------------------------------------- /output_files/blink01.fit.smsg: -------------------------------------------------------------------------------- 1 | Extra Info (176273): Performing register packing on registers with non-logic cell location assignments 2 | Extra Info (176274): Completed register packing on registers with non-logic cell location assignments 3 | Extra Info (176236): Started Fast Input/Output/OE register processing 4 | Extra Info (176237): Finished Fast Input/Output/OE register processing 5 | Extra Info (176238): Start inferring scan chains for DSP blocks 6 | Extra Info (176239): Inferring scan chains for DSP blocks is complete 7 | Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density 8 | Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks 9 | -------------------------------------------------------------------------------- /output_files/blink01.fit.summary: -------------------------------------------------------------------------------- 1 | Fitter Status : Successful - Tue Jul 21 03:14:48 2020 2 | Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 3 | Revision Name : blink01 4 | Top-level Entity Name : blink01 5 | Family : Cyclone II 6 | Device : EP2C5T144C8 7 | Timing Models : Final 8 | Total logic elements : 58 / 4,608 ( 1 % ) 9 | Total combinational functions : 58 / 4,608 ( 1 % ) 10 | Dedicated logic registers : 27 / 4,608 ( < 1 % ) 11 | Total registers : 27 12 | Total pins : 5 / 89 ( 6 % ) 13 | Total virtual pins : 0 14 | Total memory bits : 0 / 119,808 ( 0 % ) 15 | Embedded Multiplier 9-bit elements : 0 / 26 ( 0 % ) 16 | Total PLLs : 0 / 2 ( 0 % ) 17 | -------------------------------------------------------------------------------- /output_files/blink01.flow.rpt: -------------------------------------------------------------------------------- 1 | Flow report for blink01 2 | Tue Jul 21 03:14:52 2020 3 | Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Flow Summary 11 | 3. Flow Settings 12 | 4. Flow Non-Default Global Settings 13 | 5. Flow Elapsed Time 14 | 6. Flow OS Summary 15 | 7. Flow Log 16 | 8. Flow Messages 17 | 9. Flow Suppressed Messages 18 | 19 | 20 | 21 | ---------------- 22 | ; Legal Notice ; 23 | ---------------- 24 | Copyright (C) 1991-2013 Altera Corporation 25 | Your use of Altera Corporation's design tools, logic functions 26 | and other software and tools, and its AMPP partner logic 27 | functions, and any output files from any of the foregoing 28 | (including device programming or simulation files), and any 29 | associated documentation or information are expressly subject 30 | to the terms and conditions of the Altera Program License 31 | Subscription Agreement, Altera MegaCore Function License 32 | Agreement, or other applicable license agreement, including, 33 | without limitation, that your use is for the sole purpose of 34 | programming logic devices manufactured by Altera and sold by 35 | Altera or its authorized distributors. Please refer to the 36 | applicable agreement for further details. 37 | 38 | 39 | 40 | +--------------------------------------------------------------------------------------+ 41 | ; Flow Summary ; 42 | +------------------------------------+-------------------------------------------------+ 43 | ; Flow Status ; Successful - Tue Jul 21 03:14:52 2020 ; 44 | ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; 45 | ; Revision Name ; blink01 ; 46 | ; Top-level Entity Name ; blink01 ; 47 | ; Family ; Cyclone II ; 48 | ; Device ; EP2C5T144C8 ; 49 | ; Timing Models ; Final ; 50 | ; Total logic elements ; 58 / 4,608 ( 1 % ) ; 51 | ; Total combinational functions ; 58 / 4,608 ( 1 % ) ; 52 | ; Dedicated logic registers ; 27 / 4,608 ( < 1 % ) ; 53 | ; Total registers ; 27 ; 54 | ; Total pins ; 5 / 89 ( 6 % ) ; 55 | ; Total virtual pins ; 0 ; 56 | ; Total memory bits ; 0 / 119,808 ( 0 % ) ; 57 | ; Embedded Multiplier 9-bit elements ; 0 / 26 ( 0 % ) ; 58 | ; Total PLLs ; 0 / 2 ( 0 % ) ; 59 | +------------------------------------+-------------------------------------------------+ 60 | 61 | 62 | +-----------------------------------------+ 63 | ; Flow Settings ; 64 | +-------------------+---------------------+ 65 | ; Option ; Setting ; 66 | +-------------------+---------------------+ 67 | ; Start date & time ; 07/21/2020 03:14:45 ; 68 | ; Main task ; Compilation ; 69 | ; Revision Name ; blink01 ; 70 | +-------------------+---------------------+ 71 | 72 | 73 | +---------------------------------------------------------------------------------------------------------------------+ 74 | ; Flow Non-Default Global Settings ; 75 | +-------------------------------------+--------------------------------+---------------+-------------+----------------+ 76 | ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; 77 | +-------------------------------------+--------------------------------+---------------+-------------+----------------+ 78 | ; COMPILER_SIGNATURE_ID ; 61762882887784.159532648410488 ; -- ; -- ; -- ; 79 | ; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ; 80 | ; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ; 81 | ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; 82 | ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; 83 | ; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; 84 | ; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; 85 | ; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; 86 | ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; 87 | +-------------------------------------+--------------------------------+---------------+-------------+----------------+ 88 | 89 | 90 | +-------------------------------------------------------------------------------------------------------------------------------+ 91 | ; Flow Elapsed Time ; 92 | +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ 93 | ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; 94 | +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ 95 | ; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4621 MB ; 00:00:01 ; 96 | ; Fitter ; 00:00:02 ; 1.0 ; 4789 MB ; 00:00:02 ; 97 | ; Assembler ; 00:00:01 ; 1.0 ; 4536 MB ; 00:00:01 ; 98 | ; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4529 MB ; 00:00:01 ; 99 | ; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4507 MB ; 00:00:00 ; 100 | ; Total ; 00:00:05 ; -- ; -- ; 00:00:05 ; 101 | +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ 102 | 103 | 104 | +----------------------------------------------------------------------------------------+ 105 | ; Flow OS Summary ; 106 | +---------------------------+------------------+-----------+------------+----------------+ 107 | ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; 108 | +---------------------------+------------------+-----------+------------+----------------+ 109 | ; Analysis & Synthesis ; oculus_rig ; Windows 7 ; 6.2 ; x86_64 ; 110 | ; Fitter ; oculus_rig ; Windows 7 ; 6.2 ; x86_64 ; 111 | ; Assembler ; oculus_rig ; Windows 7 ; 6.2 ; x86_64 ; 112 | ; TimeQuest Timing Analyzer ; oculus_rig ; Windows 7 ; 6.2 ; x86_64 ; 113 | ; EDA Netlist Writer ; oculus_rig ; Windows 7 ; 6.2 ; x86_64 ; 114 | +---------------------------+------------------+-----------+------------+----------------+ 115 | 116 | 117 | ------------ 118 | ; Flow Log ; 119 | ------------ 120 | quartus_map --read_settings_files=on --write_settings_files=off blink01 -c blink01 121 | quartus_fit --read_settings_files=off --write_settings_files=off blink01 -c blink01 122 | quartus_asm --read_settings_files=off --write_settings_files=off blink01 -c blink01 123 | quartus_sta blink01 -c blink01 124 | quartus_eda --read_settings_files=off --write_settings_files=off blink01 -c blink01 125 | 126 | 127 | 128 | -------------------------------------------------------------------------------- /output_files/blink01.jdi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /output_files/blink01.map.rpt: -------------------------------------------------------------------------------- 1 | Analysis & Synthesis report for blink01 2 | Tue Jul 21 03:14:45 2020 3 | Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Analysis & Synthesis Summary 11 | 3. Analysis & Synthesis Settings 12 | 4. Parallel Compilation 13 | 5. Analysis & Synthesis Source Files Read 14 | 6. Analysis & Synthesis Resource Usage Summary 15 | 7. Analysis & Synthesis Resource Utilization by Entity 16 | 8. General Register Statistics 17 | 9. Elapsed Time Per Partition 18 | 10. Analysis & Synthesis Messages 19 | 20 | 21 | 22 | ---------------- 23 | ; Legal Notice ; 24 | ---------------- 25 | Copyright (C) 1991-2013 Altera Corporation 26 | Your use of Altera Corporation's design tools, logic functions 27 | and other software and tools, and its AMPP partner logic 28 | functions, and any output files from any of the foregoing 29 | (including device programming or simulation files), and any 30 | associated documentation or information are expressly subject 31 | to the terms and conditions of the Altera Program License 32 | Subscription Agreement, Altera MegaCore Function License 33 | Agreement, or other applicable license agreement, including, 34 | without limitation, that your use is for the sole purpose of 35 | programming logic devices manufactured by Altera and sold by 36 | Altera or its authorized distributors. Please refer to the 37 | applicable agreement for further details. 38 | 39 | 40 | 41 | +--------------------------------------------------------------------------------------+ 42 | ; Analysis & Synthesis Summary ; 43 | +------------------------------------+-------------------------------------------------+ 44 | ; Analysis & Synthesis Status ; Successful - Tue Jul 21 03:14:45 2020 ; 45 | ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; 46 | ; Revision Name ; blink01 ; 47 | ; Top-level Entity Name ; blink01 ; 48 | ; Family ; Cyclone II ; 49 | ; Total logic elements ; 58 ; 50 | ; Total combinational functions ; 58 ; 51 | ; Dedicated logic registers ; 27 ; 52 | ; Total registers ; 27 ; 53 | ; Total pins ; 5 ; 54 | ; Total virtual pins ; 0 ; 55 | ; Total memory bits ; 0 ; 56 | ; Embedded Multiplier 9-bit elements ; 0 ; 57 | ; Total PLLs ; 0 ; 58 | +------------------------------------+-------------------------------------------------+ 59 | 60 | 61 | +----------------------------------------------------------------------------------------------------------------------+ 62 | ; Analysis & Synthesis Settings ; 63 | +----------------------------------------------------------------------------+--------------------+--------------------+ 64 | ; Option ; Setting ; Default Value ; 65 | +----------------------------------------------------------------------------+--------------------+--------------------+ 66 | ; Device ; EP2C5T144C8 ; ; 67 | ; Top-level entity name ; blink01 ; blink01 ; 68 | ; Family name ; Cyclone II ; Cyclone IV GX ; 69 | ; Use smart compilation ; Off ; Off ; 70 | ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; 71 | ; Enable compact report table ; Off ; Off ; 72 | ; Restructure Multiplexers ; Auto ; Auto ; 73 | ; Create Debugging Nodes for IP Cores ; Off ; Off ; 74 | ; Preserve fewer node names ; On ; On ; 75 | ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; 76 | ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; 77 | ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; 78 | ; State Machine Processing ; Auto ; Auto ; 79 | ; Safe State Machine ; Off ; Off ; 80 | ; Extract Verilog State Machines ; On ; On ; 81 | ; Extract VHDL State Machines ; On ; On ; 82 | ; Ignore Verilog initial constructs ; Off ; Off ; 83 | ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; 84 | ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; 85 | ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; 86 | ; Infer RAMs from Raw Logic ; On ; On ; 87 | ; Parallel Synthesis ; On ; On ; 88 | ; DSP Block Balancing ; Auto ; Auto ; 89 | ; NOT Gate Push-Back ; On ; On ; 90 | ; Power-Up Don't Care ; On ; On ; 91 | ; Remove Redundant Logic Cells ; Off ; Off ; 92 | ; Remove Duplicate Registers ; On ; On ; 93 | ; Ignore CARRY Buffers ; Off ; Off ; 94 | ; Ignore CASCADE Buffers ; Off ; Off ; 95 | ; Ignore GLOBAL Buffers ; Off ; Off ; 96 | ; Ignore ROW GLOBAL Buffers ; Off ; Off ; 97 | ; Ignore LCELL Buffers ; Off ; Off ; 98 | ; Ignore SOFT Buffers ; On ; On ; 99 | ; Limit AHDL Integers to 32 Bits ; Off ; Off ; 100 | ; Optimization Technique ; Balanced ; Balanced ; 101 | ; Carry Chain Length ; 70 ; 70 ; 102 | ; Auto Carry Chains ; On ; On ; 103 | ; Auto Open-Drain Pins ; On ; On ; 104 | ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; 105 | ; Auto ROM Replacement ; On ; On ; 106 | ; Auto RAM Replacement ; On ; On ; 107 | ; Auto Shift Register Replacement ; Auto ; Auto ; 108 | ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; 109 | ; Auto Clock Enable Replacement ; On ; On ; 110 | ; Strict RAM Replacement ; Off ; Off ; 111 | ; Allow Synchronous Control Signals ; On ; On ; 112 | ; Force Use of Synchronous Clear Signals ; Off ; Off ; 113 | ; Auto RAM to Logic Cell Conversion ; Off ; Off ; 114 | ; Auto Resource Sharing ; Off ; Off ; 115 | ; Allow Any RAM Size For Recognition ; Off ; Off ; 116 | ; Allow Any ROM Size For Recognition ; Off ; Off ; 117 | ; Allow Any Shift Register Size For Recognition ; Off ; Off ; 118 | ; Use LogicLock Constraints during Resource Balancing ; On ; On ; 119 | ; Ignore translate_off and synthesis_off directives ; Off ; Off ; 120 | ; Timing-Driven Synthesis ; Off ; Off ; 121 | ; Report Parameter Settings ; On ; On ; 122 | ; Report Source Assignments ; On ; On ; 123 | ; Report Connectivity Checks ; On ; On ; 124 | ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; 125 | ; Synchronization Register Chain Length ; 2 ; 2 ; 126 | ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; 127 | ; HDL message level ; Level2 ; Level2 ; 128 | ; Suppress Register Optimization Related Messages ; Off ; Off ; 129 | ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; 130 | ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; 131 | ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; 132 | ; Clock MUX Protection ; On ; On ; 133 | ; Auto Gated Clock Conversion ; Off ; Off ; 134 | ; Block Design Naming ; Auto ; Auto ; 135 | ; SDC constraint protection ; Off ; Off ; 136 | ; Synthesis Effort ; Auto ; Auto ; 137 | ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; 138 | ; Pre-Mapping Resynthesis Optimization ; Off ; Off ; 139 | ; Analysis & Synthesis Message Level ; Medium ; Medium ; 140 | ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; 141 | ; Resource Aware Inference For Block RAM ; On ; On ; 142 | ; Synthesis Seed ; 1 ; 1 ; 143 | +----------------------------------------------------------------------------+--------------------+--------------------+ 144 | 145 | 146 | Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. 147 | +-------------------------------------+ 148 | ; Parallel Compilation ; 149 | +----------------------------+--------+ 150 | ; Processors ; Number ; 151 | +----------------------------+--------+ 152 | ; Number detected on machine ; 4 ; 153 | ; Maximum allowed ; 1 ; 154 | +----------------------------+--------+ 155 | 156 | 157 | +-----------------------------------------------------------------------------------------------------------------------------------------+ 158 | ; Analysis & Synthesis Source Files Read ; 159 | +----------------------------------+-----------------+-----------------+--------------------------------------------------------+---------+ 160 | ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; 161 | +----------------------------------+-----------------+-----------------+--------------------------------------------------------+---------+ 162 | ; blink01.vhd ; yes ; User VHDL File ; D:/temp-development/alteraProjects/blink01/blink01.vhd ; ; 163 | +----------------------------------+-----------------+-----------------+--------------------------------------------------------+---------+ 164 | 165 | 166 | +-----------------------------------------------------+ 167 | ; Analysis & Synthesis Resource Usage Summary ; 168 | +---------------------------------------------+-------+ 169 | ; Resource ; Usage ; 170 | +---------------------------------------------+-------+ 171 | ; Estimated Total logic elements ; 58 ; 172 | ; ; ; 173 | ; Total combinational functions ; 58 ; 174 | ; Logic element usage by number of LUT inputs ; ; 175 | ; -- 4 input functions ; 8 ; 176 | ; -- 3 input functions ; 3 ; 177 | ; -- <=2 input functions ; 47 ; 178 | ; ; ; 179 | ; Logic elements by mode ; ; 180 | ; -- normal mode ; 12 ; 181 | ; -- arithmetic mode ; 46 ; 182 | ; ; ; 183 | ; Total registers ; 27 ; 184 | ; -- Dedicated logic registers ; 27 ; 185 | ; -- I/O registers ; 0 ; 186 | ; ; ; 187 | ; I/O pins ; 5 ; 188 | ; Embedded Multiplier 9-bit elements ; 0 ; 189 | ; Maximum fan-out node ; clk ; 190 | ; Maximum fan-out ; 27 ; 191 | ; Total fan-out ; 212 ; 192 | ; Average fan-out ; 2.36 ; 193 | +---------------------------------------------+-------+ 194 | 195 | 196 | +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 197 | ; Analysis & Synthesis Resource Utilization by Entity ; 198 | +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ 199 | ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; 200 | +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ 201 | ; |blink01 ; 58 (58) ; 27 (27) ; 0 ; 0 ; 0 ; 0 ; 5 ; 0 ; |blink01 ; work ; 202 | +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+ 203 | Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. 204 | 205 | 206 | +------------------------------------------------------+ 207 | ; General Register Statistics ; 208 | +----------------------------------------------+-------+ 209 | ; Statistic ; Value ; 210 | +----------------------------------------------+-------+ 211 | ; Total registers ; 27 ; 212 | ; Number of registers using Synchronous Clear ; 23 ; 213 | ; Number of registers using Synchronous Load ; 0 ; 214 | ; Number of registers using Asynchronous Clear ; 0 ; 215 | ; Number of registers using Asynchronous Load ; 0 ; 216 | ; Number of registers using Clock Enable ; 0 ; 217 | ; Number of registers using Preset ; 0 ; 218 | +----------------------------------------------+-------+ 219 | 220 | 221 | +-------------------------------+ 222 | ; Elapsed Time Per Partition ; 223 | +----------------+--------------+ 224 | ; Partition Name ; Elapsed Time ; 225 | +----------------+--------------+ 226 | ; Top ; 00:00:00 ; 227 | +----------------+--------------+ 228 | 229 | 230 | +-------------------------------+ 231 | ; Analysis & Synthesis Messages ; 232 | +-------------------------------+ 233 | Info: ******************************************************************* 234 | Info: Running Quartus II 64-Bit Analysis & Synthesis 235 | Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 236 | Info: Processing started: Tue Jul 21 03:14:44 2020 237 | Info: Command: quartus_map --read_settings_files=on --write_settings_files=off blink01 -c blink01 238 | Warning (20028): Parallel compilation is not licensed and has been disabled 239 | Info (12021): Found 2 design units, including 1 entities, in source file blink01.vhd 240 | Info (12022): Found design unit 1: blink01-rtl 241 | Info (12023): Found entity 1: blink01 242 | Info (12127): Elaborating entity "blink01" for the top level hierarchy 243 | Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" 244 | Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL 245 | Info (21057): Implemented 63 device resources after synthesis - the final resource count might be different 246 | Info (21058): Implemented 2 input pins 247 | Info (21059): Implemented 3 output pins 248 | Info (21061): Implemented 58 logic cells 249 | Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning 250 | Info: Peak virtual memory: 4622 megabytes 251 | Info: Processing ended: Tue Jul 21 03:14:45 2020 252 | Info: Elapsed time: 00:00:01 253 | Info: Total CPU time (on all processors): 00:00:01 254 | 255 | 256 | -------------------------------------------------------------------------------- /output_files/blink01.map.summary: -------------------------------------------------------------------------------- 1 | Analysis & Synthesis Status : Successful - Tue Jul 21 03:14:45 2020 2 | Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 3 | Revision Name : blink01 4 | Top-level Entity Name : blink01 5 | Family : Cyclone II 6 | Total logic elements : 58 7 | Total combinational functions : 58 8 | Dedicated logic registers : 27 9 | Total registers : 27 10 | Total pins : 5 11 | Total virtual pins : 0 12 | Total memory bits : 0 13 | Embedded Multiplier 9-bit elements : 0 14 | Total PLLs : 0 15 | -------------------------------------------------------------------------------- /output_files/blink01.pin: -------------------------------------------------------------------------------- 1 | -- Copyright (C) 1991-2013 Altera Corporation 2 | -- Your use of Altera Corporation's design tools, logic functions 3 | -- and other software and tools, and its AMPP partner logic 4 | -- functions, and any output files from any of the foregoing 5 | -- (including device programming or simulation files), and any 6 | -- associated documentation or information are expressly subject 7 | -- to the terms and conditions of the Altera Program License 8 | -- Subscription Agreement, Altera MegaCore Function License 9 | -- Agreement, or other applicable license agreement, including, 10 | -- without limitation, that your use is for the sole purpose of 11 | -- programming logic devices manufactured by Altera and sold by 12 | -- Altera or its authorized distributors. Please refer to the 13 | -- applicable agreement for further details. 14 | -- 15 | -- This is a Quartus II output file. It is for reporting purposes only, and is 16 | -- not intended for use as a Quartus II input file. This file cannot be used 17 | -- to make Quartus II pin assignments - for instructions on how to make pin 18 | -- assignments, please see Quartus II help. 19 | --------------------------------------------------------------------------------- 20 | 21 | 22 | 23 | --------------------------------------------------------------------------------- 24 | -- NC : No Connect. This pin has no internal connection to the device. 25 | -- DNU : Do Not Use. This pin MUST NOT be connected. 26 | -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). 27 | -- VCCIO : Dedicated power pin, which MUST be connected to VCC 28 | -- of its bank. 29 | -- Bank 1: 3.3V 30 | -- Bank 2: 3.3V 31 | -- Bank 3: 3.3V 32 | -- Bank 4: 3.3V 33 | -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. 34 | -- It can also be used to report unused dedicated pins. The connection 35 | -- on the board for unused dedicated pins depends on whether this will 36 | -- be used in a future design. One example is device migration. When 37 | -- using device migration, refer to the device pin-tables. If it is a 38 | -- GND pin in the pin table or if it will not be used in a future design 39 | -- for another purpose the it MUST be connected to GND. If it is an unused 40 | -- dedicated pin, then it can be connected to a valid signal on the board 41 | -- (low, high, or toggling) if that signal is required for a different 42 | -- revision of the design. 43 | -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. 44 | -- This pin should be connected to GND. It may also be connected to a 45 | -- valid signal on the board (low, high, or toggling) if that signal 46 | -- is required for a different revision of the design. 47 | -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND 48 | -- or leave it unconnected. 49 | -- RESERVED : Unused I/O pin, which MUST be left unconnected. 50 | -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. 51 | -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. 52 | -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. 53 | -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. 54 | --------------------------------------------------------------------------------- 55 | 56 | 57 | 58 | --------------------------------------------------------------------------------- 59 | -- Pin directions (input, output or bidir) are based on device operating in user mode. 60 | --------------------------------------------------------------------------------- 61 | 62 | Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition 63 | CHIP "blink01" ASSIGNED TO AN: EP2C5T144C8 64 | 65 | Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment 66 | ------------------------------------------------------------------------------------------------------------- 67 | ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : input : 3.3-V LVCMOS : : 1 : N 68 | ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : input : 3.3-V LVCMOS : : 1 : N 69 | led0 : 3 : output : 3.3-V LVCMOS : : 1 : Y 70 | RESERVED_INPUT : 4 : : : : 1 : 71 | VCCIO1 : 5 : power : : 3.3V : 1 : 72 | GND : 6 : gnd : : : : 73 | led1 : 7 : output : 3.3-V LVCMOS : : 1 : Y 74 | RESERVED_INPUT : 8 : : : : 1 : 75 | led2 : 9 : output : 3.3-V LVCMOS : : 1 : Y 76 | TDO : 10 : output : : : 1 : 77 | TMS : 11 : input : : : 1 : 78 | TCK : 12 : input : : : 1 : 79 | TDI : 13 : input : : : 1 : 80 | DATA0 : 14 : input : : : 1 : 81 | DCLK : 15 : : : : 1 : 82 | nCE : 16 : : : : 1 : 83 | clk : 17 : input : 3.3-V LVCMOS : : 1 : Y 84 | GND+ : 18 : : : : 1 : 85 | GND : 19 : gnd : : : : 86 | nCONFIG : 20 : : : : 1 : 87 | GND+ : 21 : : : : 1 : 88 | GND+ : 22 : : : : 1 : 89 | VCCIO1 : 23 : power : : 3.3V : 1 : 90 | RESERVED_INPUT : 24 : : : : 1 : 91 | RESERVED_INPUT : 25 : : : : 1 : 92 | RESERVED_INPUT : 26 : : : : 1 : 93 | RESERVED_INPUT : 27 : : : : 1 : 94 | RESERVED_INPUT : 28 : : : : 1 : 95 | VCCIO1 : 29 : power : : 3.3V : 1 : 96 | RESERVED_INPUT : 30 : : : : 1 : 97 | RESERVED_INPUT : 31 : : : : 1 : 98 | RESERVED_INPUT : 32 : : : : 1 : 99 | GND : 33 : gnd : : : : 100 | GND_PLL1 : 34 : gnd : : : : 101 | VCCD_PLL1 : 35 : power : : 1.2V : : 102 | GND_PLL1 : 36 : gnd : : : : 103 | VCCA_PLL1 : 37 : power : : 1.2V : : 104 | GNDA_PLL1 : 38 : gnd : : : : 105 | GND : 39 : gnd : : : : 106 | RESERVED_INPUT : 40 : : : : 4 : 107 | RESERVED_INPUT : 41 : : : : 4 : 108 | RESERVED_INPUT : 42 : : : : 4 : 109 | RESERVED_INPUT : 43 : : : : 4 : 110 | RESERVED_INPUT : 44 : : : : 4 : 111 | RESERVED_INPUT : 45 : : : : 4 : 112 | VCCIO4 : 46 : power : : 3.3V : 4 : 113 | RESERVED_INPUT : 47 : : : : 4 : 114 | RESERVED_INPUT : 48 : : : : 4 : 115 | GND : 49 : gnd : : : : 116 | VCCINT : 50 : power : : 1.2V : : 117 | RESERVED_INPUT : 51 : : : : 4 : 118 | RESERVED_INPUT : 52 : : : : 4 : 119 | RESERVED_INPUT : 53 : : : : 4 : 120 | VCCIO4 : 54 : power : : 3.3V : 4 : 121 | RESERVED_INPUT : 55 : : : : 4 : 122 | GND : 56 : gnd : : : : 123 | RESERVED_INPUT : 57 : : : : 4 : 124 | RESERVED_INPUT : 58 : : : : 4 : 125 | RESERVED_INPUT : 59 : : : : 4 : 126 | RESERVED_INPUT : 60 : : : : 4 : 127 | GND : 61 : gnd : : : : 128 | VCCINT : 62 : power : : 1.2V : : 129 | RESERVED_INPUT : 63 : : : : 4 : 130 | RESERVED_INPUT : 64 : : : : 4 : 131 | RESERVED_INPUT : 65 : : : : 4 : 132 | VCCIO4 : 66 : power : : 3.3V : 4 : 133 | RESERVED_INPUT : 67 : : : : 4 : 134 | GND : 68 : gnd : : : : 135 | RESERVED_INPUT : 69 : : : : 4 : 136 | RESERVED_INPUT : 70 : : : : 4 : 137 | RESERVED_INPUT : 71 : : : : 4 : 138 | RESERVED_INPUT : 72 : : : : 4 : 139 | RESERVED_INPUT : 73 : : : : 3 : 140 | RESERVED_INPUT : 74 : : : : 3 : 141 | RESERVED_INPUT : 75 : : : : 3 : 142 | ~LVDS41p/nCEO~ : 76 : output : 3.3-V LVCMOS : : 3 : N 143 | VCCIO3 : 77 : power : : 3.3V : 3 : 144 | GND : 78 : gnd : : : : 145 | RESERVED_INPUT : 79 : : : : 3 : 146 | RESERVED_INPUT : 80 : : : : 3 : 147 | RESERVED_INPUT : 81 : : : : 3 : 148 | nSTATUS : 82 : : : : 3 : 149 | CONF_DONE : 83 : : : : 3 : 150 | MSEL1 : 84 : : : : 3 : 151 | MSEL0 : 85 : : : : 3 : 152 | RESERVED_INPUT : 86 : : : : 3 : 153 | RESERVED_INPUT : 87 : : : : 3 : 154 | GND+ : 88 : : : : 3 : 155 | GND+ : 89 : : : : 3 : 156 | GND+ : 90 : : : : 3 : 157 | GND+ : 91 : : : : 3 : 158 | RESERVED_INPUT : 92 : : : : 3 : 159 | RESERVED_INPUT : 93 : : : : 3 : 160 | RESERVED_INPUT : 94 : : : : 3 : 161 | VCCIO3 : 95 : power : : 3.3V : 3 : 162 | RESERVED_INPUT : 96 : : : : 3 : 163 | RESERVED_INPUT : 97 : : : : 3 : 164 | GND : 98 : gnd : : : : 165 | RESERVED_INPUT : 99 : : : : 3 : 166 | RESERVED_INPUT : 100 : : : : 3 : 167 | RESERVED_INPUT : 101 : : : : 3 : 168 | VCCIO3 : 102 : power : : 3.3V : 3 : 169 | RESERVED_INPUT : 103 : : : : 3 : 170 | RESERVED_INPUT : 104 : : : : 3 : 171 | GND : 105 : gnd : : : : 172 | GND_PLL2 : 106 : gnd : : : : 173 | VCCD_PLL2 : 107 : power : : 1.2V : : 174 | GND_PLL2 : 108 : gnd : : : : 175 | VCCA_PLL2 : 109 : power : : 1.2V : : 176 | GNDA_PLL2 : 110 : gnd : : : : 177 | GND : 111 : gnd : : : : 178 | RESERVED_INPUT : 112 : : : : 2 : 179 | RESERVED_INPUT : 113 : : : : 2 : 180 | RESERVED_INPUT : 114 : : : : 2 : 181 | RESERVED_INPUT : 115 : : : : 2 : 182 | VCCIO2 : 116 : power : : 3.3V : 2 : 183 | GND : 117 : gnd : : : : 184 | RESERVED_INPUT : 118 : : : : 2 : 185 | RESERVED_INPUT : 119 : : : : 2 : 186 | RESERVED_INPUT : 120 : : : : 2 : 187 | RESERVED_INPUT : 121 : : : : 2 : 188 | RESERVED_INPUT : 122 : : : : 2 : 189 | GND : 123 : gnd : : : : 190 | VCCINT : 124 : power : : 1.2V : : 191 | RESERVED_INPUT : 125 : : : : 2 : 192 | RESERVED_INPUT : 126 : : : : 2 : 193 | VCCIO2 : 127 : power : : 3.3V : 2 : 194 | GND : 128 : gnd : : : : 195 | RESERVED_INPUT : 129 : : : : 2 : 196 | GND : 130 : gnd : : : : 197 | VCCINT : 131 : power : : 1.2V : : 198 | RESERVED_INPUT : 132 : : : : 2 : 199 | RESERVED_INPUT : 133 : : : : 2 : 200 | RESERVED_INPUT : 134 : : : : 2 : 201 | RESERVED_INPUT : 135 : : : : 2 : 202 | RESERVED_INPUT : 136 : : : : 2 : 203 | RESERVED_INPUT : 137 : : : : 2 : 204 | VCCIO2 : 138 : power : : 3.3V : 2 : 205 | RESERVED_INPUT : 139 : : : : 2 : 206 | GND : 140 : gnd : : : : 207 | RESERVED_INPUT : 141 : : : : 2 : 208 | RESERVED_INPUT : 142 : : : : 2 : 209 | RESERVED_INPUT : 143 : : : : 2 : 210 | sw0 : 144 : input : 3.3-V LVCMOS : : 2 : Y 211 | -------------------------------------------------------------------------------- /output_files/blink01.pof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/output_files/blink01.pof -------------------------------------------------------------------------------- /output_files/blink01.rbf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/output_files/blink01.rbf -------------------------------------------------------------------------------- /output_files/blink01.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/output_files/blink01.sof -------------------------------------------------------------------------------- /output_files/blink01.sta.summary: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------ 2 | TimeQuest Timing Analyzer Summary 3 | ------------------------------------------------------------ 4 | 5 | Type : Slow Model Setup 'clk' 6 | Slack : -5.342 7 | TNS : -105.573 8 | 9 | Type : Slow Model Hold 'clk' 10 | Slack : 0.499 11 | TNS : 0.000 12 | 13 | Type : Slow Model Minimum Pulse Width 'clk' 14 | Slack : -1.941 15 | TNS : -42.009 16 | 17 | Type : Fast Model Setup 'clk' 18 | Slack : -1.202 19 | TNS : -18.260 20 | 21 | Type : Fast Model Hold 'clk' 22 | Slack : 0.215 23 | TNS : 0.000 24 | 25 | Type : Fast Model Minimum Pulse Width 'clk' 26 | Slack : -1.380 27 | TNS : -28.380 28 | 29 | ------------------------------------------------------------ 30 | -------------------------------------------------------------------------------- /output_files/output_file-2020-07-21.jic: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/output_files/output_file-2020-07-21.jic -------------------------------------------------------------------------------- /output_files/output_file-2020-07-21.map: -------------------------------------------------------------------------------- 1 | BLOCK START ADDRESS END ADDRESS 2 | 3 | Page_0 0x00000000 0x00026A0F 4 | 5 | 6 | 7 | Notes: 8 | 9 | - Data checksum for this conversion is 0x05A06421 10 | 11 | - All the addresses in this file are byte addresses -------------------------------------------------------------------------------- /output_files/output_file.jic: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JamesHagerman/Altera-Cyclone-II-EP2C5T144-blink/2e37d632496923ff4e09cdcb14a170bf951fa636/output_files/output_file.jic -------------------------------------------------------------------------------- /output_files/output_file.map: -------------------------------------------------------------------------------- 1 | BLOCK START ADDRESS END ADDRESS 2 | 3 | Page_0 0x00000000 0x00026A0F 4 | 5 | 6 | 7 | Notes: 8 | 9 | - Data checksum for this conversion is 0x059F9A6B 10 | 11 | - All the addresses in this file are byte addresses -------------------------------------------------------------------------------- /simulation/modelsim/blink01.sft: -------------------------------------------------------------------------------- 1 | set tool_name "ModelSim-Altera (VHDL)" 2 | set corner_file_list { 3 | {{"Slow Model"} {blink01.vho blink01_vhd.sdo}} 4 | {{"Fast Model"} {blink01_fast.vho blink01_vhd_fast.sdo}} 5 | } 6 | -------------------------------------------------------------------------------- /simulation/modelsim/blink01_modelsim.xrf: -------------------------------------------------------------------------------- 1 | vendor_name = ModelSim 2 | source_file = 1, D:/temp-development/alteraProjects/blink01/blink01.vhd 3 | source_file = 1, D:/temp-development/alteraProjects/blink01/db/blink01.cbx.xml 4 | source_file = 1, d:/altera/13.0sp1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd 5 | source_file = 1, d:/altera/13.0sp1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd 6 | source_file = 1, d:/altera/13.0sp1/quartus/libraries/vhdl/ieee/timing_b.vhd 7 | source_file = 1, d:/altera/13.0sp1/quartus/libraries/vhdl/ieee/timing_p.vhd 8 | design_name = blink01 9 | instance = comp, \cnt[13]\, cnt[13], blink01, 1 10 | instance = comp, \cnt[14]\, cnt[14], blink01, 1 11 | instance = comp, \cnt[20]\, cnt[20], blink01, 1 12 | instance = comp, \cnt[23]\, cnt[23], blink01, 1 13 | instance = comp, \Add0~2\, Add0~2, blink01, 1 14 | instance = comp, \Add0~8\, Add0~8, blink01, 1 15 | instance = comp, \Add0~18\, Add0~18, blink01, 1 16 | instance = comp, \Add0~24\, Add0~24, blink01, 1 17 | instance = comp, \Add0~26\, Add0~26, blink01, 1 18 | instance = comp, \cnt[13]~45\, cnt[13]~45, blink01, 1 19 | instance = comp, \Add0~28\, Add0~28, blink01, 1 20 | instance = comp, \cnt[14]~47\, cnt[14]~47, blink01, 1 21 | instance = comp, \Add0~30\, Add0~30, blink01, 1 22 | instance = comp, \Add0~40\, Add0~40, blink01, 1 23 | instance = comp, \cnt[20]~59\, cnt[20]~59, blink01, 1 24 | instance = comp, \cnt[23]~65\, cnt[23]~65, blink01, 1 25 | instance = comp, \cnt[1]\, cnt[1], blink01, 1 26 | instance = comp, \Equal0~3\, Equal0~3, blink01, 1 27 | instance = comp, \Equal0~6\, Equal0~6, blink01, 1 28 | instance = comp, \clk~I\, clk, blink01, 1 29 | instance = comp, \clk~clkctrl\, clk~clkctrl, blink01, 1 30 | instance = comp, \Add0~0\, Add0~0, blink01, 1 31 | instance = comp, \cnt[0]\, cnt[0], blink01, 1 32 | instance = comp, \Add0~4\, Add0~4, blink01, 1 33 | instance = comp, \cnt[2]~23\, cnt[2]~23, blink01, 1 34 | instance = comp, \cnt[2]\, cnt[2], blink01, 1 35 | instance = comp, \Add0~6\, Add0~6, blink01, 1 36 | instance = comp, \cnt[3]~25\, cnt[3]~25, blink01, 1 37 | instance = comp, \cnt[3]\, cnt[3], blink01, 1 38 | instance = comp, \Add0~10\, Add0~10, blink01, 1 39 | instance = comp, \cnt[4]~27\, cnt[4]~27, blink01, 1 40 | instance = comp, \cnt[5]~29\, cnt[5]~29, blink01, 1 41 | instance = comp, \cnt[5]\, cnt[5], blink01, 1 42 | instance = comp, \Add0~12\, Add0~12, blink01, 1 43 | instance = comp, \cnt[6]~31\, cnt[6]~31, blink01, 1 44 | instance = comp, \cnt[6]\, cnt[6], blink01, 1 45 | instance = comp, \Add0~14\, Add0~14, blink01, 1 46 | instance = comp, \cnt[7]~33\, cnt[7]~33, blink01, 1 47 | instance = comp, \cnt[8]~35\, cnt[8]~35, blink01, 1 48 | instance = comp, \cnt[8]\, cnt[8], blink01, 1 49 | instance = comp, \Add0~16\, Add0~16, blink01, 1 50 | instance = comp, \cnt[9]~37\, cnt[9]~37, blink01, 1 51 | instance = comp, \cnt[10]~39\, cnt[10]~39, blink01, 1 52 | instance = comp, \cnt[10]\, cnt[10], blink01, 1 53 | instance = comp, \cnt[9]\, cnt[9], blink01, 1 54 | instance = comp, \Add0~20\, Add0~20, blink01, 1 55 | instance = comp, \cnt[11]~41\, cnt[11]~41, blink01, 1 56 | instance = comp, \cnt[11]\, cnt[11], blink01, 1 57 | instance = comp, \Add0~22\, Add0~22, blink01, 1 58 | instance = comp, \cnt[12]~43\, cnt[12]~43, blink01, 1 59 | instance = comp, \cnt[15]~49\, cnt[15]~49, blink01, 1 60 | instance = comp, \cnt[15]\, cnt[15], blink01, 1 61 | instance = comp, \cnt[12]\, cnt[12], blink01, 1 62 | instance = comp, \Add0~32\, Add0~32, blink01, 1 63 | instance = comp, \cnt[16]~51\, cnt[16]~51, blink01, 1 64 | instance = comp, \cnt[16]\, cnt[16], blink01, 1 65 | instance = comp, \Add0~34\, Add0~34, blink01, 1 66 | instance = comp, \Add0~36\, Add0~36, blink01, 1 67 | instance = comp, \Add0~38\, Add0~38, blink01, 1 68 | instance = comp, \Add0~42\, Add0~42, blink01, 1 69 | instance = comp, \cnt[17]~53\, cnt[17]~53, blink01, 1 70 | instance = comp, \cnt[18]~55\, cnt[18]~55, blink01, 1 71 | instance = comp, \cnt[19]~57\, cnt[19]~57, blink01, 1 72 | instance = comp, \cnt[21]~61\, cnt[21]~61, blink01, 1 73 | instance = comp, \cnt[21]\, cnt[21], blink01, 1 74 | instance = comp, \Add0~44\, Add0~44, blink01, 1 75 | instance = comp, \cnt[22]~63\, cnt[22]~63, blink01, 1 76 | instance = comp, \cnt[22]\, cnt[22], blink01, 1 77 | instance = comp, \Add0~46\, Add0~46, blink01, 1 78 | instance = comp, \Add0~48\, Add0~48, blink01, 1 79 | instance = comp, \cnt[24]~67\, cnt[24]~67, blink01, 1 80 | instance = comp, \cnt[24]\, cnt[24], blink01, 1 81 | instance = comp, \cnt[18]\, cnt[18], blink01, 1 82 | instance = comp, \cnt[17]\, cnt[17], blink01, 1 83 | instance = comp, \cnt[19]\, cnt[19], blink01, 1 84 | instance = comp, \Equal0~5\, Equal0~5, blink01, 1 85 | instance = comp, \cnt[4]\, cnt[4], blink01, 1 86 | instance = comp, \cnt[7]\, cnt[7], blink01, 1 87 | instance = comp, \Equal0~1\, Equal0~1, blink01, 1 88 | instance = comp, \Equal0~2\, Equal0~2, blink01, 1 89 | instance = comp, \Equal0~0\, Equal0~0, blink01, 1 90 | instance = comp, \Equal0~4\, Equal0~4, blink01, 1 91 | instance = comp, \Equal0~7\, Equal0~7, blink01, 1 92 | instance = comp, \blink~0\, blink~0, blink01, 1 93 | instance = comp, \sw0~I\, sw0, blink01, 1 94 | instance = comp, \led1~0\, led1~0, blink01, 1 95 | instance = comp, \led1~reg0\, led1~reg0, blink01, 1 96 | instance = comp, \led0~I\, led0, blink01, 1 97 | instance = comp, \led1~I\, led1, blink01, 1 98 | instance = comp, \led2~I\, led2, blink01, 1 99 | --------------------------------------------------------------------------------