├── LICENSE ├── README.md ├── bsp └── imxrt1170_a0 │ ├── flash_api │ ├── bl_api.c │ ├── bl_api.h │ └── flexspi_nor_flash.h │ └── flash_drv │ ├── bootloader_common.h │ ├── flexspi_nor_flash.c │ ├── flexspi_nor_flash.h │ ├── flexspi_soc.c │ ├── fsl_flexspi.c │ ├── fsl_flexspi.h │ ├── fusemap.h │ ├── peripherals_pinmux.h │ └── target_config.h ├── doc ├── Architecture_Design.pptx ├── kFlashFile_Design0.PNG ├── kFlashFile_Design_Deinit.PNG ├── kFlashFile_Design_Init.PNG ├── kFlashFile_Design_Save0.PNG ├── kFlashFile_Design_Save1.PNG ├── kFlashFile_Design_Save2.PNG ├── kFlashFile_Flow_init.PNG ├── kFlashFile_Flow_save.PNG └── kFlashFile_Framework.PNG └── src ├── kflash_drv.c ├── kflash_drv.h ├── kflash_file.c └── kflash_file.h /LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # kFlashFile 2 | 3 | ## 一、简介 4 | 5 | kFlashFile 是一个基于 NOR Flash 的轻量级文件数据存储方案，用于需要断电数据保存的项目。 6 | 7 | kFlashFile 主要为 i.MXRT 系列设计，但其分层框架设计使其也可轻松移植到其他 MCU 平台。 8 | 9 | kFlashFile 从设计上分为三层： 10 | 11 | > * 最底层是Driver层：即Low-level驱动，这层是MCU相关的，对于i.MXRT来说，就是FlexSPI模块的驱动。 12 | > * 中间是Adapter层：主要用于适配底层Driver，不同MCU其Driver接口函数可能不同，因此会在这一层做到接口统一。 13 | > * 最顶层是API层：纯软件逻辑设计来实现文件数据存储，提供了四个非常简易的API。 14 | 15 | ![](https://raw.githubusercontent.com/JayHeng/kFlashFile/master/doc/kFlashFile_Framework.PNG) 16 | 17 | ## 二、设计 18 | 19 | ### 2.1 API定义 20 | 21 | kFlashFile 是一个文件数据存储的设计，file_read()、file_save()是两个必备的 API，此外也提供业界通用 API 接口file_init()、file_deinit()。 22 | 23 | > * kflash_file_init(): 用于初次分配Flash空间来存储文件数据，并且指定文件长度。如果当前指定的Flash空间里存在有效文件数据，那么继续复用。 24 | > * kflash_file_read(): 用于获取当前有效存储的文件数据，文件数据可以部分读取。 25 | > * kflash_file_save(): 用于实时写入最新的文件数据，文件数据可以部分更新。 26 | > * kflash_file_deinit(): 用于清除当前分配的Flash空间里的文件数据，以便下次重新分配。 27 | 28 | ```C 29 | status_t kflash_file_init(kflash_file_t *flashFile, uint32_t memStart, uint32_t memSize, uint32_t fileSize); 30 | status_t kflash_file_read(kflash_file_t *flashFile, uint32_t offset, uint8_t *data, uint32_t size); 31 | status_t kflash_file_save(kflash_file_t *flashFile, uint32_t offset, uint8_t *data, uint32_t size); 32 | status_t kflash_file_deinit(kflash_file_t *flashFile); 33 | ``` 34 | 35 | ### 2.2 空间分配 36 | 37 | kFlashFile 将分配的 Flash 空间分成两个部分，前面是文件数据区（Data Sectors），后面是文件头区（Header Sectors）。 38 | 39 | 文件数据区：从区内起始地址开始按序存放一份份文件数据，只要文件数据出现无法覆盖的更新（即 Flash 无法改写的特性），便会在下一个新地址重新存储。如果数据区满了，便擦除区内起始地址处的历史文件数据，继续循环存储。 40 | 41 | 文件头区：区内 Sector 起始地址放一个 Magic 值（4字节），用于标识文件头。然后开始按序记录一份份文件数据在文件数据区里的位置信息（默认用 2byte 去记录一份文件数据的位置）。如果当前 Header Sector 存储满了，便换到下一个 Header Sector 继续记录。 42 | 43 | ![](https://raw.githubusercontent.com/JayHeng/kFlashFile/master/doc/kFlashFile_Design0.PNG) 44 | 45 | ### 2.3 API主参数 46 | 47 | kFlashFile 设计上使用 kflash_file_t 型作为 API 主参数，这个参数原型定义如下： 48 | 49 | ```C 50 | typedef struct { 51 | uint32_t managedStart; 52 | uint32_t managedSize; 53 | uint32_t activedStart; 54 | uint32_t activedSize; 55 | uint32_t recordedIdx; 56 | uint32_t recordedPos; 57 | uint8_t buffer[KFLASH_MAX_FILE_SIZE]; 58 | } kflash_file_t; 59 | ``` 60 | 61 | > * managedStart： 表示文件存储区映射首地址，即 kflash_file_init() 调用时的 memStart 值加上 Flash 在内存里映射首地址，managedStart 需要以 Flash Sector 大小对齐。 62 | > * managedSize： 表示文件存储区总大小，即 kflash_file_init() 调用时的 memSize 值，需要是 Flash Sector 大小的整数倍。 63 | > * activedStart： 表示当前有效文件数据存储的映射首地址，需要以 Flash Page 大小对齐。 64 | > * activedSize： 表示当前有效文件数据长度，需要是 Flash Page 大小的整数倍。 65 | > * recordedIdx： 表示当前有效文件头所在的 Header Sector 索引。 66 | > * recordedPos： 表示 Header Sector 中用于存储当前有效文件数据位置信息的区域偏移。 67 | > * buffer[]： 当前有效的文件数据暂存区。 68 | 69 | ## 三、实现 70 | 71 | ### 3.1 Driver层 72 | 73 | 在 i.MXRT 系列上，kFlashFile 的 Driver 层即 FlexSPI NOR 驱动，这个驱动既可以采用 MCU SDK 版本，也可以采用 BootROM 版本。 74 | 75 | 此处推荐 BootROM 版本的 FlexSPI NOR 驱动，因为这个驱动历经多个 MCU ROM 的洗礼，已经相当成熟稳定。这里简单讲下其中 Flash 操作的函数： 76 | 77 | > * flexspi_nor_flash_erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length)：这个函数实现Flash擦除，虽然形参里是任意设定的start, address，但实际擦除还是以Sector对齐的，函数内部会对start和address做自动对齐。 78 | > * flexspi_nor_flash_page_program(uint32_t instance, flexspi_nor_config_t *config, uint32_t dstAddr, const uint32_t *src)：这个函数实现Flash编程，一次固定写一整个Page大小的数据，即使dstAddr不是以Page对齐，实际写入的Page数据也不会跨物理Page（会自动跳回同一个物理Page首地址，这是Flash自身特性）。 79 | 80 | 因为 flexspi_nor_flash_page_program() 每次都要固定编程整个 Page 数据，不够灵活，因此我新写了一个 flexspi_nor_flash_program() 函数，这个函数支持编程用户自定义长度的数据，并且支持跨物理 Page 去写： 81 | 82 | > * flexspi_nor_flash_program(uint32_t instance, flexspi_nor_config_t *config, uint32_t dstAddr, const uint32_t *src, uint32_t length)： 83 | 84 | 需要特别注意，对于 SDR 模式的 Flash，最小编程长度可以是 1Byte；而 DDR 模式的 Flash，最小编程长度应是 2Bytes（如果这 2Bytes 地址上有一个 Byte 内容是 0xFF，该 Byte 依旧可以被再次编程）。 85 | 86 | 此外 flexspi_nor_flash_program() 函数有一个限制，即传入的 src 源数据首地址必须 4 字节对齐，哪怕你只想写入 2 个字节，这是 FlexSPI 模块底层对驱动的要求。 87 | 88 | ### 3.2 Adapter层 89 | 90 | kFlashFile 的 Adapter 层是对 Driver 层做了一层封装，用于屏蔽硬件相关特性。该层与 MCU 以及板载 Flash 型号息息相关。下面的宏定义适用 i.MXRT1170 芯片以及连接在 FlexSPI1 上的 Octal Flash（MX25UM51345）： 91 | 92 | ```C 93 | // 表示 Flash 连接的是 FlexSPI1 94 | #define KFLASH_INSTANCE (1) 95 | // BootROM FlexSPI 驱动对 Octal Flash 支持的简易配置值 96 | #define KFLASH_CONFIG_OPTION (0xc0403007) 97 | 98 | // FlexSPI1 在系统内存中的映射首地址 99 | #define KFLASH_BASE_ADDRESS (0x30000000) 100 | // 默认的 Flash Sector/Page 大小（如果 Flash 里有 SFDP，则此处定义无效） 101 | #define KFLASH_SECTOR_SIZE (0x1000) 102 | #define KFLASH_PAGE_SIZE (256) 103 | 104 | // FlexSPI 编程接口对传入的 src 源数据首地址必须 4 字节对齐 105 | #define KFLASH_PROGRAM_ALIGNMENT (4) 106 | // Flash SDR 模式为 1，DDR 模式为 2 107 | #define KFLASH_PROGRAM_UNIT (2) 108 | ``` 109 | 110 | kFlashFile 的 Adapter 层接口函数如下，参数是硬件无关的，因此上层可以轻松基于这些接口函数做纯软件逻辑设计。 111 | 112 | ```C 113 | status_t kflash_drv_init(void); 114 | uint32_t kflash_drv_get_info(kflash_mem_info_t flashInfo); 115 | status_t kflash_drv_erase_region(uint32_t start, uint32_t length); 116 | status_t kflash_drv_program_region(uint32_t dstAddr, const uint32_t *src, uint32_t length); 117 | ``` 118 | 119 | ### 3.3 API层 120 | 121 | kFlashFile 的 API 功能设计思路前面介绍过了，这里介绍具体代码实现，先来看几个关键的宏定义： 122 | 123 | ```C 124 | // 设置 Header Sector 的个数，至少是 2 个 125 | #define KFLASH_HDR_SECTORS (2) 126 | // 设置 Header Sector 中用于存储当前有效文件数据位置信息的区域存储类型 127 | // uint16_t 最多可记录 65536 个位置，最大可支持的 Data 区域大小为 65536 * 文件数据长度 128 | #define KFLASH_HDR_POS_TYPE uint16_t /* uint16_t or uint32_t */ 129 | // 设置总分配的 Flash 长度（Data+Header Sector 的个数），至少是 4 个 130 | #define KFLASH_MIN_SECTORS (KFLASH_HDR_SECTORS + 2) 131 | // 设置最大支持的文件数据长度，需是 Flash Page 的整数倍 132 | #define KFLASH_MAX_FILE_SIZE (KFLASH_PAGE_SIZE * 2) 133 | ``` 134 | 135 | #### 3.3.1 init() 136 | 137 | kflash_file_init() 函数处理流程如下： 138 | 139 | ![](https://raw.githubusercontent.com/JayHeng/kFlashFile/master/doc/kFlashFile_Flow_init.PNG) 140 | 141 | 如果是首次指定 Flash 空间，那么直接将全部空间擦除干净，并在第一个 Header Sector 中写入初始文件头（Magic + 文件数据位置值 0），即最新有效文件数据在 Flash 空间文件数据区的首地址。 142 | 143 | ![](https://raw.githubusercontent.com/JayHeng/kFlashFile/master/doc/kFlashFile_Design_Init.PNG) 144 | 145 | 这里有一个特殊的设计，文件数据区其实并不是直接存储用户写入的文件数据，而是将用户文件数据全部按位取反之后再存储进 Flash。这里假定用户数据初始应该是全 0，然后更改主要是将 0 值改为其他值，取反之后，正好对应 Flash 里的 bit1 编程为 bit0（Flash 擦除后是全 0xFF），这样可以充分利用 Flash 覆盖操作以减少擦除次数。 146 | 147 | 函数中比较关键的步骤是找寻当前 Flash 空间中是否存在有效文件数据，方法是遍历 Header Sector，发现存在 Magic 便继续寻找最新文件数据位置信息存放的区域（默认 2 字节），按照前面的设计，只需要按序读取区域内容，直到遇到 0xFFFF 为止。 148 | 149 | #### 3.3.2 read() 150 | 151 | kflash_file_read() 函数最简单了，直接从缓存区 buffer 里获取数据即可，因为每次更新文件数据操作完成之后都会将最新文件数据放在 buffer 里。 152 | 153 | #### 3.3.3 save() 154 | 155 | kflash_file_save() 函数是最核心的函数了，这里逻辑比较复杂，涉及文件数据区全部满了之后的动作，以及文件头区某个 Sector 满了的动作。其处理流程如下： 156 | 157 | ![](https://raw.githubusercontent.com/JayHeng/kFlashFile/master/doc/kFlashFile_Flow_save.PNG) 158 | 159 | 当有一个新文件数据要求保存时，首先会判断这个文件能不能在 Flash 中直接覆盖存储，如果能，那就直接覆盖存储，文件头完全不需要更新，这种情况比较简单。 160 | 161 | ![](https://raw.githubusercontent.com/JayHeng/kFlashFile/master/doc/kFlashFile_Design_Save0.PNG) 162 | 163 | 如果新文件数据无法直接覆盖存储，那么首先判断文件数据区是否满了，如果上一个文件数据已经存在了文件数据区的最后位置，此时需要擦除数据区第一个 Sector 从头开始存储。如果没有到最后位置，那就按序往下存储。 164 | 165 | ![](https://raw.githubusercontent.com/JayHeng/kFlashFile/master/doc/kFlashFile_Design_Save1.PNG) 166 | 167 | 新文件数据已经保存到数据区之后，此时需要处理文件头，记录这个新文件数据的位置。如果文件头区已经记录到当前 Sector 的最后位置，需要切换到下一个 Sector 开始存储，切换存储完新位置后，将之前 Sector 擦除。如果没有，那就按序在当前 Sector 继续记录。 168 | 169 | ![](https://raw.githubusercontent.com/JayHeng/kFlashFile/master/doc/kFlashFile_Design_Save2.PNG) 170 | 171 | #### 3.3.4 deinit() 172 | 173 | kflash_file_deinit() 函数也比较简单，就是将文件头区域 Header Sectors 全部擦除即可，文件数据区内容可以不用管，下次重新分配 Flash 时会做擦除。 174 | 175 | ![](https://raw.githubusercontent.com/JayHeng/kFlashFile/master/doc/kFlashFile_Design_Deinit.PNG) 176 | -------------------------------------------------------------------------------- /bsp/imxrt1170_a0/flash_api/bl_api.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018-2019 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | * 7 | */ 8 | #include "bl_api.h" 9 | 10 | /******************************************************************************* 11 | * Definitions 12 | ******************************************************************************/ 13 | 14 | /******************************************************************************* 15 | * Prototypes 16 | ******************************************************************************/ 17 | 18 | /******************************************************************************* 19 | * Variables 20 | ******************************************************************************/ 21 | 22 | /******************************************************************************* 23 | * Codes 24 | ******************************************************************************/ 25 | 26 | void bl_api_init(void) 27 | { 28 | } 29 | 30 | /******************************************************************************* 31 | * FlexSPI NOR driver 32 | ******************************************************************************/ 33 | status_t flexspi_nor_flash_init(uint32_t instance, flexspi_nor_config_t *config) 34 | { 35 | return g_bootloaderTree->flexSpiNorDriver->init(instance, config); 36 | } 37 | 38 | status_t flexspi_nor_flash_page_program(uint32_t instance, 39 | flexspi_nor_config_t *config, 40 | uint32_t dstAddr, 41 | const uint32_t *src) 42 | { 43 | return g_bootloaderTree->flexSpiNorDriver->page_program(instance, config, dstAddr, src); 44 | } 45 | 46 | status_t flexspi_nor_flash_erase_all(uint32_t instance, flexspi_nor_config_t *config) 47 | { 48 | return g_bootloaderTree->flexSpiNorDriver->erase_all(instance, config); 49 | } 50 | 51 | status_t flexspi_nor_get_config(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option) 52 | { 53 | return g_bootloaderTree->flexSpiNorDriver->get_config(instance, config, option); 54 | } 55 | 56 | status_t flexspi_nor_flash_erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length) 57 | { 58 | return g_bootloaderTree->flexSpiNorDriver->erase(instance, config, start, length); 59 | } 60 | 61 | status_t flexspi_nor_flash_read( 62 | uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes) 63 | { 64 | return g_bootloaderTree->flexSpiNorDriver->read(instance, config, dst, start, bytes); 65 | } 66 | 67 | status_t flexspi_update_lut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq) 68 | { 69 | return g_bootloaderTree->flexSpiNorDriver->update_lut(instance, seqIndex, lutBase, numberOfSeq); 70 | } 71 | 72 | status_t flexspi_command_xfer(uint32_t instance, flexspi_xfer_t *xfer) 73 | { 74 | return g_bootloaderTree->flexSpiNorDriver->xfer(instance, xfer); 75 | } 76 | 77 | void flexspi_clear_cache(uint32_t instance) 78 | { 79 | g_bootloaderTree->flexSpiNorDriver->clear_cache(instance); 80 | } 81 | 82 | status_t flexspi_update_clock_source(uint32_t instance, uint32_t source) 83 | { 84 | return g_bootloaderTree->flexSpiNorDriver->set_clock_source(instance, source); 85 | } 86 | -------------------------------------------------------------------------------- /bsp/imxrt1170_a0/flash_api/bl_api.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018-2019 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | * 7 | */ 8 | #ifndef __BL_API_H__ 9 | #define __BL_API_H__ 10 | 11 | #include "fsl_device_registers.h" 12 | #include "flexspi_nor_flash.h" 13 | 14 | typedef struct 15 | { 16 | uint32_t version; 17 | status_t (*init)(uint32_t instance, flexspi_nor_config_t *config); 18 | status_t (*page_program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dstAddr, const uint32_t *src); 19 | status_t (*erase_all)(uint32_t instance, flexspi_nor_config_t *config); 20 | status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); 21 | status_t (*read)(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes); 22 | void (*clear_cache)(uint32_t instance); 23 | status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer); 24 | status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq); 25 | status_t (*get_config)(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option); 26 | status_t (*erase_sector)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); 27 | status_t (*erase_block)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); 28 | void (*hw_reset)(uint32_t instance, uint32_t resetLogic); 29 | status_t (*wait_busy)(uint32_t instance, flexspi_nor_config_t *config, bool isParallelMode, uint32_t address); 30 | status_t (*set_clock_source)(uint32_t instance, uint32_t clockSrc); 31 | void (*config_clock)(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode); 32 | 33 | } flexspi_nor_flash_driver_t; 34 | 35 | typedef struct 36 | { 37 | void (*runBootloader)(void *arg); //!< Function to start the bootloader executing 38 | const uint32_t version; //!< Bootloader version number 39 | const char *copyright; //!< Bootloader Copyright 40 | const flexspi_nor_flash_driver_t *flexSpiNorDriver; //!< FlexSPI NOR Flash API 41 | } bootloader_api_entry_t; 42 | 43 | enum 44 | { 45 | kEnterBootloader_Tag = 0xEB, 46 | kEnterBootloader_Mode_Default = 0, 47 | kEnterBootloader_Mode_SerialDownloader = 1, 48 | 49 | kEnterBootloader_SerialInterface_Auto = 0, 50 | kEnterBootloader_SerialInterface_USB = 1, 51 | kEnterBootloader_SerialInterface_UART = 2, 52 | 53 | kEnterBootloader_ImageIndex_Max = 3, 54 | }; 55 | 56 | typedef union 57 | { 58 | struct 59 | { 60 | uint32_t imageIndex : 4; 61 | uint32_t reserved : 12; 62 | uint32_t serialBootInterface : 4; 63 | uint32_t bootMode : 4; 64 | uint32_t tag : 8; 65 | } B; 66 | uint32_t U; 67 | } run_bootloader_ctx_t; 68 | 69 | /* ROM API Tree address */ 70 | #define g_bootloaderTree (*(bootloader_api_entry_t **)0x0020001c) 71 | 72 | static inline void runBootloader(run_bootloader_ctx_t *ctx) 73 | { 74 | g_bootloaderTree->runBootloader(ctx); 75 | } 76 | 77 | #endif //__BL_API_H__ 78 | -------------------------------------------------------------------------------- /bsp/imxrt1170_a0/flash_api/flexspi_nor_flash.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018-2019 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | * 7 | */ 8 | 9 | #ifndef __FLEXSPI_NOR_FLASH_H__ 10 | #define __FLEXSPI_NOR_FLASH_H__ 11 | 12 | #include "fsl_common.h" 13 | 14 | /********************************************************************************************************************** 15 | * Definitions 16 | *********************************************************************************************************************/ 17 | 18 | /* FLEXSPI memory config block related defintions */ 19 | #define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian 20 | #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 21 | #define FLEXSPI_CFG_BLK_SIZE (512) 22 | 23 | #define CMD_SDR 0x01 24 | #define CMD_DDR 0x21 25 | #define RADDR_SDR 0x02 26 | #define RADDR_DDR 0x22 27 | #define CADDR_SDR 0x03 28 | #define CADDR_DDR 0x23 29 | #define MODE1_SDR 0x04 30 | #define MODE1_DDR 0x24 31 | #define MODE2_SDR 0x05 32 | #define MODE2_DDR 0x25 33 | #define MODE4_SDR 0x06 34 | #define MODE4_DDR 0x26 35 | #define MODE8_SDR 0x07 36 | #define MODE8_DDR 0x27 37 | #define WRITE_SDR 0x08 38 | #define WRITE_DDR 0x28 39 | #define READ_SDR 0x09 40 | #define READ_DDR 0x29 41 | #define LEARN_SDR 0x0A 42 | #define LEARN_DDR 0x2A 43 | #define DATSZ_SDR 0x0B 44 | #define DATSZ_DDR 0x2B 45 | #define DUMMY_SDR 0x0C 46 | #define DUMMY_DDR 0x2C 47 | #define DUMMY_RWDS_SDR 0x0D 48 | #define DUMMY_RWDS_DDR 0x2D 49 | #define JMP_ON_CS 0x1F 50 | #define STOP 0 51 | 52 | #define FLEXSPI_1PAD 0 53 | #define FLEXSPI_2PAD 1 54 | #define FLEXSPI_4PAD 2 55 | #define FLEXSPI_8PAD 3 56 | 57 | #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 58 | (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ 59 | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 60 | 61 | //!@brief Defintions for FlexSPI Serial Clock Frequency 62 | typedef enum _FlexSpiSerialClockFreq 63 | { 64 | kFlexSpiSerialClk_NoChange = 0, 65 | kFlexSpiSerialClk_30MHz = 1, 66 | kFlexSpiSerialClk_50MHz = 2, 67 | kFlexSpiSerialClk_60MHz = 3, 68 | kFlexSpiSerialClk_75MHz = 4, 69 | kFlexSpiSerialClk_80MHz = 5, 70 | kFlexSpiSerialClk_100MHz = 6, 71 | kFlexSpiSerialClk_120MHz = 7, 72 | kFlexSpiSerialClk_133MHz = 8, 73 | kFlexSpiSerialClk_166MHz = 9, 74 | } flexspi_serial_clk_freq_t; 75 | 76 | //!@brief FlexSPI clock configuration type 77 | enum 78 | { 79 | kFlexSpiClk_SDR, //!< Clock configure for SDR mode 80 | kFlexSpiClk_DDR, //!< Clock configurat for DDR mode 81 | }; 82 | 83 | //!@brief FlexSPI Read Sample Clock Source definition 84 | typedef enum _FlashReadSampleClkSource 85 | { 86 | kFlexSPIReadSampleClk_LoopbackInternally = 0, 87 | kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, 88 | kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, 89 | kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, 90 | } flexspi_read_sample_clk_t; 91 | 92 | /* status code for flexspi */ 93 | enum _flexspi_status 94 | { 95 | kStatus_FLEXSPI_SequenceExecutionTimeout = 96 | MAKE_STATUS(kStatusGroup_FLEXSPI, 0), //!< Status for Sequence Execution timeout 97 | kStatus_FLEXSPI_InvalidSequence = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), //!< Status for Invalid Sequence 98 | kStatus_FLEXSPI_DeviceTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 2), //!< Status for Device timeout 99 | }; 100 | 101 | //!@brief Misc feature bit definitions 102 | enum 103 | { 104 | kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable 105 | kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable 106 | kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable 107 | kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable 108 | kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable 109 | kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable 110 | kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. 111 | kFlexSpiMiscOffset_UseValidTimeForAllFreq = 7, //!< Bit for DLLCR settings under all modes 112 | kFlexSpiMiscOffset_SecondPinMux = 8, //!< Bit for Second Pinmux group 113 | }; 114 | 115 | //!@brief Flash Type Definition 116 | enum 117 | { 118 | kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR 119 | kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND 120 | }; 121 | 122 | //!@brief Flash Pad Definitions 123 | enum 124 | { 125 | kSerialFlash_1Pad = 1, 126 | kSerialFlash_2Pads = 2, 127 | kSerialFlash_4Pads = 4, 128 | kSerialFlash_8Pads = 8, 129 | }; 130 | 131 | //!@brief FlexSPI LUT Sequence structure 132 | typedef struct _lut_sequence 133 | { 134 | uint8_t seqNum; //!< Sequence Number, valid number: 1-16 135 | uint8_t seqId; //!< Sequence Index, valid number: 0-15 136 | uint16_t reserved; 137 | } flexspi_lut_seq_t; 138 | 139 | //!@brief Flash Configuration Command Type 140 | enum 141 | { 142 | kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc 143 | kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command 144 | kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode 145 | kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode 146 | kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode 147 | kDeviceConfigCmdType_Reset, //!< Reset device command 148 | }; 149 | 150 | typedef struct 151 | { 152 | uint8_t time_100ps; // Data valid time, in terms of 100ps 153 | uint8_t delay_cells; // Data valid time, in terms of delay cells 154 | } flexspi_dll_time_t; 155 | 156 | //!@brief FlexSPI Memory Configuration Block 157 | typedef struct _FlexSPIConfig 158 | { 159 | uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL 160 | uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix 161 | uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use 162 | uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 163 | uint8_t dataHoldTime; //!< [0x00d-0x00d] Data hold time, default value: 3 164 | uint8_t dataSetupTime; //!< [0x00e-0x00e] Date setup time, default value: 3 165 | uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For 166 | //! Serial NAND, need to refer to datasheet 167 | uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable 168 | uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, 169 | //! Generic configuration, etc. 170 | uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for 171 | //! DPI/QPI/OPI switch or reset command 172 | flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt 173 | //! sequence number, [31:16] Reserved 174 | uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration 175 | uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable 176 | uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe 177 | flexspi_lut_seq_t 178 | configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq 179 | uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use 180 | uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands 181 | uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use 182 | uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more 183 | //! details 184 | uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details 185 | uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal 186 | uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot 187 | //! Chapter for more details 188 | uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot 189 | //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH 190 | uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use 191 | uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 192 | uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 193 | uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 194 | uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 195 | uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value 196 | uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value 197 | uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value 198 | uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value 199 | uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command 200 | uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands 201 | flexspi_dll_time_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B 202 | uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 203 | uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - 204 | //! busy flag is 0 when flash device is busy 205 | uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences 206 | flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences 207 | uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use 208 | } flexspi_mem_config_t; 209 | 210 | typedef enum _FlexSPIOperationType 211 | { 212 | kFlexSpiOperation_Command, //!< FlexSPI operation: Only command, both TX and 213 | //! RX buffer are ignored. 214 | kFlexSpiOperation_Config, //!< FlexSPI operation: Configure device mode, the 215 | //! TX FIFO size is fixed in LUT. 216 | kFlexSpiOperation_Write, //!< FlexSPI operation: Write, only TX buffer is 217 | //! effective 218 | kFlexSpiOperation_Read, //!< FlexSPI operation: Read, only Rx Buffer is 219 | //! effective. 220 | kFlexSpiOperation_End = kFlexSpiOperation_Read, 221 | } flexspi_operation_t; 222 | 223 | //!@brief FlexSPI Transfer Context 224 | typedef struct _FlexSpiXfer 225 | { 226 | flexspi_operation_t operation; //!< FlexSPI operation 227 | uint32_t baseAddress; //!< FlexSPI operation base address 228 | uint32_t seqId; //!< Sequence Id 229 | uint32_t seqNum; //!< Sequence Number 230 | bool isParallelModeEnable; //!< Is a parallel transfer 231 | uint32_t *txBuffer; //!< Tx buffer 232 | uint32_t txSize; //!< Tx size in bytes 233 | uint32_t *rxBuffer; //!< Rx buffer 234 | uint32_t rxSize; //!< Rx size in bytes 235 | } flexspi_xfer_t; 236 | 237 | //!@brief FlexSPI Clock Type 238 | typedef enum 239 | { 240 | kFlexSpiClock_CoreClock, //!< ARM Core Clock 241 | kFlexSpiClock_AhbClock, //!< AHB clock 242 | kFlexSpiClock_SerialRootClock, //!< Serial Root Clock 243 | kFlexSpiClock_IpgClock, //!< IPG clock 244 | } flexspi_clock_type_t; 245 | 246 | //!@brief Generate bit mask 247 | #define FLEXSPI_BITMASK(bit_offset) (1u << (bit_offset)) 248 | 249 | enum 250 | { 251 | kStatusGroup_FLEXSPINOR = 201, 252 | }; 253 | 254 | /* FlexSPI NOR status */ 255 | enum _flexspi_nor_status 256 | { 257 | kStatus_FLEXSPINOR_ProgramFail = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 0), //!< Status for Page programming failure 258 | kStatus_FLEXSPINOR_EraseSectorFail = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 1), //!< Status for Sector Erase failure 259 | kStatus_FLEXSPINOR_EraseAllFail = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 2), //!< Status for Chip Erase failure 260 | kStatus_FLEXSPINOR_WaitTimeout = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 3), //!< Status for timeout 261 | kStatus_FlexSPINOR_NotSupported = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 4), // Status for PageSize overflow 262 | kStatus_FlexSPINOR_WriteAlignmentError = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 5), //!< Status for Alignement error 263 | kStatus_FlexSPINOR_CommandFailure = 264 | MAKE_STATUS(kStatusGroup_FLEXSPINOR, 6), //!< Status for Erase/Program Verify Error 265 | kStatus_FlexSPINOR_SFDP_NotFound = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 7), //!< Status for SFDP read failure 266 | kStatus_FLEXSPINOR_Unsupported_SFDP_Version = 267 | MAKE_STATUS(kStatusGroup_FLEXSPINOR, 8), //!< Status for Unrecognized SFDP version 268 | kStatus_FLEXSPINOR_Flash_NotFound = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 9), //!< Status for Flash detection failure 269 | kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed = 270 | MAKE_STATUS(kStatusGroup_FLEXSPINOR, 10), //!< Status for DDR Read dummy probe failure 271 | }; 272 | 273 | enum 274 | { 275 | kSerialNorCfgOption_Tag = 0x0c, 276 | kSerialNorCfgOption_DeviceType_ReadSFDP_SDR = 0, 277 | kSerialNorCfgOption_DeviceType_ReadSFDP_DDR = 1, 278 | kSerialNorCfgOption_DeviceType_HyperFLASH1V8 = 2, 279 | kSerialNorCfgOption_DeviceType_HyperFLASH3V0 = 3, 280 | kSerialNorCfgOption_DeviceType_MacronixOctalDDR = 4, 281 | kSerialNorCfgOption_DeviceType_MacronixOctalSDR = 5, 282 | kSerialNorCfgOption_DeviceType_MicronOctalDDR = 6, 283 | kSerialNorCfgOption_DeviceType_MicronOctalSDR = 7, 284 | kSerialNorCfgOption_DeviceType_AdestoOctalDDR = 8, 285 | kSerialNorCfgOption_DeviceType_AdestoOctalSDR = 9, 286 | }; 287 | 288 | enum 289 | { 290 | kSerialNorQuadMode_NotConfig = 0, 291 | kSerialNorQuadMode_StatusReg1_Bit6 = 1, 292 | kSerialNorQuadMode_StatusReg2_Bit1 = 2, 293 | kSerialNorQuadMode_StatusReg2_Bit7 = 3, 294 | kSerialNorQuadMode_StatusReg2_Bit1_0x31 = 4, 295 | }; 296 | 297 | enum 298 | { 299 | kSerialNorEnhanceMode_Disabled = 0, 300 | kSerialNorEnhanceMode_0_4_4_Mode = 1, 301 | kSerialNorEnhanceMode_0_8_8_Mode = 2, 302 | kSerialNorEnhanceMode_DataOrderSwapped = 3, 303 | kSerialNorEnhanceMode_2ndPinMux = 4, 304 | }; 305 | 306 | /* 307 | * Serial NOR Configuration Option 308 | */ 309 | typedef struct _serial_nor_config_option 310 | { 311 | union 312 | { 313 | struct 314 | { 315 | uint32_t max_freq : 4; //!< Maximum supported Frequency 316 | uint32_t misc_mode : 4; //!< miscellaneous mode 317 | uint32_t quad_mode_setting : 4; //!< Quad mode setting 318 | uint32_t cmd_pads : 4; //!< Command pads 319 | uint32_t query_pads : 4; //!< SFDP read pads 320 | uint32_t device_type : 4; //!< Device type 321 | uint32_t option_size : 4; //!< Option size, in terms of uint32_t, size = (option_size + 1) * 4 322 | uint32_t tag : 4; //!< Tag, must be 0x0E 323 | } B; 324 | uint32_t U; 325 | } option0; 326 | 327 | union 328 | { 329 | struct 330 | { 331 | uint32_t dummy_cycles : 8; //!< Dummy cycles before read 332 | uint32_t status_override : 8; //!< Override status register value during device mode configuration 333 | uint32_t is_pinmux_group2 : 4; //!< The second group of pinmux 334 | uint32_t reserved : 12; //!< Reserved for future use 335 | } B; 336 | uint32_t U; 337 | } option1; 338 | 339 | } serial_nor_config_option_t; 340 | 341 | /* 342 | * Serial NOR configuration block 343 | */ 344 | typedef struct _flexspi_nor_config 345 | { 346 | flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI 347 | uint32_t pageSize; //!< Page size of Serial NOR 348 | uint32_t sectorSize; //!< Sector size of Serial NOR 349 | uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command 350 | uint8_t isUniformBlockSize; //!< Sector/Block size is the same 351 | uint8_t isDataOrderSwapped; //!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) 352 | uint8_t reserved0[1]; //!< Reserved for future use 353 | uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 354 | uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command 355 | uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false 356 | uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution 357 | uint32_t blockSize; //!< Block size 358 | uint32_t flashStateCtx; //!< Flash State Context 359 | uint32_t reserve2[10]; //!< Reserved for future use 360 | } flexspi_nor_config_t; 361 | 362 | #ifdef __cplusplus 363 | extern "C" { 364 | #endif 365 | 366 | //!@brief Configure FlexSPI Lookup table 367 | status_t flexspi_update_lut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq); 368 | 369 | //!@brief Perform FlexSPI command 370 | status_t flexspi_command_xfer(uint32_t instance, flexspi_xfer_t *xfer); 371 | 372 | //!@brief Clear FlexSPI cache 373 | void flexspi_clear_cache(uint32_t instance); 374 | 375 | //!@brief Update Clock source for FlexSPI 376 | status_t flexspi_update_clock_source(uint32_t instance, uint32_t source); 377 | 378 | //!@brief Initialize Serial NOR devices via FlexSPI 379 | status_t flexspi_nor_flash_init(uint32_t instance, flexspi_nor_config_t *config); 380 | 381 | //!@brief Program data to Serial NOR via FlexSPI 382 | status_t flexspi_nor_flash_page_program(uint32_t instance, 383 | flexspi_nor_config_t *config, 384 | uint32_t dstAddr, 385 | const uint32_t *src); 386 | 387 | //!@brief Erase all the Serial NOR devices connected on FlexSPI 388 | status_t flexspi_nor_flash_erase_all(uint32_t instance, flexspi_nor_config_t *config); 389 | 390 | //!@brief Get FlexSPI NOR Configuration Block based on specified option 391 | status_t flexspi_nor_get_config(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option); 392 | 393 | //!@brief Erase Flash Region specified by address and length 394 | status_t flexspi_nor_flash_erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); 395 | 396 | //!@brief Read data from Serial NOR 397 | status_t flexspi_nor_flash_read( 398 | uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes); 399 | 400 | #ifdef __cplusplus 401 | } 402 | #endif 403 | 404 | #endif // __FLEXSPI_NOR_FLASH_H__ 405 | -------------------------------------------------------------------------------- /bsp/imxrt1170_a0/flash_drv/bootloader_common.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. 3 | * Copyright 2016-2019 NXP 4 | * All rights reserved. 5 | * 6 | * 7 | * SPDX-License-Identifier: BSD-3-Clause 8 | */ 9 | #ifndef __BOOTLOADER_COMMON_H__ 10 | #define __BOOTLOADER_COMMON_H__ 11 | 12 | #include 13 | #include 14 | #include 15 | #include 16 | #include "target_config.h" 17 | 18 | //////////////////////////////////////////////////////////////////////////////// 19 | // Definitions 20 | //////////////////////////////////////////////////////////////////////////////// 21 | 22 | #ifndef NULL 23 | #define NULL 0 24 | #endif 25 | 26 | #ifndef ALIGN_DOWN 27 | #define ALIGN_DOWN(x, a) ((x) & -(a)) 28 | #endif 29 | #ifndef ALIGN_UP 30 | #define ALIGN_UP(x, a) (-(-(x) & -(a))) 31 | #endif 32 | 33 | //! @brief Bootloader status group numbers. 34 | //! 35 | //! @ingroup bl_core 36 | enum _bl_status_groups 37 | { 38 | kStatusGroup_FLEXSPINOR = 201, //!< FlexSPINOR status group number. 39 | }; 40 | 41 | //////////////////////////////////////////////////////////////////////////////// 42 | // Prototypes 43 | //////////////////////////////////////////////////////////////////////////////// 44 | 45 | 46 | #endif // __BOOTLOADER_COMMON_H__ 47 | //////////////////////////////////////////////////////////////////////////////// 48 | // EOF 49 | //////////////////////////////////////////////////////////////////////////////// 50 | -------------------------------------------------------------------------------- /bsp/imxrt1170_a0/flash_drv/flexspi_nor_flash.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2014-2016 Freescale Semiconductor, Inc. 3 | * Copyright 2016-2020 NXP 4 | * All rights reserved. 5 | * 6 | * SPDX-License-Identifier: BSD-3-Clause 7 | * 8 | */ 9 | 10 | #ifndef __FLEXSPI_NOR_FLASH_H__ 11 | #define __FLEXSPI_NOR_FLASH_H__ 12 | 13 | #include "bootloader_common.h" 14 | #include "fsl_common.h" 15 | #include "fsl_flexspi.h" 16 | 17 | /****************************************************************************** 18 | ** Change History: 19 | ** 20 | ** 1.7.0 Support JESD216D, forced internal loopback mode, forced SPI mode 21 | Removed the AHB buffer configuration from API 22 | ** 1.6.0 Support JESD216B, Support PORTB, Support parallel mode 23 | ** 1.0.0 First implementation, support basic FLEXSPI NOR operation 24 | ** 25 | *******************************************************************************/ 26 | 27 | //!@brief FLEXSPI NOR Driver Version 28 | #define FLEXSPI_NOR_DRIVER_VERSION MAKE_VERSION(1, 7, 0) 29 | 30 | /* FlexSPI NOR status */ 31 | enum _flexspi_nor_status 32 | { 33 | kStatus_FLEXSPINOR_ProgramFail = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 0), //!< Status for Page programming failure 34 | kStatus_FLEXSPINOR_EraseSectorFail = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 1), //!< Status for Sector Erase failure 35 | kStatus_FLEXSPINOR_EraseAllFail = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 2), //!< Status for Chip Erase failure 36 | kStatus_FLEXSPINOR_WaitTimeout = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 3), //!< Status for timeout 37 | kStatus_FlexSPINOR_NotSupported = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 4), // Status for PageSize overflow 38 | kStatus_FlexSPINOR_WriteAlignmentError = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 5), //!< Status for Alignement error 39 | kStatus_FlexSPINOR_CommandFailure = 40 | MAKE_STATUS(kStatusGroup_FLEXSPINOR, 6), //!< Status for Erase/Program Verify Error 41 | kStatus_FlexSPINOR_SFDP_NotFound = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 7), //!< Status for SFDP read failure 42 | kStatus_FLEXSPINOR_Unsupported_SFDP_Version = 43 | MAKE_STATUS(kStatusGroup_FLEXSPINOR, 8), //!< Status for Unrecognized SFDP version 44 | kStatus_FLEXSPINOR_Flash_NotFound = MAKE_STATUS(kStatusGroup_FLEXSPINOR, 9), //!< Status for Flash detection failure 45 | kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed = 46 | MAKE_STATUS(kStatusGroup_FLEXSPINOR, 10), //!< Status for DDR Read dummy probe failure 47 | }; 48 | 49 | enum 50 | { 51 | kSerialNorCfgOption_Tag = 0x0c, 52 | kSerialNorCfgOption_DeviceType_ReadSFDP_SDR = 0, 53 | kSerialNorCfgOption_DeviceType_ReadSFDP_DDR = 1, 54 | kSerialNorCfgOption_DeviceType_HyperFLASH1V8 = 2, 55 | kSerialNorCfgOption_DeviceType_HyperFLASH3V0 = 3, 56 | kSerialNorCfgOption_DeviceType_MacronixOctalDDR = 4, 57 | kSerialNorCfgOption_DeviceType_MacronixOctalSDR = 5, 58 | kSerialNorCfgOption_DeviceType_MicronOctalDDR = 6, 59 | kSerialNorCfgOption_DeviceType_MicronOctalSDR = 7, 60 | kSerialNorCfgOption_DeviceType_AdestoOctalDDR = 8, 61 | kSerialNorCfgOption_DeviceType_AdestoOctalSDR = 9, 62 | }; 63 | 64 | enum 65 | { 66 | kSerialNorQuadMode_NotConfig = 0, 67 | kSerialNorQuadMode_StatusReg1_Bit6 = 1, 68 | kSerialNorQuadMode_StatusReg2_Bit1 = 2, 69 | kSerialNorQuadMode_StatusReg2_Bit7 = 3, 70 | kSerialNorQuadMode_StatusReg2_Bit1_0x31 = 4, 71 | }; 72 | 73 | enum 74 | { 75 | kSerialNorOctaldMode_NoOctalEnableBit = 0, 76 | kSerialNorOctaldMode_HasOctalEnableBit = 1, 77 | }; 78 | 79 | enum 80 | { 81 | kSerialNorEnhanceMode_Disabled = 0, 82 | kSerialNorEnhanceMode_0_4_4_Mode = 1, 83 | kSerialNorEnhanceMode_0_8_8_Mode = 2, 84 | kSerialNorEnhanceMode_DataOrderSwapped = 3, 85 | kSerialNorEnhanceMode_2ndPinMux = 4, 86 | kSerialNorEnhanceMode_InternalLoopback = 5, 87 | kSerialNorEnhanceMode_SpiMode = 6, 88 | kSerialNorEnhanceMode_ExtDqs = 8, 89 | }; 90 | 91 | enum 92 | { 93 | kFlashResetLogic_Disabled = 0, 94 | kFlashResetLogic_ResetPin = 1, 95 | kFlashResetLogic_JedecHwReset = 2, 96 | }; 97 | 98 | enum 99 | { 100 | kSerialNorConnection_SinglePortA, 101 | kSerialNorConnection_Parallel, 102 | kSerialNorConnection_SinglePortB, 103 | kSerialNorConnection_BothPorts 104 | }; 105 | 106 | /* 107 | * Serial NOR Configuration Option 108 | */ 109 | typedef struct _serial_nor_config_option 110 | { 111 | union { 112 | struct 113 | { 114 | uint32_t max_freq : 4; //!< Maximum supported Frequency 115 | uint32_t misc_mode : 4; //!< miscellaneous mode 116 | uint32_t quad_mode_setting : 4; //!< Quad mode setting 117 | uint32_t cmd_pads : 4; //!< Command pads 118 | uint32_t query_pads : 4; //!< SFDP read pads 119 | uint32_t device_type : 4; //!< Device type 120 | uint32_t option_size : 4; //!< Option size, in terms of uint32_t, size = (option_size + 1) * 4 121 | uint32_t tag : 4; //!< Tag, must be 0x0E 122 | } B; 123 | uint32_t U; 124 | } option0; 125 | 126 | union { 127 | struct 128 | { 129 | uint32_t dummy_cycles : 8; //!< Dummy cycles before read 130 | uint32_t status_override : 8; //!< Override status register value during device mode configuration 131 | uint32_t pinmux_group : 4; //!< The pinmux group selection 132 | uint32_t dqs_pinmux_group : 4; //!< The DQS Pinmux Group Selection 133 | uint32_t drive_strength : 4; //!< The Drive Strength of FlexSPI Pads 134 | uint32_t flash_connection : 4; //!< Flash connection option: 0 - Single Flash connected to port A, 1 - 135 | //! Parallel mode, 2 - Single Flash connected to Port B 136 | } B; 137 | uint32_t U; 138 | } option1; 139 | 140 | } serial_nor_config_option_t; 141 | 142 | typedef union { 143 | struct 144 | { 145 | uint8_t por_mode; 146 | uint8_t current_mode; 147 | uint8_t exit_no_cmd_sequence; 148 | uint8_t restore_sequence; 149 | } B; 150 | uint32_t U; 151 | } flash_run_context_t; 152 | 153 | enum 154 | { 155 | kRestoreSequence_None = 0, 156 | kRestoreSequence_HW_Reset = 1, 157 | kRestoreSequence_4QPI_FF = 2, 158 | kRestoreSequence_5QPI_FF = 3, 159 | kRestoreSequence_8QPI_FF = 4, 160 | kRestoreSequence_Send_F0 = 5, 161 | kRestoreSequence_Send_66_99 = 6, 162 | kRestoreSequence_Send_6699_9966 = 7, 163 | kRestoreSequence_Send_06_FF, // Adesto EcoXIP 164 | }; 165 | 166 | enum 167 | { 168 | kFlashInstMode_ExtendedSpi = 0x00, 169 | kFlashInstMode_0_4_4_SDR = 0x01, 170 | kFlashInstMode_0_4_4_DDR = 0x02, 171 | kFlashInstMode_QPI_SDR = 0x41, 172 | kFlashInstMode_QPI_DDR = 0x42, 173 | kFlashInstMode_OPI_SDR = 0x81, 174 | kFlashInstMode_OPI_DDR = 0x82, 175 | }; 176 | 177 | /* 178 | * Serial NOR configuration block 179 | */ 180 | typedef struct _flexspi_nor_config 181 | { 182 | flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI 183 | uint32_t pageSize; //!< Page size of Serial NOR 184 | uint32_t sectorSize; //!< Sector size of Serial NOR 185 | uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command 186 | uint8_t isUniformBlockSize; //!< Sector/Block size is the same 187 | uint8_t isDataOrderSwapped; //!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) 188 | uint8_t reserved0[1]; //!< Reserved for future use 189 | uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 190 | uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command 191 | uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false 192 | uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution 193 | uint32_t blockSize; //!< Block size 194 | uint32_t flashStateCtx; //!< Flash State Context 195 | uint32_t reserve2[10]; //!< Reserved for future use 196 | } flexspi_nor_config_t; 197 | 198 | #ifdef __cplusplus 199 | extern "C" 200 | { 201 | #endif 202 | 203 | //!@brief Initialize Serial NOR devices via FlexSPI 204 | status_t flexspi_nor_flash_init(uint32_t instance, flexspi_nor_config_t *config); 205 | 206 | //!@brief Program data to Serial NOR via FlexSPI 207 | status_t flexspi_nor_flash_page_program(uint32_t instance, 208 | flexspi_nor_config_t *config, 209 | uint32_t dstAddr, 210 | const uint32_t *src); 211 | 212 | //!@brief Program data to Serial NOR via FlexSPI specified by address and length 213 | status_t flexspi_nor_flash_program(uint32_t instance, 214 | flexspi_nor_config_t *config, 215 | uint32_t dstAddr, 216 | const uint32_t *src, 217 | uint32_t length); 218 | 219 | //!@brief Erase all the Serial NOR devices connected on FlexSPI 220 | status_t flexspi_nor_flash_erase_all(uint32_t instance, flexspi_nor_config_t *config); 221 | 222 | //!@brief Erase one sector specified by address 223 | status_t flexspi_nor_flash_erase_sector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); 224 | 225 | //!@brief Erase one block specified by address 226 | status_t flexspi_nor_flash_erase_block(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); 227 | 228 | //!@brief Get FlexSPI NOR Configuration Block based on specified option 229 | status_t flexspi_nor_get_config(uint32_t instance, 230 | flexspi_nor_config_t *config, 231 | serial_nor_config_option_t *option); 232 | 233 | //!@brief Erase Flash Region specified by address and length 234 | status_t flexspi_nor_flash_erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); 235 | 236 | //!@brief Read data from Serial NOR 237 | status_t flexspi_nor_flash_read( 238 | uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes); 239 | 240 | //!@brief Write FlexSPI persistent content 241 | extern status_t flexspi_nor_write_persistent(const uint32_t data); 242 | 243 | //!@brief Read FlexSPI persistent content 244 | extern status_t flexspi_nor_read_persistent(uint32_t *data); 245 | 246 | //!@brief Restore Flash to SPI protocol 247 | status_t flexspi_nor_restore_spi_protocol(uint32_t instance, 248 | flexspi_nor_config_t *config, 249 | flash_run_context_t *run_ctx); 250 | 251 | //!@brief FlexSPI NOR HW Reset 252 | extern void flexspi_nor_hw_reset(uint32_t instance, uint32_t reset_logic); 253 | 254 | #ifdef __cplusplus 255 | } 256 | #endif 257 | 258 | #endif // __FLEXSPI_NOR_FLASH_H__ 259 | -------------------------------------------------------------------------------- /bsp/imxrt1170_a0/flash_drv/fsl_flexspi.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2014-2016 Freescale Semiconductor, Inc. 3 | * Copyright 2016-2019 NXP 4 | * All rights reserved. 5 | * 6 | * SPDX-License-Identifier: BSD-3-Clause 7 | * 8 | */ 9 | 10 | #ifndef __FSL_FLEXSPI_H__ 11 | #define __FSL_FLEXSPI_H__ 12 | 13 | #include "fsl_common.h" 14 | 15 | /********************************************************************************************************************** 16 | * Definitions 17 | *********************************************************************************************************************/ 18 | /* The count of FlexSPI_LUT */ 19 | #define FlexSPI_LUT_COUNT (64) 20 | /* The count of FlexSPI AHB Buffer */ 21 | #define FlexSPI_AHB_RX_BUF_COUNT (4U) 22 | /* AHB RX_BUF depth, in longwords */ 23 | #define FlexSPI_AHB_RX_BUF_DEPTH (512U) 24 | /* AHB TX BUF depth, in longwords */ 25 | #define FlexSPI_AHB_TX_BUF_DEPTH (32U) 26 | /* IP_RX_BUF depth, in longwords */ 27 | #define FlexSPI_IP_RX_BUF_DEPTH (256U) 28 | /* IP TX BUF depth, in longwords */ 29 | #define FlexSPI_IP_TX_BUF_DEPTH (256U) 30 | 31 | /* FLEXSPI memory config block related defintions */ 32 | #define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian 33 | #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 34 | #define FLEXSPI_CFG_BLK_SIZE (512) 35 | 36 | /* FLEXSPI Feature related definitions */ 37 | #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 38 | 39 | /* Lookup table related defintions */ 40 | #define CMD_INDEX_READ 0 41 | #define CMD_INDEX_READSTATUS 1 42 | #define CMD_INDEX_WRITEENABLE 2 43 | #define CMD_INDEX_WRITE 4 44 | 45 | #define CMD_LUT_SEQ_IDX_READ 0 46 | #define CMD_LUT_SEQ_IDX_READSTATUS 1 47 | #define CMD_LUT_SEQ_IDX_WRITEENABLE 3 48 | #define CMD_LUT_SEQ_IDX_WRITE 9 49 | 50 | #define CMD_SDR 0x01 51 | #define CMD_DDR 0x21 52 | #define RADDR_SDR 0x02 53 | #define RADDR_DDR 0x22 54 | #define CADDR_SDR 0x03 55 | #define CADDR_DDR 0x23 56 | #define MODE1_SDR 0x04 57 | #define MODE1_DDR 0x24 58 | #define MODE2_SDR 0x05 59 | #define MODE2_DDR 0x25 60 | #define MODE4_SDR 0x06 61 | #define MODE4_DDR 0x26 62 | #define MODE8_SDR 0x07 63 | #define MODE8_DDR 0x27 64 | #define WRITE_SDR 0x08 65 | #define WRITE_DDR 0x28 66 | #define READ_SDR 0x09 67 | #define READ_DDR 0x29 68 | #define LEARN_SDR 0x0A 69 | #define LEARN_DDR 0x2A 70 | #define DATSZ_SDR 0x0B 71 | #define DATSZ_DDR 0x2B 72 | #define DUMMY_SDR 0x0C 73 | #define DUMMY_DDR 0x2C 74 | #define DUMMY_RWDS_SDR 0x0D 75 | #define DUMMY_RWDS_DDR 0x2D 76 | #define JMP_ON_CS 0x1F 77 | #define CMD_STOP 0 78 | 79 | #define FLEXSPI_1PAD 0 80 | #define FLEXSPI_2PAD 1 81 | #define FLEXSPI_4PAD 2 82 | #define FLEXSPI_8PAD 3 83 | 84 | #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 85 | (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ 86 | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 87 | 88 | //!@brief Defintions for FlexSPI Serial Clock Frequency 89 | enum 90 | { 91 | kFlexSpiSerialClk_SafeFreq = 1, 92 | }; 93 | 94 | //!@brief FlexSPI clock configuration type 95 | enum 96 | { 97 | kFlexSpiClk_SDR, //!< Clock configure for SDR mode 98 | kFlexSpiClk_DDR, //!< Clock configurat for DDR mode 99 | }; 100 | 101 | //!@brief FlexSPI Read Sample Clock Source definition 102 | typedef enum _FlashReadSampleClkSource 103 | { 104 | kFlexSPIReadSampleClk_LoopbackInternally = 0, 105 | kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, 106 | kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, 107 | kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, 108 | } flexspi_read_sample_clk_t; 109 | 110 | //!@brief FlexSPI IP Error codes 111 | typedef enum _FlexSpiIpCmdError 112 | { 113 | kFlexSpiIpCmdError_NoError = 0, 114 | kFlexSpiIpCmdError_DataSizeNotEvenUnderParallelMode = 1, 115 | kFlexSpiIpCmdError_JumpOnCsInIpCmd = 2, 116 | kFlexSpiIpCmdError_UnknownOpCode = 3, 117 | kFlexSpiIpCmdError_SdrDummyInDdrSequence = 4, 118 | kFlexSpiIpCmdError_DDRDummyInSdrSequence = 5, 119 | kFlexSpiIpCmdError_InvalidAddress = 6, 120 | kFlexSpiIpCmdError_SequenceExecutionTimeout = 0x0E, 121 | kFlexSpiIpCmdError_FlashBoundaryAcrosss = 0x0F 122 | } flexspi_ipcmd_error_t; 123 | 124 | /* status code for flexspi */ 125 | enum _flexspi_status 126 | { 127 | kStatus_FLEXSPI_SequenceExecutionTimeout = 128 | MAKE_STATUS(kStatusGroup_FLEXSPI, 0), //!< Status for Sequence Execution timeout 129 | kStatus_FLEXSPI_InvalidSequence = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), //!< Status for Invalid Sequence 130 | kStatus_FLEXSPI_DeviceTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 2), //!< Status for Device timeout 131 | }; 132 | 133 | //!@brief Misc feature bit definitions 134 | enum 135 | { 136 | kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable 137 | kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable 138 | kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable 139 | kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable 140 | kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable 141 | kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable 142 | kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. 143 | kFlexSpiMiscOffset_UseValidTimeForAllFreq = 7, //!< Bit for DLLCR settings under all modes 144 | kFlexSpiMiscOffset_SecondPinMux = 8, //!< Bit for Second Pinmux group 145 | kFlexSpiMiscOffset_SecondDqsPinMux = 9, //!< Bit for Second DQS Pin mux 146 | kFlexSpiMiscOffset_WriteMaskEnable = 10, //!< Bit for Write Mask Enable 147 | kFlexSpiMiscOffset_WriteOpt1Clear = 11, //!< Bit for Write Opt 148 | }; 149 | 150 | //!@brief Flash Type Definition 151 | enum 152 | { 153 | kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR 154 | kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND 155 | kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH 156 | kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND 157 | kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs 158 | }; 159 | 160 | //!@brief Flash Pad Definitions 161 | enum 162 | { 163 | kSerialFlash_1Pad = 1, 164 | kSerialFlash_2Pads = 2, 165 | kSerialFlash_4Pads = 4, 166 | kSerialFlash_8Pads = 8, 167 | }; 168 | 169 | //!@brief FlexSPI LUT Sequence structure 170 | typedef struct _lut_sequence 171 | { 172 | uint8_t seqNum; //!< Sequence Number, valid number: 1-16 173 | uint8_t seqId; //!< Sequence Index, valid number: 0-15 174 | uint16_t reserved; 175 | } flexspi_lut_seq_t; 176 | 177 | //!@brief Flash Configuration Command Type 178 | enum 179 | { 180 | kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc 181 | kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command 182 | kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode 183 | kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode 184 | kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode 185 | kDeviceConfigCmdType_Reset, //!< Reset device command 186 | }; 187 | 188 | typedef struct 189 | { 190 | uint8_t time_100ps; // Data valid time, in terms of 100ps 191 | uint8_t delay_cells; // Data valid time, in terms of delay cells 192 | } flexspi_dll_time_t; 193 | 194 | //!@brief FlexSPI Memory Configuration Block 195 | typedef struct _FlexSPIConfig 196 | { 197 | uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL 198 | uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix 199 | uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use 200 | uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 201 | uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 202 | uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 203 | uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For 204 | //! Serial NAND, need to refer to datasheet 205 | uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable 206 | uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, 207 | //! Generic configuration, etc. 208 | uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for 209 | //! DPI/QPI/OPI switch or reset command 210 | flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt 211 | //! sequence number, [31:16] Reserved 212 | uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration 213 | uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable 214 | uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe 215 | flexspi_lut_seq_t 216 | configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq 217 | uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use 218 | uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands 219 | uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use 220 | uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more 221 | //! details 222 | uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details 223 | uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal 224 | uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot 225 | //! Chapter for more details 226 | uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot 227 | //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH 228 | uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use 229 | uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 230 | uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 231 | uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 232 | uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 233 | uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value 234 | uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value 235 | uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value 236 | uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value 237 | uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command 238 | uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands 239 | flexspi_dll_time_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B 240 | uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 241 | uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - 242 | //! busy flag is 0 when flash device is busy 243 | uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences 244 | flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences 245 | uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use 246 | } flexspi_mem_config_t; 247 | 248 | typedef enum _FlexSPIOperationType 249 | { 250 | kFlexSpiOperation_Command, //!< FlexSPI operation: Only command, both TX and 251 | //! RX buffer are ignored. 252 | kFlexSpiOperation_Config, //!< FlexSPI operation: Configure device mode, the 253 | //! TX FIFO size is fixed in LUT. 254 | kFlexSpiOperation_Write, //!< FlexSPI operation: Write, only TX buffer is 255 | //! effective 256 | kFlexSpiOperation_Read, //!< FlexSPI operation: Read, only Rx Buffer is 257 | //! effective. 258 | kFlexSpiOperation_End = kFlexSpiOperation_Read, 259 | } flexspi_operation_t; 260 | 261 | //!@brief FlexSPI Transfer Context 262 | typedef struct _FlexSpiXfer 263 | { 264 | flexspi_operation_t operation; //!< FlexSPI operation 265 | uint32_t baseAddress; //!< FlexSPI operation base address 266 | uint32_t seqId; //!< Sequence Id 267 | uint32_t seqNum; //!< Sequence Number 268 | bool isParallelModeEnable; //!< Is a parallel transfer 269 | uint32_t *txBuffer; //!< Tx buffer 270 | uint32_t txSize; //!< Tx size in bytes 271 | uint32_t *rxBuffer; //!< Rx buffer 272 | uint32_t rxSize; //!< Rx size in bytes 273 | } flexspi_xfer_t; 274 | 275 | //!@brief FlexSPI Clock Type 276 | typedef enum 277 | { 278 | kFlexSpiClock_CoreClock, //!< ARM Core Clock 279 | kFlexSpiClock_AhbClock, //!< AHB clock 280 | kFlexSpiClock_SerialRootClock, //!< Serial Root Clock 281 | kFlexSpiClock_IpgClock, //!< IPG clock 282 | } flexspi_clock_type_t; 283 | 284 | //!@brief Generate bit mask 285 | #define FLEXSPI_BITMASK(bit_offset) (1u << (bit_offset)) 286 | 287 | /********************************************************************************************************************** 288 | * API 289 | *********************************************************************************************************************/ 290 | 291 | #ifdef __cplusplus 292 | extern "C" 293 | { 294 | #endif 295 | 296 | //!@brief Initialize FlexSPI 297 | status_t flexspi_init(uint32_t instance, flexspi_mem_config_t *config); 298 | 299 | //!@brief Send Write enable command to Serial Memory device 300 | status_t flexspi_device_write_enable(uint32_t instance, 301 | flexspi_mem_config_t *config, 302 | bool isParallelMode, 303 | uint32_t baseAddr); 304 | 305 | //!@brief Wait until device is idle 306 | status_t flexspi_device_wait_busy(uint32_t instance, 307 | flexspi_mem_config_t *config, 308 | bool isParallelMode, 309 | uint32_t baseAddr); 310 | 311 | //!@brief Configure FlexSPI Lookup table 312 | status_t flexspi_update_lut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq); 313 | 314 | //!@brief Perform FlexSPI command 315 | status_t flexspi_command_xfer(uint32_t instance, flexspi_xfer_t *xfer); 316 | 317 | //!@brief Get FlexSPI Clock frequency 318 | extern status_t flexspi_get_clock(uint32_t instance, flexspi_clock_type_t type, uint32_t *freq); 319 | 320 | //!@brief Wait until FlexSPI controller becomes idle 321 | void flexspi_wait_idle(uint32_t instance); 322 | 323 | //!@brief Update Read Sampling Clock source 324 | void flexspi_update_read_clock_source(uint32_t instance, uint32_t src); 325 | 326 | //!@brief Update DLLCR 327 | void flexspi_set_dllcr(uint32_t instance, uint32_t value); 328 | 329 | //!@brief Clear FlexSPI cache 330 | void flexspi_clear_cache(uint32_t instance); 331 | 332 | //!@brief Clear FlexSPI sequence pointer 333 | void flexspi_clear_sequence_pointer(uint32_t instance); 334 | 335 | //!@brief Enable clock gate of FlexSPI 336 | extern void flexspi_clock_gate_enable(uint32_t instance); 337 | 338 | //!@brief Disable clock gate of FlexSPI 339 | extern void flexspi_clock_gate_disable(uint32_t instance); 340 | 341 | //!@brief Configure IOMUX for FlexSPI 342 | extern void flexspi_iomux_config(uint32_t instance, flexspi_mem_config_t *config); 343 | 344 | //!@brief Configure Clock for FlexSPI 345 | extern void flexspi_clock_config(uint32_t instance, uint32_t freq, uint32_t sampleClkMode); 346 | 347 | //!@brief Update Clock source for FlexSPI 348 | extern status_t flexspi_update_clock_source(uint32_t instance, uint32_t source); 349 | 350 | //!@brief Check whether Pad Setting Override feature is enabled. 351 | bool flexspi_is_padsetting_override_enable(flexspi_mem_config_t *config); 352 | 353 | //!@brief Check whether Differential clock feature is enabled. 354 | bool flexspi_is_differential_clock_enable(flexspi_mem_config_t *config); 355 | 356 | //!@brief Check whether DDR mode feature is enabled. 357 | bool flexspi_is_ddr_mode_enable(flexspi_mem_config_t *config); 358 | 359 | //!@brief Check whether CK2 feature is enabled. 360 | bool flexspi_is_ck2_enabled(flexspi_mem_config_t *config); 361 | 362 | //!@brief Check whether Parallel mode feature is enabled. 363 | bool flexspi_is_parallel_mode(flexspi_mem_config_t *config); 364 | 365 | //!@brief Check whether device works under word addressable mode 366 | bool flexspi_is_word_addressable(flexspi_mem_config_t *config); 367 | 368 | //!@brief Configure FlexSPI DLL register 369 | status_t flexspi_configure_dll(uint32_t instance, flexspi_mem_config_t *config); 370 | 371 | //!@brief Half FlexSPI Clock 372 | void flexspi_half_clock_control(uint32_t instance, uint32_t option); 373 | 374 | //!@brief Set Failfase setting info 375 | extern status_t flexspi_set_failsafe_setting(flexspi_mem_config_t *config); 376 | 377 | //!@brief Get Maximumn clock frequency 378 | extern status_t flexspi_get_max_supported_freq(uint32_t instance, uint32_t *freq, uint32_t clkMode); 379 | 380 | extern void flexspi_sw_delay_us(uint64_t us); 381 | 382 | extern void flexspi_update_padsetting(uint32_t instance, flexspi_mem_config_t *config, uint32_t driveStrength); 383 | 384 | extern bool is_flexspi_clock_enabled(uint32_t instance); 385 | 386 | #ifdef __cplusplus 387 | } 388 | #endif 389 | 390 | #endif 391 | -------------------------------------------------------------------------------- /bsp/imxrt1170_a0/flash_drv/fusemap.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018-2020 NXP 3 | * All rights reserved. 4 | * 5 | * SPDX-License-Identifier: BSD-3-Clause 6 | * 7 | */ 8 | 9 | #ifndef __FUSEMAP_H__ 10 | #define __FUSEMAP_H__ 11 | 12 | #include "fsl_device_registers.h" 13 | 14 | //////////////////////////////////////////////////////////////////////////////// 15 | // Definitions 16 | //////////////////////////////////////////////////////////////////////////////// 17 | 18 | #define FUSE_BANK0_OFFSET 0x800 19 | #define HW_FUSE_REG_ADDR(n) (OCOTP_BASE + FUSE_BANK0_OFFSET + ((n)*0x10)) 20 | #define HW_OCOTP_REG_RD(n) (*(volatile uint32_t *)HW_FUSE_REG_ADDR(n)) 21 | 22 | /* ======================== Boot Mode ================================= */ 23 | #define FUSE_BOOTMODE_SHIFT ((uint8_t)24) 24 | #define FUSE_BOOTMODE_MASK ((uint32_t)(3 << FUSE_BOOTMODE_SHIFT)) 25 | #define FUSE_BOOTMODE_VALUE ((SRC->SBMR2 & FUSE_BOOTMODE_MASK) >> FUSE_BOOTMODE_SHIFT) 26 | 27 | #define ROM_BOOTMODE_INTERNAL_FUSE (0) 28 | #define ROM_BOOTMODE_SERIAL (1) 29 | #define ROM_BOOTMODE_INTERNAL (2) 30 | #define ROM_BOOTMODE_TEST (3) 31 | 32 | /* ======================== Boot Configuration ================================= */ 33 | /* TEST MODE */ 34 | #define FUSE_TESTMODE_SHIFT ((uint8_t)27) 35 | #define FUSE_TESTMODE_MASK ((uint32_t)(7 << FUSE_TESTMODE_SHIFT)) 36 | #define FUSE_TESTMODE_VALUE ((SRC->SBMR2 & FUSE_TESTMODE_MASK) >> FUSE_TESTMODE_SHIFT) 37 | 38 | /* SEC_CONFIG */ 39 | #define FUSE_SECURE_CONFIG_SHIFT ((uint8_t)0) 40 | #define FUSE_SECURE_CONFIG_MASK ((uint32_t)(3 << FUSE_SECURE_CONFIG_SHIFT)) 41 | #define FUSE_SECURE_CONFIG_VALUE ((SRC->SBMR2 & FUSE_SECURE_CONFIG_MASK) >> FUSE_SECURE_CONFIG_SHIFT) 42 | 43 | /* DIR_BT_DIS */ 44 | #define FUSE_DIR_BT_DIS_SHIFT ((uint8_t)3) 45 | #define FUSE_DIR_BT_DIS_MASK ((uint32_t)(1 << FUSE_DIR_BT_DIS_SHIFT)) 46 | #define FUSE_DIR_BT_DIS_VALUE ((HW_OCOTP_REG_RD(0x16) & FUSE_DIR_BT_DIS_MASK) >> FUSE_DIR_BT_DIS_SHIFT) 47 | 48 | /* BT_FUSE_SEL */ 49 | #define FUSE_BT_FUSE_SEL_SHIFT ((uint8_t)4) 50 | #define FUSE_BT_FUSE_SEL_MASK ((uint32_t)(1 << FUSE_BT_FUSE_SEL_SHIFT)) 51 | #define FUSE_BT_FUSE_SEL_VALUE ((HW_OCOTP_REG_RD(0x16) & FUSE_BT_FUSE_SEL_MASK) >> FUSE_BT_FUSE_SEL_SHIFT) 52 | 53 | /* BT_CORE_SEL */ 54 | #define FUSE_BT_CORE_SEL_SHIFT ((uint8_t)12) 55 | #define FUSE_BT_CORE_SEL_MASK ((uint32_t)(1 << FUSE_BT_CORE_SEL_SHIFT)) 56 | #define FUSE_BT_CORE_SEL_VALUE ((HW_OCOTP_REG_RD(0x16) & FUSE_BT_FUSE_SEL_MASK) >> FUSE_BT_FUSE_SEL_SHIFT) 57 | 58 | /* M7_DISABLE */ 59 | #define FUSE_BT_M7_DISABLE_SHIFT (0) 60 | #define FUSE_BT_M7_DISABLE_MASK (1u << FUSE_BT_M7_DISABLE_SHIFT) 61 | #define FUSE_BT_M7_DISABLE_VALUE ((HW_OCOTP_REG_RD(0x4) & FUSE_BT_M7_DISABLE_MASK) >> FUSE_BT_M7_DISABLE_SHIFT) 62 | 63 | /* M4_DISABLE */ 64 | #define FUSE_BT_M4_DISABLE_SHIFT (1) 65 | #define FUSE_BT_M4_DISABLE_MASK (1u << FUSE_BT_M4_DISABLE_SHIFT) 66 | #define FUSE_BT_M4_DISABLE_VALUE ((HW_OCOTP_REG_RD(0x4) & FUSE_BT_M4_DISABLE_MASK) >> FUSE_BT_M4_DISABLE_SHIFT) 67 | 68 | /* BOOT DEVICE */ 69 | #define FUSE_BOOT_DEVICE_SHIFT ((uint8_t)4) 70 | #define FUSE_BOOT_DEVICE_MASK ((uint32_t)(0xf << FUSE_BOOT_DEVICE_SHIFT)) 71 | #define FUSE_BOOT_DEVICE_VALUE ((SRC->SBMR1 & FUSE_BOOT_DEVICE_MASK) >> FUSE_BOOT_DEVICE_SHIFT) 72 | 73 | /* SIP_PACKAGE_EN */ 74 | #define FUSE_SIP_PKG_EN_SHIFT ((uint8_t)31) 75 | #define FUSE_SIP_PKG_EN_MASK (1u << FUSE_SIP_PKG_EN_SHIFT) 76 | #define FUSE_SIP_PKG_EN_VALUE ((HW_OCOTP_REG_RD(0x12) & FUSE_SIP_PKG_EN_MASK) >> FUSE_SIP_PKG_EN_SHIFT) 77 | 78 | /* ROM_LOCK */ 79 | #define FUSE_ROM_LOCK_SHIFT ((uint8_t)9) 80 | #define FUSE_ROM_LOCK_MASK (1u << FUSE_ROM_LOCK_SHIFT) 81 | #define FUSE_ROM_LOCK_VALUE ((HW_OCOTP_REG_RD(0x0E) & FUSE_ROM_LOCK_MASK) >> FUSE_ROM_LOCK_SHIFT) 82 | 83 | /* OCRAM1_DISABLE */ 84 | #define FUSE_OCRAM1_DISABLE_SHIFT (7) 85 | #define FUSE_OCRAM1_DISABLE_MASK (1u << FUSE_OCRAM1_DISABLE_SHIFT) 86 | #define FUSE_OCRAM1_DISABLE_VALUE ((HW_OCOTP_REG_RD(0x05) & FUSE_OCRAM1_DISABLE_MASK) >> FUSE_OCRAM1_DISABLE_SHIFT) 87 | 88 | /* OCRAM2_DISABLE */ 89 | #define FUSE_OCRAM2_DISABLE_SHIFT (6) 90 | #define FUSE_OCRAM2_DISABLE_MASK (1u << FUSE_OCRAM2_DISABLE_SHIFT) 91 | #define FUSE_OCRAM2_DISABLE_VALUE ((HW_OCOTP_REG_RD(0x05) & FUSE_OCRAM2_DISABLE_MASK) >> FUSE_OCRAM2_DISABLE_SHIFT) 92 | 93 | /* SPEED_LIMIT */ 94 | #define FUSE_SPEED_LIMIT_SHIFT (2) 95 | #define FUSE_SPEED_LIMIT_MASK (1u << FUSE_SPEED_LIMIT_SHIFT) 96 | #define FUSE_SPEED_LIMIT_VALUE ((HW_OCOTP_REG_RD(0x07) & FUSE_SPEED_LIMIT_MASK) >> FUSE_SPEED_LIMIT_SHIFT) 97 | 98 | /* WIPE INVALID IMAGE */ 99 | #define FUSE_WIPE_INVALID_IMAGE_SHIFT (12) 100 | #define FUSE_WIPE_INVALID_IMAGE_MASK (1u << FUSE_WIPE_INVALID_IMAGE_SHIFT) 101 | #define FUSE_WIPE_INVALID_IMAGE \ 102 | ((HW_OCOTP_REG_RD(0x1A) & FUSE_WIPE_INVALID_IMAGE_MASK) >> FUSE_WIPE_INVALID_IMAGE_SHIFT) 103 | 104 | /* XMC_CHECK_EN */ 105 | #define FUSE_XMC_CHK_EN_SHIFT (14u) 106 | #define FUSE_XMC_CHK_EN_MASK (1ul << FUSE_XMC_CHK_EN_SHIFT) 107 | #define FUSE_XMC_CHK_EN_VALUE ((HW_OCOTP_REG_RD(0x17) & FUSE_XMC_CHK_EN_MASK) >> FUSE_XMC_CHK_EN_SHIFT) 108 | 109 | /* ======================== FlexSPI NOR Boot ================================= */ 110 | /* Encrypted XIP */ 111 | #define FUSE_ENCRYPT_XIP_SHIFT 0x01 112 | #define FUSE_ENCRYPT_XIP_MASK (1u << FUSE_ENCRYPT_XIP_SHIFT) 113 | #define FUSE_ENCRYPT_XIP_VALUE ((SRC->SBMR1 & FUSE_ENCRYPT_XIP_MASK) >> FUSE_ENCRYPT_XIP_SHIFT) 114 | 115 | /* FLASH Auto Probe */ 116 | #define FUSE_XSPI_FLASH_AUTO_PROBE_EN_SHIFT 0x00 117 | #define FUSE_XSPI_FLASH_AUTO_PROBE_EN_MASK (1u << FUSE_XSPI_FLASH_AUTO_PROBE_EN_SHIFT) 118 | #define FUSE_XSPI_FLASH_AUTO_PROBE_EN_VALUE \ 119 | \ 120 | ((SRC->SBMR1 & FUSE_XSPI_FLASH_AUTO_PROBE_EN_MASK) >> FUSE_XSPI_FLASH_AUTO_PROBE_EN_SHIFT) 121 | 122 | /* FLASH Auto Probe Type */ 123 | #define FUSE_XSPI_FLASH_AUTO_PROBE_TYPE_SHIFT 0x02 124 | #define FUSE_XSPI_FLASH_AUTO_PROBE_TYPE_MASK (0x03u << FUSE_XSPI_FLASH_AUTO_PROBE_TYPE_SHIFT) 125 | #define FUSE_XSPI_FLASH_AUTO_PROBE_TYPE_VALUE \ 126 | \ 127 | ((SRC->SBMR1 & FUSE_XSPI_FLASH_AUTO_PROBE_TYPE_MASK) >> FUSE_XSPI_FLASH_AUTO_PROBE_TYPE_SHIFT) 128 | 129 | /* Flash Type */ 130 | #define FUSE_FLASH_TYPE_SHIFT ((uint8_t)8) 131 | #define FUSE_FLASH_TYPE_MASK (0x07 << FUSE_FLASH_TYPE_SHIFT) 132 | #define FUSE_FLASH_TYPE_VALUE ((SRC->SBMR1 & FUSE_FLASH_TYPE_MASK) >> FUSE_FLASH_TYPE_SHIFT) 133 | /* FlexSPI Index */ 134 | #define FUSE_FLEXSPI_INSTANCE_SHIFT ((uint8_t)11) 135 | #define FUSE_FLEXSPI_INSTANCE_MASK (0x01 << FUSE_FLEXSPI_INSTANCE_SHIFT) 136 | #define FUSE_FLEXSPI_INSTANCE_VALUE ((SRC->SBMR1 & FUSE_FLEXSPI_INSTANCE_MASK) >> FUSE_FLEXSPI_INSTANCE_SHIFT) 137 | 138 | /* Delay-Cell_Num */ 139 | #define FUSE_DELAY_CELL_NUM_SHIFT ((uint8_t)8) 140 | #define FUSE_DELAY_CELL_NUM_MASK (0x7f << FUSE_DELAY_CELL_NUM_SHIFT) 141 | #define FUSE_DELAY_CELL_NUM_VALUE ((HW_OCOTP_REG_RD(0x19) & FUSE_DELAY_CELL_NUM_MASK) >> FUSE_DELAY_CELL_NUM_SHIFT) 142 | 143 | /* QSPI RESET pin enable */ 144 | #define FUSE_FLEXSPI_RESET_PIN_ENABLE_SHIFT (7U) 145 | #define FUSE_FLEXSPI_RESET_PIN_ENABLE_MASK (1U << FUSE_FLEXSPI_RESET_PIN_ENABLE_SHIFT) 146 | #define FUSE_FLEXSPI_RESET_PIN_ENABLE_VALUE \ 147 | ((HW_OCOTP_REG_RD(0x48) & FUSE_FLEXSPI_RESET_PIN_ENABLE_MASK) >> FUSE_FLEXSPI_RESET_PIN_ENABLE_SHIFT) 148 | 149 | /* FlexSPI JEDEC HW reset enable */ 150 | #define FUSE_FLEXSPI_JEDEC_HW_RESET_PIN_ENABLE_SHIFT (6U) 151 | #define FUSE_FLEXSPI_JEDEC_HW_RESET_PIN_ENABLE_MASK (1U << FUSE_FLEXSPI_JEDEC_HW_RESET_PIN_ENABLE_SHIFT) 152 | #define FUSE_FLEXSPI_JEDEC_HW_RESET_PIN_ENABLE_VALUE \ 153 | ((HW_OCOTP_REG_RD(0x48) & FUSE_FLEXSPI_JEDEC_HW_RESET_PIN_ENABLE_MASK) >> \ 154 | FUSE_FLEXSPI_JEDEC_HW_RESET_PIN_ENABLE_SHIFT) 155 | 156 | /* FlexSPI RESET PIN select */ 157 | #define FUSE_FLEXSPI_RESET_PIN_SEL_SHIFT (5U) 158 | #define FUSE_FLEXSPI_RESET_PIN_SEL_MASK (1U << FUSE_FLEXSPI_RESET_PIN_SEL_SHIFT) 159 | #define FUSE_FLEXSPI_RESET_PIN_SEL_VALUE \ 160 | ((HW_OCOTP_REG_RD(0x48) & FUSE_FLEXSPI_RESET_PIN_SEL_MASK) >> FUSE_FLEXSPI_RESET_PIN_SEL_SHIFT) 161 | 162 | /* Hold_Time */ 163 | #define FUSE_HOLD_TIME_SHIFT (3u) 164 | #define FUSE_HOLD_TIME_MASK (0x03u << FUSE_HOLD_TIME_SHIFT) 165 | #define FUSE_HOLD_TIME_VALUE ((HW_OCOTP_REG_RD(0x48) & FUSE_HOLD_TIME_MASK) >> FUSE_HOLD_TIME_SHIFT) 166 | 167 | /* xSPI FLASH Frequency */ 168 | #define FUSE_XSPI_FLASH_FREQ_SHIFT (0u) 169 | #define FUSE_XSPI_FLASH_FREQ_MASK (0x7u << FUSE_XSPI_FLASH_FREQ_SHIFT) 170 | #define FUSE_XSPI_FLASH_FREQ_VALUE ((HW_OCOTP_REG_RD(0x48) & FUSE_XSPI_FLASH_FREQ_MASK) >> FUSE_XSPI_FLASH_FREQ_SHIFT) 171 | 172 | /* xSPI FLASH Dummy Cycle */ 173 | #define FUSE_XSPI_FLASH_DUMMY_CYCLE_SHIFT (8u) 174 | #define FUSE_XSPI_FLASH_DUMMY_CYCLE_MASK (0xfu << FUSE_XSPI_FLASH_DUMMY_CYCLE_SHIFT) 175 | #define FUSE_XSPI_FLASH_DUMMY_CYCLE_VALUE \ 176 | ((HW_OCOTP_REG_RD(0x48) & FUSE_XSPI_FLASH_DUMMY_CYCLE_MASK) >> FUSE_XSPI_FLASH_DUMMY_CYCLE_SHIFT) 177 | 178 | /* xSPI FLASH image size */ 179 | #define FUSE_XSPI_FLASH_IMG_SIZE_SHIFT (12u) 180 | #define FUSE_XSPI_FLASH_IMG_SIZE_MASK (0x0fu << FUSE_XSPI_FLASH_IMG_SIZE_SHIFT) 181 | #define FUSE_XSPI_FLASH_IMG_SIZE_VALUE \ 182 | \ 183 | ((HW_OCOTP_REG_RD(0x48) & FUSE_XSPI_FLASH_IMG_SIZE_MASK) >> FUSE_XSPI_FLASH_IMG_SIZE_SHIFT) 184 | 185 | /* xSPI FLASH_SEC_IMAGE_OFFSET */ 186 | #define FUSE_XSPI_FLASH_SEC_IMG_OFFSET_SHIFT (16u) 187 | #define FUSE_XSPI_FLASH_SEC_IMG_OFFSET_MASK (0xffu << FUSE_XSPI_FLASH_SEC_IMG_OFFSET_SHIFT) 188 | #define FUSE_XSPI_FLASH_SEC_IMG_OFFSET_VALUE \ 189 | \ 190 | ((HW_OCOTP_REG_RD(0x48) & FUSE_XSPI_FLASH_SEC_IMG_OFFSET_MASK) >> FUSE_XSPI_FLASH_SEC_IMG_OFFSET_SHIFT) 191 | 192 | /* FLEXSPI PIN Group Selection */ 193 | #define FUSE_FLEXSPI_PIN_GROUP_SEL_SHIFT (10u) 194 | #define FUSE_FLEXSPI_PIN_GROUP_SEL_MASK (0x1u << FUSE_FLEXSPI_PIN_GROUP_SEL_SHIFT) 195 | #define FUSE_FLEXSPI_PIN_GROUP_SEL_VALUE \ 196 | \ 197 | ((HW_OCOTP_REG_RD(0x1A) & FUSE_FLEXSPI_PIN_GROUP_SEL_MASK) >> FUSE_FLEXSPI_PIN_GROUP_SEL_SHIFT) 198 | 199 | /* FLEXSPI DQS Pin Group Selection */ 200 | #define FUSE_FLEXSPI_DQS_PIN_SEL_SHIFT (11u) 201 | #define FUSE_FLEXSPI_DQS_PIN_SEL_MASK (0x1u << FUSE_FLEXSPI_DQS_PIN_SEL_SHIFT) 202 | #define FUSE_FLEXSPI_DQS_PIN_SEL_VALUE \ 203 | \ 204 | ((HW_OCOTP_REG_RD(0x1A) & FUSE_FLEXSPI_DQS_PIN_SEL_MASK) >> FUSE_FLEXSPI_DQS_PIN_SEL_SHIFT) 205 | 206 | /* FLEXSPI CONNECTION Selection */ 207 | #define FUSE_FLEXSPI_CONNECTION_SEL_SHIFT (8u) 208 | #define FUSE_FLEXSPI_CONNECTION_SEL_MASK (0x3u << FUSE_FLEXSPI_CONNECTION_SEL_SHIFT) 209 | #define FUSE_FLEXSPI_CONNECTION_SEL_VALUE \ 210 | \ 211 | ((HW_OCOTP_REG_RD(0x1A) & FUSE_FLEXSPI_CONNECTION_SEL_MASK) >> FUSE_FLEXSPI_CONNECTION_SEL_SHIFT) 212 | 213 | /* FlexSPI PAD SETTING ENABLE */ 214 | #define FUSE_FLEXSPI_PAD_SETTING_EN_SHIFT (8u) 215 | #define FUSE_FLEXSPI_PAD_SETTING_EN_MASK (0x1u << FUSE_FLEXSPI_PAD_SETTING_EN_SHIFT) 216 | #define FUSE_FLEXSPI_PAD_SETTING_EN_VALUE \ 217 | \ 218 | ((HW_OCOTP_REG_RD(0x19) & FUSE_FLEXSPI_PAD_SETTING_EN_MASK) >> FUSE_FLEXSPI_PAD_SETTING_EN_SHIFT) 219 | 220 | /* FlexSPI Pad setting override value */ 221 | #define FUSE_FLEXSPI_PAD_SETTING_OVERRIDE_SHIFT (8u) 222 | #define FUSE_FLEXSPI_PAD_SETTING_OVERRIDE_MASK (0x7u << FUSE_FLEXSPI_PAD_SETTING_OVERRIDE_SHIFT) 223 | #define FUSE_FLEXSPI_PAD_SETTING_OVERRIDE_VALUE \ 224 | \ 225 | ((HW_OCOTP_REG_RD(0x47) & FUSE_FLEXSPI_PAD_SETTING_OVERRIDE_MASK) >> FUSE_FLEXSPI_PAD_SETTING_OVERRIDE_SHIFT) 226 | 227 | /* ====================== FlexSPI NAND Boot ================================= */ 228 | /* Safe Frequency */ 229 | #define FUSE_SAFE_FREQ_SHIFT ((uint8_t)5) 230 | #define FUSE_SAFE_FREQ_MASK (1u << FUSE_SAFE_FREQ_SHIFT) 231 | #define FUSE_SAFE_FREQ_VALUE ((SRC->SBMR1 & FUSE_SAFE_FREQ_MASK) >> FUSE_SAFE_FREQ_SHIFT) 232 | 233 | /* COL_Address_width */ 234 | #define FUSE_COL_ADDRESS_WIDTH_SHIFT ((uint8_t)4) 235 | #define FUSE_COL_ADDRESS_WIDTH_MASK (1u << FUSE_COL_ADDRESS_WIDTH_SHIFT) 236 | #define FUSE_COL_ADDRESS_WIDTH_VALUE ((SRC->SBMR1 & FUSE_COL_ADDRESS_WIDTH_MASK) >> FUSE_COL_ADDRESS_WIDTH_SHIFT) 237 | 238 | /* Boot_Search_Stride */ 239 | #define FUSE_SPI_NAND_HOLD_TIME_SHIFT ((uint8_t)2) 240 | #define FUSE_SPI_NAND_HOLD_TIME_MASK (3u << FUSE_SPI_NAND_HOLD_TIME_SHIFT) 241 | #define FUSE_SPI_NAND_HOLD_TIME_VALUE ((SRC->SBMR1 & FUSE_SPI_NAND_HOLD_TIME_MASK) >> FUSE_SPI_NAND_HOLD_TIME_SHIFT) 242 | 243 | /* Boot_Search_Stride */ 244 | #define FUSE_BOOT_SEARCH_STRIDE_SHIFT ((uint8_t)0) 245 | #define FUSE_BOOT_SEARCH_STRIDE_MASK (3u << FUSE_BOOT_SEARCH_STRIDE_SHIFT) 246 | #define FUSE_BOOT_SEARCH_STRIDE_VALUE ((SRC->SBMR1 & FUSE_BOOT_SEARCH_STRIDE_MASK) >> FUSE_BOOT_SEARCH_STRIDE_SHIFT) 247 | 248 | /* Boot_Search_Count */ 249 | #define FUSE_BOOT_SEARCH_COUNT_SHIFT ((uint8_t)8) 250 | #define FUSE_BOOT_SEARCH_COUNT_MASK (1u << FUSE_BOOT_SEARCH_COUNT_SHIFT) 251 | #define FUSE_BOOT_SEARCH_COUNT_VALUE ((SRC->SBMR1 & FUSE_BOOT_SEARCH_COUNT_MASK) >> FUSE_BOOT_SEARCH_COUNT_SHIFT) 252 | 253 | /* CS_Interval */ 254 | #define FUSE_CS_INTERVAL_SHIFT ((uint8_t)9) 255 | #define FUSE_CS_INTERVAL_MASK (0x3u << FUSE_CS_INTERVAL_SHIFT) 256 | #define FUSE_CS_INTERVAL_VALUE ((SRC->SBMR1 & FUSE_CS_INTERVAL_MASK) >> FUSE_CS_INTERVAL_SHIFT) 257 | 258 | /* SPI NAND Boot - override Busy Offset */ 259 | #define FUSE_SPI_NAND_BOOT_BUSY_BIT_OFFSET_OVERRIDE_SHIFT ((uint8_t)7) 260 | #define FUSE_SPI_NAND_BOOT_BUSY_BIT_OFFSET_OVERRIDE_MASK (1u << FUSE_SPI_NAND_BOOT_BUSY_BIT_OFFSET_OVERRIDE_SHIFT) 261 | #define FUSE_SPI_NAND_BOOT_BUSY_BIT_OFFSET_OVERRIDE_VALUE \ 262 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SPI_NAND_BOOT_BUSY_BIT_OFFSET_OVERRIDE_MASK) >> \ 263 | FUSE_SPI_NAND_BOOT_BUSY_BIT_OFFSET_OVERRIDE_SHIFT) 264 | 265 | /* SPI NAND Boot - Busy Bit Offset */ 266 | #define FUSE_SPI_NAND_BOOT_BUSY_BIT_OFFSET_SHIFT ((uint8_t)8) 267 | #define FUSE_SPI_NAND_BOOT_BUSY_BIT_OFFSET_MASK (0x3fu << FUSE_SPI_NAND_BOOT_BUSY_BIT_OFFSET_SHIFT) 268 | #define FUSE_SPI_NAND_BOOT_BUSY_BIT_OFFSET_VALUE \ 269 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SPI_NAND_BOOT_BUSY_BIT_OFFSET_MASK) >> FUSE_SPI_NAND_BOOT_BUSY_BIT_OFFSET_SHIFT) 270 | 271 | /* Bypass_ECC_Read */ 272 | #define FUSE_BYPASS_ECC_READ_SHIFT ((uint8_t)14) 273 | #define FUSE_BYPASS_ECC_READ_MASK (1u << FUSE_BYPASS_ECC_READ_SHIFT) 274 | #define FUSE_BYPASS_ECC_READ_VALUE ((HW_OCOTP_REG_RD(0x48) & FUSE_BYPASS_ECC_READ_MASK) >> FUSE_BYPASS_ECC_READ_SHIFT) 275 | 276 | /* Bypass_Read_Status */ 277 | #define FUSE_BYPASS_READ_STATUS_SHIFT ((uint8_t)15) 278 | #define FUSE_BYPASS_READ_STATUS_MASK (1u << FUSE_BYPASS_READ_STATUS_SHIFT) 279 | #define FUSE_BYPASS_READ_STATUS_VALUE \ 280 | ((HW_OCOTP_REG_RD(0x48) & FUSE_BYPASS_READ_STATUS_MASK) >> FUSE_BYPASS_READ_STATUS_SHIFT) 281 | 282 | /* SPI NAND BOOT - Page read time */ 283 | #define FUSE_SPI_NAND_BOOT_PAGE_RD_TIME_SHIFT ((uint8_t)0) 284 | #define FUSE_SPI_NAND_BOOT_PAGE_RD_TIME_MASK (0x3ful << FUSE_SPI_NAND_BOOT_PAGE_RD_TIME_SHIFT) 285 | #define FUSE_SPI_NAND_BOOT_PAGE_RD_TIME_VALUE \ 286 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SPI_NAND_BOOT_PAGE_RD_TIME_MASK) >> FUSE_SPI_NAND_BOOT_PAGE_RD_TIME_SHIFT) 287 | 288 | /* SPI NAND BOOT - page read cmd */ 289 | #define FUSE_SPI_NAND_BOOT_PAGE_RD_CMD_SHIFT ((uint8_t)16) 290 | #define FUSE_SPI_NAND_BOOT_PAGE_RD_CMD_MASK (0xffu << FUSE_SPI_NAND_BOOT_PAGE_RD_CMD_SHIFT) 291 | #define FUSE_SPI_NAND_BOOT_PAGE_RD_CMD_VALUE \ 292 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SPI_NAND_BOOT_PAGE_RD_CMD_MASK) >> FUSE_SPI_NAND_BOOT_PAGE_RD_CMD_SHIFT) 293 | 294 | /* SPI NAND BOOT - cache read cmd */ 295 | #define FUSE_SPI_NAND_BOOT_CACHE_RD_CMD_SHIFT ((uint8_t)24) 296 | #define FUSE_SPI_NAND_BOOT_CACHE_RD_CMD_MASK (0xFFu << FUSE_SPI_NAND_BOOT_CACHE_RD_CMD_SHIFT) 297 | #define FUSE_SPI_NAND_BOOT_CACHE_RD_CMD_VALUE \ 298 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SPI_NAND_BOOT_CACHE_RD_CMD_MASK) >> FUSE_SPI_NAND_BOOT_CACHE_RD_CMD_SHIFT) 299 | 300 | /* ======================== SEMC NAND Boot ================================= */ 301 | /* Boot_Search_Count */ 302 | #define FUSE_SEMC_NAND_SEARCH_COUNT_SHIFT ((uint8_t)0) 303 | #define FUSE_SEMC_NAND_SEARCH_COUNT_MASK (1u << FUSE_SEMC_NAND_SEARCH_COUNT_SHIFT) 304 | #define FUSE_SEMC_NAND_SEARCH_COUNT_VALUE \ 305 | ((SRC->SBMR1 & FUSE_SEMC_NAND_SEARCH_COUNT_MASK) >> FUSE_SEMC_NAND_SEARCH_COUNT_SHIFT) 306 | 307 | /* Boot_Search_Stride */ 308 | #define FUSE_SEMC_NAND_SEARCH_STRIDE_SHIFT ((uint8_t)1) 309 | #define FUSE_SEMC_NAND_SEARCH_STRIDE_MASK (0xFu << FUSE_SEMC_NAND_SEARCH_STRIDE_SHIFT) 310 | #define FUSE_SEMC_NAND_SEARCH_STRIDE_VALUE \ 311 | ((SRC->SBMR1 & FUSE_SEMC_NAND_SEARCH_STRIDE_MASK) >> FUSE_SEMC_NAND_SEARCH_STRIDE_SHIFT) 312 | 313 | /* ONFI compliant */ 314 | #define FUSE_SEMC_NAND_ONFI_COMPLIANT_SHIFT ((uint8_t)8) 315 | #define FUSE_SEMC_NAND_ONFI_COMPLIANT_MASK (1u << FUSE_SEMC_NAND_ONFI_COMPLIANT_SHIFT) 316 | #define FUSE_SEMC_NAND_ONFI_COMPLIANT_VALUE \ 317 | ((SRC->SBMR1 & FUSE_SEMC_NAND_ONFI_COMPLIANT_MASK) >> FUSE_SEMC_NAND_ONFI_COMPLIANT_SHIFT) 318 | 319 | /* EDO mode */ 320 | #define FUSE_SEMC_NAND_EDO_MODE_SHIFT ((uint8_t)9) 321 | #define FUSE_SEMC_NAND_EDO_MODE_MASK (1u << FUSE_SEMC_NAND_EDO_MODE_SHIFT) 322 | #define FUSE_SEMC_NAND_EDO_MODE_VALUE ((SRC->SBMR1 & FUSE_SEMC_NAND_EDO_MODE_MASK) >> FUSE_SEMC_NAND_EDO_MODE_SHIFT) 323 | 324 | /* Memory Access Command */ 325 | #define FUSE_SEMC_NAND_ACCESS_COMMAND_SHIFT ((uint8_t)10) 326 | #define FUSE_SEMC_NAND_ACCESS_COMMAND_MASK (1u << FUSE_SEMC_NAND_ACCESS_COMMAND_SHIFT) 327 | #define FUSE_SEMC_NAND_ACCESS_COMMAND_VALUE \ 328 | ((SRC->SBMR1 & FUSE_SEMC_NAND_ACCESS_COMMAND_MASK) >> FUSE_SEMC_NAND_ACCESS_COMMAND_SHIFT) 329 | 330 | /* I/O Port_width */ 331 | #define FUSE_SEMC_NAND_IO_PORT_WIDTH_SHIFT ((uint8_t)3) 332 | #define FUSE_SEMC_NAND_IO_PORT_WIDTH_MASK (1u << FUSE_SEMC_NAND_IO_PORT_WIDTH_SHIFT) 333 | #define FUSE_SEMC_NAND_IO_PORT_WIDTH_VALUE \ 334 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SEMC_NAND_IO_PORT_WIDTH_MASK) >> FUSE_SEMC_NAND_IO_PORT_WIDTH_SHIFT) 335 | 336 | /* ECC Type */ 337 | #define FUSE_SEMC_NAND_ECC_TYPE_SHIFT ((uint8_t)4) 338 | #define FUSE_SEMC_NAND_ECC_TYPE_MASK (1u << FUSE_SEMC_NAND_ECC_TYPE_SHIFT) 339 | #define FUSE_SEMC_NAND_ECC_TYPE_VALUE \ 340 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SEMC_NAND_ECC_TYPE_MASK) >> FUSE_SEMC_NAND_ECC_TYPE_SHIFT) 341 | 342 | /* RDY Polarity */ 343 | #define FUSE_SEMC_NAND_RDY_POLARITY_SHIFT ((uint8_t)5) 344 | #define FUSE_SEMC_NAND_RDY_POLARITY_MASK (1u << FUSE_SEMC_NAND_RDY_POLARITY_SHIFT) 345 | #define FUSE_SEMC_NAND_RDY_POLARITY_VALUE \ 346 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SEMC_NAND_RDY_POLARITY_MASK) >> FUSE_SEMC_NAND_RDY_POLARITY_SHIFT) 347 | 348 | /* Ready Check type */ 349 | #define FUSE_SEMC_NAND_READY_CHECK_TYPE_SHIFT ((uint8_t)6) 350 | #define FUSE_SEMC_NAND_READY_CHECK_TYPE_MASK (1u << FUSE_SEMC_NAND_READY_CHECK_TYPE_SHIFT) 351 | #define FUSE_SEMC_NAND_READY_CHECK_TYPE_VALUE \ 352 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SEMC_NAND_READY_CHECK_TYPE_MASK) >> FUSE_SEMC_NAND_READY_CHECK_TYPE_SHIFT) 353 | 354 | /* Clock Frequency */ 355 | #define FUSE_SEMC_NAND_CLK_FREQ_SHIFT ((uint8_t)7) 356 | #define FUSE_SEMC_NAND_CLK_FREQ_MASK (1u << FUSE_SEMC_NAND_CLK_FREQ_SHIFT) 357 | #define FUSE_SEMC_NAND_CLK_FREQ_VALUE \ 358 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SEMC_NAND_CLK_FREQ_MASK) >> FUSE_SEMC_NAND_CLK_FREQ_SHIFT) 359 | 360 | /* Row Column address mode */ 361 | #define FUSE_SEMC_NAND_ROW_COL_ADDR_MODE_SHIFT ((uint8_t)8) 362 | #define FUSE_SEMC_NAND_ROW_COL_ADDR_MODE_MASK (0x07u << FUSE_SEMC_NAND_ROW_COL_ADDR_MODE_SHIFT) 363 | #define FUSE_SEMC_NAND_ROW_COL_ADDR_MODE_VALUE \ 364 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SEMC_NAND_ROW_COL_ADDR_MODE_MASK) >> FUSE_SEMC_NAND_ROW_COL_ADDR_MODE_SHIFT) 365 | 366 | /* COL_Address_width */ 367 | #define FUSE_SEMC_NAND_COL_ADDRESS_WIDTH_SHIFT ((uint8_t)11) 368 | #define FUSE_SEMC_NAND_COL_ADDRESS_WIDTH_MASK (0x7u << FUSE_SEMC_NAND_COL_ADDRESS_WIDTH_SHIFT) 369 | #define FUSE_SEMC_NAND_COL_ADDRESS_WIDTH_VALUE \ 370 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SEMC_NAND_COL_ADDRESS_WIDTH_MASK) >> FUSE_SEMC_NAND_COL_ADDRESS_WIDTH_SHIFT) 371 | 372 | /* Status Command Type */ 373 | #define FUSE_SEMC_NAND_STATUS_CMD_TYPE_SHIFT ((uint8_t)14) 374 | #define FUSE_SEMC_NAND_STATUS_CMD_TYPE_MASK (1u << FUSE_SEMC_NAND_STATUS_CMD_TYPE_SHIFT) 375 | #define FUSE_SEMC_NAND_STATUS_CMD_TYPE_VALUE \ 376 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SEMC_NAND_STATUS_CMD_TYPE_MASK) >> FUSE_SEMC_NAND_STATUS_CMD_TYPE_SHIFT) 377 | 378 | /* Pages in block */ 379 | #define FUSE_SEMC_NAND_PAGES_IN_BLOCK_SHIFT ((uint8_t)16) 380 | #define FUSE_SEMC_NAND_PAGES_IN_BLOCK_MASK (0x07 << FUSE_SEMC_NAND_PAGES_IN_BLOCK_SHIFT) 381 | #define FUSE_SEMC_NAND_PAGES_IN_BLOCK_VALUE \ 382 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SEMC_NAND_PAGES_IN_BLOCK_MASK) >> FUSE_SEMC_NAND_PAGES_IN_BLOCK_SHIFT) 383 | 384 | /* PCS selection */ 385 | #define FUSE_SEMC_NAND_PCS_SELECTION_SHIFT ((uint8_t)19) 386 | #define FUSE_SEMC_NAND_PCS_SELECTION_MASK (0x07 << FUSE_SEMC_NAND_PCS_SELECTION_SHIFT) 387 | #define FUSE_SEMC_NAND_PCS_SELECTION_VALUE \ 388 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SEMC_NAND_PCS_SELECTION_MASK) >> FUSE_SEMC_NAND_PCS_SELECTION_SHIFT) 389 | 390 | /* Device ECC initial status */ 391 | #define FUSE_SEMC_NAND_DEVICE_ECC_STATUS_SHIFT ((uint8_t)24) 392 | #define FUSE_SEMC_NAND_DEVICE_ECC_STATUS_MASK (1u << FUSE_SEMC_NAND_DEVICE_ECC_STATUS_SHIFT) 393 | #define FUSE_SEMC_NAND_DEVICE_ECC_STATUS_VALUE \ 394 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SEMC_NAND_DEVICE_ECC_STATUS_MASK) >> FUSE_SEMC_NAND_DEVICE_ECC_STATUS_SHIFT) 395 | 396 | /* ONFI Timing mode */ 397 | #define FUSE_SEMC_NAND_TIMING_MODE_SHIFT ((uint8_t)25) 398 | #define FUSE_SEMC_NAND_TIMING_MODE_MASK (0x07u << FUSE_SEMC_NAND_TIMING_MODE_SHIFT) 399 | #define FUSE_SEMC_NAND_TIMING_MODE_VALUE \ 400 | ((HW_OCOTP_REG_RD(0x48) & FUSE_SEMC_NAND_TIMING_MODE_MASK) >> FUSE_SEMC_NAND_TIMING_MODE_SHIFT) 401 | 402 | /* ========================== Recovery boot ======================================= */ 403 | /* Enable Recovery boot */ 404 | #define FUSE_RECOVERY_SPI_EEPROM_BOOT_ENABLE_SHIFT 24 405 | #define FUSE_RECOVERY_SPI_EEPROM_BOOT_ENABLE_MASK (1u << FUSE_RECOVERY_SPI_EEPROM_BOOT_ENABLE_SHIFT) 406 | #define FUSE_RECOVERY_SPI_EEPROM_BOOT_ENABLE_VALUE \ 407 | ((HW_OCOTP_REG_RD(0x47) & FUSE_RECOVERY_SPI_EEPROM_BOOT_ENABLE_MASK) >> FUSE_RECOVERY_SPI_EEPROM_BOOT_ENABLE_SHIFT) 408 | 409 | /* SPI_INSTANCE */ 410 | #define FUSE_SPI_INSTANCE_SHIFT ((uint8_t)25) 411 | #define FUSE_SPI_INSTANCE_MASK (0x3 << FUSE_SPI_INSTANCE_SHIFT) 412 | #define FUSE_SPI_INSTANCE_VALUE ((HW_OCOTP_REG_RD(0x47) & FUSE_SPI_INSTANCE_MASK) >> FUSE_SPI_INSTANCE_SHIFT) 413 | 414 | /* SPI_Memory_Speed */ 415 | #define FUSE_SPI_MEMORY_SPEED_SHIFT ((uint8_t)27) 416 | #define FUSE_SPI_MEMORY_SPEED_MASK (0x3 << FUSE_SPI_MEMORY_SPEED_SHIFT) 417 | #define FUSE_SPI_MEMORY_SPEED_VALUE \ 418 | ((HW_OCOTP_REG_RD(0x47) & FUSE_SPI_MEMORY_SPEED_MASK) >> FUSE_SPI_MEMORY_SPEED_SHIFT) 419 | 420 | /* ========================== LP boot ======================================= */ 421 | #define FUSE_LPB_BOOT_SHIFT 4 422 | #define FUSE_LPB_BOOT_MASK (0x03 << FUSE_LPB_BOOT_SHIFT) 423 | #define FUSE_LPB_BOOT_VALUE ((HW_OCOTP_REG_RD(0x1a) & FUSE_LPB_BOOT_MASK) >> FUSE_LPB_BOOT_SHIFT) 424 | 425 | #define FUSE_BOOT_FREQ_SHIFT 0x03 426 | #define FUSE_BOOT_FREQ_MASK (1u << FUSE_BOOT_FREQ_SHIFT) 427 | #define FUSE_BOOT_FREQ_VALUE ((HW_OCOTP_REG_RD(0x1a) & FUSE_BOOT_FREQ_MASK) >> FUSE_BOOT_FREQ_SHIFT) 428 | 429 | #define FUSE_BOOT_OSC_REF_SHIFT 0x02 430 | #define FUSE_BOOT_OSC_REF_MASK (1u << FUSE_BOOT_OSC_REF_SHIFT) 431 | #define FUSE_BOOT_OSC_REF_VALUE ((HW_OCOTP_REG_RD(0x1a) & FUSE_BOOT_OSC_REF_MASK) >> FUSE_BOOT_OSC_REF_SHIFT) 432 | 433 | /* ========================== Boot Failure Indicator Pin ====================== */ 434 | /* Enable_Boot_Failure_Indicator pin */ 435 | #define BOOT_FAIL_INDICATOR_ENABLE_SHIFT ((uint8_t)5) 436 | #define BOOT_FAIL_INDICATOR_ENABLE_MASK (1u << BOOT_FAIL_INDICATOR_ENABLE_SHIFT) 437 | #define BOOT_FAIL_INDICATOR_ENABLE_VALUE \ 438 | ((HW_OCOTP_REG_RD(0x19) & BOOT_FAIL_INDICATOR_ENABLE_MASK) >> BOOT_FAIL_INDICATOR_ENABLE_SHIFT) 439 | 440 | #define BOOT_FAIL_INDICATOR_PIN_SHIFT ((uint8_t)0) 441 | #define BOOT_FAIL_INDICATOR_PIN_MASK (0x1F << BOOT_FAIL_INDICATOR_PIN_SHIFT) 442 | #define BOOT_FAIL_INDICATOR_PIN_VALUE \ 443 | ((HW_OCOTP_REG_RD(0x19) & BOOT_FAIL_INDICATOR_PIN_MASK) >> BOOT_FAIL_INDICATOR_PIN_SHIFT) 444 | 445 | /* ============================ Secure boot =================================== */ 446 | 447 | /* TESTPORT_DISABLE */ 448 | #define FUSE_TESTPORT_DISABLE_SHIFT ((uint8_t)3) 449 | #define FUSE_TESTPORT_DISABLE_MASK (0x1u << FUSE_TESTPORT_DISABLE_SHIFT) 450 | #define FUSE_FUSE_TESTPORT_DISABLE_VALUE \ 451 | ((HW_OCOTP_REG_RD(0x0D) & FUSE_TESTPORT_DISABLE_MASK) >> FUSE_TESTPORT_DISABLE_SHIFT) 452 | 453 | /* FIELD_RETURN */ 454 | #define FUSE_FIELD_RETURN_SHIFT ((uint8_t)4) 455 | #define FUSE_FIELD_RETURN_MASK (0xFu << FUSE_FIELD_RETURN_SHIFT) 456 | #define FUSE_FIELD_RETURN_VALUE ((HW_OCOTP_REG_RD(0x0D) & FUSE_FIELD_RETURN_MASK) >> FUSE_FIELD_RETURN_SHIFT) 457 | 458 | /* SEC Config[0] */ 459 | #define FUSE_SEC_CONFIG0_FUSE_WORD_IDX (0x0E) 460 | #define FUSE_SEC_CONFIG0_SHIFT ((uint8_t)1) 461 | #define FUSE_SEC_CONFIG0_MASK (1u << FUSE_SEC_CONFIG0_SHIFT) 462 | #define FUSE_SEC_CONFIG0_VALUE ((HW_OCOTP_REG_RD(0x0E) & FUSE_SEC_CONFIG0_MASK) >> FUSE_SEC_CONFIG0_SHIFT) 463 | /* SEC_Config[1] */ 464 | #define FUSE_SEC_CONFIG1_FUSE_WORD_IDX (0x16) 465 | #define FUSE_SEC_CONFIG1_SHIFT ((uint8_t)1) 466 | #define FUSE_SEC_CONFIG1_MASK (1u << FUSE_SEC_CONFIG1_SHIFT) 467 | #define FUSE_SEC_CONFIG1_VALUE ((HW_OCOTP_REG_RD(0x16) & FUSE_SEC_CONFIG1_MASK) >> FUSE_SEC_CONFIG1_SHIFT) 468 | #define FUSE_SEC_CONFIG_VALUE (FUSE_SEC_CONFIG0_VALUE | (FUSE_SEC_CONFIG1_VALUE << 1)) 469 | 470 | /* AP_BI_VER */ 471 | #define FUSE_AP_BI_VER_SHIFT ((uint8_t)0) 472 | #define FUSE_AP_BI_VER_MASK (0xFFFFu << FUSE_AP_BI_VER_SHIFT) 473 | #define FUSE_AP_BI_VER_VALUE ((HW_OCOTP_REG_RD(0x0B) & FUSE_AP_BI_VER_MASK) >> FUSE_AP_BI_VER_SHIFT) 474 | 475 | /* ============================ Encrypt boot =================================== */ 476 | #define FUSE_ENCRYPT_XIP_ENGINE_SHIFT (12u) 477 | #define FUSE_ENCRYPT_XIP_ENGINE_MASK (1u << FUSE_ENCRYPT_XIP_ENGINE_SHIFT) 478 | #define FUSE_ENCRYPT_XIP_ENGINE \ 479 | ((HW_OCOTP_REG_RD(0x17) & FUSE_ENCRYPT_XIP_ENGINE_MASK) >> FUSE_ENCRYPT_XIP_ENGINE_SHIFT) 480 | 481 | #define FUSE_PUF_ZEROIZE_SHIFT (13u) 482 | #define FUSE_PUF_ZEROIZE_MASK (1u << FUSE_PUF_ZEROIZE_SHIFT) 483 | #define FUSE_PUF_ZEROIZE ((HW_OCOTP_REG_RD(0x17) & FUSE_PUF_ZEROIZE_MASK) >> FUSE_PUF_ZEROIZE_SHIFT) 484 | 485 | #define FUSE_OTFAD1_KEY_SEL_SHIFT (4) 486 | #define FUSE_OTFAD1_KEY_SEL_MASK (1u << FUSE_OTFAD1_KEY_SEL_SHIFT) 487 | #define FUSE_OTFAD1_KEY_SEL_VALUE ((HW_OCOTP_REG_RD(0xE) & FUSE_OTFAD1_KEY_SEL_MASK) >> FUSE_OTFAD1_KEY_SEL_SHIFT) 488 | 489 | #define FUSE_OTFAD2_KEY_SEL_SHIFT (6) 490 | #define FUSE_OTFAD2_KEY_SEL_MASK (1u << FUSE_OTFAD2_KEY_SEL_SHIFT) 491 | #define FUSE_OTFAD2_KEY_SEL_VALUE ((HW_OCOTP_REG_RD(0xE) & FUSE_OTFAD2_KEY_SEL_MASK) >> FUSE_OTFAD2_KEY_SEL_SHIFT) 492 | 493 | /* OTFAD1_DISABLE */ 494 | #define FUSE_OTFAD1_DISABLE_SHIFT (10) 495 | #define FUSE_OTFAD1_DISABLE_MASK (1u << FUSE_OTFAD1_DISABLE_SHIFT) 496 | #define FUSE_OTFAD1_DISABLE_VALUE ((HW_OCOTP_REG_RD(0x6) & FUSE_OTFAD1_DISABLE_MASK) >> FUSE_OTFAD1_DISABLE_SHIFT) 497 | 498 | /* OTFAD2 DISABLE */ 499 | #define FUSE_OTFAD2_DISABLE_SHIFT (11) 500 | #define FUSE_OTFAD2_DISABLE_MASK (1u << FUSE_OTFAD2_DISABLE_SHIFT) 501 | #define FUSE_OTFAD2_DISABLE_VALUE ((HW_OCOTP_REG_RD(0x6) & FUSE_OTFAD2_DISABLE_MASK) >> FUSE_OTFAD2_DISABLE_SHIFT) 502 | 503 | /* CAAM Disable */ 504 | #define FUSE_CAAM_DISABLE_SHIFT (9) 505 | #define FUSE_CAAM_DISABLE_MASK (1u << FUSE_CAAM_DISABLE_SHIFT) 506 | #define FUSE_CAAM_DISABLE_VALUE ((HW_OCOTP_REG_RD(0x6) & FUSE_CAAM_DISABLE_MASK) >> FUSE_CAAM_DISABLE_SHIFT) 507 | 508 | /* IEE disable */ 509 | #define FUSE_IEE_DISABLE_SHIFT (8) 510 | #define FUSE_IEE_DISABLE_MASK (1u << FUSE_IEE_DISABLE_SHIFT) 511 | #define FUSE_IEE_DISABLE_VALUE ((HW_OCOTP_REG_RD(0x6) & FUSE_IEE_DISABLE_MASK) >> FUSE_IEE_DISABLE_SHIFT) 512 | 513 | /* DRYICE disable */ 514 | #define FUSE_DRYICE_DISABLE_SHIFT (5) 515 | #define FUSE_DRYICE_DISABLE_MASK (1u << FUSE_DRYICE_DISABLE_SHIFT) 516 | #define FUSE_DRYICE_DISABLE_VALUE ((HW_OCOTP_REG_RD(0x6) & FUSE_DRYICE_DISABLE_MASK) >> FUSE_DRYICE_DISABLE_SHIFT) 517 | 518 | /* RDC disable */ 519 | #define FUSE_RDC_DISABLE_SHIFT (12) 520 | #define FUSE_RDC_DISABLE_MASK (1u << FUSE_RDC_DISABLE_SHIFT) 521 | #define FUSE_RDC_DISABLE_VALUE ((HW_OCOTP_REG_RD(0x6) & FUSE_RDC_DISABLE_MASK) >> FUSE_RDC_DISABLE_SHIFT) 522 | 523 | /* XRDC disable */ 524 | #define FUSE_XRDC_DISABLE_SHIFT (13) 525 | #define FUSE_XRDC_DISABLE_MASK (1u << FUSE_XRDC_DISABLE_SHIFT) 526 | #define FUSE_XRDC_DISABLE_VALUE (HW_OCOTP_REG_RD(0x6) & FUSE_XRDC_DISABLE_MASK) >> FUSE_XRDC_DISABLE_SHIFT) 527 | 528 | /* UDF Enable */ 529 | #define FUSE_UDF_ENABLE_SHIFT (7) 530 | #define FUSE_UDF_ENABLE_MASK (1u << FUSE_UDF_ENABLE_SHIFT) 531 | #define FUSE_UDF_ENABLE_VALUE ((HW_OCOTP_REG_RD(0x6) & FUSE_UDF_ENABLE_MASK) >> FUSE_UDF_ENABLE_SHIFT) 532 | 533 | /* PUF Enable */ 534 | #define FUSE_PUF_ENABLE_SHIFT (6) 535 | #define FUSE_PUF_ENABLE_MASK (1u << FUSE_PUF_ENABLE_SHIFT) 536 | #define FUSE_PUF_ENABLE_VALUE ((HW_OCOTP_REG_RD(0x6) & FUSE_PUF_ENABLE_MASK) >> FUSE_PUF_ENABLE_SHIFT) 537 | 538 | /*OTFAD1 SCRAMBLE EN */ 539 | #define FUSE_OTFAD1_SCRAMBLE_EN_SHIFT (0) 540 | #define FUSE_OTFAD1_SCRAMBLE_EN_MASK (1u << FUSE_OTFAD1_SCRAMBLE_EN_SHIFT) 541 | #define FUSE_OTFAD1_SCRAMBLE_EN_VALUE \ 542 | ((HW_OCOTP_REG_RD(0x47) & FUSE_OTFAD1_SCRAMBLE_EN_MASK) >> FUSE_OTFAD1_SCRAMBLE_EN_SHIFT) 543 | 544 | /*OTFAD1 KEYBLOB EN */ 545 | #define FUSE_OTFAD1_KEYBLOB_EN_SHIFT (1) 546 | #define FUSE_OTFAD1_KEYBLOB_EN_MASK (1u << FUSE_OTFAD1_KEYBLOB_EN_SHIFT) 547 | #define FUSE_OTFAD1_KEYBLOB_EN_VALUE \ 548 | ((HW_OCOTP_REG_RD(0x47) & FUSE_OTFAD1_KEYBLOB_EN_MASK) >> FUSE_OTFAD1_KEYBLOB_EN_SHIFT) 549 | 550 | /*OTFAD1 RESTRICT IPS EN */ 551 | #define FUSE_OTFAD1_RESTRICT_IP_EN_SHIFT (2) 552 | #define FUSE_OTFAD1_RESTRICT_IP_EN_MASK (1u << FUSE_OTFAD1_RESTRICT_IP_EN_SHIFT) 553 | #define FUSE_OTFAD1_RESTRICT_IP_EN_VALUE \ 554 | ((HW_OCOTP_REG_RD(0x47) & FUSE_OTFAD1_RESTRICT_IP_EN_MASK) >> FUSE_OTFAD1_RESTRICT_IP_EN_SHIFT) 555 | 556 | /*OTFAD1 KEYBLOB_CRC EN */ 557 | #define FUSE_OTFAD1_KEYBLOB_CRC_EN_SHIFT (3) 558 | #define FUSE_OTFAD1_KEYBLOB_CRC_EN_MASK (1u << FUSE_OTFAD1_KEYBLOB_CRC_EN_SHIFT) 559 | #define FUSE_OTFAD1_KEYBLOB_CRC_EN_VALUE \ 560 | ((HW_OCOTP_REG_RD(0x47) & FUSE_OTFAD1_KEYBLOB_CRC_EN_MASK) >> FUSE_OTFAD1_KEYBLOB_CRC_EN_SHIFT) 561 | 562 | /*OTFAD2 SCRAMBLE EN */ 563 | #define FUSE_OTFAD2_SCRAMBLE_EN_SHIFT (4) 564 | #define FUSE_OTFAD2_SCRAMBLE_EN_MASK (1u << FUSE_OTFAD2_SCRAMBLE_EN_SHIFT) 565 | #define FUSE_OTFAD2_SCRAMBLE_EN_VALUE \ 566 | ((HW_OCOTP_REG_RD(0x47) & FUSE_OTFAD2_SCRAMBLE_EN_MASK) >> FUSE_OTFAD2_SCRAMBLE_EN_SHIFT) 567 | 568 | /*OTFAD2 KEYBLOB EN */ 569 | #define FUSE_OTFAD2_KEYBLOB_EN_SHIFT (5) 570 | #define FUSE_OTFAD2_KEYBLOB_EN_MASK (1u << FUSE_OTFAD2_KEYBLOB_EN_SHIFT) 571 | #define FUSE_OTFAD2_KEYBLOB_EN_VALUE \ 572 | ((HW_OCOTP_REG_RD(0x47) & FUSE_OTFAD2_KEYBLOB_EN_MASK) >> FUSE_OTFAD2_KEYBLOB_EN_SHIFT) 573 | 574 | /*OTFAD2 RESTRICT IPS EN */ 575 | #define FUSE_OTFAD2_RESTRICT_IP_EN_SHIFT (6) 576 | #define FUSE_OTFAD2_RESTRICT_IP_EN_MASK (1u << FUSE_OTFAD2_RESTRICT_IP_EN_SHIFT) 577 | #define FUSE_OTFAD2_RESTRICT_IP_EN_VALUE \ 578 | ((HW_OCOTP_REG_RD(0x47) & FUSE_OTFAD2_RESTRICT_IP_EN_MASK) >> FUSE_OTFAD2_RESTRICT_IP_EN_SHIFT) 579 | 580 | /*OTFAD2 KEYBLOB_CRC EN */ 581 | #define FUSE_OTFAD2_KEYBLOB_CRC_EN_SHIFT (7) 582 | #define FUSE_OTFAD2_KEYBLOB_CRC_EN_MASK (1u << FUSE_OTFAD2_KEYBLOB_CRC_EN_SHIFT) 583 | #define FUSE_OTFAD2_KEYBLOB_CRC_EN_VALUE \ 584 | ((HW_OCOTP_REG_RD(0x47) & FUSE_OTFAD2_KEYBLOB_CRC_EN_MASK) >> FUSE_OTFAD2_KEYBLOB_CRC_EN_SHIFT) 585 | 586 | /* ========================== MMC/SD boot(Common Part)======================================= */ 587 | /* Card Type selection, eMMC or SD. */ 588 | #define FUSE_SDMMC_TYPE_SEL_SHIFT ((uint8_t)6) 589 | #define FUSE_SDMMC_TYPE_SEL_MASK ((uint32_t)(0x3 << FUSE_SDMMC_TYPE_SEL_SHIFT)) 590 | #define FUSE_SDMMC_TYPE_SEL_VALUE ((SRC->SBMR1 & FUSE_SDMMC_TYPE_SEL_MASK) >> FUSE_SDMMC_TYPE_SEL_SHIFT) 591 | 592 | /* SD1 VOLTAGE SELECTION */ 593 | #define FUSE_SD1_VOLTAGE_SELECTION_SHIFT ((uint8_t)3) 594 | #define FUSE_SD1_VOLTAGE_SELECTION_MASK ((uint32_t)(0x1 << FUSE_SD1_VOLTAGE_SELECTION_SHIFT)) 595 | #define FUSE_SD1_VOLTAGE_SELECTION_VALUE \ 596 | ((HW_OCOTP_REG_RD(0x17) & FUSE_SD1_VOLTAGE_SELECTION_MASK) >> FUSE_SD1_VOLTAGE_SELECTION_SHIFT) 597 | 598 | /* SD2 VOLTAGE SELECTION */ 599 | #define FUSE_SD2_VOLTAGE_SELECTION_SHIFT ((uint8_t)8) 600 | #define FUSE_SD2_VOLTAGE_SELECTION_MASK ((uint32_t)(0x1 << FUSE_SD2_VOLTAGE_SELECTION_SHIFT)) 601 | #define FUSE_SD2_VOLTAGE_SELECTION_VALUE \ 602 | ((SRC->SBMR1 & FUSE_SD2_VOLTAGE_SELECTION_MASK) >> FUSE_SD2_VOLTAGE_SELECTION_SHIFT) 603 | 604 | /* SD Loopback_Clock_Source */ 605 | #define FUSE_SDMMC_LOOPBACK_CLK_SOURCE_SHIFT ((uint8_t)2) 606 | #define FUSE_SDMMC_LOOPBACK_CLK_SOURCE_MASK ((uint32_t)(0x1 << FUSE_SDMMC_LOOPBACK_CLK_SOURCE_SHIFT)) 607 | #define FUSE_SDMMC_LOOPBACK_CLK_SOURCE_VALUE \ 608 | ((SRC->SBMR1 & FUSE_SDMMC_LOOPBACK_CLK_SOURCE_MASK) >> FUSE_SDMMC_LOOPBACK_CLK_SOURCE_SHIFT) 609 | 610 | /* SD/MMC/eMMC Fast_Boot */ 611 | #define FUSE_SDMMC_FAST_BOOT_SHIFT ((uint8_t)0) 612 | #define FUSE_SDMMC_FAST_BOOT_MASK ((uint32_t)(0x1 << FUSE_SDMMC_FAST_BOOT_SHIFT)) 613 | #define FUSE_SDMMC_FAST_BOOT_VALUE ((SRC->SBMR1 & FUSE_SDMMC_FAST_BOOT_MASK) >> FUSE_SDMMC_FAST_BOOT_SHIFT) 614 | 615 | /* Power cycle enable */ 616 | #define FUSE_SDMMC_POWER_CYCLE_ENABLE_SHIFT ((uint8_t)3) 617 | #define FUSE_SDMMC_POWER_CYCLE_ENABLE_MASK ((uint32_t)(0x1 << FUSE_SDMMC_POWER_CYCLE_ENABLE_SHIFT)) 618 | #define FUSE_SDMMC_POWER_CYCLE_ENABLE_VALUE \ 619 | ((SRC->SBMR1 & FUSE_SDMMC_POWER_CYCLE_ENABLE_MASK) >> FUSE_SDMMC_POWER_CYCLE_ENABLE_SHIFT) 620 | 621 | /* Power cycle selection */ 622 | #define FUSE_SDMMC_PWR_CYCLE_SEL_SHIFT ((uint8_t)6) 623 | #define FUSE_SDMMC_PWR_CYCLE_SEL_MASK ((uint32_t)(0x3 << FUSE_SDMMC_PWR_CYCLE_SEL_SHIFT)) 624 | #define FUSE_SDMMC_PWR_CYCLE_SEL_VALUE \ 625 | ((HW_OCOTP_REG_RD(0x17) & FUSE_SDMMC_PWR_CYCLE_SEL_MASK) >> FUSE_SDMMC_PWR_CYCLE_SEL_SHIFT) 626 | 627 | /* Power stable cycle selection */ 628 | #define FUSE_SDMMC_PWR_STABLE_CYCLE_SEL_SHIFT ((uint8_t)5) 629 | #define FUSE_SDMMC_PWR_STABLE_CYCLE_SEL_MASK ((uint32_t)(0x1 << FUSE_SDMMC_PWR_STABLE_CYCLE_SEL_SHIFT)) 630 | #define FUSE_SDMMC_PWR_STABLE_CYCLE_SEL_VALUE \ 631 | ((HW_OCOTP_REG_RD(0x17) & FUSE_SDMMC_PWR_STABLE_CYCLE_SEL_MASK) >> FUSE_SDMMC_PWR_STABLE_CYCLE_SEL_SHIFT) 632 | 633 | /* DLL override enable for SD/eMMC */ 634 | #define FUSE_SDMMC_DLL_OVERRIDE_ENABLE_SHIFT ((uint8_t)10) 635 | #define FUSE_SDMMC_DLL_OVERRIDE_ENABLE_MASK ((uint32_t)(0x1 << FUSE_SDMMC_DLL_OVERRIDE_ENABLE_SHIFT)) 636 | #define FUSE_SDMMC_DLL_OVERRIDE_ENABLE_VALUE \ 637 | ((HW_OCOTP_REG_RD(0x17) & FUSE_SDMMC_DLL_OVERRIDE_ENABLE_MASK) >> FUSE_SDMMC_DLL_OVERRIDE_ENABLE_SHIFT) 638 | 639 | /* DLL delay */ 640 | #define FUSE_SDMMC_DLL_DLY_SHIFT ((uint8_t)8) 641 | #define FUSE_SDMMC_DLL_DLY_MASK ((uint32_t)(0x7Fu << FUSE_SDMMC_DLL_DLY_SHIFT)) 642 | #define FUSE_SDMMC_DLL_DLY_VALUE ((HW_OCOTP_REG_RD(0x19) & FUSE_SDMMC_DLL_DLY_MASK) >> FUSE_SDMMC_DLL_DLY_SHIFT) 643 | 644 | /* SD/MMC Index */ 645 | #define FUSE_SDMMC_PORT_SEL_SHIFT ((uint8_t)1) 646 | #define FUSE_SDMMC_PORT_SEL_MASK ((uint32_t)(0x1 << FUSE_SDMMC_PORT_SEL_SHIFT)) 647 | #define FUSE_SDMMC_PORT_SEL_VALUE ((SRC->SBMR1 & FUSE_SDMMC_PORT_SEL_MASK) >> FUSE_SDMMC_PORT_SEL_SHIFT) 648 | 649 | /* SD/MMC instance 1 reset polarity */ 650 | #define FUSE_SD1_RST_ACTIVE_POLARITY_SHIFT ((uint8_t)2) 651 | #define FUSE_SD1_RST_ACTIVE_POLARITY_MASK ((uint32_t)(0x1 << FUSE_SD1_RST_ACTIVE_POLARITY_SHIFT)) 652 | #define FUSE_SD1_RST_ACTIVE_POLARITY_VALUE \ 653 | ((HW_OCOTP_REG_RD(0x17) & FUSE_SD1_RST_ACTIVE_POLARITY_MASK) >> FUSE_SD1_RST_ACTIVE_POLARITY_SHIFT) 654 | 655 | /* SD/MMC instance 2 reset polarity */ 656 | #define FUSE_SD2_RST_ACTIVE_POLARITY_SHIFT ((uint8_t)1) 657 | #define FUSE_SD2_RST_ACTIVE_POLARITY_MASK ((uint32_t)(0x1 << FUSE_SD2_RST_ACTIVE_POLARITY_SHIFT)) 658 | #define FUSE_SD2_RST_ACTIVE_POLARITY_VALUE \ 659 | ((HW_OCOTP_REG_RD(0x17) & FUSE_SD2_RST_ACTIVE_POLARITY_MASK) >> FUSE_SD2_RST_ACTIVE_POLARITY_SHIFT) 660 | 661 | /* USDHC IOMUX SION Enable */ 662 | #define FUSE_USDHC_IOMUX_SION_ENABLE_SHIFT ((uint8_t)4) 663 | #define FUSE_USDHC_IOMUX_SION_ENABLE_MASK ((uint32_t)(0x1 << FUSE_USDHC_IOMUX_SION_ENABLE_SHIFT)) 664 | #define FUSE_USDHC_IOMUX_SION_ENABLE_VALUE \ 665 | ((HW_OCOTP_REG_RD(0x17) & FUSE_USDHC_IOMUX_SION_ENABLE_MASK) >> FUSE_USDHC_IOMUX_SION_ENABLE_SHIFT) 666 | 667 | /* Disable SDMMC Manufacture Mode */ 668 | #define FUSE_SDMMC_MFG_DISABLE_SHIFT ((uint8_t)15) 669 | #define FUSE_SDMMC_MFG_DISABLE_MASK ((uint32_t)(0x1 << FUSE_SDMMC_MFG_DISABLE_SHIFT)) 670 | #define FUSE_SDMMC_MFG_DISABLE_VALUE \ 671 | ((HW_OCOTP_REG_RD(0x17) & FUSE_SDMMC_MFG_DISABLE_MASK) >> FUSE_SDMMC_MFG_DISABLE_SHIFT) 672 | 673 | /* ========================== MMC/SD boot(MMC Part)======================================= */ 674 | /* MMC Speed */ 675 | #define FUSE_MMC_SPEED_SHIFT ((uint8_t)5) 676 | #define FUSE_MMC_SPEED_MASK ((uint32_t)(0x1 << FUSE_MMC_SPEED_SHIFT)) 677 | #define FUSE_MMC_SPEED_VALUE ((SRC->SBMR1 & FUSE_MMC_SPEED_MASK) >> FUSE_MMC_SPEED_SHIFT) 678 | 679 | /* MMC/eMMC Fast_Boot_ACK_Disable */ 680 | #define FUSE_MMC_FAST_BOOT_ACK_SHIFT ((uint8_t)4) 681 | #define FUSE_MMC_FAST_BOOT_ACK_MASK ((uint32_t)(0x1 << FUSE_MMC_FAST_BOOT_ACK_SHIFT)) 682 | #define FUSE_MMC_FAST_BOOT_ACK_VALUE ((SRC->SBMR1 & FUSE_MMC_FAST_BOOT_ACK_MASK) >> FUSE_MMC_FAST_BOOT_ACK_SHIFT) 683 | 684 | /* MMC Bus_Width */ 685 | #define FUSE_MMC_BUS_WIDTH_SHIFT ((uint8_t)9) 686 | #define FUSE_MMC_BUS_WIDTH_MASK ((uint32_t)(0x3 << FUSE_MMC_BUS_WIDTH_SHIFT)) 687 | #define FUSE_MMC_BUS_WIDTH_VALUE ((SRC->SBMR1 & FUSE_MMC_BUS_WIDTH_MASK) >> FUSE_MMC_BUS_WIDTH_SHIFT) 688 | 689 | /* eMMC fast boot pre-idle reset mode fuse*/ 690 | #define FUSE_EMMC_RESET_PREIDLE_STATE_SHIFT ((uint8_t)0) 691 | #define FUSE_EMMC_RESET_PREIDLE_STATE_MASK ((uint32_t)(0x1 << FUSE_EMMC_RESET_PREIDLE_STATE_SHIFT)) 692 | #define FUSE_EMMC_RESET_PREIDLE_STATE() \ 693 | ((HW_OCOTP_REG_RD(0x17) & FUSE_EMMC_RESET_PREIDLE_STATE_MASK) >> FUSE_EMMC_RESET_PREIDLE_STATE_SHIFT) 694 | 695 | /* ========================== MMC/SD boot(SD Part)======================================= */ 696 | /* SD Speed */ 697 | #define FUSE_SD_SPEED_SHIFT ((uint8_t)4) 698 | #define FUSE_SD_SPEED_MASK ((uint32_t)(0x3 << FUSE_SD_SPEED_SHIFT)) 699 | #define FUSE_SD_SPEED_VALUE ((SRC->SBMR1 & FUSE_SD_SPEED_MASK) >> FUSE_SD_SPEED_SHIFT) 700 | 701 | /* SD_Calibration Step */ 702 | #define FUSE_SD_CAL_STEP_SHIFT ((uint8_t)8) 703 | #define FUSE_SD_CAL_STEP_MASK ((uint32_t)(0x3 << FUSE_SD_CAL_STEP_SHIFT)) 704 | #define FUSE_SD_CAL_STEP_VALUE ((HW_OCOTP_REG_RD(0x17) & FUSE_SD_CAL_STEP_MASK) >> FUSE_SD_CAL_STEP_SHIFT) 705 | 706 | /* SD BUS_Width */ 707 | #define FUSE_SD_BUS_WIDTH_SHIFT ((uint8_t)9) 708 | #define FUSE_SD_BUS_WIDTH_MASK ((uint32_t)(0x1 << FUSE_SD_BUS_WIDTH_SHIFT)) 709 | #define FUSE_SD_BUS_WIDTH_VALUE ((SRC->SBMR1 & FUSE_SD_BUS_WIDTH_MASK) >> FUSE_SD_BUS_WIDTH_SHIFT) 710 | 711 | /* ========================== Misc. Configuration ======================================= */ 712 | /* Force_Boot_from_fuse */ 713 | #define FUSE_FORCE_COLD_BOOT_SHIFT ((uint8_t)5) 714 | #define FUSE_FORCE_COLD_BOOT_MASK (1u << FUSE_FORCE_COLD_BOOT_SHIFT) 715 | #define FUSE_FORCE_COLD_BOOT_VALUE ((HW_OCOTP_REG_RD(0x16) & FUSE_FORCE_COLD_BOOT_MASK) >> FUSE_FORCE_COLD_BOOT_SHIFT) 716 | 717 | /* Force Boot from Fuse fuse */ 718 | #define FUSE_FORCE_INTERNAL_BOOT_SHIFT ((uint8_t)14) 719 | #define FUSE_FORCE_INTERNAL_BOOT_MASK (1u << FUSE_FORCE_INTERNAL_BOOT_SHIFT) 720 | #define FUSE_FORCE_INTERNAL_BOOT_VALUE \ 721 | ((HW_OCOTP_REG_RD(0x1A) & FUSE_FORCE_INTERNAL_BOOT_MASK) >> FUSE_FORCE_INTERNAL_BOOT_SHIFT) 722 | 723 | /* SDP_ENABLE fuse */ 724 | #define FUSE_SDP_DISABLE_SHIFT ((uint8_t)0) 725 | #define FUSE_SDP_DISABLE_MASK (1U << FUSE_SDP_DISABLE_SHIFT) 726 | #define FUSE_SDP_DISABLE_VALUE ((HW_OCOTP_REG_RD(0x1A) & FUSE_SDP_DISABLE_MASK) >> FUSE_SDP_DISABLE_SHIFT) 727 | 728 | /* WDOG enable fuse */ 729 | #define FUSE_WDOG_ENABLE_SHIFT ((uint8_t)15) 730 | #define FUSE_WDOG_ENABLE_MASK (1u << FUSE_WDOG_ENABLE_SHIFT) 731 | #define FUSE_WDOG_ENABLE_VALUE ((HW_OCOTP_REG_RD(0x1a) & FUSE_WDOG_ENABLE_MASK) >> FUSE_WDOG_ENABLE_SHIFT) 732 | 733 | /* WDOG Timeout selection */ 734 | #define FUSE_WDOG_TIMEOUT_SEL_SHIFT (0u) 735 | #define FUSE_WDOG_TIMEOUT_SEL_MASK (0x7ul << FUSE_WDOG_TIMEOUT_SEL_SHIFT) 736 | #define FUSE_WDOG_TIMEOUT_SEL_VAL ((HW_OCOTP_REG_RD(0x1b) & FUSE_WDOG_TIMEOUT_SEL_MASK) >> FUSE_WDOG_TIMEOUT_SEL_SHIFT) 737 | 738 | /* WDOG Reset Pin Selection */ 739 | #define FUSE_WDOG_RESET_PIN_SEL_SHIFT (3) 740 | #define FUSE_WDOG_RESET_PIN_SEL_MASK (0x3u << FUSE_WDOG_RESET_PIN_SEL_SHIFT) 741 | #define FUSE_WDOG_RESET_PIN_SEL_VAL \ 742 | ((HW_OCOTP_REG_RD(0x1b) & FUSE_WDOG_RESET_PIN_SEL_MASK) >> FUSE_WDOG_RESET_PIN_SEL_SHIFT) 743 | 744 | /* WDOG Pin Enabled */ 745 | #define FUSE_WDOG_PIN_EN_SHIFT (5) 746 | #define FUSE_WDOG_PIN_EN_MASK (1u << FUSE_WDOG_PIN_EN_SHIFT) 747 | #define FUSE_WDOG_PIN_EN_VAL ((HW_OCOTP_REG_RD(0x1b) & FUSE_WDOG_PIN_EN_MASK) >> FUSE_WDOG_PIN_EN_SHIFT) 748 | 749 | /* L1 I-Cache DISABLE */ 750 | #define FUSE_ICACHE_DISABLE_SHIFT ((uint8_t)7) 751 | #define FUSE_ICACHE_DISABLE_MASK (1u << FUSE_ICACHE_DISABLE_SHIFT) 752 | #define FUSE_ICACHE_DISABLE_VALUE ((HW_OCOTP_REG_RD(0x1a) & FUSE_ICACHE_DISABLE_MASK) >> FUSE_ICACHE_DISABLE_SHIFT) 753 | 754 | /* L1 D-Cache DISABLE */ 755 | #define FUSE_DCACHE_DISABLE_SHIFT ((uint8_t)6) 756 | #define FUSE_DCACHE_DISABLE_MASK (1u << FUSE_DCACHE_DISABLE_SHIFT) 757 | #define FUSE_DCACHE_DISABLE_VALUE ((HW_OCOTP_REG_RD(0x1a) & FUSE_DCACHE_DISABLE_MASK) >> FUSE_DCACHE_DISABLE_SHIFT) 758 | 759 | /* UART Serial Download DISABLE */ 760 | #define FUSE_UART_SERIAL_DOWNLOAD_DISABLE_SHIFT ((uint8_t)1) 761 | #define FUSE_UART_SERIAL_DOWNLOAD_DISABLE_MASK (1u << FUSE_UART_SERIAL_DOWNLOAD_DISABLE_SHIFT) 762 | #define FUSE_UART_SERIAL_DOWNLOAD_DISABLE_VALUE \ 763 | ((HW_OCOTP_REG_RD(0x1a) & FUSE_UART_SERIAL_DOWNLOAD_DISABLE_MASK) >> FUSE_UART_SERIAL_DOWNLOAD_DISABLE_SHIFT) 764 | 765 | /* FLEXRAM PART */ 766 | #define FUSE_FLEXRAM_CFG_SHIFT ((uint8_t)16) 767 | #define FUSE_FLEXRAM_CFG_MASK (0x3fu << FUSE_FLEXRAM_CFG_SHIFT) 768 | #define FUSE_FLEXRAM_CFG_VALUE ((HW_OCOTP_REG_RD(0x47) & FUSE_FLEXRAM_CFG_MASK) >> FUSE_FLEXRAM_CFG_SHIFT) 769 | 770 | /* ========================== USB Configuration ======================================= */ 771 | #define FUSE_USB_VID_SHIFT (0u) 772 | #define FUSE_USB_VID_MASK (0xFFFFu << FUSE_USB_VID_SHIFT) 773 | #define FUSE_USB_VID_VAL ((HW_OCOTP_REG_RD(0x2E) & FUSE_USB_VID_MASK) >> FUSE_USB_VID_SHIFT) 774 | 775 | #define FUSE_USB_PID_SHIFT (16u) 776 | #define FUSE_USB_PID_MASK (0xFFFFu << FUSE_USB_PID_SHIFT) 777 | #define FUSE_USB_PID_VAL ((HW_OCOTP_REG_RD(0x2E) & FUSE_USB_PID_MASK) >> FUSE_USB_PID_SHIFT) 778 | 779 | /* Disable USB SDP */ 780 | #define FUSE_USB_SDP_DISABLE_SHIFT ((uint8_t)11) 781 | #define FUSE_USB_SDP_DISABLE_MASK ((uint32_t)(0x1 << FUSE_USB_SDP_DISABLE_SHIFT)) 782 | #define FUSE_USB_SDP_DISABLE_VALUE ((HW_OCOTP_REG_RD(0x17) & FUSE_USB_SDP_DISABLE_MASK) >> FUSE_USB_SDP_DISABLE_SHIFT) 783 | 784 | /* ========================== MISC. Configuration ======================================= */ 785 | #define FUSE_OSC_4_16M_TRIM_EN_SHIFT (21) 786 | #define FUSE_OSC_4_16M_TRIM_EN_MASK (1u << FUSE_OSC_4_16M_TRIM_EN_SHIFT) 787 | #define FUSE_OSC_4_16M_TRIM_EN_VAL \ 788 | ((HW_OCOTP_REG_RD(0x21) & FUSE_OSC_4_16M_TRIM_EN_MASK) >> FUSE_OSC_4_16M_TRIM_EN_SHIFT) 789 | 790 | #define FUSE_TCM_ECC_ENABLE_SHIFT (15) 791 | #define FUSE_TCM_ECC_ENABLE_MASK (1u << FUSE_TCM_ECC_ENABLE_SHIFT) 792 | #define FUSE_TCM_ECC_ENABLE_VALUE ((HW_OCOTP_REG_RD(0x4) & FUSE_TCM_ECC_ENABLE_MASK) >> FUSE_TCM_ECC_ENABLE_SHIFT) 793 | 794 | /* XECC Enable */ 795 | #define FUSE_XECC_ENABLE_SHIFT (3) 796 | #define FUSE_XECC_ENABLE_MASK (1u << FUSE_XECC_ENABLE_SHIFT) 797 | #define FUSE_XECC_ENABLE_VALUE ((HW_OCOTP_REG_RD(0x4) & FUSE_XECC_ENABLE_MASK) >> FUSE_XECC_ENABLE_SHIFT) 798 | 799 | /* MECC Enable */ 800 | #define FUSE_MECC_ENABLE_SHIFT (2) 801 | #define FUSE_MECC_ENABLE_MASK (1u << FUSE_MECC_ENABLE_SHIFT) 802 | #define FUSE_MECC_ENABLE_VALUE ((HW_OCOTP_REG_RD(0x4) & FUSE_MECC_ENABLE_MASK) >> FUSE_MECC_ENABLE_SHIFT) 803 | 804 | #define FUSE_ROM_ECC_PRELOAD_POR_SHIFT (0) 805 | #define FUSE_ROM_ECC_PRELOAD_POR_MASK (1u << FUSE_ROM_ECC_PRELOAD_POR_SHIFT) 806 | #define FUSE_ROM_ECC_PRELOAD_POR_VALUE \ 807 | ((HW_OCOTP_REG_RD(0x15) & FUSE_ROM_ECC_PRELOAD_POR_MASK) >> FUSE_ROM_ECC_PRELOAD_POR_SHIFT) 808 | 809 | /* ========================== Device Sepefic Configuration ======================================= */ 810 | #define FUSE_DEVICE_UUID_WORD0_SHIFT (0u) 811 | #define FUSE_DEVICE_UUID_WORD0_MASK (0xFFFFFFFFu << FUSE_DEVICE_UUID_WORD0_SHIFT) 812 | #define FUSE_DEVICE_UUID_WORD0_VAL \ 813 | ((HW_OCOTP_REG_RD(0x10) & FUSE_DEVICE_UUID_WORD0_MASK) >> FUSE_DEVICE_UUID_WORD0_SHIFT) 814 | 815 | #define FUSE_DEVICE_UUID_WORD1_SHIFT (0u) 816 | #define FUSE_DEVICE_UUID_WORD1_MASK (0xFFFFFFFFu << FUSE_DEVICE_UUID_WORD1_SHIFT) 817 | #define FUSE_DEVICE_UUID_WORD1_VAL \ 818 | ((HW_OCOTP_REG_RD(0x11) & FUSE_DEVICE_UUID_WORD1_MASK) >> FUSE_DEVICE_UUID_WORD1_SHIFT) 819 | 820 | /* =========================== Analog Trime related definitions ================================== */ 821 | #define FUSE_TEMPSNS_TRIM_EN_SHIFT (4) 822 | #define FUSE_TEMPSNS_TRIM_EN_MASK (1u << FUSE_TEMPSNS_TRIM_EN_SHIFT) 823 | #define FUSE_TEMPSNS_TRIM_EN_VALUE ((HW_OCOTP_REG_RD(0x22) & FUSE_TEMPSNS_TRIM_EN_MASK) >> FUSE_TEMPSNS_TRIM_EN_SHIFT) 824 | 825 | #define FUSE_TEMPSNS_IBIAS_TRIM_SHIFT (0) 826 | #define FUSE_TEMPSNS_IBIAS_TRIM_MASK (0xfu << FUSE_TEMPSNS_IBIAS_TRIM_SHIFT) 827 | #define FUSE_TEMPSNS_IBIAS_TRIM_VALUE \ 828 | ((HW_OCOTP_REG_RD(0x22) & FUSE_TEMPSNS_IBIAS_TRIM_MASK) >> FUSE_TEMPSNS_IBIAS_TRIM_SHIFT) 829 | 830 | #define FUSE_TEMPSNS_SLOPE_CAL_SHIFT (8) 831 | #define FUSE_TEMPSNS_SLOPE_CAL_MASK (0x3Fu << FUSE_TEMPSNS_SLOPE_CAL_SHIFT) 832 | #define FUSE_TEMPSNS_SLOPE_CAL_VALUE \ 833 | ((HW_OCOTP_REG_RD(0x22) & FUSE_TEMPSNS_SLOPE_CAL_MASK) >> FUSE_TEMPSNS_SLOPE_CAL_SHIFT) 834 | 835 | #define FUSE_VMBG_REFTOP_VBGADJ_SHIFT (5) 836 | #define FUSE_VMBG_REFTOP_VBGADJ_MASK (0x7u << FUSE_VMBG_REFTOP_VBGADJ_SHIFT) 837 | #define FUSE_VMBG_REFTOP_VBGADJ_VALUE \ 838 | ((HW_OCOTP_REG_RD(0x1D) & FUSE_VMBG_REFTOP_VBGADJ_MASK) >> FUSE_VMBG_REFTOP_VBGADJ_SHIFT) 839 | 840 | #define FUSE_VMBG_REFTOP_IBZTCADJ_SHIFT (2) 841 | #define FUSE_VMBG_REFTOP_IBZTCADJ_MASK (0x7u << FUSE_VMBG_REFTOP_IBZTCADJ_SHIFT) 842 | #define FUSE_VMBG_REFTOP_IBZTCADJ_VALUE \ 843 | ((HW_OCOTP_REG_RD(0x1D) & FUSE_VMBG_REFTOP_IBZTCADJ_MASK) >> FUSE_VMBG_REFTOP_IBZTCADJ_SHIFT) 844 | 845 | #define FUSE_DCDC_TRIM_EN_SHIFT (7) 846 | #define FUSE_DCDC_TRIM_EN_MASK (1u << FUSE_DCDC_TRIM_EN_SHIFT) 847 | #define FUSE_DCDC_TRIM_EN_VALUE ((HW_OCOTP_REG_RD(0x1D) & FUSE_DCDC_TRIM_EN_MASK) >> FUSE_DCDC_TRIM_EN_SHIFT) 848 | 849 | #define FUSE_USBPHY1_TRIM_EN_SHIFT (30u) 850 | #define FUSE_USBPHY1_TRIM_EN_MASK (1u << FUSE_USBPHY1_TRIM_EN_SHIFT) 851 | #define FUSE_USBPHY1_TRIM_EN_VALUE ((HW_OCOTP_REG_RD(0x22) & FUSE_USBPHY1_TRIM_EN_MASK) >> FUSE_USBPHY1_TRIM_EN_SHIFT) 852 | 853 | #define FUSE_USBPHY2_TRIM_EN_SHIFT (31u) 854 | #define FUSE_USBPHY2_TRIM_EN_MASK (1u << FUSE_USBPHY2_TRIM_EN_SHIFT) 855 | #define FUSE_USBPHY2_TRIM_EN_VALUE ((HW_OCOTP_REG_RD(0x22) & FUSE_USBPHY2_TRIM_EN_MASK) >> FUSE_USBPHY2_TRIM_EN_SHIFT) 856 | 857 | #define FUSE_XMC_CHK_CRC_VALUE (HW_OCOTP_REG_RD(0x49)) 858 | 859 | #define FUSE_SECURE_COPY_EN_SHIFT (13u) 860 | #define FUSE_SECURE_COPY_EN_MASK (1ul << FUSE_SECURE_COPY_EN_SHIFT) 861 | #define FUSE_SECURE_COPY_EN_VALUE ((HW_OCOTP_REG_RD(0x1a) & FUSE_SECURE_COPY_EN_MASK) >> FUSE_SECURE_COPY_EN_SHIFT) 862 | 863 | #define FUSE_CDOG_TIMEOUT_SHIFT (29) 864 | #define FUSE_CDOG_TIMEOUT_MASK (7u << FUSE_CDOG_TIMEOUT_SHIFT) 865 | #define FUSE_CDOG_TIMEOUT_VALUE ((HW_OCOTP_REG_RD(0x47) & FUSE_CDOG_TIMEOUT_MASK) >> FUSE_CDOG_TIMEOUT_SHIFT) 866 | 867 | #define FUSE_CDOG_ENABLE_SHIFT (3) 868 | #define FUSE_CDOG_ENABLE_MAST (1u << FUSE_CDOG_ENABLE_SHIFT) 869 | #define FUSE_CDOG_ENABLE_VALUE ((HW_OCOTP_REG_RD(0x7) & FUSE_CDOG_ENABLE_MAST) >> FUSE_CDOG_ENABLE_SHIFT) 870 | 871 | #endif /* __FUSEMAP_H__*/ 872 | -------------------------------------------------------------------------------- /bsp/imxrt1170_a0/flash_drv/peripherals_pinmux.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 NXP 3 | * 4 | * All rights reserved. 5 | * 6 | * SPDX-License-Identifier: BSD-3-Clause 7 | */ 8 | 9 | #include "fsl_device_registers.h" 10 | 11 | //////////////////////////////////////////////////////////////////////////////// 12 | // Definitions 13 | //////////////////////////////////////////////////////////////////////////////// 14 | 15 | /*====================== LPUART IOMUXC Definitions ===========================*/ 16 | //! peripheral enable configurations 17 | #define BL_ENABLE_PINMUX_UART1 (BL_CONFIG_LPUART_1) 18 | 19 | #define UART1_RX_IOMUXC_MUX_FUNC IOMUXC_GPIO_AD_25_LPUART1_RXD 20 | #define UART1_RX_IOMUXC_MUX_GPIO IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 21 | #define UART1_RX_IOMUXC_MUX_CM4_GPIO IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 22 | #define UART1_RX_IOMUXC_PAD_DEFAULT 0x00000002 23 | #define UART1_RX_GPIO_BASE GPIO3 24 | #define UART1_RX_GPIO_CM4_BASE GPIO3 25 | #define UART1_RX_GPIO_PIN_NUM 24 // GPIO_AD_25/GPIO3[24] 26 | #define UART1_RX_GPIO_IRQn GPIO3_Combined_16_31_IRQn 27 | #define UART1_RX_GPIO_IRQHandler GPIO3_Combined_16_31_IRQHandler 28 | 29 | #define UART1_TX_IOMUXC_MUX_FUNC IOMUXC_GPIO_AD_24_LPUART1_TXD 30 | #define UART1_TX_IOMUXC_PAD_DEFAULT 0x00000002 31 | #define UART1_TX_GPIO_PIN_NUM 23 // GPIO_AD_24/GPIO3[23] 32 | 33 | #define LPUART1_PAD_CTRL (IOMUXC_SW_PAD_CTL_PAD_DSE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(1) | IOMUXC_SW_PAD_CTL_PAD_PUS(1)) 34 | #define UART1_PULLUP_PAD_CTRL (IOMUXC_SW_PAD_CTL_PAD_PUE(1) | IOMUXC_SW_PAD_CTL_PAD_PUS(1)) 35 | #define UART1_PULLUP_DISABLE_PAD_CTRL (IOMUXC_SW_PAD_CTL_PAD_PUE(1)) 36 | 37 | /*====================== SDIO SLAVE IOMUXC Definitions ===========================*/ 38 | #define BL_ENABLE_PINMUX_SDIO_SLAVE0 (BL_CONFIG_SDIO_SLAVE_0) 39 | 40 | #define SDIO0_CMD_IOMUXC_MUX_FUNC IOMUXC_GPIO_SD_B1_00_SDIO_CMD 41 | #define SDIO0_CMD_IOMUXC_PAD_DEFAULT 0x00000008 42 | #define SDIO0_CLK_IOMUXC_MUX_FUNC IOMUXC_GPIO_SD_B1_01_SDIO_CLK 43 | #define SDIO0_CLK_IOMUXC_PAD_DEFAULT 0x00000008 44 | #define SDIO0_DATA0_IOMUXC_MUX_FUNC IOMUXC_GPIO_SD_B1_02_SDIO_DATA0 45 | #define SDIO0_DATA0_IOMUXC_PAD_DEFAULT 0x00000008 46 | #define SDIO0_DATA1_IOMUXC_MUX_FUNC IOMUXC_GPIO_SD_B1_03_SDIO_DATA1 47 | #define SDIO0_DATA1_IOMUXC_PAD_DEFAULT 0x00000008 48 | #define SDIO0_DATA2_IOMUXC_MUX_FUNC IOMUXC_GPIO_SD_B1_04_SDIO_DATA2 49 | #define SDIO0_DATA2_IOMUXC_PAD_DEFAULT 0x00000008 50 | #define SDIO0_DATA3_IOMUXC_MUX_FUNC IOMUXC_GPIO_SD_B1_05_SDIO_DATA3 51 | #define SDIO0_DATA3_IOMUXC_PAD_DEFAULT 0x00000008 52 | 53 | /*====================== SAI IOMUXC Definitions ===========================*/ 54 | #define BL_ENABLE_PINMUX_SAI1 (BL_CONFIG_SAI_1) 55 | #define SAI1_MCLK_IOMUXC_MUX_FUNC IOMUXC_GPIO_AD_17_SAI1_MCLK 56 | #define SAI1_RX_SYNC_IOMUXC_MUX_FUNC IOMUXC_GPIO_AD_18_SAI1_RX_SYNC 57 | #define SAI1_RX_BCLK_IOMUXC_MUX_FUNC IOMUXC_GPIO_AD_19_SAI1_RX_BCLK 58 | #define SAI1_RX_DATA00_IOMUXC_MUX_FUNC IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 59 | #define SAI1_TX_DATA00_IOMUXC_MUX_FUNC IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 60 | #define SAI1_TX_BCLK_IOMUXC_MUX_FUNC IOMUXC_GPIO_AD_22_SAI1_TX_BCLK 61 | #define SAI1_TX_SYNC_IOMUXC_MUX_FUNC IOMUXC_GPIO_AD_23_SAI1_TX_SYNC 62 | #define SAI1_MCLK_IOMUXC_FUNC_PAD_DEFAULT 0x00000006 63 | #define SAI1_RX_SYNC_IOMUX_PAD_DEFAULT 0x0000000e 64 | #define SAI1_RX_BCLK_IOMUX_PAD_DEFAULT 0x00000006 65 | #define SAI1_RX_DATA00_IOMUX_PAD_DEFAULT 0x00000006 66 | #define SAI1_TX_DATA00_IOMUX_PAD_DEFAULT 0x00000006 67 | #define SAI1_TX_BCLK_IOMUX_PAD_DEFAULT 0x00000006 68 | #define SAI1_TX_SYNC_IOMUX_PAD_DEFAULT 0x00000006 69 | 70 | /*====================== LPSPI IOMUXC Definitions ===========================*/ 71 | /* LPSPI1 PINMUX Info */ 72 | #define SW_MUX_CTL_PAD_LPSPI1_PCS0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 73 | #define SW_MUX_CTL_PAD_LPSPI1_SCK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 74 | #define SW_MUX_CTL_PAD_LPSPI1_SIN_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 75 | #define SW_MUX_CTL_PAD_LPSPI1_SOUT_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 76 | 77 | #define SW_PAD_CTL_PAD_LPSPI1_PCS0_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 78 | #define SW_PAD_CTL_PAD_LPSPI1_SCK_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 79 | #define SW_PAD_CTL_PAD_LPSPI1_SIN_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 80 | #define SW_PAD_CTL_PAD_LPSPI1_SOUT_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 81 | 82 | #define SELECT_INPUT_LPSPI1_SDI_IDX kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT 83 | 84 | #define LPSPI1_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(0) 85 | #define GPIO_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(5) 86 | #define LPSPI1_PCS_GPIO GPIO3 87 | #define LPSPI1_PCS_GPIO_NUM 28 88 | 89 | /* LPSPI2 PINMUX Info */ 90 | #define SW_MUX_CTL_PAD_LPSPI2_PCS0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 91 | #define SW_MUX_CTL_PAD_LPSPI2_SCK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 92 | #define SW_MUX_CTL_PAD_LPSPI2_SIN_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 93 | #define SW_MUX_CTL_PAD_LPSPI2_SOUT_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 94 | 95 | #define SW_PAD_CTL_PAD_LPSPI2_PCS0_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 96 | #define SW_PAD_CTL_PAD_LPSPI2_SCK_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 97 | #define SW_PAD_CTL_PAD_LPSPI2_SIN_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 98 | #define SW_PAD_CTL_PAD_LPSPI2_SOUT_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 99 | 100 | #define SELECT_INPUT_LPSPI2_SDI_IDX kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT 101 | 102 | #define LPSPI2_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(6) 103 | #define LPSPI2_PCS_GPIO GPIO4 104 | #define LPSPI2_PCS_GPIO_NUM 17 105 | 106 | /* LPSPI3 PINMUX Info */ 107 | #define SW_MUX_CTL_PAD_LPSPI3_PCS0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 108 | #define SW_MUX_CTL_PAD_LPSPI3_SCK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 109 | #define SW_MUX_CTL_PAD_LPSPI3_SIN_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 110 | #define SW_MUX_CTL_PAD_LPSPI3_SOUT_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 111 | 112 | #define SW_PAD_CTL_PAD_LPSPI3_PCS0_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 113 | #define SW_PAD_CTL_PAD_LPSPI3_SCK_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 114 | #define SW_PAD_CTL_PAD_LPSPI3_SIN_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 115 | #define SW_PAD_CTL_PAD_LPSPI3_SOUT_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 116 | 117 | #define SELECT_INPUT_LPSPI3_SDI_IDX kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT 118 | 119 | #define LPSPI3_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(9) 120 | #define LPSPI3_PCS_GPIO GPIO4 121 | #define LPSPI3_PCS_GPIO_NUM 28 122 | 123 | /* LPSPI4 PINMUX Info */ 124 | #define SW_MUX_CTL_PAD_LPSPI4_PCS0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 125 | #define SW_MUX_CTL_PAD_LPSPI4_SCK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 126 | #define SW_MUX_CTL_PAD_LPSPI4_SIN_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 127 | #define SW_MUX_CTL_PAD_LPSPI4_SOUT_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 128 | 129 | #define SW_PAD_CTL_PAD_LPSPI4_PCS0_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 130 | #define SW_PAD_CTL_PAD_LPSPI4_SCK_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 131 | #define SW_PAD_CTL_PAD_LPSPI4_SIN_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 132 | #define SW_PAD_CTL_PAD_LPSPI4_SOUT_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 133 | 134 | #define SELECT_INPUT_LPSPI4_SDI_IDX kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT 135 | 136 | #define LPSPI4_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(9) 137 | #define LPSPI4_PCS_GPIO GPIO5 138 | #define LPSPI4_PCS_GPIO_NUM 16 139 | 140 | // Fast Slew rate 141 | // High Drive 142 | #define LPSPI1_SW_PAD_CTL_VAL \ 143 | (IOMUXC_SW_PAD_CTL_PAD_SRE(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(0) | \ 144 | IOMUXC_SW_PAD_CTL_PAD_PUS(1)) 145 | #define LPSPI2_SW_PAD_CTL_VAL (IOMUXC_SW_PAD_CTL_PAD_PDRV(0) | IOMUXC_SW_PAD_CTL_PAD_PULL(3)) 146 | #define LPSPI3_SW_PAD_CTL_VAL (IOMUXC_SW_PAD_CTL_PAD_PDRV(0) | IOMUXC_SW_PAD_CTL_PAD_PULL(3)) 147 | #define LPSPI4_SW_PAD_CTL_VAL (IOMUXC_SW_PAD_CTL_PAD_PDRV(0) | IOMUXC_SW_PAD_CTL_PAD_PULL(3)) 148 | // Fast Slew rate 149 | // High Drive 150 | #define GPIO_SW_PAD_CTL_VAL (IOMUXC_SW_PAD_CTL_PAD_SRE(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(1)) 151 | 152 | #define LPSPI1_SDI_SELECT_INPUT_VAL IOMUXC_SELECT_INPUT_DAISY(1) // SELECT_GPIO_AD_31_ALT0 153 | #define LPSPI2_SDI_SELECT_INPUT_VAL IOMUXC_SELECT_INPUT_DAISY(1) // SELECT_GPIO_SD_B2_07_ALT6 154 | #define LPSPI3_SDI_SELECT_INPUT_VAL IOMUXC_SELECT_INPUT_DAISY(1) // SELECT_GPIO_DISP_B1_05_ALT9 155 | #define LPSPI4_SDI_SELECT_INPUT_VAL IOMUXC_SELECT_INPUT_DAISY(1) // SELECT_GPIO_DISP_B2_13_ALT9 156 | 157 | /*====================== FLEXSPI1 IOMUXC Definitions ===========================*/ 158 | #define SW_MUX_CTL_PAD_FLEXSPI1B_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 159 | #define SW_MUX_CTL_PAD_FLEXSPI1B_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 160 | #define SW_MUX_CTL_PAD_FLEXSPI1B_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 161 | #define SW_MUX_CTL_PAD_FLEXSPI1B_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 162 | #define SW_MUX_CTL_PAD_FLEXSPI1B_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 163 | #define SW_MUX_CTL_PAD_FLEXSPI1B_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 164 | #define SW_MUX_CTL_PAD_FLEXSPI1B_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 165 | #define SW_MUX_CTL_PAD_FLEXSPI1B_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 166 | 167 | #define SW_MUX_CTL_PAD_FLEXSPI1A_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 168 | #define SW_MUX_CTL_PAD_FLEXSPI1A_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 169 | #define SW_MUX_CTL_PAD_FLEXSPI1A_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 170 | #define SW_MUX_CTL_PAD_FLEXSPI1A_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 171 | #define SW_MUX_CTL_PAD_FLEXSPI1A_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 172 | #define SW_MUX_CTL_PAD_FLEXSPI1A_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 173 | #define SW_MUX_CTL_PAD_FLEXSPI1A_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 174 | #define SW_MUX_CTL_PAD_FLEXSPI1A_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 175 | #define SW_MUX_CTL_PAD_FLEXSPI1A_SCLK_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 176 | 177 | #define SW_PAD_CTL_PAD_FLEXSPI1B_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 178 | #define SW_PAD_CTL_PAD_FLEXSPI1B_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 179 | #define SW_PAD_CTL_PAD_FLEXSPI1B_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 180 | #define SW_PAD_CTL_PAD_FLEXSPI1B_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 181 | #define SW_PAD_CTL_PAD_FLEXSPI1B_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 182 | #define SW_PAD_CTL_PAD_FLEXSPI1B_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 183 | #define SW_PAD_CTL_PAD_FLEXSPI1B_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 184 | #define SW_PAD_CTL_PAD_FLEXSPI1B_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 185 | 186 | #define SW_PAD_CTL_PAD_FLEXSPI1A_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 187 | #define SW_PAD_CTL_PAD_FLEXSPI1A_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 188 | #define SW_PAD_CTL_PAD_FLEXSPI1A_SS1_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 189 | #define SW_PAD_CTL_PAD_FLEXSPI1A_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 190 | #define SW_PAD_CTL_PAD_FLEXSPI1A_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 191 | #define SW_PAD_CTL_PAD_FLEXSPI1A_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 192 | #define SW_PAD_CTL_PAD_FLEXSPI1A_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 193 | #define SW_PAD_CTL_PAD_FLEXSPI1A_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 194 | #define SW_PAD_CTL_PAD_FLEXSPI1A_SCLK_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 195 | 196 | #define FLEXSPI1A_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1) 197 | #define FLEXSPI1B_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1) 198 | #define FLEXSPI1A_SS1_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(9) 199 | #define FLEXSPI1B_SS1_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(9) 200 | #define FLEXSPI1B_SS0_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(8) 201 | #define FLEXSPI1B_DQS_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(8) 202 | 203 | // Fast Slew Rate 204 | #define FLEXSPI_SW_PAD_CTL_VAL (IOMUXC_SW_PAD_CTL_PAD_SRE(1)) 205 | 206 | // Pull-down 207 | #define FLEXSPI_DQS_SW_PAD_CTL_VAL (IOMUXC_SW_PAD_CTL_PAD_PULL(2)) 208 | 209 | // Fast Slew Rate 210 | // Drive 211 | // Pulldown 212 | #define FLEXSPI_DQS_SW_PAD_AD_CTL_VAL \ 213 | (IOMUXC_SW_PAD_CTL_PAD_SRE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(1) | IOMUXC_SW_PAD_CTL_PAD_PUS(0)) 214 | 215 | /*====================== FLEXSPI1 Secondary IOMUXC Definitions ===========================*/ 216 | #define SW_MUX_CTL_PAD_FLEXSPI1A_SEC_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 217 | #define SW_MUX_CTL_PAD_FLEXSPI1A_SEC_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 218 | #define SW_MUX_CTL_PAD_FLEXSPI1A_SEC_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 219 | #define SW_MUX_CTL_PAD_FLEXSPI1A_SEC_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 220 | #define SW_MUX_CTL_PAD_FLEXSPI1A_SEC_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 221 | #define SW_MUX_CTL_PAD_FLEXSPI1A_SEC_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 222 | #define SW_MUX_CTL_PAD_FLEXSPI1A_SEC_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 223 | 224 | #define SW_PAD_CTL_PAD_FLEXSPI1A_SEC_SS0_B_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 225 | #define SW_PAD_CTL_PAD_FLEXSPI1A_SEC_SCLK_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 226 | #define SELECT_INPUT_FLEXSPI1A_SEC_SCLK_IDX kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT 227 | #define SW_PAD_CTL_PAD_FLEXSPI1A_SEC_DATA0_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 228 | #define SELECT_INPUT_FLEXSPI1A_SEC_DATA0_IDX kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT 229 | #define SW_PAD_CTL_PAD_FLEXSPI1A_SEC_DATA1_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 230 | #define SELECT_INPUT_FLEXSPI1A_SEC_DATA1_IDX kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT 231 | #define SW_PAD_CTL_PAD_FLEXSPI1A_SEC_DATA2_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 232 | #define SELECT_INPUT_FLEXSPI1A_SEC_DATA2_IDX kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT 233 | #define SW_PAD_CTL_PAD_FLEXSPI1A_SEC_DATA3_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 234 | #define SELECT_INPUT_FLEXSPI1A_SEC_DATA3_IDX kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT 235 | 236 | #define SW_MUX_CTL_PAD_FLEXSPI1B_SEC_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 237 | #define SW_MUX_CTL_PAD_FLEXSPI1B_SEC_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 238 | #define SW_MUX_CTL_PAD_FLEXSPI1B_SEC_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 239 | #define SW_MUX_CTL_PAD_FLEXSPI1B_SEC_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 240 | #define SW_MUX_CTL_PAD_FLEXSPI1B_SEC_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 241 | 242 | #define SW_PAD_CTL_PAD_FLEXSPI1B_SEC_SCLK_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 243 | #define SELECT_INPUT_FLEXSPI1B_SEC_SCLK_IDX kIOMUXC_FLEXSPIB_SCK_SELECT_INPUT 244 | #define SW_PAD_CTL_PAD_FLEXSPI1B_SEC_DATA0_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 245 | #define SELECT_INPUT_FLEXSPI1B_SEC_DATA0_IDX kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT 246 | #define SW_PAD_CTL_PAD_FLEXSPI1B_SEC_DATA1_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 247 | #define SELECT_INPUT_FLEXSPI1B_SEC_DATA1_IDX kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT 248 | #define SW_PAD_CTL_PAD_FLEXSPI1B_SEC_DATA2_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 249 | #define SELECT_INPUT_FLEXSPI1B_SEC_DATA2_IDX kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT 250 | #define SW_PAD_CTL_PAD_FLEXSPI1B_SEC_DATA3_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 251 | #define SELECT_INPUT_FLEXSPI1B_SEC_DATA3_IDX kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT 252 | 253 | #define FLEXSPI1A_SEC_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(3) 254 | 255 | /*====================== FLEXSPI2 IOMUXC Definitions ===========================*/ 256 | #define SW_MUX_CTL_PAD_FLEXSPI2B_DATA7_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 257 | #define SW_MUX_CTL_PAD_FLEXSPI2B_DATA6_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 258 | #define SW_MUX_CTL_PAD_FLEXSPI2B_DATA5_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 259 | #define SW_MUX_CTL_PAD_FLEXSPI2B_DATA4_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 260 | #define SW_MUX_CTL_PAD_FLEXSPI2B_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 261 | #define SW_MUX_CTL_PAD_FLEXSPI2B_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 262 | #define SW_MUX_CTL_PAD_FLEXSPI2B_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 263 | #define SW_MUX_CTL_PAD_FLEXSPI2B_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 264 | #define SW_MUX_CTL_PAD_FLEXSPI2B_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 265 | #define SW_MUX_CTL_PAD_FLEXSPI2B_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 266 | #define SW_MUX_CTL_PAD_FLEXSPI2B_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 267 | 268 | #define SW_MUX_CTL_PAD_FLEXSPI2A_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 269 | #define SW_MUX_CTL_PAD_FLEXSPI2A_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 270 | #define SW_MUX_CTL_PAD_FLEXSPI2A_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 271 | #define SW_MUX_CTL_PAD_FLEXSPI2A_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 272 | #define SW_MUX_CTL_PAD_FLEXSPI2A_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 273 | #define SW_MUX_CTL_PAD_FLEXSPI2A_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 274 | #define SW_MUX_CTL_PAD_FLEXSPI2A_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 275 | #define SW_MUX_CTL_PAD_FLEXSPI2A_DATA4_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 276 | #define SW_MUX_CTL_PAD_FLEXSPI2A_DATA5_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 277 | #define SW_MUX_CTL_PAD_FLEXSPI2A_DATA6_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 278 | #define SW_MUX_CTL_PAD_FLEXSPI2A_DATA7_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 279 | #define SW_MUX_CTL_PAD_FLEXSPI2A_SCLK_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 280 | 281 | #define SW_PAD_CTL_PAD_FLEXSPI2B_DATA7_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 282 | #define SW_PAD_CTL_PAD_FLEXSPI2B_DATA6_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 283 | #define SW_PAD_CTL_PAD_FLEXSPI2B_DATA5_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 284 | #define SW_PAD_CTL_PAD_FLEXSPI2B_DATA4_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 285 | #define SW_PAD_CTL_PAD_FLEXSPI2B_DATA3_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 286 | #define SW_PAD_CTL_PAD_FLEXSPI2B_DATA2_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 287 | #define SW_PAD_CTL_PAD_FLEXSPI2B_DATA1_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 288 | #define SW_PAD_CTL_PAD_FLEXSPI2B_DATA0_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 289 | #define SW_PAD_CTL_PAD_FLEXSPI2B_DQS_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 290 | #define SW_PAD_CTL_PAD_FLEXSPI2B_SS0_B_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 291 | #define SW_PAD_CTL_PAD_FLEXSPI2B_SCLK_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 292 | 293 | #define SW_PAD_CTL_PAD_FLEXSPI2A_SCLK_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 294 | #define SW_PAD_CTL_PAD_FLEXSPI2A_SS0_B_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 295 | #define SW_PAD_CTL_PAD_FLEXSPI2A_DQS_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 296 | #define SW_PAD_CTL_PAD_FLEXSPI2A_DATA0_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 297 | #define SW_PAD_CTL_PAD_FLEXSPI2A_DATA1_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 298 | #define SW_PAD_CTL_PAD_FLEXSPI2A_DATA2_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 299 | #define SW_PAD_CTL_PAD_FLEXSPI2A_DATA3_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 300 | #define SW_PAD_CTL_PAD_FLEXSPI2A_DATA4_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 301 | #define SW_PAD_CTL_PAD_FLEXSPI2A_DATA5_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 302 | #define SW_PAD_CTL_PAD_FLEXSPI2A_DATA6_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 303 | #define SW_PAD_CTL_PAD_FLEXSPI2A_DATA7_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 304 | #define SW_PAD_CTL_PAD_FLEXSPI2A_SCLK_B_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 305 | 306 | #define FLEXSPI2A_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(4) 307 | #define FLEXSPI2B_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(4) 308 | #define FLEXSPI2B_SS0_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(4) 309 | #define FLEXSPI2B_DQS_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(4) 310 | 311 | /*====================== FLEXSPI2 Second IOMUXC Definitions ===========================*/ 312 | #define SW_MUX_CTL_PAD_FLEXSPI2A_SEC_SS0_B_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 313 | #define SW_MUX_CTL_PAD_FLEXSPI2A_SEC_SCLK_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 314 | #define SW_MUX_CTL_PAD_FLEXSPI2A_SEC_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 315 | #define SW_MUX_CTL_PAD_FLEXSPI2A_SEC_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 316 | #define SW_MUX_CTL_PAD_FLEXSPI2A_SEC_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 317 | #define SW_MUX_CTL_PAD_FLEXSPI2A_SEC_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 318 | 319 | #define SW_PAD_CTL_PAD_FLEXSPI2A_SEC_SS0_B_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 320 | #define SW_PAD_CTL_PAD_FLEXSPI2A_SEC_SCLK_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 321 | #define SELECT_INPUT_FLEXSPI2A_SEC_SCLK_IDX kIOMUXC_FLEXSP2A_SCK_SELECT_INPUT 322 | #define SW_PAD_CTL_PAD_FLEXSPI2A_SEC_DATA0_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 323 | #define SELECT_INPUT_FLEXSPI2A_SEC_DATA0_IDX kIOMUXC_FLEXSP2A_DATA0_SELECT_INPUT 324 | #define SW_PAD_CTL_PAD_FLEXSPI2A_SEC_DATA1_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 325 | #define SELECT_INPUT_FLEXSPI2A_SEC_DATA1_IDX kIOMUXC_FLEXSP2A_DATA1_SELECT_INPUT 326 | #define SW_PAD_CTL_PAD_FLEXSPI2A_SEC_DATA2_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 327 | #define SELECT_INPUT_FLEXSPI2A_SEC_DATA2_IDX kIOMUXC_FLEXSPI2A_DATA2_SELECT_INPUT 328 | #define SW_PAD_CTL_PAD_FLEXSPI2A_SEC_DATA3_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 329 | #define SELECT_INPUT_FLEXSPI2A_SEC_DATA3_IDX kIOMUXC_FLEXSPI2A_DATA3_SELECT_INPUT 330 | 331 | /*====================== FLEXSPI Reset IOMUXC Definitions ===========================*/ 332 | #define SW_MUX_CTL_PAD_FLEXSPI_RESET_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 333 | #define SW_PAD_CTL_PAD_FLEXSPI_RESET_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 334 | #define FLEXSPI_RESET_PIN_MUX IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(5) 335 | #define FLEXSPI_RESET_PIN_SW_PAD_CTRL_VAL \ 336 | (IOMUXC_SW_PAD_CTL_PAD_PDRV(0) | IOMUXC_SW_PAD_CTL_PAD_PULL(1) | IOMUXC_SW_PAD_CTL_PAD_ODE(0)) 337 | #define FLEXSPI_RESET_PIN_GPIO GPIO4 338 | #define FLEXSPI_RESET_PIN_INDEX 3 339 | 340 | #define SW_MUX_CTL_PAD_FLEXSPI_SEC_RESET_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 341 | #define SW_PAD_CTL_PAD_FLEXSPI_SEC_RESET_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 342 | #define FLEXSPI_RESET_SEC_PIN_MUX IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(5) 343 | #define FLEXSPI_RESET_SEC_PIN_SW_PAD_CTRL_VAL \ 344 | (IOMUXC_SW_PAD_CTL_PAD_PDRV(0) | IOMUXC_SW_PAD_CTL_PAD_PULL(1) | IOMUXC_SW_PAD_CTL_PAD_ODE(0)) 345 | #define FLEXSPI_RESET_SEC_PIN_GPIO GPIO2 346 | #define FLEXSPI_RESET_SEC_PIN_INDEX 8 347 | 348 | /*====================== SEMC IOMUXC Definitions ===========================*/ 349 | 350 | #define SW_MUX_CTL_PAD_SEMC_DATA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 351 | #define SW_MUX_CTL_PAD_SEMC_DATA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 352 | #define SW_MUX_CTL_PAD_SEMC_DATA2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 353 | #define SW_MUX_CTL_PAD_SEMC_DATA3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 354 | #define SW_MUX_CTL_PAD_SEMC_DATA4_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 355 | #define SW_MUX_CTL_PAD_SEMC_DATA5_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 356 | #define SW_MUX_CTL_PAD_SEMC_DATA6_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 357 | #define SW_MUX_CTL_PAD_SEMC_DATA7_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 358 | #define SW_MUX_CTL_PAD_SEMC_DATA8_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 359 | #define SW_MUX_CTL_PAD_SEMC_DATA9_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 360 | #define SW_MUX_CTL_PAD_SEMC_DATA10_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 361 | #define SW_MUX_CTL_PAD_SEMC_DATA11_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 362 | #define SW_MUX_CTL_PAD_SEMC_DATA12_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 363 | #define SW_MUX_CTL_PAD_SEMC_DATA13_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 364 | #define SW_MUX_CTL_PAD_SEMC_DATA14_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 365 | #define SW_MUX_CTL_PAD_SEMC_DATA15_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 366 | #define SW_MUX_CTL_PAD_SEMC_ADDR0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 367 | #define SW_MUX_CTL_PAD_SEMC_ADDR1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 368 | #define SW_MUX_CTL_PAD_SEMC_ADDR2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 369 | #define SW_MUX_CTL_PAD_SEMC_ADDR3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 370 | #define SW_MUX_CTL_PAD_SEMC_ADDR4_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 371 | #define SW_MUX_CTL_PAD_SEMC_ADDR5_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 372 | #define SW_MUX_CTL_PAD_SEMC_ADDR6_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 373 | #define SW_MUX_CTL_PAD_SEMC_ADDR7_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 374 | #define SW_MUX_CTL_PAD_SEMC_ADDR8_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 375 | #define SW_MUX_CTL_PAD_SEMC_ADDR9_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 376 | #define SW_MUX_CTL_PAD_SEMC_ADDR10_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 377 | #define SW_MUX_CTL_PAD_SEMC_ADDR11_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 378 | #define SW_MUX_CTL_PAD_SEMC_ADDR12_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 379 | #define SW_MUX_CTL_PAD_SEMC_BA0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 380 | #define SW_MUX_CTL_PAD_SEMC_BA1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 381 | #define SW_MUX_CTL_PAD_SEMC_DQS_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 382 | #define SW_MUX_CTL_PAD_SEMC_RDY_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 383 | #define SW_MUX_CTL_PAD_SEMC_CSX0_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 384 | #define SW_MUX_CTL_PAD_SEMC_CSX1_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 385 | #define SW_MUX_CTL_PAD_SEMC_CSX2_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 386 | #define SW_MUX_CTL_PAD_SEMC_CSX3_IDX kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 387 | 388 | #define SW_PAD_CTL_PAD_SEMC_DATA0_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 389 | #define SW_PAD_CTL_PAD_SEMC_DATA1_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 390 | #define SW_PAD_CTL_PAD_SEMC_DATA2_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 391 | #define SW_PAD_CTL_PAD_SEMC_DATA3_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 392 | #define SW_PAD_CTL_PAD_SEMC_DATA4_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 393 | #define SW_PAD_CTL_PAD_SEMC_DATA5_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 394 | #define SW_PAD_CTL_PAD_SEMC_DATA6_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 395 | #define SW_PAD_CTL_PAD_SEMC_DATA7_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 396 | #define SW_PAD_CTL_PAD_SEMC_DATA8_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 397 | #define SW_PAD_CTL_PAD_SEMC_DATA9_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 398 | #define SW_PAD_CTL_PAD_SEMC_DATA10_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 399 | #define SW_PAD_CTL_PAD_SEMC_DATA11_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 400 | #define SW_PAD_CTL_PAD_SEMC_DATA12_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 401 | #define SW_PAD_CTL_PAD_SEMC_DATA13_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 402 | #define SW_PAD_CTL_PAD_SEMC_DATA14_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 403 | #define SW_PAD_CTL_PAD_SEMC_DATA15_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 404 | #define SW_PAD_CTL_PAD_SEMC_ADDR0_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 405 | #define SW_PAD_CTL_PAD_SEMC_ADDR1_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 406 | #define SW_PAD_CTL_PAD_SEMC_ADDR2_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 407 | #define SW_PAD_CTL_PAD_SEMC_ADDR3_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 408 | #define SW_PAD_CTL_PAD_SEMC_ADDR4_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 409 | #define SW_PAD_CTL_PAD_SEMC_ADDR5_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 410 | #define SW_PAD_CTL_PAD_SEMC_ADDR6_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 411 | #define SW_PAD_CTL_PAD_SEMC_ADDR7_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 412 | #define SW_PAD_CTL_PAD_SEMC_ADDR8_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 413 | #define SW_PAD_CTL_PAD_SEMC_ADDR9_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 414 | #define SW_PAD_CTL_PAD_SEMC_ADDR10_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 415 | #define SW_PAD_CTL_PAD_SEMC_ADDR11_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 416 | #define SW_PAD_CTL_PAD_SEMC_ADDR12_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 417 | #define SW_PAD_CTL_PAD_SEMC_BA0_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 418 | #define SW_PAD_CTL_PAD_SEMC_BA1_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 419 | #define SW_PAD_CTL_PAD_SEMC_DQS_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 420 | #define SW_PAD_CTL_PAD_SEMC_RDY_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 421 | #define SW_PAD_CTL_PAD_SEMC_CSX0_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 422 | #define SW_PAD_CTL_PAD_SEMC_CSX1_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 423 | #define SW_PAD_CTL_PAD_SEMC_CSX2_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 424 | #define SW_PAD_CTL_PAD_SEMC_CSX3_IDX kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 425 | 426 | #define SEMC_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(0) 427 | #define SEMC_CSX0_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(0) 428 | #define SEMC_CSX1_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(2) // SEMC_CSX1 of instance 429 | #define SEMC_CSX2_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(2) // SEMC_CSX2 of instance 430 | #define SEMC_CSX3_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(2) // SEMC_CSX3 of instance 431 | #define SEMC_CSX123_MUX_VAL IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(6) 432 | 433 | // No-Pull 434 | #define SEMC_SW_PAD_CTL_VAL IOMUXC_SW_PAD_CTL_PAD_PULL(3) 435 | 436 | // Pull-up 437 | #define SEMC_RDY_SW_PAD_CTL_VAL IOMUXC_SW_PAD_CTL_PAD_PULL(1) 438 | 439 | // Pull-down 440 | #define SEMC_DQS_SW_PAD_CTL_VAL IOMUXC_SW_PAD_CTL_PAD_PULL(2) 441 | 442 | //////////////////////////////////////////////////////////////////////////////// 443 | // EOF 444 | //////////////////////////////////////////////////////////////////////////////// 445 | -------------------------------------------------------------------------------- /bsp/imxrt1170_a0/flash_drv/target_config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 - 2019 NXP 3 | * 4 | * All rights reserved. 5 | * 6 | * SPDX-License-Identifier: BSD-3-Clause 7 | */ 8 | #if !defined(__TARGET_CONFIG_H__) 9 | #define __TARGET_CONFIG_H__ 10 | 11 | #include 12 | 13 | //////////////////////////////////////////////////////////////////////////////// 14 | // Definitions 15 | //////////////////////////////////////////////////////////////////////////////// 16 | 17 | //! @brief Constants for FlexSPI features. 18 | enum 19 | { 20 | kFlexSpi_AhbMemoryMaxSizeMB = (256u * 1024u * 1024u), 21 | }; 22 | 23 | //! @brief Version constants for the target. 24 | enum _target_version_constants 25 | { 26 | kTarget_Version_Name = 'T', 27 | kTarget_Version_Major = 2, 28 | kTarget_Version_Minor = 0, 29 | kTarget_Version_Bugfix = 0 30 | }; 31 | 32 | //!@brief FlexSPI related definitions 33 | enum 34 | { 35 | kFlexSpi1_AMBA_Base = 0x30000000u, 36 | kFlexSpi1_ALIAS_Base = 0x08000000u, 37 | kFlexSpi2_AMBA_Base = 0x60000000u, 38 | kFlexSpi_Key_Store_Offset = 0x800, 39 | }; 40 | 41 | //!@brief Memory index definitions 42 | enum 43 | { 44 | kIndexITCM = 0, 45 | kIndexDTCM = 1, 46 | kIndexOCRAM = 2, 47 | kIndexFlexSpi1 = 3, 48 | kIndexFlexSpi1Alias = 4, 49 | kIndexFlexSpi2 = 5, 50 | kIndexSemc = 6, 51 | }; 52 | 53 | //!@brief PIT backward compatible defintion 54 | #define kCLOCK_Pit kCLOCK_Pit1 55 | 56 | //!@brief FLEXSPI clock definitions 57 | enum 58 | { 59 | kFlexSpiSerialClk_30MHz = 1, 60 | kFlexSpiSerialClk_50MHz = 2, 61 | kFlexSpiSerialClk_60MHz = 3, 62 | kFlexSpiSerialClk_80MHz = 4, 63 | kFlexSpiSerialClk_100MHz = 5, 64 | kFlexSpiSerialClk_120MHz = 6, 65 | kFlexSpiSerialClk_133MHz = 7, 66 | kFlexSpiSerialClk_166MHz = 8, 67 | kFlexSpiSerialClk_200MHz = 9, 68 | }; 69 | 70 | //!@brief FLEXSPI instnaces 71 | enum 72 | { 73 | kFlexspiInstance_1 = 1, 74 | kFlexspiInstance_2 = 2, 75 | }; 76 | 77 | //!@brief FLEXSPI Boot Clock Source 78 | enum 79 | { 80 | kFlexSpiBootClkcSrc = 4, 81 | }; 82 | 83 | //!@brief LPSPI clock definitions 84 | enum 85 | { 86 | kRecoveryBoot_LpSpiRootClkFreq = 40000000ul, 87 | }; 88 | 89 | //!@brief Number of MPU entries 90 | #define MPU_ENTRY_ITCM_INDEX (3) 91 | #define MPU_ENTRY_DTCM_INDEX (4) 92 | #define MPU_ENTRY_OCRAM_INDEX (5) 93 | #define MPU_ENTRY_IMG_MEM_INDEX (6) 94 | 95 | #define MPU_ENTRIES (8) 96 | 97 | //!@brief ROMCP related definitions 98 | #define ROMCP_BASE (0x40CA4000u) //!@brief ROMCP base address 99 | //!@brief ROM Pach entries 100 | enum 101 | { 102 | kRompatchFuse_StartIndex = 0x90, 103 | kRomPatchEntries_Default = 32 - 1, 104 | kRomPatchEntries_Max = kRomPatchEntries_Default, 105 | }; 106 | 107 | enum 108 | { 109 | kMEM_ROM_BASE = 0x00200000u, 110 | kMEM_DTCM_BASE = 0x20000000u, 111 | kVectorTable_Size = 0x400, 112 | }; 113 | 114 | enum 115 | { 116 | kProduct_USB_PID = 0x013d, 117 | kProduct_USB_VID = 0x1fc9, 118 | }; 119 | 120 | // Default deley cell value 121 | #define FLEXSPI_DELAY_CELL_SDR_DEFAULT 41 122 | #define FLEXSPI_DELAY_CELL_DDR_DEFAULT 21 123 | 124 | //!@brief ROMCP lock related definitions 125 | enum 126 | { 127 | kStickyBits_ROMCP_Lock = 5u, 128 | kStickyBits_ROMCP_Lock_Mask = (1ul << kStickyBits_ROMCP_Lock), 129 | }; 130 | 131 | //!@brief ROM Readout Protection related definitions 132 | enum 133 | { 134 | kStickyBits_RomReadout_Lock = 3u, 135 | kStickyBits_RomReadout_Lock_Mask = (1ul << kStickyBits_RomReadout_Lock), 136 | }; 137 | 138 | enum 139 | { 140 | kLpsrGpr11_ReadoutLogicActive = 24, 141 | kLpsrGpr11_ReadoutLogicActive_Mask = (1ul << kLpsrGpr11_ReadoutLogicActive), 142 | }; 143 | 144 | #define LPSR_GPR41 (*(volatile uint32_t *)0x40c0c0a4) 145 | 146 | //#define XSPI_FLASH_DUMMY_CYCLE_PROBE_OFFSET (0x400) 147 | 148 | //!@brief FLEXSPI NOR configuration macros for SIP package 149 | #define FLEXSPI_SIP_NOR_DEFAULT_CONFIG() \ 150 | do \ 151 | { \ 152 | memCfg->sflashA1Size = 0; \ 153 | memCfg->sflashA2Size = 0; \ 154 | memCfg->sflashB1Size = 16 * 1024u * 1024; \ 155 | memCfg->sflashB2Size = 0; \ 156 | } while (0) 157 | 158 | #define FLEXSPI_SIP_NOR_AUTO_PROBE_CONFIG() \ 159 | do \ 160 | { \ 161 | flashAutoProbeType = kFlashAutoProbeType_QuadSpiNor; \ 162 | configOption.option0.B.option_size = 1; \ 163 | configOption.option1.B.flash_connection = kSerialNorConnection_SinglePortB; \ 164 | } while (0) 165 | 166 | #endif // __TARGET_CONFIG_H__ 167 | 168 | #define SERIAL_BOOT_INIT (0) 169 | #define SERIAL_BOOT_INIT_LOAD (1) 170 | #define SERIAL_BOOT_FULL_LOAD (2) 171 | #define MASTERBOOT_JUMP_APP (3) 172 | 173 | extern void handle_soc_pending_debug_request(uint32_t arg); 174 | #define MASTERBOOT_SERIAL_DOWNLOADER_HOOK(arg) \ 175 | do \ 176 | { \ 177 | handle_soc_pending_debug_request(arg); \ 178 | } while (0); 179 | 180 | #define MASTERBOOT_JUMP_APP_HOOK() \ 181 | do \ 182 | { \ 183 | handle_soc_pending_debug_request(MASTERBOOT_JUMP_APP); \ 184 | } while (0); 185 | 186 | //////////////////////////////////////////////////////////////////////////////// 187 | // EOF 188 | //////////////////////////////////////////////////////////////////////////////// 189 | -------------------------------------------------------------------------------- /doc/Architecture_Design.pptx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JayHeng/kFlashFile/0c8e738d3b79dcc697951016ef43656ca93795cb/doc/Architecture_Design.pptx -------------------------------------------------------------------------------- /doc/kFlashFile_Design0.PNG: -------------------------------------------------------------------------------- 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"kflash_drv.h" 6 | #include "fsl_cache.h" 7 | /******************************************************************************* 8 | * Definitions 9 | ******************************************************************************/ 10 | 11 | 12 | /******************************************************************************* 13 | * Prototypes 14 | ******************************************************************************/ 15 | 16 | 17 | /******************************************************************************* 18 | * Variables 19 | ******************************************************************************/ 20 | 21 | static flexspi_nor_config_t s_flashConfig; 22 | 23 | /******************************************************************************* 24 | * Code 25 | ******************************************************************************/ 26 | 27 | status_t kflash_drv_init(void) 28 | { 29 | status_t status; 30 | 31 | serial_nor_config_option_t configOption; 32 | configOption.option0.U = KFLASH_CONFIG_OPTION; 33 | 34 | memset(&s_flashConfig, 0x0, sizeof(flexspi_nor_config_t)); 35 | 36 | status = flexspi_nor_get_config(KFLASH_INSTANCE, &s_flashConfig, &configOption); 37 | if (status != kStatus_Success) 38 | { 39 | return status; 40 | } 41 | 42 | status = flexspi_nor_flash_init(KFLASH_INSTANCE, &s_flashConfig); 43 | if (status != kStatus_Success) 44 | { 45 | return status; 46 | } 47 | 48 | return kStatus_Success; 49 | } 50 | 51 | uint32_t kflash_drv_get_info(kflash_mem_info_t flashInfo) 52 | { 53 | if (kFlashMemInfo_PageSize == flashInfo) 54 | { 55 | if (s_flashConfig.pageSize) 56 | { 57 | return s_flashConfig.pageSize; 58 | } 59 | else 60 | { 61 | return KFLASH_PAGE_SIZE; 62 | } 63 | } 64 | else if (kFlashMemInfo_SectorSize == flashInfo) 65 | { 66 | if (s_flashConfig.sectorSize) 67 | { 68 | return s_flashConfig.sectorSize; 69 | } 70 | else 71 | { 72 | return KFLASH_SECTOR_SIZE; 73 | } 74 | } 75 | else if (kFlashMemInfo_BlockSize == flashInfo) 76 | { 77 | return s_flashConfig.blockSize; 78 | } 79 | else if (kFlashMemInfo_TotalSize == flashInfo) 80 | { 81 | if (s_flashConfig.memConfig.sflashA1Size) 82 | { 83 | return s_flashConfig.memConfig.sflashA1Size; 84 | } 85 | else if (s_flashConfig.memConfig.sflashA2Size) 86 | { 87 | return s_flashConfig.memConfig.sflashA2Size; 88 | } 89 | else if (s_flashConfig.memConfig.sflashB1Size) 90 | { 91 | return s_flashConfig.memConfig.sflashB1Size; 92 | } 93 | else if (s_flashConfig.memConfig.sflashB2Size) 94 | { 95 | return s_flashConfig.memConfig.sflashB2Size; 96 | } 97 | } 98 | 99 | return 0; 100 | } 101 | 102 | status_t kflash_drv_erase_region(uint32_t start, uint32_t length) 103 | { 104 | status_t status; 105 | 106 | status = flexspi_nor_flash_erase(KFLASH_INSTANCE, &s_flashConfig, start - KFLASH_BASE_ADDRESS, length); 107 | if (status != kStatus_Success) 108 | { 109 | return status; 110 | } 111 | 112 | DCACHE_InvalidateByRange(start, length); 113 | 114 | return kStatus_Success; 115 | } 116 | 117 | status_t kflash_drv_program_region(uint32_t dstAddr, const uint32_t *src, uint32_t length) 118 | { 119 | status_t status; 120 | 121 | status = flexspi_nor_flash_program(KFLASH_INSTANCE, &s_flashConfig, dstAddr - KFLASH_BASE_ADDRESS, src, length); 122 | if (status != kStatus_Success) 123 | { 124 | return status; 125 | } 126 | 127 | DCACHE_InvalidateByRange(dstAddr, length); 128 | 129 | return kStatus_Success; 130 | } 131 | 132 | -------------------------------------------------------------------------------- /src/kflash_drv.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Jay Heng 3 | */ 4 | 5 | #ifndef __KFLASH_DRV_H__ 6 | #define __KFLASH_DRV_H__ 7 | 8 | #include 9 | #include 10 | #include "flexspi_nor_flash.h" 11 | /******************************************************************************* 12 | * Definitions 13 | ******************************************************************************/ 14 | 15 | #define KFLASH_INSTANCE (1) 16 | #define KFLASH_CONFIG_OPTION (0xc0403007) 17 | 18 | #define KFLASH_BASE_ADDRESS (0x30000000) 19 | #define KFLASH_SECTOR_SIZE (0x1000) 20 | #define KFLASH_PAGE_SIZE (256) 21 | 22 | /* It is restriction of low level flash driver */ 23 | #define KFLASH_PROGRAM_ALIGNMENT (4) 24 | /* For SDR mode, it is 1; For DDR mode, it is 2 */ 25 | #define KFLASH_PROGRAM_UNIT (2) 26 | 27 | typedef enum 28 | { 29 | kFlashMemInfo_PageSize, 30 | kFlashMemInfo_SectorSize, 31 | kFlashMemInfo_BlockSize, 32 | kFlashMemInfo_TotalSize, 33 | } kflash_mem_info_t; 34 | 35 | /******************************************************************************* 36 | * API 37 | ******************************************************************************/ 38 | 39 | #ifdef __cplusplus 40 | extern "C" 41 | { 42 | #endif 43 | 44 | status_t kflash_drv_init(void); 45 | 46 | uint32_t kflash_drv_get_info(kflash_mem_info_t flashInfo); 47 | 48 | status_t kflash_drv_erase_region(uint32_t start, uint32_t length); 49 | 50 | status_t kflash_drv_program_region(uint32_t dstAddr, const uint32_t *src, uint32_t length); 51 | 52 | #ifdef __cplusplus 53 | } 54 | #endif 55 | 56 | #endif // __KFLASH_DRV_H__ 57 | -------------------------------------------------------------------------------- /src/kflash_file.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Jay Heng 3 | */ 4 | 5 | #include "kflash_file.h" 6 | /******************************************************************************* 7 | * Definitions 8 | ******************************************************************************/ 9 | 10 | #define KFLASH_MEM_BLANK (~(0)) 11 | 12 | #define KFLASH_HDR_MAGIC_DAT (0xABECEDA8) 13 | #define KFLASH_HDR_MAGIC_LEN (4) 14 | 15 | /******************************************************************************* 16 | * Prototypes 17 | ******************************************************************************/ 18 | 19 | static status_t kflash_check_allocation(kflash_file_t *flashFile, uint32_t memStart, uint32_t memSize, uint32_t fileSize); 20 | static void kflash_update_active_start(kflash_file_t *flashFile); 21 | static bool kflash_is_valid_file_found(kflash_file_t *flashFile); 22 | static void kflash_invert_mem_data(uint8_t *src, uint32_t length); 23 | static void kflash_pull_file_data(kflash_file_t *flashFile); 24 | static bool kflash_is_mem_blank(uint32_t start, uint32_t length); 25 | static status_t kflash_clear_data_region(kflash_file_t *flashFile); 26 | static status_t kflash_clear_header_region(kflash_file_t *flashFile); 27 | static uint32_t kflash_calculate_position_value(kflash_file_t *flashFile); 28 | static status_t kflash_push_file_header(kflash_file_t *flashFile); 29 | static status_t kflash_clean_file_system(kflash_file_t *flashFile); 30 | static bool kflash_is_valid_file_range(kflash_file_t *flashFile, uint32_t offset, uint32_t size); 31 | static bool kflash_is_file_data_changed(kflash_file_t *flashFile, uint32_t offset, uint8_t *data, uint32_t size); 32 | static bool kflash_can_file_be_overwritten(kflash_file_t *flashFile, uint32_t offset, uint8_t *data, uint32_t size); 33 | static status_t kflash_push_file_data(kflash_file_t *flashFile, uint32_t offset, uint32_t size, bool isOverwrite); 34 | 35 | /******************************************************************************* 36 | * Variables 37 | ******************************************************************************/ 38 | 39 | 40 | /******************************************************************************* 41 | * Code 42 | ******************************************************************************/ 43 | 44 | status_t kflash_file_init(kflash_file_t *flashFile, 45 | uint32_t memStart, 46 | uint32_t memSize, 47 | uint32_t fileSize) 48 | { 49 | status_t status; 50 | 51 | /* Check params */ 52 | if (NULL == flashFile) 53 | { 54 | return kStatus_KFLASHFILE_InitFail; 55 | } 56 | 57 | /* Init FlexSPI module and flash */ 58 | status = kflash_drv_init(); 59 | if (status != kStatus_Success) 60 | { 61 | return status; 62 | } 63 | 64 | /* Check and set intial file info (Const) */ 65 | status = kflash_check_allocation(flashFile, memStart, memSize, fileSize); 66 | if (status != kStatus_Success) 67 | { 68 | return status; 69 | } 70 | 71 | /* Check if there is valid file */ 72 | if (kflash_is_valid_file_found(flashFile)) 73 | { 74 | kflash_pull_file_data(flashFile); 75 | } 76 | else 77 | { 78 | status = kflash_clean_file_system(flashFile); 79 | if (status != kStatus_Success) 80 | { 81 | return status; 82 | } 83 | } 84 | 85 | return kStatus_Success; 86 | } 87 | 88 | status_t kflash_file_read(kflash_file_t *flashFile, 89 | uint32_t offset, 90 | uint8_t *data, 91 | uint32_t size) 92 | { 93 | if (kflash_is_valid_file_range(flashFile, offset, size)) 94 | { 95 | memcpy(data, &flashFile->buffer[offset], size); 96 | } 97 | else 98 | { 99 | return kStatus_KFLASHFILE_RangeError; 100 | } 101 | 102 | return kStatus_Success; 103 | } 104 | 105 | status_t kflash_file_save(kflash_file_t *flashFile, 106 | uint32_t offset, 107 | uint8_t *data, 108 | uint32_t size) 109 | { 110 | status_t status; 111 | 112 | /* Validate the user range of file data */ 113 | if (kflash_is_valid_file_range(flashFile, offset, size)) 114 | { 115 | /* Check if the file data is changed, if no, nothing needs to do */ 116 | if (!kflash_is_file_data_changed(flashFile, offset, data, size)) 117 | { 118 | return kStatus_Success; 119 | } 120 | /* Check if new file data can be overwritten in flash directly */ 121 | else if (kflash_can_file_be_overwritten(flashFile, offset, data, size)) 122 | { 123 | memcpy(&flashFile->buffer[offset], data, size); 124 | status = kflash_push_file_data(flashFile, offset, size, true); 125 | if (status != kStatus_Success) 126 | { 127 | return status; 128 | } 129 | } 130 | else 131 | { 132 | uint32_t sectorSize = kflash_drv_get_info(kFlashMemInfo_SectorSize); 133 | uint32_t managedEnd = flashFile->managedStart + flashFile->managedSize - sectorSize * KFLASH_HDR_SECTORS; 134 | uint32_t recordSwitchPos = (sectorSize - KFLASH_HDR_MAGIC_LEN) / sizeof(KFLASH_HDR_POS_TYPE); 135 | 136 | /* Find new position for file data */ 137 | if ((managedEnd - flashFile->activedSize) == flashFile->activedStart) 138 | { 139 | /* One round finished, We need to program file data from the managedStart. 140 | * We just erase the first data sector of managed flash region here. 141 | */ 142 | status = kflash_drv_erase_region(flashFile->managedStart, sectorSize); 143 | if (status != kStatus_Success) 144 | { 145 | return status; 146 | } 147 | flashFile->activedStart = flashFile->managedStart; 148 | } 149 | else if (flashFile->managedStart == flashFile->activedStart) 150 | { 151 | /* if it is the first round, nothing needs to do here. 152 | * if it is not first round, we should erase the second to the last data sector. 153 | */ 154 | if (!kflash_is_mem_blank(flashFile->managedStart + sectorSize, sectorSize)) 155 | { 156 | status = kflash_drv_erase_region(flashFile->managedStart + sectorSize, flashFile->managedSize - sectorSize * (KFLASH_HDR_SECTORS + 1)); 157 | if (status != kStatus_Success) 158 | { 159 | return status; 160 | } 161 | } 162 | flashFile->activedStart += flashFile->activedSize; 163 | } 164 | else 165 | { 166 | flashFile->activedStart += flashFile->activedSize; 167 | } 168 | 169 | /* Flush file data into new position */ 170 | memcpy(&flashFile->buffer[offset], data, size); 171 | status = kflash_push_file_data(flashFile, 0, flashFile->activedSize, false); 172 | if (status != kStatus_Success) 173 | { 174 | return status; 175 | } 176 | 177 | /* Handle file header to record new position */ 178 | if (!((flashFile->recordedPos + 1) % recordSwitchPos)) 179 | { 180 | uint32_t posSectorAddr; 181 | uint32_t preRecordIdx; 182 | 183 | flashFile->recordedIdx = flashFile->recordedIdx % KFLASH_HDR_SECTORS + 1; 184 | posSectorAddr = managedEnd + sectorSize * (flashFile->recordedIdx - 1); 185 | /* Need to erase next header sector */ 186 | if (!kflash_is_mem_blank(posSectorAddr, sectorSize)) 187 | { 188 | status = kflash_drv_erase_region(posSectorAddr, sectorSize); 189 | if (status != kStatus_Success) 190 | { 191 | return status; 192 | } 193 | } 194 | flashFile->recordedPos = 0; 195 | kflash_push_file_header(flashFile); 196 | 197 | preRecordIdx = (flashFile->recordedIdx == 1) ? KFLASH_HDR_SECTORS : (flashFile->recordedIdx - 1); 198 | posSectorAddr = managedEnd + sectorSize * (preRecordIdx - 1); 199 | /* Need to clear previous header sector */ 200 | if (!kflash_is_mem_blank(posSectorAddr, sectorSize)) 201 | { 202 | status = kflash_drv_erase_region(posSectorAddr, sectorSize); 203 | if (status != kStatus_Success) 204 | { 205 | return status; 206 | } 207 | } 208 | } 209 | else 210 | { 211 | flashFile->recordedPos++; 212 | kflash_push_file_header(flashFile); 213 | } 214 | } 215 | } 216 | else 217 | { 218 | return kStatus_KFLASHFILE_RangeError; 219 | } 220 | 221 | return kStatus_Success; 222 | } 223 | 224 | status_t kflash_file_deinit(kflash_file_t *flashFile) 225 | { 226 | return kflash_clear_header_region(flashFile); 227 | } 228 | 229 | static status_t kflash_check_allocation(kflash_file_t *flashFile, uint32_t memStart, uint32_t memSize, uint32_t fileSize) 230 | { 231 | uint32_t pageSize; 232 | uint32_t sectorSize; 233 | uint32_t totalSize; 234 | 235 | if (memStart >= KFLASH_BASE_ADDRESS) 236 | { 237 | memStart -= KFLASH_BASE_ADDRESS; 238 | } 239 | 240 | sectorSize = kflash_drv_get_info(kFlashMemInfo_SectorSize); 241 | if (memStart % sectorSize) 242 | { 243 | return kStatus_KFLASHFILE_AllocateFail; 244 | } 245 | flashFile->managedStart = memStart + KFLASH_BASE_ADDRESS; 246 | 247 | if ((memSize % sectorSize) || ((memSize / sectorSize) < KFLASH_MIN_SECTORS)) 248 | { 249 | return kStatus_KFLASHFILE_AllocateFail; 250 | } 251 | flashFile->managedSize = memSize; 252 | 253 | totalSize = kflash_drv_get_info(kFlashMemInfo_TotalSize);; 254 | if (totalSize && ((memStart + memSize) > totalSize)) 255 | { 256 | return kStatus_KFLASHFILE_AllocateFail; 257 | } 258 | 259 | pageSize = kflash_drv_get_info(kFlashMemInfo_PageSize); 260 | if ((fileSize % pageSize) || (fileSize > sectorSize) || (sectorSize % fileSize) || (fileSize > sizeof(flashFile->buffer))) 261 | { 262 | return kStatus_KFLASHFILE_AllocateFail; 263 | } 264 | flashFile->activedSize = fileSize; 265 | 266 | return kStatus_Success; 267 | } 268 | 269 | static void kflash_update_active_start(kflash_file_t *flashFile) 270 | { 271 | uint32_t sectorSize = kflash_drv_get_info(kFlashMemInfo_SectorSize); 272 | uint32_t magicAddr = flashFile->managedStart + flashFile->managedSize - sectorSize * (KFLASH_HDR_SECTORS + 1 - flashFile->recordedIdx); 273 | uint32_t posValue = *(KFLASH_HDR_POS_TYPE *)(magicAddr + KFLASH_HDR_MAGIC_LEN + flashFile->recordedPos * sizeof(KFLASH_HDR_POS_TYPE)); 274 | 275 | flashFile->activedStart = flashFile->managedStart + flashFile->activedSize * posValue; 276 | } 277 | 278 | static bool kflash_is_valid_file_found(kflash_file_t *flashFile) 279 | { 280 | uint32_t sectorSize = kflash_drv_get_info(kFlashMemInfo_SectorSize); 281 | uint32_t magicAddr = flashFile->managedStart + flashFile->managedSize; 282 | 283 | /* Clear file header recorder info */ 284 | flashFile->recordedIdx = 0; 285 | 286 | /* File header should be in the last two sectors of managed flash region*/ 287 | for (uint32_t idx = KFLASH_HDR_SECTORS; idx > 0; idx--) 288 | { 289 | magicAddr -= sectorSize; 290 | if (KFLASH_HDR_MAGIC_DAT == (*(uint32_t *)magicAddr)) 291 | { 292 | uint32_t posAddr = magicAddr + KFLASH_HDR_MAGIC_LEN; 293 | uint32_t posEnd = magicAddr + sectorSize; 294 | flashFile->recordedPos = 0; 295 | while (posAddr < posEnd) 296 | { 297 | if ((KFLASH_HDR_POS_TYPE)KFLASH_MEM_BLANK == (*(KFLASH_HDR_POS_TYPE *)posAddr)) 298 | { 299 | /* recordedPos means current active file position*/ 300 | if (flashFile->recordedPos) 301 | { 302 | flashFile->recordedPos--; 303 | } 304 | break; 305 | } 306 | else 307 | { 308 | posAddr += sizeof(KFLASH_HDR_POS_TYPE); 309 | flashFile->recordedPos++; 310 | } 311 | } 312 | /* Record file header info */ 313 | flashFile->recordedIdx = idx; 314 | kflash_update_active_start(flashFile); 315 | break; 316 | } 317 | } 318 | 319 | return (flashFile->recordedIdx != 0); 320 | } 321 | 322 | static void kflash_invert_mem_data(uint8_t *src, uint32_t length) 323 | { 324 | while (length--) 325 | { 326 | *src = ~(*src); 327 | src++; 328 | } 329 | } 330 | 331 | static void kflash_pull_file_data(kflash_file_t *flashFile) 332 | { 333 | memcpy(flashFile->buffer, (uint8_t *)flashFile->activedStart, flashFile->activedSize); 334 | 335 | /* As we always program inverted file data to flash, that's why we do this here */ 336 | kflash_invert_mem_data(flashFile->buffer, flashFile->activedSize); 337 | } 338 | 339 | static bool kflash_is_mem_blank(uint32_t start, uint32_t length) 340 | { 341 | while (length--) 342 | { 343 | if ((uint8_t)KFLASH_MEM_BLANK != (*(uint8_t *)start)) 344 | { 345 | return false; 346 | } 347 | start++; 348 | } 349 | 350 | return true; 351 | } 352 | 353 | static status_t kflash_clear_data_region(kflash_file_t *flashFile) 354 | { 355 | status_t status; 356 | uint32_t datSectorIdx = 0; 357 | uint32_t sectorSize = kflash_drv_get_info(kFlashMemInfo_SectorSize); 358 | uint32_t totalDatSectors = flashFile->managedSize / sectorSize - KFLASH_HDR_SECTORS; 359 | uint32_t eraseAddr = flashFile->managedStart; 360 | 361 | /* Make sure all data sectors are blank */ 362 | while (datSectorIdx < totalDatSectors) 363 | { 364 | if (!kflash_is_mem_blank(eraseAddr, sectorSize)) 365 | { 366 | status = kflash_drv_erase_region(eraseAddr, sectorSize); 367 | if (status != kStatus_Success) 368 | { 369 | return status; 370 | } 371 | } 372 | datSectorIdx++; 373 | eraseAddr += sectorSize; 374 | } 375 | 376 | return kStatus_Success; 377 | } 378 | static status_t kflash_clear_header_region(kflash_file_t *flashFile) 379 | { 380 | status_t status; 381 | uint32_t hdrSectorIdx = 0; 382 | uint32_t sectorSize = kflash_drv_get_info(kFlashMemInfo_SectorSize); 383 | uint32_t eraseAddr = flashFile->managedStart + flashFile->managedSize - sectorSize * KFLASH_HDR_SECTORS; 384 | 385 | /* Make sure all header sectors are blank */ 386 | while (hdrSectorIdx < KFLASH_HDR_SECTORS) 387 | { 388 | if (!kflash_is_mem_blank(eraseAddr, sectorSize)) 389 | { 390 | status = kflash_drv_erase_region(eraseAddr, sectorSize); 391 | if (status != kStatus_Success) 392 | { 393 | return status; 394 | } 395 | } 396 | hdrSectorIdx++; 397 | eraseAddr += sectorSize; 398 | } 399 | 400 | return kStatus_Success; 401 | } 402 | 403 | static uint32_t kflash_calculate_position_value(kflash_file_t *flashFile) 404 | { 405 | return ((flashFile->activedStart - flashFile->managedStart) / flashFile->activedSize); 406 | } 407 | 408 | static status_t kflash_push_file_header(kflash_file_t *flashFile) 409 | { 410 | status_t status; 411 | uint32_t sectorSize = kflash_drv_get_info(kFlashMemInfo_SectorSize); 412 | uint32_t magicAddr = flashFile->managedStart + flashFile->managedSize - sectorSize * (KFLASH_HDR_SECTORS + 1 - flashFile->recordedIdx); 413 | uint32_t magicValue = KFLASH_HDR_MAGIC_DAT; 414 | uint32_t posAddr = magicAddr + KFLASH_HDR_MAGIC_LEN + flashFile->recordedPos * sizeof(KFLASH_HDR_POS_TYPE); 415 | uint32_t posValue = kflash_calculate_position_value(flashFile); 416 | 417 | if ((uint32_t)KFLASH_MEM_BLANK == (*(uint32_t *)magicAddr)) 418 | { 419 | status = kflash_drv_program_region(magicAddr, &magicValue, KFLASH_HDR_MAGIC_LEN); 420 | if (status != kStatus_Success) 421 | { 422 | return status; 423 | } 424 | } 425 | 426 | if ((KFLASH_HDR_POS_TYPE)KFLASH_MEM_BLANK == (*(KFLASH_HDR_POS_TYPE *)posAddr)) 427 | { 428 | status = kflash_drv_program_region(posAddr, &posValue, sizeof(KFLASH_HDR_POS_TYPE)); 429 | if (status != kStatus_Success) 430 | { 431 | return status; 432 | } 433 | } 434 | else 435 | { 436 | return kStatus_KFLASHFILE_PositionError; 437 | } 438 | 439 | return kStatus_Success; 440 | } 441 | 442 | static status_t kflash_clean_file_system(kflash_file_t *flashFile) 443 | { 444 | status_t status; 445 | 446 | status = kflash_clear_data_region(flashFile); 447 | if (status != kStatus_Success) 448 | { 449 | return status; 450 | } 451 | 452 | status = kflash_clear_header_region(flashFile); 453 | if (status != kStatus_Success) 454 | { 455 | return status; 456 | } 457 | 458 | /* Set more file info (Volatile) */ 459 | flashFile->activedStart = flashFile->managedStart; 460 | flashFile->recordedIdx = 1; 461 | flashFile->recordedPos = 0; 462 | memset(flashFile->buffer, 0x0, flashFile->activedSize); 463 | 464 | /* Fill initial file header into flash */ 465 | kflash_push_file_header(flashFile); 466 | 467 | return kStatus_Success; 468 | } 469 | 470 | static bool kflash_is_valid_file_range(kflash_file_t *flashFile, uint32_t offset, uint32_t size) 471 | { 472 | return ((offset + size) <= flashFile->activedSize); 473 | } 474 | 475 | static bool kflash_is_file_data_changed(kflash_file_t *flashFile, uint32_t offset, uint8_t *data, uint32_t size) 476 | { 477 | return (memcmp(&flashFile->buffer[offset], data, size) != 0); 478 | } 479 | 480 | static bool kflash_can_file_be_overwritten(kflash_file_t *flashFile, uint32_t offset, uint8_t *data, uint32_t size) 481 | { 482 | while (size--) 483 | { 484 | /* Check if src and dest are the same, or src is 0x00 if they are different */ 485 | if ((memcmp(&flashFile->buffer[offset], data, 1) != 0) && flashFile->buffer[offset]) 486 | { 487 | return false; 488 | } 489 | offset++; 490 | data++; 491 | } 492 | 493 | return true; 494 | } 495 | 496 | static status_t kflash_push_file_data(kflash_file_t *flashFile, uint32_t offset, uint32_t size, bool isOverwrite) 497 | { 498 | status_t status; 499 | 500 | if (isOverwrite) 501 | { 502 | size = ALIGN_UP(offset + size, (uint32_t)KFLASH_PROGRAM_ALIGNMENT); 503 | offset = ALIGN_DOWN(offset, (uint32_t)KFLASH_PROGRAM_ALIGNMENT); 504 | size -= offset; 505 | } 506 | else 507 | { 508 | if (!kflash_is_mem_blank(flashFile->activedStart, flashFile->activedSize)) 509 | { 510 | return kStatus_KFLASHFILE_PositionError; 511 | } 512 | offset = 0; 513 | size = flashFile->activedSize; 514 | } 515 | 516 | /* We should program inverted file data to flash, so we have more chance to overwrite the flash */ 517 | kflash_invert_mem_data(&flashFile->buffer[offset], size); 518 | 519 | status = kflash_drv_program_region(flashFile->activedStart, (const uint32_t *)&flashFile->buffer[offset], size); 520 | 521 | /* We need to recover file data back */ 522 | kflash_invert_mem_data(&flashFile->buffer[offset], size); 523 | 524 | return status; 525 | } 526 | 527 | -------------------------------------------------------------------------------- /src/kflash_file.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2020 Jay Heng 3 | */ 4 | 5 | #ifndef __KFLASH_FILE__ 6 | #define __KFLASH_FILE__ 7 | 8 | #include "kflash_drv.h" 9 | /******************************************************************************* 10 | * Definitions 11 | ******************************************************************************/ 12 | 13 | /* The Flash size used to save file header info, at least 2 sectors */ 14 | #define KFLASH_HDR_SECTORS (2) 15 | /* The data type used to record file data position in flash */ 16 | #define KFLASH_HDR_POS_TYPE uint16_t /* uint16_t or uint32_t */ 17 | /* The min size of managed flash region */ 18 | #define KFLASH_MIN_SECTORS (KFLASH_HDR_SECTORS + 2) 19 | /* The max size of file data */ 20 | #define KFLASH_MAX_FILE_SIZE (KFLASH_PAGE_SIZE * 2) 21 | 22 | /* KFLASH file status */ 23 | enum _kflash_file_status 24 | { 25 | kStatusGroup_KFLASHFILE = 250, 26 | kStatus_KFLASHFILE_InitFail = MAKE_STATUS(kStatusGroup_KFLASHFILE, 0), 27 | kStatus_KFLASHFILE_AllocateFail = MAKE_STATUS(kStatusGroup_KFLASHFILE, 1), 28 | kStatus_KFLASHFILE_RangeError = MAKE_STATUS(kStatusGroup_KFLASHFILE, 2), 29 | kStatus_KFLASHFILE_PositionError = MAKE_STATUS(kStatusGroup_KFLASHFILE, 3), 30 | }; 31 | 32 | typedef struct { 33 | uint32_t managedStart; 34 | uint32_t managedSize; 35 | uint32_t activedStart; 36 | uint32_t activedSize; 37 | /* Valid range: 1 - KFLASH_HDR_SECTORS */ 38 | uint32_t recordedIdx; 39 | /* *(KFLASH_HDR_POS_TYPE *)(hdrSectorStartAddr + 4 + recordedPos * sizeof(KFLASH_HDR_POS_TYPE)) = 40 | (activedStart - managedStart) / sectorSize */ 41 | uint32_t recordedPos; 42 | uint8_t buffer[KFLASH_MAX_FILE_SIZE]; 43 | } kflash_file_t; 44 | 45 | /******************************************************************************* 46 | * API 47 | ******************************************************************************/ 48 | 49 | #ifdef __cplusplus 50 | extern "C" 51 | { 52 | #endif 53 | 54 | /* Allocate file system or reuse existing file system */ 55 | status_t kflash_file_init(kflash_file_t *flashFile, uint32_t memStart, uint32_t memSize, uint32_t fileSize); 56 | /* Get actived file data from managed flash region */ 57 | status_t kflash_file_read(kflash_file_t *flashFile, uint32_t offset, uint8_t *data, uint32_t size); 58 | /* Save new file data into managed flash region */ 59 | status_t kflash_file_save(kflash_file_t *flashFile, uint32_t offset, uint8_t *data, uint32_t size); 60 | /* Just clear all the file headers for managed flash region */ 61 | status_t kflash_file_deinit(kflash_file_t *flashFile); 62 | 63 | #ifdef __cplusplus 64 | } 65 | #endif 66 | 67 | #endif // __KFLASH_FILE__ 68 | --------------------------------------------------------------------------------