├── .gitignore ├── CMSIS ├── Include │ ├── arm_common_tables.h │ ├── arm_const_structs.h │ ├── arm_math.h │ ├── cmsis_armcc.h │ ├── cmsis_armclang.h │ ├── cmsis_armclang_ltm.h │ ├── cmsis_compiler.h │ ├── cmsis_gcc.h │ ├── cmsis_iccarm.h │ ├── cmsis_version.h │ ├── core_armv81mml.h │ ├── core_armv8mbl.h │ ├── core_armv8mml.h │ ├── core_cm0.h │ ├── core_cm0plus.h │ ├── core_cm1.h │ ├── core_cm23.h │ ├── core_cm3.h │ ├── core_cm33.h │ ├── core_cm35p.h │ ├── core_cm4.h │ ├── core_cm7.h │ ├── core_dsp.h │ ├── core_sc000.h │ ├── core_sc300.h │ ├── mpu_armv7.h │ ├── mpu_armv8.h │ └── tz_context.h └── LICENSE.txt ├── LICENSE ├── README.md ├── src ├── microseconds.h ├── microseconds_common.c ├── microseconds_cortexm_systick.c └── microseconds_imxrt_pit.c └── test ├── pit_imxrt1011 ├── MIMXRT1011.h ├── MIMXRT1011_features.h ├── MIMXRT1011xxxxx_flexspi_nor.icf ├── MIMXRT1011xxxxx_ram.icf ├── fsl_clock.h ├── fsl_common.h ├── fsl_device_registers.h ├── main.c ├── microseconds_demo.ewd ├── microseconds_demo.ewp ├── microseconds_demo.eww ├── startup_MIMXRT1011.s ├── system_MIMXRT1011.c └── system_MIMXRT1011.h └── systick_imxrt1011 ├── MIMXRT1011.h ├── MIMXRT1011_features.h ├── MIMXRT1011xxxxx_flexspi_nor.icf ├── MIMXRT1011xxxxx_ram.icf ├── fsl_device_registers.h ├── main.c ├── microseconds_demo.ewd ├── microseconds_demo.ewp ├── microseconds_demo.eww ├── startup_MIMXRT1011.s ├── system_MIMXRT1011.c └── system_MIMXRT1011.h /.gitignore: -------------------------------------------------------------------------------- 1 | # Object files 2 | *.o 3 | *.obj 4 | *.elf 5 | 6 | # Linker output 7 | *.map 8 | *.exp 9 | 10 | # Libraries 11 | *.lib 12 | *.a 13 | *.la 14 | *.lo 15 | 16 | # Executables 17 | *.exe 18 | *.out 19 | *.hex 20 | 21 | # IAR files 22 | *.dep 23 | *.ewt 24 | /test/*/settings 25 | /test/*/Debug 26 | /test/*/Release 27 | 28 | -------------------------------------------------------------------------------- /CMSIS/Include/arm_common_tables.h: -------------------------------------------------------------------------------- 1 | /* ---------------------------------------------------------------------- 2 | * Project: CMSIS DSP Library 3 | * Title: arm_common_tables.h 4 | * Description: Extern declaration for common tables 5 | * 6 | * $Date: 27. January 2017 7 | * $Revision: V.1.5.1 8 | * 9 | * Target Processor: Cortex-M cores 10 | * -------------------------------------------------------------------- */ 11 | /* 12 | * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. 13 | * 14 | * SPDX-License-Identifier: Apache-2.0 15 | * 16 | * Licensed under the Apache License, Version 2.0 (the License); you may 17 | * not use this file except in compliance with the License. 18 | * You may obtain a copy of the License at 19 | * 20 | * www.apache.org/licenses/LICENSE-2.0 21 | * 22 | * Unless required by applicable law or agreed to in writing, software 23 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 24 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 | * See the License for the specific language governing permissions and 26 | * limitations under the License. 27 | */ 28 | 29 | #ifndef _ARM_COMMON_TABLES_H 30 | #define _ARM_COMMON_TABLES_H 31 | 32 | #include "arm_math.h" 33 | 34 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) 35 | 36 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) 37 | extern const uint16_t armBitRevTable[1024]; 38 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 39 | 40 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) 41 | extern const float32_t twiddleCoef_16[32]; 42 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 43 | 44 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) 45 | extern const float32_t twiddleCoef_32[64]; 46 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 47 | 48 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) 49 | extern const float32_t twiddleCoef_64[128]; 50 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 51 | 52 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) 53 | extern const float32_t twiddleCoef_128[256]; 54 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 55 | 56 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) 57 | extern const float32_t twiddleCoef_256[512]; 58 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 59 | 60 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) 61 | extern const float32_t twiddleCoef_512[1024]; 62 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 63 | 64 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) 65 | extern const float32_t twiddleCoef_1024[2048]; 66 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 67 | 68 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) 69 | extern const float32_t twiddleCoef_2048[4096]; 70 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 71 | 72 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) 73 | extern const float32_t twiddleCoef_4096[8192]; 74 | #define twiddleCoef twiddleCoef_4096 75 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 76 | 77 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) 78 | extern const q31_t twiddleCoef_16_q31[24]; 79 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 80 | 81 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) 82 | extern const q31_t twiddleCoef_32_q31[48]; 83 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 84 | 85 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) 86 | extern const q31_t twiddleCoef_64_q31[96]; 87 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 88 | 89 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) 90 | extern const q31_t twiddleCoef_128_q31[192]; 91 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 92 | 93 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) 94 | extern const q31_t twiddleCoef_256_q31[384]; 95 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 96 | 97 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) 98 | extern const q31_t twiddleCoef_512_q31[768]; 99 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 100 | 101 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) 102 | extern const q31_t twiddleCoef_1024_q31[1536]; 103 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 104 | 105 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) 106 | extern const q31_t twiddleCoef_2048_q31[3072]; 107 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 108 | 109 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) 110 | extern const q31_t twiddleCoef_4096_q31[6144]; 111 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 112 | 113 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) 114 | extern const q15_t twiddleCoef_16_q15[24]; 115 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 116 | 117 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) 118 | extern const q15_t twiddleCoef_32_q15[48]; 119 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 120 | 121 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) 122 | extern const q15_t twiddleCoef_64_q15[96]; 123 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 124 | 125 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) 126 | extern const q15_t twiddleCoef_128_q15[192]; 127 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 128 | 129 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) 130 | extern const q15_t twiddleCoef_256_q15[384]; 131 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 132 | 133 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) 134 | extern const q15_t twiddleCoef_512_q15[768]; 135 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 136 | 137 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) 138 | extern const q15_t twiddleCoef_1024_q15[1536]; 139 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 140 | 141 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) 142 | extern const q15_t twiddleCoef_2048_q15[3072]; 143 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 144 | 145 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) 146 | extern const q15_t twiddleCoef_4096_q15[6144]; 147 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 148 | 149 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) 150 | extern const float32_t twiddleCoef_rfft_32[32]; 151 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 152 | 153 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) 154 | extern const float32_t twiddleCoef_rfft_64[64]; 155 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 156 | 157 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) 158 | extern const float32_t twiddleCoef_rfft_128[128]; 159 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 160 | 161 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) 162 | extern const float32_t twiddleCoef_rfft_256[256]; 163 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 164 | 165 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) 166 | extern const float32_t twiddleCoef_rfft_512[512]; 167 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 168 | 169 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) 170 | extern const float32_t twiddleCoef_rfft_1024[1024]; 171 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 172 | 173 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) 174 | extern const float32_t twiddleCoef_rfft_2048[2048]; 175 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 176 | 177 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096) 178 | extern const float32_t twiddleCoef_rfft_4096[4096]; 179 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 180 | 181 | /* floating-point bit reversal tables */ 182 | 183 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) 184 | #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) 185 | extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; 186 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 187 | 188 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) 189 | #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) 190 | extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; 191 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 192 | 193 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) 194 | #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) 195 | extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; 196 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 197 | 198 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) 199 | #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) 200 | extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; 201 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 202 | 203 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) 204 | #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) 205 | extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; 206 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 207 | 208 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) 209 | #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) 210 | extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; 211 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 212 | 213 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) 214 | #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) 215 | extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; 216 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 217 | 218 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) 219 | #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) 220 | extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; 221 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 222 | 223 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) 224 | #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) 225 | extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; 226 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 227 | 228 | 229 | /* fixed-point bit reversal tables */ 230 | 231 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) 232 | #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) 233 | extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; 234 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 235 | 236 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) 237 | #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) 238 | extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; 239 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 240 | 241 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) 242 | #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) 243 | extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; 244 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 245 | 246 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) 247 | #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) 248 | extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; 249 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 250 | 251 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) 252 | #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) 253 | extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; 254 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 255 | 256 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) 257 | #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) 258 | extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; 259 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 260 | 261 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) 262 | #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) 263 | extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; 264 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 265 | 266 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) 267 | #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) 268 | extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; 269 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 270 | 271 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) 272 | #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) 273 | extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; 274 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ 275 | 276 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) 277 | extern const float32_t realCoefA[8192]; 278 | extern const float32_t realCoefB[8192]; 279 | #endif 280 | 281 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) 282 | extern const q31_t realCoefAQ31[8192]; 283 | extern const q31_t realCoefBQ31[8192]; 284 | #endif 285 | 286 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) 287 | extern const q15_t realCoefAQ15[8192]; 288 | extern const q15_t realCoefBQ15[8192]; 289 | #endif 290 | 291 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) 292 | extern const float32_t Weights_128[256]; 293 | extern const float32_t cos_factors_128[128]; 294 | #endif 295 | 296 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) 297 | extern const float32_t Weights_512[1024]; 298 | extern const float32_t cos_factors_512[512]; 299 | #endif 300 | 301 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) 302 | extern const float32_t Weights_2048[4096]; 303 | extern const float32_t cos_factors_2048[2048]; 304 | #endif 305 | 306 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) 307 | extern const float32_t Weights_8192[16384]; 308 | extern const float32_t cos_factors_8192[8192]; 309 | #endif 310 | 311 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) 312 | extern const q15_t WeightsQ15_128[256]; 313 | extern const q15_t cos_factorsQ15_128[128]; 314 | #endif 315 | 316 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) 317 | extern const q15_t WeightsQ15_512[1024]; 318 | extern const q15_t cos_factorsQ15_512[512]; 319 | #endif 320 | 321 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) 322 | extern const q15_t WeightsQ15_2048[4096]; 323 | extern const q15_t cos_factorsQ15_2048[2048]; 324 | #endif 325 | 326 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) 327 | extern const q15_t WeightsQ15_8192[16384]; 328 | extern const q15_t cos_factorsQ15_8192[8192]; 329 | #endif 330 | 331 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) 332 | extern const q31_t WeightsQ31_128[256]; 333 | extern const q31_t cos_factorsQ31_128[128]; 334 | #endif 335 | 336 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) 337 | extern const q31_t WeightsQ31_512[1024]; 338 | extern const q31_t cos_factorsQ31_512[512]; 339 | #endif 340 | 341 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) 342 | extern const q31_t WeightsQ31_2048[4096]; 343 | extern const q31_t cos_factorsQ31_2048[2048]; 344 | #endif 345 | 346 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) 347 | extern const q31_t WeightsQ31_8192[16384]; 348 | extern const q31_t cos_factorsQ31_8192[8192]; 349 | #endif 350 | 351 | #endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ 352 | 353 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) 354 | 355 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) 356 | extern const q15_t armRecipTableQ15[64]; 357 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ 358 | 359 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) 360 | extern const q31_t armRecipTableQ31[64]; 361 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ 362 | 363 | /* Tables for Fast Math Sine and Cosine */ 364 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) 365 | extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; 366 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ 367 | 368 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) 369 | extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; 370 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ 371 | 372 | #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) 373 | extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; 374 | #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ 375 | 376 | #endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */ 377 | 378 | #endif /* ARM_COMMON_TABLES_H */ 379 | -------------------------------------------------------------------------------- /CMSIS/Include/arm_const_structs.h: -------------------------------------------------------------------------------- 1 | /* ---------------------------------------------------------------------- 2 | * Project: CMSIS DSP Library 3 | * Title: arm_const_structs.h 4 | * Description: Constant structs that are initialized for user convenience. 5 | * For example, some can be given as arguments to the arm_cfft_f32() function. 6 | * 7 | * $Date: 27. January 2017 8 | * $Revision: V.1.5.1 9 | * 10 | * Target Processor: Cortex-M cores 11 | * -------------------------------------------------------------------- */ 12 | /* 13 | * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. 14 | * 15 | * SPDX-License-Identifier: Apache-2.0 16 | * 17 | * Licensed under the Apache License, Version 2.0 (the License); you may 18 | * not use this file except in compliance with the License. 19 | * You may obtain a copy of the License at 20 | * 21 | * www.apache.org/licenses/LICENSE-2.0 22 | * 23 | * Unless required by applicable law or agreed to in writing, software 24 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 25 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 | * See the License for the specific language governing permissions and 27 | * limitations under the License. 28 | */ 29 | 30 | #ifndef _ARM_CONST_STRUCTS_H 31 | #define _ARM_CONST_STRUCTS_H 32 | 33 | #include "arm_math.h" 34 | #include "arm_common_tables.h" 35 | 36 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; 37 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; 38 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; 39 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; 40 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; 41 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; 42 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; 43 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; 44 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; 45 | 46 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; 47 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; 48 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; 49 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; 50 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; 51 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; 52 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; 53 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; 54 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; 55 | 56 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; 57 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; 58 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; 59 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; 60 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; 61 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; 62 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; 63 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; 64 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; 65 | 66 | #endif 67 | -------------------------------------------------------------------------------- /CMSIS/Include/cmsis_armcc.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_armcc.h 3 | * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file 4 | * @version V5.1.0 5 | * @date 08. May 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_ARMCC_H 26 | #define __CMSIS_ARMCC_H 27 | 28 | 29 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) 30 | #error "Please use Arm Compiler Toolchain V4.0.677 or later!" 31 | #endif 32 | 33 | /* CMSIS compiler control architecture macros */ 34 | #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ 35 | (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) 36 | #define __ARM_ARCH_6M__ 1 37 | #endif 38 | 39 | #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) 40 | #define __ARM_ARCH_7M__ 1 41 | #endif 42 | 43 | #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) 44 | #define __ARM_ARCH_7EM__ 1 45 | #endif 46 | 47 | /* __ARM_ARCH_8M_BASE__ not applicable */ 48 | /* __ARM_ARCH_8M_MAIN__ not applicable */ 49 | 50 | /* CMSIS compiler control DSP macros */ 51 | #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) 52 | #define __ARM_FEATURE_DSP 1 53 | #endif 54 | 55 | /* CMSIS compiler specific defines */ 56 | #ifndef __ASM 57 | #define __ASM __asm 58 | #endif 59 | #ifndef __INLINE 60 | #define __INLINE __inline 61 | #endif 62 | #ifndef __STATIC_INLINE 63 | #define __STATIC_INLINE static __inline 64 | #endif 65 | #ifndef __STATIC_FORCEINLINE 66 | #define __STATIC_FORCEINLINE static __forceinline 67 | #endif 68 | #ifndef __NO_RETURN 69 | #define __NO_RETURN __declspec(noreturn) 70 | #endif 71 | #ifndef __USED 72 | #define __USED __attribute__((used)) 73 | #endif 74 | #ifndef __WEAK 75 | #define __WEAK __attribute__((weak)) 76 | #endif 77 | #ifndef __PACKED 78 | #define __PACKED __attribute__((packed)) 79 | #endif 80 | #ifndef __PACKED_STRUCT 81 | #define __PACKED_STRUCT __packed struct 82 | #endif 83 | #ifndef __PACKED_UNION 84 | #define __PACKED_UNION __packed union 85 | #endif 86 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 87 | #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) 88 | #endif 89 | #ifndef __UNALIGNED_UINT16_WRITE 90 | #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) 91 | #endif 92 | #ifndef __UNALIGNED_UINT16_READ 93 | #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) 94 | #endif 95 | #ifndef __UNALIGNED_UINT32_WRITE 96 | #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) 97 | #endif 98 | #ifndef __UNALIGNED_UINT32_READ 99 | #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) 100 | #endif 101 | #ifndef __ALIGNED 102 | #define __ALIGNED(x) __attribute__((aligned(x))) 103 | #endif 104 | #ifndef __RESTRICT 105 | #define __RESTRICT __restrict 106 | #endif 107 | #ifndef __COMPILER_BARRIER 108 | #define __COMPILER_BARRIER() __memory_changed() 109 | #endif 110 | 111 | /* ######################### Startup and Lowlevel Init ######################## */ 112 | 113 | #ifndef __PROGRAM_START 114 | #define __PROGRAM_START __main 115 | #endif 116 | 117 | #ifndef __INITIAL_SP 118 | #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit 119 | #endif 120 | 121 | #ifndef __STACK_LIMIT 122 | #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base 123 | #endif 124 | 125 | #ifndef __VECTOR_TABLE 126 | #define __VECTOR_TABLE __Vectors 127 | #endif 128 | 129 | #ifndef __VECTOR_TABLE_ATTRIBUTE 130 | #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) 131 | #endif 132 | 133 | /* ########################### Core Function Access ########################### */ 134 | /** \ingroup CMSIS_Core_FunctionInterface 135 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 136 | @{ 137 | */ 138 | 139 | /** 140 | \brief Enable IRQ Interrupts 141 | \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 142 | Can only be executed in Privileged modes. 143 | */ 144 | /* intrinsic void __enable_irq(); */ 145 | 146 | 147 | /** 148 | \brief Disable IRQ Interrupts 149 | \details Disables IRQ interrupts by setting the I-bit in the CPSR. 150 | Can only be executed in Privileged modes. 151 | */ 152 | /* intrinsic void __disable_irq(); */ 153 | 154 | /** 155 | \brief Get Control Register 156 | \details Returns the content of the Control Register. 157 | \return Control Register value 158 | */ 159 | __STATIC_INLINE uint32_t __get_CONTROL(void) 160 | { 161 | register uint32_t __regControl __ASM("control"); 162 | return(__regControl); 163 | } 164 | 165 | 166 | /** 167 | \brief Set Control Register 168 | \details Writes the given value to the Control Register. 169 | \param [in] control Control Register value to set 170 | */ 171 | __STATIC_INLINE void __set_CONTROL(uint32_t control) 172 | { 173 | register uint32_t __regControl __ASM("control"); 174 | __regControl = control; 175 | } 176 | 177 | 178 | /** 179 | \brief Get IPSR Register 180 | \details Returns the content of the IPSR Register. 181 | \return IPSR Register value 182 | */ 183 | __STATIC_INLINE uint32_t __get_IPSR(void) 184 | { 185 | register uint32_t __regIPSR __ASM("ipsr"); 186 | return(__regIPSR); 187 | } 188 | 189 | 190 | /** 191 | \brief Get APSR Register 192 | \details Returns the content of the APSR Register. 193 | \return APSR Register value 194 | */ 195 | __STATIC_INLINE uint32_t __get_APSR(void) 196 | { 197 | register uint32_t __regAPSR __ASM("apsr"); 198 | return(__regAPSR); 199 | } 200 | 201 | 202 | /** 203 | \brief Get xPSR Register 204 | \details Returns the content of the xPSR Register. 205 | \return xPSR Register value 206 | */ 207 | __STATIC_INLINE uint32_t __get_xPSR(void) 208 | { 209 | register uint32_t __regXPSR __ASM("xpsr"); 210 | return(__regXPSR); 211 | } 212 | 213 | 214 | /** 215 | \brief Get Process Stack Pointer 216 | \details Returns the current value of the Process Stack Pointer (PSP). 217 | \return PSP Register value 218 | */ 219 | __STATIC_INLINE uint32_t __get_PSP(void) 220 | { 221 | register uint32_t __regProcessStackPointer __ASM("psp"); 222 | return(__regProcessStackPointer); 223 | } 224 | 225 | 226 | /** 227 | \brief Set Process Stack Pointer 228 | \details Assigns the given value to the Process Stack Pointer (PSP). 229 | \param [in] topOfProcStack Process Stack Pointer value to set 230 | */ 231 | __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) 232 | { 233 | register uint32_t __regProcessStackPointer __ASM("psp"); 234 | __regProcessStackPointer = topOfProcStack; 235 | } 236 | 237 | 238 | /** 239 | \brief Get Main Stack Pointer 240 | \details Returns the current value of the Main Stack Pointer (MSP). 241 | \return MSP Register value 242 | */ 243 | __STATIC_INLINE uint32_t __get_MSP(void) 244 | { 245 | register uint32_t __regMainStackPointer __ASM("msp"); 246 | return(__regMainStackPointer); 247 | } 248 | 249 | 250 | /** 251 | \brief Set Main Stack Pointer 252 | \details Assigns the given value to the Main Stack Pointer (MSP). 253 | \param [in] topOfMainStack Main Stack Pointer value to set 254 | */ 255 | __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) 256 | { 257 | register uint32_t __regMainStackPointer __ASM("msp"); 258 | __regMainStackPointer = topOfMainStack; 259 | } 260 | 261 | 262 | /** 263 | \brief Get Priority Mask 264 | \details Returns the current state of the priority mask bit from the Priority Mask Register. 265 | \return Priority Mask value 266 | */ 267 | __STATIC_INLINE uint32_t __get_PRIMASK(void) 268 | { 269 | register uint32_t __regPriMask __ASM("primask"); 270 | return(__regPriMask); 271 | } 272 | 273 | 274 | /** 275 | \brief Set Priority Mask 276 | \details Assigns the given value to the Priority Mask Register. 277 | \param [in] priMask Priority Mask 278 | */ 279 | __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) 280 | { 281 | register uint32_t __regPriMask __ASM("primask"); 282 | __regPriMask = (priMask); 283 | } 284 | 285 | 286 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 287 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) 288 | 289 | /** 290 | \brief Enable FIQ 291 | \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 292 | Can only be executed in Privileged modes. 293 | */ 294 | #define __enable_fault_irq __enable_fiq 295 | 296 | 297 | /** 298 | \brief Disable FIQ 299 | \details Disables FIQ interrupts by setting the F-bit in the CPSR. 300 | Can only be executed in Privileged modes. 301 | */ 302 | #define __disable_fault_irq __disable_fiq 303 | 304 | 305 | /** 306 | \brief Get Base Priority 307 | \details Returns the current value of the Base Priority register. 308 | \return Base Priority register value 309 | */ 310 | __STATIC_INLINE uint32_t __get_BASEPRI(void) 311 | { 312 | register uint32_t __regBasePri __ASM("basepri"); 313 | return(__regBasePri); 314 | } 315 | 316 | 317 | /** 318 | \brief Set Base Priority 319 | \details Assigns the given value to the Base Priority register. 320 | \param [in] basePri Base Priority value to set 321 | */ 322 | __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) 323 | { 324 | register uint32_t __regBasePri __ASM("basepri"); 325 | __regBasePri = (basePri & 0xFFU); 326 | } 327 | 328 | 329 | /** 330 | \brief Set Base Priority with condition 331 | \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, 332 | or the new value increases the BASEPRI priority level. 333 | \param [in] basePri Base Priority value to set 334 | */ 335 | __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) 336 | { 337 | register uint32_t __regBasePriMax __ASM("basepri_max"); 338 | __regBasePriMax = (basePri & 0xFFU); 339 | } 340 | 341 | 342 | /** 343 | \brief Get Fault Mask 344 | \details Returns the current value of the Fault Mask register. 345 | \return Fault Mask register value 346 | */ 347 | __STATIC_INLINE uint32_t __get_FAULTMASK(void) 348 | { 349 | register uint32_t __regFaultMask __ASM("faultmask"); 350 | return(__regFaultMask); 351 | } 352 | 353 | 354 | /** 355 | \brief Set Fault Mask 356 | \details Assigns the given value to the Fault Mask register. 357 | \param [in] faultMask Fault Mask value to set 358 | */ 359 | __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) 360 | { 361 | register uint32_t __regFaultMask __ASM("faultmask"); 362 | __regFaultMask = (faultMask & (uint32_t)1U); 363 | } 364 | 365 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 366 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ 367 | 368 | 369 | /** 370 | \brief Get FPSCR 371 | \details Returns the current value of the Floating Point Status/Control register. 372 | \return Floating Point Status/Control register value 373 | */ 374 | __STATIC_INLINE uint32_t __get_FPSCR(void) 375 | { 376 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 377 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 378 | register uint32_t __regfpscr __ASM("fpscr"); 379 | return(__regfpscr); 380 | #else 381 | return(0U); 382 | #endif 383 | } 384 | 385 | 386 | /** 387 | \brief Set FPSCR 388 | \details Assigns the given value to the Floating Point Status/Control register. 389 | \param [in] fpscr Floating Point Status/Control value to set 390 | */ 391 | __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) 392 | { 393 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 394 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 395 | register uint32_t __regfpscr __ASM("fpscr"); 396 | __regfpscr = (fpscr); 397 | #else 398 | (void)fpscr; 399 | #endif 400 | } 401 | 402 | 403 | /*@} end of CMSIS_Core_RegAccFunctions */ 404 | 405 | 406 | /* ########################## Core Instruction Access ######################### */ 407 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 408 | Access to dedicated instructions 409 | @{ 410 | */ 411 | 412 | /** 413 | \brief No Operation 414 | \details No Operation does nothing. This instruction can be used for code alignment purposes. 415 | */ 416 | #define __NOP __nop 417 | 418 | 419 | /** 420 | \brief Wait For Interrupt 421 | \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. 422 | */ 423 | #define __WFI __wfi 424 | 425 | 426 | /** 427 | \brief Wait For Event 428 | \details Wait For Event is a hint instruction that permits the processor to enter 429 | a low-power state until one of a number of events occurs. 430 | */ 431 | #define __WFE __wfe 432 | 433 | 434 | /** 435 | \brief Send Event 436 | \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 437 | */ 438 | #define __SEV __sev 439 | 440 | 441 | /** 442 | \brief Instruction Synchronization Barrier 443 | \details Instruction Synchronization Barrier flushes the pipeline in the processor, 444 | so that all instructions following the ISB are fetched from cache or memory, 445 | after the instruction has been completed. 446 | */ 447 | #define __ISB() do {\ 448 | __schedule_barrier();\ 449 | __isb(0xF);\ 450 | __schedule_barrier();\ 451 | } while (0U) 452 | 453 | /** 454 | \brief Data Synchronization Barrier 455 | \details Acts as a special kind of Data Memory Barrier. 456 | It completes when all explicit memory accesses before this instruction complete. 457 | */ 458 | #define __DSB() do {\ 459 | __schedule_barrier();\ 460 | __dsb(0xF);\ 461 | __schedule_barrier();\ 462 | } while (0U) 463 | 464 | /** 465 | \brief Data Memory Barrier 466 | \details Ensures the apparent order of the explicit memory operations before 467 | and after the instruction, without ensuring their completion. 468 | */ 469 | #define __DMB() do {\ 470 | __schedule_barrier();\ 471 | __dmb(0xF);\ 472 | __schedule_barrier();\ 473 | } while (0U) 474 | 475 | 476 | /** 477 | \brief Reverse byte order (32 bit) 478 | \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. 479 | \param [in] value Value to reverse 480 | \return Reversed value 481 | */ 482 | #define __REV __rev 483 | 484 | 485 | /** 486 | \brief Reverse byte order (16 bit) 487 | \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. 488 | \param [in] value Value to reverse 489 | \return Reversed value 490 | */ 491 | #ifndef __NO_EMBEDDED_ASM 492 | __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) 493 | { 494 | rev16 r0, r0 495 | bx lr 496 | } 497 | #endif 498 | 499 | 500 | /** 501 | \brief Reverse byte order (16 bit) 502 | \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. 503 | \param [in] value Value to reverse 504 | \return Reversed value 505 | */ 506 | #ifndef __NO_EMBEDDED_ASM 507 | __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) 508 | { 509 | revsh r0, r0 510 | bx lr 511 | } 512 | #endif 513 | 514 | 515 | /** 516 | \brief Rotate Right in unsigned value (32 bit) 517 | \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. 518 | \param [in] op1 Value to rotate 519 | \param [in] op2 Number of Bits to rotate 520 | \return Rotated value 521 | */ 522 | #define __ROR __ror 523 | 524 | 525 | /** 526 | \brief Breakpoint 527 | \details Causes the processor to enter Debug state. 528 | Debug tools can use this to investigate system state when the instruction at a particular address is reached. 529 | \param [in] value is ignored by the processor. 530 | If required, a debugger can use it to store additional information about the breakpoint. 531 | */ 532 | #define __BKPT(value) __breakpoint(value) 533 | 534 | 535 | /** 536 | \brief Reverse bit order of value 537 | \details Reverses the bit order of the given value. 538 | \param [in] value Value to reverse 539 | \return Reversed value 540 | */ 541 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 542 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) 543 | #define __RBIT __rbit 544 | #else 545 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) 546 | { 547 | uint32_t result; 548 | uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 549 | 550 | result = value; /* r will be reversed bits of v; first get LSB of v */ 551 | for (value >>= 1U; value != 0U; value >>= 1U) 552 | { 553 | result <<= 1U; 554 | result |= value & 1U; 555 | s--; 556 | } 557 | result <<= s; /* shift when v's highest bits are zero */ 558 | return result; 559 | } 560 | #endif 561 | 562 | 563 | /** 564 | \brief Count leading zeros 565 | \details Counts the number of leading zeros of a data value. 566 | \param [in] value Value to count the leading zeros 567 | \return number of leading zeros in value 568 | */ 569 | #define __CLZ __clz 570 | 571 | 572 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 573 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) 574 | 575 | /** 576 | \brief LDR Exclusive (8 bit) 577 | \details Executes a exclusive LDR instruction for 8 bit value. 578 | \param [in] ptr Pointer to data 579 | \return value of type uint8_t at (*ptr) 580 | */ 581 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 582 | #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) 583 | #else 584 | #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") 585 | #endif 586 | 587 | 588 | /** 589 | \brief LDR Exclusive (16 bit) 590 | \details Executes a exclusive LDR instruction for 16 bit values. 591 | \param [in] ptr Pointer to data 592 | \return value of type uint16_t at (*ptr) 593 | */ 594 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 595 | #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) 596 | #else 597 | #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") 598 | #endif 599 | 600 | 601 | /** 602 | \brief LDR Exclusive (32 bit) 603 | \details Executes a exclusive LDR instruction for 32 bit values. 604 | \param [in] ptr Pointer to data 605 | \return value of type uint32_t at (*ptr) 606 | */ 607 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 608 | #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) 609 | #else 610 | #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") 611 | #endif 612 | 613 | 614 | /** 615 | \brief STR Exclusive (8 bit) 616 | \details Executes a exclusive STR instruction for 8 bit values. 617 | \param [in] value Value to store 618 | \param [in] ptr Pointer to location 619 | \return 0 Function succeeded 620 | \return 1 Function failed 621 | */ 622 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 623 | #define __STREXB(value, ptr) __strex(value, ptr) 624 | #else 625 | #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 626 | #endif 627 | 628 | 629 | /** 630 | \brief STR Exclusive (16 bit) 631 | \details Executes a exclusive STR instruction for 16 bit values. 632 | \param [in] value Value to store 633 | \param [in] ptr Pointer to location 634 | \return 0 Function succeeded 635 | \return 1 Function failed 636 | */ 637 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 638 | #define __STREXH(value, ptr) __strex(value, ptr) 639 | #else 640 | #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 641 | #endif 642 | 643 | 644 | /** 645 | \brief STR Exclusive (32 bit) 646 | \details Executes a exclusive STR instruction for 32 bit values. 647 | \param [in] value Value to store 648 | \param [in] ptr Pointer to location 649 | \return 0 Function succeeded 650 | \return 1 Function failed 651 | */ 652 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 653 | #define __STREXW(value, ptr) __strex(value, ptr) 654 | #else 655 | #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 656 | #endif 657 | 658 | 659 | /** 660 | \brief Remove the exclusive lock 661 | \details Removes the exclusive lock which is created by LDREX. 662 | */ 663 | #define __CLREX __clrex 664 | 665 | 666 | /** 667 | \brief Signed Saturate 668 | \details Saturates a signed value. 669 | \param [in] value Value to be saturated 670 | \param [in] sat Bit position to saturate to (1..32) 671 | \return Saturated value 672 | */ 673 | #define __SSAT __ssat 674 | 675 | 676 | /** 677 | \brief Unsigned Saturate 678 | \details Saturates an unsigned value. 679 | \param [in] value Value to be saturated 680 | \param [in] sat Bit position to saturate to (0..31) 681 | \return Saturated value 682 | */ 683 | #define __USAT __usat 684 | 685 | 686 | /** 687 | \brief Rotate Right with Extend (32 bit) 688 | \details Moves each bit of a bitstring right by one bit. 689 | The carry input is shifted in at the left end of the bitstring. 690 | \param [in] value Value to rotate 691 | \return Rotated value 692 | */ 693 | #ifndef __NO_EMBEDDED_ASM 694 | __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) 695 | { 696 | rrx r0, r0 697 | bx lr 698 | } 699 | #endif 700 | 701 | 702 | /** 703 | \brief LDRT Unprivileged (8 bit) 704 | \details Executes a Unprivileged LDRT instruction for 8 bit value. 705 | \param [in] ptr Pointer to data 706 | \return value of type uint8_t at (*ptr) 707 | */ 708 | #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) 709 | 710 | 711 | /** 712 | \brief LDRT Unprivileged (16 bit) 713 | \details Executes a Unprivileged LDRT instruction for 16 bit values. 714 | \param [in] ptr Pointer to data 715 | \return value of type uint16_t at (*ptr) 716 | */ 717 | #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) 718 | 719 | 720 | /** 721 | \brief LDRT Unprivileged (32 bit) 722 | \details Executes a Unprivileged LDRT instruction for 32 bit values. 723 | \param [in] ptr Pointer to data 724 | \return value of type uint32_t at (*ptr) 725 | */ 726 | #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) 727 | 728 | 729 | /** 730 | \brief STRT Unprivileged (8 bit) 731 | \details Executes a Unprivileged STRT instruction for 8 bit values. 732 | \param [in] value Value to store 733 | \param [in] ptr Pointer to location 734 | */ 735 | #define __STRBT(value, ptr) __strt(value, ptr) 736 | 737 | 738 | /** 739 | \brief STRT Unprivileged (16 bit) 740 | \details Executes a Unprivileged STRT instruction for 16 bit values. 741 | \param [in] value Value to store 742 | \param [in] ptr Pointer to location 743 | */ 744 | #define __STRHT(value, ptr) __strt(value, ptr) 745 | 746 | 747 | /** 748 | \brief STRT Unprivileged (32 bit) 749 | \details Executes a Unprivileged STRT instruction for 32 bit values. 750 | \param [in] value Value to store 751 | \param [in] ptr Pointer to location 752 | */ 753 | #define __STRT(value, ptr) __strt(value, ptr) 754 | 755 | #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 756 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ 757 | 758 | /** 759 | \brief Signed Saturate 760 | \details Saturates a signed value. 761 | \param [in] value Value to be saturated 762 | \param [in] sat Bit position to saturate to (1..32) 763 | \return Saturated value 764 | */ 765 | __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) 766 | { 767 | if ((sat >= 1U) && (sat <= 32U)) 768 | { 769 | const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); 770 | const int32_t min = -1 - max ; 771 | if (val > max) 772 | { 773 | return max; 774 | } 775 | else if (val < min) 776 | { 777 | return min; 778 | } 779 | } 780 | return val; 781 | } 782 | 783 | /** 784 | \brief Unsigned Saturate 785 | \details Saturates an unsigned value. 786 | \param [in] value Value to be saturated 787 | \param [in] sat Bit position to saturate to (0..31) 788 | \return Saturated value 789 | */ 790 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) 791 | { 792 | if (sat <= 31U) 793 | { 794 | const uint32_t max = ((1U << sat) - 1U); 795 | if (val > (int32_t)max) 796 | { 797 | return max; 798 | } 799 | else if (val < 0) 800 | { 801 | return 0U; 802 | } 803 | } 804 | return (uint32_t)val; 805 | } 806 | 807 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 808 | (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ 809 | 810 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ 811 | 812 | 813 | /* ################### Compiler specific Intrinsics ########################### */ 814 | /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics 815 | Access to dedicated SIMD instructions 816 | @{ 817 | */ 818 | 819 | #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) 820 | 821 | #define __SADD8 __sadd8 822 | #define __QADD8 __qadd8 823 | #define __SHADD8 __shadd8 824 | #define __UADD8 __uadd8 825 | #define __UQADD8 __uqadd8 826 | #define __UHADD8 __uhadd8 827 | #define __SSUB8 __ssub8 828 | #define __QSUB8 __qsub8 829 | #define __SHSUB8 __shsub8 830 | #define __USUB8 __usub8 831 | #define __UQSUB8 __uqsub8 832 | #define __UHSUB8 __uhsub8 833 | #define __SADD16 __sadd16 834 | #define __QADD16 __qadd16 835 | #define __SHADD16 __shadd16 836 | #define __UADD16 __uadd16 837 | #define __UQADD16 __uqadd16 838 | #define __UHADD16 __uhadd16 839 | #define __SSUB16 __ssub16 840 | #define __QSUB16 __qsub16 841 | #define __SHSUB16 __shsub16 842 | #define __USUB16 __usub16 843 | #define __UQSUB16 __uqsub16 844 | #define __UHSUB16 __uhsub16 845 | #define __SASX __sasx 846 | #define __QASX __qasx 847 | #define __SHASX __shasx 848 | #define __UASX __uasx 849 | #define __UQASX __uqasx 850 | #define __UHASX __uhasx 851 | #define __SSAX __ssax 852 | #define __QSAX __qsax 853 | #define __SHSAX __shsax 854 | #define __USAX __usax 855 | #define __UQSAX __uqsax 856 | #define __UHSAX __uhsax 857 | #define __USAD8 __usad8 858 | #define __USADA8 __usada8 859 | #define __SSAT16 __ssat16 860 | #define __USAT16 __usat16 861 | #define __UXTB16 __uxtb16 862 | #define __UXTAB16 __uxtab16 863 | #define __SXTB16 __sxtb16 864 | #define __SXTAB16 __sxtab16 865 | #define __SMUAD __smuad 866 | #define __SMUADX __smuadx 867 | #define __SMLAD __smlad 868 | #define __SMLADX __smladx 869 | #define __SMLALD __smlald 870 | #define __SMLALDX __smlaldx 871 | #define __SMUSD __smusd 872 | #define __SMUSDX __smusdx 873 | #define __SMLSD __smlsd 874 | #define __SMLSDX __smlsdx 875 | #define __SMLSLD __smlsld 876 | #define __SMLSLDX __smlsldx 877 | #define __SEL __sel 878 | #define __QADD __qadd 879 | #define __QSUB __qsub 880 | 881 | #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ 882 | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) 883 | 884 | #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ 885 | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) 886 | 887 | #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ 888 | ((int64_t)(ARG3) << 32U) ) >> 32U)) 889 | 890 | #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ 891 | /*@} end of group CMSIS_SIMD_intrinsics */ 892 | 893 | 894 | #endif /* __CMSIS_ARMCC_H */ 895 | -------------------------------------------------------------------------------- /CMSIS/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_compiler.h 3 | * @brief CMSIS compiler generic header file 4 | * @version V5.1.0 5 | * @date 09. October 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_COMPILER_H 26 | #define __CMSIS_COMPILER_H 27 | 28 | #include 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6.6 LTM (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) 41 | #include "cmsis_armclang_ltm.h" 42 | 43 | /* 44 | * Arm Compiler above 6.10.1 (armclang) 45 | */ 46 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) 47 | #include "cmsis_armclang.h" 48 | 49 | 50 | /* 51 | * GNU Compiler 52 | */ 53 | #elif defined ( __GNUC__ ) 54 | #include "cmsis_gcc.h" 55 | 56 | 57 | /* 58 | * IAR Compiler 59 | */ 60 | #elif defined ( __ICCARM__ ) 61 | #include 62 | 63 | 64 | /* 65 | * TI Arm Compiler 66 | */ 67 | #elif defined ( __TI_ARM__ ) 68 | #include 69 | 70 | #ifndef __ASM 71 | #define __ASM __asm 72 | #endif 73 | #ifndef __INLINE 74 | #define __INLINE inline 75 | #endif 76 | #ifndef __STATIC_INLINE 77 | #define __STATIC_INLINE static inline 78 | #endif 79 | #ifndef __STATIC_FORCEINLINE 80 | #define __STATIC_FORCEINLINE __STATIC_INLINE 81 | #endif 82 | #ifndef __NO_RETURN 83 | #define __NO_RETURN __attribute__((noreturn)) 84 | #endif 85 | #ifndef __USED 86 | #define __USED __attribute__((used)) 87 | #endif 88 | #ifndef __WEAK 89 | #define __WEAK __attribute__((weak)) 90 | #endif 91 | #ifndef __PACKED 92 | #define __PACKED __attribute__((packed)) 93 | #endif 94 | #ifndef __PACKED_STRUCT 95 | #define __PACKED_STRUCT struct __attribute__((packed)) 96 | #endif 97 | #ifndef __PACKED_UNION 98 | #define __PACKED_UNION union __attribute__((packed)) 99 | #endif 100 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 101 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 102 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 103 | #endif 104 | #ifndef __UNALIGNED_UINT16_WRITE 105 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 106 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 107 | #endif 108 | #ifndef __UNALIGNED_UINT16_READ 109 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 110 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 111 | #endif 112 | #ifndef __UNALIGNED_UINT32_WRITE 113 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 114 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 115 | #endif 116 | #ifndef __UNALIGNED_UINT32_READ 117 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 118 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 119 | #endif 120 | #ifndef __ALIGNED 121 | #define __ALIGNED(x) __attribute__((aligned(x))) 122 | #endif 123 | #ifndef __RESTRICT 124 | #define __RESTRICT __restrict 125 | #endif 126 | #ifndef __COMPILER_BARRIER 127 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 128 | #define __COMPILER_BARRIER() (void)0 129 | #endif 130 | 131 | 132 | /* 133 | * TASKING Compiler 134 | */ 135 | #elif defined ( __TASKING__ ) 136 | /* 137 | * The CMSIS functions have been implemented as intrinsics in the compiler. 138 | * Please use "carm -?i" to get an up to date list of all intrinsics, 139 | * Including the CMSIS ones. 140 | */ 141 | 142 | #ifndef __ASM 143 | #define __ASM __asm 144 | #endif 145 | #ifndef __INLINE 146 | #define __INLINE inline 147 | #endif 148 | #ifndef __STATIC_INLINE 149 | #define __STATIC_INLINE static inline 150 | #endif 151 | #ifndef __STATIC_FORCEINLINE 152 | #define __STATIC_FORCEINLINE __STATIC_INLINE 153 | #endif 154 | #ifndef __NO_RETURN 155 | #define __NO_RETURN __attribute__((noreturn)) 156 | #endif 157 | #ifndef __USED 158 | #define __USED __attribute__((used)) 159 | #endif 160 | #ifndef __WEAK 161 | #define __WEAK __attribute__((weak)) 162 | #endif 163 | #ifndef __PACKED 164 | #define __PACKED __packed__ 165 | #endif 166 | #ifndef __PACKED_STRUCT 167 | #define __PACKED_STRUCT struct __packed__ 168 | #endif 169 | #ifndef __PACKED_UNION 170 | #define __PACKED_UNION union __packed__ 171 | #endif 172 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 173 | struct __packed__ T_UINT32 { uint32_t v; }; 174 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 175 | #endif 176 | #ifndef __UNALIGNED_UINT16_WRITE 177 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 178 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 179 | #endif 180 | #ifndef __UNALIGNED_UINT16_READ 181 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 182 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 183 | #endif 184 | #ifndef __UNALIGNED_UINT32_WRITE 185 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 186 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 187 | #endif 188 | #ifndef __UNALIGNED_UINT32_READ 189 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 190 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 191 | #endif 192 | #ifndef __ALIGNED 193 | #define __ALIGNED(x) __align(x) 194 | #endif 195 | #ifndef __RESTRICT 196 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 197 | #define __RESTRICT 198 | #endif 199 | #ifndef __COMPILER_BARRIER 200 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 201 | #define __COMPILER_BARRIER() (void)0 202 | #endif 203 | 204 | 205 | /* 206 | * COSMIC Compiler 207 | */ 208 | #elif defined ( __CSMC__ ) 209 | #include 210 | 211 | #ifndef __ASM 212 | #define __ASM _asm 213 | #endif 214 | #ifndef __INLINE 215 | #define __INLINE inline 216 | #endif 217 | #ifndef __STATIC_INLINE 218 | #define __STATIC_INLINE static inline 219 | #endif 220 | #ifndef __STATIC_FORCEINLINE 221 | #define __STATIC_FORCEINLINE __STATIC_INLINE 222 | #endif 223 | #ifndef __NO_RETURN 224 | // NO RETURN is automatically detected hence no warning here 225 | #define __NO_RETURN 226 | #endif 227 | #ifndef __USED 228 | #warning No compiler specific solution for __USED. __USED is ignored. 229 | #define __USED 230 | #endif 231 | #ifndef __WEAK 232 | #define __WEAK __weak 233 | #endif 234 | #ifndef __PACKED 235 | #define __PACKED @packed 236 | #endif 237 | #ifndef __PACKED_STRUCT 238 | #define __PACKED_STRUCT @packed struct 239 | #endif 240 | #ifndef __PACKED_UNION 241 | #define __PACKED_UNION @packed union 242 | #endif 243 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 244 | @packed struct T_UINT32 { uint32_t v; }; 245 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 246 | #endif 247 | #ifndef __UNALIGNED_UINT16_WRITE 248 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 249 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 250 | #endif 251 | #ifndef __UNALIGNED_UINT16_READ 252 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 253 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 254 | #endif 255 | #ifndef __UNALIGNED_UINT32_WRITE 256 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 257 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 258 | #endif 259 | #ifndef __UNALIGNED_UINT32_READ 260 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 261 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 262 | #endif 263 | #ifndef __ALIGNED 264 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 265 | #define __ALIGNED(x) 266 | #endif 267 | #ifndef __RESTRICT 268 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 269 | #define __RESTRICT 270 | #endif 271 | #ifndef __COMPILER_BARRIER 272 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 273 | #define __COMPILER_BARRIER() (void)0 274 | #endif 275 | 276 | 277 | #else 278 | #error Unknown compiler. 279 | #endif 280 | 281 | 282 | #endif /* __CMSIS_COMPILER_H */ 283 | 284 | -------------------------------------------------------------------------------- /CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.3 5 | * @date 24. June 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2019 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /CMSIS/Include/core_dsp.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_xcc.h 3 | * @brief CMSIS DSP Core Peripheral Access Layer Header File 4 | * @version V1.0 5 | * @date 20. January 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2019 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CORE_DSP_H_GENERIC 26 | #define __CORE_DSP_H_GENERIC 27 | 28 | #include 29 | 30 | #ifdef __cplusplus 31 | extern "C" { 32 | #endif 33 | 34 | /* IO definitions (access restrictions to peripheral registers) */ 35 | /** 36 | \defgroup CMSIS_glob_defs CMSIS Global Defines 37 | 38 | IO Type Qualifiers are used 39 | \li to specify the access to peripheral variables. 40 | \li for automatic generation of peripheral register debug information. 41 | */ 42 | #ifdef __cplusplus 43 | #define __I volatile /*!< Defines 'read only' permissions */ 44 | #else 45 | #define __I volatile const /*!< Defines 'read only' permissions */ 46 | #endif 47 | #define __O volatile /*!< Defines 'write only' permissions */ 48 | #define __IO volatile /*!< Defines 'read / write' permissions */ 49 | 50 | /* following defines should be used for structure members */ 51 | #define __IM volatile const /*! Defines 'read only' structure member permissions */ 52 | #define __OM volatile /*! Defines 'write only' structure member permissions */ 53 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 54 | 55 | #define __STATIC_INLINE static inline 56 | 57 | #define __BKPT(value) do {} while(0) 58 | #define __NOP() do {} while(0) 59 | 60 | #define NVIC_SetPriorityGrouping(value) do {} while(0) 61 | #define NVIC_GetPriorityGrouping() do {} while(0) 62 | #define NVIC_EnableIRQ(value) do {} while(0) 63 | #define NVIC_GetEnableIRQ(value) do {} while(0) 64 | #define NVIC_DisableIRQ(value) do {} while(0) 65 | #define NVIC_GetPendingIRQ(value) do {} while(0) 66 | #define NVIC_SetPendingIRQ(value) do {} while(0) 67 | #define NVIC_ClearPendingIRQ(value) do {} while(0) 68 | #define NVIC_GetActive(value) do {} while(0) 69 | 70 | #ifdef __cplusplus 71 | } 72 | #endif 73 | 74 | #endif /* __CORE_DSP_H_GENERIC */ 75 | -------------------------------------------------------------------------------- /CMSIS/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.1.0 5 | * @date 08. March 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2019 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ 78 | (MPU_RBAR_VALID_Msk)) 79 | 80 | /** 81 | * MPU Memory Access Attributes 82 | * 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 84 | * \param IsShareable Region is shareable between multiple bus masters. 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 87 | */ 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 | ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 | (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 | (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 | (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 93 | 94 | /** 95 | * MPU Region Attribute and Size Register Value 96 | * 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. 100 | * \param SubRegionDisable Sub-region disable field. 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. 102 | */ 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 | (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ 107 | (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ 108 | (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ 109 | (((MPU_RASR_ENABLE_Msk)))) 110 | 111 | /** 112 | * MPU Region Attribute and Size Register Value 113 | * 114 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 115 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 116 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 117 | * \param IsShareable Region is shareable between multiple bus masters. 118 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 119 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 120 | * \param SubRegionDisable Sub-region disable field. 121 | * \param Size Region size of the region to be configured, for example 4K, 8K. 122 | */ 123 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 124 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 125 | 126 | /** 127 | * MPU Memory Access Attribute for strongly ordered memory. 128 | * - TEX: 000b 129 | * - Shareable 130 | * - Non-cacheable 131 | * - Non-bufferable 132 | */ 133 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 134 | 135 | /** 136 | * MPU Memory Access Attribute for device memory. 137 | * - TEX: 000b (if shareable) or 010b (if non-shareable) 138 | * - Shareable or non-shareable 139 | * - Non-cacheable 140 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 141 | * 142 | * \param IsShareable Configures the device memory as shareable or non-shareable. 143 | */ 144 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 145 | 146 | /** 147 | * MPU Memory Access Attribute for normal memory. 148 | * - TEX: 1BBb (reflecting outer cacheability rules) 149 | * - Shareable or non-shareable 150 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 151 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 152 | * 153 | * \param OuterCp Configures the outer cache policy. 154 | * \param InnerCp Configures the inner cache policy. 155 | * \param IsShareable Configures the memory as shareable or non-shareable. 156 | */ 157 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) 158 | 159 | /** 160 | * MPU Memory Access Attribute non-cacheable policy. 161 | */ 162 | #define ARM_MPU_CACHEP_NOCACHE 0U 163 | 164 | /** 165 | * MPU Memory Access Attribute write-back, write and read allocate policy. 166 | */ 167 | #define ARM_MPU_CACHEP_WB_WRA 1U 168 | 169 | /** 170 | * MPU Memory Access Attribute write-through, no write allocate policy. 171 | */ 172 | #define ARM_MPU_CACHEP_WT_NWA 2U 173 | 174 | /** 175 | * MPU Memory Access Attribute write-back, no write allocate policy. 176 | */ 177 | #define ARM_MPU_CACHEP_WB_NWA 3U 178 | 179 | 180 | /** 181 | * Struct for a single MPU Region 182 | */ 183 | typedef struct { 184 | uint32_t RBAR; //!< The region base address register value (RBAR) 185 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 186 | } ARM_MPU_Region_t; 187 | 188 | /** Enable the MPU. 189 | * \param MPU_Control Default access permissions for unconfigured regions. 190 | */ 191 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 192 | { 193 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 194 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 195 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 196 | #endif 197 | __DSB(); 198 | __ISB(); 199 | } 200 | 201 | /** Disable the MPU. 202 | */ 203 | __STATIC_INLINE void ARM_MPU_Disable(void) 204 | { 205 | __DMB(); 206 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 207 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 208 | #endif 209 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 210 | } 211 | 212 | /** Clear and disable the given MPU region. 213 | * \param rnr Region number to be cleared. 214 | */ 215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 216 | { 217 | MPU->RNR = rnr; 218 | MPU->RASR = 0U; 219 | } 220 | 221 | /** Configure an MPU region. 222 | * \param rbar Value for RBAR register. 223 | * \param rsar Value for RSAR register. 224 | */ 225 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 226 | { 227 | MPU->RBAR = rbar; 228 | MPU->RASR = rasr; 229 | } 230 | 231 | /** Configure the given MPU region. 232 | * \param rnr Region number to be configured. 233 | * \param rbar Value for RBAR register. 234 | * \param rsar Value for RSAR register. 235 | */ 236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 237 | { 238 | MPU->RNR = rnr; 239 | MPU->RBAR = rbar; 240 | MPU->RASR = rasr; 241 | } 242 | 243 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 244 | * \param dst Destination data is copied to. 245 | * \param src Source data is copied from. 246 | * \param len Amount of data words to be copied. 247 | */ 248 | __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 249 | { 250 | uint32_t i; 251 | for (i = 0U; i < len; ++i) 252 | { 253 | dst[i] = src[i]; 254 | } 255 | } 256 | 257 | /** Load the given number of MPU regions from a table. 258 | * \param table Pointer to the MPU configuration table. 259 | * \param cnt Amount of regions to be configured. 260 | */ 261 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 262 | { 263 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 264 | while (cnt > MPU_TYPE_RALIASES) { 265 | ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); 266 | table += MPU_TYPE_RALIASES; 267 | cnt -= MPU_TYPE_RALIASES; 268 | } 269 | ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); 270 | } 271 | 272 | #endif 273 | -------------------------------------------------------------------------------- /CMSIS/Include/mpu_armv8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv8.h 3 | * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU 4 | * @version V5.1.0 5 | * @date 08. March 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2019 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV8_H 32 | #define ARM_MPU_ARMV8_H 33 | 34 | /** \brief Attribute for device memory (outer only) */ 35 | #define ARM_MPU_ATTR_DEVICE ( 0U ) 36 | 37 | /** \brief Attribute for non-cacheable, normal memory */ 38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) 39 | 40 | /** \brief Attribute for normal memory (outer and inner) 41 | * \param NT Non-Transient: Set to 1 for non-transient data. 42 | * \param WB Write-Back: Set to 1 to use write-back update policy. 43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 | */ 46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 | 49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ 50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 51 | 52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 54 | 55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 57 | 58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U) 60 | 61 | /** \brief Memory Attribute 62 | * \param O Outer memory attributes 63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 64 | */ 65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 66 | 67 | /** \brief Normal memory non-shareable */ 68 | #define ARM_MPU_SH_NON (0U) 69 | 70 | /** \brief Normal memory outer shareable */ 71 | #define ARM_MPU_SH_OUTER (2U) 72 | 73 | /** \brief Normal memory inner shareable */ 74 | #define ARM_MPU_SH_INNER (3U) 75 | 76 | /** \brief Memory access permissions 77 | * \param RO Read-Only: Set to 1 for read-only memory. 78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory. 79 | */ 80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 81 | 82 | /** \brief Region Base Address Register value 83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. 84 | * \param SH Defines the Shareability domain for this memory region. 85 | * \param RO Read-Only: Set to 1 for a read-only memory region. 86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. 87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. 88 | */ 89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 90 | ((BASE & MPU_RBAR_BASE_Msk) | \ 91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ 92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ 93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 94 | 95 | /** \brief Region Limit Address Register value 96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 97 | * \param IDX The attribute index to be associated with this memory region. 98 | */ 99 | #define ARM_MPU_RLAR(LIMIT, IDX) \ 100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 102 | (MPU_RLAR_EN_Msk)) 103 | 104 | #if defined(MPU_RLAR_PXN_Pos) 105 | 106 | /** \brief Region Limit Address Register with PXN value 107 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 108 | * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. 109 | * \param IDX The attribute index to be associated with this memory region. 110 | */ 111 | #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ 112 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 113 | ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ 114 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 115 | (MPU_RLAR_EN_Msk)) 116 | 117 | #endif 118 | 119 | /** 120 | * Struct for a single MPU Region 121 | */ 122 | typedef struct { 123 | uint32_t RBAR; /*!< Region Base Address Register value */ 124 | uint32_t RLAR; /*!< Region Limit Address Register value */ 125 | } ARM_MPU_Region_t; 126 | 127 | /** Enable the MPU. 128 | * \param MPU_Control Default access permissions for unconfigured regions. 129 | */ 130 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 131 | { 132 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 133 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 134 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 135 | #endif 136 | __DSB(); 137 | __ISB(); 138 | } 139 | 140 | /** Disable the MPU. 141 | */ 142 | __STATIC_INLINE void ARM_MPU_Disable(void) 143 | { 144 | __DMB(); 145 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 146 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 147 | #endif 148 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 149 | } 150 | 151 | #ifdef MPU_NS 152 | /** Enable the Non-secure MPU. 153 | * \param MPU_Control Default access permissions for unconfigured regions. 154 | */ 155 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 156 | { 157 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 158 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 159 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 160 | #endif 161 | __DSB(); 162 | __ISB(); 163 | } 164 | 165 | /** Disable the Non-secure MPU. 166 | */ 167 | __STATIC_INLINE void ARM_MPU_Disable_NS(void) 168 | { 169 | __DMB(); 170 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 171 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 172 | #endif 173 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 174 | } 175 | #endif 176 | 177 | /** Set the memory attribute encoding to the given MPU. 178 | * \param mpu Pointer to the MPU to be configured. 179 | * \param idx The attribute index to be set [0-7] 180 | * \param attr The attribute value to be set. 181 | */ 182 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 183 | { 184 | const uint8_t reg = idx / 4U; 185 | const uint32_t pos = ((idx % 4U) * 8U); 186 | const uint32_t mask = 0xFFU << pos; 187 | 188 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { 189 | return; // invalid index 190 | } 191 | 192 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 193 | } 194 | 195 | /** Set the memory attribute encoding. 196 | * \param idx The attribute index to be set [0-7] 197 | * \param attr The attribute value to be set. 198 | */ 199 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 200 | { 201 | ARM_MPU_SetMemAttrEx(MPU, idx, attr); 202 | } 203 | 204 | #ifdef MPU_NS 205 | /** Set the memory attribute encoding to the Non-secure MPU. 206 | * \param idx The attribute index to be set [0-7] 207 | * \param attr The attribute value to be set. 208 | */ 209 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 210 | { 211 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 212 | } 213 | #endif 214 | 215 | /** Clear and disable the given MPU region of the given MPU. 216 | * \param mpu Pointer to MPU to be used. 217 | * \param rnr Region number to be cleared. 218 | */ 219 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 220 | { 221 | mpu->RNR = rnr; 222 | mpu->RLAR = 0U; 223 | } 224 | 225 | /** Clear and disable the given MPU region. 226 | * \param rnr Region number to be cleared. 227 | */ 228 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 229 | { 230 | ARM_MPU_ClrRegionEx(MPU, rnr); 231 | } 232 | 233 | #ifdef MPU_NS 234 | /** Clear and disable the given Non-secure MPU region. 235 | * \param rnr Region number to be cleared. 236 | */ 237 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 238 | { 239 | ARM_MPU_ClrRegionEx(MPU_NS, rnr); 240 | } 241 | #endif 242 | 243 | /** Configure the given MPU region of the given MPU. 244 | * \param mpu Pointer to MPU to be used. 245 | * \param rnr Region number to be configured. 246 | * \param rbar Value for RBAR register. 247 | * \param rlar Value for RLAR register. 248 | */ 249 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 250 | { 251 | mpu->RNR = rnr; 252 | mpu->RBAR = rbar; 253 | mpu->RLAR = rlar; 254 | } 255 | 256 | /** Configure the given MPU region. 257 | * \param rnr Region number to be configured. 258 | * \param rbar Value for RBAR register. 259 | * \param rlar Value for RLAR register. 260 | */ 261 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 262 | { 263 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 264 | } 265 | 266 | #ifdef MPU_NS 267 | /** Configure the given Non-secure MPU region. 268 | * \param rnr Region number to be configured. 269 | * \param rbar Value for RBAR register. 270 | * \param rlar Value for RLAR register. 271 | */ 272 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 273 | { 274 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 275 | } 276 | #endif 277 | 278 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 279 | * \param dst Destination data is copied to. 280 | * \param src Source data is copied from. 281 | * \param len Amount of data words to be copied. 282 | */ 283 | __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 284 | { 285 | uint32_t i; 286 | for (i = 0U; i < len; ++i) 287 | { 288 | dst[i] = src[i]; 289 | } 290 | } 291 | 292 | /** Load the given number of MPU regions from a table to the given MPU. 293 | * \param mpu Pointer to the MPU registers to be used. 294 | * \param rnr First region number to be configured. 295 | * \param table Pointer to the MPU configuration table. 296 | * \param cnt Amount of regions to be configured. 297 | */ 298 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 299 | { 300 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 301 | if (cnt == 1U) { 302 | mpu->RNR = rnr; 303 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 304 | } else { 305 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); 306 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 307 | 308 | mpu->RNR = rnrBase; 309 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { 310 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 311 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); 312 | table += c; 313 | cnt -= c; 314 | rnrOffset = 0U; 315 | rnrBase += MPU_TYPE_RALIASES; 316 | mpu->RNR = rnrBase; 317 | } 318 | 319 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); 320 | } 321 | } 322 | 323 | /** Load the given number of MPU regions from a table. 324 | * \param rnr First region number to be configured. 325 | * \param table Pointer to the MPU configuration table. 326 | * \param cnt Amount of regions to be configured. 327 | */ 328 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 329 | { 330 | ARM_MPU_LoadEx(MPU, rnr, table, cnt); 331 | } 332 | 333 | #ifdef MPU_NS 334 | /** Load the given number of MPU regions from a table to the Non-secure MPU. 335 | * \param rnr First region number to be configured. 336 | * \param table Pointer to the MPU configuration table. 337 | * \param cnt Amount of regions to be configured. 338 | */ 339 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 340 | { 341 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 342 | } 343 | #endif 344 | 345 | #endif 346 | 347 | -------------------------------------------------------------------------------- /CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /CMSIS/LICENSE.txt: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | 2. Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | 3. Neither the name of the copyright holder nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # microseconds | MCU通用微秒计时函数框架 2 | 3 | 在嵌入式软件开发里，计时可以说是非常基础的功能模块了，其应用也非常广泛，比如可以辅助计算信号脉冲宽度时间，也可以直接用于常规延时等。相信很多人初次领略 MCU 的神奇都是从计时功能相关小程序开始的。 4 | 5 | 在 MCU 里要想实现精确计时，往往都是利用其内部硬件定时器。不同厂商的 MCU，其定时器设计与使用都不太一样。即使是同一 MCU 内，通常也会有好几种不同类型的定时器共存。基于此，笔者设计了一种非常简单实用的通用计时函数框架，这个框架的目的是统一计时函数接口，并且在实现上将通用部分和硬件相关部分剥离开，这样你的嵌入式项目在使用这个框架时可以无缝快捷地切换底层定时器。 6 | 7 | 注：本框架主要适合定时器时钟源不小于 1MHz 的 MCU，因为函数接口里延时最小单元是 1us。对于一些定时器时钟源低于 1MHz 的 MCU，可将本框架简单改成成毫秒(milliseconds)计时函数。 8 | 9 | ### 一、微秒(microseconds)计时函数库设计 10 | #### 1.1 函数接口定义 11 | 首先是设计通用计时函数框架头文件：microseconds.h ，这个头文件里直接定义如下 7 个接口函数原型。涵盖必备的初始化流程init()、shutdown()，最核心的计时功能get_ticks()、convert_to_microseconds()，常用的延时功能delay()、set_delay()、is_timeout()。 12 | 13 | #### 1.2 通用函数实现 14 | 然后是设计通用计时函数框架共用源文件：microseconds_common.c，这个文件里涉及三个静态全局变量定义，四个私有函数声明，以及除了 get_ticks() 之外的 6 个接口函数实现。 15 | 16 | 其中 s_tickPerMicrosecond 变量存的是每微秒对应计数值，其实这个变量不是一定要定义的，可以在函数需要时实时计算，但为了小小提升框架性能，就在 init() 里将这个值先算出来了，方便其他函数直接使用。 17 | 18 | s_highCounter 变量存的是定时器中断次数，即高位计数器，因为框架 get_ticks() 接口返回的是 64bit 的计数值，对于有些宽度小于 32bit 的定时器，我们常常需要开启定时器中断，否则无法保证系统长时间运行线性计时的正确性（比如 100MHz 时钟源的 32bit 定时器，最长约 43 秒就会清零翻转一次，需要 s_highCounter 变量记录翻转次数）。当然如果 MCU 里能级连出 64bit 的定时器，就可以不用开启中断（清零翻转的时间特别长，可近似认为是永久），s_highCounter 此时就不需要了。 19 | 20 | 关于延时函数接口，delay() 用于阻塞型延时，即调用这个函数后一定是死等指定时间后才退出，系统会被强制挂起；set_delay()/is_timeout()用于非阻塞型延时，系统可以继续干其他任务，在需要的时侯来查看一下超时时间是否到了即可。两种延时各有各的用途。 21 | 22 | ### 二、微秒(microseconds)计时函数库实现 23 | #### 2.1 定时器相关实现（基于Cortex-M内核的SysTick） 24 | 最后是设计 MCU 相关的通用计时函数框架源文件：microseconds_xxTimer.c，这里我们以 Cortex-M 系列 MCU 的内核定时器 SysTick 为例。 25 | 26 | SysTick 是 24bit 递减定时器，时钟源有两种配置：一是内核主频，二是外部时钟（看厂商实现），最常用的时钟源配置就是与内核同频。 27 | 28 | 上一节说了用 SysTick 这类宽度小于 32bit 的定时器，是需要开启定时器中断的，所以 s_highCounter 会生效。get_ticks()是整个计时函数框架里最基础也最核心的功能接口，这里面的实现有一个需要特别注意的地方，就是取系统当前计数值可能会有数值回退的风险，需要使用代码中 do {} while()；方式来确保正确性。 29 | 30 | 当然还有很多具体 MCU 平台的各种定时器实现，因此这个项目会不断更新，也欢迎大家来参与贡献。 31 | -------------------------------------------------------------------------------- /src/microseconds.h: -------------------------------------------------------------------------------- 1 | /* 2 | * SPDX-License-Identifier: BSD-3-Clause 3 | */ 4 | 5 | /* 6 | * @file microseconds.h 7 | * @brief Microseconds timer driver 8 | */ 9 | 10 | #ifndef ___MICROSECONDS_H__ 11 | #define ___MICROSECONDS_H__ 12 | 13 | #include 14 | #include 15 | /******************************************************************************* 16 | * Definitions 17 | ******************************************************************************/ 18 | 19 | /******************************************************************************* 20 | * API 21 | ******************************************************************************/ 22 | 23 | #if defined(__cplusplus) 24 | extern "C" { 25 | #endif // __cplusplus 26 | 27 | /********************************************************************/ 28 | //! @brief Initialize timer facilities. 29 | //! @brief 初始化计时 30 | void microseconds_init(void); 31 | 32 | //! @brief Shutdown the microsecond timer 33 | //! @brief 关闭计时 34 | void microseconds_shutdown(void); 35 | 36 | //! @brief Gets the clock value used for microseconds driver 37 | //! @brief 获取定时器时钟源数值 38 | uint32_t microseconds_get_clock(void); 39 | 40 | //! @brief Read back the running tick count 41 | //! @brief 获取系统累计计数值 42 | uint64_t microseconds_get_ticks(void); 43 | 44 | //! @brief Returns the conversion of ticks to actual microseconds 45 | //! @brief 将计数值转换为时间值(微秒) 46 | uint32_t microseconds_convert_to_microseconds(uint64_t ticks); 47 | 48 | //! @brief Returns the conversion of microseconds to ticks 49 | //! @brief 将时间值(微秒)转换为计数值 50 | uint64_t microseconds_convert_to_ticks(uint32_t microseconds); 51 | 52 | //! @brief Delay specified time 53 | //! @brief 阻塞型延时(微秒级) 54 | void microseconds_delay(uint32_t us); 55 | 56 | //! @brief Set delay time 57 | //! @brief 设置超时时间（用于非阻塞型延时） 58 | void microseconds_set_delay(uint32_t us); 59 | 60 | //! @brief Get timeout flag 61 | //! @brief 判断是否超时（用于非阻塞型延时） 62 | bool microseconds_is_timeout(void); 63 | 64 | #if defined(__cplusplus) 65 | } 66 | #endif // __cplusplus 67 | 68 | #endif /* ___MICROSECONDS_H__ */ 69 | 70 | -------------------------------------------------------------------------------- /src/microseconds_common.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JayHeng/microseconds/1efab5c813b5e1d6cfeb54058e06f01167bfd576/src/microseconds_common.c -------------------------------------------------------------------------------- /src/microseconds_cortexm_systick.c: -------------------------------------------------------------------------------- 1 | /* 2 | * SPDX-License-Identifier: BSD-3-Clause 3 | */ 4 | 5 | /* 6 | * @file microseconds_cortexm_systick.c 7 | * @brief Microseconds systick timer driver source file 8 | * 9 | * Notes: The driver configure systick as lifetime timer 10 | */ 11 | #include "microseconds.h" 12 | #include "assert.h" 13 | #include "fsl_device_registers.h" 14 | /******************************************************************************* 15 | * Definitions 16 | ******************************************************************************/ 17 | 18 | 19 | /******************************************************************************* 20 | * Variables 21 | ******************************************************************************/ 22 | //!< 高位计数器，仅当使能定时器超时中断时有效，用于记录中断累计次数 23 | extern volatile uint32_t s_highCounter; 24 | 25 | /******************************************************************************* 26 | * Prototypes 27 | ******************************************************************************/ 28 | 29 | 30 | /******************************************************************************* 31 | * Code 32 | ******************************************************************************/ 33 | 34 | void microseconds_timer_init(void) 35 | { 36 | // 调用 core_cmx.h 头文件里的初始化函数 37 | // SysTick时钟源为内核时钟，开启中断，重装值为 0xFFFFFF 38 | SysTick_Config(SysTick_LOAD_RELOAD_Msk + 1); 39 | } 40 | 41 | void microseconds_timer_deinit(void) 42 | { 43 | SysTick->CTRL &= ~(SysTick_CTRL_CLKSOURCE_Msk | 44 | SysTick_CTRL_TICKINT_Msk | 45 | SysTick_CTRL_ENABLE_Msk); 46 | SysTick->VAL = 0; 47 | } 48 | 49 | uint32_t microseconds_get_clock(void) 50 | { 51 | return SystemCoreClock; 52 | } 53 | 54 | //! @brief Read back the running tick count 55 | uint64_t microseconds_get_ticks(void) 56 | { 57 | uint32_t high; 58 | uint32_t low; 59 | // 这里的实现要注意确保中断发生时获取系统累计计数值的正确性 60 | do 61 | { 62 | // 先缓存高位计数器 63 | high = s_highCounter; 64 | // 再读定时器实际计数值 65 | low = ~SysTick->VAL & SysTick_LOAD_RELOAD_Msk; 66 | } while (high != s_highCounter); // 保证缓存高位值与读实际低位值间隙中没有发生中断 67 | 68 | 69 | return ((uint64_t)high << 24) + low; 70 | } 71 | 72 | //! @brief Interrupt handler for the SysTick timer, this will just increment 73 | //! the rollover counter for extended time keeping 74 | void SysTick_Handler(void) 75 | { 76 | s_highCounter++; 77 | } 78 | -------------------------------------------------------------------------------- /src/microseconds_imxrt_pit.c: -------------------------------------------------------------------------------- 1 | /* 2 | * SPDX-License-Identifier: BSD-3-Clause 3 | */ 4 | 5 | /* 6 | * @file microseconds_cortexm_systick.c 7 | * @brief Microseconds PIT timer driver source file 8 | * 9 | * Notes: The driver configure PIT as lifetime timer 10 | */ 11 | #include "microseconds.h" 12 | #include "assert.h" 13 | #include "fsl_device_registers.h" 14 | /******************************************************************************* 15 | * Definitions 16 | ******************************************************************************/ 17 | #if defined(PIT0) 18 | #define PIT PIT0 19 | #elif defined(PIT1) 20 | #define PIT PIT1 21 | #endif 22 | 23 | /******************************************************************************* 24 | * Variables 25 | ******************************************************************************/ 26 | 27 | 28 | /******************************************************************************* 29 | * Prototypes 30 | ******************************************************************************/ 31 | extern uint32_t get_pit_clock(void); 32 | 33 | /******************************************************************************* 34 | * Code 35 | ******************************************************************************/ 36 | 37 | void microseconds_timer_init(void) 38 | { 39 | // Turn on PIT: MDIS = 0, FRZ = 0 40 | PIT->MCR = 0x00; 41 | 42 | // Set up timer 1 to max value 43 | PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF; // setup timer 1 for maximum counting period 44 | PIT->CHANNEL[1].TCTRL = 0; // Disable timer 1 interrupts 45 | PIT->CHANNEL[1].TFLG = 1; // clear the timer 1 flag 46 | PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_CHN_MASK; // chain timer 1 to timer 0 47 | PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_TEN_MASK; // start timer 1 48 | 49 | // Set up timer 0 to max value 50 | PIT->CHANNEL[0].LDVAL = 0xFFFFFFFF; // setup timer 0 for maximum counting period 51 | PIT->CHANNEL[0].TFLG = 1; // clear the timer 0 flag 52 | PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK; // start timer 0 53 | } 54 | 55 | void microseconds_timer_deinit(void) 56 | { 57 | // Turn off PIT: MDIS = 1, FRZ = 0 58 | for (int32_t i = 3; i >= 0; i--) 59 | { 60 | PIT->CHANNEL[i].TCTRL = 0; // stop timer 61 | PIT->CHANNEL[i].LDVAL = 0; // clear load value 62 | } 63 | 64 | PIT->MCR |= PIT_MCR_MDIS_MASK; 65 | } 66 | 67 | uint32_t microseconds_get_clock(void) 68 | { 69 | return get_pit_clock(); 70 | } 71 | 72 | //! @brief Read back the running tick count 73 | uint64_t microseconds_get_ticks(void) 74 | { 75 | uint64_t valueH; 76 | volatile uint32_t valueL; 77 | 78 | #if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && (FSL_FEATURE_PIT_HAS_LIFETIME_TIMER == 1) 79 | // Note: first read LTMR64H and then LTMR64L. LTMR64H will have the value 80 | // of CVAL1 at the time of the first access, LTMR64L will have the value of CVAL0 at the 81 | // time of the first access, therefore the application does not need to worry about carry-over 82 | // effects of the running counter. 83 | valueH = PIT->LTMR64H; 84 | valueL = PIT->LTMR64L; 85 | #else 86 | // Make sure that there are no rollover of valueL. 87 | // Because the valueL always decreases, so, if the formal valueL is greater than 88 | // current value, that means the valueH is updated during read valueL. 89 | // In this case, we need to re-update valueH and valueL. 90 | do 91 | { 92 | valueL = PIT->CHANNEL[0].CVAL; 93 | valueH = PIT->CHANNEL[1].CVAL; 94 | } while (valueL < PIT->CHANNEL[0].CVAL); 95 | #endif // FSL_FEATURE_PIT_HAS_LIFETIME_TIMER 96 | 97 | // Invert to turn into an up counter 98 | return ~((valueH << 32) | valueL); 99 | } 100 | 101 | -------------------------------------------------------------------------------- /test/pit_imxrt1011/MIMXRT1011_features.h: -------------------------------------------------------------------------------- 1 | /* 2 | ** ################################################################### 3 | ** Version: rev. 1.0, 2019-08-01 4 | ** Build: b200921 5 | ** 6 | ** Abstract: 7 | ** Chip specific module features. 8 | ** 9 | ** Copyright 2016 Freescale Semiconductor, Inc. 10 | ** Copyright 2016-2020 NXP 11 | ** All rights reserved. 12 | ** 13 | ** SPDX-License-Identifier: BSD-3-Clause 14 | ** 15 | ** http: www.nxp.com 16 | ** mail: support@nxp.com 17 | ** 18 | ** Revisions: 19 | ** - rev. 0.1 (2019-02-14) 20 | ** Initial version. 21 | ** - rev. 1.0 (2019-08-01) 22 | ** Rev.0 Header GA 23 | ** 24 | ** ################################################################### 25 | */ 26 | 27 | #ifndef _MIMXRT1011_FEATURES_H_ 28 | #define _MIMXRT1011_FEATURES_H_ 29 | 30 | /* SOC module features */ 31 | 32 | /* @brief ADC availability on the SoC. */ 33 | #define FSL_FEATURE_SOC_ADC_COUNT (1) 34 | /* @brief AIPSTZ availability on the SoC. */ 35 | #define FSL_FEATURE_SOC_AIPSTZ_COUNT (2) 36 | /* @brief AOI availability on the SoC. */ 37 | #define FSL_FEATURE_SOC_AOI_COUNT (1) 38 | /* @brief CCM availability on the SoC. */ 39 | #define FSL_FEATURE_SOC_CCM_COUNT (1) 40 | /* @brief CCM_ANALOG availability on the SoC. */ 41 | #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) 42 | /* @brief DCDC availability on the SoC. */ 43 | #define FSL_FEATURE_SOC_DCDC_COUNT (1) 44 | /* @brief DCP availability on the SoC. */ 45 | #define FSL_FEATURE_SOC_DCP_COUNT (1) 46 | /* @brief DMAMUX availability on the SoC. */ 47 | #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 48 | /* @brief EDMA availability on the SoC. */ 49 | #define FSL_FEATURE_SOC_EDMA_COUNT (1) 50 | /* @brief EWM availability on the SoC. */ 51 | #define FSL_FEATURE_SOC_EWM_COUNT (1) 52 | /* @brief FLEXIO availability on the SoC. */ 53 | #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) 54 | /* @brief FLEXRAM availability on the SoC. */ 55 | #define FSL_FEATURE_SOC_FLEXRAM_COUNT (1) 56 | /* @brief FLEXSPI availability on the SoC. */ 57 | #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) 58 | /* @brief GPC availability on the SoC. */ 59 | #define FSL_FEATURE_SOC_GPC_COUNT (1) 60 | /* @brief GPT availability on the SoC. */ 61 | #define FSL_FEATURE_SOC_GPT_COUNT (2) 62 | /* @brief I2S availability on the SoC. */ 63 | #define FSL_FEATURE_SOC_I2S_COUNT (2) 64 | /* @brief IGPIO availability on the SoC. */ 65 | #define FSL_FEATURE_SOC_IGPIO_COUNT (3) 66 | /* @brief IOMUXC availability on the SoC. */ 67 | #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) 68 | /* @brief IOMUXC_GPR availability on the SoC. */ 69 | #define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) 70 | /* @brief IOMUXC_SNVS availability on the SoC. */ 71 | #define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1) 72 | /* @brief KPP availability on the SoC. */ 73 | #define FSL_FEATURE_SOC_KPP_COUNT (1) 74 | /* @brief LPI2C availability on the SoC. */ 75 | #define FSL_FEATURE_SOC_LPI2C_COUNT (2) 76 | /* @brief LPSPI availability on the SoC. */ 77 | #define FSL_FEATURE_SOC_LPSPI_COUNT (2) 78 | /* @brief LPUART availability on the SoC. */ 79 | #define FSL_FEATURE_SOC_LPUART_COUNT (4) 80 | /* @brief OCOTP availability on the SoC. */ 81 | #define FSL_FEATURE_SOC_OCOTP_COUNT (1) 82 | /* @brief OTFAD availability on the SoC. */ 83 | #define FSL_FEATURE_SOC_OTFAD_COUNT (1) 84 | /* @brief PIT availability on the SoC. */ 85 | #define FSL_FEATURE_SOC_PIT_COUNT (1) 86 | /* @brief PMU availability on the SoC. */ 87 | #define FSL_FEATURE_SOC_PMU_COUNT (1) 88 | /* @brief PWM availability on the SoC. */ 89 | #define FSL_FEATURE_SOC_PWM_COUNT (1) 90 | /* @brief ROMC availability on the SoC. */ 91 | #define FSL_FEATURE_SOC_ROMC_COUNT (1) 92 | /* @brief SNVS availability on the SoC. */ 93 | #define FSL_FEATURE_SOC_SNVS_COUNT (1) 94 | /* @brief SPDIF availability on the SoC. */ 95 | #define FSL_FEATURE_SOC_SPDIF_COUNT (1) 96 | /* @brief SRC availability on the SoC. */ 97 | #define FSL_FEATURE_SOC_SRC_COUNT (1) 98 | /* @brief TEMPMON availability on the SoC. */ 99 | #define FSL_FEATURE_SOC_TEMPMON_COUNT (1) 100 | /* @brief TRNG availability on the SoC. */ 101 | #define FSL_FEATURE_SOC_TRNG_COUNT (1) 102 | /* @brief USBHS availability on the SoC. */ 103 | #define FSL_FEATURE_SOC_USBHS_COUNT (1) 104 | /* @brief USBNC availability on the SoC. */ 105 | #define FSL_FEATURE_SOC_USBNC_COUNT (1) 106 | /* @brief USBPHY availability on the SoC. */ 107 | #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 108 | /* @brief USB_ANALOG availability on the SoC. */ 109 | #define FSL_FEATURE_SOC_USB_ANALOG_COUNT (1) 110 | /* @brief WDOG availability on the SoC. */ 111 | #define FSL_FEATURE_SOC_WDOG_COUNT (2) 112 | /* @brief XBARA availability on the SoC. */ 113 | #define FSL_FEATURE_SOC_XBARA_COUNT (1) 114 | /* @brief XTALOSC24M availability on the SoC. */ 115 | #define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1) 116 | 117 | /* ADC module features */ 118 | 119 | /* @brief Remove Hardware Trigger feature. */ 120 | #define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0) 121 | /* @brief Remove ALT Clock selection feature. */ 122 | #define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (0) 123 | /* @brief Conversion control count (related to number of registers HCn and Rn). */ 124 | #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (8) 125 | 126 | /* ADC_ETC module features */ 127 | 128 | /* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */ 129 | #define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1) 130 | /* @brief Has TRIGm_CHAIN_a_b IEn_EN. */ 131 | #define FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN (1) 132 | 133 | /* AOI module features */ 134 | 135 | /* @brief Maximum value of input mux. */ 136 | #define FSL_FEATURE_AOI_MODULE_INPUTS (4) 137 | /* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ 138 | #define FSL_FEATURE_AOI_EVENT_COUNT (4) 139 | 140 | /* CCM module features */ 141 | 142 | /* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */ 143 | #define FSL_FEATURE_CCM_HAS_ERRATA_50235 (0) 144 | 145 | /* DCDC module features */ 146 | 147 | /* @brief Has CTRL register (register CTRL0/1). */ 148 | #define FSL_FEATURE_DCDC_HAS_CTRL_REG (0) 149 | /* @brief DCDC VDD output count. */ 150 | #define FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT (1) 151 | /* @brief Has no current alert function (register bit field REG0[CURRENT_ALERT_RESET]). */ 152 | #define FSL_FEATURE_DCDC_HAS_NO_CURRENT_ALERT_FUNC (0) 153 | /* @brief Has switching converter differential mode (register bit field REG1[LOOPCTRL_EN_DF_HYST]). */ 154 | #define FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE (0) 155 | /* @brief Has register bit field REG0[REG_DCDC_IN_DET]. */ 156 | #define FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET (0) 157 | /* @brief Has no register bit field REG0[EN_LP_OVERLOAD_SNS]. */ 158 | #define FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS (0) 159 | /* @brief Has register bit field REG3[REG_FBK_SEL]). */ 160 | #define FSL_FEATURE_DCDC_HAS_REG3_FBK_SEL (0) 161 | 162 | /* EDMA module features */ 163 | 164 | /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 165 | #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) 166 | /* @brief Total number of DMA channels on all modules. */ 167 | #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (16) 168 | /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 169 | #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 170 | /* @brief Has DMA_Error interrupt vector. */ 171 | #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 172 | /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 173 | #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) 174 | /* @brief Channel IRQ entry shared offset. */ 175 | #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (0) 176 | /* @brief If 8 bytes transfer supported. */ 177 | #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) 178 | /* @brief If 16 bytes transfer supported. */ 179 | #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0) 180 | /* @brief If 32 bytes transfer supported. */ 181 | #define FSL_FEATURE_EDMA_SUPPORT_32_BYTES_TRANSFER (1) 182 | 183 | /* DMAMUX module features */ 184 | 185 | /* @brief Number of DMA channels (related to number of register CHCFGn). */ 186 | #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) 187 | /* @brief Total number of DMA channels on all modules. */ 188 | #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (16) 189 | /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 190 | #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 191 | /* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */ 192 | #define FSL_FEATURE_DMAMUX_HAS_A_ON (1) 193 | /* @brief Register CHCFGn width. */ 194 | #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (32) 195 | 196 | /* EWM module features */ 197 | 198 | /* @brief Has clock select (register CLKCTRL). */ 199 | #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) 200 | /* @brief Has clock prescaler (register CLKPRESCALER). */ 201 | #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 202 | 203 | /* FLEXIO module features */ 204 | 205 | /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 206 | #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 207 | /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 208 | #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) 209 | /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 210 | #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) 211 | /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 212 | #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) 213 | /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 214 | #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) 215 | /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 216 | #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) 217 | /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 218 | #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) 219 | /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 220 | #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) 221 | /* @brief Reset value of the FLEXIO_VERID register */ 222 | #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) 223 | /* @brief Reset value of the FLEXIO_PARAM register */ 224 | #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200808) 225 | /* @brief Flexio DMA request base channel */ 226 | #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) 227 | 228 | /* FLEXRAM module features */ 229 | 230 | /* @brief Bank size */ 231 | #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768) 232 | /* @brief Total Bank numbers */ 233 | #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (4) 234 | /* @brief Has FLEXRAM_MAGIC_ADDR. */ 235 | #define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (1) 236 | 237 | /* FLEXSPI module features */ 238 | 239 | /* @brief FlexSPI AHB buffer count */ 240 | #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4) 241 | /* @brief FlexSPI has no data learn. */ 242 | #define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1) 243 | /* @brief There is AHBBUSERROREN bit in INTEN register. */ 244 | #define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) 245 | /* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ 246 | #define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) 247 | 248 | /* GPC module features */ 249 | 250 | /* @brief Has DVFS0 Change Request. */ 251 | #define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0) 252 | /* @brief Has GPC interrupt/event masking. */ 253 | #define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0) 254 | /* @brief Has L2 cache power control. */ 255 | #define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0) 256 | /* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */ 257 | #define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1) 258 | /* @brief Has VADC power control. */ 259 | #define FSL_FEATURE_GPC_HAS_CNTR_VADC (0) 260 | /* @brief Has Display power control. */ 261 | #define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0) 262 | /* @brief Supports IRQ 0-31. */ 263 | #define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1) 264 | 265 | /* IGPIO module features */ 266 | 267 | /* @brief Has data register set DR_SET. */ 268 | #define FSL_FEATURE_IGPIO_HAS_DR_SET (1) 269 | /* @brief Has data register clear DR_CLEAR. */ 270 | #define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1) 271 | /* @brief Has data register toggle DR_TOGGLE. */ 272 | #define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1) 273 | 274 | /* LPI2C module features */ 275 | 276 | /* @brief Has separate DMA RX and TX requests. */ 277 | #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) 278 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 279 | #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) 280 | 281 | /* LPSPI module features */ 282 | 283 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 284 | #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16) 285 | /* @brief Has separate DMA RX and TX requests. */ 286 | #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 287 | 288 | /* LPUART module features */ 289 | 290 | /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 291 | #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 292 | /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 293 | #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 294 | /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 295 | #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 296 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 297 | #define FSL_FEATURE_LPUART_HAS_FIFO (1) 298 | /* @brief Has 32-bit register MODIR */ 299 | #define FSL_FEATURE_LPUART_HAS_MODIR (1) 300 | /* @brief Hardware flow control (RTS, CTS) is supported. */ 301 | #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 302 | /* @brief Infrared (modulation) is supported. */ 303 | #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 304 | /* @brief 2 bits long stop bit is available. */ 305 | #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 306 | /* @brief If 10-bit mode is supported. */ 307 | #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 308 | /* @brief If 7-bit mode is supported. */ 309 | #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) 310 | /* @brief Baud rate fine adjustment is available. */ 311 | #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 312 | /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 313 | #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 314 | /* @brief Baud rate oversampling is available. */ 315 | #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 316 | /* @brief Baud rate oversampling is available. */ 317 | #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 318 | /* @brief Peripheral type. */ 319 | #define FSL_FEATURE_LPUART_IS_SCI (1) 320 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 321 | #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) 322 | /* @brief Supports two match addresses to filter incoming frames. */ 323 | #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 324 | /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 325 | #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 326 | /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 327 | #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 328 | /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 329 | #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 330 | /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 331 | #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 332 | /* @brief Has improved smart card (ISO7816 protocol) support. */ 333 | #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 334 | /* @brief Has local operation network (CEA709.1-B protocol) support. */ 335 | #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 336 | /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 337 | #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 338 | /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 339 | #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 340 | /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 341 | #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 342 | /* @brief Has separate DMA RX and TX requests. */ 343 | #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 344 | /* @brief Has separate RX and TX interrupts. */ 345 | #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 346 | /* @brief Has LPAURT_PARAM. */ 347 | #define FSL_FEATURE_LPUART_HAS_PARAM (1) 348 | /* @brief Has LPUART_VERID. */ 349 | #define FSL_FEATURE_LPUART_HAS_VERID (1) 350 | /* @brief Has LPUART_GLOBAL. */ 351 | #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) 352 | /* @brief Has LPUART_PINCFG. */ 353 | #define FSL_FEATURE_LPUART_HAS_PINCFG (1) 354 | 355 | /* interrupt module features */ 356 | 357 | /* @brief Lowest interrupt request number. */ 358 | #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 359 | /* @brief Highest interrupt request number. */ 360 | #define FSL_FEATURE_INTERRUPT_IRQ_MAX (79) 361 | 362 | /* OCOTP module features */ 363 | 364 | /* @brief Has timing control, (register TIMING). */ 365 | #define FSL_FEATURE_OCOTP_HAS_TIMING_CTRL (1) 366 | /* @brief Support lock eFuse word write lock, (CTRL[WORDLOCK]). */ 367 | #define FSL_FEATURE_OCOTP_HAS_WORDLOCK (0) 368 | /* @brief Has status register. (Register HW_OCOTP_OUT_STATUS0). */ 369 | #define FSL_FEATURE_OCOTP_HAS_STATUS (0) 370 | 371 | /* OTFAD module features */ 372 | 373 | /* @brief OTFAD has Security Violation Mode (SVM) */ 374 | #define FSL_FEATURE_OTFAD_HAS_SVM_MODE (1) 375 | /* @brief OTFAD has Key Blob Processing */ 376 | #define FSL_FEATURE_OTFAD_HAS_KEYBLOB_PROCESSING (1) 377 | /* @brief OTFAD has interrupt request enable */ 378 | #define FSL_FEATURE_OTFAD_HAS_HAS_IRQ_ENABLE (1) 379 | /* @brief OTFAD has Force Error */ 380 | #define FSL_FEATURE_OTFAD_HAS_FORCE_ERR (1) 381 | 382 | /* PIT module features */ 383 | 384 | /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 385 | #define FSL_FEATURE_PIT_TIMER_COUNT (4) 386 | /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 387 | #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 388 | /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 389 | #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 390 | /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 391 | #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) 392 | /* @brief Has timer enable control. */ 393 | #define FSL_FEATURE_PIT_HAS_MDIS (1) 394 | 395 | /* PWM module features */ 396 | 397 | /* @brief If (e)FlexPWM has module A channels (outputs). */ 398 | #define FSL_FEATURE_PWM_HAS_CHANNELA (1) 399 | /* @brief If (e)FlexPWM has module B channels (outputs). */ 400 | #define FSL_FEATURE_PWM_HAS_CHANNELB (1) 401 | /* @brief If (e)FlexPWM has module X channels (outputs). */ 402 | #define FSL_FEATURE_PWM_HAS_CHANNELX (1) 403 | /* @brief If (e)FlexPWM has fractional feature. */ 404 | #define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) 405 | /* @brief If (e)FlexPWM has mux trigger source select bit field. */ 406 | #define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) 407 | /* @brief Number of submodules in each (e)FlexPWM module. */ 408 | #define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) 409 | /* @brief Number of fault channel in each (e)FlexPWM module. */ 410 | #define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) 411 | 412 | /* RTWDOG module features */ 413 | 414 | /* @brief Watchdog is available. */ 415 | #define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1) 416 | /* @brief RTWDOG_CNT can be 32-bit written. */ 417 | #define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1) 418 | 419 | /* SAI module features */ 420 | 421 | /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 422 | #define FSL_FEATURE_SAI_FIFO_COUNT (32) 423 | /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 424 | #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ 425 | (((x) == SAI1) ? (2) : \ 426 | (((x) == SAI3) ? (1) : (-1))) 427 | /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 428 | #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) 429 | /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 430 | #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) 431 | /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 432 | #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) 433 | /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 434 | #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) 435 | /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 436 | #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) 437 | /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 438 | #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 439 | /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 440 | #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) 441 | /* @brief Interrupt source number */ 442 | #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) 443 | /* @brief Has register of MCR. */ 444 | #define FSL_FEATURE_SAI_HAS_MCR (0) 445 | /* @brief Has bit field MICS of the MCR register. */ 446 | #define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) 447 | /* @brief Has register of MDR */ 448 | #define FSL_FEATURE_SAI_HAS_MDR (0) 449 | /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ 450 | #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) 451 | /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ 452 | #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) 453 | /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ 454 | #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) 455 | 456 | /* SNVS module features */ 457 | 458 | /* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ 459 | #define FSL_FEATURE_SNVS_HAS_SRTC (1) 460 | 461 | /* SRC module features */ 462 | 463 | /* @brief There is MASK_WDOG3_RST bit in SCR register. */ 464 | #define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1) 465 | /* @brief There is MIX_RST_STRCH bit in SCR register. */ 466 | #define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0) 467 | /* @brief There is DBG_RST_MSK_PG bit in SCR register. */ 468 | #define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1) 469 | /* @brief There is WDOG3_RST_OPTN bit in SCR register. */ 470 | #define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0) 471 | /* @brief There is CORES_DBG_RST bit in SCR register. */ 472 | #define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0) 473 | /* @brief There is MTSR bit in SCR register. */ 474 | #define FSL_FEATURE_SRC_HAS_SCR_MTSR (0) 475 | /* @brief There is CORE0_DBG_RST bit in SCR register. */ 476 | #define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1) 477 | /* @brief There is CORE0_RST bit in SCR register. */ 478 | #define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1) 479 | /* @brief There is LOCKUP_RST bit in SCR register. */ 480 | #define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (1) 481 | /* @brief There is SWRC bit in SCR register. */ 482 | #define FSL_FEATURE_SRC_HAS_SCR_SWRC (0) 483 | /* @brief There is EIM_RST bit in SCR register. */ 484 | #define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0) 485 | /* @brief There is LUEN bit in SCR register. */ 486 | #define FSL_FEATURE_SRC_HAS_SCR_LUEN (0) 487 | /* @brief There is no WRBC bit in SCR register. */ 488 | #define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1) 489 | /* @brief There is no WRE bit in SCR register. */ 490 | #define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1) 491 | /* @brief There is SISR register. */ 492 | #define FSL_FEATURE_SRC_HAS_SISR (0) 493 | /* @brief There is RESET_OUT bit in SRSR register. */ 494 | #define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0) 495 | /* @brief There is WDOG3_RST_B bit in SRSR register. */ 496 | #define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1) 497 | /* @brief There is JTAG_SW_RST bit in SRSR register. */ 498 | #define FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST (1) 499 | /* @brief There is SW bit in SRSR register. */ 500 | #define FSL_FEATURE_SRC_HAS_SRSR_SW (0) 501 | /* @brief There is IPP_USER_RESET_B bit in SRSR register. */ 502 | #define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1) 503 | /* @brief There is SNVS bit in SRSR register. */ 504 | #define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0) 505 | /* @brief There is CSU_RESET_B bit in SRSR register. */ 506 | #define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1) 507 | /* @brief There is LOCKUP bit in SRSR register. */ 508 | #define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (1) 509 | /* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */ 510 | #define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (0) 511 | /* @brief There is POR bit in SRSR register. */ 512 | #define FSL_FEATURE_SRC_HAS_SRSR_POR (0) 513 | /* @brief There is IPP_RESET_B bit in SRSR register. */ 514 | #define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1) 515 | /* @brief There is no WBI bit in SCR register. */ 516 | #define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1) 517 | 518 | /* SCB module features */ 519 | 520 | /* @brief L1 ICACHE line size in byte. */ 521 | #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) 522 | /* @brief L1 DCACHE line size in byte. */ 523 | #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) 524 | 525 | /* TRNG module features */ 526 | 527 | /* @brief TRNG has no TRNG_ACC bitfield. */ 528 | #define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) 529 | 530 | /* USBHS module features */ 531 | 532 | /* @brief EHCI module instance count */ 533 | #define FSL_FEATURE_USBHS_EHCI_COUNT (1) 534 | /* @brief Number of endpoints supported */ 535 | #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) 536 | 537 | /* USBPHY module features */ 538 | 539 | /* @brief USBPHY contain DCD analog module */ 540 | #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) 541 | /* @brief USBPHY has register TRIM_OVERRIDE_EN */ 542 | #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (0) 543 | /* @brief USBPHY is 28FDSOI */ 544 | #define FSL_FEATURE_USBPHY_28FDSOI (0) 545 | 546 | /* XBARA module features */ 547 | 548 | /* @brief Number of interrupt requests. */ 549 | #define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4) 550 | 551 | #endif /* _MIMXRT1011_FEATURES_H_ */ 552 | 553 | -------------------------------------------------------------------------------- /test/pit_imxrt1011/MIMXRT1011xxxxx_flexspi_nor.icf: -------------------------------------------------------------------------------- 1 | /* 2 | ** ################################################################### 3 | ** Processors: MIMXRT1011CAE4A 4 | ** MIMXRT1011DAE5A 5 | ** 6 | ** Compiler: IAR ANSI C/C++ Compiler for ARM 7 | ** Reference manual: IMXRT1010RM Rev.A, 03/2019 8 | ** Version: rev. 0.1, 2019-02-14 9 | ** Build: b190912 10 | ** 11 | ** Abstract: 12 | ** Linker file for the IAR ANSI C/C++ Compiler for ARM 13 | ** 14 | ** Copyright 2016 Freescale Semiconductor, Inc. 15 | ** Copyright 2016-2019 NXP 16 | ** All rights reserved. 17 | ** 18 | ** SPDX-License-Identifier: BSD-3-Clause 19 | ** 20 | ** http: www.nxp.com 21 | ** mail: support@nxp.com 22 | ** 23 | ** ################################################################### 24 | */ 25 | 26 | define symbol m_interrupts_start = 0x60002000; 27 | define symbol m_interrupts_end = 0x600023FF; 28 | 29 | define symbol m_text_start = 0x60002400; 30 | define symbol m_text_end = 0x60FFFFFF; 31 | 32 | define symbol m_text2_start = 0x00000000; 33 | define symbol m_text2_end = 0x00007FFF; 34 | 35 | define symbol m_data_start = 0x20000000; 36 | define symbol m_data_end = 0x20007FFF; 37 | 38 | define symbol m_data2_start = 0x20200000; 39 | define symbol m_data2_end = 0x2020FFFF; 40 | 41 | define exported symbol m_boot_hdr_conf_start = 0x60000400; 42 | define symbol m_boot_hdr_ivt_start = 0x60001000; 43 | define symbol m_boot_hdr_boot_data_start = 0x60001020; 44 | define symbol m_boot_hdr_dcd_data_start = 0x60001030; 45 | 46 | /* Sizes */ 47 | if (isdefinedsymbol(__stack_size__)) { 48 | define symbol __size_cstack__ = __stack_size__; 49 | } else { 50 | define symbol __size_cstack__ = 0x0400; 51 | } 52 | 53 | if (isdefinedsymbol(__heap_size__)) { 54 | define symbol __size_heap__ = __heap_size__; 55 | } else { 56 | define symbol __size_heap__ = 0x0400; 57 | } 58 | 59 | define exported symbol __NCACHE_REGION_START = m_data2_start; 60 | define exported symbol __NCACHE_REGION_SIZE = 0x0; 61 | 62 | define exported symbol __VECTOR_TABLE = m_interrupts_start; 63 | define exported symbol __VECTOR_RAM = m_interrupts_start; 64 | define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; 65 | 66 | define memory mem with size = 4G; 67 | define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] 68 | | mem:[from m_text_start to m_text_end]; 69 | define region TEXT2_region = mem:[from m_text2_start to m_text2_end]; 70 | define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; 71 | define region DATA2_region = mem:[from m_data2_start to m_data2_end]; 72 | define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; 73 | 74 | define block CSTACK with alignment = 8, size = __size_cstack__ { }; 75 | define block HEAP with alignment = 8, size = __size_heap__ { }; 76 | define block RW { readwrite }; 77 | define block ZI { zi }; 78 | define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; 79 | define block QACCESS_FUNC { section CodeQuickAccess }; 80 | 81 | initialize by copy { readwrite, section .textrw, section CodeQuickAccess }; 82 | do not initialize { section .noinit }; 83 | 84 | place at address mem: m_interrupts_start { readonly section .intvec }; 85 | 86 | place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; 87 | place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; 88 | place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; 89 | place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; 90 | 91 | keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; 92 | 93 | place in TEXT_region { readonly }; 94 | place in DATA_region { block RW }; 95 | place in DATA_region { block ZI }; 96 | place in DATA_region { last block HEAP }; 97 | place in DATA_region { block NCACHE_VAR }; 98 | place in CSTACK_region { block CSTACK }; 99 | place in TEXT2_region { section .textrw}; 100 | place in TEXT2_region { block QACCESS_FUNC }; 101 | -------------------------------------------------------------------------------- /test/pit_imxrt1011/MIMXRT1011xxxxx_ram.icf: -------------------------------------------------------------------------------- 1 | /* 2 | ** ################################################################### 3 | ** Processors: MIMXRT1011CAE4A 4 | ** MIMXRT1011DAE5A 5 | ** 6 | ** Compiler: IAR ANSI C/C++ Compiler for ARM 7 | ** Reference manual: IMXRT1010RM Rev.A, 03/2019 8 | ** Version: rev. 0.1, 2019-02-14 9 | ** Build: b190912 10 | ** 11 | ** Abstract: 12 | ** Linker file for the IAR ANSI C/C++ Compiler for ARM 13 | ** 14 | ** Copyright 2016 Freescale Semiconductor, Inc. 15 | ** Copyright 2016-2019 NXP 16 | ** All rights reserved. 17 | ** 18 | ** SPDX-License-Identifier: BSD-3-Clause 19 | ** 20 | ** http: www.nxp.com 21 | ** mail: support@nxp.com 22 | ** 23 | ** ################################################################### 24 | */ 25 | 26 | define symbol m_interrupts_start = 0x00000000; 27 | define symbol m_interrupts_end = 0x000003FF; 28 | 29 | define symbol m_text_start = 0x00000400; 30 | define symbol m_text_end = 0x00007FFF; 31 | 32 | define symbol m_data_start = 0x20000000; 33 | define symbol m_data_end = 0x20007FFF; 34 | 35 | define symbol m_data2_start = 0x20200000; 36 | define symbol m_data2_end = 0x2020FFFF; 37 | 38 | /* Sizes */ 39 | if (isdefinedsymbol(__stack_size__)) { 40 | define symbol __size_cstack__ = __stack_size__; 41 | } else { 42 | define symbol __size_cstack__ = 0x0400; 43 | } 44 | 45 | if (isdefinedsymbol(__heap_size__)) { 46 | define symbol __size_heap__ = __heap_size__; 47 | } else { 48 | define symbol __size_heap__ = 0x0400; 49 | } 50 | 51 | define exported symbol __NCACHE_REGION_START = m_data2_start; 52 | define exported symbol __NCACHE_REGION_SIZE = 0x0; 53 | 54 | define exported symbol __VECTOR_TABLE = m_interrupts_start; 55 | define exported symbol __VECTOR_RAM = m_interrupts_start; 56 | define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; 57 | 58 | define memory mem with size = 4G; 59 | define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] 60 | | mem:[from m_text_start to m_text_end]; 61 | define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; 62 | define region DATA2_region = mem:[from m_data2_start to m_data2_end]; 63 | define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; 64 | 65 | define block CSTACK with alignment = 8, size = __size_cstack__ { }; 66 | define block HEAP with alignment = 8, size = __size_heap__ { }; 67 | define block RW { readwrite }; 68 | define block ZI { zi }; 69 | define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; 70 | 71 | initialize by copy { readwrite, section .textrw }; 72 | do not initialize { section .noinit }; 73 | 74 | place at address mem: m_interrupts_start { readonly section .intvec }; 75 | 76 | place in TEXT_region { readonly }; 77 | place in DATA_region { block RW }; 78 | place in DATA_region { block ZI }; 79 | place in DATA_region { last block HEAP }; 80 | place in DATA_region { block NCACHE_VAR }; 81 | place in CSTACK_region { block CSTACK }; 82 | -------------------------------------------------------------------------------- /test/pit_imxrt1011/fsl_device_registers.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2014-2016 Freescale Semiconductor, Inc. 3 | * Copyright 2016-2019 NXP 4 | * All rights reserved. 5 | * 6 | * SPDX-License-Identifier: BSD-3-Clause 7 | * 8 | */ 9 | 10 | #ifndef __FSL_DEVICE_REGISTERS_H__ 11 | #define __FSL_DEVICE_REGISTERS_H__ 12 | 13 | /* 14 | * Include the cpu specific register header files. 15 | * 16 | * The CPU macro should be declared in the project or makefile. 17 | */ 18 | #if (defined(CPU_MIMXRT1011CAE4A) || defined(CPU_MIMXRT1011DAE5A)) 19 | 20 | #define MIMXRT1011_SERIES 21 | 22 | /* CMSIS-style register definitions */ 23 | #include "MIMXRT1011.h" 24 | /* CPU specific feature definitions */ 25 | #include "MIMXRT1011_features.h" 26 | 27 | #else 28 | #error "No valid CPU defined!" 29 | #endif 30 | 31 | #endif /* __FSL_DEVICE_REGISTERS_H__ */ 32 | 33 | /******************************************************************************* 34 | * EOF 35 | ******************************************************************************/ 36 | -------------------------------------------------------------------------------- /test/pit_imxrt1011/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * SPDX-License-Identifier: BSD-3-Clause 3 | */ 4 | #include "microseconds.h" 5 | #include "fsl_clock.h" 6 | #include "fsl_device_registers.h" 7 | /******************************************************************************* 8 | * Definitions 9 | ******************************************************************************/ 10 | 11 | 12 | /******************************************************************************* 13 | * Variables 14 | ******************************************************************************/ 15 | 16 | 17 | /******************************************************************************* 18 | * Prototypes 19 | ******************************************************************************/ 20 | 21 | 22 | /******************************************************************************* 23 | * Code 24 | ******************************************************************************/ 25 | 26 | //! @brief Get PIT clock value 27 | uint32_t get_pit_clock(void) 28 | { 29 | // Get PIT clock source 30 | uint32_t ahbBusDivider = ((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1; 31 | uint32_t periphDivider = ((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_PODF_MASK) >> CCM_CSCMR1_PERCLK_PODF_SHIFT) + 1; 32 | return SystemCoreClock / ahbBusDivider / periphDivider; 33 | } 34 | 35 | /*! 36 | * @brief Main function 37 | */ 38 | int main(void) 39 | { 40 | SystemCoreClockUpdate(); 41 | 42 | // PIT clock gate control ON 43 | CLOCK_EnableClock(kCLOCK_Pit); 44 | 45 | microseconds_init(); 46 | // Delay 5s 47 | microseconds_delay(5000000); 48 | // Set delay time to 5s 49 | microseconds_set_delay(5000000); 50 | // wait 5s timeout 51 | while(!microseconds_is_timeout()); 52 | 53 | microseconds_shutdown(); 54 | 55 | while (1) 56 | { 57 | } 58 | } 59 | -------------------------------------------------------------------------------- /test/pit_imxrt1011/microseconds_demo.eww: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | $WS_DIR$\microseconds_demo.ewp 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /test/pit_imxrt1011/system_MIMXRT1011.c: -------------------------------------------------------------------------------- 1 | /* 2 | ** ################################################################### 3 | ** Processors: MIMXRT1011CAE4A 4 | ** MIMXRT1011DAE5A 5 | ** 6 | ** Compilers: Freescale C/C++ for Embedded ARM 7 | ** GNU C Compiler 8 | ** IAR ANSI C/C++ Compiler for ARM 9 | ** Keil ARM C/C++ Compiler 10 | ** MCUXpresso Compiler 11 | ** 12 | ** Reference manual: IMXRT1010RM Rev.0, 09/2019 13 | ** Version: rev. 1.1, 2019-08-06 14 | ** Build: b201016 15 | ** 16 | ** Abstract: 17 | ** Provides a system configuration function and a global variable that 18 | ** contains the system frequency. It configures the device and initializes 19 | ** the oscillator (PLL) that is part of the microcontroller device. 20 | ** 21 | ** Copyright 2016 Freescale Semiconductor, Inc. 22 | ** Copyright 2016-2020 NXP 23 | ** All rights reserved. 24 | ** 25 | ** SPDX-License-Identifier: BSD-3-Clause 26 | ** 27 | ** http: www.nxp.com 28 | ** mail: support@nxp.com 29 | ** 30 | ** Revisions: 31 | ** - rev. 0.1 (2019-02-14) 32 | ** Initial version. 33 | ** - rev. 1.0 (2019-08-01) 34 | ** Rev.0 Header GA 35 | ** - rev. 1.1 (2019-08-06) 36 | ** Update header files to align with IMXRT1010RM Rev.B. 37 | ** 38 | ** ################################################################### 39 | */ 40 | 41 | /*! 42 | * @file MIMXRT1011 43 | * @version 1.1 44 | * @date 2019-08-06 45 | * @brief Device specific configuration file for MIMXRT1011 (implementation file) 46 | * 47 | * Provides a system configuration function and a global variable that contains 48 | * the system frequency. It configures the device and initializes the oscillator 49 | * (PLL) that is part of the microcontroller device. 50 | */ 51 | 52 | #include 53 | #include "fsl_device_registers.h" 54 | 55 | 56 | 57 | /* ---------------------------------------------------------------------------- 58 | -- Core clock 59 | ---------------------------------------------------------------------------- */ 60 | 61 | uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 62 | 63 | /* ---------------------------------------------------------------------------- 64 | -- SystemInit() 65 | ---------------------------------------------------------------------------- */ 66 | 67 | void SystemInit (void) { 68 | #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) 69 | SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ 70 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 71 | SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ 72 | #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 73 | #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ 74 | 75 | #if defined(__MCUXPRESSO) 76 | extern uint32_t g_pfnVectors[]; // Vector table defined in startup code 77 | SCB->VTOR = (uint32_t)g_pfnVectors; 78 | #endif 79 | 80 | /* Disable Watchdog Power Down Counter */ 81 | WDOG1->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK; 82 | WDOG2->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK; 83 | 84 | /* Watchdog disable */ 85 | 86 | #if (DISABLE_WDOG) 87 | if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U) 88 | { 89 | WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK; 90 | } 91 | if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U) 92 | { 93 | WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK; 94 | } 95 | if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U) 96 | { 97 | RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */ 98 | } 99 | else 100 | { 101 | RTWDOG->CNT = 0xC520U; 102 | RTWDOG->CNT = 0xD928U; 103 | } 104 | RTWDOG->TOVAL = 0xFFFF; 105 | RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK; 106 | #endif /* (DISABLE_WDOG) */ 107 | 108 | /* Disable Systick which might be enabled by bootrom */ 109 | if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U) 110 | { 111 | SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; 112 | } 113 | 114 | /* Enable instruction and data caches */ 115 | #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT 116 | if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) { 117 | SCB_EnableICache(); 118 | } 119 | #endif 120 | #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT 121 | if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) { 122 | SCB_EnableDCache(); 123 | } 124 | #endif 125 | 126 | SystemInitHook(); 127 | } 128 | 129 | /* ---------------------------------------------------------------------------- 130 | -- SystemCoreClockUpdate() 131 | ---------------------------------------------------------------------------- */ 132 | 133 | void SystemCoreClockUpdate (void) { 134 | 135 | uint32_t freq; 136 | uint32_t PLL2MainClock; 137 | uint32_t PLL3MainClock; 138 | 139 | /* Check if system pll is bypassed */ 140 | if((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) != 0U) 141 | { 142 | PLL2MainClock = CPU_XTAL_CLK_HZ; 143 | } 144 | else 145 | { 146 | PLL2MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) ? 22U : 20U)); 147 | } 148 | PLL2MainClock += (uint32_t)(((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM))); 149 | 150 | /* Check if usb1 pll is bypassed */ 151 | if((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) != 0U) 152 | { 153 | PLL3MainClock = CPU_XTAL_CLK_HZ; 154 | } 155 | else 156 | { 157 | PLL3MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0U) ? 22U : 20U)); 158 | } 159 | 160 | /* Periph_clk2_clk ---> Periph_clk */ 161 | if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U) 162 | { 163 | switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) 164 | { 165 | /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */ 166 | case CCM_CBCMR_PERIPH_CLK2_SEL(0U): 167 | freq = PLL3MainClock; 168 | break; 169 | 170 | /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */ 171 | case CCM_CBCMR_PERIPH_CLK2_SEL(1U): 172 | freq = CPU_XTAL_CLK_HZ; 173 | break; 174 | 175 | /* Pll2_bypass_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */ 176 | case CCM_CBCMR_PERIPH_CLK2_SEL(2U): 177 | freq = CPU_XTAL_CLK_HZ; 178 | break; 179 | 180 | case CCM_CBCMR_PERIPH_CLK2_SEL(3U): 181 | default: 182 | freq = 0U; 183 | break; 184 | } 185 | } 186 | /* Pre_Periph_clk ---> Periph_clk */ 187 | else 188 | { 189 | switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) 190 | { 191 | /* PLL2 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ 192 | case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): 193 | freq = PLL2MainClock; 194 | break; 195 | 196 | /* PLL3 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ 197 | case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): 198 | freq = PLL3MainClock / ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) * 18U; 199 | break; 200 | 201 | /* PLL2 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ 202 | case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): 203 | freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) * 18U; 204 | break; 205 | 206 | /* PLL6 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ 207 | case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): 208 | freq = 500000000U; 209 | break; 210 | 211 | default: 212 | freq = 0U; 213 | break; 214 | } 215 | } 216 | 217 | SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U)); 218 | 219 | } 220 | 221 | /* ---------------------------------------------------------------------------- 222 | -- SystemInitHook() 223 | ---------------------------------------------------------------------------- */ 224 | 225 | __attribute__ ((weak)) void SystemInitHook (void) { 226 | /* Void implementation of the weak function. */ 227 | } 228 | -------------------------------------------------------------------------------- /test/pit_imxrt1011/system_MIMXRT1011.h: -------------------------------------------------------------------------------- 1 | /* 2 | ** ################################################################### 3 | ** Processors: MIMXRT1011CAE4A 4 | ** MIMXRT1011DAE5A 5 | ** 6 | ** Compilers: Freescale C/C++ for Embedded ARM 7 | ** GNU C Compiler 8 | ** IAR ANSI C/C++ Compiler for ARM 9 | ** Keil ARM C/C++ Compiler 10 | ** MCUXpresso Compiler 11 | ** 12 | ** Reference manual: IMXRT1010RM Rev.0, 09/2019 13 | ** Version: rev. 1.1, 2019-08-06 14 | ** Build: b191119 15 | ** 16 | ** Abstract: 17 | ** Provides a system configuration function and a global variable that 18 | ** contains the system frequency. It configures the device and initializes 19 | ** the oscillator (PLL) that is part of the microcontroller device. 20 | ** 21 | ** Copyright 2016 Freescale Semiconductor, Inc. 22 | ** Copyright 2016-2019 NXP 23 | ** All rights reserved. 24 | ** 25 | ** SPDX-License-Identifier: BSD-3-Clause 26 | ** 27 | ** http: www.nxp.com 28 | ** mail: support@nxp.com 29 | ** 30 | ** Revisions: 31 | ** - rev. 0.1 (2019-02-14) 32 | ** Initial version. 33 | ** - rev. 1.0 (2019-08-01) 34 | ** Rev.0 Header GA 35 | ** - rev. 1.1 (2019-08-06) 36 | ** Update header files to align with IMXRT1010RM Rev.B. 37 | ** 38 | ** ################################################################### 39 | */ 40 | 41 | /*! 42 | * @file MIMXRT1011 43 | * @version 1.1 44 | * @date 2019-08-06 45 | * @brief Device specific configuration file for MIMXRT1011 (header file) 46 | * 47 | * Provides a system configuration function and a global variable that contains 48 | * the system frequency. It configures the device and initializes the oscillator 49 | * (PLL) that is part of the microcontroller device. 50 | */ 51 | 52 | #ifndef _SYSTEM_MIMXRT1011_H_ 53 | #define _SYSTEM_MIMXRT1011_H_ /**< Symbol preventing repeated inclusion */ 54 | 55 | #ifdef __cplusplus 56 | extern "C" { 57 | #endif 58 | 59 | #include 60 | 61 | 62 | #ifndef DISABLE_WDOG 63 | #define DISABLE_WDOG 1 64 | #endif 65 | 66 | /* Define clock source values */ 67 | 68 | #define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */ 69 | 70 | #define DEFAULT_SYSTEM_CLOCK 297000000UL /* Default System clock value */ 71 | 72 | 73 | /** 74 | * @brief System clock frequency (core clock) 75 | * 76 | * The system clock frequency supplied to the SysTick timer and the processor 77 | * core clock. This variable can be used by the user application to setup the 78 | * SysTick timer or configure other parameters. It may also be used by debugger to 79 | * query the frequency of the debug timer or configure the trace clock speed 80 | * SystemCoreClock is initialized with a correct predefined value. 81 | */ 82 | extern uint32_t SystemCoreClock; 83 | 84 | /** 85 | * @brief Setup the microcontroller system. 86 | * 87 | * Typically this function configures the oscillator (PLL) that is part of the 88 | * microcontroller device. For systems with variable clock speed it also updates 89 | * the variable SystemCoreClock. SystemInit is called from startup_device file. 90 | */ 91 | void SystemInit (void); 92 | 93 | /** 94 | * @brief Updates the SystemCoreClock variable. 95 | * 96 | * It must be called whenever the core clock is changed during program 97 | * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates 98 | * the current core clock. 99 | */ 100 | void SystemCoreClockUpdate (void); 101 | 102 | /** 103 | * @brief SystemInit function hook. 104 | * 105 | * This weak function allows to call specific initialization code during the 106 | * SystemInit() execution.This can be used when an application specific code needs 107 | * to be called as close to the reset entry as possible (for example the Multicore 108 | * Manager MCMGR_EarlyInit() function call). 109 | * NOTE: No global r/w variables can be used in this hook function because the 110 | * initialization of these variables happens after this function. 111 | */ 112 | void SystemInitHook (void); 113 | 114 | #ifdef __cplusplus 115 | } 116 | #endif 117 | 118 | #endif /* _SYSTEM_MIMXRT1011_H_ */ 119 | -------------------------------------------------------------------------------- /test/systick_imxrt1011/MIMXRT1011_features.h: -------------------------------------------------------------------------------- 1 | /* 2 | ** ################################################################### 3 | ** Version: rev. 1.0, 2019-08-01 4 | ** Build: b200921 5 | ** 6 | ** Abstract: 7 | ** Chip specific module features. 8 | ** 9 | ** Copyright 2016 Freescale Semiconductor, Inc. 10 | ** Copyright 2016-2020 NXP 11 | ** All rights reserved. 12 | ** 13 | ** SPDX-License-Identifier: BSD-3-Clause 14 | ** 15 | ** http: www.nxp.com 16 | ** mail: support@nxp.com 17 | ** 18 | ** Revisions: 19 | ** - rev. 0.1 (2019-02-14) 20 | ** Initial version. 21 | ** - rev. 1.0 (2019-08-01) 22 | ** Rev.0 Header GA 23 | ** 24 | ** ################################################################### 25 | */ 26 | 27 | #ifndef _MIMXRT1011_FEATURES_H_ 28 | #define _MIMXRT1011_FEATURES_H_ 29 | 30 | /* SOC module features */ 31 | 32 | /* @brief ADC availability on the SoC. */ 33 | #define FSL_FEATURE_SOC_ADC_COUNT (1) 34 | /* @brief AIPSTZ availability on the SoC. */ 35 | #define FSL_FEATURE_SOC_AIPSTZ_COUNT (2) 36 | /* @brief AOI availability on the SoC. */ 37 | #define FSL_FEATURE_SOC_AOI_COUNT (1) 38 | /* @brief CCM availability on the SoC. */ 39 | #define FSL_FEATURE_SOC_CCM_COUNT (1) 40 | /* @brief CCM_ANALOG availability on the SoC. */ 41 | #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) 42 | /* @brief DCDC availability on the SoC. */ 43 | #define FSL_FEATURE_SOC_DCDC_COUNT (1) 44 | /* @brief DCP availability on the SoC. */ 45 | #define FSL_FEATURE_SOC_DCP_COUNT (1) 46 | /* @brief DMAMUX availability on the SoC. */ 47 | #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 48 | /* @brief EDMA availability on the SoC. */ 49 | #define FSL_FEATURE_SOC_EDMA_COUNT (1) 50 | /* @brief EWM availability on the SoC. */ 51 | #define FSL_FEATURE_SOC_EWM_COUNT (1) 52 | /* @brief FLEXIO availability on the SoC. */ 53 | #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) 54 | /* @brief FLEXRAM availability on the SoC. */ 55 | #define FSL_FEATURE_SOC_FLEXRAM_COUNT (1) 56 | /* @brief FLEXSPI availability on the SoC. */ 57 | #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) 58 | /* @brief GPC availability on the SoC. */ 59 | #define FSL_FEATURE_SOC_GPC_COUNT (1) 60 | /* @brief GPT availability on the SoC. */ 61 | #define FSL_FEATURE_SOC_GPT_COUNT (2) 62 | /* @brief I2S availability on the SoC. */ 63 | #define FSL_FEATURE_SOC_I2S_COUNT (2) 64 | /* @brief IGPIO availability on the SoC. */ 65 | #define FSL_FEATURE_SOC_IGPIO_COUNT (3) 66 | /* @brief IOMUXC availability on the SoC. */ 67 | #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) 68 | /* @brief IOMUXC_GPR availability on the SoC. */ 69 | #define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) 70 | /* @brief IOMUXC_SNVS availability on the SoC. */ 71 | #define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1) 72 | /* @brief KPP availability on the SoC. */ 73 | #define FSL_FEATURE_SOC_KPP_COUNT (1) 74 | /* @brief LPI2C availability on the SoC. */ 75 | #define FSL_FEATURE_SOC_LPI2C_COUNT (2) 76 | /* @brief LPSPI availability on the SoC. */ 77 | #define FSL_FEATURE_SOC_LPSPI_COUNT (2) 78 | /* @brief LPUART availability on the SoC. */ 79 | #define FSL_FEATURE_SOC_LPUART_COUNT (4) 80 | /* @brief OCOTP availability on the SoC. */ 81 | #define FSL_FEATURE_SOC_OCOTP_COUNT (1) 82 | /* @brief OTFAD availability on the SoC. */ 83 | #define FSL_FEATURE_SOC_OTFAD_COUNT (1) 84 | /* @brief PIT availability on the SoC. */ 85 | #define FSL_FEATURE_SOC_PIT_COUNT (1) 86 | /* @brief PMU availability on the SoC. */ 87 | #define FSL_FEATURE_SOC_PMU_COUNT (1) 88 | /* @brief PWM availability on the SoC. */ 89 | #define FSL_FEATURE_SOC_PWM_COUNT (1) 90 | /* @brief ROMC availability on the SoC. */ 91 | #define FSL_FEATURE_SOC_ROMC_COUNT (1) 92 | /* @brief SNVS availability on the SoC. */ 93 | #define FSL_FEATURE_SOC_SNVS_COUNT (1) 94 | /* @brief SPDIF availability on the SoC. */ 95 | #define FSL_FEATURE_SOC_SPDIF_COUNT (1) 96 | /* @brief SRC availability on the SoC. */ 97 | #define FSL_FEATURE_SOC_SRC_COUNT (1) 98 | /* @brief TEMPMON availability on the SoC. */ 99 | #define FSL_FEATURE_SOC_TEMPMON_COUNT (1) 100 | /* @brief TRNG availability on the SoC. */ 101 | #define FSL_FEATURE_SOC_TRNG_COUNT (1) 102 | /* @brief USBHS availability on the SoC. */ 103 | #define FSL_FEATURE_SOC_USBHS_COUNT (1) 104 | /* @brief USBNC availability on the SoC. */ 105 | #define FSL_FEATURE_SOC_USBNC_COUNT (1) 106 | /* @brief USBPHY availability on the SoC. */ 107 | #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 108 | /* @brief USB_ANALOG availability on the SoC. */ 109 | #define FSL_FEATURE_SOC_USB_ANALOG_COUNT (1) 110 | /* @brief WDOG availability on the SoC. */ 111 | #define FSL_FEATURE_SOC_WDOG_COUNT (2) 112 | /* @brief XBARA availability on the SoC. */ 113 | #define FSL_FEATURE_SOC_XBARA_COUNT (1) 114 | /* @brief XTALOSC24M availability on the SoC. */ 115 | #define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1) 116 | 117 | /* ADC module features */ 118 | 119 | /* @brief Remove Hardware Trigger feature. */ 120 | #define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0) 121 | /* @brief Remove ALT Clock selection feature. */ 122 | #define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (0) 123 | /* @brief Conversion control count (related to number of registers HCn and Rn). */ 124 | #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (8) 125 | 126 | /* ADC_ETC module features */ 127 | 128 | /* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */ 129 | #define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1) 130 | /* @brief Has TRIGm_CHAIN_a_b IEn_EN. */ 131 | #define FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN (1) 132 | 133 | /* AOI module features */ 134 | 135 | /* @brief Maximum value of input mux. */ 136 | #define FSL_FEATURE_AOI_MODULE_INPUTS (4) 137 | /* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ 138 | #define FSL_FEATURE_AOI_EVENT_COUNT (4) 139 | 140 | /* CCM module features */ 141 | 142 | /* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */ 143 | #define FSL_FEATURE_CCM_HAS_ERRATA_50235 (0) 144 | 145 | /* DCDC module features */ 146 | 147 | /* @brief Has CTRL register (register CTRL0/1). */ 148 | #define FSL_FEATURE_DCDC_HAS_CTRL_REG (0) 149 | /* @brief DCDC VDD output count. */ 150 | #define FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT (1) 151 | /* @brief Has no current alert function (register bit field REG0[CURRENT_ALERT_RESET]). */ 152 | #define FSL_FEATURE_DCDC_HAS_NO_CURRENT_ALERT_FUNC (0) 153 | /* @brief Has switching converter differential mode (register bit field REG1[LOOPCTRL_EN_DF_HYST]). */ 154 | #define FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE (0) 155 | /* @brief Has register bit field REG0[REG_DCDC_IN_DET]. */ 156 | #define FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET (0) 157 | /* @brief Has no register bit field REG0[EN_LP_OVERLOAD_SNS]. */ 158 | #define FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS (0) 159 | /* @brief Has register bit field REG3[REG_FBK_SEL]). */ 160 | #define FSL_FEATURE_DCDC_HAS_REG3_FBK_SEL (0) 161 | 162 | /* EDMA module features */ 163 | 164 | /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 165 | #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) 166 | /* @brief Total number of DMA channels on all modules. */ 167 | #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (16) 168 | /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 169 | #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 170 | /* @brief Has DMA_Error interrupt vector. */ 171 | #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 172 | /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 173 | #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) 174 | /* @brief Channel IRQ entry shared offset. */ 175 | #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (0) 176 | /* @brief If 8 bytes transfer supported. */ 177 | #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) 178 | /* @brief If 16 bytes transfer supported. */ 179 | #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0) 180 | /* @brief If 32 bytes transfer supported. */ 181 | #define FSL_FEATURE_EDMA_SUPPORT_32_BYTES_TRANSFER (1) 182 | 183 | /* DMAMUX module features */ 184 | 185 | /* @brief Number of DMA channels (related to number of register CHCFGn). */ 186 | #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) 187 | /* @brief Total number of DMA channels on all modules. */ 188 | #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (16) 189 | /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 190 | #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 191 | /* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */ 192 | #define FSL_FEATURE_DMAMUX_HAS_A_ON (1) 193 | /* @brief Register CHCFGn width. */ 194 | #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (32) 195 | 196 | /* EWM module features */ 197 | 198 | /* @brief Has clock select (register CLKCTRL). */ 199 | #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) 200 | /* @brief Has clock prescaler (register CLKPRESCALER). */ 201 | #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 202 | 203 | /* FLEXIO module features */ 204 | 205 | /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 206 | #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 207 | /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 208 | #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) 209 | /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 210 | #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) 211 | /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 212 | #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) 213 | /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 214 | #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) 215 | /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 216 | #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) 217 | /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 218 | #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) 219 | /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 220 | #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) 221 | /* @brief Reset value of the FLEXIO_VERID register */ 222 | #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) 223 | /* @brief Reset value of the FLEXIO_PARAM register */ 224 | #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200808) 225 | /* @brief Flexio DMA request base channel */ 226 | #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) 227 | 228 | /* FLEXRAM module features */ 229 | 230 | /* @brief Bank size */ 231 | #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768) 232 | /* @brief Total Bank numbers */ 233 | #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (4) 234 | /* @brief Has FLEXRAM_MAGIC_ADDR. */ 235 | #define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (1) 236 | 237 | /* FLEXSPI module features */ 238 | 239 | /* @brief FlexSPI AHB buffer count */ 240 | #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4) 241 | /* @brief FlexSPI has no data learn. */ 242 | #define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1) 243 | /* @brief There is AHBBUSERROREN bit in INTEN register. */ 244 | #define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (1) 245 | /* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ 246 | #define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) 247 | 248 | /* GPC module features */ 249 | 250 | /* @brief Has DVFS0 Change Request. */ 251 | #define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0) 252 | /* @brief Has GPC interrupt/event masking. */ 253 | #define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0) 254 | /* @brief Has L2 cache power control. */ 255 | #define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0) 256 | /* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */ 257 | #define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1) 258 | /* @brief Has VADC power control. */ 259 | #define FSL_FEATURE_GPC_HAS_CNTR_VADC (0) 260 | /* @brief Has Display power control. */ 261 | #define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0) 262 | /* @brief Supports IRQ 0-31. */ 263 | #define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1) 264 | 265 | /* IGPIO module features */ 266 | 267 | /* @brief Has data register set DR_SET. */ 268 | #define FSL_FEATURE_IGPIO_HAS_DR_SET (1) 269 | /* @brief Has data register clear DR_CLEAR. */ 270 | #define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1) 271 | /* @brief Has data register toggle DR_TOGGLE. */ 272 | #define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1) 273 | 274 | /* LPI2C module features */ 275 | 276 | /* @brief Has separate DMA RX and TX requests. */ 277 | #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) 278 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 279 | #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) 280 | 281 | /* LPSPI module features */ 282 | 283 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 284 | #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16) 285 | /* @brief Has separate DMA RX and TX requests. */ 286 | #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 287 | 288 | /* LPUART module features */ 289 | 290 | /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 291 | #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 292 | /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 293 | #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 294 | /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 295 | #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 296 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 297 | #define FSL_FEATURE_LPUART_HAS_FIFO (1) 298 | /* @brief Has 32-bit register MODIR */ 299 | #define FSL_FEATURE_LPUART_HAS_MODIR (1) 300 | /* @brief Hardware flow control (RTS, CTS) is supported. */ 301 | #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 302 | /* @brief Infrared (modulation) is supported. */ 303 | #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 304 | /* @brief 2 bits long stop bit is available. */ 305 | #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 306 | /* @brief If 10-bit mode is supported. */ 307 | #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 308 | /* @brief If 7-bit mode is supported. */ 309 | #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) 310 | /* @brief Baud rate fine adjustment is available. */ 311 | #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 312 | /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 313 | #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 314 | /* @brief Baud rate oversampling is available. */ 315 | #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 316 | /* @brief Baud rate oversampling is available. */ 317 | #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 318 | /* @brief Peripheral type. */ 319 | #define FSL_FEATURE_LPUART_IS_SCI (1) 320 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 321 | #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) 322 | /* @brief Supports two match addresses to filter incoming frames. */ 323 | #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 324 | /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 325 | #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 326 | /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 327 | #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 328 | /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 329 | #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 330 | /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 331 | #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 332 | /* @brief Has improved smart card (ISO7816 protocol) support. */ 333 | #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 334 | /* @brief Has local operation network (CEA709.1-B protocol) support. */ 335 | #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 336 | /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 337 | #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 338 | /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 339 | #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 340 | /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 341 | #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 342 | /* @brief Has separate DMA RX and TX requests. */ 343 | #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 344 | /* @brief Has separate RX and TX interrupts. */ 345 | #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 346 | /* @brief Has LPAURT_PARAM. */ 347 | #define FSL_FEATURE_LPUART_HAS_PARAM (1) 348 | /* @brief Has LPUART_VERID. */ 349 | #define FSL_FEATURE_LPUART_HAS_VERID (1) 350 | /* @brief Has LPUART_GLOBAL. */ 351 | #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) 352 | /* @brief Has LPUART_PINCFG. */ 353 | #define FSL_FEATURE_LPUART_HAS_PINCFG (1) 354 | 355 | /* interrupt module features */ 356 | 357 | /* @brief Lowest interrupt request number. */ 358 | #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 359 | /* @brief Highest interrupt request number. */ 360 | #define FSL_FEATURE_INTERRUPT_IRQ_MAX (79) 361 | 362 | /* OCOTP module features */ 363 | 364 | /* @brief Has timing control, (register TIMING). */ 365 | #define FSL_FEATURE_OCOTP_HAS_TIMING_CTRL (1) 366 | /* @brief Support lock eFuse word write lock, (CTRL[WORDLOCK]). */ 367 | #define FSL_FEATURE_OCOTP_HAS_WORDLOCK (0) 368 | /* @brief Has status register. (Register HW_OCOTP_OUT_STATUS0). */ 369 | #define FSL_FEATURE_OCOTP_HAS_STATUS (0) 370 | 371 | /* OTFAD module features */ 372 | 373 | /* @brief OTFAD has Security Violation Mode (SVM) */ 374 | #define FSL_FEATURE_OTFAD_HAS_SVM_MODE (1) 375 | /* @brief OTFAD has Key Blob Processing */ 376 | #define FSL_FEATURE_OTFAD_HAS_KEYBLOB_PROCESSING (1) 377 | /* @brief OTFAD has interrupt request enable */ 378 | #define FSL_FEATURE_OTFAD_HAS_HAS_IRQ_ENABLE (1) 379 | /* @brief OTFAD has Force Error */ 380 | #define FSL_FEATURE_OTFAD_HAS_FORCE_ERR (1) 381 | 382 | /* PIT module features */ 383 | 384 | /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 385 | #define FSL_FEATURE_PIT_TIMER_COUNT (4) 386 | /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 387 | #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 388 | /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 389 | #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 390 | /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 391 | #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) 392 | /* @brief Has timer enable control. */ 393 | #define FSL_FEATURE_PIT_HAS_MDIS (1) 394 | 395 | /* PWM module features */ 396 | 397 | /* @brief If (e)FlexPWM has module A channels (outputs). */ 398 | #define FSL_FEATURE_PWM_HAS_CHANNELA (1) 399 | /* @brief If (e)FlexPWM has module B channels (outputs). */ 400 | #define FSL_FEATURE_PWM_HAS_CHANNELB (1) 401 | /* @brief If (e)FlexPWM has module X channels (outputs). */ 402 | #define FSL_FEATURE_PWM_HAS_CHANNELX (1) 403 | /* @brief If (e)FlexPWM has fractional feature. */ 404 | #define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) 405 | /* @brief If (e)FlexPWM has mux trigger source select bit field. */ 406 | #define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) 407 | /* @brief Number of submodules in each (e)FlexPWM module. */ 408 | #define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) 409 | /* @brief Number of fault channel in each (e)FlexPWM module. */ 410 | #define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) 411 | 412 | /* RTWDOG module features */ 413 | 414 | /* @brief Watchdog is available. */ 415 | #define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1) 416 | /* @brief RTWDOG_CNT can be 32-bit written. */ 417 | #define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1) 418 | 419 | /* SAI module features */ 420 | 421 | /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 422 | #define FSL_FEATURE_SAI_FIFO_COUNT (32) 423 | /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 424 | #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ 425 | (((x) == SAI1) ? (2) : \ 426 | (((x) == SAI3) ? (1) : (-1))) 427 | /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 428 | #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) 429 | /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 430 | #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) 431 | /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 432 | #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) 433 | /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 434 | #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) 435 | /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 436 | #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) 437 | /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 438 | #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 439 | /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 440 | #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) 441 | /* @brief Interrupt source number */ 442 | #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) 443 | /* @brief Has register of MCR. */ 444 | #define FSL_FEATURE_SAI_HAS_MCR (0) 445 | /* @brief Has bit field MICS of the MCR register. */ 446 | #define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) 447 | /* @brief Has register of MDR */ 448 | #define FSL_FEATURE_SAI_HAS_MDR (0) 449 | /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ 450 | #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) 451 | /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ 452 | #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) 453 | /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ 454 | #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) 455 | 456 | /* SNVS module features */ 457 | 458 | /* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ 459 | #define FSL_FEATURE_SNVS_HAS_SRTC (1) 460 | 461 | /* SRC module features */ 462 | 463 | /* @brief There is MASK_WDOG3_RST bit in SCR register. */ 464 | #define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1) 465 | /* @brief There is MIX_RST_STRCH bit in SCR register. */ 466 | #define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0) 467 | /* @brief There is DBG_RST_MSK_PG bit in SCR register. */ 468 | #define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1) 469 | /* @brief There is WDOG3_RST_OPTN bit in SCR register. */ 470 | #define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0) 471 | /* @brief There is CORES_DBG_RST bit in SCR register. */ 472 | #define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0) 473 | /* @brief There is MTSR bit in SCR register. */ 474 | #define FSL_FEATURE_SRC_HAS_SCR_MTSR (0) 475 | /* @brief There is CORE0_DBG_RST bit in SCR register. */ 476 | #define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1) 477 | /* @brief There is CORE0_RST bit in SCR register. */ 478 | #define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1) 479 | /* @brief There is LOCKUP_RST bit in SCR register. */ 480 | #define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (1) 481 | /* @brief There is SWRC bit in SCR register. */ 482 | #define FSL_FEATURE_SRC_HAS_SCR_SWRC (0) 483 | /* @brief There is EIM_RST bit in SCR register. */ 484 | #define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0) 485 | /* @brief There is LUEN bit in SCR register. */ 486 | #define FSL_FEATURE_SRC_HAS_SCR_LUEN (0) 487 | /* @brief There is no WRBC bit in SCR register. */ 488 | #define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1) 489 | /* @brief There is no WRE bit in SCR register. */ 490 | #define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1) 491 | /* @brief There is SISR register. */ 492 | #define FSL_FEATURE_SRC_HAS_SISR (0) 493 | /* @brief There is RESET_OUT bit in SRSR register. */ 494 | #define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0) 495 | /* @brief There is WDOG3_RST_B bit in SRSR register. */ 496 | #define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1) 497 | /* @brief There is JTAG_SW_RST bit in SRSR register. */ 498 | #define FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST (1) 499 | /* @brief There is SW bit in SRSR register. */ 500 | #define FSL_FEATURE_SRC_HAS_SRSR_SW (0) 501 | /* @brief There is IPP_USER_RESET_B bit in SRSR register. */ 502 | #define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1) 503 | /* @brief There is SNVS bit in SRSR register. */ 504 | #define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0) 505 | /* @brief There is CSU_RESET_B bit in SRSR register. */ 506 | #define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1) 507 | /* @brief There is LOCKUP bit in SRSR register. */ 508 | #define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (1) 509 | /* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */ 510 | #define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (0) 511 | /* @brief There is POR bit in SRSR register. */ 512 | #define FSL_FEATURE_SRC_HAS_SRSR_POR (0) 513 | /* @brief There is IPP_RESET_B bit in SRSR register. */ 514 | #define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1) 515 | /* @brief There is no WBI bit in SCR register. */ 516 | #define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1) 517 | 518 | /* SCB module features */ 519 | 520 | /* @brief L1 ICACHE line size in byte. */ 521 | #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) 522 | /* @brief L1 DCACHE line size in byte. */ 523 | #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) 524 | 525 | /* TRNG module features */ 526 | 527 | /* @brief TRNG has no TRNG_ACC bitfield. */ 528 | #define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) 529 | 530 | /* USBHS module features */ 531 | 532 | /* @brief EHCI module instance count */ 533 | #define FSL_FEATURE_USBHS_EHCI_COUNT (1) 534 | /* @brief Number of endpoints supported */ 535 | #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) 536 | 537 | /* USBPHY module features */ 538 | 539 | /* @brief USBPHY contain DCD analog module */ 540 | #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) 541 | /* @brief USBPHY has register TRIM_OVERRIDE_EN */ 542 | #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (0) 543 | /* @brief USBPHY is 28FDSOI */ 544 | #define FSL_FEATURE_USBPHY_28FDSOI (0) 545 | 546 | /* XBARA module features */ 547 | 548 | /* @brief Number of interrupt requests. */ 549 | #define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4) 550 | 551 | #endif /* _MIMXRT1011_FEATURES_H_ */ 552 | 553 | -------------------------------------------------------------------------------- /test/systick_imxrt1011/MIMXRT1011xxxxx_flexspi_nor.icf: -------------------------------------------------------------------------------- 1 | /* 2 | ** ################################################################### 3 | ** Processors: MIMXRT1011CAE4A 4 | ** MIMXRT1011DAE5A 5 | ** 6 | ** Compiler: IAR ANSI C/C++ Compiler for ARM 7 | ** Reference manual: IMXRT1010RM Rev.A, 03/2019 8 | ** Version: rev. 0.1, 2019-02-14 9 | ** Build: b190912 10 | ** 11 | ** Abstract: 12 | ** Linker file for the IAR ANSI C/C++ Compiler for ARM 13 | ** 14 | ** Copyright 2016 Freescale Semiconductor, Inc. 15 | ** Copyright 2016-2019 NXP 16 | ** All rights reserved. 17 | ** 18 | ** SPDX-License-Identifier: BSD-3-Clause 19 | ** 20 | ** http: www.nxp.com 21 | ** mail: support@nxp.com 22 | ** 23 | ** ################################################################### 24 | */ 25 | 26 | define symbol m_interrupts_start = 0x60002000; 27 | define symbol m_interrupts_end = 0x600023FF; 28 | 29 | define symbol m_text_start = 0x60002400; 30 | define symbol m_text_end = 0x60FFFFFF; 31 | 32 | define symbol m_text2_start = 0x00000000; 33 | define symbol m_text2_end = 0x00007FFF; 34 | 35 | define symbol m_data_start = 0x20000000; 36 | define symbol m_data_end = 0x20007FFF; 37 | 38 | define symbol m_data2_start = 0x20200000; 39 | define symbol m_data2_end = 0x2020FFFF; 40 | 41 | define exported symbol m_boot_hdr_conf_start = 0x60000400; 42 | define symbol m_boot_hdr_ivt_start = 0x60001000; 43 | define symbol m_boot_hdr_boot_data_start = 0x60001020; 44 | define symbol m_boot_hdr_dcd_data_start = 0x60001030; 45 | 46 | /* Sizes */ 47 | if (isdefinedsymbol(__stack_size__)) { 48 | define symbol __size_cstack__ = __stack_size__; 49 | } else { 50 | define symbol __size_cstack__ = 0x0400; 51 | } 52 | 53 | if (isdefinedsymbol(__heap_size__)) { 54 | define symbol __size_heap__ = __heap_size__; 55 | } else { 56 | define symbol __size_heap__ = 0x0400; 57 | } 58 | 59 | define exported symbol __NCACHE_REGION_START = m_data2_start; 60 | define exported symbol __NCACHE_REGION_SIZE = 0x0; 61 | 62 | define exported symbol __VECTOR_TABLE = m_interrupts_start; 63 | define exported symbol __VECTOR_RAM = m_interrupts_start; 64 | define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; 65 | 66 | define memory mem with size = 4G; 67 | define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] 68 | | mem:[from m_text_start to m_text_end]; 69 | define region TEXT2_region = mem:[from m_text2_start to m_text2_end]; 70 | define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; 71 | define region DATA2_region = mem:[from m_data2_start to m_data2_end]; 72 | define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; 73 | 74 | define block CSTACK with alignment = 8, size = __size_cstack__ { }; 75 | define block HEAP with alignment = 8, size = __size_heap__ { }; 76 | define block RW { readwrite }; 77 | define block ZI { zi }; 78 | define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; 79 | define block QACCESS_FUNC { section CodeQuickAccess }; 80 | 81 | initialize by copy { readwrite, section .textrw, section CodeQuickAccess }; 82 | do not initialize { section .noinit }; 83 | 84 | place at address mem: m_interrupts_start { readonly section .intvec }; 85 | 86 | place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; 87 | place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; 88 | place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; 89 | place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; 90 | 91 | keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; 92 | 93 | place in TEXT_region { readonly }; 94 | place in DATA_region { block RW }; 95 | place in DATA_region { block ZI }; 96 | place in DATA_region { last block HEAP }; 97 | place in DATA_region { block NCACHE_VAR }; 98 | place in CSTACK_region { block CSTACK }; 99 | place in TEXT2_region { section .textrw}; 100 | place in TEXT2_region { block QACCESS_FUNC }; 101 | -------------------------------------------------------------------------------- /test/systick_imxrt1011/MIMXRT1011xxxxx_ram.icf: -------------------------------------------------------------------------------- 1 | /* 2 | ** ################################################################### 3 | ** Processors: MIMXRT1011CAE4A 4 | ** MIMXRT1011DAE5A 5 | ** 6 | ** Compiler: IAR ANSI C/C++ Compiler for ARM 7 | ** Reference manual: IMXRT1010RM Rev.A, 03/2019 8 | ** Version: rev. 0.1, 2019-02-14 9 | ** Build: b190912 10 | ** 11 | ** Abstract: 12 | ** Linker file for the IAR ANSI C/C++ Compiler for ARM 13 | ** 14 | ** Copyright 2016 Freescale Semiconductor, Inc. 15 | ** Copyright 2016-2019 NXP 16 | ** All rights reserved. 17 | ** 18 | ** SPDX-License-Identifier: BSD-3-Clause 19 | ** 20 | ** http: www.nxp.com 21 | ** mail: support@nxp.com 22 | ** 23 | ** ################################################################### 24 | */ 25 | 26 | define symbol m_interrupts_start = 0x00000000; 27 | define symbol m_interrupts_end = 0x000003FF; 28 | 29 | define symbol m_text_start = 0x00000400; 30 | define symbol m_text_end = 0x00007FFF; 31 | 32 | define symbol m_data_start = 0x20000000; 33 | define symbol m_data_end = 0x20007FFF; 34 | 35 | define symbol m_data2_start = 0x20200000; 36 | define symbol m_data2_end = 0x2020FFFF; 37 | 38 | /* Sizes */ 39 | if (isdefinedsymbol(__stack_size__)) { 40 | define symbol __size_cstack__ = __stack_size__; 41 | } else { 42 | define symbol __size_cstack__ = 0x0400; 43 | } 44 | 45 | if (isdefinedsymbol(__heap_size__)) { 46 | define symbol __size_heap__ = __heap_size__; 47 | } else { 48 | define symbol __size_heap__ = 0x0400; 49 | } 50 | 51 | define exported symbol __NCACHE_REGION_START = m_data2_start; 52 | define exported symbol __NCACHE_REGION_SIZE = 0x0; 53 | 54 | define exported symbol __VECTOR_TABLE = m_interrupts_start; 55 | define exported symbol __VECTOR_RAM = m_interrupts_start; 56 | define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; 57 | 58 | define memory mem with size = 4G; 59 | define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] 60 | | mem:[from m_text_start to m_text_end]; 61 | define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; 62 | define region DATA2_region = mem:[from m_data2_start to m_data2_end]; 63 | define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; 64 | 65 | define block CSTACK with alignment = 8, size = __size_cstack__ { }; 66 | define block HEAP with alignment = 8, size = __size_heap__ { }; 67 | define block RW { readwrite }; 68 | define block ZI { zi }; 69 | define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; 70 | 71 | initialize by copy { readwrite, section .textrw }; 72 | do not initialize { section .noinit }; 73 | 74 | place at address mem: m_interrupts_start { readonly section .intvec }; 75 | 76 | place in TEXT_region { readonly }; 77 | place in DATA_region { block RW }; 78 | place in DATA_region { block ZI }; 79 | place in DATA_region { last block HEAP }; 80 | place in DATA_region { block NCACHE_VAR }; 81 | place in CSTACK_region { block CSTACK }; 82 | -------------------------------------------------------------------------------- /test/systick_imxrt1011/fsl_device_registers.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2014-2016 Freescale Semiconductor, Inc. 3 | * Copyright 2016-2019 NXP 4 | * All rights reserved. 5 | * 6 | * SPDX-License-Identifier: BSD-3-Clause 7 | * 8 | */ 9 | 10 | #ifndef __FSL_DEVICE_REGISTERS_H__ 11 | #define __FSL_DEVICE_REGISTERS_H__ 12 | 13 | /* 14 | * Include the cpu specific register header files. 15 | * 16 | * The CPU macro should be declared in the project or makefile. 17 | */ 18 | #if (defined(CPU_MIMXRT1011CAE4A) || defined(CPU_MIMXRT1011DAE5A)) 19 | 20 | #define MIMXRT1011_SERIES 21 | 22 | /* CMSIS-style register definitions */ 23 | #include "MIMXRT1011.h" 24 | /* CPU specific feature definitions */ 25 | #include "MIMXRT1011_features.h" 26 | 27 | #else 28 | #error "No valid CPU defined!" 29 | #endif 30 | 31 | #endif /* __FSL_DEVICE_REGISTERS_H__ */ 32 | 33 | /******************************************************************************* 34 | * EOF 35 | ******************************************************************************/ 36 | -------------------------------------------------------------------------------- /test/systick_imxrt1011/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * SPDX-License-Identifier: BSD-3-Clause 3 | */ 4 | #include "microseconds.h" 5 | /******************************************************************************* 6 | * Definitions 7 | ******************************************************************************/ 8 | 9 | 10 | /******************************************************************************* 11 | * Variables 12 | ******************************************************************************/ 13 | 14 | 15 | /******************************************************************************* 16 | * Prototypes 17 | ******************************************************************************/ 18 | extern void SystemCoreClockUpdate (void); 19 | 20 | /******************************************************************************* 21 | * Code 22 | ******************************************************************************/ 23 | /*! 24 | * @brief Main function 25 | */ 26 | int main(void) 27 | { 28 | SystemCoreClockUpdate(); 29 | 30 | microseconds_init(); 31 | // Delay 5s 32 | microseconds_delay(5000000); 33 | // Set delay time to 5s 34 | microseconds_set_delay(5000000); 35 | // wait 5s timeout 36 | while(!microseconds_is_timeout()); 37 | 38 | microseconds_shutdown(); 39 | 40 | while (1) 41 | { 42 | } 43 | } 44 | -------------------------------------------------------------------------------- /test/systick_imxrt1011/microseconds_demo.eww: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | $WS_DIR$\microseconds_demo.ewp 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /test/systick_imxrt1011/system_MIMXRT1011.c: -------------------------------------------------------------------------------- 1 | /* 2 | ** ################################################################### 3 | ** Processors: MIMXRT1011CAE4A 4 | ** MIMXRT1011DAE5A 5 | ** 6 | ** Compilers: Freescale C/C++ for Embedded ARM 7 | ** GNU C Compiler 8 | ** IAR ANSI C/C++ Compiler for ARM 9 | ** Keil ARM C/C++ Compiler 10 | ** MCUXpresso Compiler 11 | ** 12 | ** Reference manual: IMXRT1010RM Rev.0, 09/2019 13 | ** Version: rev. 1.1, 2019-08-06 14 | ** Build: b201016 15 | ** 16 | ** Abstract: 17 | ** Provides a system configuration function and a global variable that 18 | ** contains the system frequency. It configures the device and initializes 19 | ** the oscillator (PLL) that is part of the microcontroller device. 20 | ** 21 | ** Copyright 2016 Freescale Semiconductor, Inc. 22 | ** Copyright 2016-2020 NXP 23 | ** All rights reserved. 24 | ** 25 | ** SPDX-License-Identifier: BSD-3-Clause 26 | ** 27 | ** http: www.nxp.com 28 | ** mail: support@nxp.com 29 | ** 30 | ** Revisions: 31 | ** - rev. 0.1 (2019-02-14) 32 | ** Initial version. 33 | ** - rev. 1.0 (2019-08-01) 34 | ** Rev.0 Header GA 35 | ** - rev. 1.1 (2019-08-06) 36 | ** Update header files to align with IMXRT1010RM Rev.B. 37 | ** 38 | ** ################################################################### 39 | */ 40 | 41 | /*! 42 | * @file MIMXRT1011 43 | * @version 1.1 44 | * @date 2019-08-06 45 | * @brief Device specific configuration file for MIMXRT1011 (implementation file) 46 | * 47 | * Provides a system configuration function and a global variable that contains 48 | * the system frequency. It configures the device and initializes the oscillator 49 | * (PLL) that is part of the microcontroller device. 50 | */ 51 | 52 | #include 53 | #include "fsl_device_registers.h" 54 | 55 | 56 | 57 | /* ---------------------------------------------------------------------------- 58 | -- Core clock 59 | ---------------------------------------------------------------------------- */ 60 | 61 | uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 62 | 63 | /* ---------------------------------------------------------------------------- 64 | -- SystemInit() 65 | ---------------------------------------------------------------------------- */ 66 | 67 | void SystemInit (void) { 68 | #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) 69 | SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ 70 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 71 | SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ 72 | #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 73 | #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ 74 | 75 | #if defined(__MCUXPRESSO) 76 | extern uint32_t g_pfnVectors[]; // Vector table defined in startup code 77 | SCB->VTOR = (uint32_t)g_pfnVectors; 78 | #endif 79 | 80 | /* Disable Watchdog Power Down Counter */ 81 | WDOG1->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK; 82 | WDOG2->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK; 83 | 84 | /* Watchdog disable */ 85 | 86 | #if (DISABLE_WDOG) 87 | if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U) 88 | { 89 | WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK; 90 | } 91 | if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U) 92 | { 93 | WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK; 94 | } 95 | if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U) 96 | { 97 | RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */ 98 | } 99 | else 100 | { 101 | RTWDOG->CNT = 0xC520U; 102 | RTWDOG->CNT = 0xD928U; 103 | } 104 | RTWDOG->TOVAL = 0xFFFF; 105 | RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK; 106 | #endif /* (DISABLE_WDOG) */ 107 | 108 | /* Disable Systick which might be enabled by bootrom */ 109 | if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U) 110 | { 111 | SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; 112 | } 113 | 114 | /* Enable instruction and data caches */ 115 | #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT 116 | if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) { 117 | SCB_EnableICache(); 118 | } 119 | #endif 120 | #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT 121 | if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) { 122 | SCB_EnableDCache(); 123 | } 124 | #endif 125 | 126 | SystemInitHook(); 127 | } 128 | 129 | /* ---------------------------------------------------------------------------- 130 | -- SystemCoreClockUpdate() 131 | ---------------------------------------------------------------------------- */ 132 | 133 | void SystemCoreClockUpdate (void) { 134 | 135 | uint32_t freq; 136 | uint32_t PLL2MainClock; 137 | uint32_t PLL3MainClock; 138 | 139 | /* Check if system pll is bypassed */ 140 | if((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) != 0U) 141 | { 142 | PLL2MainClock = CPU_XTAL_CLK_HZ; 143 | } 144 | else 145 | { 146 | PLL2MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) ? 22U : 20U)); 147 | } 148 | PLL2MainClock += (uint32_t)(((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM))); 149 | 150 | /* Check if usb1 pll is bypassed */ 151 | if((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) != 0U) 152 | { 153 | PLL3MainClock = CPU_XTAL_CLK_HZ; 154 | } 155 | else 156 | { 157 | PLL3MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0U) ? 22U : 20U)); 158 | } 159 | 160 | /* Periph_clk2_clk ---> Periph_clk */ 161 | if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U) 162 | { 163 | switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) 164 | { 165 | /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */ 166 | case CCM_CBCMR_PERIPH_CLK2_SEL(0U): 167 | freq = PLL3MainClock; 168 | break; 169 | 170 | /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */ 171 | case CCM_CBCMR_PERIPH_CLK2_SEL(1U): 172 | freq = CPU_XTAL_CLK_HZ; 173 | break; 174 | 175 | /* Pll2_bypass_clk ---> Periph_clk2_clk ---> Periph_clk ---> Core_clock */ 176 | case CCM_CBCMR_PERIPH_CLK2_SEL(2U): 177 | freq = CPU_XTAL_CLK_HZ; 178 | break; 179 | 180 | case CCM_CBCMR_PERIPH_CLK2_SEL(3U): 181 | default: 182 | freq = 0U; 183 | break; 184 | } 185 | } 186 | /* Pre_Periph_clk ---> Periph_clk */ 187 | else 188 | { 189 | switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) 190 | { 191 | /* PLL2 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ 192 | case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): 193 | freq = PLL2MainClock; 194 | break; 195 | 196 | /* PLL3 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ 197 | case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): 198 | freq = PLL3MainClock / ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT) * 18U; 199 | break; 200 | 201 | /* PLL2 PFD3 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ 202 | case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): 203 | freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT) * 18U; 204 | break; 205 | 206 | /* PLL6 ---> Pre_Periph_clk ---> Periph_clk ---> Core_clock */ 207 | case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): 208 | freq = 500000000U; 209 | break; 210 | 211 | default: 212 | freq = 0U; 213 | break; 214 | } 215 | } 216 | 217 | SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U)); 218 | 219 | } 220 | 221 | /* ---------------------------------------------------------------------------- 222 | -- SystemInitHook() 223 | ---------------------------------------------------------------------------- */ 224 | 225 | __attribute__ ((weak)) void SystemInitHook (void) { 226 | /* Void implementation of the weak function. */ 227 | } 228 | -------------------------------------------------------------------------------- /test/systick_imxrt1011/system_MIMXRT1011.h: -------------------------------------------------------------------------------- 1 | /* 2 | ** ################################################################### 3 | ** Processors: MIMXRT1011CAE4A 4 | ** MIMXRT1011DAE5A 5 | ** 6 | ** Compilers: Freescale C/C++ for Embedded ARM 7 | ** GNU C Compiler 8 | ** IAR ANSI C/C++ Compiler for ARM 9 | ** Keil ARM C/C++ Compiler 10 | ** MCUXpresso Compiler 11 | ** 12 | ** Reference manual: IMXRT1010RM Rev.0, 09/2019 13 | ** Version: rev. 1.1, 2019-08-06 14 | ** Build: b191119 15 | ** 16 | ** Abstract: 17 | ** Provides a system configuration function and a global variable that 18 | ** contains the system frequency. It configures the device and initializes 19 | ** the oscillator (PLL) that is part of the microcontroller device. 20 | ** 21 | ** Copyright 2016 Freescale Semiconductor, Inc. 22 | ** Copyright 2016-2019 NXP 23 | ** All rights reserved. 24 | ** 25 | ** SPDX-License-Identifier: BSD-3-Clause 26 | ** 27 | ** http: www.nxp.com 28 | ** mail: support@nxp.com 29 | ** 30 | ** Revisions: 31 | ** - rev. 0.1 (2019-02-14) 32 | ** Initial version. 33 | ** - rev. 1.0 (2019-08-01) 34 | ** Rev.0 Header GA 35 | ** - rev. 1.1 (2019-08-06) 36 | ** Update header files to align with IMXRT1010RM Rev.B. 37 | ** 38 | ** ################################################################### 39 | */ 40 | 41 | /*! 42 | * @file MIMXRT1011 43 | * @version 1.1 44 | * @date 2019-08-06 45 | * @brief Device specific configuration file for MIMXRT1011 (header file) 46 | * 47 | * Provides a system configuration function and a global variable that contains 48 | * the system frequency. It configures the device and initializes the oscillator 49 | * (PLL) that is part of the microcontroller device. 50 | */ 51 | 52 | #ifndef _SYSTEM_MIMXRT1011_H_ 53 | #define _SYSTEM_MIMXRT1011_H_ /**< Symbol preventing repeated inclusion */ 54 | 55 | #ifdef __cplusplus 56 | extern "C" { 57 | #endif 58 | 59 | #include 60 | 61 | 62 | #ifndef DISABLE_WDOG 63 | #define DISABLE_WDOG 1 64 | #endif 65 | 66 | /* Define clock source values */ 67 | 68 | #define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */ 69 | 70 | #define DEFAULT_SYSTEM_CLOCK 297000000UL /* Default System clock value */ 71 | 72 | 73 | /** 74 | * @brief System clock frequency (core clock) 75 | * 76 | * The system clock frequency supplied to the SysTick timer and the processor 77 | * core clock. This variable can be used by the user application to setup the 78 | * SysTick timer or configure other parameters. It may also be used by debugger to 79 | * query the frequency of the debug timer or configure the trace clock speed 80 | * SystemCoreClock is initialized with a correct predefined value. 81 | */ 82 | extern uint32_t SystemCoreClock; 83 | 84 | /** 85 | * @brief Setup the microcontroller system. 86 | * 87 | * Typically this function configures the oscillator (PLL) that is part of the 88 | * microcontroller device. For systems with variable clock speed it also updates 89 | * the variable SystemCoreClock. SystemInit is called from startup_device file. 90 | */ 91 | void SystemInit (void); 92 | 93 | /** 94 | * @brief Updates the SystemCoreClock variable. 95 | * 96 | * It must be called whenever the core clock is changed during program 97 | * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates 98 | * the current core clock. 99 | */ 100 | void SystemCoreClockUpdate (void); 101 | 102 | /** 103 | * @brief SystemInit function hook. 104 | * 105 | * This weak function allows to call specific initialization code during the 106 | * SystemInit() execution.This can be used when an application specific code needs 107 | * to be called as close to the reset entry as possible (for example the Multicore 108 | * Manager MCMGR_EarlyInit() function call). 109 | * NOTE: No global r/w variables can be used in this hook function because the 110 | * initialization of these variables happens after this function. 111 | */ 112 | void SystemInitHook (void); 113 | 114 | #ifdef __cplusplus 115 | } 116 | #endif 117 | 118 | #endif /* _SYSTEM_MIMXRT1011_H_ */ 119 | --------------------------------------------------------------------------------