├── project_AXI_DMA.sim └── sim_1 │ └── behav │ └── xsim │ ├── simulate.log │ ├── xsim.dir │ ├── test_behav │ │ ├── xsimcrash.log │ │ ├── xsim.type │ │ ├── TempBreakPointFile.txt │ │ ├── xsim.dbg │ │ ├── xsim.mem │ │ ├── xsim.reloc │ │ ├── xsim.rtti │ │ ├── xsim.xdbg │ │ ├── xsimk.exe │ │ ├── xsim.svtype │ │ ├── obj │ │ │ ├── xsim_0.win64.obj │ │ │ ├── xsim_1.win64.obj │ │ │ └── xsim_1.c │ │ ├── Compile_Options.txt │ │ ├── xsimkernel.log │ │ ├── xsim.rlx │ │ └── xsimSettings.ini │ └── xil_defaultlib │ │ ├── glbl.sdb │ │ ├── test.sdb │ │ ├── top.sdb │ │ ├── axi_slave.sdb │ │ ├── axi_dma_controller.sdb │ │ └── xil_defaultlib.rlx │ ├── xsim.ini │ ├── xelab.pb │ ├── xvlog.pb │ ├── test_behav.wdb │ ├── test_vlog.prj │ ├── test.tcl │ ├── elaborate.log │ ├── compile.bat │ ├── simulate.bat │ ├── elaborate.bat │ ├── xvlog.log │ ├── glbl.v │ └── dump.vcd ├── project_AXI_DMA.cache ├── wt │ ├── project.wpc │ └── xsim.wdf └── sim │ └── ssm.db ├── project_AXI_DMA.ip_user_files └── README.txt ├── project_AXI_DMA.hw └── project_AXI_DMA.lpr ├── project_AXI_DMA.srcs ├── sources_1 │ └── new │ │ ├── ram.v │ │ ├── top.v │ │ ├── axi_dma_controller.v │ │ └── axi_slave.v └── sim_1 │ └── new │ └── axi_dma_ctl_tb.v ├── backup ├── top.v ├── axi_dma_ctl_tb.v ├── axi_dma_controller.v └── axi_slave.v ├── README.md ├── backup2 ├── top.v ├── axi_dma_ctl_tb.v ├── axi_dma_controller.v └── axi_slave.v └── project_AXI_DMA.xpr /project_AXI_DMA.sim/sim_1/behav/xsim/simulate.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/test_behav/xsimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xsim.ini: -------------------------------------------------------------------------------- 1 | xil_defaultlib=xsim.dir/xil_defaultlib 2 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/test_behav/xsim.type: -------------------------------------------------------------------------------- 1 |  -------------------------------------------------------------------------------- /project_AXI_DMA.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:4 3 | eof: 4 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/test_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jefferyy-Peng/AXI_DMA_CONTROLLER/HEAD/project_AXI_DMA.sim/sim_1/behav/xsim/xelab.pb -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xvlog.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jefferyy-Peng/AXI_DMA_CONTROLLER/HEAD/project_AXI_DMA.sim/sim_1/behav/xsim/xvlog.pb -------------------------------------------------------------------------------- /project_AXI_DMA.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/test_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jefferyy-Peng/AXI_DMA_CONTROLLER/HEAD/project_AXI_DMA.sim/sim_1/behav/xsim/test_behav.wdb -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/test_behav/xsim.dbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jefferyy-Peng/AXI_DMA_CONTROLLER/HEAD/project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/test_behav/xsim.dbg -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/test_behav/xsim.mem: -------------------------------------------------------------------------------- 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/project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jefferyy-Peng/AXI_DMA_CONTROLLER/HEAD/project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top.sdb -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/axi_slave.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jefferyy-Peng/AXI_DMA_CONTROLLER/HEAD/project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/axi_slave.sdb -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/test_behav/obj/xsim_0.win64.obj: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/test_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "test_behav" "xil_defaultlib.test" "xil_defaultlib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /project_AXI_DMA.cache/wt/xsim.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00 3 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 4 | eof:2427094519 5 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/test_behav/xsimkernel.log: -------------------------------------------------------------------------------- 1 | Running: xsim.dir/test_behav/xsimk.exe -simmode gui -wdb test_behav.wdb -simrunnum 0 -socket 57736 2 | Design successfully loaded 3 | Design Loading Memory Usage: 7780 KB (Peak: 7780 KB) 4 | Design Loading CPU Usage: 46 ms 5 | -------------------------------------------------------------------------------- /project_AXI_DMA.hw/project_AXI_DMA.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/test_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib \ 3 | "../../../../project_AXI_DMA.srcs/sources_1/new/axi_dma_controller.v" \ 4 | "../../../../project_AXI_DMA.srcs/sources_1/new/axi_slave.v" \ 5 | "../../../../project_AXI_DMA.srcs/sources_1/new/top.v" \ 6 | "../../../../project_AXI_DMA.srcs/sim_1/new/axi_dma_ctl_tb.v" \ 7 | 8 | # compile glbl module 9 | verilog xil_defaultlib "glbl.v" 10 | 11 | # Do not sort compile order 12 | nosort 13 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/test.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /project_AXI_DMA.cache/sim/ssm.db: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # DONOT REMOVE THIS FILE 3 | # Unified simulation database file for selected simulation model for IP 4 | # 5 | # File: ssm.db (Sat Feb 25 23:07:27 2023) 6 | # 7 | # This file is generated by the unified simulation automation and contains the 8 | # selected simulation model information for the IP/BD instances. 9 | # DONOT REMOVE THIS FILE 10 | ################################################################################ 11 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/test_behav/xsim.rlx: -------------------------------------------------------------------------------- 1 | 2 | { 3 | crc : 6152478253504203580 , 4 | ccp_crc : 0 , 5 | cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot test_behav xil_defaultlib.test xil_defaultlib.glbl" , 6 | buildDate : "Oct 14 2022" , 7 | buildTime : "05:20:55" , 8 | linkCmd : "F:\\Xilinx\\Vivado\\2022.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/test_behav/xsimk.exe\" \"xsim.dir/test_behav/obj/xsim_0.win64.obj\" \"xsim.dir/test_behav/obj/xsim_1.win64.obj\" -L\"F:\\Xilinx\\Vivado\\2022.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , 9 | aggregate_nets : 10 | [ 11 | ] 12 | } -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/elaborate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator v2022.2 2 | Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved. 3 | Running: F:/Xilinx/Vivado/2022.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot test_behav xil_defaultlib.test xil_defaultlib.glbl -log elaborate.log 4 | Using 2 slave threads. 5 | Starting static elaboration 6 | Pass Through NonSizing Optimizer 7 | Completed static elaboration 8 | Starting simulation data flow analysis 9 | Completed simulation data flow analysis 10 | Time Resolution for simulation is 1ps 11 | Compiling module xil_defaultlib.axi_dma_controller_default 12 | Compiling module xil_defaultlib.axi_slave_default 13 | Compiling module xil_defaultlib.top_default 14 | Compiling module xil_defaultlib.test 15 | Compiling module xil_defaultlib.glbl 16 | Built simulation snapshot test_behav 17 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx: -------------------------------------------------------------------------------- 1 | 0.7 2 | 2020.2 3 | Oct 14 2022 4 | 05:20:55 5 | F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.sim/sim_1/behav/xsim/glbl.v,1665704903,verilog,,,,glbl,,,,,,,, 6 | F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.srcs/sim_1/new/axi_dma_ctl_tb.v,1677484702,verilog,,,,test,,,,,,,, 7 | F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.srcs/sources_1/new/axi_dma_controller.v,1677484665,verilog,,F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.srcs/sources_1/new/axi_slave.v,,axi_dma_controller,,,,,,,, 8 | F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.srcs/sources_1/new/axi_slave.v,1677484328,verilog,,F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.srcs/sources_1/new/top.v,,axi_slave,,,,,,,, 9 | F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.srcs/sources_1/new/top.v,1677477719,verilog,,F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.srcs/sim_1/new/axi_dma_ctl_tb.v,,top,,,,,,,, 10 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/compile.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2022.2 (64-bit) 4 | REM 5 | REM Filename : compile.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for compiling the simulation design source files 8 | REM 9 | REM Generated by Vivado on Mon Feb 27 02:58:30 -0500 2023 10 | REM SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 11 | REM 12 | REM IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 13 | REM 14 | REM usage: compile.bat 15 | REM 16 | REM **************************************************************************** 17 | REM compile Verilog/System Verilog design sources 18 | echo "xvlog --incr --relax -prj test_vlog.prj" 19 | call xvlog --incr --relax -prj test_vlog.prj -log xvlog.log 20 | call type xvlog.log > compile.log 21 | if "%errorlevel%"=="1" goto END 22 | if "%errorlevel%"=="0" goto SUCCESS 23 | :END 24 | exit 1 25 | :SUCCESS 26 | exit 0 27 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/simulate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2022.2 (64-bit) 4 | REM 5 | REM Filename : simulate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for simulating the design by launching the simulator 8 | REM 9 | REM Generated by Vivado on Sun Feb 26 16:25:25 -0500 2023 10 | REM SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 11 | REM 12 | REM IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 13 | REM 14 | REM usage: simulate.bat 15 | REM 16 | REM **************************************************************************** 17 | REM simulate design 18 | echo "xsim test_behav -key {Behavioral:sim_1:Functional:test} -tclbatch test.tcl -view F:/Xilinx/Projects/project_AXI_DMA/test_behav.wcfg -log simulate.log" 19 | call xsim test_behav -key {Behavioral:sim_1:Functional:test} -tclbatch test.tcl -view F:/Xilinx/Projects/project_AXI_DMA/test_behav.wcfg -log simulate.log 20 | if "%errorlevel%"=="0" goto SUCCESS 21 | if "%errorlevel%"=="1" goto END 22 | :END 23 | exit 1 24 | :SUCCESS 25 | exit 0 26 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/elaborate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2022.2 (64-bit) 4 | REM 5 | REM Filename : elaborate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for elaborating the compiled design 8 | REM 9 | REM Generated by Vivado on Mon Feb 27 02:58:31 -0500 2023 10 | REM SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 11 | REM 12 | REM IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 13 | REM 14 | REM usage: elaborate.bat 15 | REM 16 | REM **************************************************************************** 17 | REM elaborate design 18 | echo "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot test_behav xil_defaultlib.test xil_defaultlib.glbl -log elaborate.log" 19 | call xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot test_behav xil_defaultlib.test xil_defaultlib.glbl -log elaborate.log 20 | if "%errorlevel%"=="0" goto SUCCESS 21 | if "%errorlevel%"=="1" goto END 22 | :END 23 | exit 1 24 | :SUCCESS 25 | exit 0 26 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xvlog.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.srcs/sources_1/new/axi_dma_controller.v" into library xil_defaultlib 2 | INFO: [VRFC 10-311] analyzing module axi_dma_controller 3 | WARNING: [VRFC 10-8374] loop variable declaration is not allowed in this mode of Verilog [F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.srcs/sources_1/new/axi_dma_controller.v:206] 4 | INFO: [VRFC 10-2263] Analyzing Verilog file "F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.srcs/sources_1/new/axi_slave.v" into library xil_defaultlib 5 | INFO: [VRFC 10-311] analyzing module axi_slave 6 | WARNING: [VRFC 10-8374] loop variable declaration is not allowed in this mode of Verilog [F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.srcs/sources_1/new/axi_slave.v:139] 7 | WARNING: [VRFC 10-8374] loop variable declaration is not allowed in this mode of Verilog [F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.srcs/sources_1/new/axi_slave.v:220] 8 | INFO: [VRFC 10-2263] Analyzing Verilog file "F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.srcs/sources_1/new/top.v" into library xil_defaultlib 9 | INFO: [VRFC 10-311] analyzing module top 10 | INFO: [VRFC 10-2263] Analyzing Verilog file "F:/Xilinx/Projects/project_AXI_DMA/project_AXI_DMA.srcs/sim_1/new/axi_dma_ctl_tb.v" into library xil_defaultlib 11 | INFO: [VRFC 10-311] analyzing module test 12 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/test_behav/xsimSettings.ini: -------------------------------------------------------------------------------- 1 | [General] 2 | ARRAY_DISPLAY_LIMIT=1024 3 | RADIX=hex 4 | TIME_UNIT=ns 5 | TRACE_LIMIT=65536 6 | VHDL_ENTITY_SCOPE_FILTER=true 7 | VHDL_PACKAGE_SCOPE_FILTER=false 8 | VHDL_BLOCK_SCOPE_FILTER=true 9 | VHDL_PROCESS_SCOPE_FILTER=false 10 | VHDL_PROCEDURE_SCOPE_FILTER=false 11 | VERILOG_MODULE_SCOPE_FILTER=true 12 | VERILOG_PACKAGE_SCOPE_FILTER=false 13 | VERILOG_BLOCK_SCOPE_FILTER=false 14 | VERILOG_TASK_SCOPE_FILTER=false 15 | VERILOG_PROCESS_SCOPE_FILTER=false 16 | INPUT_OBJECT_FILTER=true 17 | OUTPUT_OBJECT_FILTER=true 18 | INOUT_OBJECT_FILTER=true 19 | INTERNAL_OBJECT_FILTER=true 20 | CONSTANT_OBJECT_FILTER=true 21 | VARIABLE_OBJECT_FILTER=true 22 | INPUT_PROTOINST_FILTER=true 23 | OUTPUT_PROTOINST_FILTER=true 24 | INOUT_PROTOINST_FILTER=true 25 | INTERNAL_PROTOINST_FILTER=true 26 | CONSTANT_PROTOINST_FILTER=true 27 | VARIABLE_PROTOINST_FILTER=true 28 | SCOPE_NAME_COLUMN_WIDTH=75 29 | SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 30 | SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 31 | OBJECT_NAME_COLUMN_WIDTH=75 32 | OBJECT_VALUE_COLUMN_WIDTH=75 33 | OBJECT_DATA_TYPE_COLUMN_WIDTH=75 34 | PROCESS_NAME_COLUMN_WIDTH=75 35 | PROCESS_TYPE_COLUMN_WIDTH=75 36 | FRAME_INDEX_COLUMN_WIDTH=75 37 | FRAME_NAME_COLUMN_WIDTH=75 38 | FRAME_FILE_NAME_COLUMN_WIDTH=75 39 | FRAME_LINE_NUM_COLUMN_WIDTH=75 40 | LOCAL_NAME_COLUMN_WIDTH=75 41 | LOCAL_VALUE_COLUMN_WIDTH=75 42 | LOCAL_DATA_TYPE_COLUMN_WIDTH=0 43 | PROTO_NAME_COLUMN_WIDTH=0 44 | PROTO_VALUE_COLUMN_WIDTH=0 45 | INPUT_LOCAL_FILTER=1 46 | OUTPUT_LOCAL_FILTER=1 47 | INOUT_LOCAL_FILTER=1 48 | INTERNAL_LOCAL_FILTER=1 49 | CONSTANT_LOCAL_FILTER=1 50 | VARIABLE_LOCAL_FILTER=1 51 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | `ifndef GLBL 3 | `define GLBL 4 | `timescale 1 ps / 1 ps 5 | 6 | module glbl (); 7 | 8 | parameter ROC_WIDTH = 100000; 9 | parameter TOC_WIDTH = 0; 10 | parameter GRES_WIDTH = 10000; 11 | parameter GRES_START = 10000; 12 | 13 | //-------- STARTUP Globals -------------- 14 | wire GSR; 15 | wire GTS; 16 | wire GWE; 17 | wire PRLD; 18 | wire GRESTORE; 19 | tri1 p_up_tmp; 20 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 21 | 22 | wire PROGB_GLBL; 23 | wire CCLKO_GLBL; 24 | wire FCSBO_GLBL; 25 | wire [3:0] DO_GLBL; 26 | wire [3:0] DI_GLBL; 27 | 28 | reg GSR_int; 29 | reg GTS_int; 30 | reg PRLD_int; 31 | reg GRESTORE_int; 32 | 33 | //-------- JTAG Globals -------------- 34 | wire JTAG_TDO_GLBL; 35 | wire JTAG_TCK_GLBL; 36 | wire JTAG_TDI_GLBL; 37 | wire JTAG_TMS_GLBL; 38 | wire JTAG_TRST_GLBL; 39 | 40 | reg JTAG_CAPTURE_GLBL; 41 | reg JTAG_RESET_GLBL; 42 | reg JTAG_SHIFT_GLBL; 43 | reg JTAG_UPDATE_GLBL; 44 | reg JTAG_RUNTEST_GLBL; 45 | 46 | reg JTAG_SEL1_GLBL = 0; 47 | reg JTAG_SEL2_GLBL = 0 ; 48 | reg JTAG_SEL3_GLBL = 0; 49 | reg JTAG_SEL4_GLBL = 0; 50 | 51 | reg JTAG_USER_TDO1_GLBL = 1'bz; 52 | reg JTAG_USER_TDO2_GLBL = 1'bz; 53 | reg JTAG_USER_TDO3_GLBL = 1'bz; 54 | reg JTAG_USER_TDO4_GLBL = 1'bz; 55 | 56 | assign (strong1, weak0) GSR = GSR_int; 57 | assign (strong1, weak0) GTS = GTS_int; 58 | assign (weak1, weak0) PRLD = PRLD_int; 59 | assign (strong1, weak0) GRESTORE = GRESTORE_int; 60 | 61 | initial begin 62 | GSR_int = 1'b1; 63 | PRLD_int = 1'b1; 64 | #(ROC_WIDTH) 65 | GSR_int = 1'b0; 66 | PRLD_int = 1'b0; 67 | end 68 | 69 | initial begin 70 | GTS_int = 1'b1; 71 | #(TOC_WIDTH) 72 | GTS_int = 1'b0; 73 | end 74 | 75 | initial begin 76 | GRESTORE_int = 1'b0; 77 | #(GRES_START); 78 | GRESTORE_int = 1'b1; 79 | #(GRES_WIDTH); 80 | GRESTORE_int = 1'b0; 81 | end 82 | 83 | endmodule 84 | `endif 85 | -------------------------------------------------------------------------------- /project_AXI_DMA.srcs/sources_1/new/ram.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/02/26 17:38:38 7 | // Design Name: 8 | // Module Name: ram 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module ram#( 24 | parameter ADDR_WD = 32, 25 | parameter DATA_WD = 32, 26 | localparam DATA_WD_BYTE = DATA_WD / 8, 27 | localparam STRB_WD = DATA_WD / 8 28 | )( 29 | input wire clk, 30 | input wire rst, 31 | input wire [ADDR_WD - 1 : 0] mem_addr, 32 | input wire [DATA_WD - 1 : 0] mem_write_data, 33 | input wire [STRB_WD - 1 : 0] strobe, 34 | input wire mem_en, 35 | input wire mem_rh_wl, 36 | output wire [DATA_WD - 1 : 0] mem_read_data 37 | ); 38 | reg [7:0] mem [0 : 8**12 - 1]; 39 | 40 | /********************** mem initialize ***************************/ 41 | always@(posedge clk) begin 42 | if(rst) begin 43 | for(integer i = 0; i < 2**12; i = i + 1) begin 44 | mem[i] <= i; 45 | end 46 | end 47 | else begin 48 | for(integer i = 0; i < 2**12; i = i + 1) begin 49 | mem[i] <= mem[i]; 50 | end 51 | end 52 | end 53 | /********************** mem read write ***************************/ 54 | 55 | always@(posedge clk) 56 | if(!mem_rh_wl) 57 | mem[mem_addr] <= mem_en ? mem_write_data : mem[mem_addr]; 58 | else 59 | mem[mem_addr] <= mem[mem_addr]; 60 | 61 | //ram核心读 62 | always@(posedge clk) 63 | if(mem_rh_wl) 64 | mem_read_data <= mem[mem_addr] ; 65 | else 66 | mem_read_data <= mem_read_data ; 67 | 68 | //ram地址 69 | always@(posedge clk) 70 | if(rst || S_AXI_WLAST || S_AXI_RLAST) 71 | mem_addr <= 'd0; 72 | else if(w_aw_active) 73 | mem_addr <= r_awaddr; 74 | else if(w_ar_active) 75 | mem_addr <= r_araddr; 76 | else if(w_w_active || (r_rvalid & S_AXI_RREADY)) 77 | mem_addr <= mem_addr + 1; 78 | else 79 | mem_addr <= mem_addr; 80 | 81 | //ram写端口 82 | always@(posedge clk) 83 | if(w_w_active) 84 | mem_write_data <= S_AXI_WDATA ; 85 | else 86 | mem_write_data <= mem_write_data ; 87 | 88 | //ram读写控制 89 | always@(posedge clk) 90 | if(w_ar_active) 91 | mem_rh_wl <= 'd1; 92 | else if(w_aw_active) 93 | mem_rh_wl <= 'd0; 94 | else 95 | mem_rh_wl <= mem_rh_wl; 96 | 97 | //ram写使能 98 | always@(posedge clk) 99 | if(w_w_active) 100 | mem_en <= 'd1; 101 | else 102 | mem_en <= 'd0; 103 | endmodule 104 | -------------------------------------------------------------------------------- /backup/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/02/25 23:16:00 7 | // Design Name: 8 | // Module Name: top 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | `default_nettype none 24 | module top #( 25 | parameter integer ADDR_WD = 32, 26 | parameter integer DATA_WD = 32, 27 | parameter integer DATA_WD_BYTE = DATA_WD / 8, 28 | localparam integer STRB_WD = DATA_WD / 8 29 | )( 30 | input wire clk, 31 | input wire rst, 32 | // DMA Command 33 | input wire cmd_valid, 34 | input wire [ADDR_WD-1 : 0] cmd_src_addr, 35 | input wire [ADDR_WD-1 : 0] cmd_dst_addr, 36 | input wire [1:0] cmd_burst, 37 | input wire [ADDR_WD-1 : 0] cmd_len, 38 | input wire [2:0] cmd_size, 39 | output wire cmd_ready 40 | ); 41 | // Read Address Channel 42 | wire M_AXI_ARVALID; 43 | wire [ADDR_WD-1 : 0] M_AXI_ARADDR; 44 | wire [ADDR_WD-1:0] M_AXI_ARLEN; 45 | wire [2:0] M_AXI_ARSIZE; 46 | wire [1:0] M_AXI_ARBURST; 47 | wire M_AXI_ARREADY; 48 | // Read Response Channel 49 | wire M_AXI_RVALID; 50 | wire [DATA_WD-1 : 0] M_AXI_RDATA; 51 | wire [1:0] M_AXI_RRESP; 52 | wire M_AXI_RLAST; 53 | wire M_AXI_RREADY; 54 | // Write Address Channel 55 | wire M_AXI_AWVALID; 56 | wire [ADDR_WD-1 : 0] M_AXI_AWADDR; 57 | wire [ADDR_WD-1:0] M_AXI_AWLEN; 58 | wire [2:0] M_AXI_AWSIZE; 59 | wire [1:0] M_AXI_AWBURST; 60 | wire M_AXI_AWREADY; 61 | // Write Data Channel 62 | wire M_AXI_WVALID; 63 | wire [DATA_WD-1 : 0] M_AXI_WDATA; 64 | wire [STRB_WD-1 : 0] M_AXI_WSTRB; 65 | wire M_AXI_WLAST; 66 | wire M_AXI_WREADY; 67 | // Write Response Channel 68 | wire M_AXI_BVALID; 69 | wire [1:0] M_AXI_BRESP; 70 | wire M_AXI_BREADY; 71 | 72 | axi_dma_controller axi_dma_ctl( 73 | .clk(clk), 74 | .rst(rst), 75 | .cmd_valid(cmd_valid), 76 | .cmd_src_addr(cmd_src_addr), 77 | .cmd_dst_addr(cmd_dst_addr), 78 | .cmd_burst(cmd_burst), 79 | .cmd_len(cmd_len), 80 | .cmd_size(cmd_size), 81 | .cmd_ready(cmd_ready), 82 | .M_AXI_ARVALID(M_AXI_ARVALID), 83 | .M_AXI_ARADDR(M_AXI_ARADDR), 84 | .M_AXI_ARLEN(M_AXI_ARLEN), 85 | .M_AXI_ARSIZE(M_AXI_ARSIZE), 86 | .M_AXI_ARBURST(M_AXI_ARBURST), 87 | .M_AXI_ARREADY(M_AXI_ARREADY), 88 | .M_AXI_RVALID(M_AXI_RVALID), 89 | .M_AXI_RDATA(M_AXI_RDATA), 90 | .M_AXI_RRESP(M_AXI_RRESP), 91 | .M_AXI_RLAST(M_AXI_RLAST), 92 | .M_AXI_RREADY(M_AXI_RREADY), 93 | .M_AXI_AWVALID(M_AXI_AWVALID), 94 | .M_AXI_AWADDR(M_AXI_AWADDR), 95 | .M_AXI_AWLEN(M_AXI_AWLEN), 96 | .M_AXI_AWSIZE(M_AXI_AWSIZE), 97 | .M_AXI_AWBURST(M_AXI_AWBURST), 98 | .M_AXI_AWREADY(M_AXI_AWREADY), 99 | .M_AXI_WVALID(M_AXI_WVALID), 100 | .M_AXI_WDATA(M_AXI_WDATA), 101 | .M_AXI_WSTRB(M_AXI_WSTRB), 102 | .M_AXI_WLAST(M_AXI_WLAST), 103 | .M_AXI_WREADY(M_AXI_WREADY), 104 | .M_AXI_BVALID(M_AXI_BVALID), 105 | .M_AXI_BRESP(M_AXI_BRESP), 106 | .M_AXI_BREADY(M_AXI_BREADY) 107 | ); 108 | 109 | axi_slave SLAVE( 110 | .clk(clk), 111 | .rst(rst), 112 | .S_AXI_ARVALID(M_AXI_ARVALID), 113 | .S_AXI_ARADDR(M_AXI_ARADDR), 114 | .S_AXI_ARLEN(M_AXI_ARLEN), 115 | .S_AXI_ARSIZE(M_AXI_ARSIZE), 116 | .S_AXI_ARBURST(M_AXI_ARBURST), 117 | .S_AXI_ARREADY(M_AXI_ARREADY), 118 | .S_AXI_RVALID(M_AXI_RVALID), 119 | .S_AXI_RDATA(M_AXI_RDATA), 120 | .S_AXI_RRESP(M_AXI_RRESP), 121 | .S_AXI_RLAST(M_AXI_RLAST), 122 | .S_AXI_RREADY(M_AXI_RREADY), 123 | .S_AXI_AWVALID(M_AXI_AWVALID), 124 | .S_AXI_AWADDR(M_AXI_AWADDR), 125 | .S_AXI_AWLEN(M_AXI_AWLEN), 126 | .S_AXI_AWSIZE(M_AXI_AWSIZE), 127 | .S_AXI_AWBURST(M_AXI_AWBURST), 128 | .S_AXI_AWREADY(M_AXI_AWREADY), 129 | .S_AXI_WVALID(M_AXI_WVALID), 130 | .S_AXI_WDATA(M_AXI_WDATA), 131 | .S_AXI_WSTRB(M_AXI_WSTRB), 132 | .S_AXI_WLAST(M_AXI_WLAST), 133 | .S_AXI_WREADY(M_AXI_WREADY), 134 | .S_AXI_BVALID(M_AXI_BVALID), 135 | .S_AXI_BRESP(M_AXI_BRESP), 136 | .S_AXI_BREADY(M_AXI_BREADY) 137 | ); 138 | 139 | 140 | endmodule -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # AXI_DMA_CONTROLLER 2 | 3 | ## Introduction 4 | * This is a DMA controller implemented based on AXI interface. It is consisted by a master and a slave module 5 | * Now only support FIXED and INCR burst mode 6 | * Bus width and max data width in each beat is runtime configurable. It also supports AXI Narrow transfers 7 | * Unalligned Transmit and 4K address boundary handling is not supported yet 8 | 9 | ## File structure 10 | * src 11 | * axi_dma_controller.v 12 | * axi_slave.v 13 | * top.v 14 | * sim 15 | * axi_dma_ctl_tb.v 16 | 17 | ## Details 18 | ### Master 19 | * Parameters: *ADDR_WD*, *DATA_WD*, *localparam STRB_WD = DATA_WD / 8* 20 | 21 | | Signal | Meaning | Width | 22 | | ------------- |:-------------:| -----:| 23 | | clk | Global clock | 1 | 24 | | rst | Global reset | 1 | 25 | | cmd_valid | DMA command valid | 1 | 26 | | cmd_src_addr | DMA source address | ADDR_WD | 27 | | cmd_dst_addr | DMA destination address | ADDR_WD | 28 | | cmd_burst | DMA burst mode | 2 | 29 | | cmd_len | burst length | ADDR_WD | 30 | | cmd_size | Max Beat data width | 3 | 31 | | cmd_ready | DMA command ready | 1 | 32 | | M_AXI_ARVALID | Address read valid | 1 | 33 | | M_AXI_ARADDR | Address read | ADDR_WD | 34 | | M_AXI_ARLEN | burst length | ADDR_WD | 35 | | M_AXI_ARSIZE | Max Beat data width | 3 | 36 | | M_AXI_ARBURST | burst mode | 2 | 37 | | M_AXI_ARREADY | Address read ready | 1 | 38 | | M_AXI_RVALID | Read valid | 1 | 39 | | M_AXI_RDATA | Read data | DATA_WD | 40 | | M_AXI_RRESP | read response(Default OKAY) | 2 | 41 | | M_AXI_RLAST | Read terminate signal | 1 | 42 | | R_strobe | Read Strobe, implementing Narrow Transmit | STRB_WD | 43 | | M_AXI_RREADY | Read ready | 1 | 44 | | M_AXI_AWVALID | Write address valid | 1 | 45 | | M_AXI_AWADDR | write address | ADDR_WD | 46 | | M_AXI_AWSIZE | burst length | 3 | 47 | | M_AXI_AWBURST | burst mode | 2 | 48 | | M_AXI_AWREADY | Write address ready | 1 | 49 | | M_AXI_WVALID | Write valid | 1 | 50 | | M_AXI_WDATA | Write data | DATA_WD | 51 | | M_AXI_WSTRB | Write strobe | STRB_WD | 52 | | M_AXI_WLAST | Write terminate signal | 1 | 53 | | M_AXI_WREADY | Write ready | 1 | 54 | | M_AXI_BVALID | Response valid | 1 | 55 | | M_AXI_BRESP | Response signal | 2 | 56 | | M_AXI_BREADY | Response ready | 1 | 57 | 58 | 59 | ### Slave 60 | * Parameters: *ADDR_WD*, *DATA_WD*, *localparam STRB_WD = DATA_WD / 8* 61 | 62 | | Singal | Meaning | Width | 63 | | ------------- |:-------------:| -----:| 64 | | clk | Global clock | 1 | 65 | | rst | Global reset | 1 | 66 | | S_AXI_ARVALID | Read address valid | 1 | 67 | | S_AXI_ARADDR | Read address | ADDR_WD | 68 | | S_AXI_ARLEN | burst length | ADDR_WD | 69 | | S_AXI_ARSIZE | Max Beat data width | 3 | 70 | | S_AXI_ARBURST | burst mode | 2 | 71 | | S_AXI_ARREADY | Read address ready | 1 | 72 | | S_AXI_RVALID | Read valid | 1 | 73 | | S_AXI_RDATA | Read data | DATA_WD | 74 | | S_AXI_RRESP | read response(Default OKAY) | 2 | 75 | | S_AXI_RLAST | Read terminate signal | 1 | 76 | | R_strobe | Read Strobe, implementing Narrow Transmit | STRB_WD | 77 | | S_AXI_RREADY | Read ready | 1 | 78 | | S_AXI_AWVALID | Write address valid | 1 | 79 | | S_AXI_AWADDR | Write address | ADDR_WD | 80 | | S_AXI_AWSIZE | burst length | 3 | 81 | | S_AXI_AWBURST | burst mode | 2 | 82 | | S_AXI_AWREADY | Write address ready | 1 | 83 | | S_AXI_WVALID | Write valid | 1 | 84 | | S_AXI_WDATA | Write data | DATA_WD | 85 | | S_AXI_WSTRB | Write strobe | STRB_WD | 86 | | S_AXI_WLAST | Write terminate signal | 1 | 87 | | S_AXI_WREADY | Write ready | 1 | 88 | | S_AXI_BVALID | Response valid | 1 | 89 | | S_AXI_BRESP | Response signal | 2 | 90 | | S_AXI_BREADY | Response ready | 1 | 91 | 92 | ## Simulation 93 | 94 | * 32 bit bus read simulation 95 | ![image](https://user-images.githubusercontent.com/123399300/221536905-4605aceb-5c4d-49f0-899d-3c886ea214c3.png) 96 | 97 | * 32 bit bus write simulation 98 | ![image](https://user-images.githubusercontent.com/123399300/221537203-4a486177-77dd-420b-8344-ed479438b988.png) 99 | 100 | * 64 bit bus read simulation 101 | ![image](https://user-images.githubusercontent.com/123399300/221537719-4427493f-1d6e-432f-9620-128699425ddd.png) 102 | 103 | * 64 bit bus write simulation 104 | ![image](https://user-images.githubusercontent.com/123399300/221537885-a72f6fdb-09f0-4d9a-a86c-2a3f20a3b99a.png) 105 | 106 | -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/dump.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sat Feb 25 23:50:52 2023 3 | $end 4 | $version 5 | 2022.2 6 | $end 7 | $timescale 8 | 1ps 9 | $end 10 | $scope module test $end 11 | $var reg 1 ! clk $end 12 | $var reg 1 " rst $end 13 | $var reg 1 # cmd_valid $end 14 | $var reg 1 $ cmd_src_addr $end 15 | $var reg 1 % cmd_dst_addr $end 16 | $var reg 1 & cmd_burst $end 17 | $var reg 1 ' cmd_len $end 18 | $var reg 1 ( cmd_size $end 19 | $var wire 1 ) cmd_ready $end 20 | $upscope $end 21 | $enddefinitions $end 22 | #0 23 | $dumpvars 24 | 0! 25 | 0" 26 | x# 27 | x$ 28 | x% 29 | x& 30 | x' 31 | x( 32 | x) 33 | $end 34 | #5000 35 | 1! 36 | #10000 37 | 0! 38 | #15000 39 | 1! 40 | #20000 41 | 0! 42 | #25000 43 | 1! 44 | #30000 45 | 0! 46 | #35000 47 | 1! 48 | #40000 49 | 0! 50 | #45000 51 | 1! 52 | #50000 53 | 0! 54 | #55000 55 | 1! 56 | #60000 57 | 0! 58 | #65000 59 | 1! 60 | #70000 61 | 0! 62 | #75000 63 | 1! 64 | #80000 65 | 0! 66 | #85000 67 | 1! 68 | #90000 69 | 0! 70 | #95000 71 | 1! 72 | #100000 73 | 0! 74 | 1" 75 | #105000 76 | 1! 77 | 1) 78 | #110000 79 | 0! 80 | #115000 81 | 1! 82 | #120000 83 | 0! 84 | 0" 85 | #125000 86 | 1! 87 | #130000 88 | 0! 89 | #135000 90 | 1! 91 | #140000 92 | 0! 93 | 1# 94 | 0$ 95 | 0% 96 | 0& 97 | 0' 98 | 0( 99 | #145000 100 | 1! 101 | x) 102 | #150000 103 | 0! 104 | #155000 105 | 1! 106 | #160000 107 | 0! 108 | 0# 109 | #165000 110 | 1! 111 | #170000 112 | 0! 113 | #175000 114 | 1! 115 | #180000 116 | 0! 117 | #185000 118 | 1! 119 | #190000 120 | 0! 121 | #195000 122 | 1! 123 | #200000 124 | 0! 125 | #205000 126 | 1! 127 | #210000 128 | 0! 129 | #215000 130 | 1! 131 | #220000 132 | 0! 133 | #225000 134 | 1! 135 | #230000 136 | 0! 137 | #235000 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#670000 312 | 0! 313 | #675000 314 | 1! 315 | #680000 316 | 0! 317 | #685000 318 | 1! 319 | #690000 320 | 0! 321 | #695000 322 | 1! 323 | #700000 324 | 0! 325 | #705000 326 | 1! 327 | #710000 328 | 0! 329 | #715000 330 | 1! 331 | #720000 332 | 0! 333 | #725000 334 | 1! 335 | #730000 336 | 0! 337 | #735000 338 | 1! 339 | #740000 340 | 0! 341 | #745000 342 | 1! 343 | #750000 344 | 0! 345 | #755000 346 | 1! 347 | #760000 348 | 0! 349 | #765000 350 | 1! 351 | #770000 352 | 0! 353 | #775000 354 | 1! 355 | #780000 356 | 0! 357 | #785000 358 | 1! 359 | #790000 360 | 0! 361 | #795000 362 | 1! 363 | #800000 364 | 0! 365 | #805000 366 | 1! 367 | #810000 368 | 0! 369 | #815000 370 | 1! 371 | #820000 372 | 0! 373 | #825000 374 | 1! 375 | #830000 376 | 0! 377 | #835000 378 | 1! 379 | #840000 380 | 0! 381 | #845000 382 | 1! 383 | #850000 384 | 0! 385 | #855000 386 | 1! 387 | #860000 388 | 0! 389 | #865000 390 | 1! 391 | #870000 392 | 0! 393 | #875000 394 | 1! 395 | #880000 396 | 0! 397 | #885000 398 | 1! 399 | #890000 400 | 0! 401 | #895000 402 | 1! 403 | #900000 404 | 0! 405 | #905000 406 | 1! 407 | #910000 408 | 0! 409 | #915000 410 | 1! 411 | #920000 412 | 0! 413 | #925000 414 | 1! 415 | #930000 416 | 0! 417 | #935000 418 | 1! 419 | #940000 420 | 0! 421 | #945000 422 | 1! 423 | #950000 424 | 0! 425 | #955000 426 | 1! 427 | #960000 428 | 0! 429 | #965000 430 | 1! 431 | #970000 432 | 0! 433 | #975000 434 | 1! 435 | #980000 436 | 0! 437 | #985000 438 | 1! 439 | #990000 440 | 0! 441 | #995000 442 | 1! 443 | #1000000 444 | 0! 445 | -------------------------------------------------------------------------------- /backup2/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/02/25 23:16:00 7 | // Design Name: 8 | // Module Name: top 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | `default_nettype none 24 | module top #( 25 | parameter integer ADDR_WD = 32, 26 | parameter integer DATA_WD = 32, 27 | localparam DATA_WD_BYTE = DATA_WD / 8, 28 | localparam STRB_WD = DATA_WD / 8, 29 | localparam BUS_LANES = BUS_SIZE / 8 30 | )( 31 | input wire clk, 32 | input wire rst, 33 | // DMA Command 34 | input wire cmd_valid, 35 | input wire [ADDR_WD-1 : 0] cmd_src_addr, 36 | input wire [ADDR_WD-1 : 0] cmd_dst_addr, 37 | input wire [1:0] cmd_burst, 38 | input wire [ADDR_WD-1 : 0] cmd_len, 39 | input wire [2:0] cmd_size, 40 | output wire cmd_ready 41 | ); 42 | // Read Address Channel 43 | wire M_AXI_ARVALID; 44 | wire [ADDR_WD-1 : 0] M_AXI_ARADDR; 45 | wire [ADDR_WD-1:0] M_AXI_ARLEN; 46 | wire [2:0] M_AXI_ARSIZE; 47 | wire [1:0] M_AXI_ARBURST; 48 | wire M_AXI_ARREADY; 49 | // Read Response Channel 50 | wire M_AXI_RVALID; 51 | wire [DATA_WD-1 : 0] M_AXI_RDATA; 52 | wire [1:0] M_AXI_RRESP; 53 | wire M_AXI_RLAST; 54 | wire M_AXI_RREADY; 55 | wire [BUS_SIZE-1 :0] M_AXI_RBUS; 56 | // Write Address Channel 57 | wire M_AXI_AWVALID; 58 | wire [ADDR_WD-1 : 0] M_AXI_AWADDR; 59 | wire [ADDR_WD-1:0] M_AXI_AWLEN; 60 | wire [2:0] M_AXI_AWSIZE; 61 | wire [1:0] M_AXI_AWBURST; 62 | wire M_AXI_AWREADY; 63 | // Write Data Channel 64 | wire M_AXI_WVALID; 65 | wire [DATA_WD-1 : 0] M_AXI_WDATA; 66 | wire [STRB_WD-1 : 0] M_AXI_WSTRB; 67 | wire M_AXI_WLAST; 68 | wire M_AXI_WREADY; 69 | wire [BUS_SIZE-1: 0] M_AXI_WBUS; 70 | // Write Response Channel 71 | wire M_AXI_BVALID; 72 | wire [1:0] M_AXI_BRESP; 73 | wire M_AXI_BREADY; 74 | 75 | //byte lane 76 | wire [$clog2(BUS_LANES) - 1 : 0] AXI_BUS_LANES_SEL; 77 | 78 | always@(posedge clk) begin 79 | if(rst) 80 | AXI_BUS_LANES_SEL <= 0; 81 | else 82 | AXI_BUS_LANES_SEL <= AXI_BUS_LANES_SEL + 1; 83 | end 84 | 85 | axi_dma_controller #( 86 | .ADDR_WD(ADDR_WD), 87 | .DATA_WD(DATA_WD) 88 | )axi_dma_ctl ( 89 | .clk(clk), 90 | .rst(rst), 91 | .cmd_valid(cmd_valid), 92 | .cmd_src_addr(cmd_src_addr), 93 | .cmd_dst_addr(cmd_dst_addr), 94 | .cmd_burst(cmd_burst), 95 | .cmd_len(cmd_len), 96 | .cmd_size(cmd_size), 97 | .cmd_ready(cmd_ready), 98 | .M_AXI_ARVALID(M_AXI_ARVALID), 99 | .M_AXI_ARADDR(M_AXI_ARADDR), 100 | .M_AXI_ARLEN(M_AXI_ARLEN), 101 | .M_AXI_ARSIZE(M_AXI_ARSIZE), 102 | .M_AXI_ARBURST(M_AXI_ARBURST), 103 | .M_AXI_ARREADY(M_AXI_ARREADY), 104 | .M_AXI_RVALID(M_AXI_RVALID), 105 | .M_AXI_RDATA(M_AXI_RDATA), 106 | .M_AXI_RRESP(M_AXI_RRESP), 107 | .M_AXI_RLAST(M_AXI_RLAST), 108 | .M_AXI_RREADY(M_AXI_RREADY), 109 | .M_AXI_AWVALID(M_AXI_AWVALID), 110 | .M_AXI_AWADDR(M_AXI_AWADDR), 111 | .M_AXI_AWLEN(M_AXI_AWLEN), 112 | .M_AXI_AWSIZE(M_AXI_AWSIZE), 113 | .M_AXI_AWBURST(M_AXI_AWBURST), 114 | .M_AXI_AWREADY(M_AXI_AWREADY), 115 | .M_AXI_WVALID(M_AXI_WVALID), 116 | .M_AXI_WDATA(M_AXI_WDATA), 117 | .M_AXI_WSTRB(M_AXI_WSTRB), 118 | .M_AXI_WLAST(M_AXI_WLAST), 119 | .M_AXI_WREADY(M_AXI_WREADY), 120 | .M_AXI_BVALID(M_AXI_BVALID), 121 | .M_AXI_BRESP(M_AXI_BRESP), 122 | .M_AXI_BREADY(M_AXI_BREADY) 123 | ); 124 | 125 | axi_slave #( 126 | .ADDR_WD(ADDR_WD), 127 | .DATA_WD(DATA_WD) 128 | )SLAVE ( 129 | .clk(clk), 130 | .rst(rst), 131 | .S_AXI_ARVALID(M_AXI_ARVALID), 132 | .S_AXI_ARADDR(M_AXI_ARADDR), 133 | .S_AXI_ARLEN(M_AXI_ARLEN), 134 | .S_AXI_ARSIZE(M_AXI_ARSIZE), 135 | .S_AXI_ARBURST(M_AXI_ARBURST), 136 | .S_AXI_ARREADY(M_AXI_ARREADY), 137 | .S_AXI_RVALID(M_AXI_RVALID), 138 | .S_AXI_RDATA(M_AXI_RDATA), 139 | .S_AXI_RRESP(M_AXI_RRESP), 140 | .S_AXI_RLAST(M_AXI_RLAST), 141 | .S_AXI_RREADY(M_AXI_RREADY), 142 | .S_AXI_AWVALID(M_AXI_AWVALID), 143 | .S_AXI_AWADDR(M_AXI_AWADDR), 144 | .S_AXI_AWLEN(M_AXI_AWLEN), 145 | .S_AXI_AWSIZE(M_AXI_AWSIZE), 146 | .S_AXI_AWBURST(M_AXI_AWBURST), 147 | .S_AXI_AWREADY(M_AXI_AWREADY), 148 | .S_AXI_WVALID(M_AXI_WVALID), 149 | .S_AXI_WDATA(M_AXI_WDATA), 150 | .S_AXI_WSTRB(M_AXI_WSTRB), 151 | .S_AXI_WLAST(M_AXI_WLAST), 152 | .S_AXI_WREADY(M_AXI_WREADY), 153 | .S_AXI_BVALID(M_AXI_BVALID), 154 | .S_AXI_BRESP(M_AXI_BRESP), 155 | .S_AXI_BREADY(M_AXI_BREADY) 156 | ); 157 | 158 | 159 | endmodule -------------------------------------------------------------------------------- /backup/axi_dma_ctl_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/02/25 17:45:07 7 | // Design Name: 8 | // Module Name: axi_dma_ctl_tb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module test; 23 | 24 | parameter integer ADDR_WD = 32; 25 | parameter integer DATA_WD = 32; 26 | parameter integer DATA_WD_BYTE = DATA_WD / 8; 27 | 28 | reg clk; 29 | reg rst; 30 | reg cmd_valid; 31 | reg [ADDR_WD-1 : 0] cmd_src_addr; 32 | reg [ADDR_WD-1 : 0] cmd_dst_addr; 33 | reg [1:0] cmd_burst; 34 | reg [ADDR_WD-1 : 0] cmd_len; 35 | reg [2:0] cmd_size; 36 | wire cmd_ready; 37 | // wire M_AXI_ARVALID; 38 | // wire M_AXI_ARADDR; 39 | // wire M_AXI_ARLEN; 40 | // wire M_AXI_ARSIZE; 41 | // wire M_AXI_ARBURST; 42 | // reg M_AXI_ARREADY; 43 | // reg M_AXI_RVALID; 44 | // reg M_AXI_RDATA; 45 | // reg M_AXI_RRESP; 46 | // reg M_AXI_RLAST; 47 | // wire M_AXI_RREADY; 48 | // wire M_AXI_AWVALID; 49 | // wire M_AXI_AWADDR; 50 | // wire M_AXI_AWLEN; 51 | // wire M_AXI_AWSIZE; 52 | // wire M_AXI_AWBURST; 53 | // reg M_AXI_AWREADY; 54 | // wire M_AXI_WVALID; 55 | // wire M_AXI_WDATA; 56 | // wire M_AXI_WSTRB; 57 | // wire M_AXI_WLAST; 58 | // reg M_AXI_WREADY; 59 | // reg M_AXI_BVALID; 60 | // reg M_AXI_BRESP; 61 | // wire M_AXI_BREADY; 62 | 63 | // reg [DATA_WD - 1:0] mem [2**ADDR_WD - 1:0]; 64 | // reg r_s_ar_ready; 65 | // reg r_s_aw_ready; 66 | 67 | parameter FIXED = 'd0; 68 | parameter INCR = 'd1; 69 | parameter WRAP = 'd2; 70 | 71 | 72 | 73 | // Instantiate design under test 74 | top DUT( 75 | .clk(clk), 76 | .rst(rst), 77 | .cmd_valid(cmd_valid), 78 | .cmd_src_addr(cmd_src_addr), 79 | .cmd_dst_addr(cmd_dst_addr), 80 | .cmd_burst(cmd_burst), 81 | .cmd_len(cmd_len), 82 | .cmd_size(cmd_size), 83 | .cmd_ready(cmd_ready) 84 | // .M_AXI_ARVALID(M_AXI_ARVALID), 85 | // .M_AXI_ARADDR(M_AXI_ARADDR), 86 | // .M_AXI_ARLEN(M_AXI_ARLEN), 87 | // .M_AXI_ARSIZE(M_AXI_ARSIZE), 88 | // .M_AXI_ARBURST(M_AXI_ARBURST), 89 | // .M_AXI_ARREADY(M_AXI_ARREADY), 90 | // .M_AXI_RVALID(M_AXI_RVALID), 91 | // .M_AXI_RDATA(M_AXI_RDATA), 92 | // .M_AXI_RRESP(M_AXI_RRESP), 93 | // .M_AXI_RLAST(M_AXI_RLAST), 94 | // .M_AXI_RREADY(M_AXI_RREADY), 95 | // .M_AXI_AWVALID(M_AXI_AWVALID), 96 | // .M_AXI_AWADDR(M_AXI_AWADDR), 97 | // .M_AXI_AWLEN(M_AXI_AWLEN), 98 | // .M_AXI_AWSIZE(M_AXI_AWSIZE), 99 | // .M_AXI_AWBURST(M_AXI_AWBURST), 100 | // .M_AXI_AWREADY(M_AXI_AWREADY), 101 | // .M_AXI_WVALID(M_AXI_WVALID), 102 | // .M_AXI_WDATA(M_AXI_WDATA), 103 | // .M_AXI_WSTRB(M_AXI_WSTRB), 104 | // .M_AXI_WLAST(M_AXI_WLAST), 105 | // .M_AXI_WREADY(M_AXI_WREADY), 106 | // .M_AXI_BVALID(M_AXI_BVALID), 107 | // .M_AXI_BRESP(M_AXI_BRESP), 108 | // .M_AXI_BREADY(M_AXI_BREADY) 109 | ); 110 | 111 | initial begin 112 | clk = 0; 113 | forever #5 clk = ~clk; 114 | end 115 | 116 | initial begin 117 | // Dump waves 118 | // $dumpfile("dump.vcd"); 119 | // $dumpvars(1); 120 | 121 | clk = 0; 122 | rst = 0; 123 | 124 | #100; 125 | rst = 1; 126 | #20; 127 | rst = 0; 128 | cmd_src_addr = 32'd128; 129 | cmd_dst_addr = 32'd512; 130 | cmd_valid = 1; 131 | cmd_burst = INCR; 132 | cmd_len = 32; 133 | cmd_size = 3'b010; 134 | #20; 135 | cmd_valid = 0; 136 | cmd_src_addr = 0; 137 | cmd_dst_addr = 0; 138 | cmd_burst = 0; 139 | cmd_len = 0; 140 | cmd_size = 0; 141 | #200; 142 | rst = 1; 143 | #20; 144 | rst = 0; 145 | cmd_src_addr = 32'd341; 146 | cmd_dst_addr = 32'd124; 147 | cmd_valid = 1; 148 | cmd_burst = FIXED; 149 | cmd_len = 1024; 150 | cmd_size = 3'b010; 151 | #20; 152 | cmd_valid = 0; 153 | #300; 154 | 155 | 156 | 157 | 158 | end 159 | 160 | // always@( posedge clk ) begin 161 | // if(rst) begin 162 | // for(int i = 0; i < 2**ADDR_WD; i++) begin 163 | // mem[i] <= i; 164 | // end 165 | // end 166 | // else begin 167 | // for(int i = 0; i < 2**ADDR_WD; i++) begin 168 | // mem[i] <= mem[i]; 169 | // end 170 | // end 171 | // end 172 | 173 | // always@( posedge clk ) begin 174 | // if(r_s_ar_ready) begin 175 | // M_AXI_ARREADY <= 1; 176 | // end 177 | // else begin 178 | // M_AXI_ARREADY <= 0; 179 | // end 180 | // end 181 | 182 | // always@( posedge clk ) begin 183 | // if(r_s_aw_ready) begin 184 | // M_AXI_AWREADY <= 1; 185 | // end 186 | // else begin 187 | // M_AXI_AWREADY <= 0; 188 | // end 189 | // end 190 | 191 | // task display; 192 | // #1 $display("d:%0h, q:%0h, qb:%0h", 193 | // d, q, qb); 194 | // endtask 195 | 196 | endmodule -------------------------------------------------------------------------------- /backup2/axi_dma_ctl_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/02/25 17:45:07 7 | // Design Name: 8 | // Module Name: axi_dma_ctl_tb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module test; 23 | 24 | parameter integer ADDR_WD = 32; 25 | parameter integer BUS_SIZE = 32; 26 | parameter CMD_SIZE = 3'b010; 27 | 28 | reg clk; 29 | reg rst; 30 | reg cmd_valid; 31 | reg [ADDR_WD-1 : 0] cmd_src_addr; 32 | reg [ADDR_WD-1 : 0] cmd_dst_addr; 33 | reg [1:0] cmd_burst; 34 | reg [ADDR_WD-1 : 0] cmd_len; 35 | reg [2:0] cmd_size; 36 | wire cmd_ready; 37 | // wire M_AXI_ARVALID; 38 | // wire M_AXI_ARADDR; 39 | // wire M_AXI_ARLEN; 40 | // wire M_AXI_ARSIZE; 41 | // wire M_AXI_ARBURST; 42 | // reg M_AXI_ARREADY; 43 | // reg M_AXI_RVALID; 44 | // reg M_AXI_RDATA; 45 | // reg M_AXI_RRESP; 46 | // reg M_AXI_RLAST; 47 | // wire M_AXI_RREADY; 48 | // wire M_AXI_AWVALID; 49 | // wire M_AXI_AWADDR; 50 | // wire M_AXI_AWLEN; 51 | // wire M_AXI_AWSIZE; 52 | // wire M_AXI_AWBURST; 53 | // reg M_AXI_AWREADY; 54 | // wire M_AXI_WVALID; 55 | // wire M_AXI_WDATA; 56 | // wire M_AXI_WSTRB; 57 | // wire M_AXI_WLAST; 58 | // reg M_AXI_WREADY; 59 | // reg M_AXI_BVALID; 60 | // reg M_AXI_BRESP; 61 | // wire M_AXI_BREADY; 62 | 63 | // reg [DATA_WD - 1:0] mem [2**ADDR_WD - 1:0]; 64 | // reg r_s_ar_ready; 65 | // reg r_s_aw_ready; 66 | 67 | parameter FIXED = 'd0; 68 | parameter INCR = 'd1; 69 | parameter WRAP = 'd2; 70 | 71 | 72 | // Instantiate design under test 73 | top #( 74 | .ADDR_WD(ADDR_WD), 75 | .DATA_WD(BUS_SIZE) 76 | )DUT( 77 | .clk(clk), 78 | .rst(rst), 79 | .cmd_valid(cmd_valid), 80 | .cmd_src_addr(cmd_src_addr), 81 | .cmd_dst_addr(cmd_dst_addr), 82 | .cmd_burst(cmd_burst), 83 | .cmd_len(cmd_len), 84 | .cmd_size(cmd_size), 85 | .cmd_ready(cmd_ready) 86 | // .M_AXI_ARVALID(M_AXI_ARVALID), 87 | // .M_AXI_ARADDR(M_AXI_ARADDR), 88 | // .M_AXI_ARLEN(M_AXI_ARLEN), 89 | // .M_AXI_ARSIZE(M_AXI_ARSIZE), 90 | // .M_AXI_ARBURST(M_AXI_ARBURST), 91 | // .M_AXI_ARREADY(M_AXI_ARREADY), 92 | // .M_AXI_RVALID(M_AXI_RVALID), 93 | // .M_AXI_RDATA(M_AXI_RDATA), 94 | // .M_AXI_RRESP(M_AXI_RRESP), 95 | // .M_AXI_RLAST(M_AXI_RLAST), 96 | // .M_AXI_RREADY(M_AXI_RREADY), 97 | // .M_AXI_AWVALID(M_AXI_AWVALID), 98 | // .M_AXI_AWADDR(M_AXI_AWADDR), 99 | // .M_AXI_AWLEN(M_AXI_AWLEN), 100 | // .M_AXI_AWSIZE(M_AXI_AWSIZE), 101 | // .M_AXI_AWBURST(M_AXI_AWBURST), 102 | // .M_AXI_AWREADY(M_AXI_AWREADY), 103 | // .M_AXI_WVALID(M_AXI_WVALID), 104 | // .M_AXI_WDATA(M_AXI_WDATA), 105 | // .M_AXI_WSTRB(M_AXI_WSTRB), 106 | // .M_AXI_WLAST(M_AXI_WLAST), 107 | // .M_AXI_WREADY(M_AXI_WREADY), 108 | // .M_AXI_BVALID(M_AXI_BVALID), 109 | // .M_AXI_BRESP(M_AXI_BRESP), 110 | // .M_AXI_BREADY(M_AXI_BREADY) 111 | ); 112 | 113 | initial begin 114 | clk = 0; 115 | forever #5 clk = ~clk; 116 | end 117 | 118 | initial begin 119 | // Dump waves 120 | // $dumpfile("dump.vcd"); 121 | // $dumpvars(1); 122 | 123 | clk = 0; 124 | rst = 0; 125 | 126 | #100; 127 | rst = 1; 128 | #20; 129 | rst = 0; 130 | cmd_src_addr = 32'd128; 131 | cmd_dst_addr = 32'd512; 132 | cmd_valid = 1; 133 | cmd_burst = INCR; 134 | cmd_len = 32; 135 | cmd_size = 3'b000; 136 | #20; 137 | cmd_valid = 0; 138 | cmd_src_addr = 0; 139 | cmd_dst_addr = 0; 140 | cmd_burst = 0; 141 | cmd_len = 0; 142 | cmd_size = 0; 143 | #200; 144 | rst = 1; 145 | #20; 146 | rst = 0; 147 | cmd_src_addr = 32'd341; 148 | cmd_dst_addr = 32'd124; 149 | cmd_valid = 1; 150 | cmd_burst = INCR; 151 | cmd_len = 1024; 152 | cmd_size = 3'b010; 153 | #20; 154 | cmd_valid = 0; 155 | #300; 156 | 157 | 158 | 159 | 160 | end 161 | 162 | // always@( posedge clk ) begin 163 | // if(rst) begin 164 | // for(int i = 0; i < 2**ADDR_WD; i++) begin 165 | // mem[i] <= i; 166 | // end 167 | // end 168 | // else begin 169 | // for(int i = 0; i < 2**ADDR_WD; i++) begin 170 | // mem[i] <= mem[i]; 171 | // end 172 | // end 173 | // end 174 | 175 | // always@( posedge clk ) begin 176 | // if(r_s_ar_ready) begin 177 | // M_AXI_ARREADY <= 1; 178 | // end 179 | // else begin 180 | // M_AXI_ARREADY <= 0; 181 | // end 182 | // end 183 | 184 | // always@( posedge clk ) begin 185 | // if(r_s_aw_ready) begin 186 | // M_AXI_AWREADY <= 1; 187 | // end 188 | // else begin 189 | // M_AXI_AWREADY <= 0; 190 | // end 191 | // end 192 | 193 | // task display; 194 | // #1 $display("d:%0h, q:%0h, qb:%0h", 195 | // d, q, qb); 196 | // endtask 197 | 198 | endmodule -------------------------------------------------------------------------------- /project_AXI_DMA.srcs/sim_1/new/axi_dma_ctl_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/02/25 17:45:07 7 | // Design Name: 8 | // Module Name: axi_dma_ctl_tb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module test; 23 | 24 | parameter integer ADDR_WD = 32; 25 | parameter integer BUS_SIZE = 32; 26 | parameter CMD_SIZE = 3'b010; 27 | 28 | reg clk; 29 | reg rst; 30 | reg cmd_valid; 31 | reg [ADDR_WD-1 : 0] cmd_src_addr; 32 | reg [ADDR_WD-1 : 0] cmd_dst_addr; 33 | reg [1:0] cmd_burst; 34 | reg [ADDR_WD-1 : 0] cmd_len; 35 | reg [2:0] cmd_size; 36 | wire cmd_ready; 37 | // wire M_AXI_ARVALID; 38 | // wire M_AXI_ARADDR; 39 | // wire M_AXI_ARLEN; 40 | // wire M_AXI_ARSIZE; 41 | // wire M_AXI_ARBURST; 42 | // reg M_AXI_ARREADY; 43 | // reg M_AXI_RVALID; 44 | // reg M_AXI_RDATA; 45 | // reg M_AXI_RRESP; 46 | // reg M_AXI_RLAST; 47 | // wire M_AXI_RREADY; 48 | // wire M_AXI_AWVALID; 49 | // wire M_AXI_AWADDR; 50 | // wire M_AXI_AWLEN; 51 | // wire M_AXI_AWSIZE; 52 | // wire M_AXI_AWBURST; 53 | // reg M_AXI_AWREADY; 54 | // wire M_AXI_WVALID; 55 | // wire M_AXI_WDATA; 56 | // wire M_AXI_WSTRB; 57 | // wire M_AXI_WLAST; 58 | // reg M_AXI_WREADY; 59 | // reg M_AXI_BVALID; 60 | // reg M_AXI_BRESP; 61 | // wire M_AXI_BREADY; 62 | 63 | // reg [DATA_WD - 1:0] mem [2**ADDR_WD - 1:0]; 64 | // reg r_s_ar_ready; 65 | // reg r_s_aw_ready; 66 | 67 | parameter FIXED = 'd0; 68 | parameter INCR = 'd1; 69 | parameter WRAP = 'd2; 70 | 71 | 72 | // Instantiate design under test 73 | top #( 74 | .ADDR_WD(ADDR_WD), 75 | .DATA_WD(BUS_SIZE) 76 | )DUT( 77 | .clk(clk), 78 | .rst(rst), 79 | .cmd_valid(cmd_valid), 80 | .cmd_src_addr(cmd_src_addr), 81 | .cmd_dst_addr(cmd_dst_addr), 82 | .cmd_burst(cmd_burst), 83 | .cmd_len(cmd_len), 84 | .cmd_size(cmd_size), 85 | .cmd_ready(cmd_ready) 86 | // .M_AXI_ARVALID(M_AXI_ARVALID), 87 | // .M_AXI_ARADDR(M_AXI_ARADDR), 88 | // .M_AXI_ARLEN(M_AXI_ARLEN), 89 | // .M_AXI_ARSIZE(M_AXI_ARSIZE), 90 | // .M_AXI_ARBURST(M_AXI_ARBURST), 91 | // .M_AXI_ARREADY(M_AXI_ARREADY), 92 | // .M_AXI_RVALID(M_AXI_RVALID), 93 | // .M_AXI_RDATA(M_AXI_RDATA), 94 | // .M_AXI_RRESP(M_AXI_RRESP), 95 | // .M_AXI_RLAST(M_AXI_RLAST), 96 | // .M_AXI_RREADY(M_AXI_RREADY), 97 | // .M_AXI_AWVALID(M_AXI_AWVALID), 98 | // .M_AXI_AWADDR(M_AXI_AWADDR), 99 | // .M_AXI_AWLEN(M_AXI_AWLEN), 100 | // .M_AXI_AWSIZE(M_AXI_AWSIZE), 101 | // .M_AXI_AWBURST(M_AXI_AWBURST), 102 | // .M_AXI_AWREADY(M_AXI_AWREADY), 103 | // .M_AXI_WVALID(M_AXI_WVALID), 104 | // .M_AXI_WDATA(M_AXI_WDATA), 105 | // .M_AXI_WSTRB(M_AXI_WSTRB), 106 | // .M_AXI_WLAST(M_AXI_WLAST), 107 | // .M_AXI_WREADY(M_AXI_WREADY), 108 | // .M_AXI_BVALID(M_AXI_BVALID), 109 | // .M_AXI_BRESP(M_AXI_BRESP), 110 | // .M_AXI_BREADY(M_AXI_BREADY) 111 | ); 112 | 113 | initial begin 114 | clk = 0; 115 | forever #5 clk = ~clk; 116 | end 117 | 118 | initial begin 119 | // Dump waves 120 | // $dumpfile("dump.vcd"); 121 | // $dumpvars(1); 122 | 123 | clk = 0; 124 | rst = 0; 125 | 126 | #100; 127 | rst = 1; 128 | #20; 129 | rst = 0; 130 | cmd_src_addr = 32'd128; 131 | cmd_dst_addr = 32'd8; 132 | cmd_valid = 1; 133 | cmd_burst = INCR; 134 | cmd_len = 32; 135 | cmd_size = 3'b010; 136 | #20; 137 | cmd_valid = 0; 138 | cmd_src_addr = 0; 139 | cmd_dst_addr = 0; 140 | cmd_burst = 0; 141 | cmd_len = 0; 142 | cmd_size = 0; 143 | #400; 144 | rst = 1; 145 | #20; 146 | rst = 0; 147 | cmd_src_addr = 32'd128; 148 | cmd_dst_addr = 32'd8; 149 | cmd_valid = 1; 150 | cmd_burst = FIXED; 151 | cmd_len = 1024; 152 | cmd_size = 3'b001; 153 | #20; 154 | cmd_valid = 0; 155 | #300; 156 | 157 | 158 | 159 | 160 | end 161 | 162 | // always@( posedge clk ) begin 163 | // if(rst) begin 164 | // for(int i = 0; i < 2**ADDR_WD; i++) begin 165 | // mem[i] <= i; 166 | // end 167 | // end 168 | // else begin 169 | // for(int i = 0; i < 2**ADDR_WD; i++) begin 170 | // mem[i] <= mem[i]; 171 | // end 172 | // end 173 | // end 174 | 175 | // always@( posedge clk ) begin 176 | // if(r_s_ar_ready) begin 177 | // M_AXI_ARREADY <= 1; 178 | // end 179 | // else begin 180 | // M_AXI_ARREADY <= 0; 181 | // end 182 | // end 183 | 184 | // always@( posedge clk ) begin 185 | // if(r_s_aw_ready) begin 186 | // M_AXI_AWREADY <= 1; 187 | // end 188 | // else begin 189 | // M_AXI_AWREADY <= 0; 190 | // end 191 | // end 192 | 193 | // task display; 194 | // #1 $display("d:%0h, q:%0h, qb:%0h", 195 | // d, q, qb); 196 | // endtask 197 | 198 | endmodule -------------------------------------------------------------------------------- /project_AXI_DMA.srcs/sources_1/new/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/02/25 23:16:00 7 | // Design Name: 8 | // Module Name: top 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | `default_nettype none 24 | module top #( 25 | parameter integer ADDR_WD = 32, 26 | parameter integer DATA_WD = 32, 27 | localparam DATA_WD_BYTE = DATA_WD / 8, 28 | localparam STRB_WD = DATA_WD / 8 29 | //localparam BUS_LANES = BUS_SIZE / 8 30 | )( 31 | input wire clk, 32 | input wire rst, 33 | // DMA Command 34 | input wire cmd_valid, 35 | input wire [ADDR_WD-1 : 0] cmd_src_addr, 36 | input wire [ADDR_WD-1 : 0] cmd_dst_addr, 37 | input wire [1:0] cmd_burst, 38 | input wire [ADDR_WD-1 : 0] cmd_len, 39 | input wire [2:0] cmd_size, 40 | output wire cmd_ready 41 | ); 42 | // Read Address Channel 43 | wire M_AXI_ARVALID; 44 | wire [ADDR_WD-1 : 0] M_AXI_ARADDR; 45 | wire [ADDR_WD-1:0] M_AXI_ARLEN; 46 | wire [2:0] M_AXI_ARSIZE; 47 | wire [1:0] M_AXI_ARBURST; 48 | wire M_AXI_ARREADY; 49 | // Read Response Channel 50 | wire M_AXI_RVALID; 51 | wire [DATA_WD-1 : 0] M_AXI_RDATA; 52 | wire [1:0] M_AXI_RRESP; 53 | wire M_AXI_RLAST; 54 | wire M_AXI_RREADY; 55 | wire [STRB_WD-1 : 0] R_strobe; 56 | //wire [BUS_SIZE-1 :0] M_AXI_RBUS; 57 | // Write Address Channel 58 | wire M_AXI_AWVALID; 59 | wire [ADDR_WD-1 : 0] M_AXI_AWADDR; 60 | wire [ADDR_WD-1:0] M_AXI_AWLEN; 61 | wire [2:0] M_AXI_AWSIZE; 62 | wire [1:0] M_AXI_AWBURST; 63 | wire M_AXI_AWREADY; 64 | // Write Data Channel 65 | wire M_AXI_WVALID; 66 | wire [DATA_WD-1 : 0] M_AXI_WDATA; 67 | wire [STRB_WD-1 : 0] M_AXI_WSTRB; 68 | wire M_AXI_WLAST; 69 | wire M_AXI_WREADY; 70 | //wire [BUS_SIZE-1: 0] M_AXI_WBUS; 71 | // Write Response Channel 72 | wire M_AXI_BVALID; 73 | wire [1:0] M_AXI_BRESP; 74 | wire M_AXI_BREADY; 75 | 76 | //byte lane 77 | //wire [$clog2(BUS_LANES) - 1 : 0] AXI_BUS_LANES_SEL; 78 | 79 | // always@(posedge clk) begin 80 | // if(rst) 81 | // AXI_BUS_LANES_SEL <= 0; 82 | // else 83 | // AXI_BUS_LANES_SEL <= AXI_BUS_LANES_SEL + 1; 84 | // end 85 | 86 | axi_dma_controller #( 87 | .ADDR_WD(ADDR_WD), 88 | .DATA_WD(DATA_WD) 89 | )axi_dma_ctl ( 90 | .clk(clk), 91 | .rst(rst), 92 | .cmd_valid(cmd_valid), 93 | .cmd_src_addr(cmd_src_addr), 94 | .cmd_dst_addr(cmd_dst_addr), 95 | .cmd_burst(cmd_burst), 96 | .cmd_len(cmd_len), 97 | .cmd_size(cmd_size), 98 | .cmd_ready(cmd_ready), 99 | .M_AXI_ARVALID(M_AXI_ARVALID), 100 | .M_AXI_ARADDR(M_AXI_ARADDR), 101 | .M_AXI_ARLEN(M_AXI_ARLEN), 102 | .M_AXI_ARSIZE(M_AXI_ARSIZE), 103 | .M_AXI_ARBURST(M_AXI_ARBURST), 104 | .M_AXI_ARREADY(M_AXI_ARREADY), 105 | .M_AXI_RVALID(M_AXI_RVALID), 106 | .M_AXI_RDATA(M_AXI_RDATA), 107 | .M_AXI_RRESP(M_AXI_RRESP), 108 | .M_AXI_RLAST(M_AXI_RLAST), 109 | .M_AXI_RREADY(M_AXI_RREADY), 110 | .M_AXI_AWVALID(M_AXI_AWVALID), 111 | .M_AXI_AWADDR(M_AXI_AWADDR), 112 | .M_AXI_AWLEN(M_AXI_AWLEN), 113 | .M_AXI_AWSIZE(M_AXI_AWSIZE), 114 | .M_AXI_AWBURST(M_AXI_AWBURST), 115 | .M_AXI_AWREADY(M_AXI_AWREADY), 116 | .M_AXI_WVALID(M_AXI_WVALID), 117 | .M_AXI_WDATA(M_AXI_WDATA), 118 | .M_AXI_WSTRB(M_AXI_WSTRB), 119 | .M_AXI_WLAST(M_AXI_WLAST), 120 | .M_AXI_WREADY(M_AXI_WREADY), 121 | .M_AXI_BVALID(M_AXI_BVALID), 122 | .M_AXI_BRESP(M_AXI_BRESP), 123 | .M_AXI_BREADY(M_AXI_BREADY), 124 | .R_strobe(R_strobe) 125 | ); 126 | 127 | axi_slave #( 128 | .ADDR_WD(ADDR_WD), 129 | .DATA_WD(DATA_WD) 130 | )SLAVE ( 131 | .clk(clk), 132 | .rst(rst), 133 | .S_AXI_ARVALID(M_AXI_ARVALID), 134 | .S_AXI_ARADDR(M_AXI_ARADDR), 135 | .S_AXI_ARLEN(M_AXI_ARLEN), 136 | .S_AXI_ARSIZE(M_AXI_ARSIZE), 137 | .S_AXI_ARBURST(M_AXI_ARBURST), 138 | .S_AXI_ARREADY(M_AXI_ARREADY), 139 | .S_AXI_RVALID(M_AXI_RVALID), 140 | .S_AXI_RDATA(M_AXI_RDATA), 141 | .S_AXI_RRESP(M_AXI_RRESP), 142 | .S_AXI_RLAST(M_AXI_RLAST), 143 | .S_AXI_RREADY(M_AXI_RREADY), 144 | .S_AXI_AWVALID(M_AXI_AWVALID), 145 | .S_AXI_AWADDR(M_AXI_AWADDR), 146 | .S_AXI_AWLEN(M_AXI_AWLEN), 147 | .S_AXI_AWSIZE(M_AXI_AWSIZE), 148 | .S_AXI_AWBURST(M_AXI_AWBURST), 149 | .S_AXI_AWREADY(M_AXI_AWREADY), 150 | .S_AXI_WVALID(M_AXI_WVALID), 151 | .S_AXI_WDATA(M_AXI_WDATA), 152 | .S_AXI_WSTRB(M_AXI_WSTRB), 153 | .S_AXI_WLAST(M_AXI_WLAST), 154 | .S_AXI_WREADY(M_AXI_WREADY), 155 | .S_AXI_BVALID(M_AXI_BVALID), 156 | .S_AXI_BRESP(M_AXI_BRESP), 157 | .S_AXI_BREADY(M_AXI_BREADY), 158 | .R_strobe(R_strobe) 159 | ); 160 | 161 | 162 | endmodule -------------------------------------------------------------------------------- /project_AXI_DMA.sim/sim_1/behav/xsim/xsim.dir/test_behav/obj/xsim_1.c: -------------------------------------------------------------------------------- 1 | /**********************************************************************/ 2 | /* ____ ____ */ 3 | /* / /\/ / */ 4 | /* /___/ \ / */ 5 | /* \ \ \/ */ 6 | /* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ 7 | /* / / All Right Reserved. */ 8 | /* /---/ /\ */ 9 | /* \ \ / \ */ 10 | /* \___\/\___\ */ 11 | /**********************************************************************/ 12 | 13 | #if defined(_WIN32) 14 | #include "stdio.h" 15 | #define IKI_DLLESPEC __declspec(dllimport) 16 | #else 17 | #define IKI_DLLESPEC 18 | #endif 19 | #include "iki.h" 20 | #include 21 | #include 22 | #ifdef __GNUC__ 23 | #include 24 | #else 25 | #include 26 | #define alloca _alloca 27 | #endif 28 | /**********************************************************************/ 29 | /* ____ ____ */ 30 | /* / /\/ / */ 31 | /* /___/ \ / */ 32 | /* \ \ \/ */ 33 | /* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ 34 | /* / / All Right Reserved. */ 35 | /* /---/ /\ */ 36 | /* \ \ / \ */ 37 | /* \___\/\___\ */ 38 | /**********************************************************************/ 39 | 40 | #if defined(_WIN32) 41 | #include "stdio.h" 42 | #define IKI_DLLESPEC __declspec(dllimport) 43 | #else 44 | #define IKI_DLLESPEC 45 | #endif 46 | #include "iki.h" 47 | #include 48 | #include 49 | #ifdef __GNUC__ 50 | #include 51 | #else 52 | #include 53 | #define alloca _alloca 54 | #endif 55 | typedef void (*funcp)(char *, char *); 56 | extern int main(int, char**); 57 | IKI_DLLESPEC extern void execute_44(char*, char *); 58 | IKI_DLLESPEC extern void execute_45(char*, char *); 59 | IKI_DLLESPEC extern void execute_89(char*, char *); 60 | IKI_DLLESPEC extern void execute_90(char*, char *); 61 | IKI_DLLESPEC extern void execute_91(char*, char *); 62 | IKI_DLLESPEC extern void execute_92(char*, char *); 63 | IKI_DLLESPEC extern void execute_93(char*, char *); 64 | IKI_DLLESPEC extern void execute_94(char*, char *); 65 | IKI_DLLESPEC extern void execute_95(char*, char *); 66 | IKI_DLLESPEC extern void execute_96(char*, char *); 67 | IKI_DLLESPEC extern void execute_4(char*, char *); 68 | IKI_DLLESPEC extern void execute_5(char*, char *); 69 | IKI_DLLESPEC extern void execute_6(char*, char *); 70 | IKI_DLLESPEC extern void execute_7(char*, char *); 71 | IKI_DLLESPEC extern void execute_8(char*, char *); 72 | IKI_DLLESPEC extern void execute_10(char*, char *); 73 | IKI_DLLESPEC extern void execute_11(char*, char *); 74 | IKI_DLLESPEC extern void execute_12(char*, char *); 75 | IKI_DLLESPEC extern void execute_13(char*, char *); 76 | IKI_DLLESPEC extern void execute_14(char*, char *); 77 | IKI_DLLESPEC extern void execute_15(char*, char *); 78 | IKI_DLLESPEC extern void execute_16(char*, char *); 79 | IKI_DLLESPEC extern void execute_17(char*, char *); 80 | IKI_DLLESPEC extern void execute_18(char*, char *); 81 | IKI_DLLESPEC extern void execute_19(char*, char *); 82 | IKI_DLLESPEC extern void execute_20(char*, char *); 83 | IKI_DLLESPEC extern void execute_21(char*, char *); 84 | IKI_DLLESPEC extern void execute_51(char*, char *); 85 | IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); 86 | IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); 87 | IKI_DLLESPEC extern void execute_69(char*, char *); 88 | IKI_DLLESPEC extern void execute_23(char*, char *); 89 | IKI_DLLESPEC extern void execute_25(char*, char *); 90 | IKI_DLLESPEC extern void execute_26(char*, char *); 91 | IKI_DLLESPEC extern void execute_27(char*, char *); 92 | IKI_DLLESPEC extern void execute_28(char*, char *); 93 | IKI_DLLESPEC extern void execute_29(char*, char *); 94 | IKI_DLLESPEC extern void execute_30(char*, char *); 95 | IKI_DLLESPEC extern void execute_31(char*, char *); 96 | IKI_DLLESPEC extern void execute_33(char*, char *); 97 | IKI_DLLESPEC extern void execute_34(char*, char *); 98 | IKI_DLLESPEC extern void execute_35(char*, char *); 99 | IKI_DLLESPEC extern void execute_36(char*, char *); 100 | IKI_DLLESPEC extern void execute_37(char*, char *); 101 | IKI_DLLESPEC extern void execute_38(char*, char *); 102 | IKI_DLLESPEC extern void execute_39(char*, char *); 103 | IKI_DLLESPEC extern void execute_40(char*, char *); 104 | IKI_DLLESPEC extern void execute_41(char*, char *); 105 | IKI_DLLESPEC extern void execute_42(char*, char *); 106 | IKI_DLLESPEC extern void execute_43(char*, char *); 107 | IKI_DLLESPEC extern void execute_71(char*, char *); 108 | IKI_DLLESPEC extern void execute_72(char*, char *); 109 | IKI_DLLESPEC extern void execute_73(char*, char *); 110 | IKI_DLLESPEC extern void execute_74(char*, char *); 111 | IKI_DLLESPEC extern void execute_75(char*, char *); 112 | IKI_DLLESPEC extern void execute_76(char*, char *); 113 | IKI_DLLESPEC extern void execute_77(char*, char *); 114 | IKI_DLLESPEC extern void execute_83(char*, char *); 115 | IKI_DLLESPEC extern void execute_84(char*, char *); 116 | IKI_DLLESPEC extern void execute_86(char*, char *); 117 | IKI_DLLESPEC extern void execute_88(char*, char *); 118 | IKI_DLLESPEC extern void execute_47(char*, char *); 119 | IKI_DLLESPEC extern void execute_48(char*, char *); 120 | IKI_DLLESPEC extern void execute_49(char*, char *); 121 | IKI_DLLESPEC extern void execute_50(char*, char *); 122 | IKI_DLLESPEC extern void execute_97(char*, char *); 123 | IKI_DLLESPEC extern void execute_98(char*, char *); 124 | IKI_DLLESPEC extern void execute_99(char*, char *); 125 | IKI_DLLESPEC extern void execute_100(char*, char *); 126 | IKI_DLLESPEC extern void execute_101(char*, char *); 127 | IKI_DLLESPEC extern void execute_102(char*, char *); 128 | IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); 129 | funcp funcTab[72] = {(funcp)execute_44, (funcp)execute_45, (funcp)execute_89, (funcp)execute_90, (funcp)execute_91, (funcp)execute_92, (funcp)execute_93, (funcp)execute_94, (funcp)execute_95, (funcp)execute_96, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_51, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_69, (funcp)execute_23, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_71, (funcp)execute_72, (funcp)execute_73, (funcp)execute_74, (funcp)execute_75, (funcp)execute_76, (funcp)execute_77, (funcp)execute_83, (funcp)execute_84, (funcp)execute_86, (funcp)execute_88, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_97, (funcp)execute_98, (funcp)execute_99, (funcp)execute_100, (funcp)execute_101, (funcp)execute_102, (funcp)vlog_transfunc_eventcallback}; 130 | const int NumRelocateId= 72; 131 | 132 | void relocate(char *dp) 133 | { 134 | iki_relocate(dp, "xsim.dir/test_behav/xsim.reloc", (void **)funcTab, 72); 135 | 136 | /*Populate the transaction function pointer field in the whole net structure */ 137 | } 138 | 139 | void sensitize(char *dp) 140 | { 141 | iki_sensitize(dp, "xsim.dir/test_behav/xsim.reloc"); 142 | } 143 | 144 | void simulate(char *dp) 145 | { 146 | iki_schedule_processes_at_time_zero(dp, "xsim.dir/test_behav/xsim.reloc"); 147 | // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net 148 | iki_execute_processes(); 149 | 150 | // Schedule resolution functions for the multiply driven Verilog nets that have strength 151 | // Schedule transaction functions for the singly driven Verilog nets that have strength 152 | 153 | } 154 | #include "iki_bridge.h" 155 | void relocate(char *); 156 | 157 | void sensitize(char *); 158 | 159 | void simulate(char *); 160 | 161 | extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); 162 | extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; 163 | extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; 164 | 165 | int main(int argc, char **argv) 166 | { 167 | iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; 168 | iki_set_sv_type_file_path_name("xsim.dir/test_behav/xsim.svtype"); 169 | iki_set_crvs_dump_file_path_name("xsim.dir/test_behav/xsim.crvsdump"); 170 | void* design_handle = iki_create_design("xsim.dir/test_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); 171 | iki_set_rc_trial_count(100); 172 | (void) design_handle; 173 | return iki_simulate_design(); 174 | } 175 | -------------------------------------------------------------------------------- /backup/axi_dma_controller.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/02/25 17:02:22 7 | // Design Name: 8 | // Module Name: axi_dma_controller 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | `default_nettype none 24 | module axi_dma_controller #( 25 | parameter integer ADDR_WD = 32, 26 | parameter integer DATA_WD = 32, 27 | parameter integer DATA_WD_BYTE = DATA_WD / 8, 28 | localparam integer STRB_WD = DATA_WD / 8 29 | )( 30 | input wire clk, 31 | input wire rst, 32 | // DMA Command 33 | input wire cmd_valid, 34 | input wire [ADDR_WD-1 : 0] cmd_src_addr, 35 | input wire [ADDR_WD-1 : 0] cmd_dst_addr, 36 | input wire [1:0] cmd_burst, 37 | input wire [ADDR_WD-1 : 0] cmd_len, 38 | input wire [2:0] cmd_size, 39 | output wire cmd_ready, 40 | // Read Address Channel 41 | output wire M_AXI_ARVALID, 42 | output wire [ADDR_WD-1 : 0] M_AXI_ARADDR, 43 | output wire [ADDR_WD-1:0] M_AXI_ARLEN, 44 | output wire [2:0] M_AXI_ARSIZE, 45 | output wire [1:0] M_AXI_ARBURST, 46 | input wire M_AXI_ARREADY, 47 | // Read Response Channel 48 | input wire M_AXI_RVALID, 49 | input wire [DATA_WD-1 : 0] M_AXI_RDATA, 50 | input wire [1:0] M_AXI_RRESP, 51 | input wire M_AXI_RLAST, 52 | output wire M_AXI_RREADY, 53 | // Write Address Channel 54 | output wire M_AXI_AWVALID, 55 | output wire [ADDR_WD-1 : 0] M_AXI_AWADDR, 56 | output wire [ADDR_WD-1:0] M_AXI_AWLEN, 57 | output wire [2:0] M_AXI_AWSIZE, 58 | output wire [1:0] M_AXI_AWBURST, 59 | input wire M_AXI_AWREADY, 60 | // Write Data Channel 61 | output wire M_AXI_WVALID, 62 | output wire [DATA_WD-1 : 0] M_AXI_WDATA, 63 | output wire [STRB_WD-1 : 0] M_AXI_WSTRB, 64 | output wire M_AXI_WLAST, 65 | input wire M_AXI_WREADY, 66 | // Write Response Channel 67 | input wire M_AXI_BVALID, 68 | input wire [1:0] M_AXI_BRESP, 69 | output wire M_AXI_BREADY 70 | ); 71 | 72 | reg [DATA_WD - 1:0] mem [0 : 256]; 73 | 74 | reg [ADDR_WD-1 : 0] r_cmd_src_addr ; 75 | reg [ADDR_WD-1 : 0] r_cmd_dst_addr ; 76 | reg [1:0] r_cmd_burst ; 77 | reg [ADDR_WD-1 : 0] r_cmd_len ; 78 | reg [2:0] r_cmd_size ; 79 | reg r_cmd_ready ; 80 | 81 | reg [DATA_WD - 1:0] r_m_axi_rdata ; 82 | reg r_m_axi_rlast ; 83 | reg r_m_axi_rready ; 84 | 85 | reg [ADDR_WD - 1:0] r_m_axi_araddr ; 86 | reg r_m_axi_arvalid ; 87 | reg [ADDR_WD - 1:0] r_m_axi_arlen ; 88 | 89 | reg [ADDR_WD - 1:0] r_m_axi_awaddr ; 90 | reg r_m_axi_awvalid ; 91 | reg [ADDR_WD - 1:0] r_m_axi_awlen ; 92 | 93 | reg [DATA_WD - 1:0] r_m_axi_wdata ; 94 | reg r_m_axi_wlast ; 95 | reg r_m_axi_wvalid ; 96 | reg [8:0] r_write_cnt ; 97 | reg [8:0] r_read_cnt ; 98 | 99 | reg r_read_start ; 100 | reg r_write_start ; 101 | 102 | assign cmd_ready = r_cmd_ready ; 103 | 104 | assign M_AXI_ARLEN = r_m_axi_arlen ; //in word 105 | assign M_AXI_ARSIZE = r_cmd_size ; 106 | assign M_AXI_ARBURST = r_cmd_burst ; 107 | assign M_AXI_ARADDR = r_m_axi_araddr ; 108 | assign M_AXI_ARVALID = r_m_axi_arvalid ; 109 | 110 | assign M_AXI_AWLEN = r_m_axi_awlen ; //in word 111 | assign M_AXI_AWSIZE = r_cmd_size ; 112 | assign M_AXI_AWBURST = r_cmd_burst ; 113 | assign M_AXI_AWADDR = r_m_axi_awaddr ; 114 | assign M_AXI_AWVALID = r_m_axi_awvalid ; 115 | 116 | //assign M_AXI_WSTRB = {STRB_WD{1'b1}} ; 117 | assign M_AXI_WSTRB = {4'b1010} ; 118 | assign M_AXI_WDATA = r_m_axi_wdata ; 119 | assign M_AXI_WLAST = r_m_axi_wlast ; 120 | assign M_AXI_WVALID = r_m_axi_wvalid ; 121 | 122 | assign M_AXI_BREADY = 1'b1 ; 123 | 124 | assign M_AXI_RREADY = r_m_axi_rready ; 125 | 126 | 127 | /*--------------------- dma control -------------------------*/ 128 | 129 | always@(posedge clk) begin 130 | if(rst) begin 131 | r_cmd_src_addr <= 0; 132 | r_cmd_dst_addr <= 0; 133 | r_cmd_burst <= 0; 134 | r_cmd_len <= 0; 135 | r_cmd_size <= 0; 136 | r_m_axi_awlen <= 0; 137 | r_m_axi_arlen <= 0; 138 | r_read_start <= 0; 139 | end 140 | else if(cmd_valid && cmd_ready) begin 141 | r_cmd_src_addr <= cmd_src_addr; 142 | r_cmd_dst_addr <= cmd_dst_addr; 143 | r_cmd_burst <= cmd_burst; 144 | r_cmd_len <= cmd_len; 145 | r_cmd_size <= cmd_size; 146 | r_m_axi_awlen <= cmd_len/(DATA_WD_BYTE); 147 | r_m_axi_arlen <= cmd_len/(DATA_WD_BYTE); 148 | r_read_start <= 1; 149 | end 150 | else begin 151 | r_cmd_src_addr <= r_cmd_src_addr; 152 | r_cmd_dst_addr <= r_cmd_dst_addr; 153 | r_cmd_burst <= r_cmd_burst; 154 | r_cmd_len <= r_cmd_len; 155 | r_cmd_size <= r_cmd_size; 156 | r_read_start <= 0; 157 | r_m_axi_awlen <= r_m_axi_awlen; 158 | r_m_axi_arlen <= r_m_axi_arlen; 159 | end 160 | end 161 | 162 | always@(posedge clk) begin 163 | if(rst) 164 | r_cmd_ready <= 1; 165 | else if(cmd_valid && cmd_ready) 166 | r_cmd_ready <= 0; 167 | else if(M_AXI_BREADY && M_AXI_BVALID) 168 | r_cmd_ready <= 1; 169 | else 170 | r_cmd_ready <= r_cmd_ready; 171 | end 172 | 173 | /*--------------------- address read -------------------------*/ 174 | 175 | always@(posedge clk) begin 176 | if(rst) 177 | r_m_axi_araddr <= 'd0; 178 | else if(r_read_start) 179 | r_m_axi_araddr <= r_cmd_src_addr; 180 | else 181 | r_m_axi_araddr <= r_m_axi_araddr; 182 | end 183 | 184 | always@(posedge clk) begin 185 | if(rst || (M_AXI_ARREADY && M_AXI_ARVALID)) 186 | r_m_axi_arvalid <= 'd0; 187 | else if(r_read_start) 188 | r_m_axi_arvalid <= 'd1; 189 | else 190 | r_m_axi_arvalid <= r_m_axi_arvalid; 191 | end 192 | 193 | /*--------------------- read -------------------------------*/ 194 | 195 | always@(posedge clk) begin 196 | if(rst) 197 | r_m_axi_rready <= 0; 198 | else if(M_AXI_ARREADY && M_AXI_ARVALID) 199 | r_m_axi_rready <= 1; 200 | else 201 | r_m_axi_rready <= r_m_axi_rready; 202 | end 203 | 204 | always@(posedge clk) begin 205 | if(rst) begin 206 | r_read_cnt <= 0; 207 | for(integer i = 0; i < 256; i = i + 1) begin 208 | mem[i] <= 0; 209 | end 210 | end 211 | else if(M_AXI_RVALID && M_AXI_RREADY) begin 212 | r_read_cnt <= r_read_cnt + 1; 213 | mem[r_read_cnt] <= M_AXI_RDATA; 214 | r_m_axi_rdata <= M_AXI_RDATA; 215 | end 216 | else begin 217 | r_read_cnt <= r_read_cnt; 218 | mem[r_read_cnt] <= mem[r_read_cnt]; 219 | r_m_axi_rdata <= r_m_axi_rdata; 220 | end 221 | end 222 | 223 | /*--------------------- address write -------------------------*/ 224 | 225 | always@(posedge clk) begin 226 | if(rst) 227 | r_write_start <= 0; 228 | else if(M_AXI_RLAST) 229 | r_write_start <= 1; 230 | else 231 | r_write_start <= 0; 232 | end 233 | 234 | always@(posedge clk) begin 235 | if(rst) 236 | r_m_axi_awvalid <= 0; 237 | else if(r_write_start) 238 | r_m_axi_awvalid <= 1; 239 | else if(M_AXI_AWREADY && M_AXI_AWVALID) 240 | r_m_axi_awvalid <= 0; 241 | else 242 | r_m_axi_awvalid <= r_m_axi_awvalid; 243 | end 244 | 245 | always@(posedge clk) begin 246 | if(rst) 247 | r_m_axi_awaddr <= 0; 248 | else if(r_write_start) 249 | r_m_axi_awaddr <= r_cmd_dst_addr; 250 | else 251 | r_m_axi_awaddr <= r_m_axi_awaddr; 252 | end 253 | 254 | /*--------------------- write -------------------------------*/ 255 | 256 | always@(posedge clk) begin 257 | if(rst) 258 | r_m_axi_wvalid <= 0; 259 | else if(M_AXI_AWREADY && M_AXI_AWVALID) 260 | r_m_axi_wvalid <= 1; 261 | else 262 | r_m_axi_wvalid <= r_m_axi_wvalid; 263 | end 264 | 265 | always@(posedge clk) begin 266 | if(rst || M_AXI_WLAST) begin 267 | r_m_axi_wdata <= 0; 268 | r_write_cnt <= 1; 269 | end 270 | else if(M_AXI_WREADY && M_AXI_WVALID) begin 271 | r_m_axi_wdata <= mem[r_write_cnt]; 272 | r_write_cnt <= r_write_cnt + 1; 273 | end 274 | else begin 275 | r_m_axi_wdata <= r_m_axi_wdata; 276 | r_write_cnt <= r_write_cnt; 277 | end 278 | end 279 | 280 | always@(posedge clk) begin 281 | if(rst) 282 | r_m_axi_wlast <= 0; 283 | else if(r_write_cnt == M_AXI_AWLEN) 284 | r_m_axi_wlast <= 1; 285 | else 286 | r_m_axi_wlast <= 0; 287 | end 288 | 289 | /*--------------------- write response -----------------------*/ 290 | 291 | assign M_AXI_BREADY = 1'b1; 292 | 293 | 294 | endmodule 295 | 296 | 297 | 298 | 299 | -------------------------------------------------------------------------------- /backup2/axi_dma_controller.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/02/25 17:02:22 7 | // Design Name: 8 | // Module Name: axi_dma_controller 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | `default_nettype none 24 | module axi_dma_controller #( 25 | parameter integer ADDR_WD = 32, 26 | parameter integer DATA_WD = 32, 27 | localparam integer DATA_WD_BYTE = DATA_WD / 8, 28 | localparam integer STRB_WD = DATA_WD / 8 29 | )( 30 | input wire clk, 31 | input wire rst, 32 | // DMA Command 33 | input wire cmd_valid, 34 | input wire [ADDR_WD-1 : 0] cmd_src_addr, 35 | input wire [ADDR_WD-1 : 0] cmd_dst_addr, 36 | input wire [1:0] cmd_burst, 37 | input wire [ADDR_WD-1 : 0] cmd_len, 38 | input wire [2:0] cmd_size, 39 | output wire cmd_ready, 40 | // Read Address Channel 41 | output wire M_AXI_ARVALID, 42 | output wire [ADDR_WD-1 : 0] M_AXI_ARADDR, 43 | output wire [ADDR_WD-1:0] M_AXI_ARLEN, 44 | output wire [2:0] M_AXI_ARSIZE, 45 | output wire [1:0] M_AXI_ARBURST, 46 | input wire M_AXI_ARREADY, 47 | // Read Response Channel 48 | input wire M_AXI_RVALID, 49 | input wire [DATA_WD-1 : 0] M_AXI_RDATA, 50 | input wire [1:0] M_AXI_RRESP, 51 | input wire M_AXI_RLAST, 52 | output wire M_AXI_RREADY, 53 | // Write Address Channel 54 | output wire M_AXI_AWVALID, 55 | output wire [ADDR_WD-1 : 0] M_AXI_AWADDR, 56 | output wire [ADDR_WD-1:0] M_AXI_AWLEN, 57 | output wire [2:0] M_AXI_AWSIZE, 58 | output wire [1:0] M_AXI_AWBURST, 59 | input wire M_AXI_AWREADY, 60 | // Write Data Channel 61 | output wire M_AXI_WVALID, 62 | output wire [DATA_WD-1 : 0] M_AXI_WDATA, 63 | output wire [STRB_WD-1 : 0] M_AXI_WSTRB, 64 | output wire M_AXI_WLAST, 65 | input wire M_AXI_WREADY, 66 | // Write Response Channel 67 | input wire M_AXI_BVALID, 68 | input wire [1:0] M_AXI_BRESP, 69 | output wire M_AXI_BREADY 70 | ); 71 | 72 | reg [DATA_WD - 1:0] mem [0 : 256]; 73 | 74 | reg [ADDR_WD-1 : 0] r_cmd_src_addr ; 75 | reg [ADDR_WD-1 : 0] r_cmd_dst_addr ; 76 | reg [1:0] r_cmd_burst ; 77 | reg [ADDR_WD-1 : 0] r_cmd_len ; 78 | reg [2:0] r_cmd_size ; 79 | reg r_cmd_ready ; 80 | 81 | reg [DATA_WD - 1:0] r_m_axi_rdata ; 82 | reg r_m_axi_rlast ; 83 | reg r_m_axi_rready ; 84 | 85 | reg [ADDR_WD - 1:0] r_m_axi_araddr ; 86 | reg r_m_axi_arvalid ; 87 | reg [ADDR_WD - 1:0] r_m_axi_arlen ; 88 | 89 | reg [ADDR_WD - 1:0] r_m_axi_awaddr ; 90 | reg r_m_axi_awvalid ; 91 | reg [ADDR_WD - 1:0] r_m_axi_awlen ; 92 | 93 | reg [DATA_WD - 1:0] r_m_axi_wdata ; 94 | reg r_m_axi_wlast ; 95 | reg r_m_axi_wvalid ; 96 | reg [STRB_WD -1:0] r_m_axi_wstrb ; 97 | reg [8:0] r_write_cnt ; 98 | reg [8:0] r_read_cnt ; 99 | 100 | reg r_read_start ; 101 | reg r_write_start ; 102 | 103 | wire [7:0] TRANS_PER_DATA ; 104 | wire [7:0] r_cmd_size_byte ; 105 | 106 | assign r_cmd_size_byte = 2**(r_cmd_size) ; 107 | assign cmd_ready = r_cmd_ready ; 108 | 109 | assign M_AXI_ARLEN = r_m_axi_arlen ; //in word 110 | assign M_AXI_ARSIZE = r_cmd_size ; 111 | assign M_AXI_ARBURST = r_cmd_burst ; 112 | assign M_AXI_ARADDR = r_m_axi_araddr ; 113 | assign M_AXI_ARVALID = r_m_axi_arvalid ; 114 | 115 | assign M_AXI_AWLEN = r_m_axi_awlen ; //in word 116 | assign M_AXI_AWSIZE = r_cmd_size ; 117 | assign M_AXI_AWBURST = r_cmd_burst ; 118 | assign M_AXI_AWADDR = r_m_axi_awaddr ; 119 | assign M_AXI_AWVALID = r_m_axi_awvalid ; 120 | 121 | //assign M_AXI_WSTRB = {STRB_WD{1'b1}} ; 122 | assign M_AXI_WSTRB = r_m_axi_wstrb ; 123 | assign M_AXI_WDATA = r_m_axi_wdata ; 124 | assign M_AXI_WLAST = r_m_axi_wlast ; 125 | assign M_AXI_WVALID = r_m_axi_wvalid ; 126 | 127 | assign M_AXI_BREADY = 1'b1 ; 128 | 129 | assign M_AXI_RREADY = r_m_axi_rready ; 130 | assign TRANS_PER_DATA = DATA_WD_BYTE/r_cmd_size_byte ; 131 | 132 | 133 | /*--------------------- dma control -------------------------*/ 134 | 135 | always@(posedge clk) begin 136 | if(rst) begin 137 | r_cmd_src_addr <= 0; 138 | r_cmd_dst_addr <= 0; 139 | r_cmd_burst <= 0; 140 | r_cmd_len <= 0; 141 | r_cmd_size <= 0; 142 | r_m_axi_awlen <= 0; 143 | r_m_axi_arlen <= 0; 144 | r_read_start <= 0; 145 | end 146 | else if(cmd_valid && cmd_ready) begin 147 | r_cmd_src_addr <= cmd_src_addr; 148 | r_cmd_dst_addr <= cmd_dst_addr; 149 | r_cmd_burst <= cmd_burst; 150 | r_cmd_len <= cmd_len; 151 | r_cmd_size <= cmd_size; 152 | r_m_axi_awlen <= cmd_len/(DATA_WD_BYTE); 153 | r_m_axi_arlen <= cmd_len/(DATA_WD_BYTE); 154 | r_read_start <= 1; 155 | end 156 | else begin 157 | r_cmd_src_addr <= r_cmd_src_addr; 158 | r_cmd_dst_addr <= r_cmd_dst_addr; 159 | r_cmd_burst <= r_cmd_burst; 160 | r_cmd_len <= r_cmd_len; 161 | r_cmd_size <= r_cmd_size; 162 | r_read_start <= 0; 163 | r_m_axi_awlen <= r_m_axi_awlen; 164 | r_m_axi_arlen <= r_m_axi_arlen; 165 | end 166 | end 167 | 168 | always@(posedge clk) begin 169 | if(rst) 170 | r_cmd_ready <= 1; 171 | else if(cmd_valid && cmd_ready) 172 | r_cmd_ready <= 0; 173 | else if(M_AXI_BREADY && M_AXI_BVALID) 174 | r_cmd_ready <= 1; 175 | else 176 | r_cmd_ready <= r_cmd_ready; 177 | end 178 | 179 | /*--------------------- address read -------------------------*/ 180 | 181 | always@(posedge clk) begin 182 | if(rst) 183 | r_m_axi_araddr <= 'd0; 184 | else if(r_read_start) 185 | r_m_axi_araddr <= r_cmd_src_addr; 186 | else 187 | r_m_axi_araddr <= r_m_axi_araddr; 188 | end 189 | 190 | always@(posedge clk) begin 191 | if(rst || (M_AXI_ARREADY && M_AXI_ARVALID)) 192 | r_m_axi_arvalid <= 'd0; 193 | else if(r_read_start) 194 | r_m_axi_arvalid <= 'd1; 195 | else 196 | r_m_axi_arvalid <= r_m_axi_arvalid; 197 | end 198 | 199 | /*--------------------- read -------------------------------*/ 200 | 201 | always@(posedge clk) begin 202 | if(rst) 203 | r_m_axi_rready <= 0; 204 | else if(M_AXI_ARREADY && M_AXI_ARVALID) 205 | r_m_axi_rready <= 1; 206 | else 207 | r_m_axi_rready <= r_m_axi_rready; 208 | end 209 | 210 | always@(posedge clk) begin 211 | if(rst || r_trans_num == TRANS_PER_DATA) 212 | r_trans_num <= 0; 213 | else if(M_AXI_RREADY && M_AXI_RVALID) 214 | r_trans_num <= r_trans_num + 1; 215 | else 216 | r_trans_num <= r_trans_num; 217 | end 218 | 219 | always@(posedge clk) begin 220 | if(rst) begin 221 | r_read_cnt <= 0; 222 | for(integer i = 0; i < 256; i = i + 1) begin 223 | mem[i] <= 0; 224 | end 225 | end 226 | else if(M_AXI_RVALID && M_AXI_RREADY) begin 227 | r_read_cnt <= r_read_cnt + 1; 228 | case(r_cmd_size_byte) 229 | 1: begin 230 | case(DATA_WD_BYTE) 231 | 32: begin 232 | mem[r_read_cnt] <= M_AXI_RDATA >> (r_trans_num*r_cmd_size); 233 | end 234 | end 235 | end 236 | else begin 237 | r_read_cnt <= r_read_cnt; 238 | mem[r_read_cnt] <= mem[r_read_cnt]; 239 | end 240 | end 241 | 242 | /*--------------------- address write -------------------------*/ 243 | 244 | always@(posedge clk) begin 245 | if(rst) 246 | r_write_start <= 0; 247 | else if(M_AXI_RLAST) 248 | r_write_start <= 1; 249 | else 250 | r_write_start <= 0; 251 | end 252 | 253 | always@(posedge clk) begin 254 | if(rst) 255 | r_m_axi_awvalid <= 0; 256 | else if(r_write_start) 257 | r_m_axi_awvalid <= 1; 258 | else if(M_AXI_AWREADY && M_AXI_AWVALID) 259 | r_m_axi_awvalid <= 0; 260 | else 261 | r_m_axi_awvalid <= r_m_axi_awvalid; 262 | end 263 | 264 | always@(posedge clk) begin 265 | if(rst) 266 | r_m_axi_awaddr <= 0; 267 | else if(r_write_start) 268 | r_m_axi_awaddr <= r_cmd_dst_addr; 269 | else 270 | r_m_axi_awaddr <= r_m_axi_awaddr; 271 | end 272 | 273 | /*--------------------- write -------------------------------*/ 274 | 275 | always@(posedge clk) begin 276 | if(rst) 277 | r_m_axi_wvalid <= 0; 278 | else if(M_AXI_AWREADY && M_AXI_AWVALID) 279 | r_m_axi_wvalid <= 1; 280 | else 281 | r_m_axi_wvalid <= r_m_axi_wvalid; 282 | end 283 | //strobe assign 284 | always@(posedge clk) begin 285 | if(rst || w_trans_num == TRANS_PER_DATA) 286 | w_trans_num <= 0; 287 | else if(M_AXI_WREADY && M_AXI_WVALID) 288 | w_trans_num <= w_trans_num = w_trans_num + 1; 289 | else 290 | w_trans_num <= w_trans_num; 291 | end 292 | 293 | always@(posedge clk) begin 294 | if(rst) 295 | r_m_axi_wstrb <= 0; 296 | else if(M_AXI_WREADY && M_AXI_WVALID)begin 297 | if(r_cmd_size_byte <= DATA_WD_BYTE) begin 298 | case(TRANS_PER_DATA) 299 | 1: r_m_axi_wstrb <= {STRB_WD{1'b1}}; 300 | 2: trans_num <= {r_cmd_size_byte/2{1'b1},r_cmd_size_byte/2{1'b0}} 301 | 4: 302 | 8: 303 | end 304 | 305 | end 306 | else 307 | r_m_axi_wstrb <= r_m_axi_wstrb; 308 | end 309 | 310 | always@(posedge clk) begin 311 | if(rst || M_AXI_WLAST) begin 312 | r_m_axi_wdata <= 0; 313 | r_write_cnt <= 1; 314 | end 315 | else if(M_AXI_WREADY && M_AXI_WVALID) begin 316 | r_m_axi_wdata <= mem[r_write_cnt]; 317 | r_write_cnt <= r_write_cnt + 1; 318 | end 319 | else begin 320 | r_m_axi_wdata <= r_m_axi_wdata; 321 | r_write_cnt <= r_write_cnt; 322 | end 323 | end 324 | 325 | always@(posedge clk) begin 326 | if(rst) 327 | r_m_axi_wlast <= 0; 328 | else if(r_write_cnt == M_AXI_AWLEN) 329 | r_m_axi_wlast <= 1; 330 | else 331 | r_m_axi_wlast <= 0; 332 | end 333 | 334 | /*--------------------- write response -----------------------*/ 335 | 336 | assign M_AXI_BREADY = 1'b1; 337 | 338 | 339 | endmodule 340 | 341 | 342 | 343 | 344 | -------------------------------------------------------------------------------- /backup/axi_slave.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/02/25 21:37:46 7 | // Design Name: 8 | // Module Name: axi_slave 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `default_nettype none 23 | module axi_slave# 24 | ( 25 | parameter ADDR_WD = 32, 26 | parameter DATA_WD = 32, 27 | parameter DATA_WD_BYTE = DATA_WD / 8, 28 | localparam STRB_WD = DATA_WD / 8 29 | ) 30 | ( 31 | input wire clk, 32 | input wire rst, 33 | 34 | // Read Address Channel 35 | input wire S_AXI_ARVALID, 36 | input wire [ADDR_WD-1 : 0] S_AXI_ARADDR, 37 | input wire [ADDR_WD-1:0] S_AXI_ARLEN, 38 | input wire [2:0] S_AXI_ARSIZE, 39 | input wire [1:0] S_AXI_ARBURST, 40 | output wire S_AXI_ARREADY, 41 | // Read Response Channel 42 | output wire S_AXI_RVALID, 43 | output wire [DATA_WD-1 : 0] S_AXI_RDATA, 44 | output wire [1:0] S_AXI_RRESP, 45 | output wire S_AXI_RLAST, 46 | input wire S_AXI_RREADY, 47 | // Write Address Channel 48 | input wire S_AXI_AWVALID, 49 | input wire [ADDR_WD-1 : 0] S_AXI_AWADDR, 50 | input wire [ADDR_WD-1:0] S_AXI_AWLEN, 51 | input wire [2:0] S_AXI_AWSIZE, 52 | input wire [1:0] S_AXI_AWBURST, 53 | output wire S_AXI_AWREADY, 54 | // Write Data Channel 55 | input wire S_AXI_WVALID, 56 | input wire [DATA_WD-1 : 0] S_AXI_WDATA, 57 | input wire [STRB_WD-1 : 0] S_AXI_WSTRB, 58 | input wire S_AXI_WLAST, 59 | output wire S_AXI_WREADY, 60 | // Write Response Channel 61 | output wire S_AXI_BVALID, 62 | output wire [1:0] S_AXI_BRESP, 63 | input wire S_AXI_BREADY 64 | ); 65 | 66 | /**********************参数***************************/ 67 | 68 | /**********************状�?�机*************************/ 69 | 70 | /**********************寄存�?*************************/ 71 | 72 | 73 | reg [ADDR_WD-1 : 0] r_awaddr ; 74 | reg [ADDR_WD-1:0] r_awlen ; 75 | reg r_awready ; 76 | reg r_wready ; 77 | reg r_arready ; 78 | reg [ADDR_WD-1 : 0] r_araddr ; 79 | reg [ADDR_WD-1:0] r_arlen ; 80 | reg [8 : 0] r_read_cnt ; 81 | reg [8 : 0] r_write_cnt ; 82 | reg r_rvalid ; 83 | reg [DATA_WD - 1:0] r_rdata ; 84 | reg r_bvalid ; 85 | reg r_w_active_1 ; 86 | reg [DATA_WD - 1:0] r_w_strobe ; 87 | 88 | // reg [DATA_WD-1 : 0] r_ram [0 : 255] ; 89 | // reg [7:0] r_ram_addr ; 90 | // reg [DATA_WD-1 : 0] r_ram_write_data ; 91 | // reg [DATA_WD-1 : 0] r_ram_read_data ; 92 | // reg r_ram_rh_wl ; 93 | // reg r_ram_en ; 94 | 95 | reg [DATA_WD - 1:0] mem [0 : 2**12 - 1]; 96 | 97 | wire w_aw_active ; 98 | wire w_w_active ; 99 | wire w_b_active ; 100 | wire w_ar_active ; 101 | wire w_r_active ; 102 | 103 | assign w_aw_active = S_AXI_AWVALID & S_AXI_AWREADY ; 104 | assign w_w_active = S_AXI_WVALID & S_AXI_WREADY ; 105 | assign w_b_active = S_AXI_BVALID & S_AXI_BREADY ; 106 | assign w_ar_active = S_AXI_ARVALID & S_AXI_ARREADY ; 107 | assign w_r_active = S_AXI_RVALID & S_AXI_RREADY ; 108 | assign S_AXI_AWREADY = r_awready ; 109 | assign S_AXI_WREADY = r_wready ; 110 | assign S_AXI_ARREADY = r_arready ; 111 | 112 | assign S_AXI_RDATA = r_rdata ; 113 | assign S_AXI_RRESP = 'd0 ; //response OKAY 114 | assign S_AXI_RLAST = (r_read_cnt == r_arlen ) ? 115 | w_r_active : 1'b0 ; 116 | assign S_AXI_RVALID = r_rvalid ; 117 | assign S_AXI_BRESP = 'd0 ; 118 | assign S_AXI_BVALID = r_bvalid ; 119 | /********************** mem initialize ***************************/ 120 | 121 | always@ * begin 122 | for(integer j; j < 4; j = j + 1) begin 123 | r_w_strobe[j*8 + 7:j*8] = {8{S_AXI_WSTRB[j]}}; 124 | end 125 | end 126 | 127 | always@(posedge clk) begin 128 | if(rst) begin 129 | for(integer i = 0; i < 2**12; i = i + 1) begin 130 | mem[i] <= i; 131 | end 132 | end 133 | else begin 134 | for(integer i = 0; i < 2**12; i = i + 1) begin 135 | mem[i] <= mem[i]; 136 | end 137 | end 138 | end 139 | /**********************write address***************************/ 140 | always@(posedge clk) begin 141 | if(w_aw_active) 142 | r_awaddr <= S_AXI_AWADDR; 143 | else 144 | r_awaddr <= r_awaddr; 145 | end 146 | 147 | always@(posedge clk) begin 148 | if(w_aw_active) 149 | r_awlen <= S_AXI_AWLEN; 150 | // else if() 151 | else 152 | r_awlen <= r_awlen; 153 | end 154 | 155 | always@(posedge clk) begin 156 | if(rst || S_AXI_WLAST) begin 157 | r_awready <= 'd1; 158 | r_write_cnt <= 0; 159 | end 160 | else if(w_w_active) begin 161 | r_awready <= 'd0; 162 | r_write_cnt <= r_write_cnt + 1; 163 | end 164 | else begin 165 | r_awready <= r_awready; 166 | r_write_cnt <= r_write_cnt; 167 | end 168 | end 169 | 170 | always@(posedge clk) begin 171 | if(w_aw_active) 172 | r_wready <= 'd1; 173 | else if(S_AXI_WLAST) 174 | r_wready <= 'd0; 175 | else 176 | r_wready <= r_wready; 177 | end 178 | // delay 1 cycle for store 179 | always@(posedge clk) begin 180 | if(rst || S_AXI_WLAST) 181 | r_w_active_1 <= 0; 182 | else 183 | r_w_active_1 <= w_w_active; 184 | end 185 | /*--------------------------write-------------------------------*/ 186 | always@(posedge clk) begin 187 | case(S_AXI_AWBURST) 188 | 2'b0: begin //FIXED mode 189 | if(r_w_active_1) 190 | mem[S_AXI_AWADDR] <= S_AXI_WDATA & r_w_strobe; 191 | else 192 | mem[S_AXI_AWADDR] <= mem[S_AXI_AWADDR]; 193 | end 194 | 2'b1: begin //INCR mode 195 | if(r_w_active_1) 196 | mem[S_AXI_AWADDR + r_write_cnt - 1] <= S_AXI_WDATA & r_w_strobe; 197 | else 198 | mem[S_AXI_AWADDR + r_write_cnt - 1] <= mem[S_AXI_AWADDR + r_write_cnt - 1]; 199 | end 200 | default: begin //WRAP mode 201 | if(r_w_active_1) 202 | mem[S_AXI_AWADDR] <= S_AXI_WDATA & r_w_strobe; 203 | else 204 | mem[S_AXI_AWADDR] <= mem[S_AXI_AWADDR]; 205 | end 206 | endcase 207 | end 208 | 209 | // //ram核心�? 210 | // always@(posedge clk) begin 211 | // if(!r_ram_rh_wl) 212 | // r_ram[r_ram_addr_1b] <= r_ram_en ? r_ram_write_data : r_ram[r_ram_addr]; 213 | // else 214 | // r_ram[r_ram_addr_1b] <= r_ram[r_ram_addr_1b]; 215 | // end 216 | 217 | // //ram核心�? 218 | // always@(posedge clk) begin 219 | // if(r_ram_rh_wl) 220 | // r_ram_read_data <= r_ram[r_ram_addr_1b] ; 221 | // else 222 | // r_ram_read_data <= r_ram_read_data ; 223 | // end 224 | 225 | // //ram地址 226 | // always@(posedge clk) begin 227 | // if(w_rst || S_AXI_WLAST || S_AXI_RLAST) 228 | // r_ram_addr <= 'd0; 229 | // else if(w_aw_active) 230 | // r_ram_addr <= S_AXI_AWADDR[7:0]; 231 | // else if(w_ar_active) 232 | // r_ram_addr <= S_AXI_ARADDR[7:0]; 233 | // else if(w_w_active || (r_rvalid & S_AXI_RREADY)) 234 | // r_ram_addr <= r_ram_addr + 1; 235 | // else 236 | // r_ram_addr <= r_ram_addr; 237 | // end 238 | 239 | // //ram地址打一�? 240 | // always@(posedge clk) begin 241 | // r_ram_addr_1b <= r_ram_addr; 242 | // end 243 | 244 | //ram写端�? 245 | // always@(posedge clk) begin 246 | // if(w_w_active) 247 | // r_ram_write_data <= S_AXI_WDATA ; 248 | // else 249 | // r_ram_write_data <= r_ram_write_data ; 250 | // end 251 | 252 | // //ram读写控制 253 | // always@(posedge clk) begin 254 | // if(w_ar_active) 255 | // r_ram_rh_wl <= 'd1; 256 | // else if(w_aw_active) 257 | // r_ram_rh_wl <= 'd0; 258 | // else 259 | // r_ram_rh_wl <= r_ram_rh_wl; 260 | // end 261 | 262 | // //ram写使�? 263 | // always@(posedge clk) begin 264 | // if(w_w_active) 265 | // r_ram_en <= 'd1; 266 | // else 267 | // r_ram_en <= 'd0; 268 | // end 269 | 270 | 271 | /**********************read address***************************/ 272 | always@(posedge clk) begin 273 | if(rst || S_AXI_RLAST) 274 | r_arready <= 'd1; 275 | else if(w_ar_active) 276 | r_arready <= 'd0; 277 | else 278 | r_arready <= r_arready; 279 | end 280 | 281 | 282 | always@(posedge clk) begin 283 | if(w_ar_active) 284 | r_araddr <= S_AXI_ARADDR; 285 | else 286 | r_araddr <= r_araddr; 287 | end 288 | 289 | always@(posedge clk) begin 290 | if(w_ar_active) 291 | r_arlen <= S_AXI_ARLEN; 292 | else 293 | r_arlen <= r_arlen; 294 | end 295 | /********************** read ***************************/ 296 | always@(posedge clk) begin 297 | if(rst || S_AXI_RLAST) 298 | r_read_cnt <= 'd0; 299 | else if(w_r_active) 300 | r_read_cnt <= r_read_cnt + 1; 301 | else 302 | r_read_cnt <= r_read_cnt; 303 | end 304 | 305 | always@(posedge clk) begin 306 | case(S_AXI_ARBURST) 307 | 2'd0: begin //FIXED mode 308 | if(rst || S_AXI_RLAST) 309 | r_rdata <= 'd0; 310 | else if(w_r_active) 311 | r_rdata <= mem[r_araddr]; 312 | else 313 | r_rdata <= r_rdata; 314 | end 315 | 2'd1: begin //INCR mode 316 | if(rst || S_AXI_RLAST) 317 | r_rdata <= 'd0; 318 | else if(w_r_active) 319 | r_rdata <= mem[r_read_cnt + r_araddr]; 320 | else 321 | r_rdata <= r_rdata; 322 | end 323 | default: begin //WRAP mode 324 | if(rst || S_AXI_RLAST) 325 | r_rdata <= 'd0; 326 | else if(w_r_active) 327 | r_rdata <= mem[r_araddr]; 328 | else 329 | r_rdata <= r_rdata; 330 | end 331 | endcase 332 | end 333 | 334 | always@(posedge clk) begin 335 | if(rst || S_AXI_RLAST) 336 | r_rvalid <= 'd0; 337 | else if(w_ar_active) 338 | r_rvalid <= 'd1; 339 | else 340 | r_rvalid <= r_rvalid; 341 | end 342 | 343 | always@(posedge clk) begin 344 | if(S_AXI_WLAST) 345 | r_bvalid <= 'd1; 346 | else if(w_b_active) 347 | r_bvalid <= 'd0; 348 | else 349 | r_bvalid <= r_bvalid; 350 | end 351 | 352 | endmodule 353 | 354 | -------------------------------------------------------------------------------- /backup2/axi_slave.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/02/25 21:37:46 7 | // Design Name: 8 | // Module Name: axi_slave 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `default_nettype none 23 | module axi_slave# 24 | ( 25 | parameter ADDR_WD = 32, 26 | parameter DATA_WD = 32, 27 | localparam DATA_WD_BYTE = DATA_WD / 8, 28 | localparam STRB_WD = DATA_WD / 8 29 | ) 30 | ( 31 | input wire clk, 32 | input wire rst, 33 | 34 | // Read Address Channel 35 | input wire S_AXI_ARVALID, 36 | input wire [ADDR_WD-1 : 0] S_AXI_ARADDR, 37 | input wire [ADDR_WD-1:0] S_AXI_ARLEN, 38 | input wire [2:0] S_AXI_ARSIZE, 39 | input wire [1:0] S_AXI_ARBURST, 40 | output wire S_AXI_ARREADY, 41 | // Read Response Channel 42 | output wire S_AXI_RVALID, 43 | output wire [DATA_WD-1 : 0] S_AXI_RDATA, 44 | output wire [1:0] S_AXI_RRESP, 45 | output wire S_AXI_RLAST, 46 | input wire S_AXI_RREADY, 47 | // Write Address Channel 48 | input wire S_AXI_AWVALID, 49 | input wire [ADDR_WD-1 : 0] S_AXI_AWADDR, 50 | input wire [ADDR_WD-1:0] S_AXI_AWLEN, 51 | input wire [2:0] S_AXI_AWSIZE, 52 | input wire [1:0] S_AXI_AWBURST, 53 | output wire S_AXI_AWREADY, 54 | // Write Data Channel 55 | input wire S_AXI_WVALID, 56 | input wire [DATA_WD-1 : 0] S_AXI_WDATA, 57 | input wire [STRB_WD-1 : 0] S_AXI_WSTRB, 58 | input wire S_AXI_WLAST, 59 | output wire S_AXI_WREADY, 60 | // Write Response Channel 61 | output wire S_AXI_BVALID, 62 | output wire [1:0] S_AXI_BRESP, 63 | input wire S_AXI_BREADY 64 | ); 65 | 66 | /**********************参数***************************/ 67 | 68 | /**********************状�?�机*************************/ 69 | 70 | /**********************寄存�?*************************/ 71 | 72 | 73 | reg [ADDR_WD-1 : 0] r_awaddr ; 74 | reg [ADDR_WD-1:0] r_awlen ; 75 | reg r_awready ; 76 | reg r_wready ; 77 | reg r_arready ; 78 | reg [ADDR_WD-1 : 0] r_araddr ; 79 | reg [ADDR_WD-1:0] r_arlen ; 80 | reg [8 : 0] r_read_cnt ; 81 | reg [8 : 0] r_write_cnt ; 82 | reg r_rvalid ; 83 | reg [DATA_WD - 1:0] r_rdata ; 84 | reg r_bvalid ; 85 | reg r_w_active_1 ; 86 | reg [DATA_WD - 1:0] r_w_strobe ; 87 | 88 | // reg [DATA_WD-1 : 0] r_ram [0 : 255] ; 89 | // reg [7:0] r_ram_addr ; 90 | // reg [DATA_WD-1 : 0] r_ram_write_data ; 91 | // reg [DATA_WD-1 : 0] r_ram_read_data ; 92 | // reg r_ram_rh_wl ; 93 | // reg r_ram_en ; 94 | 95 | reg [7:0] mem [0 : 8**12 - 1]; 96 | reg [ADDR_WD : 0] mem_addr ; 97 | reg [7 : 0] mem_write_data ; 98 | reg [7 : 0] mem_read_data ; 99 | reg mem_rh_wl ; 100 | reg mem_en ; 101 | 102 | wire w_aw_active ; 103 | wire w_w_active ; 104 | wire w_b_active ; 105 | wire w_ar_active ; 106 | wire w_r_active ; 107 | wire [ADDR_WD-3 : 0] w_araddr_word ; 108 | wire [ADDR_WD-3 : 0] w_awaddr_word ; 109 | 110 | assign w_aw_active = S_AXI_AWVALID & S_AXI_AWREADY ; 111 | assign w_w_active = S_AXI_WVALID & S_AXI_WREADY ; 112 | assign w_b_active = S_AXI_BVALID & S_AXI_BREADY ; 113 | assign w_ar_active = S_AXI_ARVALID & S_AXI_ARREADY ; 114 | assign w_r_active = S_AXI_RVALID & S_AXI_RREADY ; 115 | assign w_araddr_word = r_araddr/4 ; 116 | assign w_awaddr_word = r_awaddr/4 ; 117 | assign S_AXI_AWREADY = r_awready ; 118 | assign S_AXI_WREADY = r_wready ; 119 | assign S_AXI_ARREADY = r_arready ; 120 | 121 | assign S_AXI_RDATA = r_rdata ; 122 | assign S_AXI_RRESP = 'd0 ; //response OKAY 123 | assign S_AXI_RLAST = (r_read_cnt == r_arlen ) ? 124 | w_r_active : 1'b0 ; 125 | assign S_AXI_RVALID = r_rvalid ; 126 | assign S_AXI_BRESP = 'd0 ; 127 | assign S_AXI_BVALID = r_bvalid ; 128 | 129 | always@ * begin 130 | for(integer j = 0; j < 4; j = j + 1) begin 131 | r_w_strobe[j*8 +:8] = {8{S_AXI_WSTRB[j]}}; 132 | end 133 | end 134 | 135 | /********************** mem initialize ***************************/ 136 | always@(posedge clk) begin 137 | if(rst) begin 138 | for(integer i = 0; i < 2**12; i = i + 1) begin 139 | mem[i] <= i; 140 | end 141 | end 142 | else begin 143 | for(integer i = 0; i < 2**12; i = i + 1) begin 144 | mem[i] <= mem[i]; 145 | end 146 | end 147 | end 148 | 149 | /**********************write address***************************/ 150 | always@(posedge clk) begin 151 | if(w_aw_active) 152 | r_awaddr <= S_AXI_AWADDR; 153 | else 154 | r_awaddr <= r_awaddr; 155 | end 156 | 157 | always@(posedge clk) begin 158 | if(w_aw_active) 159 | r_awlen <= S_AXI_AWLEN; 160 | // else if() 161 | else 162 | r_awlen <= r_awlen; 163 | end 164 | 165 | always@(posedge clk) begin 166 | if(rst || S_AXI_WLAST) begin 167 | r_awready <= 'd1; 168 | r_write_cnt <= 0; 169 | end 170 | else if(w_w_active) begin 171 | r_awready <= 'd0; 172 | r_write_cnt <= r_write_cnt + 1; 173 | end 174 | else begin 175 | r_awready <= r_awready; 176 | r_write_cnt <= r_write_cnt; 177 | end 178 | end 179 | 180 | always@(posedge clk) begin 181 | if(w_aw_active) 182 | r_wready <= 'd1; 183 | else if(S_AXI_WLAST) 184 | r_wready <= 'd0; 185 | else 186 | r_wready <= r_wready; 187 | end 188 | // delay 1 cycle for store 189 | always@(posedge clk) begin 190 | if(rst || S_AXI_WLAST) 191 | r_w_active_1 <= 0; 192 | else 193 | r_w_active_1 <= w_w_active; 194 | end 195 | /*--------------------------write-------------------------------*/ 196 | always@(posedge clk) begin 197 | case(S_AXI_AWBURST) 198 | 2'b0: begin //FIXED mode 199 | if(r_w_active_1) 200 | mem[w_awaddr_word] <= S_AXI_WDATA & r_w_strobe; 201 | else 202 | mem[w_awaddr_word] <= mem[w_awaddr_word]; 203 | end 204 | 2'b1: begin //INCR mode 205 | if(r_w_active_1) 206 | mem[w_awaddr_word + r_write_cnt - 1] <= S_AXI_WDATA & r_w_strobe; 207 | else 208 | mem[w_awaddr_word + r_write_cnt - 1] <= mem[w_awaddr_word + r_write_cnt - 1]; 209 | end 210 | default: begin //WRAP mode 211 | if(r_w_active_1) 212 | mem[w_awaddr_word] <= S_AXI_WDATA & r_w_strobe; 213 | else 214 | mem[w_awaddr_word] <= mem[w_awaddr_word]; 215 | end 216 | endcase 217 | end 218 | 219 | // //ram核心�? 220 | // always@(posedge clk) begin 221 | // if(!r_ram_rh_wl) 222 | // r_ram[r_ram_addr_1b] <= r_ram_en ? r_ram_write_data : r_ram[r_ram_addr]; 223 | // else 224 | // r_ram[r_ram_addr_1b] <= r_ram[r_ram_addr_1b]; 225 | // end 226 | 227 | // //ram核心�? 228 | // always@(posedge clk) begin 229 | // if(r_ram_rh_wl) 230 | // r_ram_read_data <= r_ram[r_ram_addr_1b] ; 231 | // else 232 | // r_ram_read_data <= r_ram_read_data ; 233 | // end 234 | 235 | // //ram地址 236 | // always@(posedge clk) begin 237 | // if(w_rst || S_AXI_WLAST || S_AXI_RLAST) 238 | // r_ram_addr <= 'd0; 239 | // else if(w_aw_active) 240 | // r_ram_addr <= S_AXI_AWADDR[7:0]; 241 | // else if(w_ar_active) 242 | // r_ram_addr <= S_AXI_ARADDR[7:0]; 243 | // else if(w_w_active || (r_rvalid & S_AXI_RREADY)) 244 | // r_ram_addr <= r_ram_addr + 1; 245 | // else 246 | // r_ram_addr <= r_ram_addr; 247 | // end 248 | 249 | // //ram地址打一�? 250 | // always@(posedge clk) begin 251 | // r_ram_addr_1b <= r_ram_addr; 252 | // end 253 | 254 | //ram写端�? 255 | // always@(posedge clk) begin 256 | // if(w_w_active) 257 | // r_ram_write_data <= S_AXI_WDATA ; 258 | // else 259 | // r_ram_write_data <= r_ram_write_data ; 260 | // end 261 | 262 | // //ram读写控制 263 | // always@(posedge clk) begin 264 | // if(w_ar_active) 265 | // r_ram_rh_wl <= 'd1; 266 | // else if(w_aw_active) 267 | // r_ram_rh_wl <= 'd0; 268 | // else 269 | // r_ram_rh_wl <= r_ram_rh_wl; 270 | // end 271 | 272 | // //ram写使�? 273 | // always@(posedge clk) begin 274 | // if(w_w_active) 275 | // r_ram_en <= 'd1; 276 | // else 277 | // r_ram_en <= 'd0; 278 | // end 279 | 280 | 281 | /**********************read address***************************/ 282 | always@(posedge clk) begin 283 | if(rst || S_AXI_RLAST) 284 | r_arready <= 'd1; 285 | else if(w_ar_active) 286 | r_arready <= 'd0; 287 | else 288 | r_arready <= r_arready; 289 | end 290 | 291 | 292 | always@(posedge clk) begin 293 | if(w_ar_active) 294 | r_araddr <= S_AXI_ARADDR; 295 | else 296 | r_araddr <= r_araddr; 297 | end 298 | 299 | always@(posedge clk) begin 300 | if(w_ar_active) 301 | r_arlen <= S_AXI_ARLEN; 302 | else 303 | r_arlen <= r_arlen; 304 | end 305 | /********************** read ***************************/ 306 | always@(posedge clk) begin 307 | if(rst || S_AXI_RLAST) 308 | r_read_cnt <= 'd0; 309 | else if(w_r_active) 310 | r_read_cnt <= r_read_cnt + 1; 311 | else 312 | r_read_cnt <= r_read_cnt; 313 | end 314 | 315 | always@(posedge clk) begin 316 | case(S_AXI_ARBURST) 317 | 2'd0: begin //FIXED mode 318 | if(rst || S_AXI_RLAST) 319 | r_rdata <= 'd0; 320 | else if(w_r_active) 321 | r_rdata <= mem[w_araddr_word]; 322 | else 323 | r_rdata <= r_rdata; 324 | end 325 | 2'd1: begin //INCR mode 326 | if(rst || S_AXI_RLAST) 327 | r_rdata <= 'd0; 328 | else if(w_r_active) 329 | r_rdata <= mem[r_read_cnt + w_araddr_word]; 330 | else 331 | r_rdata <= r_rdata; 332 | end 333 | default: begin //WRAP mode 334 | if(rst || S_AXI_RLAST) 335 | r_rdata <= 'd0; 336 | else if(w_r_active) 337 | r_rdata <= mem[w_araddr_word]; 338 | else 339 | r_rdata <= r_rdata; 340 | end 341 | endcase 342 | end 343 | 344 | always@(posedge clk) begin 345 | if(rst || S_AXI_RLAST) 346 | r_rvalid <= 'd0; 347 | else if(w_ar_active) 348 | r_rvalid <= 'd1; 349 | else 350 | r_rvalid <= r_rvalid; 351 | end 352 | 353 | always@(posedge clk) begin 354 | if(S_AXI_WLAST) 355 | r_bvalid <= 'd1; 356 | else if(w_b_active) 357 | r_bvalid <= 'd0; 358 | else 359 | r_bvalid <= r_bvalid; 360 | end 361 | 362 | endmodule 363 | 364 | -------------------------------------------------------------------------------- /project_AXI_DMA.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 125 | 126 | 127 | 128 | 129 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 161 | 162 | 163 | 164 | 165 | 167 | 168 | 169 | 170 | 171 | 174 | 175 | 177 | 178 | 180 | 181 | 183 | 184 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | default_dashboard 271 | 272 | 273 | 274 | -------------------------------------------------------------------------------- /project_AXI_DMA.srcs/sources_1/new/axi_dma_controller.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/02/25 17:02:22 7 | // Design Name: 8 | // Module Name: axi_dma_controller 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | `default_nettype none 24 | module axi_dma_controller #( 25 | parameter integer ADDR_WD = 32, 26 | parameter integer DATA_WD = 32, 27 | localparam integer DATA_WD_BYTE = DATA_WD / 8, 28 | localparam integer STRB_WD = DATA_WD / 8 29 | )( 30 | input wire clk, 31 | input wire rst, 32 | // DMA Command 33 | input wire cmd_valid, 34 | input wire [ADDR_WD-1 : 0] cmd_src_addr, 35 | input wire [ADDR_WD-1 : 0] cmd_dst_addr, 36 | input wire [1:0] cmd_burst, 37 | input wire [ADDR_WD-1 : 0] cmd_len, 38 | input wire [2:0] cmd_size, 39 | output wire cmd_ready, 40 | // Read Address Channel 41 | output wire M_AXI_ARVALID, 42 | output wire [ADDR_WD-1 : 0] M_AXI_ARADDR, 43 | output wire [ADDR_WD-1:0] M_AXI_ARLEN, 44 | output wire [2:0] M_AXI_ARSIZE, 45 | output wire [1:0] M_AXI_ARBURST, 46 | input wire M_AXI_ARREADY, 47 | // Read Response Channel 48 | input wire M_AXI_RVALID, 49 | input wire [DATA_WD-1 : 0] M_AXI_RDATA, 50 | input wire [1:0] M_AXI_RRESP, 51 | input wire M_AXI_RLAST, 52 | input wire [STRB_WD-1 : 0] R_strobe, 53 | output wire M_AXI_RREADY, 54 | // Write Address Channel 55 | output wire M_AXI_AWVALID, 56 | output wire [ADDR_WD-1 : 0] M_AXI_AWADDR, 57 | output wire [ADDR_WD-1:0] M_AXI_AWLEN, 58 | output wire [2:0] M_AXI_AWSIZE, 59 | output wire [1:0] M_AXI_AWBURST, 60 | input wire M_AXI_AWREADY, 61 | // Write Data Channel 62 | output wire M_AXI_WVALID, 63 | output wire [DATA_WD-1 : 0] M_AXI_WDATA, 64 | output wire [STRB_WD-1 : 0] M_AXI_WSTRB, 65 | output wire M_AXI_WLAST, 66 | input wire M_AXI_WREADY, 67 | // Write Response Channel 68 | input wire M_AXI_BVALID, 69 | input wire [1:0] M_AXI_BRESP, 70 | output wire M_AXI_BREADY 71 | ); 72 | 73 | reg [DATA_WD - 1:0] mem [0 : 256]; 74 | 75 | reg [ADDR_WD-1 : 0] r_cmd_src_addr ; 76 | reg [ADDR_WD-1 : 0] r_cmd_dst_addr ; 77 | reg [1:0] r_cmd_burst ; 78 | reg [2:0] r_cmd_size ; 79 | reg r_cmd_ready ; 80 | 81 | reg r_m_axi_rlast ; 82 | reg r_m_axi_rready ; 83 | 84 | reg [ADDR_WD - 1:0] r_m_axi_araddr ; 85 | reg r_m_axi_arvalid ; 86 | reg [ADDR_WD - 1:0] r_m_axi_arlen ; 87 | 88 | reg [ADDR_WD - 1:0] r_m_axi_awaddr ; 89 | reg r_m_axi_awvalid ; 90 | reg [ADDR_WD - 1:0] r_m_axi_awlen ; 91 | 92 | reg [DATA_WD - 1:0] r_m_axi_wdata ; 93 | reg r_m_axi_wlast ; 94 | reg r_m_axi_wvalid ; 95 | reg [STRB_WD -1:0] r_m_axi_wstrb ; 96 | reg [STRB_WD -1:0] r_m_axi_wstrb_1 ; 97 | reg [8:0] r_write_cnt ; 98 | reg [8:0] r_read_cnt ; 99 | 100 | reg r_read_start ; 101 | reg r_write_start ; 102 | reg [7:0] w_trans_num ; 103 | reg [DATA_WD-1:0] R_strobe_word ; 104 | 105 | wire [7:0] TRANS_PER_DATA ; 106 | wire [7:0] r_cmd_size_byte ; 107 | 108 | assign r_cmd_size_byte = 2**(r_cmd_size) ; 109 | assign cmd_ready = r_cmd_ready ; 110 | 111 | assign M_AXI_ARLEN = r_m_axi_arlen ; //in word 112 | assign M_AXI_ARSIZE = r_cmd_size ; 113 | assign M_AXI_ARBURST = r_cmd_burst ; 114 | assign M_AXI_ARADDR = r_m_axi_araddr ; 115 | assign M_AXI_ARVALID = r_m_axi_arvalid ; 116 | 117 | assign M_AXI_AWLEN = r_m_axi_awlen ; //in word 118 | assign M_AXI_AWSIZE = r_cmd_size ; 119 | assign M_AXI_AWBURST = r_cmd_burst ; 120 | assign M_AXI_AWADDR = r_m_axi_awaddr ; 121 | assign M_AXI_AWVALID = r_m_axi_awvalid ; 122 | 123 | //assign M_AXI_WSTRB = {STRB_WD{1'b1}} ; 124 | assign M_AXI_WSTRB = r_m_axi_wstrb_1 ; 125 | assign M_AXI_WDATA = r_m_axi_wdata ; 126 | assign M_AXI_WLAST = r_m_axi_wlast ; 127 | assign M_AXI_WVALID = r_m_axi_wvalid ; 128 | 129 | assign M_AXI_BREADY = 1'b1 ; 130 | 131 | assign M_AXI_RREADY = r_m_axi_rready ; 132 | assign TRANS_PER_DATA = DATA_WD_BYTE/r_cmd_size_byte ; 133 | 134 | /*--------------------- dma control -------------------------*/ 135 | 136 | always@(posedge clk) begin 137 | if(rst) begin 138 | r_cmd_src_addr <= 0; 139 | r_cmd_dst_addr <= 0; 140 | r_cmd_burst <= 0; 141 | r_cmd_size <= 0; 142 | r_m_axi_awlen <= 1; 143 | r_m_axi_arlen <= 1; 144 | r_read_start <= 0; 145 | end 146 | else if(cmd_valid && cmd_ready) begin 147 | r_cmd_src_addr <= cmd_src_addr; 148 | r_cmd_dst_addr <= cmd_dst_addr; 149 | r_cmd_burst <= cmd_burst; 150 | r_cmd_size <= cmd_size; 151 | r_m_axi_awlen <= cmd_len/(DATA_WD_BYTE); 152 | r_m_axi_arlen <= cmd_len/(DATA_WD_BYTE); 153 | r_read_start <= 1; 154 | end 155 | else begin 156 | r_cmd_src_addr <= r_cmd_src_addr; 157 | r_cmd_dst_addr <= r_cmd_dst_addr; 158 | r_cmd_burst <= r_cmd_burst; 159 | r_cmd_size <= r_cmd_size; 160 | r_read_start <= 0; 161 | r_m_axi_awlen <= r_m_axi_awlen; 162 | r_m_axi_arlen <= r_m_axi_arlen; 163 | end 164 | end 165 | 166 | always@(posedge clk) begin 167 | if(rst) 168 | r_cmd_ready <= 1; 169 | else if(cmd_valid && cmd_ready) 170 | r_cmd_ready <= 0; 171 | else if(M_AXI_BREADY && M_AXI_BVALID) 172 | r_cmd_ready <= 1; 173 | else 174 | r_cmd_ready <= r_cmd_ready; 175 | end 176 | 177 | /*--------------------- address read -------------------------*/ 178 | 179 | always@(posedge clk) begin 180 | if(rst) 181 | r_m_axi_araddr <= 'd0; 182 | else if(r_read_start) 183 | r_m_axi_araddr <= r_cmd_src_addr; 184 | else 185 | r_m_axi_araddr <= r_m_axi_araddr; 186 | end 187 | 188 | always@(posedge clk) begin 189 | if(rst || (M_AXI_ARREADY && M_AXI_ARVALID)) 190 | r_m_axi_arvalid <= 'd0; 191 | else if(r_read_start) 192 | r_m_axi_arvalid <= 'd1; 193 | else 194 | r_m_axi_arvalid <= r_m_axi_arvalid; 195 | end 196 | 197 | /*--------------------- read -------------------------------*/ 198 | integer j; 199 | always@ * begin 200 | for(j = 0; j < STRB_WD; j = j + 1) begin 201 | R_strobe_word[j*8 +:8] = {8{R_strobe[j]}}; 202 | end 203 | end 204 | 205 | always@(posedge clk) begin 206 | if(rst) 207 | r_m_axi_rready <= 0; 208 | else if(M_AXI_ARREADY && M_AXI_ARVALID) 209 | r_m_axi_rready <= 1; 210 | else 211 | r_m_axi_rready <= r_m_axi_rready; 212 | end 213 | 214 | // always@(posedge clk) begin 215 | // if(rst || r_trans_num == TRANS_PER_DATA) 216 | // r_trans_num <= 0; 217 | // else if(M_AXI_RREADY && M_AXI_RVALID) 218 | // r_trans_num <= r_trans_num + 1; 219 | // else 220 | // r_trans_num <= r_trans_num; 221 | // end 222 | 223 | integer i; 224 | always@(posedge clk) begin 225 | if(rst) begin 226 | r_read_cnt <= 0; 227 | for(i = 0; i < 256; i = i + 1) begin 228 | mem[i] <= 0; 229 | end 230 | end 231 | else if(M_AXI_RVALID && M_AXI_RREADY) begin 232 | if(TRANS_PER_DATA == 1) 233 | mem[r_read_cnt - 1] <= (M_AXI_RDATA & R_strobe_word); 234 | else 235 | mem[r_read_cnt/TRANS_PER_DATA] <= mem[r_read_cnt/TRANS_PER_DATA] + (M_AXI_RDATA & R_strobe_word); 236 | r_read_cnt <= r_read_cnt + 1; 237 | end 238 | else begin 239 | r_read_cnt <= r_read_cnt; 240 | mem[r_read_cnt] <= mem[r_read_cnt]; 241 | end 242 | end 243 | 244 | /*--------------------- address write -------------------------*/ 245 | 246 | always@(posedge clk) begin 247 | if(rst) 248 | r_write_start <= 0; 249 | else if(M_AXI_RLAST) 250 | r_write_start <= 1; 251 | else 252 | r_write_start <= 0; 253 | end 254 | 255 | always@(posedge clk) begin 256 | if(rst) 257 | r_m_axi_awvalid <= 0; 258 | else if(r_write_start) 259 | r_m_axi_awvalid <= 1; 260 | else if(M_AXI_AWREADY && M_AXI_AWVALID) 261 | r_m_axi_awvalid <= 0; 262 | else 263 | r_m_axi_awvalid <= r_m_axi_awvalid; 264 | end 265 | 266 | always@(posedge clk) begin 267 | if(rst) 268 | r_m_axi_awaddr <= 0; 269 | else if(r_write_start) 270 | r_m_axi_awaddr <= r_cmd_dst_addr; 271 | else 272 | r_m_axi_awaddr <= r_m_axi_awaddr; 273 | end 274 | 275 | /*--------------------- write -------------------------------*/ 276 | 277 | always@(posedge clk) begin 278 | if(rst) 279 | r_m_axi_wvalid <= 0; 280 | else if(M_AXI_AWREADY && M_AXI_AWVALID) 281 | r_m_axi_wvalid <= 1; 282 | else 283 | r_m_axi_wvalid <= r_m_axi_wvalid; 284 | end 285 | //strobe assign 286 | always@(posedge clk) begin 287 | if(rst || w_trans_num == TRANS_PER_DATA) 288 | w_trans_num <= 1; 289 | else if(M_AXI_WREADY && M_AXI_WVALID) 290 | w_trans_num <= w_trans_num + 1; 291 | else 292 | w_trans_num <= w_trans_num; 293 | end 294 | 295 | always@(posedge clk) begin 296 | r_m_axi_wstrb_1 <= r_m_axi_wstrb; 297 | end 298 | 299 | always@(posedge clk) begin 300 | if(rst || r_m_axi_wlast) 301 | case(TRANS_PER_DATA) 302 | 2: r_m_axi_wstrb <= {{(STRB_WD/2){1'b0}},{(STRB_WD/2){1'b1}}}; 303 | 4: r_m_axi_wstrb <= {{(3*STRB_WD/4){1'b0}},{(STRB_WD/4){1'b1}}}; 304 | 8: r_m_axi_wstrb <= {{(7*STRB_WD/8){1'b0}},{(STRB_WD/8){1'b1}}}; 305 | 16: r_m_axi_wstrb <= {{(15*STRB_WD/16){1'b0}},{(STRB_WD/16){1'b1}}}; 306 | default: r_m_axi_wstrb <= {STRB_WD{1'b1}}; 307 | endcase 308 | else if(M_AXI_WREADY && M_AXI_WVALID)begin 309 | case(TRANS_PER_DATA) 310 | 2: begin 311 | case(w_trans_num) 312 | 0: r_m_axi_wstrb <= {{(STRB_WD/2){1'b0}},{(STRB_WD/2){1'b1}}}; 313 | TRANS_PER_DATA: r_m_axi_wstrb <= {{(STRB_WD/2){1'b0}},{(STRB_WD/2){1'b1}}}; 314 | default: r_m_axi_wstrb <= r_m_axi_wstrb << STRB_WD/2; 315 | endcase 316 | end 317 | 4: begin 318 | case(w_trans_num) 319 | 0: r_m_axi_wstrb <= {{(3*STRB_WD/4){1'b0}},{(STRB_WD/4){1'b1}}}; 320 | TRANS_PER_DATA: r_m_axi_wstrb <= {{(3*STRB_WD/4){1'b0}},{(STRB_WD/4){1'b1}}}; 321 | default: r_m_axi_wstrb <= r_m_axi_wstrb << STRB_WD/4; 322 | endcase 323 | end 324 | 8: begin 325 | case(w_trans_num) 326 | 0: r_m_axi_wstrb <= {{(7*STRB_WD/8){1'b0}},{(STRB_WD/8){1'b1}}}; 327 | TRANS_PER_DATA: r_m_axi_wstrb <= {{(7*STRB_WD/8){1'b0}},{(STRB_WD/8){1'b1}}}; 328 | default: r_m_axi_wstrb <= r_m_axi_wstrb << STRB_WD/8; 329 | endcase 330 | end 331 | 16: begin 332 | case(w_trans_num) 333 | 0: r_m_axi_wstrb <= {{(15*STRB_WD/16){1'b0}},{(STRB_WD/16){1'b1}}}; 334 | TRANS_PER_DATA: r_m_axi_wstrb <= {{(15*STRB_WD/16){1'b0}},{(STRB_WD/16){1'b1}}}; 335 | default: r_m_axi_wstrb <= r_m_axi_wstrb << STRB_WD/16; 336 | endcase 337 | end 338 | default: r_m_axi_wstrb <= {STRB_WD{1'b1}}; 339 | endcase 340 | end 341 | else 342 | r_m_axi_wstrb <= r_m_axi_wstrb; 343 | end 344 | 345 | always@(posedge clk) begin 346 | if(rst || M_AXI_WLAST) begin 347 | r_m_axi_wdata <= 0; 348 | r_write_cnt <= 0; 349 | end 350 | else if(M_AXI_WREADY && M_AXI_WVALID) begin 351 | r_m_axi_wdata <= mem[r_write_cnt/TRANS_PER_DATA]; 352 | r_write_cnt <= r_write_cnt + 1; 353 | end 354 | else begin 355 | r_m_axi_wdata <= r_m_axi_wdata; 356 | r_write_cnt <= r_write_cnt; 357 | end 358 | end 359 | 360 | always@(posedge clk) begin 361 | if(rst) 362 | r_m_axi_wlast <= 0; 363 | else if(r_write_cnt == M_AXI_AWLEN - 1) 364 | r_m_axi_wlast <= 1; 365 | else 366 | r_m_axi_wlast <= 0; 367 | end 368 | 369 | /*--------------------- write response -----------------------*/ 370 | 371 | assign M_AXI_BREADY = 1'b1; 372 | 373 | 374 | endmodule 375 | 376 | 377 | 378 | 379 | -------------------------------------------------------------------------------- /project_AXI_DMA.srcs/sources_1/new/axi_slave.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/02/25 21:37:46 7 | // Design Name: 8 | // Module Name: axi_slave 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `default_nettype none 23 | module axi_slave# 24 | ( 25 | parameter ADDR_WD = 32, 26 | parameter DATA_WD = 32, 27 | localparam DATA_WD_BYTE = DATA_WD / 8, 28 | localparam STRB_WD = DATA_WD / 8 29 | ) 30 | ( 31 | input wire clk, 32 | input wire rst, 33 | 34 | // Read Address Channel 35 | input wire S_AXI_ARVALID, 36 | input wire [ADDR_WD-1 : 0] S_AXI_ARADDR, 37 | input wire [ADDR_WD-1:0] S_AXI_ARLEN, 38 | input wire [2:0] S_AXI_ARSIZE, 39 | input wire [1:0] S_AXI_ARBURST, 40 | output wire S_AXI_ARREADY, 41 | // Read Response Channel 42 | output wire S_AXI_RVALID, 43 | output wire [DATA_WD-1 : 0] S_AXI_RDATA, 44 | output wire [1:0] S_AXI_RRESP, 45 | output wire S_AXI_RLAST, 46 | output wire [STRB_WD-1 : 0] R_strobe, 47 | input wire S_AXI_RREADY, 48 | // Write Address Channel 49 | input wire S_AXI_AWVALID, 50 | input wire [ADDR_WD-1 : 0] S_AXI_AWADDR, 51 | input wire [ADDR_WD-1:0] S_AXI_AWLEN, 52 | input wire [2:0] S_AXI_AWSIZE, 53 | input wire [1:0] S_AXI_AWBURST, 54 | output wire S_AXI_AWREADY, 55 | // Write Data Channel 56 | input wire S_AXI_WVALID, 57 | input wire [DATA_WD-1 : 0] S_AXI_WDATA, 58 | input wire [STRB_WD-1 : 0] S_AXI_WSTRB, 59 | input wire S_AXI_WLAST, 60 | output wire S_AXI_WREADY, 61 | // Write Response Channel 62 | output wire S_AXI_BVALID, 63 | output wire [1:0] S_AXI_BRESP, 64 | input wire S_AXI_BREADY 65 | ); 66 | 67 | 68 | reg [ADDR_WD-1 : 0] r_awaddr ; 69 | reg r_awready ; 70 | reg r_wready ; 71 | reg r_arready ; 72 | reg [ADDR_WD-1 : 0] r_araddr ; 73 | reg [ADDR_WD-1:0] r_arlen ; 74 | reg [8 : 0] r_read_cnt ; 75 | reg [8 : 0] r_write_cnt ; 76 | reg r_rvalid ; 77 | reg [DATA_WD - 1:0] r_rdata ; 78 | reg r_bvalid ; 79 | reg r_w_active_1 ; 80 | reg [STRB_WD - 1:0] r_r_strobe ; 81 | reg [STRB_WD - 1:0] r_r_strobe_1 ; 82 | reg [7 : 0] r_trans_num ; 83 | reg [DATA_WD - 1:0] WSTRB_word ; 84 | //reg [DATA_WD - 1:0] r_w_strobe ; 85 | 86 | // reg [DATA_WD-1 : 0] r_ram [0 : 255] ; 87 | // reg [7:0] r_ram_addr ; 88 | // reg [DATA_WD-1 : 0] r_ram_write_data ; 89 | // reg [DATA_WD-1 : 0] r_ram_read_data ; 90 | // reg r_ram_rh_wl ; 91 | // reg r_ram_en ; 92 | 93 | reg [DATA_WD : 0] mem [0 : 2**12 - 1]; 94 | reg [ADDR_WD : 0] mem_addr ; 95 | reg [7 : 0] mem_write_data ; 96 | reg [7 : 0] mem_read_data ; 97 | reg mem_rh_wl ; 98 | reg mem_en ; 99 | reg [DATA_WD:0] r_w_strobe; 100 | 101 | wire w_aw_active ; 102 | wire w_w_active ; 103 | wire w_b_active ; 104 | wire w_ar_active ; 105 | wire w_r_active ; 106 | wire [ADDR_WD-3 : 0] w_araddr_word ; 107 | wire [ADDR_WD-3 : 0] w_awaddr_word ; 108 | wire [7:0] TRANS_PER_DATA ; 109 | 110 | assign w_aw_active = S_AXI_AWVALID & S_AXI_AWREADY ; 111 | assign w_w_active = S_AXI_WVALID & S_AXI_WREADY ; 112 | assign w_b_active = S_AXI_BVALID & S_AXI_BREADY ; 113 | assign w_ar_active = S_AXI_ARVALID & S_AXI_ARREADY ; 114 | assign w_r_active = S_AXI_RVALID & S_AXI_RREADY ; 115 | assign w_araddr_word = r_araddr/DATA_WD_BYTE ; 116 | assign w_awaddr_word = r_awaddr/DATA_WD_BYTE ; 117 | assign S_AXI_AWREADY = r_awready ; 118 | assign S_AXI_WREADY = r_wready ; 119 | assign S_AXI_ARREADY = r_arready ; 120 | 121 | assign R_strobe = r_r_strobe_1 ; 122 | assign S_AXI_RDATA = r_rdata ; 123 | assign S_AXI_RRESP = 'd0 ; //response OKAY 124 | assign S_AXI_RLAST = (r_read_cnt == r_arlen ) ? 125 | w_r_active : 1'b0 ; 126 | assign S_AXI_RVALID = r_rvalid ; 127 | assign S_AXI_BRESP = 'd0 ; 128 | assign S_AXI_BVALID = r_bvalid ; 129 | assign TRANS_PER_DATA = DATA_WD_BYTE/(2**(S_AXI_AWSIZE)) ; 130 | 131 | integer k; 132 | always@ * begin 133 | for(k = 0; k < 4; k = k + 1) begin 134 | r_w_strobe[k*8 +:8] = {8{S_AXI_WSTRB[k]}}; 135 | end 136 | end 137 | 138 | /********************** mem initialize ***************************/ 139 | integer i; 140 | always@(posedge clk) begin 141 | if(rst) begin 142 | for(i = 0; i < 2**12; i = i + 1) begin 143 | mem[i] <= i * 412; 144 | end 145 | end 146 | else begin 147 | for(i = 0; i < 2**12; i = i + 1) begin 148 | mem[i] <= mem[i]; 149 | end 150 | end 151 | end 152 | 153 | /**********************write address***************************/ 154 | always@(posedge clk) begin 155 | if(w_aw_active) 156 | r_awaddr <= S_AXI_AWADDR; 157 | else 158 | r_awaddr <= r_awaddr; 159 | end 160 | 161 | /*--------------------------write-------------------------------*/ 162 | 163 | always@(posedge clk) begin 164 | if(rst || S_AXI_WLAST) begin 165 | r_awready <= 'd1; 166 | r_write_cnt <= 0; 167 | end 168 | else if(w_w_active) begin 169 | r_awready <= 'd0; 170 | r_write_cnt <= r_write_cnt + 1; 171 | end 172 | else begin 173 | r_awready <= r_awready; 174 | r_write_cnt <= r_write_cnt; 175 | end 176 | end 177 | 178 | always@(posedge clk) begin 179 | if(w_aw_active) 180 | r_wready <= 'd1; 181 | else if(S_AXI_WLAST) 182 | r_wready <= 'd0; 183 | else 184 | r_wready <= r_wready; 185 | end 186 | // delay 1 cycle for store 187 | always@(posedge clk) begin 188 | if(rst || S_AXI_WLAST) 189 | r_w_active_1 <= 0; 190 | else 191 | r_w_active_1 <= w_w_active; 192 | end 193 | 194 | integer j; 195 | always@ * begin 196 | for(j = 0; j < STRB_WD; j = j + 1) begin 197 | WSTRB_word[j*8 +:8] = {8{S_AXI_WSTRB[j]}}; 198 | end 199 | end 200 | 201 | always@(posedge clk) begin 202 | case(S_AXI_AWBURST) 203 | 2'b0: begin //FIXED mode 204 | if(w_w_active || r_w_active_1) begin 205 | if(r_write_cnt % TRANS_PER_DATA == 0) 206 | mem[w_awaddr_word] <= 0 + (S_AXI_WDATA & WSTRB_word); 207 | else 208 | mem[w_awaddr_word] <= mem[w_awaddr_word] + (S_AXI_WDATA & WSTRB_word); 209 | end 210 | else 211 | mem[w_awaddr_word] <= mem[w_awaddr_word]; 212 | end 213 | 2'b1: begin //INCR mode 214 | if(w_w_active || r_w_active_1) begin 215 | if(TRANS_PER_DATA == 1) 216 | mem[w_awaddr_word + r_write_cnt - 1] <= S_AXI_WDATA & WSTRB_word; 217 | else if(r_write_cnt % TRANS_PER_DATA == 0) 218 | mem[w_awaddr_word + r_write_cnt/TRANS_PER_DATA - 1] <= 0; 219 | else 220 | mem[w_awaddr_word + r_write_cnt/TRANS_PER_DATA - 1] <= mem[w_awaddr_word + r_write_cnt/TRANS_PER_DATA - 1] + (S_AXI_WDATA & WSTRB_word); 221 | end 222 | else 223 | mem[w_awaddr_word + r_write_cnt/TRANS_PER_DATA - 1] <= mem[w_awaddr_word + r_write_cnt/TRANS_PER_DATA - 1]; 224 | end 225 | default: begin //WRAP mode 226 | if(r_w_active_1) 227 | mem[w_awaddr_word] <= S_AXI_WDATA & WSTRB_word; 228 | else 229 | mem[w_awaddr_word] <= mem[w_awaddr_word]; 230 | end 231 | endcase 232 | end 233 | 234 | 235 | /**********************read address***************************/ 236 | always@(posedge clk) begin 237 | if(rst || S_AXI_RLAST) 238 | r_arready <= 'd1; 239 | else if(w_ar_active) 240 | r_arready <= 'd0; 241 | else 242 | r_arready <= r_arready; 243 | end 244 | 245 | 246 | always@(posedge clk) begin 247 | if(w_ar_active) 248 | r_araddr <= S_AXI_ARADDR; 249 | else 250 | r_araddr <= r_araddr; 251 | end 252 | 253 | always@(posedge clk) begin 254 | if(w_ar_active) 255 | r_arlen <= S_AXI_ARLEN; 256 | else 257 | r_arlen <= r_arlen; 258 | end 259 | /********************** read ***************************/ 260 | //delay 1 cycle 261 | always@(posedge clk) begin 262 | r_r_strobe_1 <= r_r_strobe; 263 | end 264 | 265 | always@(posedge clk) begin 266 | if(rst || r_trans_num == TRANS_PER_DATA) 267 | r_trans_num <= 1; 268 | else if(w_r_active) 269 | r_trans_num <= r_trans_num + 1; 270 | else 271 | r_trans_num <= r_trans_num; 272 | end 273 | 274 | always@(posedge clk) begin 275 | // if(rst) 276 | // r_r_strobe <= 0 277 | // else if(w_r_active && r_trans_num == 0) 278 | // r_r_strobe <= 279 | // else 280 | if(rst || S_AXI_RLAST || w_ar_active) 281 | case(TRANS_PER_DATA) 282 | 2: r_r_strobe <= {{(STRB_WD/2){1'b0}},{(STRB_WD/2){1'b1}}}; 283 | 4: r_r_strobe <= {{(3*STRB_WD/4){1'b0}},{(STRB_WD/4){1'b1}}}; 284 | 8: r_r_strobe <= {{(7*STRB_WD/8){1'b0}},{(STRB_WD/8){1'b1}}}; 285 | 16: r_r_strobe <= {{(15*STRB_WD/16){1'b0}},{(STRB_WD/16){1'b1}}}; 286 | default: r_r_strobe <= {STRB_WD{1'b1}}; 287 | endcase 288 | else if(w_r_active) begin 289 | case(TRANS_PER_DATA) 290 | 2: begin 291 | case(r_trans_num) 292 | 0: r_r_strobe <= {{(STRB_WD/2){1'b0}},{(STRB_WD/2){1'b1}}}; 293 | TRANS_PER_DATA: r_r_strobe <= {{(STRB_WD/2){1'b0}},{(STRB_WD/2){1'b1}}}; 294 | default: r_r_strobe <= r_r_strobe << STRB_WD/2; 295 | endcase 296 | end 297 | 4: begin 298 | case(r_trans_num) 299 | 0: r_r_strobe <= {{(3*STRB_WD/4){1'b0}},{(STRB_WD/4){1'b1}}}; 300 | TRANS_PER_DATA: r_r_strobe <= {{(3*STRB_WD/4){1'b0}},{(STRB_WD/4){1'b1}}}; 301 | default: r_r_strobe <= r_r_strobe << STRB_WD/4; 302 | endcase 303 | end 304 | 8: begin 305 | case(r_trans_num) 306 | 0: r_r_strobe <= {{(7*STRB_WD/8){1'b0}},{(STRB_WD/8){1'b1}}}; 307 | TRANS_PER_DATA: r_r_strobe <= {{(7*STRB_WD/8){1'b0}},{(STRB_WD/8){1'b1}}}; 308 | default: r_r_strobe <= r_r_strobe << STRB_WD/8; 309 | endcase 310 | end 311 | 16: begin 312 | case(r_trans_num) 313 | 0: r_r_strobe <= {{(15*STRB_WD/16){1'b0}},{(STRB_WD/16){1'b1}}}; 314 | TRANS_PER_DATA: r_r_strobe <= {{(15*STRB_WD/16){1'b0}},{(STRB_WD/16){1'b1}}}; 315 | default: r_r_strobe <= r_r_strobe << STRB_WD/16; 316 | endcase 317 | end 318 | default: r_r_strobe <= {STRB_WD{1'b1}}; 319 | endcase 320 | end 321 | else 322 | r_r_strobe <= r_r_strobe; 323 | end 324 | 325 | always@(posedge clk) begin 326 | if(rst || S_AXI_RLAST) 327 | r_read_cnt <= 'd0; 328 | else if(w_r_active) 329 | r_read_cnt <= r_read_cnt + 1; 330 | else 331 | r_read_cnt <= r_read_cnt; 332 | end 333 | 334 | always@(posedge clk) begin 335 | case(S_AXI_ARBURST) 336 | 2'd0: begin //FIXED mode 337 | if(rst || S_AXI_RLAST) 338 | r_rdata <= 'd0; 339 | else if(w_r_active) 340 | r_rdata <= mem[w_araddr_word]; 341 | else 342 | r_rdata <= r_rdata; 343 | end 344 | 2'd1: begin //INCR mode 345 | if(rst || S_AXI_RLAST) 346 | r_rdata <= 'd0; 347 | else if(w_r_active) 348 | r_rdata <= mem[r_read_cnt/TRANS_PER_DATA + w_araddr_word]; 349 | else 350 | r_rdata <= r_rdata; 351 | end 352 | default: begin //WRAP mode 353 | if(rst || S_AXI_RLAST) 354 | r_rdata <= 'd0; 355 | else if(w_r_active) 356 | r_rdata <= mem[w_araddr_word]; 357 | else 358 | r_rdata <= r_rdata; 359 | end 360 | endcase 361 | end 362 | 363 | always@(posedge clk) begin 364 | if(rst || S_AXI_RLAST) 365 | r_rvalid <= 'd0; 366 | else if(w_ar_active) 367 | r_rvalid <= 'd1; 368 | else 369 | r_rvalid <= r_rvalid; 370 | end 371 | 372 | always@(posedge clk) begin 373 | if(S_AXI_WLAST) 374 | r_bvalid <= 'd1; 375 | else if(w_b_active) 376 | r_bvalid <= 'd0; 377 | else 378 | r_bvalid <= r_bvalid; 379 | end 380 | 381 | endmodule 382 | 383 | --------------------------------------------------------------------------------