├── py ├── images │ ├── cmac_license1.png │ ├── cmac_license2.png │ ├── intro_overlay.png │ ├── CMAC_Aldec_Setup_1.png │ └── CMAC_Aldec_Setup_2.png ├── cmac.py └── CMAC_Intro.ipynb ├── Makefile ├── ZCU111 └── vivado │ ├── SFP28_prj.tcl │ ├── Aldec_QSFP1_prj.tcl │ ├── Aldec_QSFP2_prj.tcl │ ├── constraints.xdc │ └── qsfp1_bd.tcl ├── LICENSE └── README.md /py/images/cmac_license1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JennySmith888/100GBE-PYNQ/HEAD/py/images/cmac_license1.png -------------------------------------------------------------------------------- /py/images/cmac_license2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JennySmith888/100GBE-PYNQ/HEAD/py/images/cmac_license2.png -------------------------------------------------------------------------------- /py/images/intro_overlay.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JennySmith888/100GBE-PYNQ/HEAD/py/images/intro_overlay.png -------------------------------------------------------------------------------- /py/images/CMAC_Aldec_Setup_1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JennySmith888/100GBE-PYNQ/HEAD/py/images/CMAC_Aldec_Setup_1.png -------------------------------------------------------------------------------- /py/images/CMAC_Aldec_Setup_2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JennySmith888/100GBE-PYNQ/HEAD/py/images/CMAC_Aldec_Setup_2.png -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | # Makefile 2 | 3 | vivado_dir := ZCU111/vivado 4 | board_test_dir := ZCU111 5 | 6 | all: board_test sfp28_prj qsfp1_prj qsfp2_prj 7 | 8 | board_test: 9 | cd $(board_test_dir); mkdir board_test 10 | 11 | sfp28_prj: 12 | cd $(vivado_dir); vivado -mode batch -nojou -nolog -source SFP28_prj.tcl 13 | cd $(vivado_dir); cp ./CMAC_SFP28/CMAC_SFP28.runs/impl_1/sfp28_wrapper.bit ../board_test/sfp28.bit 14 | cd $(vivado_dir); cp ./CMAC_SFP28/CMAC_SFP28.gen/sources_1/bd/sfp28/hw_handoff/sfp28.hwh ../board_test/ 15 | qsfp1_prj: 16 | cd $(vivado_dir); vivado -mode batch -nojou -nolog -source Aldec_QSFP1_prj.tcl 17 | cd $(vivado_dir); cp ./CMAC_Aldec_QSFP1/CMAC_Aldec_QSFP1.runs/impl_1/qsfp1_wrapper.bit ../board_test/qsfp1.bit 18 | cd $(vivado_dir); cp ./CMAC_Aldec_QSFP1/CMAC_Aldec_QSFP1.gen/sources_1/bd/qsfp1/hw_handoff/qsfp1.hwh ../board_test/ 19 | qsfp2_prj: 20 | cd $(vivado_dir); vivado -mode batch -nojou -nolog -source Aldec_QSFP2_prj.tcl 21 | cd $(vivado_dir); cp ./CMAC_Aldec_QSFP2/CMAC_Aldec_QSFP2.runs/impl_1/qsfp2_wrapper.bit ../board_test/qsfp2.bit 22 | cd $(vivado_dir); cp ./CMAC_Aldec_QSFP2/CMAC_Aldec_QSFP2.gen/sources_1/bd/qsfp2/hw_handoff/qsfp2.hwh ../board_test/ 23 | -------------------------------------------------------------------------------- /ZCU111/vivado/SFP28_prj.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2021 Xilinx, Inc 2 | # SPDX-License-Identifier: BSD-3-Clause 3 | 4 | # Set project origin 5 | set origin_dir "." 6 | 7 | # Set project name 8 | set _xil_proj_name_ "CMAC_SFP28" 9 | 10 | # Create project 11 | create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu28dr-ffvg1517-2-e 12 | 13 | # Set project properties 14 | set obj [current_project] 15 | set_property -name "board_part" -value "xilinx.com:zcu111:part0:1.2" -objects $obj 16 | 17 | # Build block design 18 | source ${origin_dir}/sfp28_bd.tcl 19 | 20 | # Add constraints 21 | update_compile_order -fileset sources_1 22 | add_files -fileset constrs_1 -norecurse ${origin_dir}/constraints.xdc 23 | 24 | # Generate HDL Wrapper 25 | make_wrapper -files [get_files ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/${design_name}/${design_name}.bd] -top 26 | add_files -norecurse ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/${design_name}/hdl/${design_name}_wrapper.v 27 | 28 | set_property top performance_test_sfp28_wrapper [current_fileset] 29 | update_compile_order -fileset sources_1 30 | 31 | #Uncomment below to run through bitstream generation 32 | update_compile_order -fileset sources_1 33 | launch_runs impl_1 -to_step write_bitstream -jobs 16 34 | wait_on_run impl_1 35 | 36 | -------------------------------------------------------------------------------- /ZCU111/vivado/Aldec_QSFP1_prj.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2021 Xilinx, Inc 2 | # SPDX-License-Identifier: BSD-3-Clause 3 | 4 | # Set project origin 5 | set origin_dir "." 6 | 7 | # Set project name 8 | set _xil_proj_name_ "CMAC_Aldec_QSFP1" 9 | 10 | # Create project 11 | create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu28dr-ffvg1517-2-e 12 | 13 | # Set project properties 14 | set obj [current_project] 15 | set_property -name "board_part" -value "xilinx.com:zcu111:part0:1.2" -objects $obj 16 | 17 | # Build block design 18 | source ${origin_dir}/qsfp1_bd.tcl 19 | 20 | # Add constraints 21 | update_compile_order -fileset sources_1 22 | add_files -fileset constrs_1 -norecurse ${origin_dir}/constraints.xdc 23 | 24 | # Generate HDL Wrapper 25 | make_wrapper -files [get_files ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/${design_name}/${design_name}.bd] -top 26 | add_files -norecurse ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/${design_name}/hdl/${design_name}_wrapper.v 27 | 28 | set_property top performance_test_sfp28_wrapper [current_fileset] 29 | update_compile_order -fileset sources_1 30 | 31 | #Uncomment below to run through bitstream generation 32 | update_compile_order -fileset sources_1 33 | launch_runs impl_1 -to_step write_bitstream -jobs 16 34 | wait_on_run impl_1 35 | 36 | -------------------------------------------------------------------------------- /ZCU111/vivado/Aldec_QSFP2_prj.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2021 Xilinx, Inc 2 | # SPDX-License-Identifier: BSD-3-Clause 3 | 4 | # Set project origin 5 | set origin_dir "." 6 | 7 | # Set project name 8 | set _xil_proj_name_ "CMAC_Aldec_QSFP2" 9 | 10 | # Create project 11 | create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu28dr-ffvg1517-2-e 12 | 13 | # Set project properties 14 | set obj [current_project] 15 | set_property -name "board_part" -value "xilinx.com:zcu111:part0:1.2" -objects $obj 16 | 17 | # Build block design 18 | source ${origin_dir}/qsfp2_bd.tcl 19 | 20 | # Add constraints 21 | update_compile_order -fileset sources_1 22 | add_files -fileset constrs_1 -norecurse ${origin_dir}/constraints.xdc 23 | 24 | # Generate HDL Wrapper 25 | make_wrapper -files [get_files ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/${design_name}/${design_name}.bd] -top 26 | add_files -norecurse ${origin_dir}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/${design_name}/hdl/${design_name}_wrapper.v 27 | 28 | set_property top performance_test_sfp28_wrapper [current_fileset] 29 | update_compile_order -fileset sources_1 30 | 31 | #Uncomment below to run through bitstream generation 32 | update_compile_order -fileset sources_1 33 | launch_runs impl_1 -to_step write_bitstream -jobs 16 34 | wait_on_run impl_1 35 | 36 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2021, Xilinx 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | * Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | * Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | * Neither the name of the copyright holder nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | -------------------------------------------------------------------------------- /ZCU111/vivado/constraints.xdc: -------------------------------------------------------------------------------- 1 | #set_property PACKAGE_PIN W34 [get_ports "diff_clock_rtl_clk_n"] ;# ALDEC GT CLK 2 | #set_property PACKAGE_PIN W33 [get_ports "diff_clock_rtl_clk_p"] ;# ALDEC GT CLK 3 | 4 | # change to local ZCU111 CLK 5 | set_property PACKAGE_PIN V32 [get_ports "diff_clock_rtl_clk_n"] ;# Bank 129 - MGTREFCLK1N_129 ZCU111 GT CLK 6 | set_property PACKAGE_PIN V31 [get_ports "diff_clock_rtl_clk_p"] ;# Bank 129 - MGTREFCLK1P_129 ZCU111 GT CLK 7 | 8 | set_property PACKAGE_PIN AP8 [get_ports "qsfp1_resetl"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_65 9 | set_property IOSTANDARD LVCMOS18 [get_ports "qsfp1_resetl"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_65 10 | set_property PACKAGE_PIN AJ12 [get_ports "qsfp1_modsell"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_65 11 | set_property IOSTANDARD LVCMOS18 [get_ports "qsfp1_modsell"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_65 12 | set_property PACKAGE_PIN AR9 [get_ports "qsfp1_intl"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_65 13 | set_property IOSTANDARD LVCMOS18 [get_ports "qsfp1_intl"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_65 14 | set_property PACKAGE_PIN AP9 [get_ports "qsfp1_modprsl"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65 15 | set_property IOSTANDARD LVCMOS18 [get_ports "qsfp1_modprsl"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65 16 | set_property PACKAGE_PIN AR8 [get_ports "qsfp1_lpmode"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65 17 | set_property IOSTANDARD LVCMOS18 [get_ports "qsfp1_lpmode"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65 18 | set_false_path -through [get_nets -hierarchical *qsfp1_intl_1*] 19 | set_false_path -through [get_nets -hierarchical *qsp1_modprsl_1*] 20 | 21 | # QSFP 2 22 | set_property PACKAGE_PIN AL7 [get_ports "qsfp2_resetl"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_65 23 | set_property IOSTANDARD LVCMOS18 [get_ports "qsfp2_resetl"] ;# Bank 65 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_65 24 | set_property PACKAGE_PIN AN12 [get_ports "qsfp2_modsell"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_65 25 | set_property IOSTANDARD LVCMOS18 [get_ports "qsfp2_modsell"] ;# Bank 65 VCCO - VADJ_FMC - IO_L21P_T3L_N4_AD8P_65 26 | set_property PACKAGE_PIN AM7 [get_ports "qsfp2_intl"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_65 27 | set_property IOSTANDARD LVCMOS18 [get_ports "qsfp2_intl"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14N_T2L_N3_GC_65 28 | set_property PACKAGE_PIN AM8 [get_ports "qsfp2_modprsl"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65 29 | set_property IOSTANDARD LVCMOS18 [get_ports "qsfp2_modprsl"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65 30 | set_property PACKAGE_PIN AM12 [get_ports "qsfp2_lpmode"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65 31 | set_property IOSTANDARD LVCMOS18 [get_ports "qsfp2_lpmode"] ;# Bank 65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65 32 | 33 | set_false_path -through [get_nets -hierarchical *qsfp2_intl_1*] 34 | set_false_path -through [get_nets -hierarchical *qsfp2_modprsl_1*] 35 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # 100GBE-PYNQ 2 | [Introduction](https://github.com/JennySmith888/100GBE-PYNQ#introduction) 3 | 4 | [Project Generation](https://github.com/JennySmith888/100GBE-PYNQ#project-generation) 5 | 6 | [Running the Project](https://github.com/JennySmith888/100GBE-PYNQ#running-the-project) 7 | 8 | ## Introduction 9 | This project provides an example design for working with the [UltraScale+ Integrated 100G Ethernet Subsystem (CMAC)](https://www.xilinx.com/products/intellectual-property/cmac_usplus.html) on the Xilinx [ZCU111](https://www.xilinx.com/support/documentation/boards_and_kits/zcu111/ug1271-zcu111-eval-bd.pdf). The 100G subsystem consists of a hardened IP also known as the CMAC. This hardened IP is available in Xilinx UltraScale+ devices. See the [Xilinx documentation](https://www.xilinx.com/products/intellectual-property/cmac_usplus.html) for more details on the IP core. 10 | 11 | 12 | 13 | The ZCU111 comes with four, SFP28 ports in a horizontal cage. Each of these is connected to one GTY transceiver and is capable of 25 GbE. The four together achieve 100 GbE. This project includes an example design targeting the SFP28 cage and also demonstrates 100 GbE with the newer QSFP port. The QSFP connector similarly accepts four GTY transceivers each running 25 GbE; however, they are all connected in the same connector which allows QSFP to provide 100 GbE in a smaller form factor. The Aldec [QSFP to FMC daughter card](https://www.aldec.com/en/products/emulation/daughter_cards/fmc_daughter/fmc_qsfp) is used to convert the ZCU111 FMC+ connector to two QSFP ports. This project contains an example design for each QSFP. The only difference in the Overlay designs is the CMAC and transceivers used. 14 | ## Aldec Daughter Card Connected to ZCU111 FMC+ to Create QSFP 15 | ![Alt text](./py/images/CMAC_Aldec_Setup_1.png?raw=true "Aldec Card Plugged into ZCU111 FMC+ Connector") 16 | 17 | The CMAC is configured in CAUI-4 mode meaning it achieves 100 GbE via 4, 25 Gb/sec lanes. The CMAC register map is exposed in PYNQ and a [driver](https://github.com/JennySmith888/100GBE-PYNQ/blob/main/py/cmac.py) exists to simplify core operation. The design also features 4 FS "generic" 25 GbE SFP28 passive loopback modules (Product: 109377) and 2 Amphenol 100 GbE QSFP passive loopback modules (Product: SF-100GLB0W00-0DB). If you don't have loopback modules, you can still experiment with the CMAC by enabling "Near-End PMA Loopback" in the notebook which routes the transmit path to the receive path internally as opposed to sending them off package via the transceivers. Functionality can also be probed in Vivado Hardware Manager by ILAs which exist on the CMAC transmit and receive paths. 18 | 19 | ## Passive Loopback Modules 20 | ![Alt text](./py/images/CMAC_Aldec_Setup_2.png?raw=true "Aldec Card Plugged into ZCU111 FMC+ Connector") 21 | 22 | ## Project Generation 23 | The project was built using Vivado 2020.2. Before you can regenerate the project, you must follow the steps below to obtain a free, click-through license for the CMAC IP. If you already have a CMAC license in your Vivado license manager, skip to [Building the Project](https://github.com/JennySmith888/100GBE-PYNQ#building-the-project). 24 | 25 | ### CMAC License 26 | 1. Head to the [CMAC webpage](https://www.xilinx.com/products/intellectual-property/cmac_usplus.html) and click "Get License". 27 | 2. Enter your information and click "Next" to get to the screen shown below. Check the box for the UltraScale+ Integrated 100G Ethernet No Charge License. ![Alt text](./py/images/cmac_license1.png?raw=true "Aldec Card Plugged into ZCU111 FMC+ Connector") 28 | 3. Enter the information specific to your license, for example: the host ID. Refer to your main Vivado license if needed. ![Alt text](./py/images/cmac_license2.png?raw=true "Aldec Card Plugged into ZCU111 FMC+ Connector") 29 | 4. Download the new CMAC license from your email. **Rename the file to avoid overwriting your main Vivado license in the next step**, example: `cmac.lic`. 30 | 5. Use the Vivado license manager to add the new CMAC license the same way you add the main Vivado license. See [licensing support](https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0013-vivado-installation-and-licensing-hub.html) for more details. 31 | 32 | ### Building the Project 33 | 34 | 35 | 36 | 1. Source the Vivado 2020.2 path `/2020.2/settings64.sh` 37 | 2. Clone the repo `git clone https://github.com/JennySmith888/100GBE-PYNQ.git` 38 | 3. Move into the repo folder `cd 100GBE-PYNQ` 39 | 4. Run `make` 40 | 41 | ## Running the Project 42 | To test the project, transfer the contents of `/py` and the newly populated `/ZCU111/board_test` to a ZCU111 running a [PYNQ v2.6 image](https://github.com/Xilinx/PYNQ/releases). Place them in the same folder and run the `CMAC_Intro.ipynb` notebook. If you don't have such a board available, you can still view the notebook with the executed cells [here](https://github.com/JennySmith888/100GBE-PYNQ/blob/main/py/CMAC_Intro.ipynb). 43 | 44 | -------------------------------------------------------------------------------- /py/cmac.py: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2021 Xilinx, Inc 2 | # SPDX-License-Identifier: BSD-3-Clause 3 | 4 | from pynq import DefaultIP 5 | import time 6 | 7 | class CMAC(DefaultIP): 8 | """Driver for the UltraScale+ Integrated 100 Gigabit Ethernet Subsystem. 9 | """ 10 | def __init__(self, description): 11 | cmac_registers = {'gt_reset_reg': {'address_offset': 0, 'access': 'read-write;', 'size': 32, 'host_size': 4, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 0, 'memory': 'dc_2'}, 'reset_reg': {'address_offset': 4, 'access': 'read-write;', 'size': 32, 'host_size': 4, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 1}, 'conf_tx': {'address_offset': 12, 'access': 'read-write;', 'size': 32, 'host_size': 4, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 3}, 'conf_rx': {'address_offset': 20, 'access': 'read-write;', 'size': 32, 'host_size': 4, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 4}, 'core_mode': {'address_offset': 32, 'access': 'read-write;', 'size': 32, 'host_size': 4, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 5}, 'version': {'address_offset': 36, 'access': 'read-write;', 'size': 32, 'host_size': 4, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 6}, 'gt_loopback': {'address_offset': 144, 'access': 'read-write;', 'size': 32, 'host_size': 4, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 7}, 'stat_tx_status': {'address_offset': 512, 'access': 'read-write;', 'size': 32, 'host_size': 4, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 8}, 'stat_rx_status': {'address_offset': 516, 'access': 'read-write;', 'size': 32, 'host_size': 4, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 9}, 'stat_status': {'address_offset': 520, 'access': 'read-write;', 'size': 32, 'host_size': 4, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 10}, 'stat_rx_block_lock': {'address_offset': 524, 'access': 'read-write;', 'size': 32, 'host_size': 4, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 11}, 'stat_rx_lane_sync': {'address_offset': 528, 'access': 'read-write;', 'size': 32, 'host_size': 4, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 12}, 'stat_rx_lane_sync_err': {'address_offset': 532, 'access': 'read-write;', 'size': 32, 'host_size': 4, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 13}, 'stat_cycle_count': {'address_offset': 696, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 17}, 'stat_tx_total_packets': {'address_offset': 1280, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 18}, 'stat_tx_total_good_packets': {'address_offset': 1288, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 19}, 'stat_tx_total_bytes': {'address_offset': 1296, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 20}, 'stat_tx_total_good_bytes': {'address_offset': 1304, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 21}, 'stat_tx_total_packets_64B': {'address_offset': 1312, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 22}, 'stat_tx_total_packets_65_127B': {'address_offset': 1320, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 23}, 'stat_tx_total_packets_128_255B': {'address_offset': 1328, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 24}, 'stat_tx_total_packets_256_511B': {'address_offset': 1336, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 25}, 'stat_tx_total_packets_512_1023B': {'address_offset': 1344, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 26}, 'stat_tx_total_packets_1024_1518B': {'address_offset': 1352, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 27}, 'stat_tx_total_packets_1519_1522B': {'address_offset': 1360, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 28}, 'stat_tx_total_packets_1523_1548B': {'address_offset': 1368, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 29}, 'stat_tx_total_packets_1549_2047B': {'address_offset': 1376, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 30}, 'stat_tx_total_packets_2048_4095B': {'address_offset': 1384, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 31}, 'stat_tx_total_packets_4096_8191B': {'address_offset': 1392, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 32}, 'stat_tx_total_packets_8192_9215B': {'address_offset': 1400, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 33}, 'stat_tx_total_packets_large': {'address_offset': 1408, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 34}, 'stat_tx_total_packets_small': {'address_offset': 1416, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 35}, 'stat_tx_total_bad_fcs': {'address_offset': 1464, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 36}, 'stat_tx_pause': {'address_offset': 1520, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 37}, 'stat_tx_user_pause': {'address_offset': 1528, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 38}, 'stat_rx_total_packets': {'address_offset': 1544, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 39}, 'stat_rx_total_good_packets': {'address_offset': 1552, 'access': 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'type': 'uint', 'id': 56}, 'stat_rx_total_packets_undersize': {'address_offset': 1688, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 57}, 'stat_rx_total_packets_fragmented': {'address_offset': 1696, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 58}, 'stat_rx_total_packets_oversize': {'address_offset': 1704, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 59}, 'stat_rx_total_packets_toolong': {'address_offset': 1712, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 60}, 'stat_rx_total_packets_jabber': {'address_offset': 1720, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 61}, 'stat_rx_total_bad_fcs': {'address_offset': 1728, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 62}, 'stat_rx_packets_bad_fcs': {'address_offset': 1736, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 63}, 'stat_rx_stomped_fcs': {'address_offset': 1744, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 64}, 'stat_rx_pause': {'address_offset': 1784, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 65}, 'stat_rx_user_pause': {'address_offset': 1792, 'access': 'read-write;', 'size': 64, 'host_size': 8, 'description': 'OpenCL Argument Register', 'type': 'uint', 'id': 66}} 12 | description['registers']=cmac_registers 13 | super().__init__(description=description) 14 | 15 | bindto = ['xilinx.com:ip:cmac_usplus:3.1'] 16 | 17 | def start(self): 18 | """Run core bring-up sequence. 19 | 20 | """ 21 | self.register_map.conf_rx = 1 22 | self.register_map.conf_tx = 0x10 23 | for _ in range(5): 24 | time.sleep(0.1) 25 | if self.register_map.stat_rx_status[1]: 26 | self.register_map.conf_tx = 1 27 | return 28 | raise RuntimeError('Receive channel not aligned') 29 | 30 | @property 31 | def internal_loopback(self): 32 | """True if CMAC near-end PMA loopback is enabled. 33 | """ 34 | return self.register_map.gt_loopback 35 | 36 | @internal_loopback.setter 37 | def internal_loopback(self, mode): 38 | self.register_map.gt_loopback = int(bool(mode)) 39 | 40 | def reset(self, tx=0, rx=0, gt=1): 41 | """Reset transmit path, receive path, or gigabit transceivers (full core). 42 | 43 | Parameters 44 | ---------- 45 | tx: bool 46 | Reset transmit path. 47 | rx: bool 48 | Reset receive path. 49 | gt: bool 50 | Reset GTs. 51 | 52 | """ 53 | if tx: 54 | self.register_map.reset_reg[30] = 1 55 | self.register_map.reset_reg[30] = 0 56 | if rx: 57 | self.register_map.reset_reg[31] = 1 58 | self.register_map.reset_reg[31] = 0 59 | if gt: 60 | self.register_map.gt_reset_reg[0] = 1 61 | return 62 | 63 | def copyStats(self) -> None: 64 | """Triggers a snapshot of CMAC Statistics 65 | Triggers a snapshot of all the Statistics counters into their 66 | readable register. The bit self-clears. 67 | """ 68 | self.write(0x02b0,1) 69 | 70 | def getStats(self, update_reg:bool=True) -> dict: 71 | """Return a dictionary with the CMAC stats 72 | Parameters 73 | ---------- 74 | debug: bool 75 | if enabled, the CMAC registers are copied from internal counters 76 | Returns 77 | ------- 78 | A dictionary with the CMAC statistics 79 | """ 80 | if update_reg: 81 | self.copyStats() 82 | 83 | rmap = self.register_map 84 | stats_dict = dict() 85 | stats_dict['tx'] = dict() 86 | stats_dict['rx'] = dict() 87 | stats_dict['cycle_count'] = int(rmap.stat_cycle_count) 88 | # Tx 89 | stats_dict['tx'] = { 90 | "packets": int(rmap.stat_tx_total_packets), 91 | "good_packets": int(rmap.stat_tx_total_good_packets), 92 | "bytes": int(rmap.stat_tx_total_bytes), 93 | "good_bytes": int(rmap.stat_tx_total_good_bytes), 94 | "packets_large": int(rmap.stat_tx_total_packets_large), 95 | "packets_small": int(rmap.stat_tx_total_packets_small), 96 | "bad_fcs": int(rmap.stat_tx_total_bad_fcs), 97 | "pause": int(rmap.stat_tx_pause), 98 | "user_pause": int(rmap.stat_tx_user_pause), 99 | } 100 | 101 | stats_dict['rx'] = { 102 | "packets": int(rmap.stat_rx_total_packets), 103 | "good_packets": int(rmap.stat_rx_total_good_packets), 104 | "bytes": int(rmap.stat_rx_total_bytes), 105 | "good_bytes": int(rmap.stat_rx_total_good_bytes), 106 | "packets_large": int(rmap.stat_rx_total_packets_large), 107 | "packets_small": int(rmap.stat_rx_total_packets_small), 108 | "packets_undersize": int(rmap.stat_rx_total_packets_undersize), 109 | "packets_fragmented": int(rmap.stat_rx_total_packets_fragmented), 110 | "packets_oversize": int(rmap.stat_rx_total_packets_oversize), 111 | "packets_toolong": int(rmap.stat_rx_total_packets_toolong), 112 | "packets_jabber": int(rmap.stat_rx_total_packets_jabber), 113 | "bad_fcs": int(rmap.stat_rx_total_bad_fcs), 114 | "packets_bad_fcs": int(rmap.stat_rx_packets_bad_fcs), 115 | "stomped_fcs": int(rmap.stat_rx_stomped_fcs), 116 | "pause": int(rmap.stat_rx_pause), 117 | "user_pause": int(rmap.stat_rx_user_pause), 118 | } 119 | return stats_dict 120 | -------------------------------------------------------------------------------- /py/CMAC_Intro.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "markdown", 5 | "metadata": {}, 6 | "source": [ 7 | "# Introduction" 8 | ] 9 | }, 10 | { 11 | "cell_type": "markdown", 12 | "metadata": {}, 13 | "source": [ 14 | "This notebook provides an example demonstrating how to work with Xilinx 100 GbE subsystem. The 100 GbE subsystem consists of a harded IP also known as the CMAC. This hardened IP is available in Xilinx UltraScale+ devices. See the [Xilinx documentation](https://www.xilinx.com/products/intellectual-property/cmac_usplus.html) for more details on the IP core. " 15 | ] 16 | }, 17 | { 18 | "cell_type": "markdown", 19 | "metadata": {}, 20 | "source": [ 21 | "# Overlay Block Design" 22 | ] 23 | }, 24 | { 25 | "cell_type": "markdown", 26 | "metadata": {}, 27 | "source": [ 28 | "![alt text](images/intro_overlay.png \"Aldec Daughter Card Plugged into ZCU111 FMC+ Connector\")" 29 | ] 30 | }, 31 | { 32 | "cell_type": "markdown", 33 | "metadata": {}, 34 | "source": [ 35 | "# Hardware Setup" 36 | ] 37 | }, 38 | { 39 | "cell_type": "markdown", 40 | "metadata": {}, 41 | "source": [ 42 | "The ZCU111 comes with four, SFP28 ports in a horizontal cage. Each of these is connected to one GTY transceiver and is capable of 25GbE. The four together acheive 100GbE. This design also demonstrates how to instead route the CMAC out of the onboard FMC+ connector and through an adapter board to one of two QSFP connectors. The QSFP connector similarly accepts four GTY transceivers each running 25GbE; however, they are all connected in the same connector. QSFP provides 100GbE in a smaller form factor." 43 | ] 44 | }, 45 | { 46 | "cell_type": "markdown", 47 | "metadata": {}, 48 | "source": [ 49 | "This design uses the [Aldec FMC to QSPF daughter card](https://www.aldec.com/en/products/emulation/daughter_cards/fmc_daughter/fmc_qsfp) plugged into the FMC+ connector on the [ZCU111](https://www.xilinx.com/products/boards-and-kits/zcu111.html)." 50 | ] 51 | }, 52 | { 53 | "cell_type": "markdown", 54 | "metadata": {}, 55 | "source": [ 56 | "![alt text](images/CMAC_Aldec_Setup_1.png \"Aldec Daughter Card Plugged into ZCU111 FMC+ Connector\")" 57 | ] 58 | }, 59 | { 60 | "cell_type": "markdown", 61 | "metadata": {}, 62 | "source": [ 63 | "The design also features 4 FS \"generic\" 25GbE SFP28 passive loopback modules (Product: 109377) and 2 Amphelol 100GbE QSFP passive loopback modules (Product: SF-100GLB0W00-0DB)." 64 | ] 65 | }, 66 | { 67 | "cell_type": "markdown", 68 | "metadata": {}, 69 | "source": [ 70 | "![alt text](images/CMAC_Aldec_Setup_2.png \"Aldec Daughter Card Plugged into ZCU111 FMC+ Connector\")" 71 | ] 72 | }, 73 | { 74 | "cell_type": "markdown", 75 | "metadata": {}, 76 | "source": [ 77 | "# Imports" 78 | ] 79 | }, 80 | { 81 | "cell_type": "code", 82 | "execution_count": 1, 83 | "metadata": {}, 84 | "outputs": [ 85 | { 86 | "data": { 87 | "application/javascript": [ 88 | "\n", 89 | "try {\n", 90 | "require(['notebook/js/codecell'], function(codecell) {\n", 91 | " codecell.CodeCell.options_default.highlight_modes[\n", 92 | " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", 93 | " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", 94 | " Jupyter.notebook.get_cells().map(function(cell){\n", 95 | " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", 96 | " });\n", 97 | "});\n", 98 | "} catch (e) {};\n" 99 | ] 100 | }, 101 | "metadata": {}, 102 | "output_type": "display_data" 103 | } 104 | ], 105 | "source": [ 106 | "import pynq\n", 107 | "import numpy as np\n", 108 | "from cmac import CMAC" 109 | ] 110 | }, 111 | { 112 | "cell_type": "markdown", 113 | "metadata": {}, 114 | "source": [ 115 | "# Download Overlay, Program FPGA, Initialize IP Cores" 116 | ] 117 | }, 118 | { 119 | "cell_type": "code", 120 | "execution_count": 2, 121 | "metadata": {}, 122 | "outputs": [], 123 | "source": [ 124 | "# Download Overlay\n", 125 | "ol = pynq.Overlay('sfp28.bit')" 126 | ] 127 | }, 128 | { 129 | "cell_type": "code", 130 | "execution_count": 3, 131 | "metadata": {}, 132 | "outputs": [], 133 | "source": [ 134 | "# Bind Drivers\n", 135 | "dma = ol.axi_dma_0\n", 136 | "cmac = ol.cmac_usplus_0" 137 | ] 138 | }, 139 | { 140 | "cell_type": "markdown", 141 | "metadata": {}, 142 | "source": [ 143 | "If you don't have loopback modules, you can still experiment with the CMAC by enabling \"Near-End PMA Loopback\" in the cell below which routes the transmit path to the receive path internally as opposed to sending them off package via the transceivers." 144 | ] 145 | }, 146 | { 147 | "cell_type": "code", 148 | "execution_count": 4, 149 | "metadata": {}, 150 | "outputs": [], 151 | "source": [ 152 | "# Put CMAC in internal Loopback Mode\n", 153 | "cmac.internal_loopback = 0" 154 | ] 155 | }, 156 | { 157 | "cell_type": "code", 158 | "execution_count": 5, 159 | "metadata": {}, 160 | "outputs": [], 161 | "source": [ 162 | "# Bring up the CMAC Core\n", 163 | "cmac.start()" 164 | ] 165 | }, 166 | { 167 | "cell_type": "markdown", 168 | "metadata": {}, 169 | "source": [ 170 | "# Test Functionality" 171 | ] 172 | }, 173 | { 174 | "cell_type": "markdown", 175 | "metadata": {}, 176 | "source": [ 177 | "In this overlay, we are using a DMA IP to transfer data to and from the processing system. The DMA is configured in packet mode so it supplies the necessary tlast signal for the CMAC core. The CMAC core supports packet sizes from 64 to 9,000 bytes. To illustrate data transfer, we will encode a random string as a list of bytes and store the result in a numpy array. We then allocate input and output dma buffers with size equal to the numpy array size (in this case 472 bytes)." 178 | ] 179 | }, 180 | { 181 | "cell_type": "code", 182 | "execution_count": 6, 183 | "metadata": {}, 184 | "outputs": [], 185 | "source": [ 186 | "# Random Data\n", 187 | "raw_str = ' /$$$$$$$ /$$ /$$ /$$ /$$ /$$$$$$ \\n| $$__ $$| $$ /$$/| $$$ | $$ /$$__ $$\\n| $$ \\\\ $$ \\\\ $$ /$$/ | $$$$| $$| $$ \\\\ $$\\n| $$$$$$$/ \\\\ $$$$/ | $$ $$ $$| $$ | $$\\n| $$____/ \\\\ $$/ | $$ $$$$| $$ | $$\\n| $$ | $$ | $$\\\\ $$$| $$/$$ $$\\n| $$ | $$ | $$ \\\\ $$| $$$$$$/\\n|__/ |__/ |__/ \\\\__/ \\\\____ $$$\\n \\\\__/\\n\\n \\n '" 188 | ] 189 | }, 190 | { 191 | "cell_type": "code", 192 | "execution_count": 7, 193 | "metadata": {}, 194 | "outputs": [], 195 | "source": [ 196 | "# Encode string as array of 472 bytes using default UTF-8 encoding\n", 197 | "packets_in = np.array(list(raw_str.encode()))" 198 | ] 199 | }, 200 | { 201 | "cell_type": "code", 202 | "execution_count": 8, 203 | "metadata": {}, 204 | "outputs": [], 205 | "source": [ 206 | "# Allocate input and output buffers for transfer\n", 207 | "dma_buf_in = pynq.allocate(packets_in.shape[0])\n", 208 | "dma_buf_out = pynq.allocate(packets_in.shape[0])" 209 | ] 210 | }, 211 | { 212 | "cell_type": "code", 213 | "execution_count": 9, 214 | "metadata": {}, 215 | "outputs": [], 216 | "source": [ 217 | "# Load data into input buffer\n", 218 | "dma_buf_in[:]=packets_in" 219 | ] 220 | }, 221 | { 222 | "cell_type": "markdown", 223 | "metadata": {}, 224 | "source": [ 225 | "### DMA Transfer" 226 | ] 227 | }, 228 | { 229 | "cell_type": "code", 230 | "execution_count": 10, 231 | "metadata": {}, 232 | "outputs": [], 233 | "source": [ 234 | "dma.sendchannel.transfer(dma_buf_in)" 235 | ] 236 | }, 237 | { 238 | "cell_type": "code", 239 | "execution_count": 11, 240 | "metadata": {}, 241 | "outputs": [], 242 | "source": [ 243 | "dma.recvchannel.transfer(dma_buf_out)" 244 | ] 245 | }, 246 | { 247 | "cell_type": "code", 248 | "execution_count": 12, 249 | "metadata": {}, 250 | "outputs": [], 251 | "source": [ 252 | "dma.sendchannel.wait()" 253 | ] 254 | }, 255 | { 256 | "cell_type": "code", 257 | "execution_count": 13, 258 | "metadata": {}, 259 | "outputs": [], 260 | "source": [ 261 | "dma.recvchannel.wait()" 262 | ] 263 | }, 264 | { 265 | "cell_type": "markdown", 266 | "metadata": {}, 267 | "source": [ 268 | "### Verify" 269 | ] 270 | }, 271 | { 272 | "cell_type": "code", 273 | "execution_count": 14, 274 | "metadata": {}, 275 | "outputs": [], 276 | "source": [ 277 | "# Decode output data\n", 278 | "packets_out = bytes(dma_buf_out)" 279 | ] 280 | }, 281 | { 282 | "cell_type": "code", 283 | "execution_count": 15, 284 | "metadata": {}, 285 | "outputs": [ 286 | { 287 | "name": "stdout", 288 | "output_type": "stream", 289 | "text": [ 290 | " \u0000\u0000\u0000/\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000/\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000/\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000/\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000/\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000/\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000\n", 291 | "\u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000_\u0000\u0000\u0000_\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000/\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000/\u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000/\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000_\u0000\u0000\u0000_\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000\n", 292 | "\u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000\\\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000\\\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000/\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000/\u0000\u0000\u0000 \u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000\\\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000\n", 293 | "\u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000/\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000\\\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000/\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000\n", 294 | "\u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000_\u0000\u0000\u0000_\u0000\u0000\u0000_\u0000\u0000\u0000_\u0000\u0000\u0000/\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000\\\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000/\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000\n", 295 | "\u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000\\\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000/\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000\n", 296 | "\u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000 \u0000\u0000\u0000\\\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000|\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000/\u0000\u0000\u0000\n", 297 | "\u0000\u0000\u0000|\u0000\u0000\u0000_\u0000\u0000\u0000_\u0000\u0000\u0000/\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000|\u0000\u0000\u0000_\u0000\u0000\u0000_\u0000\u0000\u0000/\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000|\u0000\u0000\u0000_\u0000\u0000\u0000_\u0000\u0000\u0000/\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000\\\u0000\u0000\u0000_\u0000\u0000\u0000_\u0000\u0000\u0000/\u0000\u0000\u0000 \u0000\u0000\u0000\\\u0000\u0000\u0000_\u0000\u0000\u0000_\u0000\u0000\u0000_\u0000\u0000\u0000_\u0000\u0000\u0000 \u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000$\u0000\u0000\u0000\n", 298 | "\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000\\\u0000\u0000\u0000_\u0000\u0000\u0000_\u0000\u0000\u0000/\u0000\u0000\u0000\n", 299 | "\u0000\u0000\u0000\n", 300 | "\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000\n", 301 | "\u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000 \u0000\u0000\u0000\n" 302 | ] 303 | } 304 | ], 305 | "source": [ 306 | "print(packets_out.decode())" 307 | ] 308 | }, 309 | { 310 | "cell_type": "code", 311 | "execution_count": 16, 312 | "metadata": {}, 313 | "outputs": [ 314 | { 315 | "data": { 316 | "text/plain": [ 317 | "True" 318 | ] 319 | }, 320 | "execution_count": 16, 321 | "metadata": {}, 322 | "output_type": "execute_result" 323 | } 324 | ], 325 | "source": [ 326 | "# Another way to verify core functionality\n", 327 | "np.array_equal(dma_buf_in,dma_buf_out)" 328 | ] 329 | }, 330 | { 331 | "cell_type": "markdown", 332 | "metadata": {}, 333 | "source": [ 334 | "Lastly, the CMAC has internal registers which can report some basic statistics. Optionally run the four DMA transfer cells multiple times to get statistics on multiple packets. Note the registers automatically self-clear after reporting. Run `cmac.getStats(False)` instead to prevent them from clearing." 335 | ] 336 | }, 337 | { 338 | "cell_type": "code", 339 | "execution_count": 17, 340 | "metadata": {}, 341 | "outputs": [ 342 | { 343 | "data": { 344 | "text/plain": [ 345 | "{'cycle_count': 2816748107,\n", 346 | " 'rx': {'bad_fcs': 0,\n", 347 | " 'bytes': 1892,\n", 348 | " 'good_bytes': 1892,\n", 349 | " 'good_packets': 1,\n", 350 | " 'packets': 1,\n", 351 | " 'packets_bad_fcs': 0,\n", 352 | " 'packets_fragmented': 0,\n", 353 | " 'packets_jabber': 0,\n", 354 | " 'packets_large': 0,\n", 355 | " 'packets_oversize': 0,\n", 356 | " 'packets_small': 0,\n", 357 | " 'packets_toolong': 0,\n", 358 | " 'packets_undersize': 0,\n", 359 | " 'pause': 0,\n", 360 | " 'stomped_fcs': 0,\n", 361 | " 'user_pause': 0},\n", 362 | " 'tx': {'bad_fcs': 0,\n", 363 | " 'bytes': 1892,\n", 364 | " 'good_bytes': 1892,\n", 365 | " 'good_packets': 1,\n", 366 | " 'packets': 1,\n", 367 | " 'packets_large': 0,\n", 368 | " 'packets_small': 0,\n", 369 | " 'pause': 0,\n", 370 | " 'user_pause': 0}}" 371 | ] 372 | }, 373 | "execution_count": 17, 374 | "metadata": {}, 375 | "output_type": "execute_result" 376 | } 377 | ], 378 | "source": [ 379 | "cmac.getStats()" 380 | ] 381 | }, 382 | { 383 | "cell_type": "markdown", 384 | "metadata": {}, 385 | "source": [ 386 | "----\n", 387 | "----\n", 388 | "\n", 389 | "Copyright (C) 2021 Xilinx, Inc\n", 390 | "\n", 391 | "SPDX-License-Identifier: BSD-3-Clause" 392 | ] 393 | } 394 | ], 395 | "metadata": { 396 | "kernelspec": { 397 | "display_name": "Python 3", 398 | "language": "python", 399 | "name": "python3" 400 | }, 401 | "language_info": { 402 | "codemirror_mode": { 403 | "name": "ipython", 404 | "version": 3 405 | }, 406 | "file_extension": ".py", 407 | "mimetype": "text/x-python", 408 | "name": "python", 409 | "nbconvert_exporter": "python", 410 | "pygments_lexer": "ipython3", 411 | "version": "3.8.3" 412 | } 413 | }, 414 | "nbformat": 4, 415 | "nbformat_minor": 4 416 | } 417 | -------------------------------------------------------------------------------- /ZCU111/vivado/qsfp1_bd.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2021 Xilinx, Inc 2 | # SPDX-License-Identifier: BSD-3-Clause 3 | 4 | ################################################################ 5 | # This is a generated script based on design: qsfp1 6 | # 7 | # Though there are limitations about the generated script, 8 | # the main purpose of this utility is to make learning 9 | # IP Integrator Tcl commands easier. 10 | ################################################################ 11 | 12 | namespace eval _tcl { 13 | proc get_script_folder {} { 14 | set script_path [file normalize [info script]] 15 | set script_folder [file dirname $script_path] 16 | return $script_folder 17 | } 18 | } 19 | variable script_folder 20 | set script_folder [_tcl::get_script_folder] 21 | 22 | ################################################################ 23 | # Check if script is running in correct Vivado version. 24 | ################################################################ 25 | set scripts_vivado_version 2020.2 26 | set current_vivado_version [version -short] 27 | 28 | if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { 29 | puts "" 30 | catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} 31 | 32 | return 1 33 | } 34 | 35 | ################################################################ 36 | # START 37 | ################################################################ 38 | 39 | # To test this script, run the following commands from Vivado Tcl console: 40 | # source qsfp1_script.tcl 41 | 42 | # If there is no project opened, this script will create a 43 | # project, but make sure you do not have an existing project 44 | # <./myproj/project_1.xpr> in the current working folder. 45 | 46 | set list_projs [get_projects -quiet] 47 | if { $list_projs eq "" } { 48 | create_project project_1 myproj -part xczu28dr-ffvg1517-2-e 49 | set_property BOARD_PART xilinx.com:zcu111:part0:1.2 [current_project] 50 | } 51 | 52 | 53 | # CHANGE DESIGN NAME HERE 54 | variable design_name 55 | set design_name qsfp1 56 | 57 | # If you do not already have an existing IP Integrator design open, 58 | # you can create a design using the following command: 59 | # create_bd_design $design_name 60 | 61 | # Creating design if needed 62 | set errMsg "" 63 | set nRet 0 64 | 65 | set cur_design [current_bd_design -quiet] 66 | set list_cells [get_bd_cells -quiet] 67 | 68 | if { ${design_name} eq "" } { 69 | # USE CASES: 70 | # 1) Design_name not set 71 | 72 | set errMsg "Please set the variable to a non-empty value." 73 | set nRet 1 74 | 75 | } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { 76 | # USE CASES: 77 | # 2): Current design opened AND is empty AND names same. 78 | # 3): Current design opened AND is empty AND names diff; design_name NOT in project. 79 | # 4): Current design opened AND is empty AND names diff; design_name exists in project. 80 | 81 | if { $cur_design ne $design_name } { 82 | common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." 83 | set design_name [get_property NAME $cur_design] 84 | } 85 | common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." 86 | 87 | } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { 88 | # USE CASES: 89 | # 5) Current design opened AND has components AND same names. 90 | 91 | set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." 92 | set nRet 1 93 | } elseif { [get_files -quiet ${design_name}.bd] ne "" } { 94 | # USE CASES: 95 | # 6) Current opened design, has components, but diff names, design_name exists in project. 96 | # 7) No opened design, design_name exists in project. 97 | 98 | set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." 99 | set nRet 2 100 | 101 | } else { 102 | # USE CASES: 103 | # 8) No opened design, design_name not in project. 104 | # 9) Current opened design, has components, but diff names, design_name not in project. 105 | 106 | common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." 107 | 108 | create_bd_design $design_name 109 | 110 | common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." 111 | current_bd_design $design_name 112 | 113 | } 114 | 115 | common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." 116 | 117 | if { $nRet != 0 } { 118 | catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} 119 | return $nRet 120 | } 121 | 122 | set bCheckIPsPassed 1 123 | ################################################################## 124 | # CHECK IPs 125 | ################################################################## 126 | set bCheckIPs 1 127 | if { $bCheckIPs == 1 } { 128 | set list_check_ips "\ 129 | xilinx.com:ip:axi_dma:7.1\ 130 | xilinx.com:ip:axi_intc:4.1\ 131 | xilinx.com:ip:smartconnect:1.0\ 132 | xilinx.com:ip:cmac_usplus:3.1\ 133 | xilinx.com:ip:proc_sys_reset:5.0\ 134 | xilinx.com:ip:axis_data_fifo:2.0\ 135 | xilinx.com:ip:system_ila:1.1\ 136 | xilinx.com:ip:util_vector_logic:2.0\ 137 | xilinx.com:ip:vio:3.0\ 138 | xilinx.com:ip:xlconcat:2.1\ 139 | xilinx.com:ip:xlconstant:1.1\ 140 | xilinx.com:ip:zynq_ultra_ps_e:3.3\ 141 | " 142 | 143 | set list_ips_missing "" 144 | common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." 145 | 146 | foreach ip_vlnv $list_check_ips { 147 | set ip_obj [get_ipdefs -all $ip_vlnv] 148 | if { $ip_obj eq "" } { 149 | lappend list_ips_missing $ip_vlnv 150 | } 151 | } 152 | 153 | if { $list_ips_missing ne "" } { 154 | catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } 155 | set bCheckIPsPassed 0 156 | } 157 | 158 | } 159 | 160 | if { $bCheckIPsPassed != 1 } { 161 | common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." 162 | return 3 163 | } 164 | 165 | ################################################################## 166 | # DESIGN PROCs 167 | ################################################################## 168 | 169 | 170 | 171 | # Procedure to create entire design; Provide argument to make 172 | # procedure reusable. If parentCell is "", will use root. 173 | proc create_root_design { parentCell } { 174 | 175 | variable script_folder 176 | variable design_name 177 | 178 | if { $parentCell eq "" } { 179 | set parentCell [get_bd_cells /] 180 | } 181 | 182 | # Get object for parentCell 183 | set parentObj [get_bd_cells $parentCell] 184 | if { $parentObj == "" } { 185 | catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} 186 | return 187 | } 188 | 189 | # Make sure parentObj is hier blk 190 | set parentType [get_property TYPE $parentObj] 191 | if { $parentType ne "hier" } { 192 | catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} 193 | return 194 | } 195 | 196 | # Save current instance; Restore later 197 | set oldCurInst [current_bd_instance .] 198 | 199 | # Set parent object as current 200 | current_bd_instance $parentObj 201 | 202 | 203 | # Create interface ports 204 | set diff_clock_rtl [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 diff_clock_rtl ] 205 | set_property -dict [ list \ 206 | CONFIG.FREQ_HZ {156250000} \ 207 | ] $diff_clock_rtl 208 | 209 | set gt_rtl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 gt_rtl ] 210 | 211 | 212 | # Create ports 213 | set qsfp1_intl [ create_bd_port -dir I qsfp1_intl ] 214 | set qsfp1_modprsl [ create_bd_port -dir I qsfp1_modprsl ] 215 | set qsfp1_modsell [ create_bd_port -dir O -from 0 -to 0 qsfp1_modsell ] 216 | set qsfp1_resetl [ create_bd_port -dir O -from 0 -to 0 qsfp1_resetl ] 217 | 218 | # Create instance: axi_dma_0, and set properties 219 | set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ] 220 | set_property -dict [ list \ 221 | CONFIG.c_include_sg {0} \ 222 | CONFIG.c_m_axi_mm2s_data_width {512} \ 223 | CONFIG.c_m_axis_mm2s_tdata_width {512} \ 224 | CONFIG.c_mm2s_burst_size {16} \ 225 | CONFIG.c_sg_include_stscntrl_strm {0} \ 226 | CONFIG.c_sg_length_width {26} \ 227 | ] $axi_dma_0 228 | 229 | # Create instance: axi_intc_0, and set properties 230 | set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ] 231 | 232 | # Create instance: axi_smc, and set properties 233 | set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] 234 | set_property -dict [ list \ 235 | CONFIG.NUM_SI {2} \ 236 | ] $axi_smc 237 | 238 | # Create instance: cmac_usplus_0, and set properties 239 | set cmac_usplus_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:3.1 cmac_usplus_0 ] 240 | set_property -dict [ list \ 241 | CONFIG.CMAC_CAUI4_MODE {1} \ 242 | CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y0} \ 243 | CONFIG.DIFFCLK_BOARD_INTERFACE {Custom} \ 244 | CONFIG.ENABLE_AXI_INTERFACE {1} \ 245 | CONFIG.GT_GROUP_SELECT {X0Y8~X0Y11} \ 246 | CONFIG.GT_REF_CLK_FREQ {156.25} \ 247 | CONFIG.INCLUDE_STATISTICS_COUNTERS {1} \ 248 | CONFIG.LANE10_GT_LOC {NA} \ 249 | CONFIG.LANE1_GT_LOC {X0Y8} \ 250 | CONFIG.LANE2_GT_LOC {X0Y9} \ 251 | CONFIG.LANE3_GT_LOC {X0Y10} \ 252 | CONFIG.LANE4_GT_LOC {X0Y11} \ 253 | CONFIG.LANE5_GT_LOC {NA} \ 254 | CONFIG.LANE6_GT_LOC {NA} \ 255 | CONFIG.LANE7_GT_LOC {NA} \ 256 | CONFIG.LANE8_GT_LOC {NA} \ 257 | CONFIG.LANE9_GT_LOC {NA} \ 258 | CONFIG.NUM_LANES {4x25} \ 259 | CONFIG.RX_EQ_MODE {DFE} \ 260 | CONFIG.RX_FLOW_CONTROL {0} \ 261 | CONFIG.TX_FLOW_CONTROL {0} \ 262 | CONFIG.USER_INTERFACE {AXIS} \ 263 | CONFIG.USE_BOARD_FLOW {true} \ 264 | ] $cmac_usplus_0 265 | 266 | # Create instance: ps8_0_axi_periph, and set properties 267 | set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] 268 | set_property -dict [ list \ 269 | CONFIG.NUM_MI {3} \ 270 | CONFIG.NUM_SI {2} \ 271 | ] $ps8_0_axi_periph 272 | 273 | # Create instance: rst_ps8_0_99M, and set properties 274 | set rst_ps8_0_99M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_99M ] 275 | 276 | # Create instance: rx_fifo, and set properties 277 | set rx_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 rx_fifo ] 278 | set_property -dict [ list \ 279 | CONFIG.FIFO_MODE {2} \ 280 | CONFIG.IS_ACLK_ASYNC {1} \ 281 | ] $rx_fifo 282 | 283 | # Create instance: system_ila_0, and set properties 284 | set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ] 285 | set_property -dict [ list \ 286 | CONFIG.C_BRAM_CNT {6} \ 287 | CONFIG.C_MON_TYPE {INTERFACE} \ 288 | CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ 289 | ] $system_ila_0 290 | 291 | # Create instance: system_ila_1, and set properties 292 | set system_ila_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_1 ] 293 | set_property -dict [ list \ 294 | CONFIG.C_BRAM_CNT {6} \ 295 | CONFIG.C_MON_TYPE {INTERFACE} \ 296 | CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ 297 | ] $system_ila_1 298 | 299 | # Create instance: system_ila_2, and set properties 300 | set system_ila_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_2 ] 301 | set_property -dict [ list \ 302 | CONFIG.C_BRAM_CNT {0} \ 303 | CONFIG.C_MON_TYPE {INTERFACE} \ 304 | CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:aximm_rtl:1.0} \ 305 | ] $system_ila_2 306 | 307 | # Create instance: tx_fifo, and set properties 308 | set tx_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 tx_fifo ] 309 | set_property -dict [ list \ 310 | CONFIG.FIFO_MODE {2} \ 311 | CONFIG.IS_ACLK_ASYNC {1} \ 312 | CONFIG.TDATA_NUM_BYTES {64} \ 313 | ] $tx_fifo 314 | 315 | # Create instance: util_vector_logic1, and set properties 316 | set util_vector_logic1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic1 ] 317 | set_property -dict [ list \ 318 | CONFIG.C_OPERATION {not} \ 319 | CONFIG.C_SIZE {1} \ 320 | CONFIG.LOGO_FILE {data/sym_notgate.png} \ 321 | ] $util_vector_logic1 322 | 323 | # Create instance: vio_0, and set properties 324 | set vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_0 ] 325 | set_property -dict [ list \ 326 | CONFIG.C_NUM_PROBE_OUT {0} \ 327 | ] $vio_0 328 | 329 | # Create instance: vio_1, and set properties 330 | set vio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_1 ] 331 | set_property -dict [ list \ 332 | CONFIG.C_NUM_PROBE_OUT {0} \ 333 | ] $vio_1 334 | 335 | # Create instance: vio_2, and set properties 336 | set vio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_2 ] 337 | set_property -dict [ list \ 338 | CONFIG.C_NUM_PROBE_IN {2} \ 339 | CONFIG.C_NUM_PROBE_OUT {0} \ 340 | ] $vio_2 341 | 342 | # Create instance: xlconcat_0, and set properties 343 | set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] 344 | 345 | # Create instance: xlconstant_0, and set properties 346 | set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] 347 | set_property -dict [ list \ 348 | CONFIG.CONST_VAL {0} \ 349 | ] $xlconstant_0 350 | 351 | # Create instance: xlconstant_1, and set properties 352 | set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] 353 | 354 | # Create instance: xlconstant_2, and set properties 355 | set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] 356 | 357 | # Create instance: zynq_ultra_ps_e_0, and set properties 358 | set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] 359 | set_property -dict [ list \ 360 | CONFIG.CAN0_BOARD_INTERFACE {custom} \ 361 | CONFIG.CAN1_BOARD_INTERFACE {custom} \ 362 | CONFIG.CSU_BOARD_INTERFACE {custom} \ 363 | CONFIG.DP_BOARD_INTERFACE {custom} \ 364 | CONFIG.GEM0_BOARD_INTERFACE {custom} \ 365 | CONFIG.GEM1_BOARD_INTERFACE {custom} \ 366 | CONFIG.GEM2_BOARD_INTERFACE {custom} \ 367 | CONFIG.GEM3_BOARD_INTERFACE {custom} \ 368 | CONFIG.GPIO_BOARD_INTERFACE {custom} \ 369 | CONFIG.IIC0_BOARD_INTERFACE {custom} \ 370 | CONFIG.IIC1_BOARD_INTERFACE {custom} \ 371 | CONFIG.NAND_BOARD_INTERFACE {custom} \ 372 | CONFIG.PCIE_BOARD_INTERFACE {custom} \ 373 | CONFIG.PJTAG_BOARD_INTERFACE {custom} \ 374 | CONFIG.PMU_BOARD_INTERFACE {custom} \ 375 | CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ 376 | CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ 377 | CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ 378 | CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \ 379 | CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ 380 | CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ 381 | CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ 382 | CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {1} \ 383 | CONFIG.PSU_IMPORT_BOARD_PRESET {} \ 384 | CONFIG.PSU_MIO_0_DIRECTION {out} \ 385 | CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ 386 | CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ 387 | CONFIG.PSU_MIO_0_POLARITY {Default} \ 388 | CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ 389 | CONFIG.PSU_MIO_0_SLEW {fast} \ 390 | CONFIG.PSU_MIO_10_DIRECTION {inout} \ 391 | CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ 392 | CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \ 393 | CONFIG.PSU_MIO_10_POLARITY {Default} \ 394 | CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ 395 | CONFIG.PSU_MIO_10_SLEW {fast} \ 396 | CONFIG.PSU_MIO_11_DIRECTION {inout} \ 397 | CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ 398 | CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \ 399 | CONFIG.PSU_MIO_11_POLARITY {Default} \ 400 | CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ 401 | CONFIG.PSU_MIO_11_SLEW {fast} \ 402 | CONFIG.PSU_MIO_12_DIRECTION {out} \ 403 | CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ 404 | CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ 405 | CONFIG.PSU_MIO_12_POLARITY {Default} \ 406 | CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ 407 | CONFIG.PSU_MIO_12_SLEW {fast} \ 408 | CONFIG.PSU_MIO_13_DIRECTION {inout} \ 409 | CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ 410 | CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ 411 | CONFIG.PSU_MIO_13_POLARITY {Default} \ 412 | CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ 413 | CONFIG.PSU_MIO_13_SLEW {fast} \ 414 | CONFIG.PSU_MIO_14_DIRECTION {inout} \ 415 | CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ 416 | CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \ 417 | CONFIG.PSU_MIO_14_POLARITY {Default} \ 418 | CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ 419 | CONFIG.PSU_MIO_14_SLEW {fast} \ 420 | CONFIG.PSU_MIO_15_DIRECTION {inout} \ 421 | CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ 422 | CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \ 423 | CONFIG.PSU_MIO_15_POLARITY {Default} \ 424 | CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ 425 | CONFIG.PSU_MIO_15_SLEW {fast} \ 426 | CONFIG.PSU_MIO_16_DIRECTION {inout} \ 427 | CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ 428 | CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \ 429 | CONFIG.PSU_MIO_16_POLARITY {Default} \ 430 | CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ 431 | CONFIG.PSU_MIO_16_SLEW {fast} \ 432 | CONFIG.PSU_MIO_17_DIRECTION {inout} \ 433 | CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ 434 | CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \ 435 | CONFIG.PSU_MIO_17_POLARITY {Default} \ 436 | CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ 437 | CONFIG.PSU_MIO_17_SLEW {fast} \ 438 | CONFIG.PSU_MIO_18_DIRECTION {in} \ 439 | CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ 440 | CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \ 441 | CONFIG.PSU_MIO_18_POLARITY {Default} \ 442 | CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ 443 | CONFIG.PSU_MIO_18_SLEW {fast} \ 444 | CONFIG.PSU_MIO_19_DIRECTION {out} \ 445 | CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ 446 | CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ 447 | CONFIG.PSU_MIO_19_POLARITY {Default} \ 448 | CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ 449 | CONFIG.PSU_MIO_19_SLEW {fast} \ 450 | CONFIG.PSU_MIO_1_DIRECTION {inout} \ 451 | CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ 452 | CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \ 453 | CONFIG.PSU_MIO_1_POLARITY {Default} \ 454 | CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ 455 | CONFIG.PSU_MIO_1_SLEW {fast} \ 456 | CONFIG.PSU_MIO_20_DIRECTION {inout} \ 457 | CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ 458 | CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \ 459 | CONFIG.PSU_MIO_20_POLARITY {Default} \ 460 | CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ 461 | CONFIG.PSU_MIO_20_SLEW {fast} \ 462 | CONFIG.PSU_MIO_21_DIRECTION {inout} \ 463 | CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ 464 | CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \ 465 | CONFIG.PSU_MIO_21_POLARITY {Default} \ 466 | CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ 467 | CONFIG.PSU_MIO_21_SLEW {fast} \ 468 | CONFIG.PSU_MIO_22_DIRECTION {inout} \ 469 | CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ 470 | CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ 471 | CONFIG.PSU_MIO_22_POLARITY {Default} \ 472 | CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ 473 | CONFIG.PSU_MIO_22_SLEW {fast} \ 474 | CONFIG.PSU_MIO_23_DIRECTION {inout} \ 475 | CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ 476 | CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \ 477 | CONFIG.PSU_MIO_23_POLARITY {Default} \ 478 | CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ 479 | CONFIG.PSU_MIO_23_SLEW {fast} \ 480 | CONFIG.PSU_MIO_24_DIRECTION {inout} \ 481 | CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ 482 | CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \ 483 | CONFIG.PSU_MIO_24_POLARITY {Default} \ 484 | CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ 485 | CONFIG.PSU_MIO_24_SLEW {fast} \ 486 | CONFIG.PSU_MIO_25_DIRECTION {inout} \ 487 | CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ 488 | CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \ 489 | CONFIG.PSU_MIO_25_POLARITY {Default} \ 490 | CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ 491 | CONFIG.PSU_MIO_25_SLEW {fast} \ 492 | CONFIG.PSU_MIO_26_DIRECTION {inout} \ 493 | CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ 494 | CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \ 495 | CONFIG.PSU_MIO_26_POLARITY {Default} \ 496 | CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ 497 | CONFIG.PSU_MIO_26_SLEW {fast} \ 498 | CONFIG.PSU_MIO_27_DIRECTION {out} \ 499 | CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ 500 | CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ 501 | CONFIG.PSU_MIO_27_POLARITY {Default} \ 502 | CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ 503 | CONFIG.PSU_MIO_27_SLEW {fast} \ 504 | CONFIG.PSU_MIO_28_DIRECTION {in} \ 505 | CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ 506 | CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \ 507 | CONFIG.PSU_MIO_28_POLARITY {Default} \ 508 | CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ 509 | CONFIG.PSU_MIO_28_SLEW {fast} \ 510 | CONFIG.PSU_MIO_29_DIRECTION {out} \ 511 | CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ 512 | CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ 513 | CONFIG.PSU_MIO_29_POLARITY {Default} \ 514 | CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ 515 | CONFIG.PSU_MIO_29_SLEW {fast} \ 516 | CONFIG.PSU_MIO_2_DIRECTION {inout} \ 517 | CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ 518 | CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \ 519 | CONFIG.PSU_MIO_2_POLARITY {Default} \ 520 | CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ 521 | CONFIG.PSU_MIO_2_SLEW {fast} \ 522 | CONFIG.PSU_MIO_30_DIRECTION {in} \ 523 | CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ 524 | CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \ 525 | CONFIG.PSU_MIO_30_POLARITY {Default} \ 526 | CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ 527 | CONFIG.PSU_MIO_30_SLEW {fast} \ 528 | CONFIG.PSU_MIO_31_DIRECTION {inout} \ 529 | CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ 530 | CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \ 531 | CONFIG.PSU_MIO_31_POLARITY {Default} \ 532 | CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ 533 | CONFIG.PSU_MIO_31_SLEW {fast} \ 534 | CONFIG.PSU_MIO_32_DIRECTION {out} \ 535 | CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ 536 | CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ 537 | CONFIG.PSU_MIO_32_POLARITY {Default} \ 538 | CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ 539 | CONFIG.PSU_MIO_32_SLEW {fast} \ 540 | CONFIG.PSU_MIO_33_DIRECTION {out} \ 541 | CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ 542 | CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ 543 | CONFIG.PSU_MIO_33_POLARITY {Default} \ 544 | CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ 545 | CONFIG.PSU_MIO_33_SLEW {fast} \ 546 | CONFIG.PSU_MIO_34_DIRECTION {out} \ 547 | CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ 548 | CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ 549 | CONFIG.PSU_MIO_34_POLARITY {Default} \ 550 | CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ 551 | CONFIG.PSU_MIO_34_SLEW {fast} \ 552 | CONFIG.PSU_MIO_35_DIRECTION {out} \ 553 | CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ 554 | CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ 555 | CONFIG.PSU_MIO_35_POLARITY {Default} \ 556 | CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ 557 | CONFIG.PSU_MIO_35_SLEW {fast} \ 558 | CONFIG.PSU_MIO_36_DIRECTION {out} \ 559 | CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ 560 | CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ 561 | CONFIG.PSU_MIO_36_POLARITY {Default} \ 562 | CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ 563 | CONFIG.PSU_MIO_36_SLEW {fast} \ 564 | CONFIG.PSU_MIO_37_DIRECTION {out} \ 565 | CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ 566 | CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ 567 | CONFIG.PSU_MIO_37_POLARITY {Default} \ 568 | CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ 569 | CONFIG.PSU_MIO_37_SLEW {fast} \ 570 | CONFIG.PSU_MIO_38_DIRECTION {inout} \ 571 | CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ 572 | CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \ 573 | CONFIG.PSU_MIO_38_POLARITY {Default} \ 574 | CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ 575 | CONFIG.PSU_MIO_38_SLEW {fast} \ 576 | CONFIG.PSU_MIO_39_DIRECTION {inout} \ 577 | CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ 578 | CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \ 579 | CONFIG.PSU_MIO_39_POLARITY {Default} \ 580 | CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ 581 | CONFIG.PSU_MIO_39_SLEW {fast} \ 582 | CONFIG.PSU_MIO_3_DIRECTION {inout} \ 583 | CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ 584 | CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ 585 | CONFIG.PSU_MIO_3_POLARITY {Default} \ 586 | CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ 587 | CONFIG.PSU_MIO_3_SLEW {fast} \ 588 | CONFIG.PSU_MIO_40_DIRECTION {inout} \ 589 | CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ 590 | CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \ 591 | CONFIG.PSU_MIO_40_POLARITY {Default} \ 592 | CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ 593 | CONFIG.PSU_MIO_40_SLEW {fast} \ 594 | CONFIG.PSU_MIO_41_DIRECTION {inout} \ 595 | CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ 596 | CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \ 597 | CONFIG.PSU_MIO_41_POLARITY {Default} \ 598 | CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ 599 | CONFIG.PSU_MIO_41_SLEW {fast} \ 600 | CONFIG.PSU_MIO_42_DIRECTION {inout} \ 601 | CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ 602 | CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \ 603 | CONFIG.PSU_MIO_42_POLARITY {Default} \ 604 | CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ 605 | CONFIG.PSU_MIO_42_SLEW {fast} \ 606 | CONFIG.PSU_MIO_43_DIRECTION {inout} \ 607 | CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ 608 | CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \ 609 | CONFIG.PSU_MIO_43_POLARITY {Default} \ 610 | CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ 611 | CONFIG.PSU_MIO_43_SLEW {fast} \ 612 | CONFIG.PSU_MIO_44_DIRECTION {inout} \ 613 | CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ 614 | CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \ 615 | CONFIG.PSU_MIO_44_POLARITY {Default} \ 616 | CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ 617 | CONFIG.PSU_MIO_44_SLEW {fast} \ 618 | CONFIG.PSU_MIO_45_DIRECTION {in} \ 619 | CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ 620 | CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \ 621 | CONFIG.PSU_MIO_45_POLARITY {Default} \ 622 | CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ 623 | CONFIG.PSU_MIO_45_SLEW {fast} \ 624 | CONFIG.PSU_MIO_46_DIRECTION {inout} \ 625 | CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ 626 | CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \ 627 | CONFIG.PSU_MIO_46_POLARITY {Default} \ 628 | CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ 629 | CONFIG.PSU_MIO_46_SLEW {fast} \ 630 | CONFIG.PSU_MIO_47_DIRECTION {inout} \ 631 | CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ 632 | CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \ 633 | CONFIG.PSU_MIO_47_POLARITY {Default} \ 634 | CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ 635 | CONFIG.PSU_MIO_47_SLEW {fast} \ 636 | CONFIG.PSU_MIO_48_DIRECTION {inout} \ 637 | CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ 638 | CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \ 639 | CONFIG.PSU_MIO_48_POLARITY {Default} \ 640 | CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ 641 | CONFIG.PSU_MIO_48_SLEW {fast} \ 642 | CONFIG.PSU_MIO_49_DIRECTION {inout} \ 643 | CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ 644 | CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \ 645 | CONFIG.PSU_MIO_49_POLARITY {Default} \ 646 | CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ 647 | CONFIG.PSU_MIO_49_SLEW {fast} \ 648 | CONFIG.PSU_MIO_4_DIRECTION {inout} \ 649 | CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ 650 | CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \ 651 | CONFIG.PSU_MIO_4_POLARITY {Default} \ 652 | CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ 653 | CONFIG.PSU_MIO_4_SLEW {fast} \ 654 | CONFIG.PSU_MIO_50_DIRECTION {inout} \ 655 | CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ 656 | CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \ 657 | CONFIG.PSU_MIO_50_POLARITY {Default} \ 658 | CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ 659 | CONFIG.PSU_MIO_50_SLEW {fast} \ 660 | CONFIG.PSU_MIO_51_DIRECTION {out} \ 661 | CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ 662 | CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ 663 | CONFIG.PSU_MIO_51_POLARITY {Default} \ 664 | CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ 665 | CONFIG.PSU_MIO_51_SLEW {fast} \ 666 | CONFIG.PSU_MIO_52_DIRECTION {in} \ 667 | CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ 668 | CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \ 669 | CONFIG.PSU_MIO_52_POLARITY {Default} \ 670 | CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ 671 | CONFIG.PSU_MIO_52_SLEW {fast} \ 672 | CONFIG.PSU_MIO_53_DIRECTION {in} \ 673 | CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ 674 | CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \ 675 | CONFIG.PSU_MIO_53_POLARITY {Default} \ 676 | CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ 677 | CONFIG.PSU_MIO_53_SLEW {fast} \ 678 | CONFIG.PSU_MIO_54_DIRECTION {inout} \ 679 | CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ 680 | CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \ 681 | CONFIG.PSU_MIO_54_POLARITY {Default} \ 682 | CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ 683 | CONFIG.PSU_MIO_54_SLEW {fast} \ 684 | CONFIG.PSU_MIO_55_DIRECTION {in} \ 685 | CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ 686 | CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \ 687 | CONFIG.PSU_MIO_55_POLARITY {Default} \ 688 | CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ 689 | CONFIG.PSU_MIO_55_SLEW {fast} \ 690 | CONFIG.PSU_MIO_56_DIRECTION {inout} \ 691 | CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ 692 | CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \ 693 | CONFIG.PSU_MIO_56_POLARITY {Default} \ 694 | CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ 695 | CONFIG.PSU_MIO_56_SLEW {fast} \ 696 | CONFIG.PSU_MIO_57_DIRECTION {inout} \ 697 | CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ 698 | CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \ 699 | CONFIG.PSU_MIO_57_POLARITY {Default} \ 700 | CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ 701 | CONFIG.PSU_MIO_57_SLEW {fast} \ 702 | CONFIG.PSU_MIO_58_DIRECTION {out} \ 703 | CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ 704 | CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ 705 | CONFIG.PSU_MIO_58_POLARITY {Default} \ 706 | CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ 707 | CONFIG.PSU_MIO_58_SLEW {fast} \ 708 | CONFIG.PSU_MIO_59_DIRECTION {inout} \ 709 | CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ 710 | CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \ 711 | CONFIG.PSU_MIO_59_POLARITY {Default} \ 712 | CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ 713 | CONFIG.PSU_MIO_59_SLEW {fast} \ 714 | CONFIG.PSU_MIO_5_DIRECTION {out} \ 715 | CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ 716 | CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ 717 | CONFIG.PSU_MIO_5_POLARITY {Default} \ 718 | CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ 719 | CONFIG.PSU_MIO_5_SLEW {fast} \ 720 | CONFIG.PSU_MIO_60_DIRECTION {inout} \ 721 | CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ 722 | CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \ 723 | CONFIG.PSU_MIO_60_POLARITY {Default} \ 724 | CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ 725 | CONFIG.PSU_MIO_60_SLEW {fast} \ 726 | CONFIG.PSU_MIO_61_DIRECTION {inout} \ 727 | CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ 728 | CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \ 729 | CONFIG.PSU_MIO_61_POLARITY {Default} \ 730 | CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ 731 | CONFIG.PSU_MIO_61_SLEW {fast} \ 732 | CONFIG.PSU_MIO_62_DIRECTION {inout} \ 733 | CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ 734 | CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \ 735 | CONFIG.PSU_MIO_62_POLARITY {Default} \ 736 | CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ 737 | CONFIG.PSU_MIO_62_SLEW {fast} \ 738 | CONFIG.PSU_MIO_63_DIRECTION {inout} \ 739 | CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ 740 | CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \ 741 | CONFIG.PSU_MIO_63_POLARITY {Default} \ 742 | CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ 743 | CONFIG.PSU_MIO_63_SLEW {fast} \ 744 | CONFIG.PSU_MIO_64_DIRECTION {out} \ 745 | CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ 746 | CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ 747 | CONFIG.PSU_MIO_64_POLARITY {Default} \ 748 | CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ 749 | CONFIG.PSU_MIO_64_SLEW {fast} \ 750 | CONFIG.PSU_MIO_65_DIRECTION {out} \ 751 | CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ 752 | CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ 753 | CONFIG.PSU_MIO_65_POLARITY {Default} \ 754 | CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ 755 | CONFIG.PSU_MIO_65_SLEW {fast} \ 756 | CONFIG.PSU_MIO_66_DIRECTION {out} \ 757 | CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ 758 | CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ 759 | CONFIG.PSU_MIO_66_POLARITY {Default} \ 760 | CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ 761 | CONFIG.PSU_MIO_66_SLEW {fast} \ 762 | CONFIG.PSU_MIO_67_DIRECTION {out} \ 763 | CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ 764 | CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ 765 | CONFIG.PSU_MIO_67_POLARITY {Default} \ 766 | CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ 767 | CONFIG.PSU_MIO_67_SLEW {fast} \ 768 | CONFIG.PSU_MIO_68_DIRECTION {out} \ 769 | CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ 770 | CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ 771 | CONFIG.PSU_MIO_68_POLARITY {Default} \ 772 | CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ 773 | CONFIG.PSU_MIO_68_SLEW {fast} \ 774 | CONFIG.PSU_MIO_69_DIRECTION {out} \ 775 | CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ 776 | CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ 777 | CONFIG.PSU_MIO_69_POLARITY {Default} \ 778 | CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ 779 | CONFIG.PSU_MIO_69_SLEW {fast} \ 780 | CONFIG.PSU_MIO_6_DIRECTION {out} \ 781 | CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ 782 | CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ 783 | CONFIG.PSU_MIO_6_POLARITY {Default} \ 784 | CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ 785 | CONFIG.PSU_MIO_6_SLEW {fast} \ 786 | CONFIG.PSU_MIO_70_DIRECTION {in} \ 787 | CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ 788 | CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ 789 | CONFIG.PSU_MIO_70_POLARITY {Default} \ 790 | CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ 791 | CONFIG.PSU_MIO_70_SLEW {fast} \ 792 | CONFIG.PSU_MIO_71_DIRECTION {in} \ 793 | CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ 794 | CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \ 795 | CONFIG.PSU_MIO_71_POLARITY {Default} \ 796 | CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ 797 | CONFIG.PSU_MIO_71_SLEW {fast} \ 798 | CONFIG.PSU_MIO_72_DIRECTION {in} \ 799 | CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ 800 | CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \ 801 | CONFIG.PSU_MIO_72_POLARITY {Default} \ 802 | CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ 803 | CONFIG.PSU_MIO_72_SLEW {fast} \ 804 | CONFIG.PSU_MIO_73_DIRECTION {in} \ 805 | CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ 806 | CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \ 807 | CONFIG.PSU_MIO_73_POLARITY {Default} \ 808 | CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ 809 | CONFIG.PSU_MIO_73_SLEW {fast} \ 810 | CONFIG.PSU_MIO_74_DIRECTION {in} \ 811 | CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ 812 | CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \ 813 | CONFIG.PSU_MIO_74_POLARITY {Default} \ 814 | CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ 815 | CONFIG.PSU_MIO_74_SLEW {fast} \ 816 | CONFIG.PSU_MIO_75_DIRECTION {in} \ 817 | CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ 818 | CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \ 819 | CONFIG.PSU_MIO_75_POLARITY {Default} \ 820 | CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ 821 | CONFIG.PSU_MIO_75_SLEW {fast} \ 822 | CONFIG.PSU_MIO_76_DIRECTION {out} \ 823 | CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ 824 | CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ 825 | CONFIG.PSU_MIO_76_POLARITY {Default} \ 826 | CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ 827 | CONFIG.PSU_MIO_76_SLEW {fast} \ 828 | CONFIG.PSU_MIO_77_DIRECTION {inout} \ 829 | CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ 830 | CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \ 831 | CONFIG.PSU_MIO_77_POLARITY {Default} \ 832 | CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ 833 | CONFIG.PSU_MIO_77_SLEW {fast} \ 834 | CONFIG.PSU_MIO_7_DIRECTION {out} \ 835 | CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ 836 | CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ 837 | CONFIG.PSU_MIO_7_POLARITY {Default} \ 838 | CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ 839 | CONFIG.PSU_MIO_7_SLEW {fast} \ 840 | CONFIG.PSU_MIO_8_DIRECTION {inout} \ 841 | CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ 842 | CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \ 843 | CONFIG.PSU_MIO_8_POLARITY {Default} \ 844 | CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ 845 | CONFIG.PSU_MIO_8_SLEW {fast} \ 846 | CONFIG.PSU_MIO_9_DIRECTION {inout} \ 847 | CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ 848 | CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \ 849 | CONFIG.PSU_MIO_9_POLARITY {Default} \ 850 | CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ 851 | CONFIG.PSU_MIO_9_SLEW {fast} \ 852 | CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ 853 | CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#gpio0[20]#gpio0[21]#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ 854 | CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ 855 | CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ 856 | CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ 857 | CONFIG.PSU_SMC_CYCLE_T0 {NA} \ 858 | CONFIG.PSU_SMC_CYCLE_T1 {NA} \ 859 | CONFIG.PSU_SMC_CYCLE_T2 {NA} \ 860 | CONFIG.PSU_SMC_CYCLE_T3 {NA} \ 861 | CONFIG.PSU_SMC_CYCLE_T4 {NA} \ 862 | CONFIG.PSU_SMC_CYCLE_T5 {NA} \ 863 | CONFIG.PSU_SMC_CYCLE_T6 {NA} \ 864 | CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ 865 | CONFIG.PSU_VALUE_SILVERSION {3} \ 866 | CONFIG.PSU__ACPU0__POWER__ON {1} \ 867 | CONFIG.PSU__ACPU1__POWER__ON {1} \ 868 | CONFIG.PSU__ACPU2__POWER__ON {1} \ 869 | CONFIG.PSU__ACPU3__POWER__ON {1} \ 870 | CONFIG.PSU__ACTUAL__IP {1} \ 871 | CONFIG.PSU__ACT_DDR_FREQ_MHZ {1066.656006} \ 872 | CONFIG.PSU__AFI0_COHERENCY {0} \ 873 | CONFIG.PSU__AFI1_COHERENCY {0} \ 874 | CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ 875 | CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ 876 | CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \ 877 | CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ 878 | CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ 879 | CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ 880 | CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \ 881 | CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ 882 | CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ 883 | CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ 884 | CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ 885 | CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ 886 | CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ 887 | CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ 888 | CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ 889 | CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ 890 | CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ 891 | CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ 892 | CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ 893 | CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ 894 | CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ 895 | CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ 896 | CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ 897 | CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ 898 | CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ 899 | CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ 900 | CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ 901 | CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ 902 | CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ 903 | CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ 904 | CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ 905 | CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ 906 | CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ 907 | CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ 908 | CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ 909 | CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ 910 | CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ 911 | CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ 912 | CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ 913 | CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ 914 | CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ 915 | CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ 916 | CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ 917 | CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ 918 | CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ 919 | CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ 920 | CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ 921 | CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ 922 | CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ 923 | CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ 924 | CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ 925 | CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \ 926 | CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ 927 | CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ 928 | CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ 929 | CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ 930 | CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ 931 | CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ 932 | CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ 933 | CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \ 934 | CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ 935 | CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ 936 | CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ 937 | CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {533.328003} \ 938 | CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ 939 | CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \ 940 | CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ 941 | CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ 942 | CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ 943 | CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ 944 | CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ 945 | CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ 946 | CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \ 947 | CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ 948 | CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ 949 | CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ 950 | CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ 951 | CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ 952 | CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.999750} \ 953 | CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \ 954 | CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ 955 | CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ 956 | CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ 957 | CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ 958 | CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785446} \ 959 | CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \ 960 | CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ 961 | CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ 962 | CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ 963 | CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.997009} \ 964 | CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ 965 | CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ 966 | CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ 967 | CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ 968 | CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ 969 | CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ 970 | CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ 971 | CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ 972 | CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ 973 | CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \ 974 | CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ 975 | CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ 976 | CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ 977 | CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ 978 | CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ 979 | CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ 980 | CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ 981 | CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ 982 | CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ 983 | CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ 984 | CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ 985 | CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ 986 | CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.997498} \ 987 | CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \ 988 | CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ 989 | CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ 990 | CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ 991 | CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ 992 | CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ 993 | CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ 994 | CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.328003} \ 995 | CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ 996 | CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ 997 | CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ 998 | CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ 999 | CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ 1000 | CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ 1001 | CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ 1002 | CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ 1003 | CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ 1004 | CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ 1005 | CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \ 1006 | CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ 1007 | CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ 1008 | CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ 1009 | CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ 1010 | CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ 1011 | CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ 1012 | CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ 1013 | CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ 1014 | CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999500} \ 1015 | CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ 1016 | CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ 1017 | CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ 1018 | CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ 1019 | CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ 1020 | CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ 1021 | CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ 1022 | CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ 1023 | CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ 1024 | CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ 1025 | CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ 1026 | CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ 1027 | CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ 1028 | CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ 1029 | CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \ 1030 | CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ 1031 | CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ 1032 | CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ 1033 | CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ 1034 | CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ 1035 | CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \ 1036 | CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ 1037 | CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \ 1038 | CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ 1039 | CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ 1040 | CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ 1041 | CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ 1042 | CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ 1043 | CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ 1044 | CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ 1045 | CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.984985} \ 1046 | CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ 1047 | CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ 1048 | CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ 1049 | CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ 1050 | CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ 1051 | CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ 1052 | CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ 1053 | CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ 1054 | CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ 1055 | CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ 1056 | CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ 1057 | CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ 1058 | CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ 1059 | CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ 1060 | CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ 1061 | CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ 1062 | CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ 1063 | CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \ 1064 | CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ 1065 | CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ 1066 | CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ 1067 | CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ 1068 | CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.997498} \ 1069 | CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ 1070 | CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ 1071 | CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ 1072 | CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ 1073 | CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999001} \ 1074 | CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ 1075 | CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ 1076 | CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ 1077 | CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ 1078 | CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999001} \ 1079 | CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ 1080 | CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ 1081 | CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ 1082 | CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ 1083 | CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ 1084 | CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ 1085 | CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ 1086 | CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ 1087 | CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ 1088 | CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ 1089 | CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ 1090 | CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \ 1091 | CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ 1092 | CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ 1093 | CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ 1094 | CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ 1095 | CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ 1096 | CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ 1097 | CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ 1098 | CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \ 1099 | CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ 1100 | CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ 1101 | CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ 1102 | CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ 1103 | CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ 1104 | CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ 1105 | CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ 1106 | CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ 1107 | CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ 1108 | CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ 1109 | CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ 1110 | CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ 1111 | CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \ 1112 | CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ 1113 | CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ 1114 | CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ 1115 | CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999001} \ 1116 | CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ 1117 | CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ 1118 | CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ 1119 | CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ 1120 | CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \ 1121 | CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \ 1122 | CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ 1123 | CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \ 1124 | CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \ 1125 | CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \ 1126 | CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ 1127 | CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ 1128 | CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \ 1129 | CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \ 1130 | CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \ 1131 | CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ 1132 | CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ 1133 | CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \ 1134 | CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \ 1135 | CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \ 1136 | CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ 1137 | CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ 1138 | CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ 1139 | CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ 1140 | CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ 1141 | CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \ 1142 | CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ 1143 | CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ 1144 | CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ 1145 | CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ 1146 | CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ 1147 | CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \ 1148 | CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \ 1149 | CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ 1150 | CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ 1151 | CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \ 1152 | CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.498123} \ 1153 | CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ 1154 | CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ 1155 | CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ 1156 | CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ 1157 | CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \ 1158 | CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ 1159 | CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ 1160 | CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ 1161 | CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \ 1162 | CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \ 1163 | CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \ 1164 | CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ 1165 | CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ 1166 | CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \ 1167 | CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999001} \ 1168 | CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ 1169 | CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ 1170 | CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ 1171 | CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999001} \ 1172 | CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ 1173 | CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ 1174 | CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ 1175 | CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ 1176 | CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \ 1177 | CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ 1178 | CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ 1179 | CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ 1180 | CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ 1181 | CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \ 1182 | CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ 1183 | CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ 1184 | CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ 1185 | CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ 1186 | CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \ 1187 | CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ 1188 | CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ 1189 | CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ 1190 | CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ 1191 | CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \ 1192 | CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ 1193 | CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ 1194 | CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ 1195 | CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ 1196 | CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ 1197 | CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ 1198 | CONFIG.PSU__CSU_COHERENCY {0} \ 1199 | CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ 1200 | CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \ 1201 | CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ 1202 | CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ 1203 | CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ 1204 | CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \ 1205 | CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ 1206 | CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ 1207 | CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ 1208 | CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \ 1209 | CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ 1210 | CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ 1211 | CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ 1212 | CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \ 1213 | CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ 1214 | CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ 1215 | CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ 1216 | CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \ 1217 | CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ 1218 | CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ 1219 | CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ 1220 | CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \ 1221 | CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ 1222 | CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ 1223 | CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ 1224 | CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \ 1225 | CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ 1226 | CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ 1227 | CONFIG.PSU__DDRC__AL {0} \ 1228 | CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ 1229 | CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ 1230 | CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ 1231 | CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ 1232 | CONFIG.PSU__DDRC__CL {15} \ 1233 | CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ 1234 | CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ 1235 | CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \ 1236 | CONFIG.PSU__DDRC__CWL {14} \ 1237 | CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ 1238 | CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ 1239 | CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ 1240 | CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ 1241 | CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ 1242 | CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \ 1243 | CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ 1244 | CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ 1245 | CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ 1246 | CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ 1247 | CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ 1248 | CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ 1249 | CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ 1250 | CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ 1251 | CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ 1252 | CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ 1253 | CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ 1254 | CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ 1255 | CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ 1256 | CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ 1257 | CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ 1258 | CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ 1259 | CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ 1260 | CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ 1261 | CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ 1262 | CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ 1263 | CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ 1264 | CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ 1265 | CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ 1266 | CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ 1267 | CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ 1268 | CONFIG.PSU__DDRC__ECC {Disabled} \ 1269 | CONFIG.PSU__DDRC__ECC_SCRUB {0} \ 1270 | CONFIG.PSU__DDRC__ENABLE {1} \ 1271 | CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ 1272 | CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ 1273 | CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ 1274 | CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ 1275 | CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ 1276 | CONFIG.PSU__DDRC__FGRM {1X} \ 1277 | CONFIG.PSU__DDRC__FREQ_MHZ {1} \ 1278 | CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ 1279 | CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ 1280 | CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ 1281 | CONFIG.PSU__DDRC__LP_ASR {manual normal} \ 1282 | CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ 1283 | CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ 1284 | CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ 1285 | CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ 1286 | CONFIG.PSU__DDRC__PLL_BYPASS {0} \ 1287 | CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ 1288 | CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ 1289 | CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ 1290 | CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ 1291 | CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ 1292 | CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ 1293 | CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ 1294 | CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ 1295 | CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ 1296 | CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ 1297 | CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ 1298 | CONFIG.PSU__DDRC__T_FAW {30.0} \ 1299 | CONFIG.PSU__DDRC__T_RAS_MIN {33} \ 1300 | CONFIG.PSU__DDRC__T_RC {47.06} \ 1301 | CONFIG.PSU__DDRC__T_RCD {15} \ 1302 | CONFIG.PSU__DDRC__T_RP {15} \ 1303 | CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ 1304 | CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ 1305 | CONFIG.PSU__DDRC__VREF {1} \ 1306 | CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ 1307 | CONFIG.PSU__DDR_QOS_ENABLE {0} \ 1308 | CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \ 1309 | CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \ 1310 | CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \ 1311 | CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \ 1312 | CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \ 1313 | CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \ 1314 | CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \ 1315 | CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \ 1316 | CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \ 1317 | CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \ 1318 | CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \ 1319 | CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \ 1320 | CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \ 1321 | CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \ 1322 | CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \ 1323 | CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \ 1324 | CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \ 1325 | CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \ 1326 | CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \ 1327 | CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ 1328 | CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \ 1329 | CONFIG.PSU__DEVICE_TYPE {RFSOC} \ 1330 | CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ 1331 | CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ 1332 | CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ 1333 | CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ 1334 | CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ 1335 | CONFIG.PSU__DLL__ISUSED {1} \ 1336 | CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ 1337 | CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ 1338 | CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ 1339 | CONFIG.PSU__DP__REF_CLK_FREQ {27} \ 1340 | CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \ 1341 | CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ 1342 | CONFIG.PSU__ENET0__FIFO__ENABLE {0} \ 1343 | CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \ 1344 | CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ 1345 | CONFIG.PSU__ENET0__PTP__ENABLE {0} \ 1346 | CONFIG.PSU__ENET0__TSU__ENABLE {0} \ 1347 | CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ 1348 | CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \ 1349 | CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ 1350 | CONFIG.PSU__ENET1__PTP__ENABLE {0} \ 1351 | CONFIG.PSU__ENET1__TSU__ENABLE {0} \ 1352 | CONFIG.PSU__ENET2__FIFO__ENABLE {0} \ 1353 | CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \ 1354 | CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ 1355 | CONFIG.PSU__ENET2__PTP__ENABLE {0} \ 1356 | CONFIG.PSU__ENET2__TSU__ENABLE {0} \ 1357 | CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ 1358 | CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ 1359 | CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ 1360 | CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ 1361 | CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ 1362 | CONFIG.PSU__ENET3__PTP__ENABLE {0} \ 1363 | CONFIG.PSU__ENET3__TSU__ENABLE {0} \ 1364 | CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ 1365 | CONFIG.PSU__EN_EMIO_TRACE {0} \ 1366 | CONFIG.PSU__EP__IP {0} \ 1367 | CONFIG.PSU__EXPAND__CORESIGHT {0} \ 1368 | CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ 1369 | CONFIG.PSU__EXPAND__GIC {0} \ 1370 | CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ 1371 | CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ 1372 | CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ 1373 | CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \ 1374 | CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999001} \ 1375 | CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ 1376 | CONFIG.PSU__FPGA_PL0_ENABLE {1} \ 1377 | CONFIG.PSU__FPGA_PL1_ENABLE {0} \ 1378 | CONFIG.PSU__FPGA_PL2_ENABLE {0} \ 1379 | CONFIG.PSU__FPGA_PL3_ENABLE {0} \ 1380 | CONFIG.PSU__FP__POWER__ON {1} \ 1381 | CONFIG.PSU__FTM__CTI_IN_0 {0} \ 1382 | CONFIG.PSU__FTM__CTI_IN_1 {0} \ 1383 | CONFIG.PSU__FTM__CTI_IN_2 {0} \ 1384 | CONFIG.PSU__FTM__CTI_IN_3 {0} \ 1385 | CONFIG.PSU__FTM__CTI_OUT_0 {0} \ 1386 | CONFIG.PSU__FTM__CTI_OUT_1 {0} \ 1387 | CONFIG.PSU__FTM__CTI_OUT_2 {0} \ 1388 | CONFIG.PSU__FTM__CTI_OUT_3 {0} \ 1389 | CONFIG.PSU__FTM__GPI {0} \ 1390 | CONFIG.PSU__FTM__GPO {0} \ 1391 | CONFIG.PSU__GEM0_COHERENCY {0} \ 1392 | CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \ 1393 | CONFIG.PSU__GEM1_COHERENCY {0} \ 1394 | CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ 1395 | CONFIG.PSU__GEM2_COHERENCY {0} \ 1396 | CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \ 1397 | CONFIG.PSU__GEM3_COHERENCY {0} \ 1398 | CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ 1399 | CONFIG.PSU__GEM__TSU__ENABLE {0} \ 1400 | CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ 1401 | CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ 1402 | CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ 1403 | CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ 1404 | CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ 1405 | CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ 1406 | CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ 1407 | CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ 1408 | CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ 1409 | CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ 1410 | CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ 1411 | CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ 1412 | CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ 1413 | CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ 1414 | CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ 1415 | CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ 1416 | CONFIG.PSU__GPIO_EMIO_WIDTH {1} \ 1417 | CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \ 1418 | CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \ 1419 | CONFIG.PSU__GPU_PP0__POWER__ON {0} \ 1420 | CONFIG.PSU__GPU_PP1__POWER__ON {0} \ 1421 | CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \ 1422 | CONFIG.PSU__GT__LINK_SPEED {HBR} \ 1423 | CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ 1424 | CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ 1425 | CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ 1426 | CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \ 1427 | CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \ 1428 | CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \ 1429 | CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \ 1430 | CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \ 1431 | CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \ 1432 | CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ 1433 | CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ 1434 | CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ 1435 | CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ 1436 | CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ 1437 | CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ 1438 | CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ 1439 | CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ 1440 | CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ 1441 | CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ 1442 | CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ 1443 | CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ 1444 | CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \ 1445 | CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ 1446 | CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \ 1447 | CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ 1448 | CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \ 1449 | CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ 1450 | CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \ 1451 | CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999001} \ 1452 | CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.999001} \ 1453 | CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ 1454 | CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \ 1455 | CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \ 1456 | CONFIG.PSU__IRQ_P2F_AMS__INT {0} \ 1457 | CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \ 1458 | CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \ 1459 | CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \ 1460 | CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \ 1461 | CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \ 1462 | CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \ 1463 | CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \ 1464 | CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \ 1465 | CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \ 1466 | CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \ 1467 | CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \ 1468 | CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \ 1469 | CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \ 1470 | CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \ 1471 | CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \ 1472 | CONFIG.PSU__IRQ_P2F_CSU__INT {0} \ 1473 | CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \ 1474 | CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \ 1475 | CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \ 1476 | CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \ 1477 | CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \ 1478 | CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \ 1479 | CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \ 1480 | CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \ 1481 | CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \ 1482 | CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \ 1483 | CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \ 1484 | CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \ 1485 | CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \ 1486 | CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \ 1487 | CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \ 1488 | CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \ 1489 | CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ 1490 | CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ 1491 | CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \ 1492 | CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ 1493 | CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ 1494 | CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ 1495 | CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ 1496 | CONFIG.PSU__IRQ_P2F_NAND__INT {0} \ 1497 | CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \ 1498 | CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \ 1499 | CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \ 1500 | CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \ 1501 | CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \ 1502 | CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \ 1503 | CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \ 1504 | CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \ 1505 | CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \ 1506 | CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \ 1507 | CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \ 1508 | CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \ 1509 | CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \ 1510 | CONFIG.PSU__IRQ_P2F_SATA__INT {0} \ 1511 | CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \ 1512 | CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \ 1513 | CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \ 1514 | CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \ 1515 | CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \ 1516 | CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \ 1517 | CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \ 1518 | CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \ 1519 | CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \ 1520 | CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \ 1521 | CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \ 1522 | CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \ 1523 | CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \ 1524 | CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \ 1525 | CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \ 1526 | CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \ 1527 | CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \ 1528 | CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \ 1529 | CONFIG.PSU__IRQ_P2F_UART0__INT {0} \ 1530 | CONFIG.PSU__IRQ_P2F_UART1__INT {0} \ 1531 | CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \ 1532 | CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \ 1533 | CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \ 1534 | CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \ 1535 | CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \ 1536 | CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \ 1537 | CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \ 1538 | CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \ 1539 | CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \ 1540 | CONFIG.PSU__L2_BANK0__POWER__ON {1} \ 1541 | CONFIG.PSU__LPDMA0_COHERENCY {0} \ 1542 | CONFIG.PSU__LPDMA1_COHERENCY {0} \ 1543 | CONFIG.PSU__LPDMA2_COHERENCY {0} \ 1544 | CONFIG.PSU__LPDMA3_COHERENCY {0} \ 1545 | CONFIG.PSU__LPDMA4_COHERENCY {0} \ 1546 | CONFIG.PSU__LPDMA5_COHERENCY {0} \ 1547 | CONFIG.PSU__LPDMA6_COHERENCY {0} \ 1548 | CONFIG.PSU__LPDMA7_COHERENCY {0} \ 1549 | CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \ 1550 | CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ 1551 | CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \ 1552 | CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ 1553 | CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ 1554 | CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ 1555 | CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \ 1556 | CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \ 1557 | CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \ 1558 | CONFIG.PSU__NAND_COHERENCY {0} \ 1559 | CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \ 1560 | CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \ 1561 | CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \ 1562 | CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ 1563 | CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \ 1564 | CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \ 1565 | CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \ 1566 | CONFIG.PSU__NUM_FABRIC_RESETS {1} \ 1567 | CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ 1568 | CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ 1569 | CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ 1570 | CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ 1571 | CONFIG.PSU__OVERRIDE_HPX_QOS {0} \ 1572 | CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ 1573 | CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ 1574 | CONFIG.PSU__PCIE__ACS_VIOLATION {0} \ 1575 | CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ 1576 | CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \ 1577 | CONFIG.PSU__PCIE__BAR0_64BIT {0} \ 1578 | CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ 1579 | CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \ 1580 | CONFIG.PSU__PCIE__BAR0_VAL {} \ 1581 | CONFIG.PSU__PCIE__BAR1_64BIT {0} \ 1582 | CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ 1583 | CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \ 1584 | CONFIG.PSU__PCIE__BAR1_VAL {} \ 1585 | CONFIG.PSU__PCIE__BAR2_64BIT {0} \ 1586 | CONFIG.PSU__PCIE__BAR2_ENABLE {0} \ 1587 | CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \ 1588 | CONFIG.PSU__PCIE__BAR2_VAL {} \ 1589 | CONFIG.PSU__PCIE__BAR3_64BIT {0} \ 1590 | CONFIG.PSU__PCIE__BAR3_ENABLE {0} \ 1591 | CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \ 1592 | CONFIG.PSU__PCIE__BAR3_VAL {} \ 1593 | CONFIG.PSU__PCIE__BAR4_64BIT {0} \ 1594 | CONFIG.PSU__PCIE__BAR4_ENABLE {0} \ 1595 | CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \ 1596 | CONFIG.PSU__PCIE__BAR4_VAL {} \ 1597 | CONFIG.PSU__PCIE__BAR5_64BIT {0} \ 1598 | CONFIG.PSU__PCIE__BAR5_ENABLE {0} \ 1599 | CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \ 1600 | CONFIG.PSU__PCIE__BAR5_VAL {} \ 1601 | CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \ 1602 | CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \ 1603 | CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \ 1604 | CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \ 1605 | CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \ 1606 | CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \ 1607 | CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \ 1608 | CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \ 1609 | CONFIG.PSU__PCIE__DEVICE_ID {} \ 1610 | CONFIG.PSU__PCIE__ECRC_CHECK {0} \ 1611 | CONFIG.PSU__PCIE__ECRC_ERR {0} \ 1612 | CONFIG.PSU__PCIE__ECRC_GEN {0} \ 1613 | CONFIG.PSU__PCIE__EROM_ENABLE {0} \ 1614 | CONFIG.PSU__PCIE__EROM_VAL {} \ 1615 | CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \ 1616 | CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \ 1617 | CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \ 1618 | CONFIG.PSU__PCIE__INTX_GENERATION {0} \ 1619 | CONFIG.PSU__PCIE__LANE0__ENABLE {0} \ 1620 | CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ 1621 | CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ 1622 | CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ 1623 | CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \ 1624 | CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \ 1625 | CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \ 1626 | CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \ 1627 | CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \ 1628 | CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \ 1629 | CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \ 1630 | CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \ 1631 | CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \ 1632 | CONFIG.PSU__PCIE__MULTIHEADER {0} \ 1633 | CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \ 1634 | CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \ 1635 | CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \ 1636 | CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \ 1637 | CONFIG.PSU__PCIE__RECEIVER_ERR {0} \ 1638 | CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \ 1639 | CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ 1640 | CONFIG.PSU__PCIE__REVISION_ID {} \ 1641 | CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \ 1642 | CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \ 1643 | CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \ 1644 | CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \ 1645 | CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \ 1646 | CONFIG.PSU__PCIE__VENDOR_ID {} \ 1647 | CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \ 1648 | CONFIG.PSU__PL_CLK0_BUF {TRUE} \ 1649 | CONFIG.PSU__PL_CLK1_BUF {FALSE} \ 1650 | CONFIG.PSU__PL_CLK2_BUF {FALSE} \ 1651 | CONFIG.PSU__PL_CLK3_BUF {FALSE} \ 1652 | CONFIG.PSU__PL__POWER__ON {1} \ 1653 | CONFIG.PSU__PMU_COHERENCY {0} \ 1654 | CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ 1655 | CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ 1656 | CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ 1657 | CONFIG.PSU__PMU__GPI0__ENABLE {0} \ 1658 | CONFIG.PSU__PMU__GPI1__ENABLE {0} \ 1659 | CONFIG.PSU__PMU__GPI2__ENABLE {0} \ 1660 | CONFIG.PSU__PMU__GPI3__ENABLE {0} \ 1661 | CONFIG.PSU__PMU__GPI4__ENABLE {0} \ 1662 | CONFIG.PSU__PMU__GPI5__ENABLE {0} \ 1663 | CONFIG.PSU__PMU__GPO0__ENABLE {1} \ 1664 | CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ 1665 | CONFIG.PSU__PMU__GPO1__ENABLE {1} \ 1666 | CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ 1667 | CONFIG.PSU__PMU__GPO2__ENABLE {1} \ 1668 | CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ 1669 | CONFIG.PSU__PMU__GPO2__POLARITY {low} \ 1670 | CONFIG.PSU__PMU__GPO3__ENABLE {1} \ 1671 | CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ 1672 | CONFIG.PSU__PMU__GPO3__POLARITY {low} \ 1673 | CONFIG.PSU__PMU__GPO4__ENABLE {1} \ 1674 | CONFIG.PSU__PMU__GPO4__IO {MIO 36} \ 1675 | CONFIG.PSU__PMU__GPO4__POLARITY {low} \ 1676 | CONFIG.PSU__PMU__GPO5__ENABLE {1} \ 1677 | CONFIG.PSU__PMU__GPO5__IO {MIO 37} \ 1678 | CONFIG.PSU__PMU__GPO5__POLARITY {low} \ 1679 | CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ 1680 | CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ 1681 | CONFIG.PSU__PRESET_APPLIED {1} \ 1682 | CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ 1683 | CONFIG.PSU__PROTECTION__DEBUG {0} \ 1684 | CONFIG.PSU__PROTECTION__ENABLE {0} \ 1685 | CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ 1686 | CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \ 1687 | CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ 1688 | CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ 1689 | CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \ 1690 | CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ 1691 | CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ 1692 | CONFIG.PSU__PROTECTION__SLAVES { \ 1693 | LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1 \ 1694 | } \ 1695 | CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \ 1696 | CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ 1697 | CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \ 1698 | CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \ 1699 | CONFIG.PSU__QSPI_COHERENCY {0} \ 1700 | CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ 1701 | CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ 1702 | CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ 1703 | CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ 1704 | CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ 1705 | CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ 1706 | CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ 1707 | CONFIG.PSU__REPORT__DBGLOG {0} \ 1708 | CONFIG.PSU__RPU_COHERENCY {0} \ 1709 | CONFIG.PSU__RPU__POWER__ON {1} \ 1710 | CONFIG.PSU__SATA__LANE0__ENABLE {0} \ 1711 | CONFIG.PSU__SATA__LANE1__ENABLE {1} \ 1712 | CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ 1713 | CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ 1714 | CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ 1715 | CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk3} \ 1716 | CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ 1717 | CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \ 1718 | CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \ 1719 | CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \ 1720 | CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \ 1721 | CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \ 1722 | CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \ 1723 | CONFIG.PSU__SD0_COHERENCY {0} \ 1724 | CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \ 1725 | CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \ 1726 | CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \ 1727 | CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \ 1728 | CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \ 1729 | CONFIG.PSU__SD0__RESET__ENABLE {0} \ 1730 | CONFIG.PSU__SD1_COHERENCY {0} \ 1731 | CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ 1732 | CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \ 1733 | CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ 1734 | CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ 1735 | CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ 1736 | CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \ 1737 | CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ 1738 | CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ 1739 | CONFIG.PSU__SD1__RESET__ENABLE {0} \ 1740 | CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ 1741 | CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \ 1742 | CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \ 1743 | CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \ 1744 | CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \ 1745 | CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \ 1746 | CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \ 1747 | CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ 1748 | CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \ 1749 | CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \ 1750 | CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ 1751 | CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ 1752 | CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \ 1753 | CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ 1754 | CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ 1755 | CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ 1756 | CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \ 1757 | CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ 1758 | CONFIG.PSU__TCM0A__POWER__ON {1} \ 1759 | CONFIG.PSU__TCM0B__POWER__ON {1} \ 1760 | CONFIG.PSU__TCM1A__POWER__ON {1} \ 1761 | CONFIG.PSU__TCM1B__POWER__ON {1} \ 1762 | CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \ 1763 | CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \ 1764 | CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \ 1765 | CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \ 1766 | CONFIG.PSU__TRISTATE__INVERTED {1} \ 1767 | CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ 1768 | CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ 1769 | CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ 1770 | CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \ 1771 | CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ 1772 | CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ 1773 | CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ 1774 | CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \ 1775 | CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ 1776 | CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ 1777 | CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ 1778 | CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \ 1779 | CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ 1780 | CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ 1781 | CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ 1782 | CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \ 1783 | CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ 1784 | CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \ 1785 | CONFIG.PSU__UART0__BAUD_RATE {115200} \ 1786 | CONFIG.PSU__UART0__MODEM__ENABLE {0} \ 1787 | CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ 1788 | CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ 1789 | CONFIG.PSU__UART1__BAUD_RATE {115200} \ 1790 | CONFIG.PSU__UART1__MODEM__ENABLE {0} \ 1791 | CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ 1792 | CONFIG.PSU__UART1__PERIPHERAL__IO {EMIO} \ 1793 | CONFIG.PSU__USB0_COHERENCY {0} \ 1794 | CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ 1795 | CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ 1796 | CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ 1797 | CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ 1798 | CONFIG.PSU__USB0__RESET__ENABLE {0} \ 1799 | CONFIG.PSU__USB1_COHERENCY {0} \ 1800 | CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \ 1801 | CONFIG.PSU__USB1__RESET__ENABLE {0} \ 1802 | CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ 1803 | CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \ 1804 | CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ 1805 | CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ 1806 | CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ 1807 | CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \ 1808 | CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \ 1809 | CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ 1810 | CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ 1811 | CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \ 1812 | CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \ 1813 | CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \ 1814 | CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \ 1815 | CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \ 1816 | CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \ 1817 | CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \ 1818 | CONFIG.PSU__USE__ADMA {0} \ 1819 | CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \ 1820 | CONFIG.PSU__USE__AUDIO {0} \ 1821 | CONFIG.PSU__USE__CLK {0} \ 1822 | CONFIG.PSU__USE__CLK0 {0} \ 1823 | CONFIG.PSU__USE__CLK1 {0} \ 1824 | CONFIG.PSU__USE__CLK2 {0} \ 1825 | CONFIG.PSU__USE__CLK3 {0} \ 1826 | CONFIG.PSU__USE__CROSS_TRIGGER {0} \ 1827 | CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \ 1828 | CONFIG.PSU__USE__DEBUG__TEST {0} \ 1829 | CONFIG.PSU__USE__EVENT_RPU {0} \ 1830 | CONFIG.PSU__USE__FABRIC__RST {1} \ 1831 | CONFIG.PSU__USE__FTM {0} \ 1832 | CONFIG.PSU__USE__GDMA {0} \ 1833 | CONFIG.PSU__USE__IRQ {0} \ 1834 | CONFIG.PSU__USE__IRQ0 {1} \ 1835 | CONFIG.PSU__USE__IRQ1 {0} \ 1836 | CONFIG.PSU__USE__M_AXI_GP0 {1} \ 1837 | CONFIG.PSU__USE__M_AXI_GP1 {1} \ 1838 | CONFIG.PSU__USE__M_AXI_GP2 {0} \ 1839 | CONFIG.PSU__USE__PROC_EVENT_BUS {0} \ 1840 | CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \ 1841 | CONFIG.PSU__USE__RST0 {0} \ 1842 | CONFIG.PSU__USE__RST1 {0} \ 1843 | CONFIG.PSU__USE__RST2 {0} \ 1844 | CONFIG.PSU__USE__RST3 {0} \ 1845 | CONFIG.PSU__USE__RTC {0} \ 1846 | CONFIG.PSU__USE__STM {0} \ 1847 | CONFIG.PSU__USE__S_AXI_ACE {0} \ 1848 | CONFIG.PSU__USE__S_AXI_ACP {0} \ 1849 | CONFIG.PSU__USE__S_AXI_GP0 {1} \ 1850 | CONFIG.PSU__USE__S_AXI_GP1 {0} \ 1851 | CONFIG.PSU__USE__S_AXI_GP2 {0} \ 1852 | CONFIG.PSU__USE__S_AXI_GP3 {0} \ 1853 | CONFIG.PSU__USE__S_AXI_GP4 {0} \ 1854 | CONFIG.PSU__USE__S_AXI_GP5 {0} \ 1855 | CONFIG.PSU__USE__S_AXI_GP6 {0} \ 1856 | CONFIG.PSU__USE__USB3_0_HUB {0} \ 1857 | CONFIG.PSU__USE__USB3_1_HUB {0} \ 1858 | CONFIG.PSU__USE__VIDEO {0} \ 1859 | CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \ 1860 | CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \ 1861 | CONFIG.QSPI_BOARD_INTERFACE {custom} \ 1862 | CONFIG.SATA_BOARD_INTERFACE {custom} \ 1863 | CONFIG.SD0_BOARD_INTERFACE {custom} \ 1864 | CONFIG.SD1_BOARD_INTERFACE {custom} \ 1865 | CONFIG.SPI0_BOARD_INTERFACE {custom} \ 1866 | CONFIG.SPI1_BOARD_INTERFACE {custom} \ 1867 | CONFIG.SUBPRESET1 {Custom} \ 1868 | CONFIG.SUBPRESET2 {Custom} \ 1869 | CONFIG.SWDT0_BOARD_INTERFACE {custom} \ 1870 | CONFIG.SWDT1_BOARD_INTERFACE {custom} \ 1871 | CONFIG.TRACE_BOARD_INTERFACE {custom} \ 1872 | CONFIG.TTC0_BOARD_INTERFACE {custom} \ 1873 | CONFIG.TTC1_BOARD_INTERFACE {custom} \ 1874 | CONFIG.TTC2_BOARD_INTERFACE {custom} \ 1875 | CONFIG.TTC3_BOARD_INTERFACE {custom} \ 1876 | CONFIG.UART0_BOARD_INTERFACE {custom} \ 1877 | CONFIG.UART1_BOARD_INTERFACE {custom} \ 1878 | CONFIG.USB0_BOARD_INTERFACE {custom} \ 1879 | CONFIG.USB1_BOARD_INTERFACE {custom} \ 1880 | ] $zynq_ultra_ps_e_0 1881 | 1882 | # Create interface connections 1883 | connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins tx_fifo/S_AXIS] 1884 | connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_0/M_AXI_MM2S] [get_bd_intf_pins axi_smc/S00_AXI] 1885 | connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_0/M_AXI_S2MM] [get_bd_intf_pins axi_smc/S01_AXI] 1886 | connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HPC0_FPD] 1887 | connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins cmac_usplus_0/axis_tx] [get_bd_intf_pins tx_fifo/M_AXIS] 1888 | connect_bd_intf_net -intf_net [get_bd_intf_nets axis_data_fifo_0_M_AXIS] [get_bd_intf_pins system_ila_0/SLOT_0_AXIS] [get_bd_intf_pins tx_fifo/M_AXIS] 1889 | connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] [get_bd_intf_pins rx_fifo/M_AXIS] 1890 | connect_bd_intf_net -intf_net cmac_usplus_0_axis_rx [get_bd_intf_pins cmac_usplus_0/axis_rx] [get_bd_intf_pins rx_fifo/S_AXIS] 1891 | connect_bd_intf_net -intf_net [get_bd_intf_nets cmac_usplus_0_axis_rx] [get_bd_intf_pins rx_fifo/S_AXIS] [get_bd_intf_pins system_ila_1/SLOT_0_AXIS] 1892 | connect_bd_intf_net -intf_net cmac_usplus_0_gt_serial_port [get_bd_intf_ports gt_rtl] [get_bd_intf_pins cmac_usplus_0/gt_serial_port] 1893 | connect_bd_intf_net -intf_net diff_clock_rtl_1 [get_bd_intf_ports diff_clock_rtl] [get_bd_intf_pins cmac_usplus_0/gt_ref_clk] 1894 | connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI] 1895 | connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins cmac_usplus_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] 1896 | connect_bd_intf_net -intf_net [get_bd_intf_nets ps8_0_axi_periph_M01_AXI] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI] [get_bd_intf_pins system_ila_2/SLOT_0_AXI] 1897 | connect_bd_intf_net -intf_net ps8_0_axi_periph_M02_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins ps8_0_axi_periph/M02_AXI] 1898 | connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD] 1899 | connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM1_FPD [get_bd_intf_pins ps8_0_axi_periph/S01_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM1_FPD] 1900 | 1901 | # Create port connections 1902 | connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins xlconcat_0/In0] 1903 | connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins axi_dma_0/s2mm_introut] [get_bd_pins xlconcat_0/In1] 1904 | connect_bd_net -net axi_intc_0_irq [get_bd_pins axi_intc_0/irq] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq0] 1905 | connect_bd_net -net cmac_usplus_0_gt_rxusrclk2 [get_bd_pins cmac_usplus_0/gt_rxusrclk2] [get_bd_pins cmac_usplus_0/rx_clk] [get_bd_pins rx_fifo/s_axis_aclk] [get_bd_pins system_ila_1/clk] [get_bd_pins vio_0/clk] 1906 | connect_bd_net -net cmac_usplus_0_gt_txusrclk2 [get_bd_pins cmac_usplus_0/gt_txusrclk2] [get_bd_pins system_ila_0/clk] [get_bd_pins tx_fifo/m_axis_aclk] 1907 | connect_bd_net -net cmac_usplus_0_stat_rx_aligned [get_bd_pins cmac_usplus_0/stat_rx_aligned] [get_bd_pins vio_0/probe_in0] 1908 | connect_bd_net -net cmac_usplus_0_usr_rx_reset [get_bd_pins cmac_usplus_0/usr_rx_reset] [get_bd_pins util_vector_logic1/Op1] 1909 | connect_bd_net -net qsfp1_intl_1 [get_bd_ports qsfp1_intl] [get_bd_pins vio_2/probe_in0] 1910 | connect_bd_net -net qsp1_modprsl_1 [get_bd_ports qsfp1_modprsl] [get_bd_pins vio_2/probe_in1] 1911 | connect_bd_net -net rst_ps8_0_99M_peripheral_aresetn [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/M02_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins ps8_0_axi_periph/S01_ARESETN] [get_bd_pins rst_ps8_0_99M/peripheral_aresetn] [get_bd_pins system_ila_2/resetn] [get_bd_pins tx_fifo/s_axis_aresetn] 1912 | connect_bd_net -net rst_ps8_0_99M_peripheral_reset [get_bd_pins cmac_usplus_0/s_axi_sreset] [get_bd_pins cmac_usplus_0/sys_reset] [get_bd_pins rst_ps8_0_99M/peripheral_reset] [get_bd_pins vio_1/probe_in0] 1913 | connect_bd_net -net util_vector_logic1_Res [get_bd_pins rx_fifo/s_axis_aresetn] [get_bd_pins util_vector_logic1/Res] 1914 | connect_bd_net -net util_vector_logic3_Res [get_bd_pins cmac_usplus_0/core_drp_reset] [get_bd_pins cmac_usplus_0/core_rx_reset] [get_bd_pins cmac_usplus_0/core_tx_reset] [get_bd_pins cmac_usplus_0/drp_clk] [get_bd_pins cmac_usplus_0/gtwiz_reset_rx_datapath] [get_bd_pins cmac_usplus_0/gtwiz_reset_tx_datapath] [get_bd_pins cmac_usplus_0/pm_tick] [get_bd_pins xlconstant_0/dout] 1915 | connect_bd_net -net xlconcat_0_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins xlconcat_0/dout] 1916 | connect_bd_net -net xlconstant_1_dout [get_bd_pins system_ila_0/resetn] [get_bd_pins system_ila_1/resetn] [get_bd_pins xlconstant_1/dout] 1917 | connect_bd_net -net xlconstant_2_dout [get_bd_ports qsfp1_modsell] [get_bd_ports qsfp1_resetl] [get_bd_pins xlconstant_2/dout] 1918 | connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins cmac_usplus_0/init_clk] [get_bd_pins cmac_usplus_0/s_axi_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/M02_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins ps8_0_axi_periph/S01_ACLK] [get_bd_pins rst_ps8_0_99M/slowest_sync_clk] [get_bd_pins rx_fifo/m_axis_aclk] [get_bd_pins system_ila_2/clk] [get_bd_pins tx_fifo/s_axis_aclk] [get_bd_pins vio_1/clk] [get_bd_pins vio_2/clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihpc0_fpd_aclk] 1919 | connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_99M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] 1920 | 1921 | # Create address segments 1922 | assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force 1923 | assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_DDR_LOW] -force 1924 | assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force 1925 | assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP0/HPC0_QSPI] -force 1926 | assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] -force 1927 | assign_bd_address -offset 0xA0020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force 1928 | assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmac_usplus_0/s_axi/Reg] -force 1929 | 1930 | 1931 | # Restore current instance 1932 | current_bd_instance $oldCurInst 1933 | 1934 | validate_bd_design 1935 | save_bd_design 1936 | } 1937 | # End of create_root_design() 1938 | 1939 | 1940 | ################################################################## 1941 | # MAIN FLOW 1942 | ################################################################## 1943 | 1944 | create_root_design "" 1945 | 1946 | 1947 | --------------------------------------------------------------------------------