├── .DS_Store ├── clk_div.v ├── 7seg_Dev_IO.v ├── mips_ps2_vga.s ├── Ext_32.v ├── mux2to1_32.v ├── REG32.v ├── led_Dev_IO.v ├── 7seg_Dev.v ├── Anti_jitter.v ├── mux4to1_32.v ├── mux4to1_5.v ├── Counter_3channel.v ├── Regs.v ├── nor32.v ├── or32.v ├── SignalExt_32.v ├── and32.v ├── srl32.v ├── xor32.v ├── or_bit_32.v ├── ADC32.v ├── clk_25hmz.v ├── mux8to1_32.v ├── ALU.v ├── forREG.v ├── forALU.v ├── testfortop.v ├── muliti_cycle_cpu.v ├── ps2_keyboard.v ├── forMCPU.v ├── vgac.v ├── forDatapath.v ├── forBUS.v ├── Datapath.v ├── ctrl.v ├── MIO_BUS.v ├── Top.v └── BULLET.s /.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JeremyJiWZ/FPGA/HEAD/.DS_Store -------------------------------------------------------------------------------- /clk_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JeremyJiWZ/FPGA/HEAD/clk_div.v -------------------------------------------------------------------------------- /7seg_Dev_IO.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JeremyJiWZ/FPGA/HEAD/7seg_Dev_IO.v -------------------------------------------------------------------------------- /mips_ps2_vga.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JeremyJiWZ/FPGA/HEAD/mips_ps2_vga.s -------------------------------------------------------------------------------- /Ext_32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Ext_32(input [15:0] imm_16,output[31:0] Imm_32); 3 | assign Imm_32={{16{imm_16[15]}},imm_16}; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /mux2to1_32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module mux2to1_32(input sel,input [31:0]a, input [31:0]b, output reg [31:0]o); 3 | 4 | always @(*) begin 5 | case (sel) 6 | 1'b0 : begin o <= b; end 7 | 1'b1 : begin o <= a; end 8 | endcase 9 | end 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /REG32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module REG32(input clk,input rst,input CE,input [31:0]D,output [31:0]Q 3 | ); 4 | reg [31:0]REG; 5 | assign Q = REG; 6 | always @(posedge clk or posedge rst) 7 | begin if(rst==1) REG<=0; 8 | else if(CE==1) REG<=D; 9 | end 10 | 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /led_Dev_IO.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module led_Dev_IO(input clk, 3 | input rst, 4 | input GPIOf0000000_we, 5 | input [31:0] Peripheral_in, 6 | output [1:0] counter_set, 7 | output [7:0] led_out, 8 | output [21:0] GPIOf0 9 | ); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /7seg_Dev.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module seven_seg_dev(input[31:0] disp_num, 3 | input [1:0] SW, 4 | input flash_clk, 5 | input [1:0] Scanning, 6 | input [3:0] pointing, 7 | input [3:0] blinking, 8 | output[3:0] AN, 9 | output [7:0] SEGMENT 10 | ); 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /Anti_jitter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Anti_jitter(input wire clk, 3 | input wire [3:0] button, 4 | input wire [7:0] SW, 5 | output reg [3:0]button_out, 6 | output reg [3:0]button_pulse, 7 | output reg [7:0] SW_OK, 8 | output reg rst 9 | 10 | ); 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /mux4to1_32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module mux4to1_32(input [1:0]sel,input [31:0]a, input [31:0]b,input [31:0]c, input [31:0]d, output reg [31:0]o); 3 | always @(*) begin 4 | case (sel) 5 | 2'b00 : begin o = a; end 6 | 2'b01 : begin o = b; end 7 | 2'b10 : begin o = c; end 8 | 2'b11 : begin o = d; end 9 | endcase 10 | end 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /mux4to1_5.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module mux4to1_5(input [1:0]sel,input [4:0]a, input [4:0]b,input [4:0]c,input [4:0]d, output reg [4:0]o); 3 | 4 | always @(*) begin 5 | case (sel) 6 | 2'b00 : begin o <= a; end 7 | 2'b01 : begin o <= b; end 8 | 2'b10 : begin o <= c; end 9 | 2'b11 : begin o <= d; end 10 | endcase 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /Counter_3channel.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Counter_x(input clk, 3 | input rst, 4 | input clk0, 5 | input clk1, 6 | input clk2, 7 | input counter_we, 8 | input [31:0] counter_val, 9 | input [1:0] counter_ch, 10 | 11 | output counter0_OUT, 12 | output counter1_OUT, 13 | output counter2_OUT, 14 | output [31:0] counter_out 15 | 16 | ); 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /Regs.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Regs(input clk,rst,L_S, 3 | input [4:0] R_addr_A,R_addr_B,Wt_addr, 4 | input [31:0] Wt_data, 5 | output [31:0] rdata_A,rdata_B 6 | ); 7 | reg [31:0]register[1:31]; 8 | integer i; 9 | assign rdata_A=(R_addr_A==0)?0:register[R_addr_A]; 10 | assign rdata_B=(R_addr_B==0)?0:register[R_addr_B]; 11 | 12 | always @(posedge clk or posedge rst) 13 | begin if(rst==1) for(i=1;i<32;i=i+1) register[i]<=0; 14 | else if((Wt_addr!=0)&&(L_S==1)) register[Wt_addr]<=Wt_data; 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /nor32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:33:57 04/10/2015 7 | // Design Name: 8 | // Module Name: nor32 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module nor32(input [31:0]A,input [31:0]B,output [31:0]res 22 | ); 23 | assign res=~(A|B); 24 | 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /or32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:20:54 04/10/2015 7 | // Design Name: 8 | // Module Name: or32 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module or32(input [31:0]A,input [31:0]B,output [31:0]res 22 | ); 23 | assign res=A|B; 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /SignalExt_32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12:56:07 03/18/2015 7 | // Design Name: 8 | // Module Name: SignalExt_32 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module SignalExt_32(input S,output [31:0]So 22 | ); 23 | assign So={32{S}}; 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /and32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:18:24 04/10/2015 7 | // Design Name: 8 | // Module Name: and32 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module and32(input [31:0]A,input [31:0]B,output [31:0]res 22 | ); 23 | assign res=A&B; 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /srl32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:34:30 04/10/2015 7 | // Design Name: 8 | // Module Name: srl32 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module srl32(input [31:0]A,input [31:0]B,output [31:0]res 22 | ); 23 | assign res=B>>A; 24 | 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /xor32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:32:06 04/10/2015 7 | // Design Name: 8 | // Module Name: xor32 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module xor32(input [31:0]A,input [31:0]B,output [31:0]res 22 | ); 23 | assign res=A^B; 24 | 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /or_bit_32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12:58:09 03/18/2015 7 | // Design Name: 8 | // Module Name: or_bit_32 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module or_bit_32( 22 | input[31:0] A, 23 | output o 24 | ); 25 | 26 | assign o=|A[31:0]; 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /ADC32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:23:00 04/10/2015 7 | // Design Name: 8 | // Module Name: ADC32 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ADC32(input [31:0]A,input [31:0]B,input C0,output [32:0]S 22 | ); 23 | assign B0=C0^1'b0; 24 | assign S={1'b0,A}+{B0,B}+C0; 25 | 26 | endmodule 27 | 28 | -------------------------------------------------------------------------------- /clk_25hmz.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:16:56 08/27/2015 7 | // Design Name: 8 | // Module Name: clk_25mhz 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module clk_25mhz(input clk_50mhz, output reg clk_25mhz); 22 | reg cnt; 23 | always@(posedge clk_50mhz) begin 24 | cnt=~cnt; 25 | if (cnt) 26 | clk_25mhz=~clk_25mhz; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /mux8to1_32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 00:59:48 12/01/2014 7 | // Design Name: 8 | // Module Name: mux8to1_32 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module mux8to1_32(input [2:0]sel,input [31:0] x0, input [31:0]x1,input [31:0]x2 ,input [31:0]x3, 22 | input [31:0]x4 ,input [31:0]x5,input [31:0]x6,input [31:0]x7,output reg [31:0]o); 23 | 24 | always @(*) begin 25 | case (sel[2:0]) 26 | 3'b000 : begin o <= x0; end 27 | 3'b001 : begin o <= x1; end 28 | 3'b010 : begin o <= x2; end 29 | 3'b011 : begin o <= x3; end 30 | 3'b100 : begin o <= x4; end 31 | 3'b101 : begin o <= x5; end 32 | 3'b110 : begin o <= x6; end 33 | 3'b111 : begin o <= x7; end 34 | endcase 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /ALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ALU( 4 | input [2:0]ALU_operation, 5 | input [31:0]A, 6 | input [31:0]B, 7 | output [31:0]res, 8 | output zero, 9 | output overflow 10 | ); 11 | wire [31:0]X[7:0]; 12 | wire [32:0]S; 13 | wire [31:0]So; 14 | wire [31:0]B0; 15 | assign X[2]=S[31:0]; 16 | assign X[6]=S[31:0]; 17 | assign X[7]={31'h00000000,S[31]}; 18 | and32 U1(.A(A[31:0]), 19 | .B(B[31:0]), 20 | .res(X[0])); 21 | or32 U2(.A(A[31:0]), 22 | .B(B[31:0]), 23 | .res(X[1])); 24 | ADC32 U3(.C0(ALU_operation[2]), 25 | .A(A[31:0]), 26 | .B(B0[31:0]), 27 | .S(S[32:0])); 28 | xor32 U4(.A(A[31:0]), 29 | .B(B[31:0]), 30 | .res(X[3])); 31 | nor32 U5(.A(A[31:0]), 32 | .B(B[31:0]), 33 | .res(X[4])); 34 | srl32 U6(.A(A[31:0]), 35 | .B(B[31:0]), 36 | .res(X[5])); 37 | xor32 U7(.A(So[31:0]), 38 | .B(B[31:0]), 39 | .res(B0[31:0])); 40 | SignalExt_32 U8(.S(ALU_operation[2]), 41 | .So(So[31:0])); 42 | mux8to1_32 U9(.sel(ALU_operation[2:0]), 43 | .x0(X[0]), 44 | .x1(X[1]), 45 | .x2(X[2]), 46 | .x3(X[3]), 47 | .x4(X[4]), 48 | .x5(X[5]), 49 | .x6(X[6]), 50 | .x7(X[7]), 51 | .o(res[31:0])); 52 | or_bit_32 U10(.A(res[31:0]), 53 | .o(zero)); 54 | endmodule 55 | -------------------------------------------------------------------------------- /forREG.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 23:44:27 06/08/2015 8 | // Design Name: REG32 9 | // Module Name: C:/Users/Apple/Desktop/Project3/project3.1/forREG.v 10 | // Project Name: project3 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: REG32 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module forREG; 26 | 27 | // Inputs 28 | reg clk; 29 | reg rst; 30 | reg CE; 31 | reg [31:0] D; 32 | 33 | // Outputs 34 | wire [31:0] Q; 35 | 36 | // Instantiate the Unit Under Test (UUT) 37 | REG32 uut ( 38 | .clk(clk), 39 | .rst(rst), 40 | .CE(CE), 41 | .D(D), 42 | .Q(Q) 43 | ); 44 | 45 | initial begin 46 | // Initialize Inputs 47 | clk = 0; 48 | rst = 0; 49 | CE = 0; 50 | D = 0; 51 | 52 | // Wait 100 ns for global reset to finish 53 | #100; 54 | rst=1; 55 | #100; 56 | rst=0; 57 | #100; 58 | D=1; 59 | CE=1; 60 | #100; 61 | clk=1; 62 | // Add stimulus here 63 | 64 | end 65 | 66 | endmodule 67 | 68 | -------------------------------------------------------------------------------- /forALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 14:40:43 08/25/2015 8 | // Design Name: ALU 9 | // Module Name: D:/3130100658/poroject4/forALU.v 10 | // Project Name: project3 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: ALU 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module forALU; 26 | 27 | // Inputs 28 | reg [2:0] ALU_operation; 29 | reg [31:0] A; 30 | reg [31:0] B; 31 | 32 | // Outputs 33 | wire [31:0] res; 34 | wire zero; 35 | wire overflow; 36 | 37 | // Instantiate the Unit Under Test (UUT) 38 | ALU uut ( 39 | .ALU_operation(ALU_operation), 40 | .A(A), 41 | .B(B), 42 | .res(res), 43 | .zero(zero), 44 | .overflow(overflow) 45 | ); 46 | 47 | initial begin 48 | // Initialize Inputs 49 | ALU_operation = 0; 50 | A = 0; 51 | B = 0; 52 | 53 | // Wait 100 ns for global reset to finish 54 | #100; 55 | 56 | // Add stimulus here 57 | A=6; 58 | B=4; 59 | ALU_operation=7; 60 | #100; 61 | A=4; 62 | B=6; 63 | #100; 64 | A=32'hfffffff0; 65 | B=0; 66 | #100; 67 | A=64; 68 | B=576; 69 | #100; 70 | A=576; 71 | B=64; 72 | #100; 73 | A=0;//down 74 | B=416; 75 | #100; 76 | A=16; 77 | #100; 78 | A=32; 79 | #100; 80 | A=16;//right 81 | B=576; 82 | #100; 83 | end 84 | 85 | endmodule 86 | 87 | -------------------------------------------------------------------------------- /testfortop.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 15:11:18 09/02/2015 8 | // Design Name: Top 9 | // Module Name: D:/3130100658/poroject4/testfortop.v 10 | // Project Name: project3 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: Top 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module testfortop; 26 | 27 | // Inputs 28 | reg [3:0] BTN; 29 | reg [7:0] SW; 30 | reg clk_50mhz; 31 | reg PS2_Data; 32 | reg PS2_clk; 33 | 34 | // Outputs 35 | wire [3:0] AN; 36 | wire [7:0] SEGMENT; 37 | wire [7:0] LED; 38 | wire [2:0] Red; 39 | wire [2:0] Green; 40 | wire [1:0] Blue; 41 | wire vsync; 42 | wire hsync; 43 | 44 | // Instantiate the Unit Under Test (UUT) 45 | Top uut ( 46 | .BTN(BTN), 47 | .SW(SW), 48 | .clk_50mhz(clk_50mhz), 49 | .PS2_Data(PS2_Data), 50 | .PS2_clk(PS2_clk), 51 | .AN(AN), 52 | .SEGMENT(SEGMENT), 53 | .LED(LED), 54 | .Red(Red), 55 | .Green(Green), 56 | .Blue(Blue), 57 | .vsync(vsync), 58 | .hsync(hsync) 59 | ); 60 | 61 | initial begin 62 | // Initialize Inputs 63 | BTN = 0; 64 | SW = 0; 65 | clk_50mhz = 0; 66 | PS2_Data = 0; 67 | PS2_clk = 0; 68 | 69 | // Wait 100 ns for global reset to finish 70 | #100; 71 | 72 | // Add stimulus here 73 | 74 | end 75 | always begin 76 | clk_50mhz=~clk_50mhz; 77 | #10; 78 | end 79 | 80 | endmodule 81 | 82 | -------------------------------------------------------------------------------- /muliti_cycle_cpu.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module Muliti_CPU(input clk, //muliti_CPU 3 | input reset, 4 | input MIO_ready, 5 | 6 | output[31:0] PC_out, //TEST 7 | output[31:0] inst_out, //TEST 8 | output mem_w, 9 | output[31:0] Addr_out, 10 | output[31:0] Data_out, 11 | input [31:0] Data_in, 12 | output CPU_MIO, 13 | input INT, 14 | output[4:0]state //Test 15 | ); 16 | wire zero,overflow,MemRead,MemWrite; 17 | wire lorD,IRWrite,RegWrite,ALUSrcA,PCWrite,PCWriteCond,Branch; 18 | wire [1:0]RegDst; 19 | wire [1:0]MemtoReg; 20 | wire [1:0]ALUSrcB; 21 | wire [1:0]PCSource; 22 | wire [2:0]ALU_operation; 23 | wire S; 24 | 25 | assign mem_w=(~MemRead)&MemWrite; 26 | 27 | ctrl U11(.clk(clk), 28 | .reset(reset), 29 | .zero(zero), 30 | .overflow(overflow), 31 | .MIO_ready(MIO_ready), 32 | .inst_in(inst_out[31:0]), 33 | .MemRead(MemRead), 34 | .MemWrite(MemWrite), 35 | .CPU_MIO(CPU_MIO), 36 | .lorD(lorD), 37 | .IRWrite(IRWrite), 38 | .RegWrite(RegWrite), 39 | .ALUSrcA(ALUSrcA), 40 | .PCWrite(PCWrite), 41 | .PCWriteCond(PCWriteCond), 42 | .Branch(Branch), 43 | .RegDst(RegDst[1:0]), 44 | .MemtoReg(MemtoReg[1:0]), 45 | .ALUSrcB(ALUSrcB[1:0]), 46 | .PCSource(PCSource[1:0]), 47 | .ALU_operation(ALU_operation[2:0]), 48 | .state_out(state[4:0]), 49 | .S(S)); 50 | Datapath U12(.clk(clk), 51 | .rst(reset), 52 | .MIO_ready(MIO_ready), 53 | .lorD(lorD), 54 | .IRWrite(IRWrite), 55 | .RegWrite(RegWrite), 56 | .ALUSrcA(ALUSrcA), 57 | .PCWrite(PCWrite), 58 | .PCWriteCond(PCWriteCond), 59 | .Branch(Branch), 60 | .RegDst(RegDst[1:0]), 61 | .MemtoReg(MemtoReg[1:0]), 62 | .ALUSrcB(ALUSrcB[1:0]), 63 | .PCSource(PCSource[1:0]), 64 | .ALU_Control(ALU_operation[2:0]), 65 | .Data_in(Data_in[31:0]), 66 | .zero(zero), 67 | .overflow(overflow), 68 | .PC_Current(PC_out[31:0]), 69 | .inst(inst_out[31:0]), 70 | .Data_out(Data_out[31:0]), 71 | .S(S), 72 | .M_addr(Addr_out[31:0])); 73 | endmodule 74 | 75 | 76 | 77 | 78 | -------------------------------------------------------------------------------- /ps2_keyboard.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:22:45 08/26/2015 7 | // Design Name: 8 | // Module Name: ps2_keyboard 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ps2_keyboard (input clk,// 50 MHz 22 | input clrn, //active low 23 | input ps2_clk, // ps2 clock 24 | input ps2_data, // ps2 data 25 | input rdn, // read, active low 26 | output [7:0]data, // 8-bit code 27 | output ready, // code ready 28 | output reg overflow); // fifo overflow 29 | reg [9:0] buffer; // ps2_data bits 30 | reg [7:0] fifo[7:0]; // circular fifo 31 | reg [3:0] count; // count ps2_data bits 32 | reg [2:0] w_ptr,r_ptr; // fifo w/r pointers 33 | reg [1:0] ps2_clk_sync; // for detecting falling edge 34 | 35 | always @ (posedge clk) 36 | ps2_clk_sync <= {ps2_clk_sync[0],ps2_clk}; 37 | wire sampling = ps2_clk_sync[1] &~ps2_clk_sync[0]; // had a falling edge 38 | 39 | always @ (posedge clk) begin 40 | if (!clrn) begin // on reset 41 | count <= 0; // clear count 42 | w_ptr <= 0; // clear w_ptr 43 | r_ptr <= 0; // clear r_ptr 44 | overflow <= 0; // clear overflow 45 | end else if (sampling) begin // if sampling 46 | if (count == 4'd10) begin // if got one frame 47 | if ((buffer[0] == 0) && (ps2_data) && (^buffer[9:1])) begin 48 | if ((w_ptr + 3'b1) != r_ptr) begin 49 | fifo[w_ptr] <= buffer[8:1]; 50 | w_ptr <= w_ptr + 3'b1; // w_ptr++ 51 | end else begin 52 | overflow <= 1; // overflow 53 | end 54 | end 55 | count <= 0; // for next frame 56 | end else begin // else 57 | buffer[count] <= ps2_data; // store ps2_data 58 | count <= count + 4'b1; // count++ 59 | end 60 | end 61 | if (!rdn && ready) begin // on cpu read 62 | r_ptr <= r_ptr + 3'b1; // r_ptr++ 63 | overflow <= 0; // clear overflow 64 | end 65 | end 66 | assign ready = (w_ptr != r_ptr); // fifo is not empty 67 | assign data = fifo[r_ptr]; // code byte 68 | endmodule 69 | -------------------------------------------------------------------------------- /forMCPU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 21:20:41 06/08/2015 8 | // Design Name: Muliti_CPU 9 | // Module Name: C:/Users/Apple/Desktop/Project3/project3.1/forMCPU.v 10 | // Project Name: project3 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: Muliti_CPU 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module forMCPU; 26 | 27 | // Inputs 28 | reg clk; 29 | reg reset; 30 | reg MIO_ready; 31 | reg [31:0] Data_in; 32 | reg INT; 33 | 34 | // Outputs 35 | wire [31:0] PC_out; 36 | wire [31:0] inst_out; 37 | wire mem_w; 38 | wire [31:0] Addr_out; 39 | wire [31:0] Data_out; 40 | wire CPU_MIO; 41 | wire [4:0] state; 42 | 43 | // Instantiate the Unit Under Test (UUT) 44 | Muliti_CPU uut ( 45 | .clk(clk), 46 | .reset(reset), 47 | .MIO_ready(MIO_ready), 48 | .PC_out(PC_out), 49 | .inst_out(inst_out), 50 | .mem_w(mem_w), 51 | .Addr_out(Addr_out), 52 | .Data_out(Data_out), 53 | .Data_in(Data_in), 54 | .CPU_MIO(CPU_MIO), 55 | .INT(INT), 56 | .state(state) 57 | ); 58 | 59 | initial begin 60 | clk = 1; 61 | reset = 0; 62 | Data_in = 0; 63 | MIO_ready = 0; 64 | INT = 0; 65 | #1; 66 | reset = 1; 67 | #1; 68 | reset = 0; 69 | #1; 70 | Data_in=32'b00001000000000000000000000000101; 71 | //j next_pc=14 72 | repeat(3) begin 73 | #1; 74 | clk=1; 75 | #1; 76 | clk = 0; 77 | end 78 | Data_in=32'b00001100000000000000000000000101; 79 | //jal next_pc=14 80 | repeat(4) begin 81 | #1; 82 | clk=1; 83 | #1; 84 | clk = 0; 85 | end 86 | Data_in=32'b00000011111000000000000000001000; 87 | //jr $ra; //next_pc=24 88 | repeat(3) begin 89 | #1; 90 | clk=1; 91 | #1; 92 | clk = 0; 93 | end 94 | Data_in=32'b00000011111000000100100000001001; 95 | //jalr $ra,$t1; //next_pc=24,$t1=28 96 | repeat(3) begin 97 | #1; 98 | clk=1; 99 | #1; 100 | clk = 0; 101 | end 102 | Data_in=32'b00000001001000000000000000001000; 103 | //jr $t1; //next_pc=28 104 | repeat(4) begin 105 | #1; 106 | clk=1; 107 | #1; 108 | clk = 0; 109 | end 110 | end 111 | 112 | 113 | endmodule 114 | 115 | -------------------------------------------------------------------------------- /vgac.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:38:09 08/27/2015 7 | // Design Name: 8 | // Module Name: vgac 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module vgac (input vga_clk, // 25MHz 22 | input clrn, //active low 23 | input [7:0]d_in, // rrr_ggg_bb, pixel 24 | output reg[8:0]row_addr, // pixel ram row address, 480 (512) lines 25 | output reg[9:0]col_addr, // pixel ram col address, 640 (1024) pixels 26 | output reg rdn, // read pixel RAM (active low) 27 | output reg [2:0]r,g, 28 | output reg [1:0]b, // red, green, blue colors, 29 | output reg hs,vs); // horizontal and vertical synchronization 30 | // vgac 31 | // h_count: vga horizontal counter (0-799 pixels) 32 | reg [9:0] h_count; 33 | initial begin h_count = 0; end 34 | always @ (posedge vga_clk or negedge clrn) begin 35 | if (!clrn) begin 36 | h_count <= 10'h0; 37 | end else if (h_count == 10'd799) begin 38 | h_count <= 10'h0; 39 | end else begin 40 | h_count <= h_count + 10'h1; 41 | end 42 | end 43 | // v_count: vga vertical counter (0-524 lines) 44 | reg [9:0] v_count; 45 | initial begin v_count = 0; end 46 | always @ (posedge vga_clk or negedge clrn) begin 47 | if (!clrn) begin 48 | v_count <= 10'h0; 49 | end else if (h_count == 10'd799) begin 50 | if (v_count == 10'd524) begin 51 | v_count <= 10'h0; 52 | end else begin 53 | v_count <= v_count + 10'h1; 54 | end 55 | end 56 | end 57 | // signals, will be latched for outputs 58 | wire [9:0] row = v_count - 10'd35; // pixel ram row address 59 | wire [9:0] col = h_count - 10'd143; // pixel ram col address 60 | wire h_sync = (h_count > 10'd95); // 96 -> 799 61 | wire v_sync = (v_count > 10'd1); // 2 -> 524 62 | wire read = (h_count > 10'd142) && // 143 -> 782 = 63 | (h_count < 10'd783) && // 640 pixels 64 | (v_count > 10'd34) && // 35 -> 514 = 65 | (v_count < 10'd515); // 480 lines 66 | // vga signals 67 | always @ (posedge vga_clk) begin 68 | row_addr <= row[8:0]; // pixel ram row address 69 | col_addr <= col; // pixel ram col address 70 | rdn <= ~read; // read pixel (active low) 71 | hs <= h_sync; // horizontal synch 72 | vs <= v_sync; // vertical synch 73 | r <= rdn ? 3'h0 : d_in[7:5]; // 3-bit red 74 | g <= rdn ? 3'h0 : d_in[4:2]; // 3-bit green 75 | b <= rdn ? 2'h0 : d_in[1:0]; // 2-bit blue 76 | end 77 | endmodule 78 | -------------------------------------------------------------------------------- /forDatapath.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 23:11:29 06/08/2015 8 | // Design Name: Datapath 9 | // Module Name: C:/Users/Apple/Desktop/Project3/project3.1/forDatapath.v 10 | // Project Name: project3 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: Datapath 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module forDatapath; 26 | 27 | // Inputs 28 | reg clk; 29 | reg reset; 30 | reg [1:0] PCSource; 31 | reg lorD; 32 | reg [2:0] ALU_Control; 33 | reg ALUSrcA; 34 | reg RegWrite; 35 | reg [1:0] RegDst; 36 | reg IRWrite; 37 | reg [31:0] Data_in; 38 | reg [1:0] MemtoReg; 39 | reg MIO_ready; 40 | reg [1:0] ALUSrcB; 41 | reg PCWrite; 42 | reg PCWriteCond; 43 | reg Branch; 44 | reg S; 45 | 46 | // Outputs 47 | wire [31:0] PC_Current; 48 | wire [31:0] M_addr; 49 | wire [31:0] Data_out; 50 | wire overflow; 51 | wire zero; 52 | wire [31:0] inst; 53 | 54 | // Instantiate the Unit Under Test (UUT) 55 | Datapath uut ( 56 | .clk(clk), 57 | .rst(reset), 58 | .PCSource(PCSource), 59 | .lorD(lorD), 60 | .ALU_Control(ALU_Control), 61 | .ALUSrcA(ALUSrcA), 62 | .RegWrite(RegWrite), 63 | .RegDst(RegDst), 64 | .IRWrite(IRWrite), 65 | .Data_in(Data_in), 66 | .MemtoReg(MemtoReg), 67 | .MIO_ready(MIO_ready), 68 | .ALUSrcB(ALUSrcB), 69 | .PCWrite(PCWrite), 70 | .PCWriteCond(PCWriteCond), 71 | .Branch(Branch), 72 | .S(S), 73 | .PC_Current(PC_Current), 74 | .M_addr(M_addr), 75 | .Data_out(Data_out), 76 | .overflow(overflow), 77 | .zero(zero), 78 | .inst(inst) 79 | ); 80 | 81 | initial begin 82 | // Initialize Inputs 83 | clk = 0; 84 | reset = 0; 85 | PCSource = 0; 86 | lorD = 0; 87 | ALU_Control = 0; 88 | ALUSrcA = 0; 89 | RegWrite = 0; 90 | RegDst = 0; 91 | IRWrite = 0; 92 | Data_in = 0; 93 | MemtoReg = 0; 94 | MIO_ready = 0; 95 | ALUSrcB = 0; 96 | PCWrite = 0; 97 | PCWriteCond = 0; 98 | Branch = 0; 99 | S = 0; 100 | 101 | // Wait 100 ns for global reset to finish 102 | #100; 103 | reset=1; 104 | #100; 105 | reset=0; 106 | #100; 107 | Data_in=32'b00100000000010011111111111111111; 108 | //addi $t1,$zero,-1; //$t1=ffffffff; 109 | #100; 110 | clk=1; 111 | #100; 112 | IRWrite = 1'b1; 113 | PCWrite = 1'b1; 114 | ALUSrcB=2'b10; 115 | lorD = 1'b1; 116 | ALUSrcA=1; 117 | clk = 0; 118 | #100; 119 | clk=1; 120 | #100; 121 | ALU_Control=3'b010; 122 | clk = 0; 123 | #100; 124 | clk=1; 125 | #100; 126 | clk = 0; 127 | #100; 128 | clk=1; 129 | #100; 130 | clk = 0; 131 | // Add stimulus here 132 | 133 | end 134 | 135 | endmodule 136 | 137 | -------------------------------------------------------------------------------- /forBUS.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 16:21:41 09/04/2015 8 | // Design Name: MIO_BUS 9 | // Module Name: D:/3130100658/poroject4/forBUS.v 10 | // Project Name: project3 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: MIO_BUS 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module forBUS; 26 | 27 | // Inputs 28 | reg clk; 29 | reg rst; 30 | reg mem_w; 31 | reg counter0_out; 32 | reg counter1_out; 33 | reg counter2_out; 34 | reg [3:0] BTN; 35 | reg [7:0] SW; 36 | reg [7:0] led_out; 37 | reg [31:0] Cpu_data2bus; 38 | reg [31:0] ram_data_out; 39 | reg [31:0] addr_bus; 40 | reg [31:0] counter_out; 41 | reg ps2_ready; 42 | reg [7:0] ps2_data; 43 | reg vga_rdn; 44 | reg [9:0] vx; 45 | reg [9:0] vy; 46 | 47 | // Outputs 48 | wire data_ram_we; 49 | wire GPIOf0000000_we; 50 | wire GPIOe0000000_we; 51 | wire counter_we; 52 | wire vram_we; 53 | wire [11:0] ram_addr; 54 | wire [31:0] Cpu_data4bus; 55 | wire [31:0] ram_data_in; 56 | wire [31:0] Peripheral_in; 57 | wire [14:0] vram_addr; 58 | wire [7:0] vram_data_in; 59 | wire ps2_rdn; 60 | 61 | // Instantiate the Unit Under Test (UUT) 62 | MIO_BUS uut ( 63 | .clk(clk), 64 | .rst(rst), 65 | .mem_w(mem_w), 66 | .counter0_out(counter0_out), 67 | .counter1_out(counter1_out), 68 | .counter2_out(counter2_out), 69 | .BTN(BTN), 70 | .SW(SW), 71 | .led_out(led_out), 72 | .Cpu_data2bus(Cpu_data2bus), 73 | .ram_data_out(ram_data_out), 74 | .addr_bus(addr_bus), 75 | .counter_out(counter_out), 76 | .ps2_ready(ps2_ready), 77 | .ps2_data(ps2_data), 78 | .vga_rdn(vga_rdn), 79 | .vx(vx), 80 | .vy(vy), 81 | .data_ram_we(data_ram_we), 82 | .GPIOf0000000_we(GPIOf0000000_we), 83 | .GPIOe0000000_we(GPIOe0000000_we), 84 | .counter_we(counter_we), 85 | .vram_we(vram_we), 86 | .ram_addr(ram_addr), 87 | .Cpu_data4bus(Cpu_data4bus), 88 | .ram_data_in(ram_data_in), 89 | .Peripheral_in(Peripheral_in), 90 | .vram_addr(vram_addr), 91 | .vram_data_in(vram_data_in), 92 | .ps2_rdn(ps2_rdn) 93 | ); 94 | 95 | initial begin 96 | // Initialize Inputs 97 | clk = 0; 98 | rst = 0; 99 | mem_w = 0; 100 | counter0_out = 0; 101 | counter1_out = 0; 102 | counter2_out = 0; 103 | BTN = 0; 104 | SW = 0; 105 | led_out = 0; 106 | Cpu_data2bus = 0; 107 | ram_data_out = 0; 108 | addr_bus = 0; 109 | counter_out = 0; 110 | ps2_ready = 0; 111 | ps2_data = 0; 112 | vga_rdn = 0; 113 | vx = 0; 114 | vy = 0; 115 | 116 | // Wait 100 ns for global reset to finish 117 | #100; 118 | ps2_ready = 1; 119 | ps2_data = 8'h1b; 120 | #100; 121 | // Add stimulus here 122 | addr_bus = 32'hd0000000; 123 | #10; 124 | ps2_data = 0; 125 | 126 | end 127 | always begin 128 | clk=~clk; 129 | #10; 130 | end 131 | 132 | endmodule 133 | 134 | -------------------------------------------------------------------------------- /Datapath.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Datapath( input clk, 4 | input rst, 5 | input [1:0]PCSource, 6 | input lorD, 7 | input [2:0]ALU_Control, 8 | input ALUSrcA, 9 | input RegWrite, 10 | input [1:0]RegDst, 11 | input IRWrite, 12 | input [31:0]Data_in, 13 | input [1:0]MemtoReg, 14 | input MIO_ready, 15 | input [1:0]ALUSrcB, 16 | 17 | input PCWrite, 18 | input PCWriteCond, 19 | input Branch, 20 | input S, 21 | 22 | output [31:0]PC_Current, 23 | output [31:0]M_addr, 24 | output [31:0]Data_out, 25 | 26 | output overflow, 27 | output zero, 28 | output [31:0]inst 29 | 30 | ); 31 | wire [31:0]A; 32 | wire [31:0]B; 33 | wire [31:0]res; 34 | //U1 35 | wire [4:0]Wt_addr; 36 | wire [31:0]Wt_data; 37 | wire [31:0]rdata_A; 38 | //U2 39 | wire [31:0]IR; 40 | //IR 41 | wire [31:0]MDR; 42 | //MDR 43 | wire CE; 44 | wire [31:0]D; 45 | //PC 46 | wire [31:0]ALUOut; 47 | //ALUOut 48 | wire [31:0]lui; 49 | //MUX2 50 | wire [31:0]Imm_32; 51 | //Ext_32 52 | wire [31:0]Imm_32_2; 53 | //MUX4 54 | wire [31:0]Jump_addr; 55 | //MUX5 56 | wire [31:0]PC_CurrentOrSrl; 57 | assign CE=MIO_ready&&(PCWrite||(PCWriteCond&&(Branch^zero))); 58 | assign lui={IR[15:0],16'h0000}; 59 | assign Imm_32_2=Imm_32<<2; 60 | assign Jump_addr={PC_Current[31:28],IR[25:0],2'b00}; 61 | assign inst=IR; 62 | assign PC_CurrentOrSrl = S?{27'h0000000,IR[10:6]}:PC_Current; 63 | ALU U1(.A(A[31:0]), 64 | .B(B[31:0]), 65 | .ALU_operation(ALU_Control), 66 | .zero(zero), 67 | .res(res[31:0]), 68 | .overflow(overflow)); 69 | Regs U2(.clk(clk), 70 | .rst(rst), 71 | .R_addr_A(IR[25:21]), 72 | .R_addr_B(IR[20:16]), 73 | .Wt_addr(Wt_addr[4:0]), 74 | .Wt_data(Wt_data[31:0]), 75 | .L_S(RegWrite), 76 | .rdata_A(rdata_A[31:0]), 77 | .rdata_B(Data_out[31:0])); 78 | REG32 U3(.clk(clk), 79 | .rst(0), 80 | .CE(IRWrite), 81 | .D(Data_in[31:0]), 82 | .Q(IR[31:0])); 83 | REG32 U4(.clk(clk), 84 | .rst(0), 85 | .CE(1), 86 | .D(Data_in[31:0]), 87 | .Q(MDR[31:0])); 88 | REG32 U5(.clk(clk), 89 | .rst(rst), 90 | .CE(CE), 91 | .D(D[31:0]), 92 | .Q(PC_Current[31:0])); 93 | REG32 U6(.clk(clk), 94 | .rst(0), 95 | .CE(1), 96 | .D(res[31:0]), 97 | .Q(ALUOut[31:0])); 98 | mux4to1_5 MUX1(.sel(RegDst[1:0]), 99 | .a(IR[20:16]), 100 | .b(IR[15:11]), 101 | .c(5'b11111), 102 | .d(0), 103 | .o(Wt_addr[4:0])); 104 | mux4to1_32 MUX2(.sel(MemtoReg[1:0]), 105 | .a(ALUOut[31:0]), 106 | .b(MDR[31:0]), 107 | .c(lui[31:0]), 108 | .d(PC_Current[31:0]), 109 | .o(Wt_data[31:0])); 110 | Ext_32 Ext_32(.imm_16(IR[15:0]), 111 | .Imm_32(Imm_32[31:0])); 112 | mux2to1_32 MUX3(.sel(ALUSrcA), 113 | .a(rdata_A[31:0]), 114 | .b(PC_CurrentOrSrl[31:0]), 115 | .o(A[31:0])); 116 | mux4to1_32 MUX4(.sel(ALUSrcB[1:0]), 117 | .a(Data_out[31:0]), 118 | .b(4), 119 | .c(Imm_32[31:0]), 120 | .d(Imm_32_2[31:0]), 121 | .o(B[31:0])); 122 | mux4to1_32 MUX5(.sel(PCSource[1:0]), 123 | .a(res[31:0]), 124 | .b(ALUOut[31:0]), 125 | .c(Jump_addr[31:0]), 126 | .d(A[31:0]), 127 | .o(D[31:0])); 128 | mux2to1_32 MUX6(.sel(lorD), 129 | .a(ALUOut[31:0]), 130 | .b(PC_Current[31:0]), 131 | .o(M_addr[31:0])); 132 | 133 | 134 | 135 | endmodule 136 | -------------------------------------------------------------------------------- /ctrl.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ctrl(input clk, 4 | input reset, 5 | input zero, 6 | input overflow, 7 | input MIO_ready, 8 | input [31:0]inst_in, 9 | output reg MemRead, 10 | output reg MemWrite, 11 | output reg CPU_MIO, 12 | output reg lorD, 13 | output reg IRWrite, 14 | output reg RegWrite, 15 | output reg ALUSrcA, 16 | output reg PCWrite, 17 | output reg PCWriteCond, 18 | output reg Branch, 19 | output reg [1:0]RegDst, 20 | output reg [1:0]MemtoReg, 21 | output reg [1:0]ALUSrcB, 22 | output reg [1:0]PCSource, 23 | output reg [2:0]ALU_operation, 24 | output reg S, 25 | output [4:0]state_out); 26 | 27 | reg [4:0]state; 28 | 29 | parameter IF = 5'b00000, ID=5'b00001, EX_R= 5'b00010, EX_Mem=5'b00011, EX_I= 5'b00100, 30 | Lui_WB=5'b00101, EX_beq=5'b00110, EX_bne= 5'b00111, EX_jr= 5'b01000, EX_JAL=5'b01001, 31 | Exe_J= 5'b01010, MEM_RD=5'b01011, MEM_WD= 5'b01100, WB_R= 5'b01101, WB_I=5'b01110, WB_LW=5'b01111, Error=11111, 32 | EX_jalr=5'b10000; 33 | parameter AND=3'b000, OR=3'b001, ADD=3'b010, SUB=3'b110, 34 | NOR=3'b100, SLT=3'b111, XOR=3'b011, SRL=3'b101; 35 | 36 | 37 | `define CPU_ctrl_signals {S,PCWrite,PCWriteCond, lorD, MemRead, MemWrite,IRWrite, MemtoReg,PCSource, ALUSrcB,ALUSrcA,RegWrite,RegDst,CPU_MIO} 38 | 39 | assign state_out=state; 40 | 41 | always @ (posedge clk or posedge reset) begin 42 | if (reset==1) begin `CPU_ctrl_signals<=18'h12821;ALU_operation<=ADD;state <= IF; end 43 | else begin 44 | case (state) 45 | IF: begin 46 | if(MIO_ready) begin `CPU_ctrl_signals <=18'h00060; ALU_operation<=ADD; state <= ID; end 47 | else begin `CPU_ctrl_signals<=18'h12821;ALU_operation<=ADD;state <= IF; end 48 | end 49 | ID: begin 50 | case(inst_in[31:26]) 51 | 6'h00: begin 52 | case (inst_in[5:0]) 53 | 6'b100000: begin `CPU_ctrl_signals <= 18'h00010; ALU_operation<= ADD; state <= EX_R;end 54 | 6'b100010: begin `CPU_ctrl_signals <= 18'h00010; ALU_operation<= SUB; state <= EX_R;end 55 | 6'b100100: begin `CPU_ctrl_signals <= 18'h00010; ALU_operation<= AND; state <= EX_R;end 56 | 6'b100101: begin `CPU_ctrl_signals <= 18'h00010; ALU_operation<= OR; state <= EX_R;end 57 | 6'b100110: begin `CPU_ctrl_signals <= 18'h00010; ALU_operation<= XOR; state <= EX_R;end 58 | 6'b100111: begin `CPU_ctrl_signals <= 18'h00010; ALU_operation<= NOR; state <= EX_R;end 59 | 6'b101010: begin `CPU_ctrl_signals <= 18'h00010; ALU_operation<= SLT; state <= EX_R;end 60 | 6'b000010: begin `CPU_ctrl_signals <= 18'h20000; ALU_operation<= SRL; state <= EX_R;end 61 | 6'b001000: begin `CPU_ctrl_signals <= 18'h10190; state <= EX_jr; end//Jr 62 | 6'b001001: begin `CPU_ctrl_signals <= 18'h1079a; ALU_operation<=ADD; state <= EX_jalr; end//Jalr 63 | default: begin `CPU_ctrl_signals<=18'h12821;ALU_operation<=ADD;state <= IF;end 64 | endcase 65 | end 66 | 6'h08: begin `CPU_ctrl_signals<=18'h00050;ALU_operation<=ADD; state<= EX_I;end //addi 67 | 6'h0C: begin `CPU_ctrl_signals<=18'h00050;ALU_operation<=AND; state<= EX_I;end //andi 68 | 6'h0D: begin `CPU_ctrl_signals<=18'h00050;ALU_operation<=OR; state<= EX_I;end //ori 69 | 6'h0E: begin `CPU_ctrl_signals<=18'h00050;ALU_operation<=XOR; state<= EX_I;end //xori 70 | 6'h0F: begin `CPU_ctrl_signals<=18'h00408;state<= Lui_WB;end //lui 71 | 6'h23: begin `CPU_ctrl_signals<=18'h00050;ALU_operation<=ADD; state<=EX_Mem;end //lw 72 | 6'h2b: begin `CPU_ctrl_signals<=18'h00050;ALU_operation<=ADD; state<=EX_Mem;end //sw 73 | 6'h04: begin `CPU_ctrl_signals<=18'h0a090;ALU_operation<=SUB; state<=EX_beq;Branch<=1;end //beq 74 | 6'h05: begin `CPU_ctrl_signals<=18'h0a090;ALU_operation<=XOR; state<=EX_bne;Branch<=0;end //bne 75 | 6'h0a: begin `CPU_ctrl_signals<=18'h00050;ALU_operation<=SLT; state<= EX_I;end //slti 76 | 6'h02: begin `CPU_ctrl_signals<=18'h10100;state<= Exe_J;end //j 77 | 6'h03: begin `CPU_ctrl_signals<=18'h0060c;state<= EX_JAL;end //jal 78 | endcase 79 | end 80 | EX_R:begin `CPU_ctrl_signals<=18'h0000a;state <= WB_R; end 81 | EX_I:begin `CPU_ctrl_signals<=18'h00008;state <= WB_I; end 82 | 83 | 84 | EX_Mem:begin 85 | if(inst_in[31:26]==6'h23) begin `CPU_ctrl_signals<=18'h06000;state <= MEM_RD;end //lw 86 | else begin `CPU_ctrl_signals<=18'h05000;state <= MEM_WD;end //sw 87 | end 88 | MEM_RD:begin `CPU_ctrl_signals<=18'h00208;state <=WB_LW ;end //lw 89 | EX_JAL:begin `CPU_ctrl_signals<=18'h10100;state<= Exe_J;end 90 | WB_R:begin `CPU_ctrl_signals<=18'h12821;ALU_operation<=ADD;state <= IF;end 91 | WB_I:begin `CPU_ctrl_signals<=18'h12821;ALU_operation<=ADD;state <= IF;end 92 | EX_jr:begin `CPU_ctrl_signals<=18'h12821;ALU_operation<=ADD;state <= IF;end 93 | EX_jalr:begin `CPU_ctrl_signals<=18'h12821;ALU_operation<=ADD;state <= IF;end 94 | Lui_WB:begin `CPU_ctrl_signals<=18'h12821;ALU_operation<=ADD;state <= IF;end 95 | WB_LW:begin `CPU_ctrl_signals<=18'h12821;ALU_operation<=ADD;state <= IF;end 96 | MEM_WD:begin `CPU_ctrl_signals<=18'h12821;ALU_operation<=ADD;state <= IF;end //sw 97 | EX_beq:begin `CPU_ctrl_signals<=18'h12821;ALU_operation<=ADD;state <= IF;end //beq 98 | EX_bne:begin `CPU_ctrl_signals<=18'h12821;ALU_operation<=ADD;state <= IF;end //bne 99 | Exe_J:begin `CPU_ctrl_signals<=18'h12821;ALU_operation<=ADD;state <= IF;end //j 100 | endcase 101 | end 102 | end 103 | 104 | endmodule 105 | 106 | 107 | 108 | 109 | -------------------------------------------------------------------------------- /MIO_BUS.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:56:39 08/30/2015 7 | // Design Name: 8 | // Module Name: MIO_BUS 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module MIO_BUS( input clk, 22 | input rst, 23 | input mem_w, 24 | input counter0_out, 25 | input counter1_out, 26 | input counter2_out, 27 | input [3:0]BTN, 28 | input [7:0]SW, led_out, 29 | input [31:0] Cpu_data2bus, ram_data_out, addr_bus, counter_out, 30 | input ps2_ready, 31 | input [7:0]ps2_data, 32 | input vga_rdn, 33 | input [9:0]vx, vy, 34 | input [6:0]cram2bus, 35 | output reg data_ram_we, GPIOf0000000_we, GPIOe0000000_we, counter_we, vram_we, 36 | output reg [9:0]ram_addr, 37 | output reg [31:0]Cpu_data4bus, ram_data_in, Peripheral_in, 38 | output reg [14:0]vram_addr, 39 | output reg [7:0]vram_data_in, 40 | output reg ps2_rdn, 41 | output reg cram_we, 42 | output reg [6:0]data2cram, 43 | output reg [12:0]addr2cram, 44 | output reg graph_mode, 45 | output reg cram_CV 46 | ); 47 | reg [7:0]led_in; 48 | wire counter_over; 49 | wire graph_mode_clk; 50 | //status for tank and bullet 51 | reg [31:0] tank1, tank2, bullet1, bullet2; 52 | //++++++++initial VGA signal:++++++++++++++++ 53 | initial begin 54 | tank1 = 32'hc0000000; 55 | tank2 = 32'h80067E3F; 56 | bullet1 = 32'h60006040; 57 | bullet2 = 32'h4006DE30; 58 | vram_addr = 0; 59 | graph_mode = 0; 60 | end 61 | //++++++++RAM & IO decode signals: 62 | always @* begin 63 | cram_CV = 0; 64 | data_ram_we = 0; 65 | counter_we = 0; 66 | GPIOf0000000_we = 0; 67 | GPIOe0000000_we = 0; 68 | ram_addr = 10'h000; 69 | ram_data_in = 32'h00000000; 70 | Peripheral_in = 32'h0; 71 | Cpu_data4bus = 32'h0; 72 | vram_we = 0; 73 | vram_data_in = 8'h00; 74 | ps2_rdn = 1; 75 | tank1=tank1; 76 | bullet1=bullet1; 77 | tank2=tank2; 78 | bullet2=bullet2; 79 | case(addr_bus[31:28]) 80 | 4'h0: begin//data_ram(0000-0ffc) 81 | data_ram_we = mem_w; 82 | ram_addr = addr_bus[11:2]; 83 | ram_data_in = Cpu_data2bus; 84 | Cpu_data4bus = ram_data_out; 85 | end 86 | 4'ha: begin 87 | graph_mode = Cpu_data2bus[0]; 88 | end 89 | 4'he: begin//7 segment leds(e0000000-efffffff) 90 | GPIOe0000000_we = mem_w; 91 | Peripheral_in = Cpu_data2bus; 92 | Cpu_data4bus = counter_out; 93 | end 94 | 4'hf: begin//led(f0000000-fffffff0, 8 leds&counter, f0000004-fffffff4) 95 | if(addr_bus[2]) begin//f0000004 96 | counter_we = mem_w; 97 | Peripheral_in = Cpu_data2bus; 98 | Cpu_data4bus = counter_out; 99 | end 100 | else begin //f0000000 101 | GPIOf0000000_we = mem_w; 102 | Peripheral_in = Cpu_data2bus; //writer counter set & Initialization& led 103 | Cpu_data4bus = {counter0_out, counter1_out, counter2_out, 9'h000, led_out, BTN, SW}; 104 | end 105 | end 106 | 4'hc: begin //c0000000 for VGA 107 | case(addr_bus[3:0]) 108 | 4'h0:begin //tank1 109 | tank1 = Cpu_data2bus; 110 | end 111 | 4'h4:begin //tank2 112 | tank2 = Cpu_data2bus; 113 | end 114 | 4'h8:begin //bullet1 115 | bullet1 = Cpu_data2bus; 116 | end 117 | 4'hc:begin //bullet2 118 | bullet2 = Cpu_data2bus; 119 | end 120 | default: begin 121 | tank1 = tank1; 122 | tank2 = tank2; 123 | bullet1 = bullet1; 124 | bullet2 = bullet2; 125 | end 126 | endcase 127 | vram_data_in = Cpu_data2bus; 128 | end 129 | 4'hd: begin //d0000000 for ps2 130 | Cpu_data4bus = {23'h0, ps2_ready, ps2_data}; 131 | ps2_rdn = mem_w?1:0; 132 | data2cram = Cpu_data2bus; 133 | addr2cram = addr_bus[14:2]; 134 | cram_we = mem_w; 135 | cram_CV = 1; 136 | end 137 | endcase 138 | end 139 | always @* begin 140 | if(vx>=tank1[9:0]&& 141 | vx=tank1[19:10]&& 143 | vy=tank2[9:0]&& 160 | vx=tank2[19:10]&& 162 | vy=bullet1[9:0]&& 179 | vx=bullet1[19:10]&& 181 | vy=bullet2[9:0]&& 186 | vx=bullet2[19:10]&& 188 | vy