├── .gitattributes ├── .gitignore ├── FPGA小学期MIPS-CPU设计指导（参考资料） ├── lab_doc │ ├── lab01.pdf │ ├── lab02.pdf │ ├── lab03.pdf │ ├── lab04.pdf │ └── lab05.pdf ├── lab_solution by JmingS and HminL │ ├── Lab1 │ │ ├── Lab1.gise │ │ ├── Lab1.xise │ │ ├── _ngo │ │ │ └── netlist.lst │ │ ├── _xmsgs │ │ │ ├── bitgen.xmsgs │ │ │ ├── map.xmsgs │ │ │ ├── ngdbuild.xmsgs │ │ │ ├── par.xmsgs │ │ │ ├── pn_parser.xmsgs │ │ │ ├── trce.xmsgs │ │ │ └── xst.xmsgs │ │ ├── iseconfig │ │ │ ├── Lab1.projectmgr │ │ │ └── top.xreport │ │ ├── myucf.ucf │ │ ├── top.bgn │ │ ├── top.bit │ │ ├── top.bld │ │ ├── top.cmd_log │ │ ├── top.drc │ │ ├── top.lso │ │ ├── top.ncd │ │ ├── top.ngc │ │ ├── top.ngd │ │ ├── top.ngr │ │ ├── top.pad │ │ ├── top.par │ │ ├── top.pcf │ │ ├── top.prj │ │ ├── top.ptwx │ │ ├── top.stx │ │ ├── top.syr │ │ ├── top.twr │ │ ├── top.twx │ │ ├── top.unroutes │ │ ├── top.ut │ │ ├── top.v │ │ ├── top.xpi │ │ ├── top.xst │ │ ├── top_bitgen.xwbt │ │ ├── top_envsettings.html │ │ ├── top_guide.ncd │ │ ├── top_map.map │ │ ├── top_map.mrp │ │ ├── top_map.ncd │ │ ├── top_map.ngm │ │ ├── top_map.xrpt │ │ ├── top_ngdbuild.xrpt │ │ ├── top_pad.csv │ │ ├── top_pad.txt │ │ ├── top_par.xrpt │ │ ├── top_summary.html │ │ ├── top_summary.xml │ │ ├── top_tb.v │ │ ├── top_usage.xml │ │ ├── top_xst.xrpt │ │ ├── usage_statistics_webtalk.html │ │ ├── webtalk.log │ │ ├── webtalk_pn.xml │ │ ├── xlnx_auto_0_xdb │ │ │ └── cst.xbcd │ │ └── xst │ │ │ └── work │ │ │ ├── hdllib.ref │ │ │ └── vlg6F │ │ │ └── top.bin │ ├── Lab2 │ │ ├── ALU.v │ │ ├── ALU_isim_beh.exe │ │ ├── ALU_tb.v │ │ ├── ALU_tb_beh.prj │ │ ├── ALU_tb_isim_beh.exe │ │ ├── ALU_tb_isim_beh.wdb │ │ ├── Ctr.v │ │ ├── Ctr_summary.html │ │ ├── Ctr_tb.v │ │ ├── Ctr_tb_isim_beh.exe │ │ ├── Lab2.gise │ │ ├── Lab2.xise │ │ ├── _xmsgs │ │ │ └── pn_parser.xmsgs │ │ ├── fuse.log │ │ ├── fuse.xmsgs │ │ ├── fuseRelaunch.cmd │ │ ├── iseconfig │ │ │ ├── Ctr.xreport │ │ │ └── Lab2.projectmgr │ │ ├── isim.cmd │ │ ├── isim.log │ │ ├── isim │ │ │ ├── ALU_tb_isim_beh.exe.sim │ │ │ │ ├── ALU_tb_isim_beh.exe │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId.dat │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ └── work │ │ │ │ │ ├── ALU_tb_isim_beh.exe_main.c │ │ │ │ │ ├── ALU_tb_isim_beh.exe_main.nt.obj │ │ │ │ │ ├── m_00000000001638485174_0886308060.c │ │ │ │ │ ├── m_00000000001638485174_0886308060.didat │ │ │ │ │ ├── m_00000000001638485174_0886308060.nt.obj │ │ │ │ │ ├── m_00000000003030424505_4236420359.c │ │ │ │ │ ├── m_00000000003030424505_4236420359.didat │ │ │ │ │ ├── m_00000000003030424505_4236420359.nt.obj │ │ │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ │ └── m_00000000004134447467_2073120511.nt.obj │ │ │ ├── Ctr_tb_isim_beh.exe.sim │ │ │ │ ├── Ctr_tb_isim_beh.exe │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId.dat │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ └── work │ │ │ │ │ ├── Ctr_tb_isim_beh.exe_main.c │ │ │ │ │ ├── Ctr_tb_isim_beh.exe_main.nt.obj │ │ │ │ │ ├── m_00000000002127762115_2244092194.c │ │ │ │ │ ├── m_00000000002127762115_2244092194.didat │ │ │ │ │ ├── m_00000000002127762115_2244092194.nt.obj │ │ │ │ │ ├── m_00000000002434782108_0503210188.c │ │ │ │ │ ├── m_00000000002434782108_0503210188.didat │ │ │ │ │ ├── m_00000000002434782108_0503210188.nt.obj │ │ │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ │ └── m_00000000004134447467_2073120511.nt.obj │ │ │ ├── isim_usage_statistics.html │ │ │ ├── pn_info │ │ │ └── work │ │ │ │ ├── @a@l@u.sdb │ │ │ │ ├── @a@l@u_tb.sdb │ │ │ │ └── glbl.sdb │ │ └── xilinxsim.ini │ ├── Lab3 │ │ ├── Data │ │ ├── Data_memory.v │ │ ├── Data_memory_tb.v │ │ ├── Data_memory_tb_isim_beh.exe │ │ ├── Data_memory_tb_isim_beh1.wdb │ │ ├── Instruction_memory.cmd_log │ │ ├── Instruction_memory.lso │ │ ├── Instruction_memory.prj │ │ ├── Instruction_memory.syr │ │ ├── Instruction_memory.v │ │ ├── Instruction_memory.xst │ │ ├── Instruction_memory_envsettings.html │ │ ├── Instruction_memory_summary.html │ │ ├── Instruction_memory_tb.v │ │ ├── Instruction_memory_tb_isim_beh.exe │ │ ├── Instruction_memory_tb_isim_beh1.wdb │ │ ├── Instruction_memory_xst.xrpt │ │ ├── Lab3.gise │ │ ├── Lab3.xise │ │ ├── _xmsgs │ │ │ ├── pn_parser.xmsgs │ │ │ └── xst.xmsgs │ │ ├── fuse.log │ │ ├── fuse.xmsgs │ │ ├── fuseRelaunch.cmd │ │ ├── instruction │ │ ├── iseconfig │ │ │ ├── Instruction_memory.xreport │ │ │ └── Lab3.projectmgr │ │ ├── isim.cmd │ │ ├── isim.log │ │ ├── isim │ │ │ ├── Data_memory_tb_isim_beh.exe.sim │ │ │ │ ├── Data_memory_tb_isim_beh.exe │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId.dat │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ └── work │ │ │ │ │ ├── Data_memory_tb_isim_beh.exe_main.c │ │ │ │ │ ├── Data_memory_tb_isim_beh.exe_main.nt.obj │ │ │ │ │ ├── m_00000000000528498023_2183975219.c │ │ │ │ │ ├── m_00000000000528498023_2183975219.didat │ │ │ │ │ ├── m_00000000000528498023_2183975219.nt.obj │ │ │ │ │ ├── m_00000000003577048177_1151974483.c │ │ │ │ │ ├── m_00000000003577048177_1151974483.didat │ │ │ │ │ ├── m_00000000003577048177_1151974483.nt.obj │ │ │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ │ └── m_00000000004134447467_2073120511.nt.obj │ │ │ ├── Instruction_memory_tb_isim_beh.exe.sim │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ ├── Instruction_memory_tb_isim_beh.exe │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId.dat │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ └── work │ │ │ │ │ ├── Instruction_memory_tb_isim_beh.exe_main.c │ │ │ │ │ ├── Instruction_memory_tb_isim_beh.exe_main.nt.obj │ │ │ │ │ ├── m_00000000001806517667_2032185554.c │ │ │ │ │ ├── m_00000000001806517667_2032185554.didat │ │ │ │ │ ├── m_00000000001806517667_2032185554.nt.obj │ │ │ │ │ ├── m_00000000002153817270_3075357700.c │ │ │ │ │ ├── m_00000000002153817270_3075357700.didat │ │ │ │ │ ├── m_00000000002153817270_3075357700.nt.obj │ │ │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ │ └── m_00000000004134447467_2073120511.nt.obj │ │ │ ├── isim_usage_statistics.html │ │ │ ├── pn_info │ │ │ ├── register_tb_isim_beh.exe.sim │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId.dat │ │ │ │ ├── register_tb_isim_beh.exe │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ └── work │ │ │ │ │ ├── m_00000000003162073797_3913188552.c │ │ │ │ │ ├── m_00000000003162073797_3913188552.didat │ │ │ │ │ ├── m_00000000003162073797_3913188552.nt.obj │ │ │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ │ ├── m_00000000004134447467_2073120511.nt.obj │ │ │ │ │ ├── m_00000000004262842399_0400504063.c │ │ │ │ │ ├── m_00000000004262842399_0400504063.didat │ │ │ │ │ ├── m_00000000004262842399_0400504063.nt.obj │ │ │ │ │ ├── register_tb_isim_beh.exe_main.c │ │ │ │ │ └── register_tb_isim_beh.exe_main.nt.obj │ │ │ └── work │ │ │ │ ├── glbl.sdb │ │ │ │ ├── register.sdb │ │ │ │ └── register_tb.sdb │ │ ├── register │ │ ├── register.v │ │ ├── register_tb.v │ │ ├── register_tb_beh.prj │ │ ├── register_tb_isim_beh.exe │ │ ├── register_tb_isim_beh.wdb │ │ ├── register_tb_isim_beh1.wdb │ │ ├── register_tb_stx_beh.prj │ │ ├── webtalk_pn.xml │ │ ├── xilinxsim.ini │ │ └── xst │ │ │ └── work │ │ │ ├── hdllib.ref │ │ │ └── vlg42 │ │ │ └── _instruction__memory.bin │ ├── Lab4 │ │ ├── ALU.v │ │ ├── ALU_summary.html │ │ ├── Clk_gen.v │ │ ├── Clk_gen_arwz.ucf │ │ ├── Ctr.v │ │ ├── Data │ │ ├── Data_memory.v │ │ ├── Instruction_memory.v │ │ ├── Lab4.gise │ │ ├── Lab4.xise │ │ ├── _xmsgs │ │ │ └── pn_parser.xmsgs │ │ ├── fuse.log │ │ ├── fuse.xmsgs │ │ ├── fuseRelaunch.cmd │ │ ├── instruction │ │ ├── ipcore_dir │ │ │ ├── Clk_gen.v │ │ │ ├── Clk_gen.xaw │ │ │ ├── Clk_gen_arwz.ucf │ │ │ ├── Clk_gen_flist.txt │ │ │ ├── _xmsgs │ │ │ │ └── cg.xmsgs │ │ │ ├── coregen.log │ │ │ ├── create_Clk_gen.tcl │ │ │ └── xaw2verilog.log │ │ ├── iseconfig │ │ │ ├── ALU.xreport │ │ │ ├── Lab4.projectmgr │ │ │ └── top.xreport │ │ ├── isim │ │ │ └── pn_info │ │ ├── myucf.ucf │ │ ├── register.v │ │ ├── top.v │ │ ├── top_summary.html │ │ ├── top_tb.v │ │ ├── top_tb_beh.prj │ │ ├── xaw2verilog.log │ │ └── xilinxsim.ini │ ├── Lab4_1 │ │ ├── ALU.v │ │ ├── ALU_summary.html │ │ ├── Ctr.v │ │ ├── Ctr_summary.html │ │ ├── Data_memory.v │ │ ├── Instruction_memory.v │ │ ├── Lab4_1.gise │ │ ├── Lab4_1.xise │ │ ├── _xmsgs │ │ │ ├── pn_parser.xmsgs │ │ │ └── xst.xmsgs │ │ ├── fuse.log │ │ ├── fuse.xmsgs │ │ ├── fuseRelaunch.cmd │ │ ├── ipcore_dir │ │ │ ├── Clk_gen.asy │ │ │ ├── Clk_gen.gise │ │ │ ├── Clk_gen.ncf │ │ │ ├── Clk_gen.sym │ │ │ ├── Clk_gen.ucf │ │ │ ├── Clk_gen.v │ │ │ ├── Clk_gen.veo │ │ │ ├── Clk_gen.xco │ │ │ ├── Clk_gen.xdc │ │ │ ├── Clk_gen.xise │ │ │ ├── Clk_gen │ │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ │ ├── doc │ │ │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ │ │ ├── clk_wiz_v3_6_vinfo.html │ │ │ │ │ └── pg065_clk_wiz.pdf │ │ │ │ ├── example_design │ │ │ │ │ ├── Clk_gen_exdes.ucf │ │ │ │ │ ├── Clk_gen_exdes.v │ │ │ │ │ └── Clk_gen_exdes.xdc │ │ │ │ ├── implement │ │ │ │ │ ├── implement.bat │ │ │ │ │ ├── implement.sh │ │ │ │ │ ├── planAhead_ise.bat │ │ │ │ │ ├── planAhead_ise.sh │ │ │ │ │ ├── planAhead_ise.tcl │ │ │ │ │ ├── planAhead_rdn.bat │ │ │ │ │ ├── planAhead_rdn.sh │ │ │ │ │ ├── planAhead_rdn.tcl │ │ │ │ │ ├── xst.prj │ │ │ │ │ └── xst.scr │ │ │ │ └── simulation │ │ │ │ │ ├── Clk_gen_tb.v │ │ │ │ │ ├── functional │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.bat │ │ │ │ │ ├── simulate_isim.sh │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ ├── wave.do │ │ │ │ │ └── wave.sv │ │ │ │ │ └── timing │ │ │ │ │ ├── Clk_gen_tb.v │ │ │ │ │ ├── sdf_cmd_file │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.sh │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ └── wave.do │ │ │ ├── Clk_gen_flist.txt │ │ │ ├── Clk_gen_xmdf.tcl │ │ │ ├── _xmsgs │ │ │ │ ├── cg.xmsgs │ │ │ │ └── pn_parser.xmsgs │ │ │ ├── coregen.cgp │ │ │ ├── coregen.log │ │ │ ├── create_Clk_gen.tcl │ │ │ ├── edit_Clk_gen.tcl │ │ │ └── tmp │ │ │ │ ├── _cg │ │ │ │ └── _dbg │ │ │ │ │ ├── xil_307.in │ │ │ │ │ └── xil_307.out │ │ │ │ ├── _xmsgs │ │ │ │ └── pn_parser.xmsgs │ │ │ │ └── customization_gui.0.0613500764879.out │ │ ├── iseconfig │ │ │ ├── ALU.xreport │ │ │ ├── Ctr.xreport │ │ │ └── Lab4_1.projectmgr │ │ ├── isim.cmd │ │ ├── isim │ │ │ └── pn_info │ │ ├── myucf.ucf │ │ ├── register.v │ │ ├── register_isim_beh.exe │ │ ├── register_isim_beh1.wdb │ │ ├── top.cmd_log │ │ ├── top.lso │ │ ├── top.prj │ │ ├── top.syr │ │ ├── top.v │ │ ├── top.xst │ │ ├── top_envsettings.html │ │ ├── top_summary.html │ │ ├── top_tb.v │ │ ├── top_tb_beh.prj │ │ ├── top_tb_isim_beh.exe │ │ ├── top_tb_isim_beh.wdb │ │ ├── top_xst.xrpt │ │ ├── webtalk_pn.xml │ │ └── xilinxsim.ini │ ├── Lab4_2 │ │ ├── ALU.v │ │ ├── ALU_isim_beh.exe │ │ ├── ALU_summary.html │ │ ├── Ctr.v │ │ ├── Data │ │ ├── Data_memory.v │ │ ├── Data_memory_isim_beh.exe │ │ ├── Data_memory_isim_beh1.wdb │ │ ├── Instruction_memory.v │ │ ├── Instruction_memory_isim_beh.exe │ │ ├── Lab4_2.gise │ │ ├── Lab4_2.xise │ │ ├── _xmsgs │ │ │ └── pn_parser.xmsgs │ │ ├── fuse.log │ │ ├── fuse.xmsgs │ │ ├── fuseRelaunch.cmd │ │ ├── instruction │ │ ├── ipcore_dir │ │ │ ├── Clk_gen.asy │ │ │ ├── Clk_gen.gise │ │ │ ├── Clk_gen.sym │ │ │ ├── Clk_gen.ucf │ │ │ ├── Clk_gen.v │ │ │ ├── Clk_gen.veo │ │ │ ├── Clk_gen.xco │ │ │ ├── Clk_gen.xdc │ │ │ ├── Clk_gen.xise │ │ │ ├── Clk_gen │ │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ │ ├── doc │ │ │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ │ │ ├── clk_wiz_v3_6_vinfo.html │ │ │ │ │ └── pg065_clk_wiz.pdf │ │ │ │ ├── example_design │ │ │ │ │ ├── Clk_gen_exdes.ucf │ │ │ │ │ ├── Clk_gen_exdes.v │ │ │ │ │ └── Clk_gen_exdes.xdc │ │ │ │ ├── implement │ │ │ │ │ ├── implement.bat │ │ │ │ │ ├── implement.sh │ │ │ │ │ ├── planAhead_ise.bat │ │ │ │ │ ├── planAhead_ise.sh │ │ │ │ │ ├── planAhead_ise.tcl │ │ │ │ │ ├── planAhead_rdn.bat │ │ │ │ │ ├── planAhead_rdn.sh │ │ │ │ │ ├── planAhead_rdn.tcl │ │ │ │ │ ├── xst.prj │ │ │ │ │ └── xst.scr │ │ │ │ └── simulation │ │ │ │ │ ├── Clk_gen_tb.v │ │ │ │ │ ├── functional │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.bat │ │ │ │ │ ├── simulate_isim.sh │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ ├── wave.do │ │ │ │ │ └── wave.sv │ │ │ │ │ └── timing │ │ │ │ │ ├── Clk_gen_tb.v │ │ │ │ │ ├── sdf_cmd_file │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.sh │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ └── wave.do │ │ │ ├── Clk_gen_flist.txt │ │ │ ├── Clk_gen_xmdf.tcl │ │ │ ├── _xmsgs │ │ │ │ ├── cg.xmsgs │ │ │ │ └── pn_parser.xmsgs │ │ │ ├── coregen.cgp │ │ │ ├── coregen.log │ │ │ ├── create_Clk_gen.tcl │ │ │ ├── edit_Clk_gen.tcl │ │ │ └── tmp │ │ │ │ ├── _cg │ │ │ │ └── _dbg │ │ │ │ │ ├── xil_152.in │ │ │ │ │ └── xil_152.out │ │ │ │ ├── _xmsgs │ │ │ │ └── pn_parser.xmsgs │ │ │ │ └── customization_gui.0.0913053695538.out │ │ ├── iseconfig │ │ │ ├── ALU.xreport │ │ │ ├── Lab4_2.projectmgr │ │ │ └── top.xreport │ │ ├── isim.cmd │ │ ├── isim.log │ │ ├── isim │ │ │ ├── isim_usage_statistics.html │ │ │ ├── pn_info │ │ │ ├── top_isim_beh.exe.sim │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId.dat │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ ├── top_isim_beh.exe │ │ │ │ ├── unisims_ver │ │ │ │ │ ├── m_00000000000740258969_1625843133.c │ │ │ │ │ ├── m_00000000000740258969_1625843133.didat │ │ │ │ │ ├── m_00000000000740258969_1625843133.nt.obj │ │ │ │ │ ├── m_00000000000740258969_3897995058.c │ │ │ │ │ ├── m_00000000000740258969_3897995058.didat │ │ │ │ │ ├── m_00000000000740258969_3897995058.nt.obj │ │ │ │ │ ├── m_00000000001946988858_2297623829.c │ │ │ │ │ ├── m_00000000001946988858_2297623829.didat │ │ │ │ │ ├── m_00000000001946988858_2297623829.nt.obj │ │ │ │ │ ├── m_00000000002399568039_2282143210.c │ │ │ │ │ ├── m_00000000002399568039_2282143210.didat │ │ │ │ │ ├── m_00000000002399568039_2282143210.nt.obj │ │ │ │ │ ├── m_00000000002922998384_0762524165.c │ │ │ │ │ ├── m_00000000002922998384_0762524165.didat │ │ │ │ │ ├── m_00000000002922998384_0762524165.nt.obj │ │ │ │ │ ├── m_00000000003131622635_0225263307.c │ │ │ │ │ ├── m_00000000003131622635_0225263307.didat │ │ │ │ │ ├── m_00000000003131622635_0225263307.nt.obj │ │ │ │ │ ├── m_00000000003266096158_2593380106.c │ │ │ │ │ ├── m_00000000003266096158_2593380106.didat │ │ │ │ │ └── m_00000000003266096158_2593380106.nt.obj │ │ │ │ └── work │ │ │ │ │ ├── m_00000000000139310833_1306970619.c │ │ │ │ │ ├── m_00000000000139310833_1306970619.didat │ │ │ │ │ ├── m_00000000000139310833_1306970619.nt.obj │ │ │ │ │ ├── m_00000000001638485174_0886308060.c │ │ │ │ │ ├── m_00000000001638485174_0886308060.didat │ │ │ │ │ ├── m_00000000001638485174_0886308060.nt.obj │ │ │ │ │ ├── m_00000000002127762115_2244092194.c │ │ │ │ │ ├── m_00000000002127762115_2244092194.didat │ │ │ │ │ ├── m_00000000002127762115_2244092194.nt.obj │ │ │ │ │ ├── m_00000000002629890179_2032185554.c │ │ │ │ │ ├── m_00000000002629890179_2032185554.didat │ │ │ │ │ ├── m_00000000002629890179_2032185554.nt.obj │ │ │ │ │ ├── m_00000000003162073797_3913188552.c │ │ │ │ │ ├── m_00000000003162073797_3913188552.didat │ │ │ │ │ ├── m_00000000003162073797_3913188552.nt.obj │ │ │ │ │ ├── m_00000000003524194649_0967167703.c │ │ │ │ │ ├── m_00000000003524194649_0967167703.didat │ │ │ │ │ ├── m_00000000003524194649_0967167703.nt.obj │ │ │ │ │ ├── m_00000000003577048177_1151974483.c │ │ │ │ │ ├── m_00000000003577048177_1151974483.didat │ │ │ │ │ ├── m_00000000003577048177_1151974483.nt.obj │ │ │ │ │ ├── m_00000000004096139096_3823007873.c │ │ │ │ │ ├── m_00000000004096139096_3823007873.didat │ │ │ │ │ ├── m_00000000004096139096_3823007873.nt.obj │ │ │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ │ ├── m_00000000004134447467_2073120511.nt.obj │ │ │ │ │ ├── top_isim_beh.exe_main.c │ │ │ │ │ └── top_isim_beh.exe_main.nt.obj │ │ │ ├── top_tb_isim_beh.exe.sim │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId.dat │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ ├── top_tb_isim_beh.exe │ │ │ │ ├── unisims_ver │ │ │ │ │ ├── m_00000000000740258969_1625843133.c │ │ │ │ │ ├── m_00000000000740258969_1625843133.didat │ │ │ │ │ ├── m_00000000000740258969_1625843133.nt.obj │ │ │ │ │ ├── m_00000000000740258969_3897995058.c │ │ │ │ │ ├── m_00000000000740258969_3897995058.didat │ │ │ │ │ ├── m_00000000000740258969_3897995058.nt.obj │ │ │ │ │ ├── m_00000000001946988858_2297623829.c │ │ │ │ │ ├── m_00000000001946988858_2297623829.didat │ │ │ │ │ ├── m_00000000001946988858_2297623829.nt.obj │ │ │ │ │ ├── m_00000000002399568039_2282143210.c │ │ │ │ │ ├── m_00000000002399568039_2282143210.didat │ │ │ │ │ ├── m_00000000002399568039_2282143210.nt.obj │ │ │ │ │ ├── m_00000000002922998384_0762524165.c │ │ │ │ │ ├── m_00000000002922998384_0762524165.didat │ │ │ │ │ ├── m_00000000002922998384_0762524165.nt.obj │ │ │ │ │ ├── m_00000000003131622635_0225263307.c │ │ │ │ │ ├── m_00000000003131622635_0225263307.didat │ │ │ │ │ ├── m_00000000003131622635_0225263307.nt.obj │ │ │ │ │ ├── m_00000000003266096158_2593380106.c │ │ │ │ │ ├── m_00000000003266096158_2593380106.didat │ │ │ │ │ └── m_00000000003266096158_2593380106.nt.obj │ │ │ │ └── work │ │ │ │ │ ├── m_00000000000063944133_3115858369.c │ │ │ │ │ ├── m_00000000000063944133_3115858369.didat │ │ │ │ │ ├── m_00000000000063944133_3115858369.nt.obj │ │ │ │ │ ├── m_00000000000139310833_1306970619.c │ │ │ │ │ ├── m_00000000000139310833_1306970619.didat │ │ │ │ │ ├── m_00000000000139310833_1306970619.nt.obj │ │ │ │ │ ├── m_00000000001638485174_0886308060.c │ │ │ │ │ ├── m_00000000001638485174_0886308060.didat │ │ │ │ │ ├── m_00000000001638485174_0886308060.nt.obj │ │ │ │ │ ├── m_00000000002127762115_2244092194.c │ │ │ │ │ ├── m_00000000002127762115_2244092194.didat │ │ │ │ │ ├── m_00000000002127762115_2244092194.nt.obj │ │ │ │ │ ├── m_00000000002629890179_2032185554.c │ │ │ │ │ ├── m_00000000002629890179_2032185554.didat │ │ │ │ │ ├── m_00000000002629890179_2032185554.nt.obj │ │ │ │ │ ├── m_00000000003162073797_3913188552.c │ │ │ │ │ ├── m_00000000003162073797_3913188552.didat │ │ │ │ │ ├── m_00000000003162073797_3913188552.nt.obj │ │ │ │ │ ├── m_00000000003524194649_0967167703.c │ │ │ │ │ ├── m_00000000003524194649_0967167703.didat │ │ │ │ │ ├── m_00000000003524194649_0967167703.nt.obj │ │ │ │ │ ├── m_00000000003577048177_1151974483.c │ │ │ │ │ ├── m_00000000003577048177_1151974483.didat │ │ │ │ │ ├── m_00000000003577048177_1151974483.nt.obj │ │ │ │ │ ├── m_00000000004096139096_3823007873.c │ │ │ │ │ ├── m_00000000004096139096_3823007873.didat │ │ │ │ │ ├── m_00000000004096139096_3823007873.nt.obj │ │ │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ │ ├── m_00000000004134447467_2073120511.nt.obj │ │ │ │ │ ├── top_tb_isim_beh.exe_main.c │ │ │ │ │ └── top_tb_isim_beh.exe_main.nt.obj │ │ │ └── work │ │ │ │ ├── @a@l@u.sdb │ │ │ │ ├── @clk_gen.sdb │ │ │ │ ├── @ctr.sdb │ │ │ │ ├── @data_memory.sdb │ │ │ │ ├── @instruction_memory.sdb │ │ │ │ ├── glbl.sdb │ │ │ │ ├── register.sdb │ │ │ │ ├── signext.sdb │ │ │ │ ├── top.sdb │ │ │ │ └── top_tb.sdb │ │ ├── myucf.ucf │ │ ├── register │ │ ├── register.v │ │ ├── signext.v │ │ ├── simulation │ │ │ └── end.wcfg │ │ ├── top.v │ │ ├── top_isim_beh.exe │ │ ├── top_summary.html │ │ ├── top_tb.v │ │ ├── top_tb_beh.prj │ │ ├── top_tb_isim_beh.exe │ │ ├── top_tb_isim_beh.wdb │ │ ├── top_tb_isim_beh1.wdb │ │ └── xilinxsim.ini │ ├── Lab5_1 │ │ ├── ALU.v │ │ ├── ALU_isim_beh.exe │ │ ├── Ctr.v │ │ ├── Ctr_isim_beh.exe │ │ ├── Data │ │ ├── Data_memory.v │ │ ├── DmemB.mif │ │ ├── Instruction_memory.v │ │ ├── Instruction_memory_isim_beh.exe │ │ ├── Instruction_memory_isim_beh1.wdb │ │ ├── Lab5.gise │ │ ├── Lab5.xise │ │ ├── _xmsgs │ │ │ └── pn_parser.xmsgs │ │ ├── data.coe │ │ ├── fuse.log │ │ ├── fuse.xmsgs │ │ ├── fuseRelaunch.cmd │ │ ├── instruction │ │ ├── ipcore_dir │ │ │ ├── Clk_gen.asy │ │ │ ├── Clk_gen.gise │ │ │ ├── Clk_gen.sym │ │ │ ├── Clk_gen.ucf │ │ │ ├── Clk_gen.v │ │ │ ├── Clk_gen.veo │ │ │ ├── Clk_gen.xco │ │ │ ├── Clk_gen.xdc │ │ │ ├── Clk_gen.xise │ │ │ ├── Clk_gen │ │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ │ ├── doc │ │ │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ │ │ ├── clk_wiz_v3_6_vinfo.html │ │ │ │ │ └── pg065_clk_wiz.pdf │ │ │ │ ├── example_design │ │ │ │ │ ├── Clk_gen_exdes.ucf │ │ │ │ │ ├── Clk_gen_exdes.v │ │ │ │ │ └── Clk_gen_exdes.xdc │ │ │ │ ├── implement │ │ │ │ │ ├── implement.bat │ │ │ │ │ ├── implement.sh │ │ │ │ │ ├── planAhead_ise.bat │ │ │ │ │ ├── planAhead_ise.sh │ │ │ │ │ ├── planAhead_ise.tcl │ │ │ │ │ ├── planAhead_rdn.bat │ │ │ │ │ ├── planAhead_rdn.sh │ │ │ │ │ ├── planAhead_rdn.tcl │ │ │ │ │ ├── xst.prj │ │ │ │ │ └── xst.scr │ │ │ │ └── simulation │ │ │ │ │ ├── Clk_gen_tb.v │ │ │ │ │ ├── functional │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.bat │ │ │ │ │ ├── simulate_isim.sh │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ ├── wave.do │ │ │ │ │ └── wave.sv │ │ │ │ │ └── timing │ │ │ │ │ ├── Clk_gen_tb.v │ │ │ │ │ ├── sdf_cmd_file │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.sh │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ └── wave.do │ │ │ ├── Clk_gen_flist.txt │ │ │ ├── Clk_gen_xmdf.tcl │ │ │ ├── DmemB.asy │ │ │ ├── DmemB.gise │ │ │ ├── DmemB.mif │ │ │ ├── DmemB.ngc │ │ │ ├── DmemB.sym │ │ │ ├── DmemB.v │ │ │ ├── DmemB.veo │ │ │ ├── DmemB.xco │ │ │ ├── DmemB.xise │ │ │ ├── DmemB │ │ │ │ ├── blk_mem_gen_v7_3_readme.txt │ │ │ │ ├── doc │ │ │ │ │ ├── blk_mem_gen_v7_3_vinfo.html │ │ │ │ │ └── pg058-blk-mem-gen.pdf │ │ │ │ ├── example_design │ │ │ │ │ ├── DmemB_exdes.ucf │ │ │ │ │ ├── DmemB_exdes.vhd │ │ │ │ │ ├── DmemB_exdes.xdc │ │ │ │ │ └── DmemB_prod.vhd │ │ │ │ ├── implement │ │ │ │ │ ├── implement.bat │ │ │ │ │ ├── implement.sh │ │ │ │ │ ├── planAhead_ise.bat │ │ │ │ │ ├── planAhead_ise.sh │ │ │ │ │ ├── planAhead_ise.tcl │ │ │ │ │ ├── xst.prj │ │ │ │ │ └── xst.scr │ │ │ │ └── simulation │ │ │ │ │ ├── DmemB_synth.vhd │ │ │ │ │ ├── DmemB_tb.vhd │ │ │ │ │ ├── addr_gen.vhd │ │ │ │ │ ├── bmg_stim_gen.vhd │ │ │ │ │ ├── bmg_tb_pkg.vhd │ │ │ │ │ ├── checker.vhd │ │ │ │ │ ├── data_gen.vhd │ │ │ │ │ ├── functional │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.bat │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ ├── wave_mti.do │ │ │ │ │ └── wave_ncsim.sv │ │ │ │ │ ├── random.vhd │ │ │ │ │ └── timing │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.bat │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ ├── wave_mti.do │ │ │ │ │ └── wave_ncsim.sv │ │ │ ├── DmemB_flist.txt │ │ │ ├── DmemB_xmdf.tcl │ │ │ ├── _xmsgs │ │ │ │ ├── cg.xmsgs │ │ │ │ └── pn_parser.xmsgs │ │ │ ├── coregen.cgp │ │ │ ├── coregen.log │ │ │ ├── create_Clk_gen.tcl │ │ │ ├── create_DmemB.tcl │ │ │ ├── data.coe │ │ │ ├── edit_Clk_gen.tcl │ │ │ ├── edit_DmemB.tcl │ │ │ ├── summary.log │ │ │ └── tmp │ │ │ │ ├── DmemB.lso │ │ │ │ ├── _cg │ │ │ │ └── _dbg │ │ │ │ │ ├── xil_918.in │ │ │ │ │ └── xil_918.out │ │ │ │ ├── _xmsgs │ │ │ │ ├── pn_parser.xmsgs │ │ │ │ └── xst.xmsgs │ │ │ │ └── customization_gui.0.213712161506.out │ │ ├── iseconfig │ │ │ ├── Lab5.projectmgr │ │ │ └── top.xreport │ │ ├── isim.cmd │ │ ├── isim.log │ │ ├── isim │ │ │ ├── isim_usage_statistics.html │ │ │ ├── pn_info │ │ │ ├── top_tb_isim_beh.exe.sim │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId.dat │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ ├── top_tb_isim_beh.exe │ │ │ │ ├── unisims_ver │ │ │ │ │ ├── m_00000000000740258969_1625843133.c │ │ │ │ │ ├── m_00000000000740258969_1625843133.didat │ │ │ │ │ ├── m_00000000000740258969_1625843133.nt.obj │ │ │ │ │ ├── m_00000000000740258969_3897995058.c │ │ │ │ │ ├── m_00000000000740258969_3897995058.didat │ │ │ │ │ ├── m_00000000000740258969_3897995058.nt.obj │ │ │ │ │ ├── m_00000000001946988858_2297623829.c │ │ │ │ │ ├── m_00000000001946988858_2297623829.didat │ │ │ │ │ ├── m_00000000001946988858_2297623829.nt.obj │ │ │ │ │ ├── m_00000000002399568039_2282143210.c │ │ │ │ │ ├── m_00000000002399568039_2282143210.didat │ │ │ │ │ ├── m_00000000002399568039_2282143210.nt.obj │ │ │ │ │ ├── m_00000000002922998384_0762524165.c │ │ │ │ │ ├── m_00000000002922998384_0762524165.didat │ │ │ │ │ ├── m_00000000002922998384_0762524165.nt.obj │ │ │ │ │ ├── m_00000000003131622635_0225263307.c │ │ │ │ │ ├── m_00000000003131622635_0225263307.didat │ │ │ │ │ ├── m_00000000003131622635_0225263307.nt.obj │ │ │ │ │ ├── m_00000000003266096158_2593380106.c │ │ │ │ │ ├── m_00000000003266096158_2593380106.didat │ │ │ │ │ └── m_00000000003266096158_2593380106.nt.obj │ │ │ │ └── work │ │ │ │ │ ├── m_00000000000063944133_3115858369.c │ │ │ │ │ ├── m_00000000000063944133_3115858369.didat │ │ │ │ │ ├── m_00000000000063944133_3115858369.nt.obj │ │ │ │ │ ├── m_00000000000139310833_1306970619.c │ │ │ │ │ ├── m_00000000000139310833_1306970619.didat │ │ │ │ │ ├── m_00000000000139310833_1306970619.nt.obj │ │ │ │ │ ├── m_00000000000552152946_3823007873.c │ │ │ │ │ ├── m_00000000000552152946_3823007873.didat │ │ │ │ │ ├── m_00000000000552152946_3823007873.nt.obj │ │ │ │ │ ├── m_00000000001638485174_0886308060.c │ │ │ │ │ ├── m_00000000001638485174_0886308060.didat │ │ │ │ │ ├── m_00000000001638485174_0886308060.nt.obj │ │ │ │ │ ├── m_00000000001886194798_2244092194.c │ │ │ │ │ ├── m_00000000001886194798_2244092194.didat │ │ │ │ │ ├── m_00000000001886194798_2244092194.nt.obj │ │ │ │ │ ├── m_00000000002629890179_2032185554.c │ │ │ │ │ ├── m_00000000002629890179_2032185554.didat │ │ │ │ │ ├── m_00000000002629890179_2032185554.nt.obj │ │ │ │ │ ├── m_00000000003162073797_3913188552.c │ │ │ │ │ ├── m_00000000003162073797_3913188552.didat │ │ │ │ │ ├── m_00000000003162073797_3913188552.nt.obj │ │ │ │ │ ├── m_00000000003524194649_0967167703.c │ │ │ │ │ ├── m_00000000003524194649_0967167703.didat │ │ │ │ │ ├── m_00000000003524194649_0967167703.nt.obj │ │ │ │ │ ├── m_00000000003577048177_1151974483.c │ │ │ │ │ ├── m_00000000003577048177_1151974483.didat │ │ │ │ │ ├── m_00000000003577048177_1151974483.nt.obj │ │ │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ │ ├── m_00000000004134447467_2073120511.nt.obj │ │ │ │ │ ├── top_tb_isim_beh.exe_main.c │ │ │ │ │ └── top_tb_isim_beh.exe_main.nt.obj │ │ │ └── work │ │ │ │ ├── @a@l@u.sdb │ │ │ │ ├── @clk_gen.sdb │ │ │ │ ├── @ctr.sdb │ │ │ │ ├── @data_memory.sdb │ │ │ │ ├── @instruction_memory.sdb │ │ │ │ ├── glbl.sdb │ │ │ │ ├── register.sdb │ │ │ │ ├── signext.sdb │ │ │ │ ├── top.sdb │ │ │ │ └── top_tb.sdb │ │ ├── myucf.ucf │ │ ├── register │ │ ├── register.v │ │ ├── register_isim_beh.exe │ │ ├── signext.v │ │ ├── simulation │ │ │ ├── end.wcfg │ │ │ └── end1.wcfg │ │ ├── top.v │ │ ├── top_isim_beh.exe │ │ ├── top_stx_beh.prj │ │ ├── top_summary.html │ │ ├── top_tb.v │ │ ├── top_tb_beh.prj │ │ ├── top_tb_isim_beh.exe │ │ ├── top_tb_isim_beh.wdb │ │ └── xilinxsim.ini │ ├── Lab5_2 │ │ ├── ALU.v │ │ ├── ALU_isim_beh.exe │ │ ├── Ctr.v │ │ ├── Ctr_isim_beh.exe │ │ ├── Ctr_isim_beh1.wdb │ │ ├── Data │ │ ├── Data_memory.v │ │ ├── DmemB.mif │ │ ├── Instruction_memory.v │ │ ├── Instruction_memory_isim_beh.exe │ │ ├── Instruction_memory_isim_beh1.wdb │ │ ├── Lab5.gise │ │ ├── Lab5.xise │ │ ├── _xmsgs │ │ │ └── pn_parser.xmsgs │ │ ├── data.coe │ │ ├── fuse.log │ │ ├── fuse.xmsgs │ │ ├── fuseRelaunch.cmd │ │ ├── instruction │ │ ├── ipcore_dir │ │ │ ├── Clk_gen.asy │ │ │ ├── Clk_gen.gise │ │ │ ├── Clk_gen.sym │ │ │ ├── Clk_gen.ucf │ │ │ ├── Clk_gen.v │ │ │ ├── Clk_gen.veo │ │ │ ├── Clk_gen.xco │ │ │ ├── Clk_gen.xdc │ │ │ ├── Clk_gen.xise │ │ │ ├── Clk_gen │ │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ │ ├── doc │ │ │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ │ │ ├── clk_wiz_v3_6_vinfo.html │ │ │ │ │ └── pg065_clk_wiz.pdf │ │ │ │ ├── example_design │ │ │ │ │ ├── Clk_gen_exdes.ucf │ │ │ │ │ ├── Clk_gen_exdes.v │ │ │ │ │ └── Clk_gen_exdes.xdc │ │ │ │ ├── implement │ │ │ │ │ ├── implement.bat │ │ │ │ │ ├── implement.sh │ │ │ │ │ ├── planAhead_ise.bat │ │ │ │ │ ├── planAhead_ise.sh │ │ │ │ │ ├── planAhead_ise.tcl │ │ │ │ │ ├── planAhead_rdn.bat │ │ │ │ │ ├── planAhead_rdn.sh │ │ │ │ │ ├── planAhead_rdn.tcl │ │ │ │ │ ├── xst.prj │ │ │ │ │ └── xst.scr │ │ │ │ └── simulation │ │ │ │ │ ├── Clk_gen_tb.v │ │ │ │ │ ├── functional │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.bat │ │ │ │ │ ├── simulate_isim.sh │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ ├── wave.do │ │ │ │ │ └── wave.sv │ │ │ │ │ └── timing │ │ │ │ │ ├── Clk_gen_tb.v │ │ │ │ │ ├── sdf_cmd_file │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.sh │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ └── wave.do │ │ │ ├── Clk_gen_flist.txt │ │ │ ├── Clk_gen_xmdf.tcl │ │ │ ├── DmemB.asy │ │ │ ├── DmemB.gise │ │ │ ├── DmemB.mif │ │ │ ├── DmemB.ngc │ │ │ ├── DmemB.sym │ │ │ ├── DmemB.v │ │ │ ├── DmemB.veo │ │ │ ├── DmemB.xco │ │ │ ├── DmemB.xise │ │ │ ├── DmemB │ │ │ │ ├── blk_mem_gen_v7_3_readme.txt │ │ │ │ ├── doc │ │ │ │ │ ├── blk_mem_gen_v7_3_vinfo.html │ │ │ │ │ └── pg058-blk-mem-gen.pdf │ │ │ │ ├── example_design │ │ │ │ │ ├── DmemB_exdes.ucf │ │ │ │ │ ├── DmemB_exdes.vhd │ │ │ │ │ ├── DmemB_exdes.xdc │ │ │ │ │ └── DmemB_prod.vhd │ │ │ │ ├── implement │ │ │ │ │ ├── implement.bat │ │ │ │ │ ├── implement.sh │ │ │ │ │ ├── planAhead_ise.bat │ │ │ │ │ ├── planAhead_ise.sh │ │ │ │ │ ├── planAhead_ise.tcl │ │ │ │ │ ├── xst.prj │ │ │ │ │ └── xst.scr │ │ │ │ └── simulation │ │ │ │ │ ├── DmemB_synth.vhd │ │ │ │ │ ├── DmemB_tb.vhd │ │ │ │ │ ├── addr_gen.vhd │ │ │ │ │ ├── bmg_stim_gen.vhd │ │ │ │ │ ├── bmg_tb_pkg.vhd │ │ │ │ │ ├── checker.vhd │ │ │ │ │ ├── data_gen.vhd │ │ │ │ │ ├── functional │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.bat │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ ├── wave_mti.do │ │ │ │ │ └── wave_ncsim.sv │ │ │ │ │ ├── random.vhd │ │ │ │ │ └── timing │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.bat │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ ├── wave_mti.do │ │ │ │ │ └── wave_ncsim.sv │ │ │ ├── DmemB_flist.txt │ │ │ ├── DmemB_xmdf.tcl │ │ │ ├── _xmsgs │ │ │ │ ├── cg.xmsgs │ │ │ │ └── pn_parser.xmsgs │ │ │ ├── coregen.cgp │ │ │ ├── coregen.log │ │ │ ├── create_Clk_gen.tcl │ │ │ ├── create_DmemB.tcl │ │ │ ├── data.coe │ │ │ ├── edit_Clk_gen.tcl │ │ │ ├── edit_DmemB.tcl │ │ │ ├── summary.log │ │ │ └── tmp │ │ │ │ ├── DmemB.lso │ │ │ │ ├── _cg │ │ │ │ └── _dbg │ │ │ │ │ ├── xil_918.in │ │ │ │ │ └── xil_918.out │ │ │ │ ├── _xmsgs │ │ │ │ ├── pn_parser.xmsgs │ │ │ │ └── xst.xmsgs │ │ │ │ └── customization_gui.0.213712161506.out │ │ ├── iseconfig │ │ │ ├── Lab5.projectmgr │ │ │ └── top.xreport │ │ ├── isim.cmd │ │ ├── isim.log │ │ ├── isim │ │ │ ├── isim_usage_statistics.html │ │ │ ├── pn_info │ │ │ ├── top_tb_isim_beh.exe.sim │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId.dat │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ ├── top_tb_isim_beh.exe │ │ │ │ ├── unisims_ver │ │ │ │ │ ├── m_00000000000740258969_1625843133.c │ │ │ │ │ ├── m_00000000000740258969_1625843133.didat │ │ │ │ │ ├── m_00000000000740258969_1625843133.nt.obj │ │ │ │ │ ├── m_00000000000740258969_3897995058.c │ │ │ │ │ ├── m_00000000000740258969_3897995058.didat │ │ │ │ │ ├── m_00000000000740258969_3897995058.nt.obj │ │ │ │ │ ├── m_00000000001946988858_2297623829.c │ │ │ │ │ ├── m_00000000001946988858_2297623829.didat │ │ │ │ │ ├── m_00000000001946988858_2297623829.nt.obj │ │ │ │ │ ├── m_00000000002399568039_2282143210.c │ │ │ │ │ ├── m_00000000002399568039_2282143210.didat │ │ │ │ │ ├── m_00000000002399568039_2282143210.nt.obj │ │ │ │ │ ├── m_00000000002922998384_0762524165.c │ │ │ │ │ ├── m_00000000002922998384_0762524165.didat │ │ │ │ │ ├── m_00000000002922998384_0762524165.nt.obj │ │ │ │ │ ├── m_00000000003131622635_0225263307.c │ │ │ │ │ ├── m_00000000003131622635_0225263307.didat │ │ │ │ │ ├── m_00000000003131622635_0225263307.nt.obj │ │ │ │ │ ├── m_00000000003266096158_2593380106.c │ │ │ │ │ ├── m_00000000003266096158_2593380106.didat │ │ │ │ │ └── m_00000000003266096158_2593380106.nt.obj │ │ │ │ └── work │ │ │ │ │ ├── m_00000000000063944133_3115858369.c │ │ │ │ │ ├── m_00000000000063944133_3115858369.didat │ │ │ │ │ ├── m_00000000000063944133_3115858369.nt.obj │ │ │ │ │ ├── m_00000000000139310833_1306970619.c │ │ │ │ │ ├── m_00000000000139310833_1306970619.didat │ │ │ │ │ ├── m_00000000000139310833_1306970619.nt.obj │ │ │ │ │ ├── m_00000000001638485174_0886308060.c │ │ │ │ │ ├── m_00000000001638485174_0886308060.didat │ │ │ │ │ ├── m_00000000001638485174_0886308060.nt.obj │ │ │ │ │ ├── m_00000000001886194798_2244092194.c │ │ │ │ │ ├── m_00000000001886194798_2244092194.didat │ │ │ │ │ ├── m_00000000001886194798_2244092194.nt.obj │ │ │ │ │ ├── m_00000000002629890179_2032185554.c │ │ │ │ │ ├── m_00000000002629890179_2032185554.didat │ │ │ │ │ ├── m_00000000002629890179_2032185554.nt.obj │ │ │ │ │ ├── m_00000000003162073797_3913188552.c │ │ │ │ │ ├── m_00000000003162073797_3913188552.didat │ │ │ │ │ ├── m_00000000003162073797_3913188552.nt.obj │ │ │ │ │ ├── m_00000000003380540956_3823007873.c │ │ │ │ │ ├── m_00000000003380540956_3823007873.didat │ │ │ │ │ ├── m_00000000003380540956_3823007873.nt.obj │ │ │ │ │ ├── m_00000000003524194649_0967167703.c │ │ │ │ │ ├── m_00000000003524194649_0967167703.didat │ │ │ │ │ ├── m_00000000003524194649_0967167703.nt.obj │ │ │ │ │ ├── m_00000000003577048177_1151974483.c │ │ │ │ │ ├── m_00000000003577048177_1151974483.didat │ │ │ │ │ ├── m_00000000003577048177_1151974483.nt.obj │ │ │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ │ ├── m_00000000004134447467_2073120511.nt.obj │ │ │ │ │ ├── top_tb_isim_beh.exe_main.c │ │ │ │ │ └── top_tb_isim_beh.exe_main.nt.obj │ │ │ └── work │ │ │ │ ├── @a@l@u.sdb │ │ │ │ ├── @clk_gen.sdb │ │ │ │ ├── @ctr.sdb │ │ │ │ ├── @data_memory.sdb │ │ │ │ ├── @instruction_memory.sdb │ │ │ │ ├── glbl.sdb │ │ │ │ ├── register.sdb │ │ │ │ ├── signext.sdb │ │ │ │ ├── top.sdb │ │ │ │ └── top_tb.sdb │ │ ├── myucf.ucf │ │ ├── register │ │ ├── register.v │ │ ├── register_isim_beh.exe │ │ ├── signext.v │ │ ├── simulation │ │ │ ├── end.wcfg │ │ │ └── end1.wcfg │ │ ├── top.v │ │ ├── top_isim_beh.exe │ │ ├── top_stx_beh.prj │ │ ├── top_summary.html │ │ ├── top_tb.v │ │ ├── top_tb_beh.prj │ │ ├── top_tb_isim_beh.exe │ │ ├── top_tb_isim_beh.wdb │ │ └── xilinxsim.ini │ ├── Lab5_3 │ │ ├── ALU.v │ │ ├── ALU_isim_beh.exe │ │ ├── ALU_isim_beh1.wdb │ │ ├── Ctr.v │ │ ├── Ctr_isim_beh.exe │ │ ├── Ctr_isim_beh1.wdb │ │ ├── Data │ │ ├── Data_memory.v │ │ ├── DmemB.mif │ │ ├── Instruction_memory.v │ │ ├── Instruction_memory_isim_beh.exe │ │ ├── Instruction_memory_isim_beh1.wdb │ │ ├── Lab5.gise │ │ ├── Lab5.xise │ │ ├── _xmsgs │ │ │ └── pn_parser.xmsgs │ │ ├── data.coe │ │ ├── fuse.log │ │ ├── fuse.xmsgs │ │ ├── fuseRelaunch.cmd │ │ ├── instruction │ │ ├── instruction1 │ │ ├── instruction2 │ │ ├── ipcore_dir │ │ │ ├── Clk_gen.asy │ │ │ ├── Clk_gen.gise │ │ │ ├── Clk_gen.sym │ │ │ ├── Clk_gen.ucf │ │ │ ├── Clk_gen.v │ │ │ ├── Clk_gen.veo │ │ │ ├── Clk_gen.xco │ │ │ ├── Clk_gen.xdc │ │ │ ├── Clk_gen.xise │ │ │ ├── Clk_gen │ │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ │ ├── doc │ │ │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ │ │ ├── clk_wiz_v3_6_vinfo.html │ │ │ │ │ └── pg065_clk_wiz.pdf │ │ │ │ ├── example_design │ │ │ │ │ ├── Clk_gen_exdes.ucf │ │ │ │ │ ├── Clk_gen_exdes.v │ │ │ │ │ └── Clk_gen_exdes.xdc │ │ │ │ ├── implement │ │ │ │ │ ├── implement.bat │ │ │ │ │ ├── implement.sh │ │ │ │ │ ├── planAhead_ise.bat │ │ │ │ │ ├── planAhead_ise.sh │ │ │ │ │ ├── planAhead_ise.tcl │ │ │ │ │ ├── planAhead_rdn.bat │ │ │ │ │ ├── planAhead_rdn.sh │ │ │ │ │ ├── planAhead_rdn.tcl │ │ │ │ │ ├── xst.prj │ │ │ │ │ └── xst.scr │ │ │ │ └── simulation │ │ │ │ │ ├── Clk_gen_tb.v │ │ │ │ │ ├── functional │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.bat │ │ │ │ │ ├── simulate_isim.sh │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ ├── wave.do │ │ │ │ │ └── wave.sv │ │ │ │ │ └── timing │ │ │ │ │ ├── Clk_gen_tb.v │ │ │ │ │ ├── sdf_cmd_file │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.sh │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ └── wave.do │ │ │ ├── Clk_gen_flist.txt │ │ │ ├── Clk_gen_xmdf.tcl │ │ │ ├── DmemB.asy │ │ │ ├── DmemB.gise │ │ │ ├── DmemB.mif │ │ │ ├── DmemB.ngc │ │ │ ├── DmemB.sym │ │ │ ├── DmemB.v │ │ │ ├── DmemB.veo │ │ │ ├── DmemB.xco │ │ │ ├── DmemB.xise │ │ │ ├── DmemB │ │ │ │ ├── blk_mem_gen_v7_3_readme.txt │ │ │ │ ├── doc │ │ │ │ │ ├── blk_mem_gen_v7_3_vinfo.html │ │ │ │ │ └── pg058-blk-mem-gen.pdf │ │ │ │ ├── example_design │ │ │ │ │ ├── DmemB_exdes.ucf │ │ │ │ │ ├── DmemB_exdes.vhd │ │ │ │ │ ├── DmemB_exdes.xdc │ │ │ │ │ └── DmemB_prod.vhd │ │ │ │ ├── implement │ │ │ │ │ ├── implement.bat │ │ │ │ │ ├── implement.sh │ │ │ │ │ ├── planAhead_ise.bat │ │ │ │ │ ├── planAhead_ise.sh │ │ │ │ │ ├── planAhead_ise.tcl │ │ │ │ │ ├── xst.prj │ │ │ │ │ └── xst.scr │ │ │ │ └── simulation │ │ │ │ │ ├── DmemB_synth.vhd │ │ │ │ │ ├── DmemB_tb.vhd │ │ │ │ │ ├── addr_gen.vhd │ │ │ │ │ ├── bmg_stim_gen.vhd │ │ │ │ │ ├── bmg_tb_pkg.vhd │ │ │ │ │ ├── checker.vhd │ │ │ │ │ ├── data_gen.vhd │ │ │ │ │ ├── functional │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.bat │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ ├── wave_mti.do │ │ │ │ │ └── wave_ncsim.sv │ │ │ │ │ ├── random.vhd │ │ │ │ │ └── timing │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.bat │ │ │ │ │ ├── simulate_mti.bat │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ ├── wave_mti.do │ │ │ │ │ └── wave_ncsim.sv │ │ │ ├── DmemB_flist.txt │ │ │ ├── DmemB_xmdf.tcl │ │ │ ├── _xmsgs │ │ │ │ ├── cg.xmsgs │ │ │ │ └── pn_parser.xmsgs │ │ │ ├── coregen.cgp │ │ │ ├── coregen.log │ │ │ ├── create_Clk_gen.tcl │ │ │ ├── create_DmemB.tcl │ │ │ ├── data.coe │ │ │ ├── edit_Clk_gen.tcl │ │ │ ├── edit_DmemB.tcl │ │ │ ├── summary.log │ │ │ └── tmp │ │ │ │ ├── DmemB.lso │ │ │ │ ├── _cg │ │ │ │ └── _dbg │ │ │ │ │ ├── xil_531.in │ │ │ │ │ └── xil_531.out │ │ │ │ ├── _xmsgs │ │ │ │ ├── pn_parser.xmsgs │ │ │ │ └── xst.xmsgs │ │ │ │ └── customization_gui.0.213712161506.out │ │ ├── iseconfig │ │ │ ├── Lab5.projectmgr │ │ │ └── top.xreport │ │ ├── isim.cmd │ │ ├── isim.log │ │ ├── isim │ │ │ ├── isim_usage_statistics.html │ │ │ ├── pn_info │ │ │ ├── top_tb_isim_beh.exe.sim │ │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ │ ├── ISimEngine-DesignHierarchy1.dbg │ │ │ │ ├── isimcrash.log │ │ │ │ ├── isimkernel.log │ │ │ │ ├── netId.dat │ │ │ │ ├── netId1.dat │ │ │ │ ├── tmp_save │ │ │ │ │ └── _1 │ │ │ │ ├── top_tb_isim_beh.exe │ │ │ │ ├── unisims_ver │ │ │ │ │ ├── m_00000000000740258969_1625843133.c │ │ │ │ │ ├── m_00000000000740258969_1625843133.didat │ │ │ │ │ ├── m_00000000000740258969_1625843133.nt.obj │ │ │ │ │ ├── m_00000000000740258969_3897995058.c │ │ │ │ │ ├── m_00000000000740258969_3897995058.didat │ │ │ │ │ ├── m_00000000000740258969_3897995058.nt.obj │ │ │ │ │ ├── m_00000000001946988858_2297623829.c │ │ │ │ │ ├── m_00000000001946988858_2297623829.didat │ │ │ │ │ ├── m_00000000001946988858_2297623829.nt.obj │ │ │ │ │ ├── m_00000000002399568039_2282143210.c │ │ │ │ │ ├── m_00000000002399568039_2282143210.didat │ │ │ │ │ ├── m_00000000002399568039_2282143210.nt.obj │ │ │ │ │ ├── m_00000000002922998384_0762524165.c │ │ │ │ │ ├── m_00000000002922998384_0762524165.didat │ │ │ │ │ ├── m_00000000002922998384_0762524165.nt.obj │ │ │ │ │ ├── m_00000000003131622635_0225263307.c │ │ │ │ │ ├── m_00000000003131622635_0225263307.didat │ │ │ │ │ ├── m_00000000003131622635_0225263307.nt.obj │ │ │ │ │ ├── m_00000000003266096158_2593380106.c │ │ │ │ │ ├── m_00000000003266096158_2593380106.didat │ │ │ │ │ └── m_00000000003266096158_2593380106.nt.obj │ │ │ │ └── work │ │ │ │ │ ├── m_00000000000063944133_3115858369.c │ │ │ │ │ ├── m_00000000000063944133_3115858369.didat │ │ │ │ │ ├── m_00000000000063944133_3115858369.nt.obj │ │ │ │ │ ├── m_00000000000139310833_1306970619.c │ │ │ │ │ ├── m_00000000000139310833_1306970619.didat │ │ │ │ │ ├── m_00000000000139310833_1306970619.nt.obj │ │ │ │ │ ├── m_00000000000859371319_3823007873.c │ │ │ │ │ ├── m_00000000000859371319_3823007873.didat │ │ │ │ │ ├── m_00000000000859371319_3823007873.nt.obj │ │ │ │ │ ├── m_00000000001798480423_0886308060.c │ │ │ │ │ ├── m_00000000001798480423_0886308060.didat │ │ │ │ │ ├── m_00000000001798480423_0886308060.nt.obj │ │ │ │ │ ├── m_00000000001886194798_2244092194.c │ │ │ │ │ ├── m_00000000001886194798_2244092194.didat │ │ │ │ │ ├── m_00000000001886194798_2244092194.nt.obj │ │ │ │ │ ├── m_00000000002629890179_2032185554.c │ │ │ │ │ ├── m_00000000002629890179_2032185554.didat │ │ │ │ │ ├── m_00000000002629890179_2032185554.nt.obj │ │ │ │ │ ├── m_00000000003162073797_3913188552.c │ │ │ │ │ ├── m_00000000003162073797_3913188552.didat │ │ │ │ │ ├── m_00000000003162073797_3913188552.nt.obj │ │ │ │ │ ├── m_00000000003524194649_0967167703.c │ │ │ │ │ ├── m_00000000003524194649_0967167703.didat │ │ │ │ │ ├── m_00000000003524194649_0967167703.nt.obj │ │ │ │ │ ├── m_00000000003577048177_1151974483.c │ │ │ │ │ ├── m_00000000003577048177_1151974483.didat │ │ │ │ │ ├── m_00000000003577048177_1151974483.nt.obj │ │ │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ │ ├── m_00000000004134447467_2073120511.nt.obj │ │ │ │ │ ├── top_tb_isim_beh.exe_main.c │ │ │ │ │ └── top_tb_isim_beh.exe_main.nt.obj │ │ │ └── work │ │ │ │ ├── @a@l@u.sdb │ │ │ │ ├── @clk_gen.sdb │ │ │ │ ├── @ctr.sdb │ │ │ │ ├── @data_memory.sdb │ │ │ │ ├── @instruction_memory.sdb │ │ │ │ ├── glbl.sdb │ │ │ │ ├── register.sdb │ │ │ │ ├── signext.sdb │ │ │ │ ├── top.sdb │ │ │ │ └── top_tb.sdb │ │ ├── myucf.ucf │ │ ├── register │ │ ├── register.v │ │ ├── register_isim_beh.exe │ │ ├── signext.v │ │ ├── signext_isim_beh.exe │ │ ├── simulation │ │ │ ├── end.wcfg │ │ │ └── end1.wcfg │ │ ├── top.v │ │ ├── top_isim_beh.exe │ │ ├── top_stx_beh.prj │ │ ├── top_summary.html │ │ ├── top_tb.v │ │ ├── top_tb_beh.prj │ │ ├── top_tb_isim_beh.exe │ │ ├── top_tb_isim_beh.wdb │ │ ├── top_tb_isim_beh1.wdb │ │ └── xilinxsim.ini │ └── Lab5_4 │ │ ├── ALU.v │ │ ├── ALU_isim_beh.exe │ │ ├── ALU_isim_beh1.wdb │ │ ├── Ctr.v │ │ ├── Ctr_isim_beh.exe │ │ ├── Ctr_isim_beh1.wdb │ │ ├── Data │ │ ├── Data_memory.v │ │ ├── DmemB.mif │ │ ├── Instruction_memory.v │ │ ├── Instruction_memory_isim_beh.exe │ │ ├── Instruction_memory_isim_beh1.wdb │ │ ├── Lab5.gise │ │ ├── Lab5.xise │ │ ├── MIPS_Scope.cdc │ │ ├── _ngo │ │ ├── cs_icon_pro │ │ │ ├── _xmsgs │ │ │ │ └── xst.xmsgs │ │ │ ├── coregen.cgc │ │ │ ├── coregen.cgp │ │ │ ├── coregen.log │ │ │ ├── generate_icon_pro.xco │ │ │ ├── icon_pro.gise │ │ │ ├── icon_pro.ucf │ │ │ ├── icon_pro.vhd │ │ │ ├── icon_pro.vho │ │ │ ├── icon_pro.xco │ │ │ ├── icon_pro.xise │ │ │ ├── icon_pro_flist.txt │ │ │ ├── icon_pro_readme.txt │ │ │ ├── icon_pro_xmdf.tcl │ │ │ └── tmp │ │ │ │ └── _xmsgs │ │ │ │ └── pn_parser.xmsgs │ │ ├── cs_ila_pro_0 │ │ │ ├── _xmsgs │ │ │ │ └── xst.xmsgs │ │ │ ├── coregen.cgc │ │ │ ├── coregen.cgp │ │ │ ├── coregen.log │ │ │ ├── generate_ila_pro_0.xco │ │ │ ├── ila_pro_0.cdc │ │ │ ├── ila_pro_0.gise │ │ │ ├── ila_pro_0.ucf │ │ │ ├── ila_pro_0.vhd │ │ │ ├── ila_pro_0.vho │ │ │ ├── ila_pro_0.xco │ │ │ ├── ila_pro_0.xise │ │ │ ├── ila_pro_0_flist.txt │ │ │ ├── ila_pro_0_readme.txt │ │ │ ├── ila_pro_0_xmdf.tcl │ │ │ └── tmp │ │ │ │ └── _xmsgs │ │ │ │ └── pn_parser.xmsgs │ │ ├── icon_pro.ngc │ │ ├── ila_pro_0.ngc │ │ ├── netlist.lst │ │ ├── top_cs_signalbrowser.ngo │ │ └── top_cs_signalbrowser.ver │ │ ├── _xmsgs │ │ ├── bitgen.xmsgs │ │ ├── map.xmsgs │ │ ├── ngcbuild.xmsgs │ │ ├── ngdbuild.xmsgs │ │ ├── par.xmsgs │ │ ├── pn_parser.xmsgs │ │ ├── trce.xmsgs │ │ └── xst.xmsgs │ │ ├── data.coe │ │ ├── fuse.log │ │ ├── fuse.xmsgs │ │ ├── fuseRelaunch.cmd │ │ ├── instruction │ │ ├── instruction2 │ │ ├── ipcore_dir │ │ ├── Clk_gen.asy │ │ ├── Clk_gen.gise │ │ ├── Clk_gen.ncf │ │ ├── Clk_gen.sym │ │ ├── Clk_gen.ucf │ │ ├── Clk_gen.v │ │ ├── Clk_gen.veo │ │ ├── Clk_gen.xco │ │ ├── Clk_gen.xdc │ │ ├── Clk_gen.xise │ │ ├── Clk_gen │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ ├── doc │ │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ │ ├── clk_wiz_v3_6_vinfo.html │ │ │ │ └── pg065_clk_wiz.pdf │ │ │ ├── example_design │ │ │ │ ├── Clk_gen_exdes.ucf │ │ │ │ ├── Clk_gen_exdes.v │ │ │ │ └── Clk_gen_exdes.xdc │ │ │ ├── implement │ │ │ │ ├── implement.bat │ │ │ │ ├── implement.sh │ │ │ │ ├── planAhead_ise.bat │ │ │ │ ├── planAhead_ise.sh │ │ │ │ ├── planAhead_ise.tcl │ │ │ │ ├── planAhead_rdn.bat │ │ │ │ ├── planAhead_rdn.sh │ │ │ │ ├── planAhead_rdn.tcl │ │ │ │ ├── xst.prj │ │ │ │ └── xst.scr │ │ │ └── simulation │ │ │ │ ├── Clk_gen_tb.v │ │ │ │ ├── functional │ │ │ │ ├── simcmds.tcl │ │ │ │ ├── simulate_isim.bat │ │ │ │ ├── simulate_isim.sh │ │ │ │ ├── simulate_mti.bat │ │ │ │ ├── simulate_mti.do │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ ├── simulate_vcs.sh │ │ │ │ ├── ucli_commands.key │ │ │ │ ├── vcs_session.tcl │ │ │ │ ├── wave.do │ │ │ │ └── wave.sv │ │ │ │ └── timing │ │ │ │ ├── Clk_gen_tb.v │ │ │ │ ├── sdf_cmd_file │ │ │ │ ├── simcmds.tcl │ │ │ │ ├── simulate_isim.sh │ │ │ │ ├── simulate_mti.bat │ │ │ │ ├── simulate_mti.do │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ ├── simulate_vcs.sh │ │ │ │ ├── ucli_commands.key │ │ │ │ ├── vcs_session.tcl │ │ │ │ └── wave.do │ │ ├── Clk_gen_flist.txt │ │ ├── Clk_gen_xmdf.tcl │ │ ├── DmemB.asy │ │ ├── DmemB.gise │ │ ├── DmemB.mif │ │ ├── DmemB.ngc │ │ ├── DmemB.sym │ │ ├── DmemB.v │ │ ├── DmemB.veo │ │ ├── DmemB.xco │ │ ├── DmemB.xise │ │ ├── DmemB │ │ │ ├── blk_mem_gen_v7_3_readme.txt │ │ │ ├── doc │ │ │ │ ├── blk_mem_gen_v7_3_vinfo.html │ │ │ │ └── pg058-blk-mem-gen.pdf │ │ │ ├── example_design │ │ │ │ ├── DmemB_exdes.ucf │ │ │ │ ├── DmemB_exdes.vhd │ │ │ │ ├── DmemB_exdes.xdc │ │ │ │ └── DmemB_prod.vhd │ │ │ ├── implement │ │ │ │ ├── implement.bat │ │ │ │ ├── implement.sh │ │ │ │ ├── planAhead_ise.bat │ │ │ │ ├── planAhead_ise.sh │ │ │ │ ├── planAhead_ise.tcl │ │ │ │ ├── xst.prj │ │ │ │ └── xst.scr │ │ │ └── simulation │ │ │ │ ├── DmemB_synth.vhd │ │ │ │ ├── DmemB_tb.vhd │ │ │ │ ├── addr_gen.vhd │ │ │ │ ├── bmg_stim_gen.vhd │ │ │ │ ├── bmg_tb_pkg.vhd │ │ │ │ ├── checker.vhd │ │ │ │ ├── data_gen.vhd │ │ │ │ ├── functional │ │ │ │ ├── simcmds.tcl │ │ │ │ ├── simulate_isim.bat │ │ │ │ ├── simulate_mti.bat │ │ │ │ ├── simulate_mti.do │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ ├── simulate_vcs.sh │ │ │ │ ├── ucli_commands.key │ │ │ │ ├── vcs_session.tcl │ │ │ │ ├── wave_mti.do │ │ │ │ └── wave_ncsim.sv │ │ │ │ ├── random.vhd │ │ │ │ └── timing │ │ │ │ ├── simcmds.tcl │ │ │ │ ├── simulate_isim.bat │ │ │ │ ├── simulate_mti.bat │ │ │ │ ├── simulate_mti.do │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ ├── simulate_vcs.sh │ │ │ │ ├── ucli_commands.key │ │ │ │ ├── vcs_session.tcl │ │ │ │ ├── wave_mti.do │ │ │ │ └── wave_ncsim.sv │ │ ├── DmemB_flist.txt │ │ ├── DmemB_xmdf.tcl │ │ ├── _xmsgs │ │ │ ├── cg.xmsgs │ │ │ └── pn_parser.xmsgs │ │ ├── coregen.cgp │ │ ├── coregen.log │ │ ├── create_Clk_gen.tcl │ │ ├── create_DmemB.tcl │ │ ├── data.coe │ │ ├── edit_Clk_gen.tcl │ │ ├── edit_DmemB.tcl │ │ ├── summary.log │ │ └── tmp │ │ │ ├── DmemB.lso │ │ │ ├── _cg │ │ │ └── _dbg │ │ │ │ ├── xil_418.in │ │ │ │ └── xil_418.out │ │ │ ├── _xmsgs │ │ │ ├── pn_parser.xmsgs │ │ │ └── xst.xmsgs │ │ │ └── customization_gui.0.213712161506.out │ │ ├── iseconfig │ │ ├── Lab5.projectmgr │ │ └── top.xreport │ │ ├── isim.cmd │ │ ├── isim.log │ │ ├── isim │ │ ├── isim_usage_statistics.html │ │ ├── pn_info │ │ ├── signext_isim_beh.exe.sim │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ ├── isimcrash.log │ │ │ ├── isimkernel.log │ │ │ ├── netId.dat │ │ │ ├── signext_isim_beh.exe │ │ │ ├── tmp_save │ │ │ │ └── _1 │ │ │ └── work │ │ │ │ ├── m_00000000003524194649_0967167703.c │ │ │ │ ├── m_00000000003524194649_0967167703.didat │ │ │ │ ├── m_00000000003524194649_0967167703.nt.obj │ │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ ├── m_00000000004134447467_2073120511.nt.obj │ │ │ │ ├── signext_isim_beh.exe_main.c │ │ │ │ └── signext_isim_beh.exe_main.nt.obj │ │ ├── top_isim_beh.exe.sim │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ ├── isimcrash.log │ │ │ ├── isimkernel.log │ │ │ ├── libPortability.dll │ │ │ ├── netId.dat │ │ │ ├── tmp_save │ │ │ │ └── _1 │ │ │ ├── top_isim_beh.exe │ │ │ ├── unisims_ver │ │ │ │ ├── m_00000000000740258969_1625843133.c │ │ │ │ ├── m_00000000000740258969_1625843133.didat │ │ │ │ ├── m_00000000000740258969_1625843133.nt64.obj │ │ │ │ ├── m_00000000000740258969_3897995058.c │ │ │ │ ├── m_00000000000740258969_3897995058.didat │ │ │ │ ├── m_00000000000740258969_3897995058.nt64.obj │ │ │ │ ├── m_00000000001946988858_2297623829.c │ │ │ │ ├── m_00000000001946988858_2297623829.didat │ │ │ │ ├── m_00000000001946988858_2297623829.nt64.obj │ │ │ │ ├── m_00000000002399568039_2282143210.c │ │ │ │ ├── m_00000000002399568039_2282143210.didat │ │ │ │ ├── m_00000000002399568039_2282143210.nt64.obj │ │ │ │ ├── m_00000000002922998384_0762524165.c │ │ │ │ ├── m_00000000002922998384_0762524165.didat │ │ │ │ ├── m_00000000002922998384_0762524165.nt64.obj │ │ │ │ ├── m_00000000003131622635_0225263307.c │ │ │ │ ├── m_00000000003131622635_0225263307.didat │ │ │ │ ├── m_00000000003131622635_0225263307.nt64.obj │ │ │ │ ├── m_00000000003266096158_2593380106.c │ │ │ │ ├── m_00000000003266096158_2593380106.didat │ │ │ │ └── m_00000000003266096158_2593380106.nt64.obj │ │ │ └── work │ │ │ │ ├── m_00000000000139310833_1306970619.c │ │ │ │ ├── m_00000000000139310833_1306970619.didat │ │ │ │ ├── m_00000000000139310833_1306970619.nt64.obj │ │ │ │ ├── m_00000000001886194798_2244092194.c │ │ │ │ ├── m_00000000001886194798_2244092194.didat │ │ │ │ ├── m_00000000001886194798_2244092194.nt64.obj │ │ │ │ ├── m_00000000002504749971_3823007873.c │ │ │ │ ├── m_00000000002504749971_3823007873.didat │ │ │ │ ├── m_00000000002504749971_3823007873.nt64.obj │ │ │ │ ├── m_00000000002629890179_2032185554.c │ │ │ │ ├── m_00000000002629890179_2032185554.didat │ │ │ │ ├── m_00000000002629890179_2032185554.nt64.obj │ │ │ │ ├── m_00000000003162073797_3913188552.c │ │ │ │ ├── m_00000000003162073797_3913188552.didat │ │ │ │ ├── m_00000000003162073797_3913188552.nt64.obj │ │ │ │ ├── m_00000000003524194649_0967167703.c │ │ │ │ ├── m_00000000003524194649_0967167703.didat │ │ │ │ ├── m_00000000003524194649_0967167703.nt64.obj │ │ │ │ ├── m_00000000003577048177_1151974483.c │ │ │ │ ├── m_00000000003577048177_1151974483.didat │ │ │ │ ├── m_00000000003577048177_1151974483.nt64.obj │ │ │ │ ├── m_00000000003865117803_0886308060.c │ │ │ │ ├── m_00000000003865117803_0886308060.didat │ │ │ │ ├── m_00000000003865117803_0886308060.nt64.obj │ │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ ├── m_00000000004134447467_2073120511.nt64.obj │ │ │ │ ├── top_isim_beh.exe_main.c │ │ │ │ └── top_isim_beh.exe_main.nt64.obj │ │ ├── top_tb_isim_beh.exe.sim │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ ├── isimcrash.log │ │ │ ├── isimkernel.log │ │ │ ├── netId.dat │ │ │ ├── tmp_save │ │ │ │ └── _1 │ │ │ ├── top_tb_isim_beh.exe │ │ │ ├── unisims_ver │ │ │ │ ├── m_00000000000740258969_1625843133.c │ │ │ │ ├── m_00000000000740258969_1625843133.didat │ │ │ │ ├── m_00000000000740258969_1625843133.nt.obj │ │ │ │ ├── m_00000000000740258969_3897995058.c │ │ │ │ ├── m_00000000000740258969_3897995058.didat │ │ │ │ ├── m_00000000000740258969_3897995058.nt.obj │ │ │ │ ├── m_00000000001946988858_2297623829.c │ │ │ │ ├── m_00000000001946988858_2297623829.didat │ │ │ │ ├── m_00000000001946988858_2297623829.nt.obj │ │ │ │ ├── m_00000000002399568039_2282143210.c │ │ │ │ ├── m_00000000002399568039_2282143210.didat │ │ │ │ ├── m_00000000002399568039_2282143210.nt.obj │ │ │ │ ├── m_00000000002922998384_0762524165.c │ │ │ │ ├── m_00000000002922998384_0762524165.didat │ │ │ │ ├── m_00000000002922998384_0762524165.nt.obj │ │ │ │ ├── m_00000000003131622635_0225263307.c │ │ │ │ ├── m_00000000003131622635_0225263307.didat │ │ │ │ ├── m_00000000003131622635_0225263307.nt.obj │ │ │ │ ├── m_00000000003266096158_2593380106.c │ │ │ │ ├── m_00000000003266096158_2593380106.didat │ │ │ │ └── m_00000000003266096158_2593380106.nt.obj │ │ │ └── work │ │ │ │ ├── m_00000000000139310833_1306970619.c │ │ │ │ ├── m_00000000000139310833_1306970619.didat │ │ │ │ ├── m_00000000000139310833_1306970619.nt.obj │ │ │ │ ├── m_00000000000204716602_3115858369.c │ │ │ │ ├── m_00000000000204716602_3115858369.didat │ │ │ │ ├── m_00000000000204716602_3115858369.nt.obj │ │ │ │ ├── m_00000000001886194798_2244092194.c │ │ │ │ ├── m_00000000001886194798_2244092194.didat │ │ │ │ ├── m_00000000001886194798_2244092194.nt.obj │ │ │ │ ├── m_00000000002504749971_3823007873.c │ │ │ │ ├── m_00000000002504749971_3823007873.didat │ │ │ │ ├── m_00000000002504749971_3823007873.nt.obj │ │ │ │ ├── m_00000000002629890179_2032185554.c │ │ │ │ ├── m_00000000002629890179_2032185554.didat │ │ │ │ ├── m_00000000002629890179_2032185554.nt.obj │ │ │ │ ├── m_00000000003162073797_3913188552.c │ │ │ │ ├── m_00000000003162073797_3913188552.didat │ │ │ │ ├── m_00000000003162073797_3913188552.nt.obj │ │ │ │ ├── m_00000000003524194649_0967167703.c │ │ │ │ ├── m_00000000003524194649_0967167703.didat │ │ │ │ ├── m_00000000003524194649_0967167703.nt.obj │ │ │ │ ├── m_00000000003577048177_1151974483.c │ │ │ │ ├── m_00000000003577048177_1151974483.didat │ │ │ │ ├── m_00000000003577048177_1151974483.nt.obj │ │ │ │ ├── m_00000000003865117803_0886308060.c │ │ │ │ ├── m_00000000003865117803_0886308060.didat │ │ │ │ ├── m_00000000003865117803_0886308060.nt.obj │ │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ │ ├── m_00000000004134447467_2073120511.nt.obj │ │ │ │ ├── top_tb_isim_beh.exe_main.c │ │ │ │ └── top_tb_isim_beh.exe_main.nt.obj │ │ └── work │ │ │ ├── @a@l@u.sdb │ │ │ ├── @clk_gen.sdb │ │ │ ├── @ctr.sdb │ │ │ ├── @data_memory.sdb │ │ │ ├── @instruction_memory.sdb │ │ │ ├── glbl.sdb │ │ │ ├── register.sdb │ │ │ ├── signext.sdb │ │ │ ├── top.sdb │ │ │ └── top_tb.sdb │ │ ├── myucf.ucf │ │ ├── par_usage_statistics.html │ │ ├── register │ │ ├── register.v │ │ ├── register_isim_beh.exe │ │ ├── signext.v │ │ ├── signext_isim_beh.exe │ │ ├── simulation │ │ ├── end.wcfg │ │ └── end1.wcfg │ │ ├── top.bgn │ │ ├── top.bit │ │ ├── top.bld │ │ ├── top.cmd_log │ │ ├── top.drc │ │ ├── top.lso │ │ ├── top.ncd │ │ ├── top.ngc │ │ ├── top.ngd │ │ ├── top.ngr │ │ ├── top.pad │ │ ├── top.par │ │ ├── top.pcf │ │ ├── top.prj │ │ ├── top.ptwx │ │ ├── top.stx │ │ ├── top.syr │ │ ├── top.twr │ │ ├── top.twx │ │ ├── top.unroutes │ │ ├── top.ut │ │ ├── top.v │ │ ├── top.xpi │ │ ├── top.xst │ │ ├── top_bitgen.xwbt │ │ ├── top_cs.blc │ │ ├── top_cs.ngc │ │ ├── top_envsettings.html │ │ ├── top_guide.ncd │ │ ├── top_isim_beh.exe │ │ ├── top_map.map │ │ ├── top_map.mrp │ │ ├── top_map.ncd │ │ ├── top_map.ngm │ │ ├── top_map.xrpt │ │ ├── top_ngdbuild.xrpt │ │ ├── top_pad.csv │ │ ├── top_pad.txt │ │ ├── top_par.xrpt │ │ ├── top_stx_beh.prj │ │ ├── top_summary.html │ │ ├── top_summary.xml │ │ ├── top_tb.v │ │ ├── top_tb_beh.prj │ │ ├── top_tb_isim_beh.exe │ │ ├── top_tb_isim_beh.wdb │ │ ├── top_tb_isim_beh1.wdb │ │ ├── top_usage.xml │ │ ├── top_xst.xrpt │ │ ├── usage_statistics_webtalk.html │ │ ├── webtalk.log │ │ ├── webtalk_pn.xml │ │ ├── xilinxsim.ini │ │ ├── xlnx_auto_0_xdb │ │ └── cst.xbcd │ │ └── xst │ │ └── work │ │ ├── work.sdbl │ │ └── work.sdbx └── 目录说明以及使用注意事项.txt ├── MIPS单周期流处理器 源码 ├── ALU.v ├── ALU_isim_beh.exe ├── ALU_summary.html ├── Ctr.v ├── Data ├── Data_memory.v ├── Data_memory_isim_beh.exe ├── Data_memory_isim_beh1.wdb ├── Instruction_memory.v ├── Instruction_memory_isim_beh.exe ├── Lab4_2.gise ├── Lab4_2.xise ├── _xmsgs │ └── pn_parser.xmsgs ├── fuse.log ├── fuse.xmsgs ├── fuseRelaunch.cmd ├── instruction ├── ipcore_dir │ ├── Clk_gen.asy │ ├── Clk_gen.gise │ ├── Clk_gen.sym │ ├── Clk_gen.ucf │ ├── Clk_gen.v │ ├── Clk_gen.veo │ ├── Clk_gen.xco │ ├── Clk_gen.xdc │ ├── Clk_gen.xise │ ├── Clk_gen │ │ ├── clk_wiz_v3_6_readme.txt │ │ ├── doc │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ ├── clk_wiz_v3_6_vinfo.html │ │ │ └── pg065_clk_wiz.pdf │ │ ├── example_design │ │ │ ├── Clk_gen_exdes.ucf │ │ │ ├── Clk_gen_exdes.v │ │ │ └── Clk_gen_exdes.xdc │ │ ├── implement │ │ │ ├── implement.bat │ │ │ ├── implement.sh │ │ │ ├── planAhead_ise.bat │ │ │ ├── planAhead_ise.sh │ │ │ ├── planAhead_ise.tcl │ │ │ ├── planAhead_rdn.bat │ │ │ ├── planAhead_rdn.sh │ │ │ ├── planAhead_rdn.tcl │ │ │ ├── xst.prj │ │ │ └── xst.scr │ │ └── simulation │ │ │ ├── Clk_gen_tb.v │ │ │ ├── functional │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_isim.bat │ │ │ ├── simulate_isim.sh │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_vcs.sh │ │ │ ├── ucli_commands.key │ │ │ ├── vcs_session.tcl │ │ │ ├── wave.do │ │ │ └── wave.sv │ │ │ └── timing │ │ │ ├── Clk_gen_tb.v │ │ │ ├── sdf_cmd_file │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_isim.sh │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_vcs.sh │ │ │ ├── ucli_commands.key │ │ │ ├── vcs_session.tcl │ │ │ └── wave.do │ ├── Clk_gen_flist.txt │ ├── Clk_gen_xmdf.tcl │ ├── _xmsgs │ │ ├── cg.xmsgs │ │ └── pn_parser.xmsgs │ ├── coregen.cgp │ ├── coregen.log │ ├── create_Clk_gen.tcl │ ├── edit_Clk_gen.tcl │ └── tmp │ │ ├── _cg │ │ └── _dbg │ │ │ ├── xil_152.in │ │ │ └── xil_152.out │ │ ├── _xmsgs │ │ └── pn_parser.xmsgs │ │ └── customization_gui.0.0913053695538.out ├── iseconfig │ ├── ALU.xreport │ ├── Lab4_2.projectmgr │ └── top.xreport ├── isim.cmd ├── isim.log ├── isim │ ├── Instruction_memory_isim_beh.exe.sim │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ ├── Instruction_memory_isim_beh.exe │ │ ├── isimcrash.log │ │ ├── isimkernel.log │ │ ├── netId.dat │ │ ├── tmp_save │ │ │ └── _1 │ │ └── work │ │ │ ├── Instruction_memory_isim_beh.exe_main.c │ │ │ ├── Instruction_memory_isim_beh.exe_main.nt.obj │ │ │ ├── m_00000000001806517667_2032185554.c │ │ │ ├── m_00000000001806517667_2032185554.didat │ │ │ ├── m_00000000001806517667_2032185554.nt.obj │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ └── m_00000000004134447467_2073120511.nt.obj │ ├── isim_usage_statistics.html │ ├── pn_info │ ├── top_tb_isim_beh.exe.sim │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ ├── isimcrash.log │ │ ├── isimkernel.log │ │ ├── netId.dat │ │ ├── tmp_save │ │ │ └── _1 │ │ ├── top_tb_isim_beh.exe │ │ ├── unisims_ver │ │ │ ├── m_00000000000740258969_1625843133.c │ │ │ ├── m_00000000000740258969_1625843133.didat │ │ │ ├── m_00000000000740258969_1625843133.nt.obj │ │ │ ├── m_00000000000740258969_3897995058.c │ │ │ ├── m_00000000000740258969_3897995058.didat │ │ │ ├── m_00000000000740258969_3897995058.nt.obj │ │ │ ├── m_00000000001946988858_2297623829.c │ │ │ ├── m_00000000001946988858_2297623829.didat │ │ │ ├── m_00000000001946988858_2297623829.nt.obj │ │ │ ├── m_00000000002399568039_2282143210.c │ │ │ ├── m_00000000002399568039_2282143210.didat │ │ │ ├── m_00000000002399568039_2282143210.nt.obj │ │ │ ├── m_00000000002922998384_0762524165.c │ │ │ ├── m_00000000002922998384_0762524165.didat │ │ │ ├── m_00000000002922998384_0762524165.nt.obj │ │ │ ├── m_00000000003131622635_0225263307.c │ │ │ ├── m_00000000003131622635_0225263307.didat │ │ │ ├── m_00000000003131622635_0225263307.nt.obj │ │ │ ├── m_00000000003266096158_2593380106.c │ │ │ ├── m_00000000003266096158_2593380106.didat │ │ │ └── m_00000000003266096158_2593380106.nt.obj │ │ └── work │ │ │ ├── m_00000000000063944133_3115858369.c │ │ │ ├── m_00000000000063944133_3115858369.didat │ │ │ ├── m_00000000000063944133_3115858369.nt.obj │ │ │ ├── m_00000000000139310833_1306970619.c │ │ │ ├── m_00000000000139310833_1306970619.didat │ │ │ ├── m_00000000000139310833_1306970619.nt.obj │ │ │ ├── m_00000000001638485174_0886308060.c │ │ │ ├── m_00000000001638485174_0886308060.didat │ │ │ ├── m_00000000001638485174_0886308060.nt.obj │ │ │ ├── m_00000000001806517667_2032185554.c │ │ │ ├── m_00000000001806517667_2032185554.didat │ │ │ ├── m_00000000001806517667_2032185554.nt.obj │ │ │ ├── m_00000000002127762115_2244092194.c │ │ │ ├── m_00000000002127762115_2244092194.didat │ │ │ ├── m_00000000002127762115_2244092194.nt.obj │ │ │ ├── m_00000000003162073797_3913188552.c │ │ │ ├── m_00000000003162073797_3913188552.didat │ │ │ ├── m_00000000003162073797_3913188552.nt.obj │ │ │ ├── m_00000000003524194649_0967167703.c │ │ │ ├── m_00000000003524194649_0967167703.didat │ │ │ ├── m_00000000003524194649_0967167703.nt.obj │ │ │ ├── m_00000000003577048177_1151974483.c │ │ │ ├── m_00000000003577048177_1151974483.didat │ │ │ ├── m_00000000003577048177_1151974483.nt.obj │ │ │ ├── m_00000000004057003703_3823007873.c │ │ │ ├── m_00000000004057003703_3823007873.didat │ │ │ ├── m_00000000004057003703_3823007873.nt.obj │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ ├── m_00000000004134447467_2073120511.nt.obj │ │ │ ├── top_tb_isim_beh.exe_main.c │ │ │ └── top_tb_isim_beh.exe_main.nt.obj │ └── work │ │ ├── @a@l@u.sdb │ │ ├── @clk_gen.sdb │ │ ├── @ctr.sdb │ │ ├── @data_memory.sdb │ │ ├── @instruction_memory.sdb │ │ ├── glbl.sdb │ │ ├── register.sdb │ │ ├── signext.sdb │ │ ├── top.sdb │ │ └── top_tb.sdb ├── myucf.ucf ├── register ├── register.v ├── signext.v ├── simulation │ └── end.wcfg ├── top.v ├── top_isim_beh.exe ├── top_summary.html ├── top_tb.v ├── top_tb_beh.prj ├── top_tb_isim_beh.exe ├── top_tb_isim_beh.wdb ├── top_tb_isim_beh1.wdb └── xilinxsim.ini ├── MIPS多周期流水化处理器 报告.doc ├── MIPS多周期流水化处理器 源码 ├── ALU.v ├── ALU_isim_beh.exe ├── ALU_isim_beh1.wdb ├── Ctr.v ├── Ctr_isim_beh.exe ├── Ctr_isim_beh1.wdb ├── Data ├── Data_memory.v ├── DmemB.mif ├── Instruction_memory.v ├── Instruction_memory_isim_beh.exe ├── Instruction_memory_isim_beh1.wdb ├── Lab5.gise ├── Lab5.xise ├── MIPS_Scope.cdc ├── _ngo │ ├── cs_icon_pro │ │ ├── _xmsgs │ │ │ └── xst.xmsgs │ │ ├── coregen.cgc │ │ ├── coregen.cgp │ │ ├── coregen.log │ │ ├── generate_icon_pro.xco │ │ ├── icon_pro.gise │ │ ├── icon_pro.ucf │ │ ├── icon_pro.vhd │ │ ├── icon_pro.vho │ │ ├── icon_pro.xco │ │ ├── icon_pro.xise │ │ ├── icon_pro_flist.txt │ │ ├── icon_pro_readme.txt │ │ ├── icon_pro_xmdf.tcl │ │ └── tmp │ │ │ └── _xmsgs │ │ │ └── pn_parser.xmsgs │ ├── cs_ila_pro_0 │ │ ├── _xmsgs │ │ │ └── xst.xmsgs │ │ ├── coregen.cgc │ │ ├── coregen.cgp │ │ ├── coregen.log │ │ ├── generate_ila_pro_0.xco │ │ ├── ila_pro_0.cdc │ │ ├── ila_pro_0.gise │ │ ├── ila_pro_0.ucf │ │ ├── ila_pro_0.vhd │ │ ├── ila_pro_0.vho │ │ ├── ila_pro_0.xco │ │ ├── ila_pro_0.xise │ │ ├── ila_pro_0_flist.txt │ │ ├── ila_pro_0_readme.txt │ │ ├── ila_pro_0_xmdf.tcl │ │ └── tmp │ │ │ └── _xmsgs │ │ │ └── pn_parser.xmsgs │ ├── icon_pro.ngc │ ├── ila_pro_0.ngc │ ├── netlist.lst │ ├── top_cs_signalbrowser.ngo │ └── top_cs_signalbrowser.ver ├── _xmsgs │ ├── bitgen.xmsgs │ ├── map.xmsgs │ ├── ngcbuild.xmsgs │ ├── ngdbuild.xmsgs │ ├── par.xmsgs │ ├── pn_parser.xmsgs │ ├── trce.xmsgs │ └── xst.xmsgs ├── data.coe ├── fuse.log ├── fuse.xmsgs ├── fuseRelaunch.cmd ├── instruction ├── instruction2 ├── ipcore_dir │ ├── Clk_gen.asy │ ├── Clk_gen.gise │ ├── Clk_gen.ncf │ ├── Clk_gen.sym │ ├── Clk_gen.ucf │ ├── Clk_gen.v │ ├── Clk_gen.veo │ ├── Clk_gen.xco │ ├── Clk_gen.xdc │ ├── Clk_gen.xise │ ├── Clk_gen │ │ ├── clk_wiz_v3_6_readme.txt │ │ ├── doc │ │ │ ├── clk_wiz_v3_6_readme.txt │ │ │ ├── clk_wiz_v3_6_vinfo.html │ │ │ └── pg065_clk_wiz.pdf │ │ ├── example_design │ │ │ ├── Clk_gen_exdes.ucf │ │ │ ├── Clk_gen_exdes.v │ │ │ └── Clk_gen_exdes.xdc │ │ ├── implement │ │ │ ├── implement.bat │ │ │ ├── implement.sh │ │ │ ├── planAhead_ise.bat │ │ │ ├── planAhead_ise.sh │ │ │ ├── planAhead_ise.tcl │ │ │ ├── planAhead_rdn.bat │ │ │ ├── planAhead_rdn.sh │ │ │ ├── planAhead_rdn.tcl │ │ │ ├── xst.prj │ │ │ └── xst.scr │ │ └── simulation │ │ │ ├── Clk_gen_tb.v │ │ │ ├── functional │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_isim.bat │ │ │ ├── simulate_isim.sh │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_vcs.sh │ │ │ ├── ucli_commands.key │ │ │ ├── vcs_session.tcl │ │ │ ├── wave.do │ │ │ └── wave.sv │ │ │ └── timing │ │ │ ├── Clk_gen_tb.v │ │ │ ├── sdf_cmd_file │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_isim.sh │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_vcs.sh │ │ │ ├── ucli_commands.key │ │ │ ├── vcs_session.tcl │ │ │ └── wave.do │ ├── Clk_gen_flist.txt │ ├── Clk_gen_xmdf.tcl │ ├── DmemB.asy │ ├── DmemB.gise │ ├── DmemB.mif │ ├── DmemB.ngc │ ├── DmemB.sym │ ├── DmemB.v │ ├── DmemB.veo │ ├── DmemB.xco │ ├── DmemB.xise │ ├── DmemB │ │ ├── blk_mem_gen_v7_3_readme.txt │ │ ├── doc │ │ │ ├── blk_mem_gen_v7_3_vinfo.html │ │ │ └── pg058-blk-mem-gen.pdf │ │ ├── example_design │ │ │ ├── DmemB_exdes.ucf │ │ │ ├── DmemB_exdes.vhd │ │ │ ├── DmemB_exdes.xdc │ │ │ └── DmemB_prod.vhd │ │ ├── implement │ │ │ ├── implement.bat │ │ │ ├── implement.sh │ │ │ ├── planAhead_ise.bat │ │ │ ├── planAhead_ise.sh │ │ │ ├── planAhead_ise.tcl │ │ │ ├── xst.prj │ │ │ └── xst.scr │ │ └── simulation │ │ │ ├── DmemB_synth.vhd │ │ │ ├── DmemB_tb.vhd │ │ │ ├── addr_gen.vhd │ │ │ ├── bmg_stim_gen.vhd │ │ │ ├── bmg_tb_pkg.vhd │ │ │ ├── checker.vhd │ │ │ ├── data_gen.vhd │ │ │ ├── functional │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_isim.bat │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_vcs.sh │ │ │ ├── ucli_commands.key │ │ │ ├── vcs_session.tcl │ │ │ ├── wave_mti.do │ │ │ └── wave_ncsim.sv │ │ │ ├── random.vhd │ │ │ └── timing │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_isim.bat │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_vcs.sh │ │ │ ├── ucli_commands.key │ │ │ ├── vcs_session.tcl │ │ │ ├── wave_mti.do │ │ │ └── wave_ncsim.sv │ ├── DmemB_flist.txt │ ├── DmemB_xmdf.tcl │ ├── _xmsgs │ │ ├── cg.xmsgs │ │ └── pn_parser.xmsgs │ ├── coregen.cgp │ ├── coregen.log │ ├── create_Clk_gen.tcl │ ├── create_DmemB.tcl │ ├── data.coe │ ├── edit_Clk_gen.tcl │ ├── edit_DmemB.tcl │ ├── summary.log │ └── tmp │ │ ├── DmemB.lso │ │ ├── _cg │ │ └── _dbg │ │ │ ├── xil_418.in │ │ │ └── xil_418.out │ │ ├── _xmsgs │ │ ├── pn_parser.xmsgs │ │ └── xst.xmsgs │ │ └── customization_gui.0.213712161506.out ├── iseconfig │ ├── Lab5.projectmgr │ └── top.xreport ├── isim.cmd ├── isim.log ├── isim │ ├── isim_usage_statistics.html │ ├── pn_info │ ├── signext_isim_beh.exe.sim │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ ├── isimcrash.log │ │ ├── isimkernel.log │ │ ├── netId.dat │ │ ├── signext_isim_beh.exe │ │ ├── tmp_save │ │ │ └── _1 │ │ └── work │ │ │ ├── m_00000000003524194649_0967167703.c │ │ │ ├── m_00000000003524194649_0967167703.didat │ │ │ ├── m_00000000003524194649_0967167703.nt.obj │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ ├── m_00000000004134447467_2073120511.nt.obj │ │ │ ├── signext_isim_beh.exe_main.c │ │ │ └── signext_isim_beh.exe_main.nt.obj │ ├── top_isim_beh.exe.sim │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ ├── isimcrash.log │ │ ├── isimkernel.log │ │ ├── libPortability.dll │ │ ├── netId.dat │ │ ├── tmp_save │ │ │ └── _1 │ │ ├── top_isim_beh.exe │ │ ├── unisims_ver │ │ │ ├── m_00000000000740258969_1625843133.c │ │ │ ├── m_00000000000740258969_1625843133.didat │ │ │ ├── m_00000000000740258969_1625843133.nt64.obj │ │ │ ├── m_00000000000740258969_3897995058.c │ │ │ ├── m_00000000000740258969_3897995058.didat │ │ │ ├── m_00000000000740258969_3897995058.nt64.obj │ │ │ ├── m_00000000001946988858_2297623829.c │ │ │ ├── m_00000000001946988858_2297623829.didat │ │ │ ├── m_00000000001946988858_2297623829.nt64.obj │ │ │ ├── m_00000000002399568039_2282143210.c │ │ │ ├── m_00000000002399568039_2282143210.didat │ │ │ ├── m_00000000002399568039_2282143210.nt64.obj │ │ │ ├── m_00000000002922998384_0762524165.c │ │ │ ├── m_00000000002922998384_0762524165.didat │ │ │ ├── m_00000000002922998384_0762524165.nt64.obj │ │ │ ├── m_00000000003131622635_0225263307.c │ │ │ ├── m_00000000003131622635_0225263307.didat │ │ │ ├── m_00000000003131622635_0225263307.nt64.obj │ │ │ ├── m_00000000003266096158_2593380106.c │ │ │ ├── m_00000000003266096158_2593380106.didat │ │ │ └── m_00000000003266096158_2593380106.nt64.obj │ │ └── work │ │ │ ├── m_00000000000139310833_1306970619.c │ │ │ ├── m_00000000000139310833_1306970619.didat │ │ │ ├── m_00000000000139310833_1306970619.nt64.obj │ │ │ ├── m_00000000001886194798_2244092194.c │ │ │ ├── m_00000000001886194798_2244092194.didat │ │ │ ├── m_00000000001886194798_2244092194.nt64.obj │ │ │ ├── m_00000000002504749971_3823007873.c │ │ │ ├── m_00000000002504749971_3823007873.didat │ │ │ ├── m_00000000002504749971_3823007873.nt64.obj │ │ │ ├── m_00000000002629890179_2032185554.c │ │ │ ├── m_00000000002629890179_2032185554.didat │ │ │ ├── m_00000000002629890179_2032185554.nt64.obj │ │ │ ├── m_00000000003162073797_3913188552.c │ │ │ ├── m_00000000003162073797_3913188552.didat │ │ │ ├── m_00000000003162073797_3913188552.nt64.obj │ │ │ ├── m_00000000003524194649_0967167703.c │ │ │ ├── m_00000000003524194649_0967167703.didat │ │ │ ├── m_00000000003524194649_0967167703.nt64.obj │ │ │ ├── m_00000000003577048177_1151974483.c │ │ │ ├── m_00000000003577048177_1151974483.didat │ │ │ ├── m_00000000003577048177_1151974483.nt64.obj │ │ │ ├── m_00000000003865117803_0886308060.c │ │ │ ├── m_00000000003865117803_0886308060.didat │ │ │ ├── m_00000000003865117803_0886308060.nt64.obj │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ ├── m_00000000004134447467_2073120511.nt64.obj │ │ │ ├── top_isim_beh.exe_main.c │ │ │ └── top_isim_beh.exe_main.nt64.obj │ ├── top_tb_isim_beh.exe.sim │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ ├── isimcrash.log │ │ ├── isimkernel.log │ │ ├── netId.dat │ │ ├── tmp_save │ │ │ └── _1 │ │ ├── top_tb_isim_beh.exe │ │ ├── unisims_ver │ │ │ ├── m_00000000000740258969_1625843133.c │ │ │ ├── m_00000000000740258969_1625843133.didat │ │ │ ├── m_00000000000740258969_1625843133.nt.obj │ │ │ ├── m_00000000000740258969_3897995058.c │ │ │ ├── m_00000000000740258969_3897995058.didat │ │ │ ├── m_00000000000740258969_3897995058.nt.obj │ │ │ ├── m_00000000001946988858_2297623829.c │ │ │ ├── m_00000000001946988858_2297623829.didat │ │ │ ├── m_00000000001946988858_2297623829.nt.obj │ │ │ ├── m_00000000002399568039_2282143210.c │ │ │ ├── m_00000000002399568039_2282143210.didat │ │ │ ├── m_00000000002399568039_2282143210.nt.obj │ │ │ ├── m_00000000002922998384_0762524165.c │ │ │ ├── m_00000000002922998384_0762524165.didat │ │ │ ├── m_00000000002922998384_0762524165.nt.obj │ │ │ ├── m_00000000003131622635_0225263307.c │ │ │ ├── m_00000000003131622635_0225263307.didat │ │ │ ├── m_00000000003131622635_0225263307.nt.obj │ │ │ ├── m_00000000003266096158_2593380106.c │ │ │ ├── m_00000000003266096158_2593380106.didat │ │ │ └── m_00000000003266096158_2593380106.nt.obj │ │ └── work │ │ │ ├── m_00000000000139310833_1306970619.c │ │ │ ├── m_00000000000139310833_1306970619.didat │ │ │ ├── m_00000000000139310833_1306970619.nt.obj │ │ │ ├── m_00000000000204716602_3115858369.c │ │ │ ├── m_00000000000204716602_3115858369.didat │ │ │ ├── m_00000000000204716602_3115858369.nt.obj │ │ │ ├── m_00000000001886194798_2244092194.c │ │ │ ├── m_00000000001886194798_2244092194.didat │ │ │ ├── m_00000000001886194798_2244092194.nt.obj │ │ │ ├── m_00000000002504749971_3823007873.c │ │ │ ├── m_00000000002504749971_3823007873.didat │ │ │ ├── m_00000000002504749971_3823007873.nt.obj │ │ │ ├── m_00000000002629890179_2032185554.c │ │ │ ├── m_00000000002629890179_2032185554.didat │ │ │ ├── m_00000000002629890179_2032185554.nt.obj │ │ │ ├── m_00000000003162073797_3913188552.c │ │ │ ├── m_00000000003162073797_3913188552.didat │ │ │ ├── m_00000000003162073797_3913188552.nt.obj │ │ │ ├── m_00000000003524194649_0967167703.c │ │ │ ├── m_00000000003524194649_0967167703.didat │ │ │ ├── m_00000000003524194649_0967167703.nt.obj │ │ │ ├── m_00000000003577048177_1151974483.c │ │ │ ├── m_00000000003577048177_1151974483.didat │ │ │ ├── m_00000000003577048177_1151974483.nt.obj │ │ │ ├── m_00000000003865117803_0886308060.c │ │ │ ├── m_00000000003865117803_0886308060.didat │ │ │ ├── m_00000000003865117803_0886308060.nt.obj │ │ │ ├── m_00000000004134447467_2073120511.c │ │ │ ├── m_00000000004134447467_2073120511.didat │ │ │ ├── m_00000000004134447467_2073120511.nt.obj │ │ │ ├── top_tb_isim_beh.exe_main.c │ │ │ └── top_tb_isim_beh.exe_main.nt.obj │ └── work │ │ ├── @a@l@u.sdb │ │ ├── @clk_gen.sdb │ │ ├── @ctr.sdb │ │ ├── @data_memory.sdb │ │ ├── @instruction_memory.sdb │ │ ├── glbl.sdb │ │ ├── register.sdb │ │ ├── signext.sdb │ │ ├── top.sdb │ │ └── top_tb.sdb ├── myucf.ucf ├── par_usage_statistics.html ├── register ├── register.v ├── register_isim_beh.exe ├── signext.v ├── signext_isim_beh.exe ├── simulation │ ├── end.wcfg │ └── end1.wcfg ├── top.bgn ├── top.bit ├── top.bld ├── top.cmd_log ├── top.drc ├── top.lso ├── top.ncd ├── top.ngc ├── top.ngd ├── top.ngr ├── top.pad ├── top.par ├── top.pcf ├── top.prj ├── top.ptwx ├── top.stx ├── top.syr ├── top.twr ├── top.twx ├── top.unroutes ├── top.ut ├── top.v ├── top.xpi ├── top.xst ├── top_bitgen.xwbt ├── top_cs.blc ├── top_cs.ngc ├── top_envsettings.html ├── top_guide.ncd ├── top_isim_beh.exe ├── top_map.map ├── top_map.mrp ├── top_map.ncd ├── top_map.ngm ├── top_map.xrpt ├── top_ngdbuild.xrpt ├── top_pad.csv ├── top_pad.txt ├── top_par.xrpt ├── top_stx_beh.prj ├── top_summary.html ├── top_summary.xml ├── top_tb.v ├── top_tb_beh.prj ├── top_tb_isim_beh.exe ├── top_tb_isim_beh.wdb ├── top_tb_isim_beh1.wdb ├── top_usage.xml ├── top_xst.xrpt ├── usage_statistics_webtalk.html ├── webtalk.log ├── webtalk_pn.xml ├── xilinxsim.ini ├── xlnx_auto_0_xdb │ └── cst.xbcd └── xst │ └── work │ ├── work.sdbl │ └── work.sdbx ├── MIPS多周期流水化处理器 设计图.jpg └── README.md /.gitattributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/.gitattributes -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/.gitignore -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_doc/lab01.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_doc/lab01.pdf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_doc/lab02.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_doc/lab02.pdf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_doc/lab03.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_doc/lab03.pdf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_doc/lab04.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_doc/lab04.pdf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_doc/lab05.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_doc/lab05.pdf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/Lab1.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/Lab1.gise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/Lab1.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/Lab1.xise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | E:\JmingProjects\ISE\Lab1\top.ngc 1435839040 2 | OK 3 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/_xmsgs/map.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/_xmsgs/map.xmsgs -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/_xmsgs/par.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/_xmsgs/par.xmsgs -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/_xmsgs/xst.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/_xmsgs/xst.xmsgs -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/myucf.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/myucf.ucf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.bgn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.bgn -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.bit -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.bld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.bld -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.cmd_log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.cmd_log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.drc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.drc -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.ncd -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.ngc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.ngc -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.ngd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.ngd -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.ngr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.ngr -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.pad: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.pad -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.par: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.par -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.pcf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.pcf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.prj: -------------------------------------------------------------------------------- 1 | verilog work "top.v" 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.ptwx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.ptwx -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.stx: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.syr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.syr -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.twr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.twr -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.twx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.twx -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.unroutes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.unroutes -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.ut: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.ut -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=OFF 4 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.xst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top.xst -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_bitgen.xwbt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_bitgen.xwbt -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_guide.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_guide.ncd -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_map.map: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_map.map -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_map.mrp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_map.mrp -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_map.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_map.ncd -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_map.ngm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_map.ngm -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_map.xrpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_map.xrpt -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_pad.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_pad.csv -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_pad.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_pad.txt -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_par.xrpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_par.xrpt -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_summary.html -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_tb.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_usage.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_usage.xml -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_xst.xrpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/top_xst.xrpt -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/webtalk.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab1/webtalk.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/ALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/ALU.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/ALU_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/ALU_tb.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/Ctr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/Ctr.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/Ctr_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/Ctr_tb.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/Lab2.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/Lab2.gise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/Lab2.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/Lab2.xise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/fuse.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/fuse.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/fuse.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/fuse.xmsgs -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/isim.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/isim.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/isim/ALU_tb_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/isim/Ctr_tb_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab2/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/Data: -------------------------------------------------------------------------------- 1 | 1 2 | 10 3 | 3 4 | 4 5 | 5 6 | 6 7 | 7 8 | 10 -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/Data_memory.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/Data_memory.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/Instruction_memory.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/Instruction_memory.prj: -------------------------------------------------------------------------------- 1 | verilog work "Instruction_memory.v" 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/Lab3.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/Lab3.gise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/Lab3.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/Lab3.xise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/fuse.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/fuse.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/fuse.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/fuse.xmsgs -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/instruction: -------------------------------------------------------------------------------- 1 | 11 2 | 7 3 | 5 -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/isim.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/isim.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/isim/Data_memory_tb_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/isim/Instruction_memory_tb_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/isim/register_tb_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/register: -------------------------------------------------------------------------------- 1 | 10 2 | 9 3 | 8 4 | 7 5 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/register.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/register_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/register_tb.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab3/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/ALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/ALU.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/Clk_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/Clk_gen.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/Ctr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/Ctr.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/Data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/Data -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/Data_memory.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/Data_memory.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/Lab4.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/Lab4.gise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/Lab4.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/Lab4.xise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/fuse.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/fuse.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/fuse.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/fuse.xmsgs -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/instruction: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/instruction -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/ipcore_dir/xaw2verilog.log: -------------------------------------------------------------------------------- 1 | xaw2verilog: Completed successfully 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/myucf.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/myucf.ucf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/register.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/top.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/top_tb.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/xaw2verilog.log: -------------------------------------------------------------------------------- 1 | xaw2verilog: Completed successfully 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/ALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/ALU.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/Ctr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/Ctr.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/Lab4_1.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/Lab4_1.gise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/Lab4_1.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/Lab4_1.xise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/fuse.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/fuse.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/fuse.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/fuse.xmsgs -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/ipcore_dir/Clk_gen/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/myucf.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/myucf.ucf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/register.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/top.cmd_log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/top.cmd_log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/top.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/top.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/top.prj -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/top.syr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/top.syr -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/top.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/top.xst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/top.xst -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/top_tb.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_1/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/ALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/ALU.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/Ctr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/Ctr.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/Data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/Data -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/Lab4_2.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/Lab4_2.gise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/Lab4_2.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/Lab4_2.xise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/fuse.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/fuse.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/fuse.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/fuse.xmsgs -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/instruction: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/instruction -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/ipcore_dir/Clk_gen/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/isim.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/isim.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/isim/top_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/isim/top_tb_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/myucf.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/myucf.ucf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/register: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/register -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/register.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/signext.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/signext.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/top.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/top_tb.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab4_2/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/ALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/ALU.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/Ctr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/Ctr.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/Data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/Data -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/DmemB.mif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/DmemB.mif -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/Lab5.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/Lab5.gise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/Lab5.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/Lab5.xise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/data.coe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/data.coe -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/fuse.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/fuse.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/fuse.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/fuse.xmsgs -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/instruction: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/instruction -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/ipcore_dir/Clk_gen/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/ipcore_dir/DmemB/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/DmemB_exdes.vhd 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/ipcore_dir/tmp/DmemB.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/isim.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/isim.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/isim/top_tb_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/myucf.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/myucf.ucf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/register: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/register -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/register.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/signext.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/signext.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/top.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/top_tb.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_1/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/ALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/ALU.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/Ctr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/Ctr.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/Data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/Data -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/DmemB.mif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/DmemB.mif -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/Lab5.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/Lab5.gise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/Lab5.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/Lab5.xise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/data.coe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/data.coe -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/fuse.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/fuse.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/fuse.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/fuse.xmsgs -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/instruction: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/instruction -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/ipcore_dir/Clk_gen/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/ipcore_dir/DmemB/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/DmemB_exdes.vhd 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/ipcore_dir/tmp/DmemB.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/isim.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/isim.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/isim/top_tb_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/myucf.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/myucf.ucf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/register: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/register -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/register.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/signext.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/signext.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/top.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/top_tb.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_2/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/ALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/ALU.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/Ctr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/Ctr.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/Data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/Data -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/DmemB.mif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/DmemB.mif -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/Lab5.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/Lab5.gise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/Lab5.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/Lab5.xise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/data.coe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/data.coe -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/fuse.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/fuse.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/fuse.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/fuse.xmsgs -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/instruction: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/instruction -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/ipcore_dir/Clk_gen/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/ipcore_dir/DmemB/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/DmemB_exdes.vhd 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/ipcore_dir/tmp/DmemB.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/isim.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/isim.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/isim/top_tb_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/myucf.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/myucf.ucf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/register: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/register -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/register.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/signext.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/signext.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/top.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/top_tb.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_3/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/ALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/ALU.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/Ctr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/Ctr.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/Data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/Data -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/DmemB.mif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/DmemB.mif -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/Lab5.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/Lab5.gise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/Lab5.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/Lab5.xise -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | E:\JmingProjects\ISE\Lab5_4\top_cs.ngc 1437029680 2 | OK 3 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/_ngo/top_cs_signalbrowser.ver: -------------------------------------------------------------------------------- 1 | ISE Version 14.7.0 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/data.coe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/data.coe -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/fuse.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/fuse.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/fuse.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/fuse.xmsgs -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/instruction: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/instruction -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/ipcore_dir/Clk_gen/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/ipcore_dir/DmemB/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/DmemB_exdes.vhd 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/ipcore_dir/tmp/DmemB.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/isim.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/isim.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/isim/signext_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/isim/top_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/isim/top_tb_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/myucf.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/myucf.ucf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/register: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/register -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/register.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/signext.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/signext.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.bgn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.bgn -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.bit -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.bld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.bld -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.cmd_log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.cmd_log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.drc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.drc -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.ncd -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.ngc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.ngc -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.ngd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.ngd -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.ngr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.ngr -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.pad: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.pad -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.par: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.par -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.pcf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.pcf -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.prj -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.ptwx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.ptwx -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.stx: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.syr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.syr -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.twr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.twr -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.twx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.twx -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.ut: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.ut -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=YES 4 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.xst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top.xst -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_cs.blc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_cs.blc -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_cs.ngc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_cs.ngc -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_map.map: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_map.map -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_map.mrp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_map.mrp -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_map.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_map.ncd -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_map.ngm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_map.ngm -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_pad.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_pad.csv -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_pad.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_pad.txt -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/top_tb.v -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/webtalk.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/webtalk.log -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/lab_solution by JmingS and HminL/Lab5_4/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /FPGA小学期MIPS-CPU设计指导（参考资料）/目录说明以及使用注意事项.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/FPGA小学期MIPS-CPU设计指导（参考资料）/目录说明以及使用注意事项.txt -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ALU.v -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ALU_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ALU_isim_beh.exe -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ALU_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ALU_summary.html -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/Ctr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/Ctr.v -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/Data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/Data -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/Data_memory.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/Data_memory.v -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/Data_memory_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/Data_memory_isim_beh.exe -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/Data_memory_isim_beh1.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/Data_memory_isim_beh1.wdb -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/Instruction_memory.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/Instruction_memory.v -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/Instruction_memory_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/Instruction_memory_isim_beh.exe -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/Lab4_2.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/Lab4_2.gise -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/Lab4_2.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/Lab4_2.xise -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/_xmsgs/pn_parser.xmsgs -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/fuse.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/fuse.log -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/fuse.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/fuse.xmsgs -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/fuseRelaunch.cmd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/fuseRelaunch.cmd -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/instruction: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/instruction -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.asy: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.asy -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.gise -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.sym: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.sym -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.ucf -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.v -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.veo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.veo -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.xco: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.xco -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.xdc -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen.xise -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/clk_wiz_v3_6_readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/clk_wiz_v3_6_readme.txt -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/doc/clk_wiz_v3_6_readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/doc/clk_wiz_v3_6_readme.txt -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/doc/clk_wiz_v3_6_vinfo.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/doc/clk_wiz_v3_6_vinfo.html -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/doc/pg065_clk_wiz.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/doc/pg065_clk_wiz.pdf -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/example_design/Clk_gen_exdes.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/example_design/Clk_gen_exdes.ucf -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/example_design/Clk_gen_exdes.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/example_design/Clk_gen_exdes.v -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/example_design/Clk_gen_exdes.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/example_design/Clk_gen_exdes.xdc -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/implement.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/implement.bat -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/implement.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/implement.sh -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_ise.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_ise.bat -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_ise.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_ise.sh -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_ise.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_ise.tcl -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_rdn.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_rdn.bat -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_rdn.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_rdn.sh -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_rdn.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_rdn.tcl -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/xst.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/xst.prj -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/xst.scr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/implement/xst.scr -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/Clk_gen_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/Clk_gen_tb.v -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simcmds.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simcmds.tcl -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_isim.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_isim.bat -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_isim.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_isim.sh -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_mti.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_mti.bat -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_mti.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_mti.do -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_mti.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_mti.sh -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_ncsim.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_ncsim.sh -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_vcs.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_vcs.sh -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/ucli_commands.key: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/ucli_commands.key -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/vcs_session.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/vcs_session.tcl -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/wave.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/wave.do -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/wave.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/functional/wave.sv -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/Clk_gen_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/Clk_gen_tb.v -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/sdf_cmd_file: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/sdf_cmd_file -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simcmds.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simcmds.tcl -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_isim.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_isim.sh -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_mti.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_mti.bat -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_mti.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_mti.do -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_mti.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_mti.sh -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_ncsim.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_ncsim.sh -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_vcs.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_vcs.sh -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/ucli_commands.key: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/ucli_commands.key -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/wave.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen/simulation/timing/wave.do -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen_flist.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen_flist.txt -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/Clk_gen_xmdf.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/Clk_gen_xmdf.tcl -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/_xmsgs/cg.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/_xmsgs/cg.xmsgs -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/_xmsgs/pn_parser.xmsgs -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/coregen.cgp -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/coregen.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/coregen.log -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/create_Clk_gen.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/create_Clk_gen.tcl -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/edit_Clk_gen.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/edit_Clk_gen.tcl -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/tmp/_cg/_dbg/xil_152.in: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/tmp/_cg/_dbg/xil_152.in -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/tmp/_cg/_dbg/xil_152.out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/tmp/_cg/_dbg/xil_152.out -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/ipcore_dir/tmp/customization_gui.0.0913053695538.out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/ipcore_dir/tmp/customization_gui.0.0913053695538.out -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/iseconfig/ALU.xreport: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/iseconfig/ALU.xreport -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/iseconfig/Lab4_2.projectmgr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/iseconfig/Lab4_2.projectmgr -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/iseconfig/top.xreport: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/iseconfig/top.xreport -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim.log -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/Instruction_memory_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/Instruction_memory_isim_beh.exe.sim/isimkernel.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/Instruction_memory_isim_beh.exe.sim/isimkernel.log -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/Instruction_memory_isim_beh.exe.sim/netId.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/Instruction_memory_isim_beh.exe.sim/netId.dat -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/Instruction_memory_isim_beh.exe.sim/tmp_save/_1: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/Instruction_memory_isim_beh.exe.sim/tmp_save/_1 -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/isim_usage_statistics.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/isim_usage_statistics.html -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/top_tb_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/top_tb_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/top_tb_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/top_tb_isim_beh.exe.sim/isimkernel.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/top_tb_isim_beh.exe.sim/isimkernel.log -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/top_tb_isim_beh.exe.sim/netId.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/top_tb_isim_beh.exe.sim/netId.dat -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/top_tb_isim_beh.exe.sim/tmp_save/_1: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/top_tb_isim_beh.exe.sim/tmp_save/_1 -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/top_tb_isim_beh.exe.sim/top_tb_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/top_tb_isim_beh.exe.sim/top_tb_isim_beh.exe -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/top_tb_isim_beh.exe.sim/work/top_tb_isim_beh.exe_main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/top_tb_isim_beh.exe.sim/work/top_tb_isim_beh.exe_main.c -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/work/@a@l@u.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/work/@a@l@u.sdb -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/work/@clk_gen.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/work/@clk_gen.sdb -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/work/@ctr.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/work/@ctr.sdb -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/work/@data_memory.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/work/@data_memory.sdb -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/work/@instruction_memory.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/work/@instruction_memory.sdb -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/work/glbl.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/work/glbl.sdb -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/work/register.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/work/register.sdb -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/work/signext.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/work/signext.sdb -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/work/top.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/work/top.sdb -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/isim/work/top_tb.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/isim/work/top_tb.sdb -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/myucf.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/myucf.ucf -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/register: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/register -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/register.v -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/signext.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/signext.v -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/simulation/end.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/simulation/end.wcfg -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/top.v -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/top_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/top_isim_beh.exe -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/top_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/top_summary.html -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/top_tb.v -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/top_tb_beh.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/top_tb_beh.prj -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/top_tb_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/top_tb_isim_beh.exe -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/top_tb_isim_beh.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/top_tb_isim_beh.wdb -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/top_tb_isim_beh1.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS单周期流处理器 源码/top_tb_isim_beh1.wdb -------------------------------------------------------------------------------- /MIPS单周期流处理器 源码/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 报告.doc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 报告.doc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ALU.v -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ALU_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ALU_isim_beh.exe -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ALU_isim_beh1.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ALU_isim_beh1.wdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/Ctr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/Ctr.v -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/Ctr_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/Ctr_isim_beh.exe -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/Ctr_isim_beh1.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/Ctr_isim_beh1.wdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/Data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/Data -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/Data_memory.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/Data_memory.v -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/DmemB.mif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/DmemB.mif -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/Instruction_memory.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/Instruction_memory.v -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/Instruction_memory_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/Instruction_memory_isim_beh.exe -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/Instruction_memory_isim_beh1.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/Instruction_memory_isim_beh1.wdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/Lab5.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/Lab5.gise -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/Lab5.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/Lab5.xise -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/MIPS_Scope.cdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/MIPS_Scope.cdc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/_xmsgs/xst.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/_xmsgs/xst.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/coregen.cgc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/coregen.cgc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/coregen.cgp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/coregen.cgp -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/coregen.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/coregen.log -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/generate_icon_pro.xco: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/generate_icon_pro.xco -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro.gise -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro.ucf -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro.vhd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro.vho: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro.vho -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro.xco: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro.xco -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro.xise -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro_flist.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro_flist.txt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro_readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro_readme.txt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro_xmdf.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/icon_pro_xmdf.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/tmp/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_icon_pro/tmp/_xmsgs/pn_parser.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/_xmsgs/xst.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/_xmsgs/xst.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/coregen.cgc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/coregen.cgc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/coregen.cgp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/coregen.cgp -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/coregen.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/coregen.log -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/generate_ila_pro_0.xco: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/generate_ila_pro_0.xco -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0.cdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0.cdc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0.gise -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0.ucf -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0.vhd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0.vho: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0.vho -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0.xco: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0.xco -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0.xise -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0_flist.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0_flist.txt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0_readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0_readme.txt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0_xmdf.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/ila_pro_0_xmdf.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/tmp/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/cs_ila_pro_0/tmp/_xmsgs/pn_parser.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/icon_pro.ngc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/icon_pro.ngc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/ila_pro_0.ngc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/ila_pro_0.ngc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | E:\JmingProjects\ISE\Lab5_4\top_cs.ngc 1437029680 2 | OK 3 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/top_cs_signalbrowser.ngo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_ngo/top_cs_signalbrowser.ngo -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_ngo/top_cs_signalbrowser.ver: -------------------------------------------------------------------------------- 1 | ISE Version 14.7.0 2 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_xmsgs/bitgen.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_xmsgs/bitgen.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_xmsgs/map.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_xmsgs/map.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_xmsgs/ngcbuild.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_xmsgs/ngcbuild.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_xmsgs/ngdbuild.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_xmsgs/ngdbuild.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_xmsgs/par.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_xmsgs/par.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_xmsgs/pn_parser.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_xmsgs/trce.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_xmsgs/trce.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/_xmsgs/xst.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/_xmsgs/xst.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/data.coe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/data.coe -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/fuse.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/fuse.log -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/fuse.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/fuse.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/fuseRelaunch.cmd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/fuseRelaunch.cmd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/instruction: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/instruction -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/instruction2: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/instruction2 -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.asy: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.asy -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.gise -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.ncf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.ncf -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.sym: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.sym -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.ucf -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.v -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.veo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.veo -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.xco: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.xco -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.xdc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen.xise -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/clk_wiz_v3_6_readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/clk_wiz_v3_6_readme.txt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/doc/clk_wiz_v3_6_readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/doc/clk_wiz_v3_6_readme.txt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/doc/clk_wiz_v3_6_vinfo.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/doc/clk_wiz_v3_6_vinfo.html -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/doc/pg065_clk_wiz.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/doc/pg065_clk_wiz.pdf -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/example_design/Clk_gen_exdes.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/example_design/Clk_gen_exdes.ucf -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/example_design/Clk_gen_exdes.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/example_design/Clk_gen_exdes.v -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/example_design/Clk_gen_exdes.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/example_design/Clk_gen_exdes.xdc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/implement.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/implement.bat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/implement.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/implement.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_ise.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_ise.bat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_ise.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_ise.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_ise.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_ise.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_rdn.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_rdn.bat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_rdn.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_rdn.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_rdn.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/planAhead_rdn.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/xst.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/xst.prj -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/xst.scr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/implement/xst.scr -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/Clk_gen_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/Clk_gen_tb.v -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simcmds.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simcmds.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_isim.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_isim.bat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_isim.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_isim.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_mti.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_mti.bat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_mti.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_mti.do -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_mti.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_mti.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_ncsim.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_ncsim.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_vcs.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/simulate_vcs.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/ucli_commands.key: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/ucli_commands.key -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/vcs_session.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/vcs_session.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/wave.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/wave.do -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/wave.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/functional/wave.sv -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/Clk_gen_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/Clk_gen_tb.v -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/sdf_cmd_file: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/sdf_cmd_file -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simcmds.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simcmds.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_isim.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_isim.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_mti.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_mti.bat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_mti.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_mti.do -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_mti.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_mti.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_ncsim.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_ncsim.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_vcs.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/simulate_vcs.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/ucli_commands.key: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/ucli_commands.key -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/wave.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen/simulation/timing/wave.do -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen_flist.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen_flist.txt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen_xmdf.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/Clk_gen_xmdf.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.asy: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.asy -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.gise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.gise -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.mif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.mif -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.ngc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.ngc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.sym: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.sym -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.v -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.veo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.veo -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.xco: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.xco -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.xise: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB.xise -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/blk_mem_gen_v7_3_readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/blk_mem_gen_v7_3_readme.txt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/doc/blk_mem_gen_v7_3_vinfo.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/doc/blk_mem_gen_v7_3_vinfo.html -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/doc/pg058-blk-mem-gen.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/doc/pg058-blk-mem-gen.pdf -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/example_design/DmemB_exdes.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/example_design/DmemB_exdes.ucf -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/example_design/DmemB_exdes.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/example_design/DmemB_exdes.vhd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/example_design/DmemB_exdes.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/example_design/DmemB_exdes.xdc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/example_design/DmemB_prod.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/example_design/DmemB_prod.vhd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/implement/implement.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/implement/implement.bat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/implement/implement.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/implement/implement.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/implement/planAhead_ise.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/implement/planAhead_ise.bat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/implement/planAhead_ise.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/implement/planAhead_ise.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/implement/planAhead_ise.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/implement/planAhead_ise.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/DmemB_exdes.vhd 2 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/implement/xst.scr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/implement/xst.scr -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/DmemB_synth.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/DmemB_synth.vhd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/DmemB_tb.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/DmemB_tb.vhd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/addr_gen.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/addr_gen.vhd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/bmg_stim_gen.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/bmg_stim_gen.vhd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/bmg_tb_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/bmg_tb_pkg.vhd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/checker.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/checker.vhd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/data_gen.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/data_gen.vhd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/simcmds.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/simcmds.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/simulate_isim.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/simulate_isim.bat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/simulate_mti.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/simulate_mti.bat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/simulate_mti.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/simulate_mti.do -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/simulate_mti.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/simulate_mti.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/simulate_ncsim.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/simulate_ncsim.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/simulate_vcs.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/simulate_vcs.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/ucli_commands.key: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/ucli_commands.key -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/vcs_session.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/vcs_session.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/wave_mti.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/wave_mti.do -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/wave_ncsim.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/functional/wave_ncsim.sv -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/random.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/random.vhd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/simcmds.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/simcmds.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/simulate_isim.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/simulate_isim.bat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/simulate_mti.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/simulate_mti.bat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/simulate_mti.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/simulate_mti.do -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/simulate_mti.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/simulate_mti.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/simulate_ncsim.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/simulate_ncsim.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/simulate_vcs.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/simulate_vcs.sh -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/ucli_commands.key: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/ucli_commands.key -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/vcs_session.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/wave_mti.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/wave_mti.do -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/wave_ncsim.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB/simulation/timing/wave_ncsim.sv -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB_flist.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB_flist.txt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/DmemB_xmdf.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/DmemB_xmdf.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/_xmsgs/cg.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/_xmsgs/cg.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/_xmsgs/pn_parser.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/coregen.cgp -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/coregen.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/coregen.log -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/create_Clk_gen.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/create_Clk_gen.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/create_DmemB.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/create_DmemB.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/data.coe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/data.coe -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/edit_Clk_gen.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/edit_Clk_gen.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/edit_DmemB.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/edit_DmemB.tcl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/summary.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/summary.log -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/tmp/DmemB.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/tmp/_cg/_dbg/xil_418.in: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/tmp/_cg/_dbg/xil_418.in -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/tmp/_cg/_dbg/xil_418.out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/tmp/_cg/_dbg/xil_418.out -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/tmp/_xmsgs/xst.xmsgs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/tmp/_xmsgs/xst.xmsgs -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/ipcore_dir/tmp/customization_gui.0.213712161506.out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/ipcore_dir/tmp/customization_gui.0.213712161506.out -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/iseconfig/Lab5.projectmgr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/iseconfig/Lab5.projectmgr -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/iseconfig/top.xreport: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/iseconfig/top.xreport -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim.log -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/isim_usage_statistics.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/isim_usage_statistics.html -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.7 2 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/signext_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/signext_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/signext_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/signext_isim_beh.exe.sim/isimkernel.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/signext_isim_beh.exe.sim/isimkernel.log -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/signext_isim_beh.exe.sim/netId.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/signext_isim_beh.exe.sim/netId.dat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/signext_isim_beh.exe.sim/signext_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/signext_isim_beh.exe.sim/signext_isim_beh.exe -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/signext_isim_beh.exe.sim/tmp_save/_1: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/signext_isim_beh.exe.sim/tmp_save/_1 -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/isimkernel.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/isimkernel.log -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/libPortability.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/libPortability.dll -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/netId.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/netId.dat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/tmp_save/_1: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/tmp_save/_1 -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/top_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/top_isim_beh.exe -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/work/top_isim_beh.exe_main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/top_isim_beh.exe.sim/work/top_isim_beh.exe_main.c -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_tb_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/top_tb_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_tb_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_tb_isim_beh.exe.sim/isimkernel.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/top_tb_isim_beh.exe.sim/isimkernel.log -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_tb_isim_beh.exe.sim/netId.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/top_tb_isim_beh.exe.sim/netId.dat -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_tb_isim_beh.exe.sim/tmp_save/_1: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/top_tb_isim_beh.exe.sim/tmp_save/_1 -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_tb_isim_beh.exe.sim/top_tb_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/top_tb_isim_beh.exe.sim/top_tb_isim_beh.exe -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/top_tb_isim_beh.exe.sim/work/top_tb_isim_beh.exe_main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/top_tb_isim_beh.exe.sim/work/top_tb_isim_beh.exe_main.c -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/work/@a@l@u.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/work/@a@l@u.sdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/work/@clk_gen.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/work/@clk_gen.sdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/work/@ctr.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/work/@ctr.sdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/work/@data_memory.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/work/@data_memory.sdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/work/@instruction_memory.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/work/@instruction_memory.sdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/work/glbl.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/work/glbl.sdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/work/register.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/work/register.sdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/work/signext.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/work/signext.sdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/work/top.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/work/top.sdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/isim/work/top_tb.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/isim/work/top_tb.sdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/myucf.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/myucf.ucf -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/par_usage_statistics.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/par_usage_statistics.html -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/register: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/register -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/register.v -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/register_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/register_isim_beh.exe -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/signext.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/signext.v -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/signext_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/signext_isim_beh.exe -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/simulation/end.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/simulation/end.wcfg -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/simulation/end1.wcfg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/simulation/end1.wcfg -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.bgn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.bgn -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.bit -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.bld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.bld -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.cmd_log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.cmd_log -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.drc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.drc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.ncd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.ngc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.ngc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.ngd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.ngd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.ngr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.ngr -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.pad: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.pad -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.par: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.par -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.pcf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.pcf -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.prj -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.ptwx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.ptwx -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.stx: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.syr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.syr -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.twr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.twr -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.twx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.twx -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.unroutes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.unroutes -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.ut: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.ut -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.v -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=YES 4 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top.xst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top.xst -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_bitgen.xwbt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_bitgen.xwbt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_cs.blc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_cs.blc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_cs.ngc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_cs.ngc -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_envsettings.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_envsettings.html -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_guide.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_guide.ncd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_isim_beh.exe -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_map.map: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_map.map -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_map.mrp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_map.mrp -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_map.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_map.ncd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_map.ngm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_map.ngm -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_map.xrpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_map.xrpt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_ngdbuild.xrpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_ngdbuild.xrpt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_pad.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_pad.csv -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_pad.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_pad.txt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_par.xrpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_par.xrpt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_stx_beh.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_stx_beh.prj -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_summary.html -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_summary.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_summary.xml -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_tb.v -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_tb_beh.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_tb_beh.prj -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_tb_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_tb_isim_beh.exe -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_tb_isim_beh.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_tb_isim_beh.wdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_tb_isim_beh1.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_tb_isim_beh1.wdb -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_usage.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_usage.xml -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/top_xst.xrpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/top_xst.xrpt -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/usage_statistics_webtalk.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/usage_statistics_webtalk.html -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/webtalk.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/webtalk.log -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/webtalk_pn.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/webtalk_pn.xml -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/xlnx_auto_0_xdb/cst.xbcd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/xlnx_auto_0_xdb/cst.xbcd -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/xst/work/work.sdbl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/xst/work/work.sdbl -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 源码/xst/work/work.sdbx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 源码/xst/work/work.sdbx -------------------------------------------------------------------------------- /MIPS多周期流水化处理器 设计图.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/MIPS多周期流水化处理器 设计图.jpg -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JianmingS/MIPS-architecture-CPU-design-based-on-FPGA/HEAD/README.md --------------------------------------------------------------------------------