├── bb-clk.jpg ├── ip ├── openofdm_tx │ ├── src │ │ ├── icmem_8.mem │ │ ├── icmem_16.mem │ │ ├── icmem_32.mem │ │ ├── icmem_64.mem │ │ ├── convenc.v │ │ ├── ram_simo.v │ │ ├── l_stf_rom.v │ │ ├── crc32_tx.v │ │ ├── ht_stf_rom.v │ │ ├── dot11_tx_tb.v │ │ ├── dpram.v │ │ ├── bimpy.v │ │ ├── ht_ltf_rom.v │ │ ├── axi_fifo_bram.v │ │ ├── modulation.v │ │ ├── convround.v │ │ └── bitreverse.v │ └── unit_test │ │ └── test_vec │ │ ├── tx_intf.mem │ │ └── ht_tx_intf_mem_mcs7_gi1_aggr0_byte100.mem ├── rx_intf │ ├── src │ │ ├── edge_to_flip.v │ │ ├── mv_avg.v │ │ ├── byte_to_word_fcs_sn_insert.v │ │ └── mv_avg_dual_ch.v │ └── unit_test │ │ └── adc_intf │ │ └── adc_intf_tb.v ├── tx_intf │ └── src │ │ ├── edge_to_flip.v │ │ ├── tx_interrupt_selection.v │ │ ├── ht_sig_crc_calc.v │ │ ├── div_int.v │ │ ├── csi_fuzzer.v │ │ └── dac_intf.v ├── xpu │ ├── src │ │ ├── edge_to_flip.v │ │ ├── tsf_timer.v │ │ ├── cca.v │ │ ├── n_sym_len14_pkt.v │ │ ├── dc_rm.v │ │ ├── cw_exp.v │ │ ├── fifo_sample_delay.v │ │ ├── iq_abs_avg.v │ │ ├── mv_avg.v │ │ ├── mv_avg_dual_ch.v │ │ ├── time_slice_gen.v │ │ └── rssi.v │ └── unit_test │ │ ├── fifo_sample_delay │ │ └── fifo_sample_delay_tb.v │ │ └── mv_avg │ │ └── test_vec │ │ └── test_data_in_out.m ├── board_def.v ├── ultra_scale_tcl_gen.sh ├── create_vivado_proj.sh ├── connect_openwifi_ip_ultra_scale.tcl ├── side_ch │ └── src │ │ ├── dpram.v │ │ ├── side_ch_s_axis.v │ │ ├── side_ch_counter.v │ │ └── side_ch_counter_event_cfg.v ├── parse_board_name.tcl └── connect_openwifi_ip.tcl ├── openwifi-logo.png ├── boards ├── e310v2 │ ├── README.assets │ │ └── struct.png │ ├── README.md │ └── set_files.tcl ├── pack_hdf_bit.sh ├── antsdr_e200 │ ├── set_files.tcl │ └── README.md ├── post_script_common.tcl ├── sdrpi │ ├── notets.md │ ├── set_files.tcl │ └── src │ │ ├── ccbob_constr.xdc │ │ ├── sdrpi_constr_lvds.xdc │ │ └── sdrpi_constr.xdc ├── antsdr │ ├── set_files.tcl │ ├── notes.md │ └── src │ │ ├── ccbob_constr.xdc │ │ ├── antsdr_constr.xdc │ │ ├── antsdr_constr_lvds.xdc │ │ └── system.xdc ├── zed_fmcs2 │ └── set_files.tcl ├── zc702_fmcs2 │ └── set_files.tcl ├── zc706_fmcs2 │ ├── set_files.tcl │ └── src │ │ └── system.xdc ├── neptunesdr │ ├── set_files.tcl │ └── src │ │ ├── neptunesdr_constr.xdc │ │ └── neptunesdr_constr_lvds.xdc ├── adrv9361z7035 │ └── set_files.tcl ├── adrv9364z7020 │ └── set_files.tcl ├── zcu102_fmcs2 │ ├── set_files.tcl │ └── src │ │ ├── system_wrapper.v │ │ └── system_top.v ├── sdk_update.sh ├── package_ip_complex.tcl ├── package_ip.tcl └── create_ip_repo.sh ├── get_git_rev.sh ├── .gitmodules ├── get_ip_openofdm_rx.sh ├── .gitattributes ├── CONTRIBUTING.md ├── prepare_adi_lib.sh ├── .github └── ISSUE_TEMPLATE │ └── issue-description.md ├── prepare_adi_board_ip.sh └── gpio_led.md /bb-clk.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JiaoXianjun/openwifi-hw/HEAD/bb-clk.jpg -------------------------------------------------------------------------------- /ip/openofdm_tx/src/icmem_8.mem: -------------------------------------------------------------------------------- 1 | 4000000000 2 | 2d4142d414 3 | 0000040000 4 | d2bec2d414 5 | -------------------------------------------------------------------------------- /openwifi-logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JiaoXianjun/openwifi-hw/HEAD/openwifi-logo.png -------------------------------------------------------------------------------- /boards/e310v2/README.assets/struct.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JiaoXianjun/openwifi-hw/HEAD/boards/e310v2/README.assets/struct.png -------------------------------------------------------------------------------- /ip/openofdm_tx/src/icmem_16.mem: -------------------------------------------------------------------------------- 1 | 4000000000 2 | 3b20d187de 3 | 2d4142d414 4 | 187de3b20d 5 | 0000040000 6 | e78223b20d 7 | d2bec2d414 8 | c4df3187de 9 | -------------------------------------------------------------------------------- /get_git_rev.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # xianjun.jiao@imec.be 4 | 5 | if git log -1 > /dev/null 2>&1; then 6 | GIT_REV=$(git log -1 --pretty=%h) 7 | else 8 | GIT_REV=ffffffff 9 | fi 10 | 11 | echo $GIT_REV 12 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "adi-hdl"] 2 | path = adi-hdl 3 | url = https://github.com/analogdevicesinc/hdl.git 4 | [submodule "ip/openofdm_rx"] 5 | path = ip/openofdm_rx 6 | url = https://github.com/open-sdr/openofdm.git 7 | -------------------------------------------------------------------------------- /get_ip_openofdm_rx.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | home_dir=$(pwd) 4 | 5 | set -x 6 | cd ip/ 7 | git submodule init openofdm_rx 8 | git submodule update openofdm_rx 9 | # cd openofdm_rx 10 | # git checkout dot11zynq 11 | # git pull origin dot11zynq 12 | 13 | cd $home_dir 14 | -------------------------------------------------------------------------------- /ip/openofdm_tx/src/icmem_32.mem: -------------------------------------------------------------------------------- 1 | 4000000000 2 | 3ec530c7c6 3 | 3b20d187de 4 | 3536d238e7 5 | 2d4142d414 6 | 238e73536d 7 | 187de3b20d 8 | 0c7c63ec53 9 | 0000040000 10 | f383a3ec53 11 | e78223b20d 12 | dc7193536d 13 | d2bec2d414 14 | cac93238e7 15 | c4df3187de 16 | c13ad0c7c6 17 | -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | *.v linguist-language=Verilog 2 | *.html linguist-generated 3 | *.htm linguist-generated 4 | *.c linguist-generated 5 | *.h linguist-generated 6 | .project linguist-generated 7 | *.xml linguist-generated 8 | *.xci linguist-generated 9 | *.tcl linguist-generated 10 | -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | CLA([Individual](https://users.ugent.be/~xjiao/openwifi-Individual.pdf), [Entity](https://users.ugent.be/~xjiao/openwifi-Entity.pdf)) needs to be signed and sent to Filip.Louagie@UGent.be before you contributing. 2 | 3 | CLA is generated by the [Project Harmony](http://www.harmonyagreements.org/index.html). 4 | -------------------------------------------------------------------------------- /ip/openofdm_tx/unit_test/test_vec/tx_intf.mem: -------------------------------------------------------------------------------- 1 | 0000000001000e0b 2 | 000003EC84006400 3 | cd0860002e000204 4 | f13c01d62000a637 5 | 0000af3bad086000 6 | 697262202c796f4a 7 | 7261707320746867 8 | 76696420666f206b 9 | 440a2c7974696e69 10 | 2072657468677561 11 | 6973796c4520666f 12 | 657269460a2c6d75 13 | 64657269736e692d 14 | 6165727420657720 15 | 0000000000000000 16 | -------------------------------------------------------------------------------- /ip/openofdm_tx/unit_test/test_vec/ht_tx_intf_mem_mcs7_gi1_aggr0_byte100.mem: -------------------------------------------------------------------------------- 1 | 00000000010002AB 2 | 000002E886006407 3 | cd0860002e000204 4 | f13c01d62000a637 5 | 0000af3bad086000 6 | 697262202c796f4a 7 | 7261707320746867 8 | 76696420666f206b 9 | 440a2c7974696e69 10 | 2072657468677561 11 | 6973796c4520666f 12 | 657269460a2c6d75 13 | 64657269736e692d 14 | 6165727420657720 15 | 0000000000000000 16 | -------------------------------------------------------------------------------- /ip/openofdm_tx/src/icmem_64.mem: -------------------------------------------------------------------------------- 1 | 4000000000 2 | 3fb120645f 3 | 3ec530c7c6 4 | 3d3e812940 5 | 3b20d187de 6 | 387161e2b6 7 | 3536d238e7 8 | 317902899e 9 | 2d4142d414 10 | 2899e31790 11 | 238e73536d 12 | 1e2b638716 13 | 187de3b20d 14 | 129403d3e8 15 | 0c7c63ec53 16 | 0645f3fb12 17 | 0000040000 18 | f9ba13fb12 19 | f383a3ec53 20 | ed6c03d3e8 21 | e78223b20d 22 | e1d4a38716 23 | dc7193536d 24 | d766231790 25 | d2bec2d414 26 | ce8702899e 27 | cac93238e7 28 | c78ea1e2b6 29 | c4df3187de 30 | c2c1812940 31 | c13ad0c7c6 32 | c04ee0645f 33 | -------------------------------------------------------------------------------- /boards/e310v2/README.md: -------------------------------------------------------------------------------- 1 | # ANTSDR-E310V2 2 | 3 | The AntSDR E310V2 is an upgraded version of the previous E310 model. Its system structure is shown in the following figure. 4 | 5 | ![struct](README.assets/struct.png) 6 | 7 | Based on the original version, we have optimized the RF performance, added a GPS module, increased an external 10M/PPS input interface, and used a VCXO. The combination of VCXO and external reference input with DAC can generate a more accurate and stable clock. In addition, the Ethernet on the PL makes it possible for E310V2 to be compatible with UHD for higher bandwidth transmission. 8 | -------------------------------------------------------------------------------- /ip/rx_intf/src/edge_to_flip.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | module edge_to_flip 4 | #( 5 | parameter TEMP0 = 16, 6 | parameter TEMP1 = 5 7 | ) 8 | ( 9 | input clk, 10 | input rstn, 11 | 12 | input data_in, 13 | output reg flip_output 14 | ); 15 | 16 | reg data_in_reg; 17 | always @(posedge clk) begin 18 | if (~rstn) begin 19 | data_in_reg <= 0; 20 | flip_output <= 0; 21 | end else begin 22 | data_in_reg <= data_in; 23 | flip_output <= ((data_in==1 && data_in_reg==0)?(~flip_output):flip_output); 24 | end 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /ip/tx_intf/src/edge_to_flip.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | module edge_to_flip 4 | #( 5 | parameter TEMP0 = 16, 6 | parameter TEMP1 = 5 7 | ) 8 | ( 9 | input clk, 10 | input rstn, 11 | 12 | input data_in, 13 | output reg flip_output 14 | ); 15 | 16 | reg data_in_reg; 17 | always @(posedge clk) begin 18 | if (~rstn) begin 19 | data_in_reg <= 0; 20 | flip_output <= 0; 21 | end else begin 22 | data_in_reg <= data_in; 23 | flip_output <= ((data_in==1 && data_in_reg==0)?(~flip_output):flip_output); 24 | end 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /ip/xpu/src/edge_to_flip.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | module edge_to_flip 4 | #( 5 | parameter TEMP0 = 16, 6 | parameter TEMP1 = 5 7 | ) 8 | ( 9 | input clk, 10 | input rstn, 11 | 12 | input data_in, 13 | output reg flip_output 14 | ); 15 | 16 | reg data_in_reg; 17 | always @(posedge clk) begin 18 | if (~rstn) begin 19 | data_in_reg <= 0; 20 | flip_output <= 0; 21 | end else begin 22 | data_in_reg <= data_in; 23 | flip_output <= ((data_in==1 && data_in_reg==0)?(~flip_output):flip_output); 24 | end 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /boards/pack_hdf_bit.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # // Author: Xianjun Jiao 4 | # // SPDX-FileCopyrightText: 2022 UGent 5 | # // SPDX-License-Identifier: AGPL-3.0-or-later 6 | 7 | BOARD_NAME_ALL="antsdr antsdr_e200 e310v2 sdrpi zc706_fmcs2 zed_fmcs2 zc702_fmcs2 adrv9361z7035 adrv9364z7020 zcu102_fmcs2 neptunesdr" 8 | for BOARD_NAME in $BOARD_NAME_ALL 9 | do 10 | tar -zcvf $BOARD_NAME/sdk/system_top_hw_platform_0/hdf_and_bit.tar.gz $BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf $BOARD_NAME/sdk/system_top_hw_platform_0/system_top.bit 11 | rm $BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf $BOARD_NAME/sdk/system_top_hw_platform_0/system_top.bit 12 | done 13 | -------------------------------------------------------------------------------- /boards/antsdr_e200/set_files.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2025 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | # files and directories for the board 6 | 7 | set files [list \ 8 | [file normalize "${origin_dir}/../../adi-hdl/library/common/ad_iobuf.v"] \ 9 | [file normalize "${origin_dir}/src/system_wrapper.v"] \ 10 | [file normalize "${origin_dir}/src/system.bd" ]\ 11 | [file normalize "${origin_dir}/src/system_top.v" ]\ 12 | ] 13 | 14 | set files_xdc [list \ 15 | [file normalize "$origin_dir/src/system.xdc"]\ 16 | ] 17 | 18 | set ip_repos [list \ 19 | [file normalize "$origin_dir/../../adi-hdl/library"]\ 20 | [file normalize "$origin_dir/ip_repo/"]\ 21 | ] 22 | 23 | set board_part_repos [] 24 | -------------------------------------------------------------------------------- /ip/openofdm_tx/src/convenc.v: -------------------------------------------------------------------------------- 1 | /* 2 | * convenc - convolutional encoder implementation with generator polynomials, g0 = 133 and g1 = 171, of rate R = 1/2 3 | * 4 | * Michael Tetemke Mehari michael.mehari@ugent.be 5 | */ 6 | 7 | module convenc 8 | ( 9 | input wire clk, 10 | input wire rst, 11 | 12 | input wire enc_en, 13 | input wire bit_in, 14 | output wire [1:0] bits_out 15 | ); 16 | 17 | reg [5:0] state; 18 | always @(posedge clk) 19 | if (rst) begin 20 | state <= 0; 21 | end else if(enc_en) begin 22 | state <= {state[4:0], bit_in}; 23 | end 24 | assign bits_out[0] = bit_in ^ state[0] ^ state[1] ^ state[2] ^ state[5]; 25 | assign bits_out[1] = bit_in ^ state[1] ^ state[2] ^ state[4] ^ state[5]; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /prepare_adi_lib.sh: -------------------------------------------------------------------------------- 1 | 2 | #!/bin/bash 3 | if [ "$#" -ne 1 ]; then 4 | echo "You must enter exactly 1 arguments: \$XILINX_DIR" 5 | exit 1 6 | fi 7 | 8 | XILINX_DIR=$1 9 | 10 | if [ -d "$XILINX_DIR/Vivado" ]; then 11 | echo "\$XILINX_DIR is found!" 12 | else 13 | echo "\$XILINX_DIR is not correct. Please check!" 14 | exit 1 15 | fi 16 | 17 | home_dir=$(pwd) 18 | 19 | set -x 20 | 21 | git submodule init adi-hdl 22 | git submodule update adi-hdl 23 | cd ./adi-hdl/ 24 | # git reset --hard 2019_r1 25 | # git reset --hard f61d9707eb0a62533efd6facab59ab2444da94c9 26 | git reset --hard 27 | git fetch 28 | git checkout 2022_R2 29 | git reset --hard 2022_R2 30 | 31 | # # the lib need to be built! 32 | source $XILINX_DIR/Vivado/2022.2/settings64.sh 33 | cd library/ 34 | make 35 | 36 | cd $home_dir 37 | -------------------------------------------------------------------------------- /ip/board_def.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | // board specific definitions 3 | 4 | // clock_speed.v has NUM_CLK_PER_US. The value is determined by .tcl (_high.tcl or _low.tcl) 5 | //`define NUM_CLK_PER_US 250 // 250MHz clock for ultrascale+ FPGA 6 | //`define NUM_CLK_PER_US 200 // 200MHz clock for fast FPGA, like -2 and above grade Zynq7000 7 | //`define NUM_CLK_PER_US 100 // 100MHz clock for slow FPGA, like -1 grade Zynq7000 8 | 9 | `define SAMPLING_RATE_MHZ 20 10 | `define ASSUMED_COUNTER_CLK_MHZ 10 // 10MHz is assumed in SW/driver for sub us resolutuion FPGA counters 11 | `define NUM_CLK_PER_SAMPLE ((`NUM_CLK_PER_US)/`SAMPLING_RATE_MHZ) 12 | `define COUNT_TOP_1M ((`NUM_CLK_PER_US)-1) 13 | `define COUNT_SCALE ((`NUM_CLK_PER_US)/(`ASSUMED_COUNTER_CLK_MHZ)) 14 | -------------------------------------------------------------------------------- /boards/e310v2/set_files.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2025 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | # files and directories for the board 6 | 7 | set files [list \ 8 | [file normalize "${origin_dir}/../../adi-hdl/library/common/ad_iobuf.v"] \ 9 | [file normalize "${origin_dir}/src/system_wrapper.v"] \ 10 | [file normalize "${origin_dir}/src/system.bd" ]\ 11 | [file normalize "${origin_dir}/src/system_top.v" ]\ 12 | [file normalize "${origin_dir}/src/ad5640_spi.v" ]\ 13 | [file normalize "${origin_dir}/src/ppsloop.v" ]\ 14 | ] 15 | 16 | set files_xdc [list \ 17 | [file normalize "$origin_dir/src/system.xdc"]\ 18 | ] 19 | 20 | set ip_repos [list \ 21 | [file normalize "$origin_dir/../../adi-hdl/library"]\ 22 | [file normalize "$origin_dir/ip_repo/"]\ 23 | ] 24 | 25 | set board_part_repos [] 26 | -------------------------------------------------------------------------------- /boards/post_script_common.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2025 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | # common operations for all boards at the end of openwifi.tcl 6 | 7 | open_bd_design {./src/system.bd} 8 | 9 | if {$BOARD_NAME!="rfsoc4x2"} { 10 | set_property CONFIG.FREQ_HZ 40000000 [get_bd_pins /util_ad9361_divclk/clk_out] 11 | } 12 | 13 | update_compile_order -fileset sources_1 14 | 15 | report_ip_status -name ip_status 16 | upgrade_ip [get_ips {system_rx_intf_0_0 system_tx_intf_0_0 system_openofdm_tx_0_0 system_xpu_0_0 system_side_ch_0_0}] -log ip_upgrade.log 17 | export_ip_user_files -of_objects [get_ips {system_rx_intf_0_0 system_tx_intf_0_0 system_openofdm_tx_0_0 system_xpu_0_0 system_side_ch_0_0}] -no_script -sync -force -quiet 18 | report_ip_status -name ip_status 19 | 20 | save_bd_design 21 | -------------------------------------------------------------------------------- /boards/sdrpi/notets.md: -------------------------------------------------------------------------------- 1 | #sdrpi for openwifi-hw 2 | 3 | ## Introduction 4 | [SDRPi](https://github.com/hexsdr/) is a SDR hardware platform based on [xilinx zynq7020](https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html) and [adi ad936x](https://www.analog.com/en/products/ad9361.html). 5 | 6 | SDRPi is a smart and powerful SDR platform according Raspberry Pi size.Hareware feature is : ZYNQ 7Z020CLG400 ,1GB DDR3 memory fo PS, 1G Ethernet RJ45 for PS,1G Ethernet RJ45 for PL, USB OTG(act as USB host or USB SLAVE ), dual USB uarts for PS and PL,on board USB to JTAG debuger,TF card , bootable QSPI FLASH and also 27 IOs from PL bank; AD9361 RF design is based FMCOMMS3 with RF amplifier.it also has a Ublox m8t GPS module and 40MHZ VCXO. 7 | It could be used as a traditional SDR device such as PlutoSDR or FMCOMMS2/3/4 with Xilinx evaluation board, and it also be used as hardware platform to support openwifi. -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/issue-description.md: -------------------------------------------------------------------------------- 1 | --- 2 | name: Issue description 3 | about: Please report issue by this template 4 | title: '' 5 | labels: '' 6 | assignees: '' 7 | 8 | --- 9 | 10 | 0. Could you send email to xianjun.jiao@ugent.be to introduce your self? 11 | 12 | 1. Our image is used directly or you build your own image? 13 | 14 | 2. What is your own modification? 15 | 16 | 3. Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision 17 | 18 | 4. Board/hardware type 19 | 20 | 5. WiFi channel number 21 | 22 | 6. Steps to reproduce the issue, and the related error message, screenshot, etc 23 | 24 | 7. Describe your debug efforts by Linux native tools, such as tcpdump and "cat /proc/interrupts" 25 | 26 | 8. Describe your debug efforts by: https://github.com/open-sdr/openwifi/blob/master/doc/README.md#Debug-methods 27 | 28 | 9. Any other thing we need to know for helping you better? 29 | -------------------------------------------------------------------------------- /boards/antsdr/set_files.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2025 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | # files and directories for the board 6 | 7 | set files [list \ 8 | [file normalize "${origin_dir}/../../adi-hdl/library/common/ad_iobuf.v"] \ 9 | [file normalize "${origin_dir}/src/system_wrapper.v"] \ 10 | [file normalize "${origin_dir}/src/system.bd" ]\ 11 | [file normalize "${origin_dir}/src/system_top.v" ]\ 12 | ] 13 | 14 | set files_xdc [list \ 15 | [file normalize "${origin_dir}/src/antsdr_constr.xdc"]\ 16 | [file normalize "${origin_dir}/src/antsdr_constr_lvds.xdc"]\ 17 | [file normalize "${origin_dir}/src/ccbob_constr.xdc"]\ 18 | [file normalize "$origin_dir/src/system.xdc"]\ 19 | ] 20 | 21 | set ip_repos [list \ 22 | [file normalize "$origin_dir/../../adi-hdl/library"]\ 23 | [file normalize "$origin_dir/ip_repo/"]\ 24 | ] 25 | 26 | set board_part_repos [] 27 | -------------------------------------------------------------------------------- /boards/sdrpi/set_files.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2025 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | # files and directories for the board 6 | 7 | set files [list \ 8 | [file normalize "${origin_dir}/../../adi-hdl/library/common/ad_iobuf.v"] \ 9 | [file normalize "${origin_dir}/src/system_wrapper.v"] \ 10 | [file normalize "${origin_dir}/src/system.bd" ]\ 11 | [file normalize "${origin_dir}/src/system_top.v" ]\ 12 | ] 13 | 14 | set files_xdc [list \ 15 | [file normalize "${origin_dir}/src/sdrpi_constr.xdc"]\ 16 | [file normalize "${origin_dir}/src/sdrpi_constr_lvds.xdc"]\ 17 | [file normalize "${origin_dir}/src/ccbob_constr.xdc"]\ 18 | [file normalize "$origin_dir/src/system.xdc"]\ 19 | ] 20 | 21 | set ip_repos [list \ 22 | [file normalize "$origin_dir/../../adi-hdl/library"]\ 23 | [file normalize "$origin_dir/ip_repo/"]\ 24 | ] 25 | 26 | set board_part_repos [] 27 | -------------------------------------------------------------------------------- /boards/zed_fmcs2/set_files.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2025 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | # files and directories for the board 6 | 7 | set files [list \ 8 | [file normalize "${origin_dir}/../../adi-hdl/library/common/ad_iobuf.v"] \ 9 | [file normalize "${origin_dir}/src/system_wrapper.v"] \ 10 | [file normalize "${origin_dir}/src/system.bd" ]\ 11 | [file normalize "${origin_dir}/src/system_top.v" ]\ 12 | ] 13 | 14 | set files_xdc [list \ 15 | [file normalize "$origin_dir/../../adi-hdl/projects/fmcomms2/zed/system_constr.xdc"]\ 16 | [file normalize "$origin_dir/../../adi-hdl/projects/common/zed/zed_system_constr.xdc"]\ 17 | [file normalize "$origin_dir/src/system.xdc"]\ 18 | ] 19 | 20 | set ip_repos [list \ 21 | [file normalize "$origin_dir/../../adi-hdl/library"]\ 22 | [file normalize "$origin_dir/ip_repo/"]\ 23 | ] 24 | 25 | set board_part_repos [] 26 | -------------------------------------------------------------------------------- /boards/zc702_fmcs2/set_files.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2025 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | # files and directories for the board 6 | 7 | set files [list \ 8 | [file normalize "${origin_dir}/../../adi-hdl/library/common/ad_iobuf.v"] \ 9 | [file normalize "${origin_dir}/src/system_wrapper.v"] \ 10 | [file normalize "${origin_dir}/src/system.bd" ]\ 11 | [file normalize "${origin_dir}/src/system_top.v" ]\ 12 | ] 13 | 14 | set files_xdc [list \ 15 | [file normalize "$origin_dir/../../adi-hdl/projects/fmcomms2/zc702/system_constr.xdc"]\ 16 | [file normalize "$origin_dir/../../adi-hdl/projects/common/zc702/zc702_system_constr.xdc"]\ 17 | [file normalize "$origin_dir/src/system.xdc"]\ 18 | ] 19 | 20 | set ip_repos [list \ 21 | [file normalize "$origin_dir/../../adi-hdl/library"]\ 22 | [file normalize "$origin_dir/ip_repo/"]\ 23 | ] 24 | 25 | set board_part_repos [] 26 | -------------------------------------------------------------------------------- /boards/zc706_fmcs2/set_files.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2025 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | # files and directories for the board 6 | 7 | set files [list \ 8 | [file normalize "${origin_dir}/../../adi-hdl/library/common/ad_iobuf.v"] \ 9 | [file normalize "${origin_dir}/src/system_wrapper.v"] \ 10 | [file normalize "${origin_dir}/src/system.bd" ]\ 11 | [file normalize "${origin_dir}/src/system_top.v" ]\ 12 | ] 13 | 14 | set files_xdc [list \ 15 | [file normalize "$origin_dir/../../adi-hdl/projects/fmcomms2/zc706/system_constr.xdc"]\ 16 | [file normalize "$origin_dir/../../adi-hdl/projects/common/zc706/zc706_system_constr.xdc"]\ 17 | [file normalize "$origin_dir/src/system.xdc"]\ 18 | ] 19 | 20 | set ip_repos [list \ 21 | [file normalize "$origin_dir/../../adi-hdl/library"]\ 22 | [file normalize "$origin_dir/ip_repo/"]\ 23 | ] 24 | 25 | set board_part_repos [] 26 | -------------------------------------------------------------------------------- /boards/neptunesdr/set_files.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2025 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | # files and directories for the board 6 | 7 | set files [list \ 8 | [file normalize "${origin_dir}/../../adi-hdl/library/common/ad_iobuf.v"] \ 9 | [file normalize "${origin_dir}/src/system_wrapper.v"] \ 10 | [file normalize "${origin_dir}/src/system.bd" ]\ 11 | [file normalize "${origin_dir}/src/system_top.v" ]\ 12 | ] 13 | 14 | set files_xdc [list \ 15 | [file normalize "${origin_dir}/src/neptunesdr_constr.xdc"]\ 16 | [file normalize "${origin_dir}/src/neptunesdr_constr_lvds.xdc"]\ 17 | [file normalize "${origin_dir}/src/ccbob_constr.xdc"]\ 18 | [file normalize "$origin_dir/src/system.xdc"]\ 19 | ] 20 | 21 | set ip_repos [list \ 22 | [file normalize "$origin_dir/../../adi-hdl/library"]\ 23 | [file normalize "$origin_dir/ip_repo/"]\ 24 | ] 25 | 26 | set board_part_repos [] 27 | -------------------------------------------------------------------------------- /ip/openofdm_tx/src/ram_simo.v: -------------------------------------------------------------------------------- 1 | /* 2 | * ram_simo - single input multiple output (simo) ram 3 | * 4 | * Michael Tetemke Mehari mehari.michael@gmail.com 5 | */ 6 | 7 | 8 | module ram_simo #(DEPTH=64) 9 | ( 10 | input wire clk, 11 | 12 | input wire [$clog2(DEPTH*8)-1:0] waddr, 13 | input wire [$clog2(DEPTH)-1:0] raddr, 14 | input wire wen, 15 | input wire data_i, 16 | 17 | output wire [5:0] data_o 18 | ); 19 | 20 | reg [DEPTH*8-1:0] mem; 21 | 22 | // Empty memory initialization (only for simulation purpose) 23 | initial mem = {DEPTH*8{1'b0}}; 24 | 25 | // Data is latched on the positive edge of the clock 26 | always @(posedge clk) 27 | if (wen) 28 | mem[waddr] <= data_i; 29 | 30 | assign data_o[0] = mem[{raddr,3'd0}]; 31 | assign data_o[1] = mem[{raddr,3'd1}]; 32 | assign data_o[2] = mem[{raddr,3'd2}]; 33 | assign data_o[3] = mem[{raddr,3'd3}]; 34 | assign data_o[4] = mem[{raddr,3'd4}]; 35 | assign data_o[5] = mem[{raddr,3'd5}]; 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /boards/adrv9361z7035/set_files.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2025 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | # files and directories for the board 6 | 7 | set files [list \ 8 | [file normalize "${origin_dir}/../../adi-hdl/library/common/ad_iobuf.v"] \ 9 | [file normalize "${origin_dir}/src/system_wrapper.v"] \ 10 | [file normalize "${origin_dir}/src/system.bd" ]\ 11 | [file normalize "${origin_dir}/src/system_top.v" ]\ 12 | ] 13 | 14 | set files_xdc [list \ 15 | [file normalize "$origin_dir/../../adi-hdl/projects/adrv9361z7035/common/adrv9361z7035_constr.xdc"]\ 16 | [file normalize "$origin_dir/../../adi-hdl/projects/adrv9361z7035/common/adrv9361z7035_constr_lvds.xdc"]\ 17 | [file normalize "$origin_dir/../../adi-hdl/projects/adrv9361z7035/common/ccbob_constr.xdc"]\ 18 | [file normalize "$origin_dir/src/system.xdc"]\ 19 | ] 20 | 21 | set ip_repos [list \ 22 | [file normalize "$origin_dir/../../adi-hdl/library"]\ 23 | [file normalize "$origin_dir/ip_repo/"]\ 24 | ] 25 | 26 | set board_part_repos [] 27 | -------------------------------------------------------------------------------- /boards/adrv9364z7020/set_files.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2025 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | # files and directories for the board 6 | 7 | set files [list \ 8 | [file normalize "${origin_dir}/../../adi-hdl/library/common/ad_iobuf.v"] \ 9 | [file normalize "${origin_dir}/src/system_wrapper.v"] \ 10 | [file normalize "${origin_dir}/src/system.bd" ]\ 11 | [file normalize "${origin_dir}/src/system_top.v" ]\ 12 | ] 13 | 14 | set files_xdc [list \ 15 | [file normalize "$origin_dir/../../adi-hdl/projects/adrv9364z7020/common/adrv9364z7020_constr.xdc"]\ 16 | [file normalize "$origin_dir/../../adi-hdl/projects/adrv9364z7020/common/adrv9364z7020_constr_lvds.xdc"]\ 17 | [file normalize "$origin_dir/../../adi-hdl/projects/adrv9364z7020/common/ccbob_constr.xdc"]\ 18 | [file normalize "$origin_dir/src/system.xdc"]\ 19 | ] 20 | 21 | set ip_repos [list \ 22 | [file normalize "$origin_dir/../../adi-hdl/library"]\ 23 | [file normalize "$origin_dir/ip_repo/"]\ 24 | ] 25 | 26 | set board_part_repos [] 27 | -------------------------------------------------------------------------------- /boards/antsdr_e200/README.md: -------------------------------------------------------------------------------- 1 | # ANTSDR-E200 2 | 3 | ANTSDR-E200 is similar to MicroPhase ANTSDR-E310 device. 4 | 5 | ANTSDR-E200 has a smaller size and some differences in hardware structure. The ethernet is placed at the PL side. 6 | 7 | ![e200_struct](README.assets/e200_struct.svg) 8 | 9 | Since the performance of the zynq processor is not very strong, the Ethernet cannot run at a very high bandwidth. For some SDR applications, the Ethernet may be required to transmit baseband signals above 15MSPS sample rate. In this case, the bandwidth of the Ethernet will reach 60MB/s. If the Ethernet on the PS side wants to run at this bandwidth, it will take up a lot of CPU resources and the bandwidth is still difficult to meet. For this reason, we moved the network port to the PL side. 10 | 11 | But this has no effect on IIO-based SDR drivers, because we still use ZYNQ's GEM controller. O(∩_∩)O 12 | 13 | When we moved the ethernet to PL, the ANTSDR-E200 could support UHD driver, If anyone is interested in this, you can refer to our project [antsdr_uhd](https://github.com/MicroPhase/antsdr_uhd). 14 | 15 | -------------------------------------------------------------------------------- /ip/ultra_scale_tcl_gen.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # set -x 4 | set -f 5 | for i in $(find . -name '*.tcl'); do 6 | echo "$i" 7 | num_sub_dir=$(echo "$i" | tr -cd '/' | wc -c) 8 | 9 | if [ "$num_sub_dir" -ne 2 ] || [[ "$i" =~ "_ultra_scale.tcl" ]]; then 10 | echo "skip" 11 | echo " " 12 | else 13 | if grep -q "xilinx.com:zc706:part0:1.4" "$i" && grep -q "xc7z045ffg900-2" "$i" ; then 14 | # echo $num_sub_dir 15 | string_len=$(echo "$i" | wc -c) 16 | filename_core=$(echo "$i" | cut -c1-$[$string_len-5]) 17 | # echo $filename_core 18 | filename_new_ext="_ultra_scale.tcl" 19 | filename_new="$filename_core$filename_new_ext" 20 | cp "$i" $filename_new 21 | sed -i 's/xc7z045ffg900-2/xczu9eg-ffvb1156-2-e/g' $filename_new 22 | sed -i 's/"xilinx.com:zc706:part0:1.4"/"xilinx.com:zcu102:part0:3.1"/g' $filename_new 23 | echo $filename_new "is generated" 24 | echo " " 25 | else 26 | echo "skip1" 27 | echo " " 28 | fi 29 | fi 30 | 31 | done -------------------------------------------------------------------------------- /boards/antsdr/notes.md: -------------------------------------------------------------------------------- 1 | # antsdr for openwifi-hw 2 | 3 | ## Introduction 4 | [ANTSDR](https://github.com/MicroPhase/antsdr-fw) is a SDR hardware platform based on [xilinx zynq7020](https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html) and [adi ad936x](https://www.analog.com/en/products/ad9361.html). It could be used as a traditional SDR device such as PlutoSDR or FMCOMMS2/3/4 with Xilinx evaluation board, and it also be used as hardware platform to support openwifi. 5 | 6 | 9 | 12 | 13 | ## Work to be done 14 | The antsdr has RF switch in the front-end, for now, the RF switch is fixed at a higer range, which will isolation the frequency below 3GHz and pass the frequency at 3GHz~6GHz. 15 | For future work, it can add the rf swicth control in the devicetree, and this will change the rf switch with the frequency change. 16 | -------------------------------------------------------------------------------- /boards/zcu102_fmcs2/set_files.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2025 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | # files and directories for the board 6 | 7 | set files [list \ 8 | [file normalize "$origin_dir/../../adi-hdl/library/common/ad_iobuf.v"]\ 9 | [file normalize "$origin_dir/src/system_wrapper.v"]\ 10 | [file normalize "$origin_dir/src/system.bd"]\ 11 | [file normalize "$origin_dir/src/system_top.v"]\ 12 | [file normalize "$origin_dir/ip_repo/openofdm_rx/src/atan_lut.coe"]\ 13 | [file normalize "$origin_dir/ip_repo/openofdm_rx/src/deinter_lut.coe"]\ 14 | [file normalize "$origin_dir/ip_repo/openofdm_rx/src/rot_lut.coe"]\ 15 | ] 16 | 17 | set files_xdc [list \ 18 | [file normalize "$origin_dir/../../adi-hdl/projects/common/zcu102/zcu102_system_constr.xdc"]\ 19 | [file normalize "$origin_dir/../../adi-hdl/projects/fmcomms2/zcu102/system_constr.xdc"]\ 20 | [file normalize "$origin_dir/src/system.xdc"]\ 21 | ] 22 | 23 | set ip_repos [list \ 24 | [file normalize "$origin_dir/../../adi-hdl/library"]\ 25 | [file normalize "$origin_dir/ip_repo/"]\ 26 | ] 27 | 28 | set board_part_repos [] 29 | -------------------------------------------------------------------------------- /ip/openofdm_tx/src/l_stf_rom.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Legacy short_preamble_rom - TODO 3 | * 4 | * Michael Tetemke Mehari michael.mehari@ugent.be 5 | * Xianjun Jiao xianjun.jiao@imec.be putaoshu@msn.com 6 | */ 7 | `include "openofdm_tx_pre_def.v" 8 | 9 | module l_stf_rom 10 | ( 11 | input [3:0] addr, 12 | output reg [31:0] dout 13 | ); 14 | 15 | always @ * 16 | case (addr) 17 | 0: dout = 32'h05E305E3; 18 | 1: dout = 32'hEF0C004D; 19 | 2: dout = 32'hFE47F5F3; 20 | 3: dout = 32'h1246FE61; 21 | 4: dout = 32'h0BC70000; 22 | 5: dout = 32'h1246FE61; 23 | 6: dout = 32'hFE47F5F3; 24 | 7: dout = 32'hEF0C004D; 25 | 8: dout = 32'h05E305E3; 26 | 9: dout = 32'h004DEF0C; 27 | 10: dout = 32'hF5F3FE47; 28 | 11: dout = 32'hFE611246; 29 | 12: dout = 32'h00000BC7; 30 | 13: dout = 32'hFE611246; 31 | 14: dout = 32'hF5F3FE47; 32 | 15: dout = 32'h004DEF0C; 33 | 34 | default: dout = 32'h00000000; 35 | endcase 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /ip/tx_intf/src/tx_interrupt_selection.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | `timescale 1 ns / 1 ps 4 | 5 | module tx_interrupt_selection 6 | ( 7 | // selection 8 | input wire [2:0] src_sel, 9 | 10 | // src 11 | input wire s00_axis_tlast, 12 | input wire phy_tx_start, 13 | input wire tx_start_from_acc, 14 | input wire tx_end_from_acc, 15 | input wire tx_try_complete, 16 | 17 | // to ps interrupt 18 | output reg tx_itrpt 19 | ); 20 | 21 | always @( src_sel, s00_axis_tlast,phy_tx_start, tx_start_from_acc, tx_end_from_acc,tx_try_complete) 22 | begin 23 | case (src_sel) 24 | 3'b000 : begin 25 | tx_itrpt = s00_axis_tlast; 26 | end 27 | 3'b001 : begin 28 | tx_itrpt = phy_tx_start; 29 | end 30 | 3'b010 : begin 31 | tx_itrpt = tx_start_from_acc; 32 | end 33 | 3'b011 : begin 34 | tx_itrpt = tx_end_from_acc; 35 | end 36 | 3'b100 : begin 37 | tx_itrpt = tx_try_complete; 38 | end 39 | default: begin 40 | tx_itrpt = 0; 41 | end 42 | endcase 43 | end 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /ip/tx_intf/src/ht_sig_crc_calc.v: -------------------------------------------------------------------------------- 1 | // Michael Tetemke Mehari (michael.mehari@ugent.be) 2 | 3 | module ht_sig_crc_calc( 4 | input wire clk, 5 | input wire reset, 6 | input wire [33:0] d, 7 | input wire start, 8 | output reg busy, 9 | output reg valid, 10 | output reg [7:0] crc 11 | ); 12 | 13 | reg [5:0] i; 14 | reg [33:0] data; 15 | reg [7:0] c; 16 | 17 | wire temp; 18 | assign temp = c[7] ^ data[i]; 19 | 20 | always @(posedge clk) begin 21 | if(reset) begin 22 | valid <= 0; 23 | i <= 0; 24 | data <= 0; 25 | c <= 0; 26 | busy <= 0; 27 | crc <= 0; 28 | 29 | end else begin 30 | if (start) begin 31 | valid <= 0; 32 | i <= 0; 33 | data <= d; 34 | c <= 8'b11111111; 35 | busy <= 1; 36 | crc <= 0; 37 | 38 | end else if (busy) begin 39 | 40 | c[7] <= c[6]; 41 | c[6] <= c[5]; 42 | c[5] <= c[4]; 43 | c[4] <= c[3]; 44 | c[3] <= c[2]; 45 | c[2] <= c[1] ^ temp; 46 | c[1] <= c[0] ^ temp; 47 | c[0] <= temp; 48 | 49 | if (i == 34) begin 50 | busy <= 0; 51 | valid <= 1; 52 | crc <= ~({c[0],c[1],c[2],c[3],c[4],c[5],c[6],c[7]}); 53 | end else begin 54 | i <= i + 1; 55 | end 56 | end else begin 57 | valid <= 0; 58 | end 59 | end 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /ip/openofdm_tx/src/crc32_tx.v: -------------------------------------------------------------------------------- 1 | /* 2 | * crc32 - TODO 3 | * 4 | * Michael Tetemke Mehari michael.mehari@ugent.be 5 | */ 6 | 7 | module crc32_tx 8 | ( 9 | input wire rst, 10 | input wire clk, 11 | 12 | input wire crc_en, 13 | input wire [3:0] data_in, 14 | output reg [31:0] crc_out 15 | ); 16 | 17 | wire [3:0] idx; 18 | reg [31:0] crc_table; 19 | always @(*) begin 20 | case(idx) 21 | 4'b0000: begin crc_table = 32'h4DBDF21C; end 22 | 4'b0001: begin crc_table = 32'h500AE278; end 23 | 4'b0010: begin crc_table = 32'h76D3D2D4; end 24 | 4'b0011: begin crc_table = 32'h6B64C2B0; end 25 | 4'b0100: begin crc_table = 32'h3B61B38C; end 26 | 4'b0101: begin crc_table = 32'h26D6A3E8; end 27 | 4'b0110: begin crc_table = 32'h000F9344; end 28 | 4'b0111: begin crc_table = 32'h1DB88320; end 29 | 4'b1000: begin crc_table = 32'hA005713C; end 30 | 4'b1001: begin crc_table = 32'hBDB26158; end 31 | 4'b1010: begin crc_table = 32'h9B6B51F4; end 32 | 4'b1011: begin crc_table = 32'h86DC4190; end 33 | 4'b1100: begin crc_table = 32'hD6D930AC; end 34 | 4'b1101: begin crc_table = 32'hCB6E20C8; end 35 | 4'b1110: begin crc_table = 32'hEDB71064; end 36 | 4'b1111: begin crc_table = 32'hF0000000; end 37 | endcase 38 | end 39 | assign idx = crc_out[3:0] ^ data_in; 40 | 41 | 42 | always @(posedge clk) 43 | if (rst) 44 | crc_out <= 0; 45 | else if(crc_en) 46 | crc_out <= {4'b0000, crc_out[31:4]} ^ crc_table; 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /ip/rx_intf/unit_test/adc_intf/adc_intf_tb.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | `timescale 1ns/1ps 4 | 5 | module adc_intf_tb #( 6 | parameter integer IQ_DATA_WIDTH = 16 7 | ) ( 8 | ); 9 | 10 | reg adc_rst; 11 | reg adc_clk; 12 | reg [(4*IQ_DATA_WIDTH-1) : 0] adc_data; 13 | 14 | reg acc_clk_raw; 15 | wire acc_clk; 16 | reg acc_rstn; 17 | 18 | wire [2:0] bb_gain; 19 | wire [(4*IQ_DATA_WIDTH-1) : 0] data_to_bb; 20 | wire data_to_bb_valid; 21 | 22 | initial begin 23 | // $dumpfile("adc_intf_tb.vcd"); 24 | // $dumpvars; 25 | 26 | adc_clk = 0; 27 | acc_clk_raw = 0; 28 | 29 | adc_rst = 0; 30 | acc_rstn = 1; 31 | 32 | adc_data = 0; 33 | 34 | #13 adc_rst = 1; 35 | #16 acc_rstn = 0; 36 | 37 | #73 acc_rstn = 1; 38 | #97 adc_rst = 0; 39 | end 40 | 41 | assign bb_gain = 0; 42 | always begin // clk gen 43 | #5 acc_clk_raw = !acc_clk_raw; //100MHz 44 | end 45 | assign #3.3 acc_clk = acc_clk_raw; 46 | 47 | always begin // clk gen 48 | #12.5 adc_clk = !adc_clk; //40MHz 49 | end 50 | 51 | always @(posedge adc_clk) begin 52 | if (adc_rst) begin 53 | adc_data <= 0; 54 | end else begin 55 | adc_data <= adc_data + 1; 56 | end 57 | end 58 | 59 | adc_intf #(.IQ_DATA_WIDTH(IQ_DATA_WIDTH)) adc_intf_inst ( 60 | .adc_rst(adc_rst), 61 | .adc_clk(adc_clk), 62 | .adc_data(adc_data), 63 | .adc_data_valid(1), 64 | 65 | .acc_clk(acc_clk), 66 | .acc_rstn(acc_rstn), 67 | 68 | .bb_gain(bb_gain), 69 | .data_to_bb(data_to_bb), 70 | .data_to_bb_valid(data_to_bb_valid) 71 | ); 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /ip/xpu/src/tsf_timer.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | `include "clock_speed.v" 3 | `include "board_def.v" 4 | 5 | `timescale 1 ns / 1 ps 6 | 7 | module tsf_timer # 8 | ( 9 | parameter integer TIMER_WIDTH = 64 10 | ) 11 | ( 12 | input wire clk, 13 | input wire rstn, 14 | input wire tsf_load_control, //rising edge will load load_val into timer 15 | input wire [(TIMER_WIDTH-1) : 0] tsf_load_val, 16 | output reg [(TIMER_WIDTH-1) : 0] tsf_runtime_val, 17 | output reg tsf_pulse_1M 18 | ); 19 | 20 | reg [7:0] counter_1M; 21 | reg tsf_load_control_reg; 22 | 23 | always @( posedge clk ) 24 | begin 25 | if ( rstn == 0 ) 26 | begin 27 | counter_1M <= 0; 28 | tsf_runtime_val <= 0; 29 | tsf_pulse_1M <= 0; 30 | tsf_load_control_reg <= 0; 31 | end 32 | else 33 | begin 34 | tsf_load_control_reg <= tsf_load_control; 35 | if (counter_1M == `COUNT_TOP_1M || (tsf_load_control==0 && tsf_load_control_reg==1)) begin 36 | counter_1M <= 0; 37 | end else begin 38 | counter_1M <= counter_1M + 1'b1; 39 | end 40 | 41 | if (tsf_load_control==0 && tsf_load_control_reg==1) begin 42 | tsf_pulse_1M <= 0; 43 | tsf_runtime_val <= tsf_load_val; 44 | end else begin 45 | if (counter_1M == 0) begin 46 | tsf_pulse_1M <= 1; 47 | tsf_runtime_val <= tsf_runtime_val + 1'b1; 48 | end else begin 49 | tsf_pulse_1M <= 0; 50 | tsf_runtime_val <= tsf_runtime_val; 51 | end 52 | end 53 | end 54 | end 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /boards/sdk_update.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # // Author: Xianjun Jiao 4 | # // SPDX-FileCopyrightText: 2022 UGent 5 | # // SPDX-License-Identifier: AGPL-3.0-or-later 6 | 7 | if [ "$#" -ne 2 ]; then 8 | echo "You must enter the \$BOARD_NAME and \$OPENWIFI_HW_IMG_DIR as argument" 9 | echo "Like: antsdr antsdr_e200 sdrpi e310v2 adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371 neptunesdr" 10 | exit 1 11 | fi 12 | 13 | set -ex 14 | 15 | BOARD_NAME=$1 16 | OPENWIFI_HW_IMG_DIR=$2 17 | echo $BOARD_NAME 18 | echo $OPENWIFI_HW_IMG_DIR 19 | 20 | TARGET_SDK_DIR=$OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/ 21 | if test -d "$TARGET_SDK_DIR"; then 22 | echo "Found $TARGET_SDK_DIR" 23 | else 24 | echo "Create $TARGET_SDK_DIR" 25 | mkdir $TARGET_SDK_DIR -p 26 | fi 27 | 28 | rm -rf $TARGET_SDK_DIR/* 29 | cp $BOARD_NAME/openwifi_$BOARD_NAME/system_top.xsa $TARGET_SDK_DIR/ -rf 30 | if [ -f "$BOARD_NAME/openwifi_$BOARD_NAME/openwifi_$BOARD_NAME.runs/impl_1/system_top.ltx" ]; then 31 | cp $BOARD_NAME/openwifi_$BOARD_NAME/openwifi_$BOARD_NAME.runs/impl_1/system_top.ltx $TARGET_SDK_DIR/ -rf 32 | else 33 | echo "No debug probe file found." 34 | fi 35 | 36 | echo "openwifi-hw-git-branch" >> $TARGET_SDK_DIR//git_info.txt 37 | git branch >> $TARGET_SDK_DIR//git_info.txt 38 | echo " " >> $TARGET_SDK_DIR//git_info.txt 39 | echo "openwifi-hw-git-commit" >> $TARGET_SDK_DIR//git_info.txt 40 | git log -3 >> $TARGET_SDK_DIR//git_info.txt 41 | echo " " >> $TARGET_SDK_DIR//git_info.txt 42 | echo "openofdm_rx-git-branch" >> $TARGET_SDK_DIR//git_info.txt 43 | git --git-dir ../ip/openofdm_rx/.git branch >> $TARGET_SDK_DIR//git_info.txt 44 | echo " " >> $TARGET_SDK_DIR//git_info.txt 45 | echo "openofdm_rx-git-commit" >> $TARGET_SDK_DIR//git_info.txt 46 | git --git-dir ../ip/openofdm_rx/.git log -3 >> $TARGET_SDK_DIR//git_info.txt 47 | echo " " >> $TARGET_SDK_DIR//git_info.txt 48 | -------------------------------------------------------------------------------- /boards/package_ip_complex.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2022 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | set ip_tcl_filename [lindex $argv 0] 6 | set src_dir [lindex $argv 1] 7 | set ip_dir [lindex $argv 2] 8 | set BOARD_NAME [lindex $argv 3] 9 | 10 | exec rm -rf project_1 11 | exec rm -rf $ip_dir 12 | 13 | set current_dir [pwd] 14 | cd $src_dir/ 15 | 16 | set argc 1 17 | set argv [list $BOARD_NAME] 18 | source ./$ip_tcl_filename 19 | 20 | update_compile_order -fileset sources_1 21 | update_compile_order -fileset sources_1 22 | 23 | # ipx::package_project -root_dir /home/jxj/git/openwifi-hw/boards/antsdr/ip_repo/rx_intf -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false 24 | ipx::package_project -root_dir $ip_dir -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false 25 | # ipx::unload_core /home/jxj/git/openwifi-hw/boards/antsdr/ip_repo/rx_intf/component.xml 26 | ipx::unload_core $ip_dir/component.xml 27 | # ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory /home/jxj/git/openwifi-hw/boards/antsdr/ip_repo/rx_intf /home/jxj/git/openwifi-hw/boards/antsdr/ip_repo/rx_intf/component.xml 28 | ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $ip_dir $ip_dir/component.xml 29 | 30 | update_compile_order -fileset sources_1 31 | set_property core_revision 2 [ipx::current_core] 32 | 33 | ipx::update_source_project_archive -component [ipx::current_core] 34 | ipx::create_xgui_files [ipx::current_core] 35 | ipx::update_checksums [ipx::current_core] 36 | ipx::save_core [ipx::current_core] 37 | ipx::move_temp_component_back -component [ipx::current_core] 38 | 39 | close_project -delete 40 | # set_property ip_repo_paths /home/jxj/git/openwifi-hw/boards/antsdr/ip_repo/rx_intf [current_project] 41 | # update_ip_catalog 42 | 43 | close_project -delete 44 | 45 | cd $current_dir/ 46 | -------------------------------------------------------------------------------- /boards/antsdr/src/ccbob_constr.xdc: -------------------------------------------------------------------------------- 1 | 2 | ## constraints (ccbrk.c + ccbrk_lb.a) 3 | ## ad9361 clkout forward 4 | 5 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports clkout_out] 6 | set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports gpio_bd[0]] 7 | set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[1]] 8 | set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[2]] 9 | set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports gpio_bd[3]] 10 | set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS33} [get_ports gpio_bd[4]] 11 | set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports gpio_bd[5]] 12 | set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports gpio_bd[6]] 13 | set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports gpio_bd[7]] 14 | set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[8]] 15 | set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[9]] 16 | set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[10]] 17 | 18 | set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports rx1_band_sel_h] 19 | set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS33} [get_ports rx1_band_sel_l] 20 | set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33} [get_ports tx1_band_sel_h] 21 | set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33} [get_ports tx1_band_sel_l] 22 | set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports rx2_band_sel_h] 23 | set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports rx2_band_sel_l] 24 | set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports tx2_band_sel_h] 25 | set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports tx2_band_sel_l] 26 | -------------------------------------------------------------------------------- /ip/openofdm_tx/src/ht_stf_rom.v: -------------------------------------------------------------------------------- 1 | /* 2 | * HT short_preamble_rom - TODO 3 | * 4 | * Michael Tetemke Mehari michael.mehari@ugent.be 5 | * Xianjun Jiao xianjun.jiao@imec.be putaoshu@msn.com 6 | */ 7 | `include "openofdm_tx_pre_def.v" 8 | 9 | module ht_stf_rom 10 | ( 11 | input [3:0] addr, 12 | output reg [31:0] dout 13 | ); 14 | 15 | always @ * 16 | case (addr) 17 | /*michael code*/ 18 | // 0: dout = 32'h02D402D4; 19 | // 1: dout = 32'hF7DB0025; 20 | // 2: dout = 32'hFF2CFB2C; 21 | // 3: dout = 32'h08C7FF39; 22 | // 4: dout = 32'h05A80000; 23 | // 5: dout = 32'h08C7FF39; 24 | // 6: dout = 32'hFF2CFB2C; 25 | // 7: dout = 32'hF7DB0025; 26 | // 8: dout = 32'h02D402D4; 27 | // 9: dout = 32'h0025F7DB; 28 | // 10: dout = 32'hFB2CFF2C; 29 | // 11: dout = 32'hFF3908C7; 30 | // 12: dout = 32'h000005A8; 31 | // 13: dout = 32'hFF3908C7; 32 | // 14: dout = 32'hFB2CFF2C; 33 | // 15: dout = 32'h0025F7DB; 34 | 35 | 36 | /*after scaling*/ 37 | 0: dout = 32'h061C061C; 38 | 1: dout = 32'hEE680050; 39 | 2: dout = 32'hFE36F592; 40 | 3: dout = 32'h12F6FE52; 41 | 4: dout = 32'h0C380000; 42 | 5: dout = 32'h12F6FE52; 43 | 6: dout = 32'hFE36F592; 44 | 7: dout = 32'hEE680050; 45 | 8: dout = 32'h061C061C; 46 | 9: dout = 32'h0050EE68; 47 | 10: dout = 32'hF592FE36; 48 | 11: dout = 32'hFE5212F6; 49 | 12: dout = 32'h00000C38; 50 | 13: dout = 32'hFE5212F6; 51 | 14: dout = 32'hF592FE36; 52 | 15: dout = 32'h0050EE68; 53 | 54 | default: dout = 32'h00000000; 55 | endcase 56 | 57 | endmodule 58 | 59 | 60 | -------------------------------------------------------------------------------- /ip/openofdm_tx/src/dot11_tx_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module dot11_tx_tb; 4 | 5 | reg clock; 6 | reg reset; 7 | 8 | reg phy_tx_start; 9 | wire phy_tx_done; 10 | wire phy_tx_started; 11 | 12 | reg [63:0] bram_din; 13 | wire [9:0] bram_addr; 14 | 15 | wire result_iq_valid; 16 | wire signed [15:0] result_i; 17 | wire signed [15:0] result_q; 18 | 19 | integer result_fd; 20 | 21 | reg [63:0] Memory [0:1023]; 22 | initial begin 23 | $dumpfile("dot11_tx.vcd"); 24 | $dumpvars; 25 | 26 | // $readmemh("../../../../../unit_test/test_vec/tx_intf.mem", Memory); 27 | // $readmemh("../../../../../unit_test/test_vec/ht_tx_intf_mem_mcs7_gi1_aggr0_byte100.mem", Memory); 28 | $readmemh("../../../../../unit_test/test_vec/ht_tx_intf_mem_mcs7_gi1_aggr0_byte8176.mem", Memory); 29 | 30 | result_fd = $fopen("dot11_tx.txt", "w"); 31 | 32 | clock = 0; 33 | reset = 1; 34 | phy_tx_start = 0; 35 | 36 | # 20 reset = 0; 37 | phy_tx_start = 1; 38 | # 25 phy_tx_start = 0; 39 | end 40 | 41 | always begin //200MHz 42 | #2.5 clock = !clock; 43 | end 44 | 45 | always @(posedge clock) begin 46 | if(reset) 47 | bram_din <= 0; 48 | else begin 49 | if (result_iq_valid) 50 | $fwrite(result_fd, "%d %d\n", result_i, result_q); 51 | 52 | bram_din <= Memory[bram_addr]; 53 | if (phy_tx_done == 1) begin 54 | $fclose(result_fd); 55 | $finish; 56 | end 57 | end 58 | end 59 | 60 | 61 | dot11_tx dot11_tx_inst ( 62 | .clk(clock), 63 | .phy_tx_arest(reset), 64 | 65 | .phy_tx_start(phy_tx_start), 66 | .phy_tx_done(phy_tx_done), 67 | .phy_tx_started(phy_tx_started), 68 | 69 | .init_pilot_scram_state(7'b1111111), 70 | .init_data_scram_state(7'b1111111), 71 | 72 | .bram_din(bram_din), 73 | .bram_addr(bram_addr), 74 | 75 | .result_iq_ready(1'b1), 76 | .result_iq_valid(result_iq_valid), 77 | .result_i(result_i), 78 | .result_q(result_q) 79 | ); 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /prepare_adi_board_ip.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | if [ "$#" -ne 2 ]; then 3 | echo "You must enter exactly 2 arguments: \$XILINX_DIR \$BOARD_NAME" 4 | exit 1 5 | fi 6 | 7 | XILINX_DIR=$1 8 | 9 | if [ -d "$XILINX_DIR/Vivado" ]; then 10 | echo "\$XILINX_DIR is found!" 11 | else 12 | echo "\$XILINX_DIR is not correct. Please check!" 13 | exit 1 14 | fi 15 | 16 | BOARD_NAME=$2 17 | 18 | # [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9361z7035_fmc" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then 19 | 20 | if [ "$BOARD_NAME" == "zcu102_fmcs2" ]; then 21 | ADI_PROJECT_DIR=./adi-hdl/projects/fmcomms2/zcu102/ 22 | elif [ "$BOARD_NAME" == "zcu102_9371" ]; then 23 | ADI_PROJECT_DIR=./adi-hdl/projects/fmcomms2/zcu102/ 24 | elif [ "$BOARD_NAME" == "zc706_fmcs2" ]; then 25 | ADI_PROJECT_DIR=./adi-hdl/projects/fmcomms2/zc706/ 26 | elif [ "$BOARD_NAME" == "zc702_fmcs2" ]; then 27 | ADI_PROJECT_DIR=./adi-hdl/projects/fmcomms2/zc702/ 28 | elif [ "$BOARD_NAME" == "zed_fmcs2" ]; then 29 | ADI_PROJECT_DIR=./adi-hdl/projects/fmcomms2/zed/ 30 | elif [ "$BOARD_NAME" == "adrv9361z7035" ]; then 31 | ADI_PROJECT_DIR=./adi-hdl/projects/adrv9361z7035/ccbob_lvds/ 32 | #elif [ "$BOARD_NAME" == "adrv9361z7035_fmc" ]; then 33 | # ADI_PROJECT_DIR=./adi-hdl/projects/adrv9361z7035/ccfmc_lvds/ 34 | elif [ "$BOARD_NAME" == "adrv9364z7020" ] || [ "$BOARD_NAME" == "antsdr" ] || [ "$BOARD_NAME" == "antsdr_e200" ] || [ "$BOARD_NAME" == "e310v2" ] || [ "$BOARD_NAME" == "sdrpi" ] || [ "$BOARD_NAME" == "neptunesdr" ]; then 35 | ADI_PROJECT_DIR=./adi-hdl/projects/adrv9364z7020/ccbob_lvds/ 36 | else 37 | echo "\$BOARD_NAME is not correct. Please check!" 38 | exit 1 39 | fi 40 | 41 | echo $ADI_PROJECT_DIR 42 | 43 | home_dir=$(pwd) 44 | 45 | set -x 46 | 47 | source $XILINX_DIR/Vivado/2022.2/settings64.sh 48 | 49 | cd $ADI_PROJECT_DIR 50 | make 51 | 52 | cd $home_dir 53 | -------------------------------------------------------------------------------- /ip/create_vivado_proj.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Author: Xianjun jiao 4 | # SPDX-FileCopyrightText: 2025 UGent 5 | # SPDX-License-Identifier: AGPL-3.0-or-later 6 | 7 | print_usage () { 8 | echo "usage:" 9 | echo "Need at least 2 arguments: \$XILINX_DIR \$TCL_FILENAME" 10 | echo "More arguments (max 7) will be passed as arguments to the .tcl script to create ip_name_pre_def.v" 11 | echo "Among these max 7 arguments:" 12 | echo "- the 1st: BOARD_NAME (antsdr antsdr_e200 e310v2 sdrpi zc706_fmcs2 zed_fmcs2 zc702_fmcs2 adrv9361z7035 adrv9364z7020 zcu102_fmcs2 neptunesdr)" 13 | echo "- the 2nd: NUM_CLK_PER_US (for example: input 100 for 100MHz)" 14 | echo "- the 3rd-7th: User pre defines (assume it is ABC) for conditional compiling. Will be \`define IP_NAME_ABC in ip_name_pre_def.v" 15 | echo " - the 3rd exception: in the case of openofdm_rx, it indicates SAMPLE_FILE for simulation. Can be changed later in openofdm_rx_pre_def.v" 16 | } 17 | 18 | print_usage 19 | 20 | if [ "$#" -lt 2 ]; then 21 | exit 1 22 | fi 23 | 24 | XILINX_DIR=$1 25 | TCL_FILENAME=$2 26 | 27 | echo XILINX_DIR $XILINX_DIR 28 | echo TCL_FILENAME $TCL_FILENAME 29 | 30 | if [ -d "$XILINX_DIR/Vivado" ]; then 31 | echo "$XILINX_DIR is found!" 32 | else 33 | echo "$XILINX_DIR is not correct. Please check!" 34 | exit 1 35 | fi 36 | 37 | if [ -f "$TCL_FILENAME" ]; then 38 | echo "$TCL_FILENAME is found!" 39 | else 40 | echo "$TCL_FILENAME does NOT exist. Please check!" 41 | exit 1 42 | fi 43 | 44 | source $XILINX_DIR/Vivado/2022.2/settings64.sh 45 | 46 | ARG1="" 47 | ARG2="" 48 | ARG3="" 49 | ARG4="" 50 | ARG5="" 51 | ARG6="" 52 | ARG7="" 53 | 54 | if [[ -n $3 ]]; then 55 | ARG1=$3 56 | fi 57 | if [[ -n $4 ]]; then 58 | ARG2=$4 59 | fi 60 | if [[ -n $5 ]]; then 61 | ARG3=$5 62 | fi 63 | if [[ -n $6 ]]; then 64 | ARG4=$6 65 | fi 66 | if [[ -n $7 ]]; then 67 | ARG5=$7 68 | fi 69 | if [[ -n $8 ]]; then 70 | ARG6=$8 71 | fi 72 | if [[ -n $9 ]]; then 73 | ARG7=$9 74 | fi 75 | 76 | set -x 77 | vivado -source $TCL_FILENAME -tclargs $ARG1 $ARG2 $ARG3 $ARG4 $ARG5 $ARG6 $ARG7 78 | set +x 79 | 80 | -------------------------------------------------------------------------------- /ip/connect_openwifi_ip_ultra_scale.tcl: -------------------------------------------------------------------------------- 1 | connect_bd_intf_net -boundary_type upper [get_bd_intf_pins openwifi_ip/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_ACP_FPD] 2 | connect_bd_intf_net -boundary_type upper [get_bd_intf_pins openwifi_ip/M00_AXI1] [get_bd_intf_pins sys_ps8/S_AXI_HP3_FPD] 3 | 4 | connect_bd_intf_net -boundary_type upper [get_bd_intf_pins openwifi_ip/S00_AXI] [get_bd_intf_pins sys_ps8/M_AXI_HPM0_FPD] 5 | connect_bd_net [get_bd_pins openwifi_ip/adc_clk] [get_bd_pins util_ad9361_divclk/clk_out] 6 | connect_bd_net [get_bd_pins openwifi_ip/adc_rst] [get_bd_pins util_ad9361_divclk_reset/peripheral_reset] 7 | connect_bd_net [get_bd_pins openwifi_ip/ext_reset_in] [get_bd_pins sys_ps8/pl_resetn2] 8 | 9 | connect_bd_net [get_bd_pins openwifi_ip/gpio_status] [get_bd_pins xlslice_0/Dout] 10 | 11 | connect_bd_net [get_bd_pins openwifi_ip/m_axi_mm2s_aclk] [get_bd_pins sys_ps8/pl_clk2] 12 | connect_bd_net [get_bd_pins sys_ps8/saxihp3_fpd_aclk] [get_bd_pins sys_ps8/pl_clk2] 13 | connect_bd_net [get_bd_pins sys_ps8/saxiacp_fpd_aclk] [get_bd_pins sys_ps8/pl_clk2] 14 | connect_bd_net [get_bd_pins sys_ps8/maxihpm0_fpd_aclk] [get_bd_pins sys_ps8/pl_clk2] 15 | 16 | # delete_bd_objs [get_bd_nets ps_intr_04_1] 17 | # connect_bd_net [get_bd_pins sys_concat_intc_0/In4] [get_bd_pins openwifi_ip/tx_itrpt0] 18 | # delete_bd_objs [get_bd_nets ps_intr_05_1] 19 | # connect_bd_net [get_bd_pins sys_concat_intc_0/In5] [get_bd_pins openwifi_ip/tx_itrpt1] 20 | # delete_bd_objs [get_bd_nets ps_intr_06_1] 21 | # connect_bd_net [get_bd_pins sys_concat_intc_0/In6] [get_bd_pins openwifi_ip/mm2s_introut] 22 | # delete_bd_objs [get_bd_nets ps_intr_02_1] 23 | # connect_bd_net [get_bd_pins sys_concat_intc_0/In2] [get_bd_pins openwifi_ip/mm2s_introut1] 24 | # delete_bd_objs [get_bd_nets ps_intr_01_1] 25 | # connect_bd_net [get_bd_pins sys_concat_intc_0/In1] [get_bd_pins openwifi_ip/rx_pkt_intr] 26 | # delete_bd_objs [get_bd_nets ps_intr_03_1] 27 | # connect_bd_net [get_bd_pins sys_concat_intc_0/In3] [get_bd_pins openwifi_ip/s2mm_introut] 28 | # delete_bd_objs [get_bd_nets ps_intr_07_1] 29 | # connect_bd_net [get_bd_pins sys_concat_intc_0/In7] [get_bd_pins openwifi_ip/s2mm_introut1] 30 | save_bd_design 31 | 32 | -------------------------------------------------------------------------------- /ip/tx_intf/src/div_int.v: -------------------------------------------------------------------------------- 1 | // Project F: Division (Integer) 2 | // (C)2021 Will Green, Open source hardware released under the MIT License 3 | // 4 | // Update to verilog implementation 5 | // Michael Tetemke Mehari (michael.mehari@ugent.be) 6 | 7 | `timescale 1ns / 1ps 8 | 9 | module div_int #(parameter WIDTH=4) ( 10 | input wire clk, 11 | input wire reset, 12 | input wire start, // start signal 13 | output reg busy, // calculation in progress 14 | output reg valid, // quotient and remainder are valid 15 | output reg dbz, // divide by zero flag 16 | input wire [WIDTH-1:0] x, // dividend 17 | input wire [WIDTH-1:0] y, // divisor 18 | output reg [WIDTH-1:0] q, // quotient 19 | output reg [WIDTH-1:0] r // remainder 20 | ); 21 | 22 | reg [WIDTH-1:0] y1; // copy of divisor 23 | reg [WIDTH-1:0] q1, q1_next; // intermediate quotient 24 | reg [WIDTH:0] ac, ac_next; // accumulator (1 bit wider) 25 | reg [$clog2(WIDTH)-1:0] i; // iteration counter 26 | 27 | always @* begin 28 | if (ac >= {1'b0,y1}) begin 29 | ac_next = ac - y1; 30 | {ac_next, q1_next} = {ac_next[WIDTH-1:0], q1, 1'b1}; 31 | end else begin 32 | {ac_next, q1_next} = {ac, q1} << 1; 33 | end 34 | end 35 | 36 | always @(posedge clk) begin 37 | if(reset) begin 38 | busy <= 0; 39 | valid <= 0; 40 | dbz <= 0; 41 | i <= 0; 42 | y1 <= 0; 43 | ac <= 0; 44 | q1 <= 0; 45 | 46 | end else begin 47 | if (start) begin 48 | valid <= 0; 49 | i <= 0; 50 | if (y == 0) begin // catch divide by zero 51 | busy <= 0; 52 | dbz <= 1; 53 | end else begin // initialize values 54 | busy <= 1; 55 | dbz <= 0; 56 | y1 <= y; 57 | {ac, q1} <= {{WIDTH{1'b0}}, x, 1'b0}; 58 | end 59 | 60 | end else if (busy) begin 61 | if (i == WIDTH-1) begin // we're done 62 | busy <= 0; 63 | valid <= 1; 64 | q <= q1_next; 65 | r <= ac_next[WIDTH:1]; // undo final shift 66 | end else begin // next iteration 67 | i <= i + 1; 68 | ac <= ac_next; 69 | q1 <= q1_next; 70 | end 71 | end else begin 72 | valid <= 0; 73 | end 74 | end 75 | end 76 | endmodule 77 | 78 | -------------------------------------------------------------------------------- /ip/xpu/unit_test/fifo_sample_delay/fifo_sample_delay_tb.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | `timescale 1ns/1ps 4 | 5 | module fifo_sample_delay_tb #( 6 | parameter integer IQ_DATA_WIDTH = 16 7 | ) ( 8 | ); 9 | 10 | reg clock; 11 | reg reset; 12 | reg [(IQ_DATA_WIDTH-1):0] data_in; 13 | reg data_in_valid; 14 | wire [(IQ_DATA_WIDTH-1):0] data_out; 15 | wire data_out_valid; 16 | reg [15:0] clk_count; 17 | 18 | integer sample_count; 19 | 20 | `define SPEED_100M // comment out this to use 200M 21 | 22 | `define NUM_SAMPLE 1000 23 | 24 | initial begin 25 | $dumpfile("fifo_sample_delay_tb.vcd"); 26 | $dumpvars; 27 | 28 | data_in <= 0; 29 | data_in_valid <= 0; 30 | clk_count <= 0; 31 | sample_count = 0; 32 | clock = 0; 33 | 34 | reset = 1; 35 | #100 reset = 0; 36 | // 5clk reset (100MHz) at a specific time 37 | #1003 reset = 1; 38 | #57 reset = 0; 39 | // 5clk reset (100MHz) at a specific time 40 | #2005 reset = 1; 41 | #87 reset = 0; 42 | // 5clk reset (100MHz) at a specific time 43 | #3008 reset = 1; 44 | #50 reset = 0; 45 | end 46 | 47 | always begin // clk gen 48 | `ifdef SPEED_100M 49 | #5 clock = !clock; //100MHz 50 | `else 51 | #2.5 clock = !clock;//200MHz 52 | `endif 53 | end 54 | 55 | `ifdef SPEED_100M 56 | `define CLK_COUNT_TOP_FOR_VALID 4 // for 100M; 100/20 = 5 57 | `else 58 | `define CLK_COUNT_TOP_FOR_VALID 9 // for 200M; 200/20 = 10 59 | `endif 60 | always @(posedge clock) begin 61 | if (clk_count == `CLK_COUNT_TOP_FOR_VALID) begin 62 | data_in_valid <= 1; 63 | data_in <= data_in + 1; 64 | clk_count <= 0; 65 | sample_count = sample_count + 1; 66 | if (sample_count == `NUM_SAMPLE) 67 | $finish; 68 | end else begin 69 | data_in_valid <= 0; 70 | clk_count <= clk_count + 1; 71 | data_in <= -data_in;//to emulate value change between valid 72 | end 73 | end 74 | 75 | fifo_sample_delay #(.DATA_WIDTH(IQ_DATA_WIDTH), .LOG2_FIFO_DEPTH(7)) fifo_sample_delay_inst ( 76 | .clk(clock), 77 | .rst(reset), 78 | 79 | .delay_ctl(4), 80 | .data_in(data_in), 81 | .data_in_valid(data_in_valid), 82 | .data_out(data_out), 83 | .data_out_valid(data_out_valid) 84 | ); 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /boards/package_ip.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2022 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | set part_string [lindex $argv 0] 6 | set src_dir [lindex $argv 1] 7 | set ip_dir [lindex $argv 2] 8 | 9 | exec rm -rf project_1 10 | exec rm -rf $ip_dir 11 | 12 | # create_project project_1 ./project_1 -part xc7z020clg484-1 13 | create_project project_1 ./project_1 -part $part_string 14 | # set_property board_part em.avnet.com:zed:part0:1.4 [current_project] 15 | 16 | # set files [glob /home/jxj/git/openwifi-hw/boards/antsdr/ip_repo_src/rx_intf/src/*.v] 17 | set files [glob $src_dir/*] 18 | add_files $files 19 | # set files [list [file normalize "./ip_repo/openwifi_hw_git_rev.v"] [file normalize "./ip_repo/board_def.v"] [file normalize "./ip_repo/clock_speed.v"] [file normalize "./ip_repo/has_side_ch_flag.v"] [file normalize "./ip_repo/fpga_scale.v"]] 20 | # add_files $files 21 | update_compile_order -fileset sources_1 22 | update_compile_order -fileset sources_1 23 | 24 | # ipx::package_project -root_dir /home/jxj/git/openwifi-hw/boards/antsdr/ip_repo/rx_intf -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false 25 | ipx::package_project -root_dir $ip_dir -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false 26 | # ipx::unload_core /home/jxj/git/openwifi-hw/boards/antsdr/ip_repo/rx_intf/component.xml 27 | ipx::unload_core $ip_dir/component.xml 28 | # ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory /home/jxj/git/openwifi-hw/boards/antsdr/ip_repo/rx_intf /home/jxj/git/openwifi-hw/boards/antsdr/ip_repo/rx_intf/component.xml 29 | ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $ip_dir $ip_dir/component.xml 30 | 31 | update_compile_order -fileset sources_1 32 | set_property core_revision 2 [ipx::current_core] 33 | 34 | ipx::update_source_project_archive -component [ipx::current_core] 35 | ipx::create_xgui_files [ipx::current_core] 36 | ipx::update_checksums [ipx::current_core] 37 | ipx::save_core [ipx::current_core] 38 | ipx::move_temp_component_back -component [ipx::current_core] 39 | 40 | close_project -delete 41 | # set_property ip_repo_paths /home/jxj/git/openwifi-hw/boards/antsdr/ip_repo/rx_intf [current_project] 42 | # update_ip_catalog 43 | 44 | close_project -delete 45 | 46 | -------------------------------------------------------------------------------- /ip/side_ch/src/dpram.v: -------------------------------------------------------------------------------- 1 | // Original: https://github.com/KennethWilke/sv-dpram/blob/master/dpram.sv 2 | // Modified to Verilog by xianjun.jiao@imec.be; putaoshu@msn.com 3 | // License: https://github.com/KennethWilke/sv-dpram/blob/master/LICENSE 4 | // Copyright (c) 2023, Kenneth Wilke 5 | 6 | // Permission to use, copy, modify, and/or distribute this software for any 7 | // purpose with or without fee is hereby granted, provided that the above 8 | // copyright notice and this permission notice appear in all copies. 9 | 10 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 11 | // REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 12 | // AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 13 | // INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 14 | // LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 15 | // OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 | // PERFORMANCE OF THIS SOFTWARE. 17 | 18 | // Dual-ported parameterized RAM module 19 | 20 | `timescale 1ns/1ns 21 | 22 | module dpram 23 | #(parameter DATA_WIDTH = 8, 24 | parameter ADDRESS_WIDTH = 8) ( 25 | input clock, 26 | input reset, 27 | 28 | input enable_a, 29 | input write_enable, 30 | input [ADDRESS_WIDTH-1:0] write_address, 31 | input [DATA_WIDTH-1:0] write_data, 32 | output reg [DATA_WIDTH-1:0] read_data_a, 33 | 34 | input enable_b, 35 | input [ADDRESS_WIDTH-1:0] read_address, 36 | output reg [DATA_WIDTH-1:0] read_data 37 | ); 38 | 39 | reg [DATA_WIDTH-1:0] memory [(1< 5 | 6 | // Permission to use, copy, modify, and/or distribute this software for any 7 | // purpose with or without fee is hereby granted, provided that the above 8 | // copyright notice and this permission notice appear in all copies. 9 | 10 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 11 | // REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 12 | // AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 13 | // INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 14 | // LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 15 | // OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 | // PERFORMANCE OF THIS SOFTWARE. 17 | 18 | // Dual-ported parameterized RAM module 19 | 20 | `timescale 1ns/1ns 21 | 22 | module dpram 23 | #(parameter DATA_WIDTH = 8, 24 | parameter ADDRESS_WIDTH = 8) ( 25 | input clock, 26 | input reset, 27 | 28 | input enable_a, 29 | input write_enable, 30 | input [ADDRESS_WIDTH-1:0] write_address, 31 | input [DATA_WIDTH-1:0] write_data, 32 | output reg [DATA_WIDTH-1:0] read_data_a, 33 | 34 | input enable_b, 35 | input [ADDRESS_WIDTH-1:0] read_address, 36 | output reg [DATA_WIDTH-1:0] read_data 37 | ); 38 | 39 | reg [DATA_WIDTH-1:0] memory [(1< 0)) begin 51 | is_counting<=1; 52 | wait_after_decode_count<=0; 53 | end else begin 54 | wait_after_decode_count<=(is_counting? (wait_after_decode_count+1):wait_after_decode_count); 55 | is_counting<=( (wait_after_decode_count>=wait_after_decode_top_scale)?0:is_counting ); 56 | end 57 | end 58 | end 59 | 60 | assign ch_idle_rssi = (is_counting?1:( (rssi_half_db<=rssi_half_db_th) && (~demod_is_ongoing) )); 61 | assign ch_idle = (ch_idle_rssi&&(~tx_rf_is_ongoing)&&(~cts_toself_rf_is_ongoing)&&(~ack_cts_is_ongoing)); // remove tx_control_state_idle condition, need to separate ch_idle and internal state 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /ip/xpu/src/n_sym_len14_pkt.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | `timescale 1 ns / 1 ps 4 | 5 | module n_sym_len14_pkt # 6 | ( 7 | ) 8 | ( 9 | input wire ht_flag, 10 | input wire [3:0] rate_mcs, 11 | output wire [2:0] n_sym 12 | ); 13 | 14 | reg [2:0] num_data_ofdm_symbol; 15 | 16 | assign n_sym = num_data_ofdm_symbol; 17 | // lookup table for how many data OFDM symbol will be used for ACK/CTS (length 14) 18 | // to decide recv_ack_timeout_top and others 19 | //always @( signal_rate[7],signal_rate[3:0] ) 20 | always @( ht_flag, rate_mcs ) 21 | begin 22 | case ({ht_flag,rate_mcs}) 23 | 5'b01011 : begin //non-ht 6Mbps 24 | num_data_ofdm_symbol = 6; 25 | end 26 | 5'b01111 : begin //non-ht 9Mbps 27 | num_data_ofdm_symbol = 4; 28 | end 29 | 5'b01010 : begin //non-ht 12Mbps 30 | num_data_ofdm_symbol = 3; 31 | end 32 | 5'b01110 : begin //non-ht 18Mbps 33 | num_data_ofdm_symbol = 2; 34 | end 35 | 5'b01001 : begin //non-ht 24Mbps 36 | num_data_ofdm_symbol = 2; 37 | end 38 | 5'b01101 : begin //non-ht 36Mbps 39 | num_data_ofdm_symbol = 1; 40 | end 41 | 5'b01000 : begin //non-ht 48Mbps 42 | num_data_ofdm_symbol = 1; 43 | end 44 | 5'b01100 : begin //non-ht 54Mbps 45 | num_data_ofdm_symbol = 1; 46 | end 47 | 5'b10000 : begin //ht mcs 0 48 | num_data_ofdm_symbol = 6; 49 | end 50 | 5'b10001 : begin //ht mcs 1 51 | num_data_ofdm_symbol = 3; 52 | end 53 | 5'b10010 : begin //ht mcs 2 54 | num_data_ofdm_symbol = 2; 55 | end 56 | 5'b10011 : begin //ht mcs 3 57 | num_data_ofdm_symbol = 2; 58 | end 59 | 5'b10100 : begin //ht mcs 4 60 | num_data_ofdm_symbol = 1; 61 | end 62 | 5'b10101 : begin //ht mcs 5 63 | num_data_ofdm_symbol = 1; 64 | end 65 | 5'b10110 : begin //ht mcs 6 66 | num_data_ofdm_symbol = 1; 67 | end 68 | 5'b10111 : begin //ht mcs 7 69 | num_data_ofdm_symbol = 1; 70 | end 71 | default: begin 72 | num_data_ofdm_symbol = 6; 73 | end 74 | endcase 75 | end 76 | 77 | endmodule 78 | -------------------------------------------------------------------------------- /ip/xpu/src/dc_rm.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | `timescale 1 ns / 1 ps 4 | 5 | module dc_rm # 6 | ( 7 | parameter DATA_WIDTH = 16 8 | ) 9 | ( 10 | input wire clk, 11 | input wire rstn, 12 | input wire signed [(DATA_WIDTH-1):0] ddc_i, 13 | input wire signed [(DATA_WIDTH-1):0] ddc_q, 14 | input wire ddc_iq_valid, 15 | output wire signed [(DATA_WIDTH-1):0] i_dc_rm, 16 | output wire signed [(DATA_WIDTH-1):0] q_dc_rm, 17 | output wire iq_dc_rm_valid 18 | ); 19 | 20 | wire signed [DATA_WIDTH-1:0] ddc_i_mv_avg; 21 | wire signed [DATA_WIDTH-1:0] ddc_q_mv_avg; 22 | // wire signed [(2*DATA_WIDTH-1):0] dc_rm_mv_avg_internal; 23 | 24 | wire dc_rm_ready_internal; 25 | 26 | // assign ddc_i_mv_avg = dc_rm_mv_avg_internal[(DATA_WIDTH-1):0]; 27 | // assign ddc_q_mv_avg = dc_rm_mv_avg_internal[(2*DATA_WIDTH-1):DATA_WIDTH]; 28 | 29 | assign i_dc_rm = ddc_i - ddc_i_mv_avg; 30 | assign q_dc_rm = ddc_q - ddc_q_mv_avg; 31 | 32 | // mv_avg128 # ( 33 | // ) mv_avg128_i ( 34 | // .M_AXIS_DATA_tdata(dc_rm_mv_avg_internal), 35 | // .M_AXIS_DATA_tvalid(iq_dc_rm_valid), 36 | // .S_AXIS_DATA_tdata({ddc_q,ddc_i}), 37 | // .S_AXIS_DATA_tready(dc_rm_ready_internal), 38 | // .S_AXIS_DATA_tvalid(ddc_iq_valid), 39 | // .aclk(clk), 40 | // .aresetn(rstn) 41 | // ); 42 | 43 | mv_avg_dual_ch #(.DATA_WIDTH0(DATA_WIDTH), .DATA_WIDTH1(DATA_WIDTH), .LOG2_AVG_LEN(7)) mv_avg128_dual_ch_inst ( 44 | .clk(clk), 45 | .rstn(rstn), 46 | 47 | .data_in0(ddc_i), 48 | .data_in1(ddc_q), 49 | .data_in_valid(ddc_iq_valid), 50 | 51 | .data_out0(ddc_i_mv_avg), 52 | .data_out1(ddc_q_mv_avg), 53 | .data_out_valid(iq_dc_rm_valid) 54 | ); 55 | 56 | // mv_avg #(.DATA_WIDTH(DATA_WIDTH), .LOG2_AVG_LEN(7)) mv_avg128_i_inst ( 57 | // .clk(clk), 58 | // .rstn(rstn), 59 | 60 | // .data_in(ddc_i), 61 | // .data_in_valid(ddc_iq_valid), 62 | // .data_out(ddc_i_mv_avg), 63 | // .data_out_valid(iq_dc_rm_valid) 64 | // ); 65 | // mv_avg #(.DATA_WIDTH(DATA_WIDTH), .LOG2_AVG_LEN(7)) mv_avg128_q_inst ( 66 | // .clk(clk), 67 | // .rstn(rstn), 68 | 69 | // .data_in(ddc_q), 70 | // .data_in_valid(ddc_iq_valid), 71 | // .data_out(ddc_q_mv_avg), 72 | // .data_out_valid() 73 | // ); 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /ip/xpu/unit_test/mv_avg/test_vec/test_data_in_out.m: -------------------------------------------------------------------------------- 1 | function test_data_in_out 2 | clear all; 3 | close all; 4 | 5 | % a = round(randn(2000,1).*1000); 6 | % fp = fopen('data_in.txt', 'w'); 7 | % for i=1:length(a) 8 | % fprintf(fp, '%d\n', a(i)); 9 | % end 10 | % fclose(fp); 11 | 12 | % data_in = load('data_in_sync_short_prod.txt'); 13 | data_in = load('data_in.txt'); 14 | 15 | data_out_golden = mv_avg(data_in, 32); 16 | data_out_golden(1:2) = []; 17 | data_out_golden(500:501) = []; 18 | data_out_golden(1000:1002) = []; 19 | data_out_golden(1500:1501) = []; 20 | % subplot(2,1,1); 21 | plot(data_out_golden, 'b'); hold on; grid on; 22 | % data_out = load('data_out.txt'); 23 | % subplot(2,1,1); plot(data_out, 'r*-'); 24 | data_out_new = load('data_out_new.txt'); 25 | % subplot(2,1,1); 26 | plot(data_out_new, 'r'); 27 | legend('golden', 'verilog'); 28 | 29 | % data_out128_golden = mv_avg(data_in, 128); 30 | % subplot(2,1,2); plot(data_out128_golden, 'b'); hold on; grid on; 31 | % % data_out128 = load('data_out128.txt'); 32 | % % subplot(2,1,2); plot(data_out128, 'r*-'); 33 | % data_out128_new = load('data_out128_new.txt'); 34 | % subplot(2,1,2); plot(data_out128_new, 'r.'); 35 | 36 | figure; 37 | % subplot(2,2,1); plot(data_out_golden(1:997) - data_out); 38 | % subplot(2,1,1); 39 | plot(data_out_golden(1:length(data_out_new)) - data_out_new); 40 | % subplot(2,2,3); plot(data_out128_golden(1:997) - data_out128); 41 | % subplot(2,1,2); plot(data_out128_golden(1:length(data_out128_new)) - data_out128_new); 42 | 43 | % dual channel version 44 | figure; 45 | data_out_golden0 = mv_avg(data_in, 16); 46 | data_out_golden0(1:2) = []; 47 | data_out_golden0(500:501) = []; 48 | data_out_golden0(1000:1002) = []; 49 | data_out_golden0(1500:1501) = []; 50 | data_out_golden1 = mv_avg(-data_in, 16); 51 | data_out_golden1(1:2) = []; 52 | data_out_golden1(500:501) = []; 53 | data_out_golden1(1000:1002) = []; 54 | data_out_golden1(1500:1501) = []; 55 | plot(data_out_golden0, 'b'); hold on; grid on; 56 | plot(data_out_golden1, 'b--'); hold on; grid on; 57 | a = load('data_out_dual_ch.txt'); 58 | data_out0 = a(:,1); 59 | data_out1 = a(:,2); 60 | plot(data_out0, 'r'); 61 | plot(data_out1, 'r--'); 62 | legend('golden0', 'golden1', 'verilog0', 'verilog1'); 63 | 64 | figure; 65 | plot(data_out_golden0(1:length(data_out0)) - data_out0, 'b'); hold on; grid on; 66 | plot(data_out_golden1(1:length(data_out0)) - data_out1, 'r'); 67 | 68 | function a = mv_avg(b, mv_avg_len) 69 | c = [zeros(mv_avg_len-1,1); b]; 70 | a = zeros(length(b),1); 71 | for i=1:length(b) 72 | a(i) = floor(sum(c(i:(i+mv_avg_len-1)))./mv_avg_len); 73 | end 74 | -------------------------------------------------------------------------------- /ip/xpu/src/cw_exp.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1 ns / 1 ps 3 | 4 | `include "xpu_pre_def.v" 5 | 6 | `ifdef XPU_ENABLE_DBG 7 | `define DEBUG_PREFIX (*mark_debug="true",DONT_TOUCH="TRUE"*) 8 | `else 9 | `define DEBUG_PREFIX 10 | `endif 11 | 12 | module cw_exp # 13 | ( 14 | 15 | ) 16 | ( 17 | input wire clk, 18 | input wire rstn, 19 | input wire tx_try_complete, 20 | input wire quit_retrans, 21 | input wire [31:0] cw_combined, 22 | input wire retrans_trigger, 23 | input wire [1:0] tx_queue_idx, 24 | `DEBUG_PREFIX output reg [3:0] cw_exp 25 | ); 26 | // (* mark_debug = "true", DONT_TOUCH = "TRUE" *) 27 | reg [3:0] cw_min; 28 | // (* mark_debug = "true", DONT_TOUCH = "TRUE" *) 29 | reg [3:0] cw_max; 30 | reg [1:0] tx_queue_idx_reg; 31 | // (* mark_debug = "true", DONT_TOUCH = "TRUE" *) 32 | reg cw_update; 33 | 34 | always @(tx_queue_idx,cw_combined) begin 35 | case(tx_queue_idx) 36 | 2'b00: begin 37 | cw_min=cw_combined[3:0]; 38 | cw_max=cw_combined[7:4]; 39 | end 40 | 2'b01: begin 41 | cw_min=cw_combined[11:8]; 42 | cw_max=cw_combined[15:12]; 43 | end 44 | 2'b10: begin 45 | cw_min=cw_combined[19:16]; 46 | cw_max=cw_combined[23:20]; 47 | end 48 | 2'b11: begin 49 | cw_min=cw_combined[27:24]; 50 | cw_max=cw_combined[31:28]; 51 | end 52 | default:begin 53 | cw_min=cw_combined[3:0]; 54 | cw_max=cw_combined[7:4]; 55 | end 56 | endcase 57 | end 58 | 59 | always @( posedge clk ) 60 | begin 61 | if ( rstn == 0 ) 62 | begin 63 | cw_exp <= cw_min; 64 | end else begin 65 | if (cw_update==1 || tx_try_complete || quit_retrans) begin 66 | cw_exp <= cw_min ; 67 | end else begin 68 | if (retrans_trigger && (cw_exp < cw_max)) begin 69 | cw_exp <= cw_exp + 1'b1; 70 | end else begin 71 | cw_exp <= cw_exp ; 72 | end 73 | end 74 | end 75 | end 76 | 77 | always @( posedge clk ) 78 | begin 79 | if ( rstn == 0 ) 80 | begin 81 | tx_queue_idx_reg <= 0; 82 | cw_update <= 0; 83 | end else begin 84 | tx_queue_idx_reg <= tx_queue_idx ; 85 | if(tx_queue_idx_reg != tx_queue_idx) begin 86 | cw_update <= 1; 87 | end else begin 88 | cw_update <= 0; 89 | end 90 | end 91 | end 92 | endmodule 93 | -------------------------------------------------------------------------------- /ip/parse_board_name.tcl: -------------------------------------------------------------------------------- 1 | # // Author: Xianjun Jiao 2 | # // SPDX-FileCopyrightText: 2022 UGent 3 | # // SPDX-License-Identifier: AGPL-3.0-or-later 4 | 5 | # fpga_size_flag: 0 small; 1 big 6 | 7 | if {$BOARD_NAME=="zed_fmcs2"} { 8 | set ultra_scale_flag 0 9 | set part_string "xc7z020clg484-1" 10 | set board_part_string [] 11 | set board_id_string "zed" 12 | set fpga_size_flag 0 13 | } elseif {$BOARD_NAME=="zcu102_fmcs2"} { 14 | set ultra_scale_flag 1 15 | set part_string "xczu9eg-ffvb1156-2-e" 16 | set board_part_string "xilinx.com:zcu102:part0:3.4" 17 | set board_id_string "zcu102" 18 | set fpga_size_flag 1 19 | } elseif {$BOARD_NAME=="zc706_fmcs2"} { 20 | set ultra_scale_flag 0 21 | set part_string "xc7z045ffg900-2" 22 | set board_part_string [] 23 | set board_id_string "zc706" 24 | set fpga_size_flag 1 25 | } elseif {$BOARD_NAME=="zc702_fmcs2"} { 26 | set ultra_scale_flag 0 27 | set part_string "xc7z020clg484-1" 28 | set board_part_string [] 29 | set board_id_string "zc702" 30 | set fpga_size_flag 0 31 | } elseif {$BOARD_NAME=="antsdr"} { 32 | set ultra_scale_flag 0 33 | set part_string "xc7z020clg400-1" 34 | set board_part_string [] 35 | set board_id_string [] 36 | set fpga_size_flag 0 37 | } elseif {$BOARD_NAME=="antsdr_e200"} { 38 | set ultra_scale_flag 0 39 | set part_string "xc7z020clg400-1" 40 | set board_part_string [] 41 | set board_id_string [] 42 | set fpga_size_flag 0 43 | } elseif {$BOARD_NAME=="sdrpi"} { 44 | set ultra_scale_flag 0 45 | set part_string "xc7z020clg400-1" 46 | set board_part_string [] 47 | set board_id_string [] 48 | set fpga_size_flag 0 49 | } elseif {$BOARD_NAME=="adrv9361z7035"} { 50 | set ultra_scale_flag 0 51 | set part_string "xc7z035ifbg676-2L" 52 | set board_part_string [] 53 | set board_id_string [] 54 | set fpga_size_flag 1 55 | } elseif {$BOARD_NAME=="adrv9364z7020"} { 56 | set ultra_scale_flag 0 57 | set part_string "xc7z020clg400-1" 58 | set board_part_string [] 59 | set board_id_string [] 60 | set fpga_size_flag 0 61 | } elseif {$BOARD_NAME=="neptunesdr"} { 62 | set ultra_scale_flag 0 63 | set part_string "xc7z020clg400-1" 64 | set board_part_string [] 65 | set board_id_string [] 66 | set fpga_size_flag 0 67 | } elseif {$BOARD_NAME=="e310v2"} { 68 | set ultra_scale_flag 0 69 | set part_string "xc7z020clg400-1" 70 | set board_part_string [] 71 | set board_id_string [] 72 | set fpga_size_flag 0 73 | } else { 74 | set ultra_scale_flag [] 75 | set part_string [] 76 | set fpga_size_flag [] 77 | set board_part_string [] 78 | set board_id_string [] 79 | puts "$BOARD_NAME is not valid!" 80 | } 81 | -------------------------------------------------------------------------------- /ip/xpu/src/fifo_sample_delay.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | `timescale 1 ns / 1 ps 4 | 5 | module fifo_sample_delay # 6 | ( 7 | parameter integer DATA_WIDTH = 8, 8 | parameter integer LOG2_FIFO_DEPTH = 7 9 | ) 10 | ( 11 | input wire clk, 12 | input wire rst, 13 | 14 | input wire [(LOG2_FIFO_DEPTH-1):0] delay_ctl, 15 | 16 | input wire [(DATA_WIDTH-1):0] data_in, 17 | input wire data_in_valid, 18 | output wire [(DATA_WIDTH-1):0] data_out, 19 | output wire data_out_valid 20 | ); 21 | 22 | wire [LOG2_FIFO_DEPTH:0] rd_data_count; 23 | wire [LOG2_FIFO_DEPTH:0] wr_data_count; 24 | wire full; 25 | wire empty; 26 | 27 | reg rd_en_start; 28 | wire rd_en; 29 | 30 | reg [LOG2_FIFO_DEPTH:0] wr_data_count_reg; 31 | wire wr_complete_pulse; 32 | 33 | assign wr_complete_pulse = (wr_data_count > wr_data_count_reg); 34 | assign rd_en = (rd_en_start&wr_complete_pulse); 35 | assign data_out_valid = (rd_en_start&data_in_valid); 36 | 37 | xpm_fifo_sync #( 38 | .DOUT_RESET_VALUE("0"), // String 39 | .ECC_MODE("no_ecc"), // String 40 | .FIFO_MEMORY_TYPE("auto"), // String 41 | .FIFO_READ_LATENCY(0), // DECIMAL 42 | .FIFO_WRITE_DEPTH(1< $filename_to_write 47 | echo "//Multiple pre_def.v with different content for different IP are not allowed in the final signle Vivado project!" >> $filename_to_write 48 | echo "\`define $BOARD_NAME" >> $filename_to_write 49 | done 50 | 51 | MODULE_NAME="" 52 | for ARGUMENT in "$@" 53 | do 54 | if [ "$ARGUMENT" = "xpu" ] || [ "$ARGUMENT" = "tx_intf" ] || [ "$ARGUMENT" = "rx_intf" ] || [ "$ARGUMENT" = "openofdm_tx" ] || [ "$ARGUMENT" = "openofdm_rx" ] || [ "$ARGUMENT" = "side_ch" ]; then 55 | start_to_write=1 56 | fi 57 | 58 | if [ $start_to_write == "1" ]; then 59 | if [ "$ARGUMENT" = "xpu" ] || [ "$ARGUMENT" = "tx_intf" ] || [ "$ARGUMENT" = "rx_intf" ] || [ "$ARGUMENT" = "openofdm_tx" ] || [ "$ARGUMENT" = "openofdm_rx" ] || [ "$ARGUMENT" = "side_ch" ]; then 60 | filename_to_write=ip_config/$ARGUMENT"_pre_def.v" 61 | echo "" >> $filename_to_write 62 | echo "//Pre defines for IP $ARGUMENT. Please align with those when you design/customize/modify the IP" >> $filename_to_write 63 | 64 | echo "" 65 | MODULE_NAME=${ARGUMENT^^} 66 | echo "$MODULE_NAME:" 67 | else 68 | echo "\`define ${MODULE_NAME}_${ARGUMENT}" >> $filename_to_write 69 | 70 | echo "\`define ${MODULE_NAME}_${ARGUMENT}" 71 | fi 72 | fi 73 | done 74 | 75 | source $XILINX_ENV_FILE 76 | 77 | set -x 78 | vivado -source ../ip_repo_gen.tcl 79 | set +x 80 | -------------------------------------------------------------------------------- /boards/sdrpi/src/ccbob_constr.xdc: -------------------------------------------------------------------------------- 1 | 2 | # ports connect to P1 in sdrpi board. 3 | 4 | # // gpio_bd[0] -> P1.gpio1 5 | # // gpio_bd[1] -> P1.gpio2 6 | # // gpio_bd[2] -> P1.gpio3 7 | # // ...... 8 | # // gpio_bd[24] -> P1.gpio25 9 | # // gpio_bd[25] -> P1.gpio26 10 | 11 | 12 | 13 | 14 | set_property -dict { PACKAGE_PIN g14 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[0]] 15 | set_property -dict { PACKAGE_PIN v10 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[1]] 16 | set_property -dict { PACKAGE_PIN w10 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[2]] 17 | set_property -dict { PACKAGE_PIN y9 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[3]] 18 | set_property -dict { PACKAGE_PIN u9 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[4]] 19 | set_property -dict { PACKAGE_PIN v8 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[5]] 20 | set_property -dict { PACKAGE_PIN y7 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[6]] 21 | set_property -dict { PACKAGE_PIN y13 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[7]] 22 | set_property -dict { PACKAGE_PIN v6 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[8]] 23 | set_property -dict { PACKAGE_PIN y12 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[9]] 24 | set_property -dict { PACKAGE_PIN w11 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[10]] 25 | set_property -dict { PACKAGE_PIN t9 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[11]] 26 | set_property -dict { PACKAGE_PIN w9 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[12]] 27 | set_property -dict { PACKAGE_PIN v7 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[13]] 28 | set_property -dict { PACKAGE_PIN u10 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[14]] 29 | set_property -dict { PACKAGE_PIN v11 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[15]] 30 | set_property -dict { PACKAGE_PIN y8 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[16]] 31 | set_property -dict { PACKAGE_PIN y6 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[17]] 32 | set_property -dict { PACKAGE_PIN u8 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[18]] 33 | set_property -dict { PACKAGE_PIN w6 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[19]] 34 | set_property -dict { PACKAGE_PIN u5 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[20]] 35 | set_property -dict { PACKAGE_PIN t5 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[21]] 36 | set_property -dict { PACKAGE_PIN y11 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[22]] 37 | set_property -dict { PACKAGE_PIN u7 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[23]] 38 | set_property -dict { PACKAGE_PIN w8 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[24]] 39 | set_property -dict { PACKAGE_PIN v5 IOSTANDARD LVCMOS25 } [get_ports gpio_bd[25]] 40 | 41 | 42 | -------------------------------------------------------------------------------- /ip/connect_openwifi_ip.tcl: -------------------------------------------------------------------------------- 1 | connect_bd_intf_net -boundary_type upper [get_bd_intf_pins openwifi_ip/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_ACP] 2 | connect_bd_intf_net -boundary_type upper [get_bd_intf_pins openwifi_ip/M00_AXI1] [get_bd_intf_pins sys_ps7/S_AXI_HP3] 3 | connect_bd_net [get_bd_pins openwifi_ip/fifo_rd_en] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en] 4 | connect_bd_net [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout] [get_bd_pins openwifi_ip/fifo_rd_dout] 5 | connect_bd_net [get_bd_pins openwifi_ip/fifo_rd_underflow] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow] 6 | connect_bd_net [get_bd_pins openwifi_ip/dac_data] [get_bd_pins util_ad9361_dac_upack/dac_data] 7 | connect_bd_net [get_bd_pins util_ad9361_dac_upack/dac_valid] [get_bd_pins openwifi_ip/dac_valid] 8 | connect_bd_net [get_bd_pins openwifi_ip/dac_dunf] [get_bd_pins axi_ad9361_dac_fifo/din_unf] 9 | connect_bd_intf_net -boundary_type upper [get_bd_intf_pins openwifi_ip/S00_AXI] [get_bd_intf_pins sys_ps7/M_AXI_GP1] 10 | connect_bd_net [get_bd_pins openwifi_ip/adc_clk] [get_bd_pins util_ad9361_divclk/clk_out] 11 | connect_bd_net [get_bd_pins openwifi_ip/adc_rst] [get_bd_pins util_ad9361_divclk_reset/peripheral_reset] 12 | connect_bd_net [get_bd_pins openwifi_ip/adc_data] [get_bd_pins util_ad9361_adc_pack/adc_data] 13 | connect_bd_net [get_bd_pins openwifi_ip/adc_valid] [get_bd_pins util_ad9361_adc_pack/adc_valid] 14 | connect_bd_net [get_bd_pins openwifi_ip/ext_reset_in] [get_bd_pins sys_ps7/FCLK_RESET2_N] 15 | startgroup 16 | create_bd_port -dir I -from 7 -to 0 gpio_status_1 17 | connect_bd_net [get_bd_pins /openwifi_ip/gpio_status] [get_bd_ports gpio_status_1] 18 | endgroup 19 | connect_bd_net [get_bd_pins openwifi_ip/m_axi_mm2s_aclk] [get_bd_pins sys_ps7/FCLK_CLK2] 20 | connect_bd_net [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] [get_bd_pins sys_ps7/FCLK_CLK2] 21 | connect_bd_net [get_bd_pins sys_ps7/S_AXI_ACP_ACLK] [get_bd_pins sys_ps7/FCLK_CLK2] 22 | connect_bd_net [get_bd_pins sys_ps7/M_AXI_GP1_ACLK] [get_bd_pins sys_ps7/FCLK_CLK2] 23 | delete_bd_objs [get_bd_nets ps_intr_04_1] 24 | connect_bd_net [get_bd_pins sys_concat_intc/In4] [get_bd_pins openwifi_ip/tx_itrpt0] 25 | delete_bd_objs [get_bd_nets ps_intr_05_1] 26 | connect_bd_net [get_bd_pins sys_concat_intc/In5] [get_bd_pins openwifi_ip/tx_itrpt1] 27 | delete_bd_objs [get_bd_nets ps_intr_06_1] 28 | connect_bd_net [get_bd_pins sys_concat_intc/In6] [get_bd_pins openwifi_ip/mm2s_introut] 29 | delete_bd_objs [get_bd_nets ps_intr_02_1] 30 | connect_bd_net [get_bd_pins sys_concat_intc/In2] [get_bd_pins openwifi_ip/mm2s_introut1] 31 | delete_bd_objs [get_bd_nets ps_intr_01_1] 32 | connect_bd_net [get_bd_pins sys_concat_intc/In1] [get_bd_pins openwifi_ip/rx_pkt_intr] 33 | delete_bd_objs [get_bd_nets ps_intr_03_1] 34 | connect_bd_net [get_bd_pins sys_concat_intc/In3] [get_bd_pins openwifi_ip/s2mm_introut] 35 | delete_bd_objs [get_bd_nets ps_intr_07_1] 36 | connect_bd_net [get_bd_pins sys_concat_intc/In7] [get_bd_pins openwifi_ip/s2mm_introut1] 37 | save_bd_design 38 | 39 | -------------------------------------------------------------------------------- /ip/tx_intf/src/csi_fuzzer.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | `timescale 1 ns / 1 ps 4 | 5 | module csi_fuzzer # 6 | ( 7 | parameter integer CSI_FUZZER_WIDTH = 6, 8 | parameter integer IQ_DATA_WIDTH = 16 9 | ) 10 | ( 11 | input wire rstn, 12 | input wire clk, 13 | 14 | // input data 15 | input wire [(2*IQ_DATA_WIDTH-1):0] iq, 16 | input wire iq_valid, 17 | 18 | // FIR coef of the fuzzer 19 | input wire signed [(CSI_FUZZER_WIDTH-1):0] bb_gain1, 20 | input wire bb_gain1_rot90_flag, 21 | input wire signed [(CSI_FUZZER_WIDTH-1):0] bb_gain2, 22 | input wire bb_gain2_rot90_flag, 23 | 24 | // output data 25 | output reg [(2*IQ_DATA_WIDTH-1):0] iq_out 26 | ); 27 | 28 | wire signed [(IQ_DATA_WIDTH-1) : 0] i0; 29 | wire signed [(IQ_DATA_WIDTH-1) : 0] q0; 30 | reg signed [(IQ_DATA_WIDTH-1) : 0] i1; 31 | reg signed [(IQ_DATA_WIDTH-1) : 0] q1; 32 | reg signed [(IQ_DATA_WIDTH-1) : 0] i2; 33 | reg signed [(IQ_DATA_WIDTH-1) : 0] q2; 34 | 35 | reg signed [(CSI_FUZZER_WIDTH+IQ_DATA_WIDTH-1) : 0] tap1_result_i; 36 | reg signed [(CSI_FUZZER_WIDTH+IQ_DATA_WIDTH-1) : 0] tap1_result_q; 37 | reg signed [(CSI_FUZZER_WIDTH+IQ_DATA_WIDTH-1) : 0] tap2_result_i; 38 | reg signed [(CSI_FUZZER_WIDTH+IQ_DATA_WIDTH-1) : 0] tap2_result_q; 39 | 40 | assign i0 = iq[ (IQ_DATA_WIDTH-1) : 0]; 41 | assign q0 = iq[(2*IQ_DATA_WIDTH-1) : IQ_DATA_WIDTH]; 42 | 43 | // delay samples for different taps 44 | always @(posedge clk) 45 | begin 46 | if (!rstn) begin 47 | i1 <= 0; 48 | q1 <= 0; 49 | i2 <= 0; 50 | q2 <= 0; 51 | iq_out <= 0; 52 | tap1_result_i <= 0; 53 | tap1_result_q <= 0; 54 | tap2_result_i <= 0; 55 | tap2_result_q <= 0; 56 | end else begin 57 | if (iq_valid) begin 58 | i2 <= i1; 59 | q2 <= q1; 60 | i1 <= i0; 61 | q1 <= q0; 62 | 63 | iq_out[ (IQ_DATA_WIDTH-1) : 0] <= i0 + tap1_result_i[(CSI_FUZZER_WIDTH+IQ_DATA_WIDTH-1):CSI_FUZZER_WIDTH] + tap2_result_i[(CSI_FUZZER_WIDTH+IQ_DATA_WIDTH-1):CSI_FUZZER_WIDTH]; 64 | iq_out[(2*IQ_DATA_WIDTH-1) : IQ_DATA_WIDTH] <= q0 + tap1_result_q[(CSI_FUZZER_WIDTH+IQ_DATA_WIDTH-1):CSI_FUZZER_WIDTH] + tap2_result_q[(CSI_FUZZER_WIDTH+IQ_DATA_WIDTH-1):CSI_FUZZER_WIDTH]; 65 | 66 | tap1_result_i <= (bb_gain1_rot90_flag==0?(i1*bb_gain1):(-q1*bb_gain1)); 67 | tap1_result_q <= (bb_gain1_rot90_flag==0?(q1*bb_gain1):( i1*bb_gain1)); 68 | 69 | tap2_result_i <= (bb_gain2_rot90_flag==0?(i2*bb_gain2):(-q2*bb_gain2)); 70 | tap2_result_q <= (bb_gain2_rot90_flag==0?(q2*bb_gain2):( i2*bb_gain2)); 71 | end 72 | end 73 | end 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /ip/rx_intf/src/mv_avg.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | module mv_avg 4 | #( 5 | parameter DATA_WIDTH = 16, 6 | parameter LOG2_AVG_LEN = 5 7 | ) 8 | ( 9 | input clk, 10 | input rstn, 11 | 12 | input signed [DATA_WIDTH-1:0] data_in, 13 | input data_in_valid, 14 | 15 | output reg signed [DATA_WIDTH-1:0] data_out, 16 | output reg data_out_valid 17 | ); 18 | 19 | localparam FIFO_SIZE = 1<>1); 39 | assign iq_rssi = ((i_abs_mv_avg+q_abs_mv_avg)>>1); 40 | 41 | dc_rm # ( 42 | .DATA_WIDTH(IQ_DATA_WIDTH) 43 | ) dc_rm_i ( 44 | .clk(clk), 45 | .rstn(rstn), 46 | .ddc_i(ddc_i), 47 | .ddc_q(ddc_q), 48 | .ddc_iq_valid(ddc_iq_valid), 49 | .i_dc_rm(i_dc_rm), 50 | .q_dc_rm(q_dc_rm), 51 | .iq_dc_rm_valid(iq_dc_rm_valid) 52 | ); 53 | 54 | // mv_avg32 # ( 55 | // ) mv_avg32_i ( 56 | // .M_AXIS_DATA_tdata(iq_abs_mv_avg), 57 | // .M_AXIS_DATA_tvalid(iq_rssi_valid), 58 | // .S_AXIS_DATA_tdata({q_abs,i_abs}), 59 | // .S_AXIS_DATA_tready(iq_abs_avg_ready_internal), 60 | // .S_AXIS_DATA_tvalid(iq_dc_rm_valid), 61 | // .aclk(clk), 62 | // .aresetn(rstn) 63 | // ); 64 | 65 | mv_avg_dual_ch #(.DATA_WIDTH0(IQ_DATA_WIDTH), .DATA_WIDTH1(IQ_DATA_WIDTH), .LOG2_AVG_LEN(5)) mv_avg32_dual_ch_inst ( 66 | .clk(clk), 67 | .rstn(rstn), 68 | 69 | .data_in0(i_abs), 70 | .data_in1(q_abs), 71 | .data_in_valid(iq_dc_rm_valid), 72 | 73 | .data_out0(i_abs_mv_avg), 74 | .data_out1(q_abs_mv_avg), 75 | .data_out_valid(iq_rssi_valid) 76 | ); 77 | 78 | // mv_avg #(.DATA_WIDTH(IQ_DATA_WIDTH), .LOG2_AVG_LEN(5)) mv_avg32_i_inst ( 79 | // .clk(clk), 80 | // .rstn(rstn), 81 | 82 | // .data_in(i_abs), 83 | // .data_in_valid(iq_dc_rm_valid), 84 | // .data_out(i_abs_mv_avg), 85 | // .data_out_valid(iq_rssi_valid) 86 | // ); 87 | // mv_avg #(.DATA_WIDTH(IQ_DATA_WIDTH), .LOG2_AVG_LEN(5)) mv_avg32_q_inst ( 88 | // .clk(clk), 89 | // .rstn(rstn), 90 | 91 | // .data_in(q_abs), 92 | // .data_in_valid(iq_dc_rm_valid), 93 | // .data_out(q_abs_mv_avg), 94 | // .data_out_valid() 95 | // ); 96 | 97 | endmodule 98 | -------------------------------------------------------------------------------- /boards/antsdr/src/antsdr_constr.xdc: -------------------------------------------------------------------------------- 1 | 2 | # constraints (pzsdr1.b) 3 | # ad9361 4 | 5 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P 6 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N 7 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports gpio_status[2]] ; ## H25 FMC_LPC_LA21_P 8 | set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports gpio_status[3]] ; ## H26 FMC_LPC_LA21_N 9 | set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports gpio_status[4]] ; ## G24 FMC_LPC_LA22_P 10 | set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS25} [get_ports gpio_status[5]] ; ## G25 FMC_LPC_LA22_N 11 | set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS25} [get_ports gpio_status[6]] ; ## D23 FMC_LPC_LA23_P 12 | set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS25} [get_ports gpio_status[7]] ; ## D24 FMC_LPC_LA23_N 13 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]] ; ## H28 FMC_LPC_LA24_P 14 | set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS33} [get_ports gpio_ctl[1]] ; ## H29 FMC_LPC_LA24_N 15 | set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS33} [get_ports gpio_ctl[2]] ; ## G27 FMC_LPC_LA25_P 16 | set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports gpio_ctl[3]] ; ## G28 FMC_LPC_LA25_N 17 | set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P 18 | set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N 19 | set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P 20 | set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P 21 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N 22 | 23 | set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P 24 | set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N 25 | set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P 26 | set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N 27 | 28 | # iic 29 | set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports gpio_clksel] 30 | set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports clkout_in] 31 | set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_scl] 32 | set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_sda] 33 | -------------------------------------------------------------------------------- /boards/antsdr/src/antsdr_constr_lvds.xdc: -------------------------------------------------------------------------------- 1 | 2 | # constraints (pzsdr1.b) 3 | # ad9361 4 | set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVDS_25 } [get_ports tx_clk_out_n ] 5 | set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25 } [get_ports tx_clk_out_p ] 6 | set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVDS_25 } [get_ports tx_data_out_n[0] ] 7 | set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVDS_25 } [get_ports tx_data_out_p[0] ] 8 | set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVDS_25 } [get_ports tx_data_out_n[1] ] 9 | set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVDS_25 } [get_ports tx_data_out_p[1] ] 10 | set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVDS_25 } [get_ports tx_data_out_n[2] ] 11 | set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVDS_25 } [get_ports tx_data_out_p[2] ] 12 | set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVDS_25 } [get_ports tx_data_out_n[3] ] 13 | set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 } [get_ports tx_data_out_p[3] ] 14 | set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVDS_25 } [get_ports tx_data_out_n[4] ] 15 | set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVDS_25 } [get_ports tx_data_out_p[4] ] 16 | set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVDS_25 } [get_ports tx_data_out_n[5] ] 17 | set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVDS_25 } [get_ports tx_data_out_p[5] ] 18 | set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVDS_25 } [get_ports tx_frame_out_n ] 19 | set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVDS_25 } [get_ports tx_frame_out_p ] 20 | set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_clk_in_n ] 21 | set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_clk_in_p ] 22 | set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_data_in_n[0] ] 23 | set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_data_in_p[0] ] 24 | set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_data_in_n[1] ] 25 | set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_data_in_p[1] ] 26 | set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_data_in_n[2] ] 27 | set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_data_in_p[2] ] 28 | set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_data_in_n[3] ] 29 | set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_data_in_p[3] ] 30 | set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_data_in_n[4] ] 31 | set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_data_in_p[4] ] 32 | set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_data_in_n[5] ] 33 | set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_data_in_p[5] ] 34 | set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_frame_in_n ] 35 | set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVDS_25 DIFF_TERM TRUE } [get_ports rx_frame_in_p ] 36 | 37 | # clocks 38 | 39 | create_clock -name rx_clk -period 8 [get_ports rx_clk_in_p] 40 | 41 | -------------------------------------------------------------------------------- /ip/xpu/src/mv_avg.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | module mv_avg 4 | #( 5 | parameter DATA_WIDTH = 16, 6 | parameter LOG2_AVG_LEN = 5 7 | ) 8 | ( 9 | input clk, 10 | input rstn, 11 | 12 | input signed [DATA_WIDTH-1:0] data_in, 13 | input data_in_valid, 14 | 15 | output wire signed [DATA_WIDTH-1:0] data_out, 16 | output wire data_out_valid 17 | ); 18 | 19 | localparam FIFO_SIZE = 1< wr_data_count_reg); 37 | assign data_out_valid = wr_complete_pulse_reg; 38 | assign data_out = running_total[TOTAL_WIDTH-1:LOG2_AVG_LEN]; 39 | 40 | xpm_fifo_sync #( 41 | .DOUT_RESET_VALUE("0"), // String 42 | .ECC_MODE("no_ecc"), // String 43 | .FIFO_MEMORY_TYPE("auto"), // String 44 | .FIFO_READ_LATENCY(0), // DECIMAL 45 | .FIFO_WRITE_DEPTH(FIFO_SIZE), // DECIMAL minimum 16! 46 | .FULL_RESET_VALUE(0), // DECIMAL 47 | .PROG_EMPTY_THRESH(10), // DECIMAL 48 | .PROG_FULL_THRESH(10), // DECIMAL 49 | .RD_DATA_COUNT_WIDTH(LOG2_AVG_LEN+1), // DECIMAL 50 | .READ_DATA_WIDTH(DATA_WIDTH), // DECIMAL 51 | .READ_MODE("fwft"), // String 52 | .USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count 53 | .WAKEUP_TIME(0), // DECIMAL 54 | .WRITE_DATA_WIDTH(DATA_WIDTH), // DECIMAL 55 | .WR_DATA_COUNT_WIDTH(LOG2_AVG_LEN+1) // DECIMAL 56 | ) fifo_1clk_for_mv_avg_i ( 57 | .almost_empty(), 58 | .almost_full(), 59 | .data_valid(), 60 | .dbiterr(), 61 | .dout(data_in_old), 62 | .empty(empty), 63 | .full(full), 64 | .overflow(), 65 | .prog_empty(), 66 | .prog_full(), 67 | .rd_data_count(), 68 | .rd_rst_busy(), 69 | .sbiterr(), 70 | .underflow(), 71 | .wr_ack(), 72 | .wr_data_count(wr_data_count), 73 | .wr_rst_busy(), 74 | .din(data_in), 75 | .injectdbiterr(), 76 | .injectsbiterr(), 77 | .rd_en(rd_en), 78 | .rst(~rstn), 79 | .sleep(), 80 | .wr_clk(clk), 81 | .wr_en(data_in_valid) 82 | ); 83 | 84 | always @(posedge clk) begin 85 | if (~rstn) begin 86 | data_in_reg <= 0; 87 | wr_data_count_reg <= 0; 88 | running_total <= 0; 89 | rd_en <= 0; 90 | rd_en_start <= 0; 91 | wr_complete_pulse_reg <= 0; 92 | end else begin 93 | wr_complete_pulse_reg <= wr_complete_pulse; 94 | data_in_reg <= (data_in_valid?data_in:data_in_reg); 95 | wr_data_count_reg <= wr_data_count; 96 | rd_en_start <= ((wr_data_count == (FIFO_SIZE))?1:rd_en_start); 97 | rd_en <= (rd_en_start?wr_complete_pulse:rd_en); 98 | if (wr_complete_pulse) begin 99 | running_total <= running_total + ext_data_in - (rd_en_start?ext_data_in_old:0); 100 | end 101 | end 102 | end 103 | 104 | endmodule 105 | -------------------------------------------------------------------------------- /ip/openofdm_tx/src/bimpy.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: ../../ifft64/bimpy.v 4 | // 5 | // Project: A General Purpose Pipelined FFT Implementation 6 | // 7 | // Purpose: A simple 2-bit multiply based upon the fact that LUT's allow 8 | // 6-bits of input. In other words, I could build a 3-bit 9 | // multiply from 6 LUTs (5 actually, since the first could have two 10 | // outputs). This would allow multiplication of three bit digits, save 11 | // only for the fact that you would need two bits of carry. The bimpy 12 | // approach throttles back a bit and does a 2x2 bit multiply in a LUT, 13 | // guaranteeing that it will never carry more than one bit. While this 14 | // multiply is hardware independent (and can still run under Verilator 15 | // therefore), it is really motivated by trying to optimize for a 16 | // specific piece of hardware (Xilinx-7 series ...) that has at least 17 | // 4-input LUT's with carry chains. 18 | // 19 | // 20 | // 21 | // Creator: Dan Gisselquist, Ph.D. 22 | // Gisselquist Technology, LLC 23 | // 24 | //////////////////////////////////////////////////////////////////////////////// 25 | // 26 | // Copyright (C) 2015-2019, Gisselquist Technology, LLC 27 | // 28 | // This file is part of the general purpose pipelined FFT project. 29 | // 30 | // The pipelined FFT project is free software (firmware): you can redistribute 31 | // it and/or modify it under the terms of the GNU Lesser General Public License 32 | // as published by the Free Software Foundation, either version 3 of the 33 | // License, or (at your option) any later version. 34 | // 35 | // The pipelined FFT project is distributed in the hope that it will be useful, 36 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 37 | // MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser 38 | // General Public License for more details. 39 | // 40 | // You should have received a copy of the GNU Lesser General Public License 41 | // along with this program. (It's in the $(ROOT)/doc directory. Run make 42 | // with no target there if the PDF file isn't present.) If not, see 43 | // for a copy. 44 | // 45 | // License: LGPL, v3, as defined and found on www.gnu.org, 46 | // http://www.gnu.org/licenses/lgpl.html 47 | // 48 | // 49 | //////////////////////////////////////////////////////////////////////////////// 50 | // 51 | // 52 | //`default_nettype none 53 | // 54 | module bimpy(i_clk, i_ce, i_a, i_b, o_r); 55 | parameter BW=18; // Number of bits in i_b 56 | localparam LUTB=2; // Number of bits in i_a for our LUT multiply 57 | input wire i_clk, i_ce; 58 | input wire [(LUTB-1):0] i_a; 59 | input wire [(BW-1):0] i_b; 60 | output reg [(BW+LUTB-1):0] o_r; 61 | 62 | wire [(BW+LUTB-2):0] w_r; 63 | wire [(BW+LUTB-3):1] c; 64 | 65 | assign w_r = { ((i_a[1])?i_b:{(BW){1'b0}}), 1'b0 } 66 | ^ { 1'b0, ((i_a[0])?i_b:{(BW){1'b0}}) }; 67 | assign c = { ((i_a[1])?i_b[(BW-2):0]:{(BW-1){1'b0}}) } 68 | & ((i_a[0])?i_b[(BW-1):1]:{(BW-1){1'b0}}); 69 | 70 | initial o_r = 0; 71 | always @(posedge i_clk) 72 | if (i_ce) 73 | o_r <= w_r + { c, 2'b0 }; 74 | 75 | `ifdef FORMAL 76 | reg f_past_valid; 77 | 78 | initial f_past_valid = 1'b0; 79 | always @(posedge i_clk) 80 | f_past_valid <= 1'b1; 81 | 82 | `define ASSERT assert 83 | 84 | always @(posedge i_clk) 85 | if ((f_past_valid)&&($past(i_ce))) 86 | begin 87 | if ($past(i_a)==0) 88 | `ASSERT(o_r == 0); 89 | else if ($past(i_a) == 1) 90 | `ASSERT(o_r == $past(i_b)); 91 | 92 | if ($past(i_b)==0) 93 | `ASSERT(o_r == 0); 94 | else if ($past(i_b) == 1) 95 | `ASSERT(o_r[(LUTB-1):0] == $past(i_a)); 96 | end 97 | `endif 98 | endmodule 99 | -------------------------------------------------------------------------------- /ip/side_ch/src/side_ch_s_axis.v: -------------------------------------------------------------------------------- 1 | // based on Xilinx module template 2 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 3 | 4 | `timescale 1 ns / 1 ps 5 | 6 | module side_ch_s_axis # 7 | ( 8 | parameter integer C_S_AXIS_TDATA_WIDTH = 64, 9 | parameter integer MAX_NUM_DMA_SYMBOL = 8192, 10 | parameter integer MAX_BIT_NUM_DMA_SYMBOL = 14 11 | ) 12 | ( 13 | input wire s_axis_endless_mode, 14 | input wire [MAX_BIT_NUM_DMA_SYMBOL-1 : 0] S_AXIS_NUM_DMA_SYMBOL, 15 | 16 | output wire s_axis_state, 17 | 18 | output wire [C_S_AXIS_TDATA_WIDTH-1 : 0] data_to_pl, 19 | input wire pl_ask_data, 20 | output wire [MAX_BIT_NUM_DMA_SYMBOL-1 : 0] s_axis_data_count, 21 | output wire emptyn_to_pl, 22 | 23 | input wire S_AXIS_ACLK, 24 | input wire S_AXIS_ARESETN, 25 | output wire S_AXIS_TREADY, 26 | input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA, 27 | input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB, 28 | input wire S_AXIS_TLAST, 29 | input wire S_AXIS_TVALID 30 | ); 31 | function integer clogb2 (input integer bit_depth); 32 | begin 33 | for(clogb2=0; bit_depth>0; clogb2=clogb2+1) 34 | bit_depth = bit_depth >> 1; 35 | end 36 | endfunction 37 | 38 | localparam integer bit_num = clogb2(MAX_NUM_DMA_SYMBOL); 39 | 40 | localparam [1:0] IDLE = 1'b0, // This is the initial/idle state 41 | WRITE_FIFO = 1'b1; // In this state FIFO is written with the 42 | 43 | reg mst_exec_state; 44 | 45 | wire axis_tready; 46 | wire fifo_wren; 47 | 48 | reg [bit_num-1:0] write_pointer; 49 | reg writes_done; 50 | 51 | wire EMPTY; 52 | wire FULL; 53 | 54 | assign s_axis_state = mst_exec_state; 55 | assign fifo_wren = (S_AXIS_TVALID && axis_tready); 56 | assign S_AXIS_TREADY= axis_tready; 57 | assign axis_tready = ( (mst_exec_state == WRITE_FIFO) && (write_pointer <= S_AXIS_NUM_DMA_SYMBOL || (s_axis_endless_mode==1)) ) && (!FULL); 58 | assign emptyn_to_pl = (!EMPTY); 59 | 60 | always @(posedge S_AXIS_ACLK) 61 | begin 62 | if (!S_AXIS_ARESETN) 63 | begin 64 | mst_exec_state <= IDLE; 65 | end 66 | else 67 | case (mst_exec_state) 68 | IDLE: 69 | if (S_AXIS_TVALID) 70 | begin 71 | mst_exec_state <= WRITE_FIFO; 72 | end 73 | else 74 | begin 75 | mst_exec_state <= IDLE; 76 | end 77 | WRITE_FIFO: 78 | if (writes_done) 79 | begin 80 | mst_exec_state <= IDLE; 81 | end 82 | else 83 | begin 84 | mst_exec_state <= WRITE_FIFO; 85 | end 86 | endcase 87 | end 88 | 89 | always@(posedge S_AXIS_ACLK) 90 | begin 91 | if ((!S_AXIS_ARESETN) || (writes_done == 1'b1) ) 92 | begin 93 | write_pointer <= 0; 94 | writes_done <= 1'b0; 95 | end 96 | else 97 | if ( write_pointer <= S_AXIS_NUM_DMA_SYMBOL || (s_axis_endless_mode==1) ) 98 | begin 99 | if (fifo_wren) 100 | begin 101 | write_pointer <= write_pointer + 1; 102 | writes_done <= 1'b0; 103 | end 104 | if ( (write_pointer == S_AXIS_NUM_DMA_SYMBOL && (s_axis_endless_mode==0) ) || S_AXIS_TLAST ) 105 | begin 106 | writes_done <= 1'b1; 107 | end 108 | end 109 | end 110 | 111 | fifo64_1clk_dep512 fifo64_1clk_dep512_i ( 112 | .CLK(S_AXIS_ACLK), 113 | .DATAO(data_to_pl), 114 | .DI(S_AXIS_TDATA), 115 | .EMPTY(EMPTY), 116 | .FULL(FULL), 117 | .RDEN(pl_ask_data), 118 | .RST(!S_AXIS_ARESETN), 119 | .WREN(fifo_wren), 120 | .data_count(s_axis_data_count) 121 | ); 122 | 123 | endmodule 124 | -------------------------------------------------------------------------------- /ip/openofdm_tx/src/ht_ltf_rom.v: -------------------------------------------------------------------------------- 1 | /* 2 | * HT long_preamble_rom - TODO 3 | * 4 | * Michael Tetemke Mehari michael.mehari@ugent.be 5 | * Xianjun Jiao xianjun.jiao@imec.be putaoshu@msn.com 6 | */ 7 | `include "openofdm_tx_pre_def.v" 8 | 9 | module ht_ltf_rom 10 | ( 11 | input [6:0] addr, 12 | output reg [31:0] dout 13 | ); 14 | 15 | always @ * 16 | case (addr) 17 | 0: dout = 32'h08000400; 18 | 1: dout = 32'h0F430285; 19 | 2: dout = 32'hFD1FEC0B; 20 | 3: dout = 32'h0782FE9C; 21 | 4: dout = 32'h03220D06; 22 | 5: dout = 32'hEE7DFF47; 23 | 6: dout = 32'h00201579; 24 | 7: dout = 32'h06D4FA1F; 25 | 8: dout = 32'h0C7C0624; 26 | 9: dout = 32'hFB180DF6; 27 | 10: dout = 32'hF1430374; 28 | 11: dout = 32'h07A81176; 29 | 12: dout = 32'h02B4F4BC; 30 | 13: dout = 32'h0C65FD14; 31 | 14: dout = 32'h05170813; 32 | 15: dout = 32'hFF5812D1; 33 | 16: dout = 32'h14000000; 34 | 17: dout = 32'hFF58ED2F; 35 | 18: dout = 32'h0517F7ED; 36 | 19: dout = 32'h0C6502EC; 37 | 20: dout = 32'h02B40B44; 38 | 21: dout = 32'h07A8EE8A; 39 | 22: dout = 32'hF143FC8C; 40 | 23: dout = 32'hFB18F20A; 41 | 24: dout = 32'h0C7CF9DC; 42 | 25: dout = 32'h06D405E1; 43 | 26: dout = 32'h0020EA87; 44 | 27: dout = 32'hEE7D00B9; 45 | 28: dout = 32'h0322F2FA; 46 | 29: dout = 32'h07820164; 47 | 30: dout = 32'hFD1F13F5; 48 | 31: dout = 32'h0F43FD7B; 49 | 32: dout = 32'h0800FC00; 50 | 33: dout = 32'h04BA0788; 51 | 34: dout = 32'hF8AD0A15; 52 | 35: dout = 32'hEF330443; 53 | 36: dout = 32'h0A860E4A; 54 | 37: dout = 32'h08E70134; 55 | 38: dout = 32'hF848094F; 56 | 39: dout = 32'hF8C6FF82; 57 | 40: dout = 32'hFB84E9DC; 58 | 41: dout = 32'hF0660092; 59 | 42: dout = 32'hEFB4FB54; 60 | 43: dout = 32'h099CF7AE; 61 | 44: dout = 32'hFFA40694; 62 | 45: dout = 32'hF43D0E74; 63 | 46: dout = 32'h0BBD0E0D; 64 | 47: dout = 32'h01930C23; 65 | 48: dout = 32'hEC000000; 66 | 49: dout = 32'h0193F3DD; 67 | 50: dout = 32'h0BBDF1F3; 68 | 51: dout = 32'hF43DF18C; 69 | 52: dout = 32'hFFA4F96C; 70 | 53: dout = 32'h099C0852; 71 | 54: dout = 32'hEFB404AC; 72 | 55: dout = 32'hF066FF6E; 73 | 56: dout = 32'hFB841624; 74 | 57: dout = 32'hF8C6007E; 75 | 58: dout = 32'hF848F6B1; 76 | 59: dout = 32'h08E7FECC; 77 | 60: dout = 32'h0A86F1B6; 78 | 61: dout = 32'hEF33FBBD; 79 | 62: dout = 32'hF8ADF5EB; 80 | 63: dout = 32'h04BAF878; 81 | 64: dout = 32'h08000400; 82 | 65: dout = 32'h0F430285; 83 | 66: dout = 32'hFD1FEC0B; 84 | 67: dout = 32'h0782FE9C; 85 | 68: dout = 32'h03220D06; 86 | 69: dout = 32'hEE7DFF47; 87 | 70: dout = 32'h00201579; 88 | 71: dout = 32'h06D4FA1F; 89 | 72: dout = 32'h0C7C0624; 90 | 73: dout = 32'hFB180DF6; 91 | 74: dout = 32'hF1430374; 92 | 75: dout = 32'h07A81176; 93 | 76: dout = 32'h02B4F4BC; 94 | 77: dout = 32'h0C65FD14; 95 | 78: dout = 32'h05170813; 96 | 79: dout = 32'hFF5812D1; 97 | 98 | default: dout = 32'h00000000; 99 | endcase 100 | 101 | endmodule 102 | -------------------------------------------------------------------------------- /ip/side_ch/src/side_ch_counter.v: -------------------------------------------------------------------------------- 1 | 2 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 3 | 4 | `include "side_ch_pre_def.v" 5 | 6 | `ifdef SIDE_CH_ENABLE_DBG 7 | `define DEBUG_PREFIX (*mark_debug="true",DONT_TOUCH="TRUE"*) 8 | `else 9 | `define DEBUG_PREFIX 10 | `endif 11 | 12 | `timescale 1 ns / 1 ps 13 | 14 | module side_ch_counter # 15 | ( 16 | // parameter integer TSF_TIMER_WIDTH = 64, // according to 802.11 standard 17 | 18 | // parameter integer GPIO_STATUS_WIDTH = 8, 19 | // parameter integer RSSI_HALF_DB_WIDTH = 11, 20 | // parameter integer C_S_AXI_DATA_WIDTH = 32, 21 | // parameter integer IQ_DATA_WIDTH = 16, 22 | // parameter integer C_S_AXIS_TDATA_WIDTH = 64, 23 | // parameter integer MAX_NUM_DMA_SYMBOL = 8192, 24 | // parameter integer MAX_BIT_NUM_DMA_SYMBOL = 14 25 | parameter integer COUNTER_WIDTH = 16 26 | ) 27 | ( 28 | input wire clk, 29 | // input wire rstn, 30 | 31 | // from arm. capture reg write to clear the corresponding counter 32 | input wire slv_reg_wren_signal, 33 | input wire [4:0] axi_awaddr_core, 34 | 35 | // counter++ event input 36 | input wire event0, 37 | input wire event1, 38 | input wire event2, 39 | input wire event3, 40 | input wire event4, 41 | input wire event5, 42 | 43 | output reg [COUNTER_WIDTH-1 : 0] counter0, 44 | output reg [COUNTER_WIDTH-1 : 0] counter1, 45 | output reg [COUNTER_WIDTH-1 : 0] counter2, 46 | output reg [COUNTER_WIDTH-1 : 0] counter3, 47 | output reg [COUNTER_WIDTH-1 : 0] counter4, 48 | output reg [COUNTER_WIDTH-1 : 0] counter5 49 | ); 50 | 51 | reg event0_reg; 52 | reg event1_reg; 53 | reg event2_reg; 54 | reg event3_reg; 55 | reg event4_reg; 56 | reg event5_reg; 57 | 58 | wire counter0_rst; 59 | wire counter1_rst; 60 | wire counter2_rst; 61 | wire counter3_rst; 62 | wire counter4_rst; 63 | wire counter5_rst; 64 | 65 | assign counter0_rst = (slv_reg_wren_signal==1 && axi_awaddr_core==26);//slv_reg26 wr 66 | assign counter1_rst = (slv_reg_wren_signal==1 && axi_awaddr_core==27);//slv_reg27 wr 67 | assign counter2_rst = (slv_reg_wren_signal==1 && axi_awaddr_core==28);//slv_reg28 wr 68 | assign counter3_rst = (slv_reg_wren_signal==1 && axi_awaddr_core==29);//slv_reg29 wr 69 | assign counter4_rst = (slv_reg_wren_signal==1 && axi_awaddr_core==30);//slv_reg30 wr 70 | assign counter5_rst = (slv_reg_wren_signal==1 && axi_awaddr_core==31);//slv_reg31 wr 71 | 72 | always @(posedge clk) begin 73 | if (counter0_rst) begin 74 | counter0 <= 0; 75 | event0_reg <= 0; 76 | end else begin 77 | event0_reg <= event0; 78 | if (event0==1 && event0_reg==0) begin 79 | counter0 <= counter0 + 1; 80 | end 81 | end 82 | end 83 | always @(posedge clk) begin 84 | if (counter1_rst) begin 85 | counter1 <= 0; 86 | event1_reg <= 0; 87 | end else begin 88 | event1_reg <= event1; 89 | if (event1==1 && event1_reg==0) begin 90 | counter1 <= counter1 + 1; 91 | end 92 | end 93 | end 94 | always @(posedge clk) begin 95 | if (counter2_rst) begin 96 | counter2 <= 0; 97 | event2_reg <= 0; 98 | end else begin 99 | event2_reg <= event2; 100 | if (event2==1 && event2_reg==0) begin 101 | counter2 <= counter2 + 1; 102 | end 103 | end 104 | end 105 | always @(posedge clk) begin 106 | if (counter3_rst) begin 107 | counter3 <= 0; 108 | event3_reg <= 0; 109 | end else begin 110 | event3_reg <= event3; 111 | if (event3==1 && event3_reg==0) begin 112 | counter3 <= counter3 + 1; 113 | end 114 | end 115 | end 116 | always @(posedge clk) begin 117 | if (counter4_rst) begin 118 | counter4 <= 0; 119 | event4_reg <= 0; 120 | end else begin 121 | event4_reg <= event4; 122 | if (event4==1 && event4_reg==0) begin 123 | counter4 <= counter4 + 1; 124 | end 125 | end 126 | end 127 | always @(posedge clk) begin 128 | if (counter5_rst) begin 129 | counter5 <= 0; 130 | event5_reg <= 0; 131 | end else begin 132 | event5_reg <= event5; 133 | if (event5==1 && event5_reg==0) begin 134 | counter5 <= counter5 + 1; 135 | end 136 | end 137 | end 138 | endmodule 139 | -------------------------------------------------------------------------------- /boards/neptunesdr/src/neptunesdr_constr.xdc: -------------------------------------------------------------------------------- 1 | # constraints (pzsdr1.b) 2 | # ad9361 3 | 4 | set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports enable] ; ## IO_L10P_T1_AD11P_35 U1,K19,IO_L10_35_ENABLE 5 | set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35 U1,L17,IO_L11_35_TXNRX 6 | 7 | set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35 U1,H15,IO_L19_35_CTRL_OUT0 8 | set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35 U1,G15,IO_L19_35_CTRL_OUT1 9 | set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gpio_status[2]] ; ## IO_L20P_T3_AD6P_35 U1,K14,IO_L20_35_CTRL_OUT2 10 | set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS25} [get_ports gpio_status[3]] ; ## IO_L20N_T3_AD6N_35 U1,J14,IO_L20_35_CTRL_OUT3 11 | set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gpio_status[4]] ; ## IO_L21P_T3_DQS_AD14P_35 U1,N15,IO_L21_35_CTRL_OUT4 12 | set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS25} [get_ports gpio_status[5]] ; ## IO_L21N_T3_DQS_AD14N_35 U1,N16,IO_L21_35_CTRL_OUT5 13 | set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS25} [get_ports gpio_status[6]] ; ## IO_L22P_T3_AD7P_35 U1,L14,IO_L22_35_CTRL_OUT6 14 | set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports gpio_status[7]] ; ## IO_L22N_T3_AD7N_35 U1,L15,IO_L22_35_CTRL_OUT7 15 | set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]] ; ## IO_L23P_T3_34 U1,N17,IO_L23_34_CTRL_IN0 16 | set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]] ; ## IO_L23N_T3_34 U1,P18,IO_L23_34_CTRL_IN1 17 | set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]] ; ## IO_L24P_T3_34 U1,P15,IO_L24_34_CTRL_IN2 18 | set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]] ; ## IO_L24N_T3_34 U1,P16,IO_L24_34_CTRL_IN3 19 | set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## IO_L11P_T1_SRCC_35 U1,L16,IO_L11_35_EN_AGC 20 | set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## IO_L10N_T1_AD11N_35 U1,J19,IO_L10_35_SYNC_IN 21 | set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## IO_0_35 U1,G14,IO_00_35_AD9364_RST 22 | set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports gpio_clksel] ; ## IO_0_34 NO USE U1,R19,IO_00_34_AD9364_CLKSEL 23 | 24 | set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## IO_L23P_T3_35 U1,M14,IO_L23_35_SPI_ENB 25 | set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## IO_L23N_T3_35 U1,M15,IO_L23_35_SPI_CLK 26 | set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## IO_L24P_T3_AD15P_35 U1,K16,IO_L24_35_SPI_DI 27 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## IO_L24N_T3_AD15N_35 U1,J16,IO_L24_35_SPI_DO 28 | 29 | set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports clkout_in] ; ## IO_25_35 U1,J15,IO_25_35_AD9364_CLKOUT 30 | 31 | # iic 32 | 33 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl] ; ## IO_L22N_T3_13 U1,W6,SCL,JX2,17,I2C_SCL 34 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda] ; ## IO_L22P_T3_13 U1,V6,SDA,JX2,19,I2C_SDA -------------------------------------------------------------------------------- /ip/side_ch/src/side_ch_counter_event_cfg.v: -------------------------------------------------------------------------------- 1 | 2 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 3 | 4 | `include "side_ch_pre_def.v" 5 | 6 | `ifdef SIDE_CH_ENABLE_DBG 7 | `define DEBUG_PREFIX (*mark_debug="true",DONT_TOUCH="TRUE"*) 8 | `else 9 | `define DEBUG_PREFIX 10 | `endif 11 | 12 | `timescale 1 ns / 1 ps 13 | 14 | module side_ch_counter_event_cfg # 15 | ( 16 | // parameter integer TSF_TIMER_WIDTH = 64, // according to 802.11 standard 17 | 18 | parameter integer GPIO_STATUS_WIDTH = 8, 19 | parameter integer RSSI_HALF_DB_WIDTH = 11, 20 | parameter integer C_S_AXI_DATA_WIDTH = 32 21 | // parameter integer IQ_DATA_WIDTH = 16, 22 | // parameter integer C_S_AXIS_TDATA_WIDTH = 64, 23 | // parameter integer MAX_NUM_DMA_SYMBOL = 8192, 24 | // parameter integer MAX_BIT_NUM_DMA_SYMBOL = 14 25 | // parameter integer COUNTER_WIDTH = 16 26 | ) 27 | ( 28 | input wire clk, 29 | input wire rstn, 30 | 31 | // original event source 32 | input wire [(GPIO_STATUS_WIDTH-2):0] gain_th, 33 | input wire signed [(RSSI_HALF_DB_WIDTH-1):0] rssi_half_db_th, 34 | input wire [(GPIO_STATUS_WIDTH-1):0] gpio_status, 35 | input wire signed [(RSSI_HALF_DB_WIDTH-1):0] rssi_half_db, 36 | 37 | input wire short_preamble_detected, 38 | input wire long_preamble_detected, 39 | 40 | input wire pkt_header_valid_strobe, 41 | input wire pkt_header_valid, 42 | 43 | input wire [C_S_AXI_DATA_WIDTH-1 : 0] addr2_target, 44 | input wire [47:0] addr2, 45 | input wire pkt_for_me, 46 | input wire is_data, 47 | 48 | input wire fcs_in_strobe, 49 | input wire fcs_ok, 50 | 51 | input wire phy_tx_start, 52 | input wire phy_tx_done, 53 | input wire tx_pkt_need_ack, 54 | 55 | // from arm. event source select 56 | input wire event0_sel, 57 | input wire event1_sel, 58 | input wire event2_sel, 59 | input wire event3_sel, 60 | input wire event4_sel, 61 | input wire event5_sel, 62 | 63 | // counter++ event output 64 | output reg event0, 65 | output reg event1, 66 | output reg event2, 67 | output reg event3, 68 | output reg event4, 69 | output reg event5 70 | ); 71 | 72 | reg [(GPIO_STATUS_WIDTH-2):0] gpio_status_reg; 73 | wire agc_lock; 74 | wire gain_change; 75 | wire rssi_above_th; 76 | wire addr2_match; 77 | 78 | assign agc_lock = gpio_status[GPIO_STATUS_WIDTH-1]; 79 | assign gain_change = (gpio_status[(GPIO_STATUS_WIDTH-2):0] != gpio_status_reg); 80 | assign rssi_above_th = (rssi_half_db> rssi_half_db_th); 81 | assign addr2_match = ({addr2[23:16],addr2[31:24],addr2[39:32],addr2[47:40]} == addr2_target); 82 | 83 | always @(posedge clk) begin 84 | if (!rstn) begin 85 | gpio_status_reg <= 0; 86 | end else begin 87 | gpio_status_reg <= gpio_status[(GPIO_STATUS_WIDTH-2):0]; 88 | end 89 | end 90 | 91 | always @( event0_sel, short_preamble_detected, phy_tx_start ) 92 | begin 93 | case (event0_sel) 94 | 0: begin event0 <= short_preamble_detected; end 95 | 1: begin event0 <= phy_tx_start; end 96 | endcase 97 | end 98 | 99 | always @( event1_sel, long_preamble_detected, phy_tx_done ) 100 | begin 101 | case (event1_sel) 102 | 0: begin event1 <= long_preamble_detected; end 103 | 1: begin event1 <= phy_tx_done; end 104 | endcase 105 | end 106 | 107 | always @( event2_sel, pkt_header_valid_strobe, rssi_above_th) 108 | begin 109 | case (event2_sel) 110 | 0: begin event2 <= pkt_header_valid_strobe; end 111 | 1: begin event2 <= rssi_above_th; end 112 | endcase 113 | end 114 | 115 | always @( event3_sel, pkt_header_valid_strobe, pkt_header_valid, gain_change) 116 | begin 117 | case (event3_sel) 118 | 0: begin event3 <= (pkt_header_valid_strobe&pkt_header_valid); end 119 | 1: begin event3 <= gain_change; end 120 | endcase 121 | end 122 | 123 | always @( event4_sel, fcs_in_strobe, addr2_match, pkt_for_me, is_data, agc_lock) 124 | begin 125 | case (event4_sel) 126 | 0: begin event4 <= (((fcs_in_strobe&addr2_match)&pkt_for_me)&is_data); end 127 | 1: begin event4 <= agc_lock; end 128 | endcase 129 | end 130 | 131 | always @( event5_sel, fcs_in_strobe, fcs_ok, addr2_match, pkt_for_me, is_data, tx_pkt_need_ack) 132 | begin 133 | case (event5_sel) 134 | 0: begin event5 <= ((((fcs_in_strobe&fcs_ok)&addr2_match)&pkt_for_me)&is_data); end 135 | 1: begin event5 <= tx_pkt_need_ack; end 136 | endcase 137 | end 138 | 139 | endmodule 140 | -------------------------------------------------------------------------------- /boards/zcu102_fmcs2/src/system_wrapper.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | // based on Xilinx Vivado auto generated script. openwifi add necessary modifications. 3 | //Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 4 | //-------------------------------------------------------------------------------- 5 | //Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018 6 | //Date : Mon Mar 9 17:57:32 2020 7 | //Host : jxj-xps running 64-bit Ubuntu 18.04.4 LTS 8 | //Command : generate_target system_wrapper.bd 9 | //Design : system_wrapper 10 | //Purpose : IP block netlist 11 | //-------------------------------------------------------------------------------- 12 | `timescale 1 ps / 1 ps 13 | 14 | module system_wrapper 15 | (enable, 16 | gpio_i, 17 | gpio_o, 18 | gpio_t, 19 | gpio_pmod1_0, 20 | gpio_pmod1_1, 21 | gpio_pmod1_2, 22 | rx_clk_in_n, 23 | rx_clk_in_p, 24 | rx_data_in_n, 25 | rx_data_in_p, 26 | rx_frame_in_n, 27 | rx_frame_in_p, 28 | spi0_csn, 29 | spi0_miso, 30 | spi0_mosi, 31 | spi0_sclk, 32 | spi1_csn, 33 | spi1_miso, 34 | spi1_mosi, 35 | spi1_sclk, 36 | tdd_sync_i, 37 | tdd_sync_o, 38 | tdd_sync_t, 39 | tx_clk_out_n, 40 | tx_clk_out_p, 41 | tx_data_out_n, 42 | tx_data_out_p, 43 | tx_frame_out_n, 44 | tx_frame_out_p, 45 | txnrx, 46 | up_enable, 47 | up_txnrx); 48 | output enable; 49 | input [94:0]gpio_i; 50 | output [94:0]gpio_o; 51 | output [94:0]gpio_t; 52 | output gpio_pmod1_0; 53 | output gpio_pmod1_1; 54 | output gpio_pmod1_2; 55 | input rx_clk_in_n; 56 | input rx_clk_in_p; 57 | input [5:0]rx_data_in_n; 58 | input [5:0]rx_data_in_p; 59 | input rx_frame_in_n; 60 | input rx_frame_in_p; 61 | output [2:0]spi0_csn; 62 | input spi0_miso; 63 | output spi0_mosi; 64 | output spi0_sclk; 65 | output [2:0]spi1_csn; 66 | input spi1_miso; 67 | output spi1_mosi; 68 | output spi1_sclk; 69 | input tdd_sync_i; 70 | output tdd_sync_o; 71 | output tdd_sync_t; 72 | output tx_clk_out_n; 73 | output tx_clk_out_p; 74 | output [5:0]tx_data_out_n; 75 | output [5:0]tx_data_out_p; 76 | output tx_frame_out_n; 77 | output tx_frame_out_p; 78 | output txnrx; 79 | input up_enable; 80 | input up_txnrx; 81 | 82 | wire enable; 83 | wire [94:0]gpio_i; 84 | wire [94:0]gpio_o; 85 | wire [94:0]gpio_t; 86 | wire gpio_pmod1_0; 87 | wire gpio_pmod1_1; 88 | wire gpio_pmod1_2; 89 | wire rx_clk_in_n; 90 | wire rx_clk_in_p; 91 | wire [5:0]rx_data_in_n; 92 | wire [5:0]rx_data_in_p; 93 | wire rx_frame_in_n; 94 | wire rx_frame_in_p; 95 | wire [2:0]spi0_csn; 96 | wire spi0_miso; 97 | wire spi0_mosi; 98 | wire spi0_sclk; 99 | wire [2:0]spi1_csn; 100 | wire spi1_miso; 101 | wire spi1_mosi; 102 | wire spi1_sclk; 103 | wire tdd_sync_i; 104 | wire tdd_sync_o; 105 | wire tdd_sync_t; 106 | wire tx_clk_out_n; 107 | wire tx_clk_out_p; 108 | wire [5:0]tx_data_out_n; 109 | wire [5:0]tx_data_out_p; 110 | wire tx_frame_out_n; 111 | wire tx_frame_out_p; 112 | wire txnrx; 113 | wire up_enable; 114 | wire up_txnrx; 115 | 116 | system system_i 117 | (.enable(enable), 118 | .gpio_i(gpio_i), 119 | .gpio_o(gpio_o), 120 | .gpio_t(gpio_t), 121 | .gpio_pmod1_0(gpio_pmod1_0), 122 | .gpio_pmod1_1(gpio_pmod1_1), 123 | .gpio_pmod1_2(gpio_pmod1_2), 124 | .rx_clk_in_n(rx_clk_in_n), 125 | .rx_clk_in_p(rx_clk_in_p), 126 | .rx_data_in_n(rx_data_in_n), 127 | .rx_data_in_p(rx_data_in_p), 128 | .rx_frame_in_n(rx_frame_in_n), 129 | .rx_frame_in_p(rx_frame_in_p), 130 | .spi0_csn(spi0_csn), 131 | .spi0_miso(spi0_miso), 132 | .spi0_mosi(spi0_mosi), 133 | .spi0_sclk(spi0_sclk), 134 | .spi1_csn(spi1_csn), 135 | .spi1_miso(spi1_miso), 136 | .spi1_mosi(spi1_mosi), 137 | .spi1_sclk(spi1_sclk), 138 | .tdd_sync_i(tdd_sync_i), 139 | .tdd_sync_o(tdd_sync_o), 140 | .tdd_sync_t(tdd_sync_t), 141 | .tx_clk_out_n(tx_clk_out_n), 142 | .tx_clk_out_p(tx_clk_out_p), 143 | .tx_data_out_n(tx_data_out_n), 144 | .tx_data_out_p(tx_data_out_p), 145 | .tx_frame_out_n(tx_frame_out_n), 146 | .tx_frame_out_p(tx_frame_out_p), 147 | .txnrx(txnrx), 148 | .up_enable(up_enable), 149 | .up_txnrx(up_txnrx)); 150 | endmodule 151 | -------------------------------------------------------------------------------- /ip/xpu/src/mv_avg_dual_ch.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | module mv_avg_dual_ch 4 | #( 5 | parameter DATA_WIDTH0 = 16, 6 | parameter DATA_WIDTH1 = 16, 7 | parameter LOG2_AVG_LEN = 5 8 | ) 9 | ( 10 | input clk, 11 | input rstn, 12 | 13 | input signed [DATA_WIDTH0-1:0] data_in0, 14 | input signed [DATA_WIDTH1-1:0] data_in1, 15 | input data_in_valid, 16 | 17 | output signed [DATA_WIDTH0-1:0] data_out0, 18 | output signed [DATA_WIDTH1-1:0] data_out1, 19 | output data_out_valid 20 | ); 21 | 22 | localparam FIFO_SIZE = 1< wr_data_count_reg); 46 | assign data_out_valid = wr_complete_pulse_reg; 47 | assign data_out0 = running_total0[TOTAL_WIDTH0-1:LOG2_AVG_LEN]; 48 | assign data_out1 = running_total1[TOTAL_WIDTH1-1:LOG2_AVG_LEN]; 49 | 50 | xpm_fifo_sync #( 51 | .DOUT_RESET_VALUE("0"), // String 52 | .ECC_MODE("no_ecc"), // String 53 | .FIFO_MEMORY_TYPE("auto"), // String 54 | .FIFO_READ_LATENCY(0), // DECIMAL 55 | .FIFO_WRITE_DEPTH(FIFO_SIZE), // DECIMAL minimum 16! 56 | .FULL_RESET_VALUE(0), // DECIMAL 57 | .PROG_EMPTY_THRESH(10), // DECIMAL 58 | .PROG_FULL_THRESH(10), // DECIMAL 59 | .RD_DATA_COUNT_WIDTH(LOG2_AVG_LEN+1), // DECIMAL 60 | .READ_DATA_WIDTH(DATA_WIDTH0+DATA_WIDTH1), // DECIMAL 61 | .READ_MODE("fwft"), // String 62 | .USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count 63 | .WAKEUP_TIME(0), // DECIMAL 64 | .WRITE_DATA_WIDTH(DATA_WIDTH0+DATA_WIDTH1), // DECIMAL 65 | .WR_DATA_COUNT_WIDTH(LOG2_AVG_LEN+1) // DECIMAL 66 | ) fifo_1clk_for_mv_avg_dual_ch_i ( 67 | .almost_empty(), 68 | .almost_full(), 69 | .data_valid(), 70 | .dbiterr(), 71 | .dout({data_in_old1, data_in_old0}), 72 | .empty(empty), 73 | .full(full), 74 | .overflow(), 75 | .prog_empty(), 76 | .prog_full(), 77 | .rd_data_count(), 78 | .rd_rst_busy(), 79 | .sbiterr(), 80 | .underflow(), 81 | .wr_ack(), 82 | .wr_data_count(wr_data_count), 83 | .wr_rst_busy(), 84 | .din({data_in1, data_in0}), 85 | .injectdbiterr(), 86 | .injectsbiterr(), 87 | .rd_en(rd_en), 88 | .rst(~rstn), 89 | .sleep(), 90 | .wr_clk(clk), 91 | .wr_en(data_in_valid) 92 | ); 93 | 94 | always @(posedge clk) begin 95 | if (~rstn) begin 96 | data_in0_reg <= 0; 97 | data_in1_reg <= 0; 98 | wr_complete_pulse_reg <= 0; 99 | wr_data_count_reg <= 0; 100 | running_total0 <= 0; 101 | running_total1 <= 0; 102 | rd_en <= 0; 103 | rd_en_start <= 0; 104 | end else begin 105 | data_in0_reg <= (data_in_valid?data_in0:data_in0_reg); 106 | data_in1_reg <= (data_in_valid?data_in1:data_in1_reg); 107 | wr_complete_pulse_reg <= wr_complete_pulse; 108 | wr_data_count_reg <= wr_data_count; 109 | rd_en_start <= ((wr_data_count == (FIFO_SIZE))?1:rd_en_start); 110 | rd_en <= (rd_en_start?wr_complete_pulse:rd_en); 111 | if (wr_complete_pulse) begin 112 | running_total0 <= running_total0 + ext_data_in0 - (rd_en_start?ext_data_in_old0:0); 113 | running_total1 <= running_total1 + ext_data_in1 - (rd_en_start?ext_data_in_old1:0); 114 | end 115 | end 116 | end 117 | 118 | endmodule 119 | -------------------------------------------------------------------------------- /ip/rx_intf/src/mv_avg_dual_ch.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | module mv_avg_dual_ch 4 | #( 5 | parameter DATA_WIDTH0 = 16, 6 | parameter DATA_WIDTH1 = 16, 7 | parameter LOG2_AVG_LEN = 5 8 | ) 9 | ( 10 | input clk, 11 | input rstn, 12 | 13 | input signed [DATA_WIDTH0-1:0] data_in0, 14 | input signed [DATA_WIDTH1-1:0] data_in1, 15 | input data_in_valid, 16 | 17 | output signed [DATA_WIDTH0-1:0] data_out0, 18 | output signed [DATA_WIDTH1-1:0] data_out1, 19 | output data_out_valid 20 | ); 21 | 22 | localparam FIFO_SIZE = 1< wr_data_count_reg); 46 | assign data_out_valid = wr_complete_pulse_reg; 47 | assign data_out0 = running_total0[TOTAL_WIDTH0-1:LOG2_AVG_LEN]; 48 | assign data_out1 = running_total1[TOTAL_WIDTH1-1:LOG2_AVG_LEN]; 49 | 50 | xpm_fifo_sync #( 51 | .DOUT_RESET_VALUE("0"), // String 52 | .ECC_MODE("no_ecc"), // String 53 | .FIFO_MEMORY_TYPE("auto"), // String 54 | .FIFO_READ_LATENCY(0), // DECIMAL 55 | .FIFO_WRITE_DEPTH(FIFO_SIZE), // DECIMAL minimum 16! 56 | .FULL_RESET_VALUE(0), // DECIMAL 57 | .PROG_EMPTY_THRESH(10), // DECIMAL 58 | .PROG_FULL_THRESH(10), // DECIMAL 59 | .RD_DATA_COUNT_WIDTH(LOG2_AVG_LEN+1), // DECIMAL 60 | .READ_DATA_WIDTH(DATA_WIDTH0+DATA_WIDTH1), // DECIMAL 61 | .READ_MODE("fwft"), // String 62 | .USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count 63 | .WAKEUP_TIME(0), // DECIMAL 64 | .WRITE_DATA_WIDTH(DATA_WIDTH0+DATA_WIDTH1), // DECIMAL 65 | .WR_DATA_COUNT_WIDTH(LOG2_AVG_LEN+1) // DECIMAL 66 | ) fifo_1clk_for_mv_avg_dual_ch_i ( 67 | .almost_empty(), 68 | .almost_full(), 69 | .data_valid(), 70 | .dbiterr(), 71 | .dout({data_in_old1, data_in_old0}), 72 | .empty(empty), 73 | .full(full), 74 | .overflow(), 75 | .prog_empty(), 76 | .prog_full(), 77 | .rd_data_count(), 78 | .rd_rst_busy(), 79 | .sbiterr(), 80 | .underflow(), 81 | .wr_ack(), 82 | .wr_data_count(wr_data_count), 83 | .wr_rst_busy(), 84 | .din({data_in1, data_in0}), 85 | .injectdbiterr(), 86 | .injectsbiterr(), 87 | .rd_en(rd_en), 88 | .rst(~rstn), 89 | .sleep(), 90 | .wr_clk(clk), 91 | .wr_en(data_in_valid) 92 | ); 93 | 94 | always @(posedge clk) begin 95 | if (~rstn) begin 96 | data_in0_reg <= 0; 97 | data_in1_reg <= 0; 98 | wr_complete_pulse_reg <= 0; 99 | wr_data_count_reg <= 0; 100 | running_total0 <= 0; 101 | running_total1 <= 0; 102 | rd_en <= 0; 103 | rd_en_start <= 0; 104 | end else begin 105 | data_in0_reg <= (data_in_valid?data_in0:data_in0_reg); 106 | data_in1_reg <= (data_in_valid?data_in1:data_in1_reg); 107 | wr_complete_pulse_reg <= wr_complete_pulse; 108 | wr_data_count_reg <= wr_data_count; 109 | rd_en_start <= ((wr_data_count == (FIFO_SIZE))?1:rd_en_start); 110 | rd_en <= (rd_en_start?wr_complete_pulse:rd_en); 111 | if (wr_complete_pulse) begin 112 | running_total0 <= running_total0 + ext_data_in0 - (rd_en_start?ext_data_in_old0:0); 113 | running_total1 <= running_total1 + ext_data_in1 - (rd_en_start?ext_data_in_old1:0); 114 | end 115 | end 116 | end 117 | 118 | endmodule 119 | -------------------------------------------------------------------------------- /ip/xpu/src/time_slice_gen.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | `timescale 1 ns / 1 ps 4 | 5 | `include "xpu_pre_def.v" 6 | 7 | `ifdef XPU_ENABLE_DBG 8 | `define DEBUG_PREFIX (*mark_debug="true",DONT_TOUCH="TRUE"*) 9 | `else 10 | `define DEBUG_PREFIX 11 | `endif 12 | 13 | module time_slice_gen # 14 | ( 15 | ) 16 | (// generate time slice for tx_control.v 17 | input wire clk, 18 | input wire rstn, 19 | 20 | input wire tsf_pulse_1M, 21 | 22 | input wire slv_reg_wren_signal, 23 | input wire [1:0] count_total_slice_idx, 24 | input wire [19:0] count_total, 25 | input wire [1:0] count_start_slice_idx, 26 | input wire [19:0] count_start, 27 | input wire [1:0] count_end_slice_idx, 28 | input wire [19:0] count_end, 29 | 30 | output wire cycle_start0, 31 | 32 | output reg slice_en0, 33 | output reg slice_en1, 34 | output reg slice_en2, 35 | output reg slice_en3 36 | ); 37 | 38 | reg [19:0] count_total0; 39 | reg [19:0] count_total1; 40 | reg [19:0] count_total2; 41 | reg [19:0] count_total3; 42 | 43 | reg [19:0] count_start0; 44 | reg [19:0] count_start1; 45 | reg [19:0] count_start2; 46 | reg [19:0] count_start3; 47 | 48 | reg [19:0] count_end0; 49 | reg [19:0] count_end1; 50 | reg [19:0] count_end2; 51 | reg [19:0] count_end3; 52 | 53 | reg [19:0] counter0; 54 | reg [19:0] counter1; 55 | reg [19:0] counter2; 56 | reg [19:0] counter3; 57 | 58 | assign cycle_start0 = (counter0==count_total0); 59 | 60 | always @( posedge clk ) begin 61 | if ( rstn == 0 ) begin 62 | count_total0 <= count_total0; 63 | count_total1 <= count_total1; 64 | count_total2 <= count_total2; 65 | count_total3 <= count_total3; 66 | 67 | count_start0 <= count_start0; 68 | count_start1 <= count_start1; 69 | count_start2 <= count_start2; 70 | count_start3 <= count_start3; 71 | 72 | count_end0 <= count_end0; 73 | count_end1 <= count_end1; 74 | count_end2 <= count_end2; 75 | count_end3 <= count_end3; 76 | 77 | counter0 <= 0; 78 | counter1 <= 0; 79 | counter2 <= 0; 80 | counter3 <= 0; 81 | 82 | slice_en0 <= 1; 83 | slice_en1 <= 1; 84 | slice_en2 <= 1; 85 | slice_en3 <= 1; 86 | end else begin 87 | // capture input value to correct slice register 88 | count_total0 <= ( (slv_reg_wren_signal==1 && count_total_slice_idx==0)?count_total:count_total0 ); 89 | count_total1 <= ( (slv_reg_wren_signal==1 && count_total_slice_idx==1)?count_total:count_total1 ); 90 | count_total2 <= ( (slv_reg_wren_signal==1 && count_total_slice_idx==2)?count_total:count_total2 ); 91 | count_total3 <= ( (slv_reg_wren_signal==1 && count_total_slice_idx==3)?count_total:count_total3 ); 92 | 93 | count_start0 <= ( (slv_reg_wren_signal==1 && count_start_slice_idx==0)?count_start:count_start0 ); 94 | count_start1 <= ( (slv_reg_wren_signal==1 && count_start_slice_idx==1)?count_start:count_start1 ); 95 | count_start2 <= ( (slv_reg_wren_signal==1 && count_start_slice_idx==2)?count_start:count_start2 ); 96 | count_start3 <= ( (slv_reg_wren_signal==1 && count_start_slice_idx==3)?count_start:count_start3 ); 97 | 98 | count_end0 <= ( (slv_reg_wren_signal==1 && count_end_slice_idx==0)?count_end:count_end0 ); 99 | count_end1 <= ( (slv_reg_wren_signal==1 && count_end_slice_idx==1)?count_end:count_end1 ); 100 | count_end2 <= ( (slv_reg_wren_signal==1 && count_end_slice_idx==2)?count_end:count_end2 ); 101 | count_end3 <= ( (slv_reg_wren_signal==1 && count_end_slice_idx==3)?count_end:count_end3 ); 102 | 103 | // generate slice enable signal 104 | counter0 <= ( tsf_pulse_1M?( counter0==count_total0? 0 : (counter0 + 1) ):counter0 ); 105 | counter1 <= ( tsf_pulse_1M?( counter1==count_total1? 0 : (counter1 + 1) ):counter1 ); 106 | counter2 <= ( tsf_pulse_1M?( counter2==count_total2? 0 : (counter2 + 1) ):counter2 ); 107 | counter3 <= ( tsf_pulse_1M?( counter3==count_total3? 0 : (counter3 + 1) ):counter3 ); 108 | 109 | slice_en0 <= ( (counter0<=count_end0) && (counter0>=count_start0) ); 110 | slice_en1 <= ( (counter1<=count_end1) && (counter1>=count_start1) ); 111 | slice_en2 <= ( (counter2<=count_end2) && (counter2>=count_start2) ); 112 | slice_en3 <= ( (counter3<=count_end3) && (counter3>=count_start3) ); 113 | end 114 | end 115 | 116 | endmodule 117 | -------------------------------------------------------------------------------- /ip/xpu/src/rssi.v: -------------------------------------------------------------------------------- 1 | // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; 2 | 3 | `timescale 1 ns / 1 ps 4 | 5 | `include "xpu_pre_def.v" 6 | 7 | `ifdef XPU_ENABLE_DBG 8 | `define DEBUG_PREFIX (*mark_debug="true",DONT_TOUCH="TRUE"*) 9 | `else 10 | `define DEBUG_PREFIX 11 | `endif 12 | 13 | module rssi # 14 | ( 15 | parameter integer GPIO_STATUS_WIDTH = 8, 16 | parameter integer DELAY_CTL_WIDTH = 7, 17 | parameter integer RSSI_HALF_DB_WIDTH = 11, 18 | parameter integer IQ_RSSI_HALF_DB_WIDTH = 9, 19 | parameter integer IQ_DATA_WIDTH = 16 20 | ) 21 | ( 22 | // ad9361 status and ctrl 23 | input wire [7:0] gpio_status, 24 | 25 | input wire clk, 26 | input wire rstn, 27 | input wire fifo_delay_rstn, 28 | 29 | input wire pkt_header_valid_strobe, 30 | 31 | input wire [(DELAY_CTL_WIDTH-1):0] delay_ctl, 32 | `DEBUG_PREFIX input wire [(RSSI_HALF_DB_WIDTH-1):0] rssi_half_db_offset, 33 | 34 | // Ports to receive IQ from DDC 35 | input wire signed [(IQ_DATA_WIDTH-1):0] ddc_i, 36 | input wire signed [(IQ_DATA_WIDTH-1):0] ddc_q, 37 | input wire ddc_iq_valid, 38 | 39 | // result outputs 40 | `DEBUG_PREFIX output wire signed [(IQ_RSSI_HALF_DB_WIDTH-1):0] iq_rssi_half_db, 41 | `DEBUG_PREFIX output wire iq_rssi_half_db_valid, 42 | `DEBUG_PREFIX output reg signed [(RSSI_HALF_DB_WIDTH-1):0] rssi_half_db_lock_by_sig_valid, 43 | `DEBUG_PREFIX output reg [(GPIO_STATUS_WIDTH-1):0] gpio_status_lock_by_sig_valid, 44 | `DEBUG_PREFIX output reg signed [(RSSI_HALF_DB_WIDTH-1):0] rssi_half_db, 45 | `DEBUG_PREFIX output reg rssi_half_db_valid, 46 | `DEBUG_PREFIX output wire [(GPIO_STATUS_WIDTH-1):0] gpio_status_delay, 47 | `DEBUG_PREFIX output wire gpio_status_delay_valid 48 | ); 49 | 50 | reg fifo_delay_rstn_delay1; 51 | reg fifo_delay_rstn_delay2; 52 | reg fifo_delay_rstn_delay3; 53 | reg fifo_delay_rstn_delay4; 54 | 55 | wire signed [(IQ_DATA_WIDTH-1):0] iq_rssi; 56 | wire iq_rssi_valid; 57 | 58 | iq_abs_avg # ( 59 | .IQ_DATA_WIDTH(IQ_DATA_WIDTH) 60 | ) iq_abs_avg_i ( 61 | .clk(clk), 62 | .rstn(rstn), 63 | .ddc_i(ddc_i), 64 | .ddc_q(ddc_q), 65 | .ddc_iq_valid(ddc_iq_valid), 66 | .iq_rssi(iq_rssi), 67 | .iq_rssi_valid(iq_rssi_valid) 68 | ); 69 | 70 | iq_rssi_to_db # ( 71 | .IQ_DATA_WIDTH(IQ_DATA_WIDTH), 72 | .IQ_RSSI_HALF_DB_WIDTH(IQ_RSSI_HALF_DB_WIDTH) 73 | ) iq_rssi_to_db_i ( 74 | .clk(clk), 75 | .rstn(rstn), 76 | .iq_rssi(iq_rssi), 77 | .iq_rssi_valid(iq_rssi_valid), 78 | .iq_rssi_half_db(iq_rssi_half_db), // step size is 0.5dB not 1dB! 79 | .iq_rssi_half_db_valid(iq_rssi_half_db_valid) 80 | ); 81 | 82 | fifo_sample_delay # (.DATA_WIDTH(GPIO_STATUS_WIDTH), .LOG2_FIFO_DEPTH(DELAY_CTL_WIDTH)) fifo_sample_delay_i ( 83 | .clk(clk), 84 | .rst(~(fifo_delay_rstn&fifo_delay_rstn_delay1&fifo_delay_rstn_delay2&fifo_delay_rstn_delay3&fifo_delay_rstn_delay4)), 85 | .delay_ctl(delay_ctl), 86 | .data_in(gpio_status), 87 | .data_in_valid(iq_rssi_half_db_valid), 88 | .data_out(gpio_status_delay), 89 | .data_out_valid(gpio_status_delay_valid) 90 | ); 91 | 92 | always @( posedge clk ) 93 | if ( rstn == 1'b0 ) 94 | begin 95 | rssi_half_db <= 0; 96 | rssi_half_db_valid <= 0; 97 | end 98 | else 99 | begin 100 | rssi_half_db_valid <= gpio_status_delay_valid; 101 | if (gpio_status_delay_valid) 102 | begin 103 | rssi_half_db <= (rssi_half_db_offset + iq_rssi_half_db - {3'b0, gpio_status_delay[6:0], 1'b0} ); // temp formula 104 | end 105 | end 106 | 107 | always @( posedge clk ) 108 | if ( rstn == 1'b0 ) 109 | begin 110 | fifo_delay_rstn_delay1 <= fifo_delay_rstn; 111 | fifo_delay_rstn_delay2 <= fifo_delay_rstn; 112 | fifo_delay_rstn_delay3 <= fifo_delay_rstn; 113 | fifo_delay_rstn_delay4 <= fifo_delay_rstn; 114 | 115 | rssi_half_db_lock_by_sig_valid <= 0; 116 | gpio_status_lock_by_sig_valid <= 0; 117 | end 118 | else 119 | begin 120 | fifo_delay_rstn_delay1 <= fifo_delay_rstn; 121 | fifo_delay_rstn_delay2 <= fifo_delay_rstn_delay1; 122 | fifo_delay_rstn_delay3 <= fifo_delay_rstn_delay2; 123 | fifo_delay_rstn_delay4 <= fifo_delay_rstn_delay3; 124 | 125 | if (pkt_header_valid_strobe) 126 | begin 127 | rssi_half_db_lock_by_sig_valid <= rssi_half_db; 128 | gpio_status_lock_by_sig_valid <= gpio_status; 129 | end 130 | end 131 | 132 | endmodule 133 | -------------------------------------------------------------------------------- /ip/openofdm_tx/src/axi_fifo_bram.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright 2012-2014 Ettus Research LLC 3 | // Copyright 2018 Ettus Research, a National Instruments Company 4 | // 5 | // SPDX-License-Identifier: LGPL-3.0-or-later 6 | // 7 | 8 | 9 | 10 | // Block RAM AXI fifo 11 | 12 | 13 | module axi_fifo_bram 14 | #(parameter WIDTH=32, SIZE=9) 15 | (input clk, input reset, input clear, 16 | input [WIDTH-1:0] i_tdata, 17 | input i_tvalid, 18 | output i_tready, 19 | output reg [WIDTH-1:0] o_tdata = 'd0, 20 | output reg o_tvalid = 1'b0, 21 | input o_tready, 22 | 23 | output reg [15:0] space, 24 | output reg [15:0] occupied); 25 | 26 | wire [WIDTH-1:0] int_tdata; 27 | wire int_tready; 28 | 29 | wire full, empty; 30 | wire write = i_tvalid & i_tready; 31 | // read_int will assert when either a read occurs or the output register is empty (and there is data in the shift register fifo) 32 | wire read_int = ~empty & int_tready; 33 | // read will only assert when an actual 1read request occurs at the interface 34 | wire read = o_tready & o_tvalid; 35 | 36 | assign i_tready = ~full; 37 | 38 | // Read side states 39 | localparam ST_EMPTY = 0; 40 | localparam PRE_READ = 1; 41 | localparam READING = 2; 42 | 43 | reg [SIZE-1:0] wr_addr, rd_addr; 44 | reg [1:0] read_state; 45 | 46 | reg empty_reg = 1'b1, full_reg = 1'b0; 47 | always @(posedge clk) 48 | if(reset) 49 | wr_addr <= 0; 50 | else if(clear) 51 | wr_addr <= 0; 52 | else if(write) 53 | wr_addr <= wr_addr + 1; 54 | 55 | dpram #(.DATA_WIDTH(WIDTH),.ADDRESS_WIDTH(SIZE)) 56 | ram ( 57 | .clock(clk), 58 | .reset(reset), 59 | .enable_a(1), 60 | .write_enable(write), 61 | .write_address(wr_addr), 62 | .write_data(i_tdata), 63 | .read_data_a(), 64 | 65 | .enable_b((read_state==PRE_READ)|read_int), 66 | .read_address(rd_addr), 67 | .read_data(int_tdata)); 68 | 69 | always @(posedge clk) 70 | if(reset) 71 | begin 72 | read_state <= ST_EMPTY; 73 | rd_addr <= 0; 74 | empty_reg <= 1; 75 | end 76 | else 77 | if(clear) 78 | begin 79 | read_state <= ST_EMPTY; 80 | rd_addr <= 0; 81 | empty_reg <= 1; 82 | end 83 | else 84 | case(read_state) 85 | ST_EMPTY : 86 | if(write) 87 | begin 88 | //rd_addr <= wr_addr; 89 | read_state <= PRE_READ; 90 | end 91 | PRE_READ : 92 | begin 93 | read_state <= READING; 94 | empty_reg <= 0; 95 | rd_addr <= rd_addr + 1; 96 | end 97 | 98 | READING : 99 | if(read_int) 100 | if(rd_addr == wr_addr) 101 | begin 102 | empty_reg <= 1; 103 | if(write) 104 | read_state <= PRE_READ; 105 | else 106 | read_state <= ST_EMPTY; 107 | end 108 | else 109 | rd_addr <= rd_addr + 1; 110 | endcase // case(read_state) 111 | 112 | wire [SIZE-1:0] dont_write_past_me = rd_addr - 2; 113 | wire becoming_full = wr_addr == dont_write_past_me; 114 | 115 | always @(posedge clk) 116 | if(reset) 117 | full_reg <= 0; 118 | else if(clear) 119 | full_reg <= 0; 120 | else if(read_int & ~write) 121 | full_reg <= 0; 122 | //else if(write & ~read_int & (wr_addr == (rd_addr-3))) 123 | else if(write & ~read_int & becoming_full) 124 | full_reg <= 1; 125 | 126 | //assign empty = (read_state != READING); 127 | assign empty = empty_reg; 128 | 129 | // assign full = ((rd_addr - 1) == wr_addr); 130 | assign full = full_reg; 131 | 132 | // Output registered stage 133 | always @(posedge clk) 134 | begin 135 | // Valid flag 136 | if (reset | clear) 137 | o_tvalid <= 1'b0; 138 | else if (int_tready) 139 | o_tvalid <= ~empty; 140 | 141 | // Data 142 | if (int_tready) 143 | o_tdata <= int_tdata; 144 | end 145 | 146 | assign int_tready = o_tready | ~o_tvalid; 147 | 148 | ////////////////////////////////////////////// 149 | // space and occupied are for diagnostics only 150 | // not guaranteed exact 151 | 152 | localparam NUMLINES = (1< 26 | // 27 | // OR 28 | // 29 | // 2. An ADI specific BSD license, which can be found in the top level directory 30 | // of this repository (LICENSE_ADIBSD), and also on-line at: 31 | // https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD 32 | // This will allow to generate bit files and not release the source code, 33 | // as long as it attaches to an ADI device. 34 | // 35 | // *************************************************************************** 36 | // *************************************************************************** 37 | 38 | `timescale 1ns/100ps 39 | 40 | module system_top ( 41 | 42 | input [12:0] gpio_bd_i, 43 | output [ 7:0] gpio_bd_o, 44 | 45 | output gpio_pmod1_0, 46 | output gpio_pmod1_1, 47 | output gpio_pmod1_2, 48 | 49 | input rx_clk_in_p, 50 | input rx_clk_in_n, 51 | input rx_frame_in_p, 52 | input rx_frame_in_n, 53 | input [ 5:0] rx_data_in_p, 54 | input [ 5:0] rx_data_in_n, 55 | output tx_clk_out_p, 56 | output tx_clk_out_n, 57 | output tx_frame_out_p, 58 | output tx_frame_out_n, 59 | output [ 5:0] tx_data_out_p, 60 | output [ 5:0] tx_data_out_n, 61 | 62 | output enable, 63 | output txnrx, 64 | 65 | output gpio_resetb, 66 | output gpio_sync, 67 | output gpio_en_agc, 68 | output [ 3:0] gpio_ctl, 69 | input [ 7:0] gpio_status, 70 | 71 | output spi_csn, 72 | output spi_clk, 73 | output spi_mosi, 74 | input spi_miso); 75 | 76 | // internal signals 77 | 78 | wire [94:0] gpio_i; 79 | wire [94:0] gpio_o; 80 | wire [ 2:0] spi0_csn; 81 | 82 | // defaults 83 | 84 | assign gpio_resetb = gpio_o[46:46]; 85 | assign gpio_sync = gpio_o[45:45]; 86 | assign gpio_en_agc = gpio_o[44:44]; 87 | assign gpio_ctl = gpio_o[43:40]; 88 | assign gpio_bd_o = gpio_o[20:13]; 89 | 90 | assign gpio_i[94:40] = gpio_o[94:40]; 91 | assign gpio_i[39:32] = gpio_status; 92 | assign gpio_i[31:13] = gpio_o[31:13]; 93 | assign gpio_i[12: 0] = gpio_bd_i; 94 | 95 | assign spi_csn = spi0_csn[0]; 96 | 97 | // instantiations 98 | 99 | system_wrapper i_system_wrapper ( 100 | .enable (enable), 101 | .gpio_i (gpio_i), 102 | .gpio_o (gpio_o), 103 | .gpio_t (), 104 | .gpio_pmod1_0(gpio_pmod1_0), 105 | .gpio_pmod1_1(gpio_pmod1_1), 106 | .gpio_pmod1_2(gpio_pmod1_2), 107 | .rx_clk_in_n (rx_clk_in_n), 108 | .rx_clk_in_p (rx_clk_in_p), 109 | .rx_data_in_n (rx_data_in_n), 110 | .rx_data_in_p (rx_data_in_p), 111 | .rx_frame_in_n (rx_frame_in_n), 112 | .rx_frame_in_p (rx_frame_in_p), 113 | .spi0_csn (spi0_csn), 114 | .spi0_miso (spi_miso), 115 | .spi0_mosi (spi_mosi), 116 | .spi0_sclk (spi_clk), 117 | .spi1_csn (), 118 | .spi1_miso (1'b0), 119 | .spi1_mosi (), 120 | .spi1_sclk (), 121 | .tdd_sync_i (1'b0), 122 | .tdd_sync_o (), 123 | .tdd_sync_t (), 124 | .tx_clk_out_n (tx_clk_out_n), 125 | .tx_clk_out_p (tx_clk_out_p), 126 | .tx_data_out_n (tx_data_out_n), 127 | .tx_data_out_p (tx_data_out_p), 128 | .tx_frame_out_n (tx_frame_out_n), 129 | .tx_frame_out_p (tx_frame_out_p), 130 | .txnrx (txnrx), 131 | .up_enable (gpio_o[47]), 132 | .up_txnrx (gpio_o[48])); 133 | 134 | endmodule 135 | 136 | // *************************************************************************** 137 | // *************************************************************************** 138 | -------------------------------------------------------------------------------- /ip/openofdm_tx/src/modulation.v: -------------------------------------------------------------------------------- 1 | /* 2 | * modulation - TODO 3 | * 4 | * Michael Tetemke Mehari michael.mehari@ugent.be 5 | * Xianjun Jiao xianjun.jiao@imec.be putaoshu@msn.com 6 | */ 7 | `include "openofdm_tx_pre_def.v" 8 | 9 | module modulation 10 | ( 11 | input wire [2:0] N_BPSC, 12 | input wire [5:0] bits_in, 13 | output reg [31:0] IQ 14 | ); 15 | 16 | // combinatorial logic 17 | always @* begin 18 | IQ = {16'h0000, 16'h0000}; 19 | // BPSK 20 | if(N_BPSC == 1) begin 21 | case(bits_in[0]) 22 | 1'b0: IQ = {16'hC000, 16'h0000}; 23 | 24 | 1'b1: IQ = {16'h4000, 16'h0000}; 25 | endcase 26 | 27 | // QPSK 28 | end else if(N_BPSC == 2) begin 29 | case(bits_in[1:0]) 30 | 2'b00: IQ = {16'hD2BF, 16'hD2BF}; 31 | 2'b10: IQ = {16'hD2BF, 16'h2D41}; 32 | 33 | 2'b01: IQ = {16'h2D41, 16'hD2BF}; 34 | 2'b11: IQ = {16'h2D41, 16'h2D41}; 35 | endcase 36 | 37 | // 16 QAM 38 | end else if(N_BPSC == 4) begin 39 | case(bits_in[3:0]) 40 | 4'b0000: IQ = {16'hC349, 16'hC349}; 41 | 4'b1000: IQ = {16'hC349, 16'hEBC3}; 42 | 4'b1100: IQ = {16'hC349, 16'h143D}; 43 | 4'b0100: IQ = {16'hC349, 16'h3CB7}; 44 | 45 | 4'b0010: IQ = {16'hEBC3, 16'hC349}; 46 | 4'b1010: IQ = {16'hEBC3, 16'hEBC3}; 47 | 4'b1110: IQ = {16'hEBC3, 16'h143D}; 48 | 4'b0110: IQ = {16'hEBC3, 16'h3CB7}; 49 | 50 | 4'b0011: IQ = {16'h143D, 16'hC349}; 51 | 4'b1011: IQ = {16'h143D, 16'hEBC3}; 52 | 4'b1111: IQ = {16'h143D, 16'h143D}; 53 | 4'b0111: IQ = {16'h143D, 16'h3CB7}; 54 | 55 | 4'b0001: IQ = {16'h3CB7, 16'hC349}; 56 | 4'b1001: IQ = {16'h3CB7, 16'hEBC3}; 57 | 4'b1101: IQ = {16'h3CB7, 16'h143D}; 58 | 4'b0101: IQ = {16'h3CB7, 16'h3CB7}; 59 | endcase 60 | 61 | // 64 QAM 62 | end else if(N_BPSC == 6) begin 63 | case(bits_in[5:0]) 64 | 6'b000000: IQ = {16'hBAE0, 16'hBAE0}; 65 | 6'b100000: IQ = {16'hBAE0, 16'hCEA0}; 66 | 6'b110000: IQ = {16'hBAE0, 16'hE260}; 67 | 6'b010000: IQ = {16'hBAE0, 16'hF620}; 68 | 6'b011000: IQ = {16'hBAE0, 16'h09E0}; 69 | 6'b111000: IQ = {16'hBAE0, 16'h1DA0}; 70 | 6'b101000: IQ = {16'hBAE0, 16'h3160}; 71 | 6'b001000: IQ = {16'hBAE0, 16'h4520}; 72 | 73 | 6'b000100: IQ = {16'hCEA0, 16'hBAE0}; 74 | 6'b100100: IQ = {16'hCEA0, 16'hCEA0}; 75 | 6'b110100: IQ = {16'hCEA0, 16'hE260}; 76 | 6'b010100: IQ = {16'hCEA0, 16'hF620}; 77 | 6'b011100: IQ = {16'hCEA0, 16'h09E0}; 78 | 6'b111100: IQ = {16'hCEA0, 16'h1DA0}; 79 | 6'b101100: IQ = {16'hCEA0, 16'h3160}; 80 | 6'b001100: IQ = {16'hCEA0, 16'h4520}; 81 | 82 | 6'b000110: IQ = {16'hE260, 16'hBAE0}; 83 | 6'b100110: IQ = {16'hE260, 16'hCEA0}; 84 | 6'b110110: IQ = {16'hE260, 16'hE260}; 85 | 6'b010110: IQ = {16'hE260, 16'hF620}; 86 | 6'b011110: IQ = {16'hE260, 16'h09E0}; 87 | 6'b111110: IQ = {16'hE260, 16'h1DA0}; 88 | 6'b101110: IQ = {16'hE260, 16'h3160}; 89 | 6'b001110: IQ = {16'hE260, 16'h4520}; 90 | 91 | 6'b000010: IQ = {16'hF620, 16'hBAE0}; 92 | 6'b100010: IQ = {16'hF620, 16'hCEA0}; 93 | 6'b110010: IQ = {16'hF620, 16'hE260}; 94 | 6'b010010: IQ = {16'hF620, 16'hF620}; 95 | 6'b011010: IQ = {16'hF620, 16'h09E0}; 96 | 6'b111010: IQ = {16'hF620, 16'h1DA0}; 97 | 6'b101010: IQ = {16'hF620, 16'h3160}; 98 | 6'b001010: IQ = {16'hF620, 16'h4520}; 99 | 100 | 6'b000011: IQ = {16'h09E0, 16'hBAE0}; 101 | 6'b100011: IQ = {16'h09E0, 16'hCEA0}; 102 | 6'b110011: IQ = {16'h09E0, 16'hE260}; 103 | 6'b010011: IQ = {16'h09E0, 16'hF620}; 104 | 6'b011011: IQ = {16'h09E0, 16'h09E0}; 105 | 6'b111011: IQ = {16'h09E0, 16'h1DA0}; 106 | 6'b101011: IQ = {16'h09E0, 16'h3160}; 107 | 6'b001011: IQ = {16'h09E0, 16'h4520}; 108 | 109 | 6'b000111: IQ = {16'h1DA0, 16'hBAE0}; 110 | 6'b100111: IQ = {16'h1DA0, 16'hCEA0}; 111 | 6'b110111: IQ = {16'h1DA0, 16'hE260}; 112 | 6'b010111: IQ = {16'h1DA0, 16'hF620}; 113 | 6'b011111: IQ = {16'h1DA0, 16'h09E0}; 114 | 6'b111111: IQ = {16'h1DA0, 16'h1DA0}; 115 | 6'b101111: IQ = {16'h1DA0, 16'h3160}; 116 | 6'b001111: IQ = {16'h1DA0, 16'h4520}; 117 | 118 | 6'b000101: IQ = {16'h3160, 16'hBAE0}; 119 | 6'b100101: IQ = {16'h3160, 16'hCEA0}; 120 | 6'b110101: IQ = {16'h3160, 16'hE260}; 121 | 6'b010101: IQ = {16'h3160, 16'hF620}; 122 | 6'b011101: IQ = {16'h3160, 16'h09E0}; 123 | 6'b111101: IQ = {16'h3160, 16'h1DA0}; 124 | 6'b101101: IQ = {16'h3160, 16'h3160}; 125 | 6'b001101: IQ = {16'h3160, 16'h4520}; 126 | 127 | 6'b000001: IQ = {16'h4520, 16'hBAE0}; 128 | 6'b100001: IQ = {16'h4520, 16'hCEA0}; 129 | 6'b110001: IQ = {16'h4520, 16'hE260}; 130 | 6'b010001: IQ = {16'h4520, 16'hF620}; 131 | 6'b011001: IQ = {16'h4520, 16'h09E0}; 132 | 6'b111001: IQ = {16'h4520, 16'h1DA0}; 133 | 6'b101001: IQ = {16'h4520, 16'h3160}; 134 | 6'b001001: IQ = {16'h4520, 16'h4520}; 135 | endcase 136 | end 137 | end 138 | endmodule 139 | -------------------------------------------------------------------------------- /ip/openofdm_tx/src/convround.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: convround.v 4 | // 5 | // Project: A General Purpose Pipelined FFT Implementation 6 | // 7 | // Purpose: A convergent rounding routine, also known as banker's 8 | // rounding, Dutch rounding, Gaussian rounding, unbiased 9 | // rounding, or ... more, at least according to Wikipedia. 10 | // 11 | // This form of rounding works by rounding, when the direction is in 12 | // question, towards the nearest even value. 13 | // 14 | // 15 | // Creator: Dan Gisselquist, Ph.D. 16 | // Gisselquist Technology, LLC 17 | // 18 | //////////////////////////////////////////////////////////////////////////////// 19 | // 20 | // Copyright (C) 2015-2019, Gisselquist Technology, LLC 21 | // 22 | // This file is part of the general purpose pipelined FFT project. 23 | // 24 | // The pipelined FFT project is free software (firmware): you can redistribute 25 | // it and/or modify it under the terms of the GNU Lesser General Public License 26 | // as published by the Free Software Foundation, either version 3 of the 27 | // License, or (at your option) any later version. 28 | // 29 | // The pipelined FFT project is distributed in the hope that it will be useful, 30 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | // MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser 32 | // General Public License for more details. 33 | // 34 | // You should have received a copy of the GNU Lesser General Public License 35 | // along with this program. (It's in the $(ROOT)/doc directory. Run make 36 | // with no target there if the PDF file isn't present.) If not, see 37 | // for a copy. 38 | // 39 | // License: LGPL, v3, as defined and found on www.gnu.org, 40 | // http://www.gnu.org/licenses/lgpl.html 41 | // 42 | // 43 | //////////////////////////////////////////////////////////////////////////////// 44 | // 45 | // 46 | //`default_nettype none 47 | // 48 | module convround(i_clk, i_ce, i_val, o_val); 49 | parameter IWID=16, OWID=8, SHIFT=0; 50 | input wire i_clk, i_ce; 51 | input wire signed [(IWID-1):0] i_val; 52 | output reg signed [(OWID-1):0] o_val; 53 | 54 | // Let's deal with three cases to be as general as we can be here 55 | // 56 | // 1. The desired output would lose no bits at all 57 | // 2. One bit would be dropped, so the rounding is simply 58 | // adjusting the value to be the nearest even number in 59 | // cases of being halfway between two. If identically 60 | // equal to a number, we just leave it as is. 61 | // 3. Two or more bits would be dropped. In this case, we round 62 | // normally unless we are rounding a value of exactly 63 | // halfway between the two. In the halfway case we round 64 | // to the nearest even number. 65 | generate 66 | if (IWID == OWID) // In this case, the shift is irrelevant and 67 | begin // cannot be applied. No truncation or rounding takes 68 | // effect here. 69 | 70 | always @(posedge i_clk) 71 | if (i_ce) o_val <= i_val[(IWID-1):0]; 72 | 73 | end else if (IWID-SHIFT < OWID) 74 | begin // No truncation or rounding, output drops no bits 75 | // Instead, we need to stuff the bits in the output 76 | 77 | always @(posedge i_clk) 78 | if (i_ce) o_val <= { {(OWID-IWID+SHIFT){i_val[IWID-SHIFT-1]}}, i_val[(IWID-SHIFT-1):0] }; 79 | 80 | end else if (IWID-SHIFT == OWID) 81 | begin // No truncation or rounding, output drops no bits 82 | 83 | always @(posedge i_clk) 84 | if (i_ce) o_val <= i_val[(IWID-SHIFT-1):0]; 85 | 86 | end else if (IWID-SHIFT-1 == OWID) 87 | begin // Output drops one bit, can only add one or ... not. 88 | wire [(OWID-1):0] truncated_value, rounded_up; 89 | wire last_valid_bit, first_lost_bit; 90 | assign truncated_value=i_val[(IWID-1-SHIFT):(IWID-SHIFT-OWID)]; 91 | assign rounded_up=truncated_value + {{(OWID-1){1'b0}}, 1'b1 }; 92 | assign last_valid_bit = truncated_value[0]; 93 | assign first_lost_bit = i_val[0]; 94 | 95 | always @(posedge i_clk) 96 | if (i_ce) 97 | begin 98 | if (!first_lost_bit) // Round down / truncate 99 | o_val <= truncated_value; 100 | else if (last_valid_bit)// Round up to nearest 101 | o_val <= rounded_up; // even value 102 | else // else round down to the nearest 103 | o_val <= truncated_value; // even value 104 | end 105 | 106 | end else // If there's more than one bit we are dropping 107 | begin 108 | wire [(OWID-1):0] truncated_value, rounded_up; 109 | wire last_valid_bit, first_lost_bit; 110 | 111 | assign truncated_value=i_val[(IWID-1-SHIFT):(IWID-SHIFT-OWID)]; 112 | assign rounded_up=truncated_value + {{(OWID-1){1'b0}}, 1'b1 }; 113 | assign last_valid_bit = truncated_value[0]; 114 | assign first_lost_bit = i_val[(IWID-SHIFT-OWID-1)]; 115 | 116 | wire [(IWID-SHIFT-OWID-2):0] other_lost_bits; 117 | assign other_lost_bits = i_val[(IWID-SHIFT-OWID-2):0]; 118 | 119 | always @(posedge i_clk) 120 | if (i_ce) 121 | begin 122 | if (!first_lost_bit) // Round down / truncate 123 | o_val <= truncated_value; 124 | else if (|other_lost_bits) // Round up to 125 | o_val <= rounded_up; // closest value 126 | else if (last_valid_bit) // Round up to 127 | o_val <= rounded_up; // nearest even 128 | else // else round down to nearest even 129 | o_val <= truncated_value; 130 | end 131 | end 132 | endgenerate 133 | 134 | endmodule 135 | -------------------------------------------------------------------------------- /boards/neptunesdr/src/neptunesdr_constr_lvds.xdc: -------------------------------------------------------------------------------- 1 | 2 | # constraints (pzsdr1.b) 3 | # ad9361 4 | 5 | set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## IO_L12P_T1_MRCC_35 U1,K17,IO_L12_MRCC_35_DATA_CLK_P 6 | set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## IO_L12N_T1_MRCC_35 U1,K18,IO_L12_MRCC_35_DATA_CLK_N 7 | set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## IO_L7P_T1_AD2P_35 U1,M19,IO_L07_35_RX_FRAME_P 8 | set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## IO_L7N_T1_AD2N_35 U1,M20,IO_L07_35_RX_FRAME_N 9 | set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## IO_L1P_T0_AD0P_35 U1,C20,IO_L01_35_RX_D0_P 10 | set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## IO_L1N_T0_AD0N_35 U1,B20,IO_L01_35_RX_D0_N 11 | set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## IO_L2P_T0_AD8P_35 U1,B19,IO_L02_35_RX_D1_P 12 | set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## IO_L2N_T0_AD8N_35 U1,A20,IO_L02_35_RX_D1_N 13 | set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## IO_L3P_T0_DQS_AD1P_35 U1,E17,IO_L03_35_RX_D2_P 14 | set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## IO_L3N_T0_DQS_AD1N_35 U1,D18,IO_L03_35_RX_D2_N 15 | set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## IO_L4P_T0_35 U1,D19,IO_L04_35_RX_D3_P 16 | set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## IO_L4N_T0_35 U1,D20,IO_L04_35_RX_D3_N 17 | set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## IO_L5P_T0_AD9P_35 U1,E18,IO_L05_35_RX_D4_P 18 | set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## IO_L5N_T0_AD9N_35 U1,E19,IO_L05_35_RX_D4_N 19 | set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## IO_L6P_T0_35 U1,F16,IO_L06_35_RX_D5_P 20 | set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## IO_L6N_T0_VREF_35 U1,F17,IO_L06_35_RX_D5_N 21 | set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## IO_L8P_T1_AD10P_35 U1,M17,IO_L08_35_FB_CLK_P 22 | set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## IO_L8N_T1_AD10N_35 U1,M18,IO_L08_35_FB_CLK_N 23 | set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## IO_L9P_T1_DQS_AD3P_35 U1,L19,IO_L09_35_TX_FRAME_P 24 | set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## IO_L9N_T1_DQS_AD3N_35 U1,L20,IO_L09_35_TX_FRAME_N 25 | set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## IO_L13P_T2_MRCC_35 U1,H16,IO_L13_35_TX_D0_P 26 | set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## IO_L13N_T2_MRCC_35 U1,H17,IO_L13_35_TX_D0_N 27 | set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## IO_L14P_T2_AD4P_SRCC_35 U1,J18,IO_L14_35_TX_D1_P 28 | set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## IO_L14N_T2_AD4N_SRCC_35 U1,H18,IO_L14_35_TX_D1_N 29 | set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## IO_L15P_T2_DQS_AD12P_35 U1,F19,IO_L15_35_TX_D2_P 30 | set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## IO_L15N_T2_DQS_AD12N_35 U1,F20,IO_L15_35_TX_D2_N 31 | set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## IO_L16P_T2_35 U1,G17,IO_L16_35_TX_D3_P 32 | set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## IO_L16N_T2_35 U1,G18,IO_L16_35_TX_D3_N 33 | set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## IO_L17P_T2_AD5P_35 U1,J20,IO_L17_35_TX_D4_P 34 | set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## IO_L17N_T2_AD5N_35 U1,H20,IO_L17_35_TX_D4_N 35 | set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## IO_L18P_T2_AD13P_35 U1,G19,IO_L18_35_TX_D5_P 36 | set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35 U1,G20,IO_L18_35_TX_D5_N 37 | 38 | # clocks 39 | 40 | create_clock -name rx_clk -period 8 [get_ports rx_clk_in_p] 41 | 42 | -------------------------------------------------------------------------------- /ip/openofdm_tx/src/bitreverse.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: bitreverse.v 4 | // 5 | // Project: A General Purpose Pipelined FFT Implementation 6 | // 7 | // Purpose: This module bitreverses a pipelined FFT input. It differes 8 | // from the dblreverse module in that this is just a simple and 9 | // straightforward bitreverse, rather than one written to handle two 10 | // words at once. 11 | // 12 | // 13 | // Creator: Dan Gisselquist, Ph.D. 14 | // Gisselquist Technology, LLC 15 | // 16 | //////////////////////////////////////////////////////////////////////////////// 17 | // 18 | // Copyright (C) 2015-2019, Gisselquist Technology, LLC 19 | // 20 | // This file is part of the general purpose pipelined FFT project. 21 | // 22 | // The pipelined FFT project is free software (firmware): you can redistribute 23 | // it and/or modify it under the terms of the GNU Lesser General Public License 24 | // as published by the Free Software Foundation, either version 3 of the 25 | // License, or (at your option) any later version. 26 | // 27 | // The pipelined FFT project is distributed in the hope that it will be useful, 28 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | // MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser 30 | // General Public License for more details. 31 | // 32 | // You should have received a copy of the GNU Lesser General Public License 33 | // along with this program. (It's in the $(ROOT)/doc directory. Run make 34 | // with no target there if the PDF file isn't present.) If not, see 35 | // for a copy. 36 | // 37 | // License: LGPL, v3, as defined and found on www.gnu.org, 38 | // http://www.gnu.org/licenses/lgpl.html 39 | // 40 | // 41 | //////////////////////////////////////////////////////////////////////////////// 42 | // 43 | // 44 | //`default_nettype none 45 | // 46 | module bitreverse(i_clk, i_reset, i_ce, i_in, o_out, o_sync); 47 | parameter LGSIZE=5, WIDTH=24; 48 | input wire i_clk, i_reset, i_ce; 49 | input wire [(2*WIDTH-1):0] i_in; 50 | output reg [(2*WIDTH-1):0] o_out; 51 | output reg o_sync; 52 | reg [(LGSIZE):0] wraddr; 53 | wire [(LGSIZE):0] rdaddr; 54 | 55 | reg [(2*WIDTH-1):0] brmem [0:((1<<(LGSIZE+1))-1)]; 56 | 57 | genvar k; 58 | generate for(k=0; k