├── LICENSE ├── README.md └── source └── mmio.d /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. By contrast, 15 | the GNU General Public License is intended to guarantee your freedom to 16 | share and change all versions of a program--to make sure it remains free 17 | software for all its users. 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It is currently quite specific to the STM32 ARM Cortex-M4 microcontroller, but it would be nice if it could be made more general purpose. 4 | 5 | The design of this library was originally influenced by a paper written by Ken Smith titled "[C++ Hardware Register Access Redux](http://yogiken.files.wordpress.com/2010/02/c-register-access.pdf)". It was then modified to take advantage of some unique features of the D programming language. 6 | 7 | To date, this library has only been used with the [GDC compiler](https://github.com/D-Programming-GDC/GDC). 8 | 9 | Goals 10 | --------- 11 | * Reduce code size and increase performance by utilizing the D programming language's Compile-Time Function Execution (CTFE) feature reducing register access to as few instructions as possible. 12 | * Provide a strong correlation between code and datasheet to make authoring code from the datasheet and verifying code against the datasheet convenient and less error-prone. 13 | * Provide convenient and efficient access to registers and bitfileds with object-oriented syntax. 14 | * Together with tooling, such as code completion (see [DCD](https://github.com/Hackerpilot/DCD)), provide context-sensitive information to the programmer to reduce the frequency with which he/she has to refer to the datasheet. 15 | 16 | Features 17 | -------- 18 | * Enforces word, half-word, and byte access policy at compile time. See `Access` enum. 19 | * Enforces mutability constraints such as read, write, readwrite, etc... at compile time. See `Mutability` enum. 20 | * Optimizes byte-aligned and half-word aligned bitfields generating atomic read/write operations resulting in smaller code size and faster performance. 21 | * Optimizes bitfieds of a single bit, via bit-banding, generating atomic read/write operations resulting in smaller code size and faster performance. 22 | * Can combine multiple bitfield accesses within a single register into one read-modify-write operation resulting in smaller code size and faster performance. 23 | * Enables intuitive and obvious register modeling that directly cross-references back to register specifications in the datasheet. 24 | 25 | Licensing 26 | --------- 27 | See the LICENSE file for licensing information. 28 | 29 | -------------------------------------------------------------------------------- /source/mmio.d: -------------------------------------------------------------------------------- 1 | // Copyright © 2017 Michael V. Franklin 2 | // 3 | // This program is free software: you can redistribute it and/or modify 4 | // it under the terms of the GNU General Public License as published by 5 | // the Free Software Foundation, either version 3 of the License, or 6 | // (at your option) any later version. 7 | // 8 | // This program is distributed in the hope that it will be useful, 9 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | // GNU General Public License for more details. 12 | // 13 | // You should have received a copy of the GNU General Public License 14 | // along with this program. If not, see . 15 | 16 | /*************************************************************************** 17 | Implementation of memory-mapped I/O registers in D. The idea for this 18 | came from a paper by Ken Smith titled "C++ Hardware Register Access Redux". 19 | At the time of this writing, a link to the could be found here: 20 | http://yogiken.files.wordpress.com/2010/02/c-register-access.pdf 21 | 22 | The idea, is that all of this logic will actually be evaluated at compile 23 | time and each BitField access will only cost a few instructions of assembly. 24 | 25 | Right now, this will probably only work for 32-bit platforms. I'd like to 26 | modify this so it is portable to even 16, and 8 bit platforms, but one step 27 | at a time. 28 | 29 | * It enforces word, half-word, and byte access policy at compile time. 30 | See Access. 31 | * It enforces mutability constraints such as read, write, readwrite, etc... 32 | at compile time. See Mutability. 33 | * It optimizes byte-aligned and half-word aligned bitfields generating atomic 34 | read/write operations resulting in smaller code size and faster performance. 35 | * It optimizes bitfieds of a single bit, via bit-banding, generating atomic 36 | read/write operations resulting in smaller code size and faster performance. 37 | * It can combine multiple bitfield accesses within a single register into one 38 | read-modify-write operation resulting in smaller code size and faster 39 | performance. 40 | * It enables intuitive and obvious register modeling that directly cross-references 41 | back to register specifications. 42 | 43 | Example: 44 | -------------------- 45 | // A peripherals's register specification can be modeled as follows 46 | // TODO: make a more meaningful example 47 | final abstract class MyPeripheral : Peripheral!(0x2000_1000) 48 | { 49 | final abstract class MyRegister0 : Register!(0x0000, Access.Word) 50 | { 51 | alias EntireRegister = BitField!(31, 0, Mutability.rw); 52 | alias Bits31To17 = BitField!(17, 2, Mutability.rw); 53 | alias Bits15to8 = BitField!(15, 8, Mutability.rw); 54 | alias Bits1to0 = BitField!( 1, 0, Mutability.rw); 55 | alias Bit1 = Bit!(1, Mutability.rw); 56 | alias Bit0 = Bit!(0, Mutability.rw); 57 | } 58 | 59 | final abstract class MyRegister1 : Register!(0x0004, Access.Word) 60 | { 61 | alias EntireRegister = BitField!(31, 0, Mutability.rw); 62 | alias Bits31To17 = BitField!(17, 2, Mutability.rw); 63 | alias Bits15to8 = BitField!(15, 8, Mutability.rw); 64 | alias Bits1to0 = BitField!( 1, 0, Mutability.rw); 65 | alias Bit1 = Bit!(1, Mutability.rw); 66 | alias Bit0 = Bit!(0, Mutability.rw); 67 | } 68 | } 69 | -------------------- 70 | */ 71 | module mmio; 72 | 73 | import gcc.attribute; 74 | 75 | private alias Address = uint; 76 | private alias BitIndex = uint; 77 | private alias HalfWord = ushort; 78 | private alias Word = uint; 79 | 80 | // These are the bit band address that can be translated to bit-band addresses 81 | // that can address a single bit 82 | private immutable Address PeripheralRegionStart = 0x4000_0000u; 83 | private immutable size_t PeripheralRegionSize = 0x000F_FFFFu; 84 | private immutable Address PeripheralRegionEnd = PeripheralRegionStart + PeripheralRegionSize - 1; 85 | private immutable Address PeripheralBitBandRegionStart = 0x4200_0000u; 86 | 87 | private immutable Address SRAMRegionStart = 0x2000_0000u; 88 | private immutable size_t SRAMRegionSize = 0x000F_FFFFu; 89 | private immutable Address SRAMRegionEnd = SRAMRegionStart + SRAMRegionSize - 1; 90 | private immutable Address SRAMBitBandRegionStart = 0x2200_0000u; 91 | 92 | /**************************************************************************** 93 | Template wrapping volatileLoad intrinsic casting to basic type based on 94 | size. 95 | */ 96 | private T volatileLoad(T)(T* a) @trusted nothrow 97 | { 98 | static import core.bitop; 99 | static if (T.sizeof == 1) 100 | { 101 | return cast(T)core.bitop.volatileLoad(cast(ubyte*)a); 102 | } 103 | else static if (T.sizeof == 2) 104 | { 105 | return cast(T)core.bitop.volatileLoad(cast(ushort*)a); 106 | } 107 | else static if (T.sizeof == 4) 108 | { 109 | return cast(T)core.bitop.volatileLoad(cast(uint*)a); 110 | } 111 | else 112 | { 113 | static assert(false, "Size not supported."); 114 | } 115 | } 116 | 117 | /**************************************************************************** 118 | Template wrapping volatileStore intrinsic casting to basic type based on 119 | size. 120 | */ 121 | private void volatileStore(T)(T* a, in T v) @trusted nothrow 122 | { 123 | static import core.bitop; 124 | static if (T.sizeof == 1) 125 | { 126 | core.bitop.volatileStore(cast(ubyte*)a, cast(ubyte)v); 127 | } 128 | else static if (T.sizeof == 2) 129 | { 130 | core.bitop.volatileStore(cast(ushort*)a, cast(ushort)v); 131 | } 132 | else static if (T.sizeof == 4) 133 | { 134 | core.bitop.volatileStore(cast(uint*)a, cast(uint)v); 135 | } 136 | else 137 | { 138 | static assert(false, "Size not supported."); 139 | } 140 | } 141 | 142 | /**************************************************************************** 143 | Defines the width of access to the fields of a register. For example, some 144 | registers can only be accessed by 32-bit words. 145 | */ 146 | enum Access 147 | { 148 | /**************************************************************************** 149 | Register can only be accessed as a 32-bit word 150 | */ 151 | Word = 4, 152 | 153 | /**************************************************************************** 154 | Register can be accessed as individual bytes or 32-bit words 155 | */ 156 | Byte_Word = 1 | Word, 157 | 158 | /**************************************************************************** 159 | Register can be accessed as 16-bit halfwords or 32-bit words 160 | */ 161 | HalfWord_Word = 2 | Word, 162 | 163 | /**************************************************************************** 164 | Register can be accessed as individual bytes, 16-bit halfwords, or 32-Bit 165 | words 166 | */ 167 | Byte_HalfWord_Word = 1 | 2 | Word 168 | } 169 | 170 | /**************************************************************************** 171 | Mutability (Read/Write policy) as specified in the datasheet 172 | see pp. 57 of the STM32 reference manual 173 | */ 174 | enum Mutability 175 | { 176 | /**************************************************************************** 177 | Software can read and write to these bits. 178 | */ 179 | rw, 180 | 181 | /**************************************************************************** 182 | Software can only read these bits 183 | */ 184 | r, 185 | 186 | /**************************************************************************** 187 | Software can only write to this bit. Reading the bit returns the reset 188 | value. 189 | */ 190 | w, 191 | 192 | /**************************************************************************** 193 | Software can read as well as clear this bit by writing 1. Writing '0' has 194 | no effect on the bit value. 195 | */ 196 | rc_w1, 197 | 198 | /**************************************************************************** 199 | Software can read as well as clear this bit by writing 0. Writing '1' has 200 | no effect on the bit value. 201 | */ 202 | rc_w0, 203 | 204 | /**************************************************************************** 205 | Software can read this bit. Reading this bit automatically clears it to '0'. 206 | Writing '0' has no effect on the bit value 207 | */ 208 | rc_r, 209 | 210 | /**************************************************************************** 211 | Software can read as well as set this bit. Writing '0' has no effect on the 212 | bit value. 213 | */ 214 | rs, 215 | 216 | /**************************************************************************** 217 | Software can read this bit. Writing '0' or '1' triggers an event but has no 218 | effect on the bit value. 219 | */ 220 | rt_w 221 | } 222 | 223 | /**************************************************************************** 224 | Defines how the bitfield is aligned within a register 225 | */ 226 | private enum Alignment 227 | { 228 | /**************************************************************************** 229 | Bitfield is not aligned on any bondary 230 | */ 231 | None = 0, 232 | 233 | /**************************************************************************** 234 | Bitfield is aligned on an 8-bit byte boundary 235 | */ 236 | Byte = 1, 237 | 238 | /**************************************************************************** 239 | Bitfield is aligned on a 16-bit boundary 240 | */ 241 | HalfWord = 2 242 | } 243 | 244 | /*********************************************************************** 245 | Whether or not the mutability policy allows for reading the bit/ 246 | bitfield's value 247 | */ 248 | static auto canRead(immutable Mutability m) @safe pure nothrow 249 | { 250 | return m == Mutability.r || m == Mutability.rw 251 | || m == Mutability.rt_w || m == Mutability.rs 252 | || m == Mutability.rc_r || m == Mutability.rc_w0 253 | || m == Mutability.rc_w1; 254 | } 255 | 256 | /*********************************************************************** 257 | Whether or not the mutability policy allows for writing the bit/ 258 | bitfield's value 259 | */ 260 | static auto canWrite(immutable Mutability m) @safe pure nothrow 261 | { 262 | return m == Mutability.w || m == Mutability.rw 263 | || m == Mutability.rc_w0 || m == Mutability.rc_w1 264 | || m == Mutability.rs; 265 | } 266 | 267 | /*********************************************************************** 268 | Whether or not the mutability policy allows for only setting or 269 | clearing a bit 270 | */ 271 | static auto canOnlySetOrClear(immutable Mutability m) @safe pure nothrow 272 | { 273 | return m == Mutability.rc_w0 || m == Mutability.rc_w1 274 | || m == Mutability.rs; 275 | } 276 | 277 | /*********************************************************************** 278 | Whether or not the mutability policy applies only to single bits 279 | */ 280 | static auto isForBitsOnly(immutable Mutability m) @safe pure nothrow 281 | { 282 | return m == Mutability.rc_w0 || m == Mutability.rc_w1 283 | || m == Mutability.rs || m == Mutability.rc_r 284 | || m == Mutability.rt_w; 285 | } 286 | 287 | /*********************************************************************** 288 | Provides information about a bit field given the specified bit indices 289 | */ 290 | mixin template BitFieldDimensions(BitIndex bitIndex0, BitIndex bitIndex1) 291 | { 292 | /*************************************************************** 293 | Index of this BitField's most significant Bit 294 | */ 295 | static immutable auto mostSignificantBitIndex = bitIndex0 >= bitIndex1 ? bitIndex0 : bitIndex1; 296 | 297 | /*********************************************************************** 298 | Index of this BitField's least significant Bit 299 | */ 300 | static immutable auto leastSignificantBitIndex = bitIndex0 <= bitIndex1 ? bitIndex0 : bitIndex1; 301 | 302 | /*********************************************************************** 303 | Total number of bits in this BitField 304 | */ 305 | static immutable auto numberOfBits = mostSignificantBitIndex - leastSignificantBitIndex + 1; 306 | 307 | /*************************************************************** 308 | Determines if bitIndex is a valid index for this register 309 | 310 | Returns: true if the bitIndex is valid, false if not 311 | */ 312 | private static auto isValidBitIndex(immutable BitIndex bitIndex) @safe pure nothrow 313 | { 314 | return bitIndex >= 0 && bitIndex < (Word.sizeof * 8); 315 | } 316 | 317 | /*********************************************************************** 318 | Gets a bit-mask for this bit field for masking just this BitField out 319 | of the register. 320 | */ 321 | private static immutable auto bitMask = numberOfBits >= 32 322 | ? uint.max // if numberOfBits >=32, the left shift below will fail to compile 323 | : ((1 << numberOfBits) - 1) << leastSignificantBitIndex; 324 | 325 | /*********************************************************************** 326 | Takes a value and moves its bits to align with this bitfields position 327 | in the register. 328 | */ 329 | private static Word maskValue(T)(T value) @safe pure nothrow 330 | { 331 | return (value << leastSignificantBitIndex) & bitMask; 332 | } 333 | 334 | /*********************************************************************** 335 | Whether or not this bitfield is aligned to an even multiple of bytes 336 | */ 337 | private static Alignment alignment() @property @safe pure nothrow 338 | { 339 | // If half-word aligned 340 | static if (((mostSignificantBitIndex + 1) % 16) == 0 && (leastSignificantBitIndex % 16) == 0) 341 | { 342 | return Alignment.HalfWord; 343 | } 344 | // If byte aligned 345 | else if (((mostSignificantBitIndex + 1) % 8) == 0 && (leastSignificantBitIndex % 8) == 0) 346 | { 347 | return Alignment.Byte; 348 | } 349 | // if not aligned 350 | else 351 | { 352 | return Alignment.None; 353 | } 354 | } 355 | 356 | static if (alignment == Alignment.Byte) 357 | { 358 | /*********************************************************************** 359 | Gets the address of this bitfield at its aligned byte's location 360 | */ 361 | private static immutable Address byteAlignedAddress = address + (leastSignificantBitIndex / 8u); 362 | } 363 | 364 | static if (alignment == Alignment.HalfWord) 365 | { 366 | /*********************************************************************** 367 | Gets the address of this bitfield at its aligned half-word's location 368 | */ 369 | private static immutable Address halfWordAlignedAddress = address + (leastSignificantBitIndex / 16u); 370 | } 371 | 372 | // The bitBandAddress property should only be generated if the address 373 | // of this register is aliased to a bit-banded region 374 | static if(isBitBandable) 375 | { 376 | private static Address bitBandAddress() @property @safe pure nothrow 377 | { 378 | static if (address >= PeripheralRegionStart && address <= PeripheralRegionEnd) 379 | { 380 | return PeripheralBitBandRegionStart + ((address - PeripheralRegionStart) * 32u) + (leastSignificantBitIndex * 4u); 381 | } 382 | else static if (address >= SRAMRegionStart && address <= SRAMRegionEnd) 383 | { 384 | return SRAMBitBandRegionStart + ((address - SRAMRegionStart) * 32u) + (leastSignificantBitIndex * 4u); 385 | } 386 | else 387 | { 388 | static assert(false, "Address not aliased to bit-banded region"); 389 | } 390 | } 391 | } 392 | } 393 | 394 | /*********************************************************************** 395 | Provides access and mutability enforcement for a bitfield. 396 | */ 397 | mixin template BitFieldMutation(Mutability mutability, ValueType_) 398 | { 399 | alias ValueType = ValueType_; 400 | 401 | // Sanity check: ensure bit indices are of within the size of the register 402 | static assert(isValidBitIndex(bitIndex0) && isValidBitIndex(bitIndex1), "Invalid bit index"); 403 | 404 | // Ensure correct mutability for the size of the bitfield. Some policies 405 | // are only relevant to single bits 406 | static assert(numberOfBits == 1 || !mutability.isForBitsOnly(), "Mutability is only applicable to a single bit"); 407 | 408 | // if mutabililty policy allows for reading the bit/bitfield's value 409 | static if (mutability.canRead()) 410 | { 411 | /*********************************************************************** 412 | Get this BitField's value 413 | */ 414 | @inline static ValueType value() @property @trusted nothrow 415 | { 416 | // If only a single bit, use bit banding 417 | static if (numberOfBits == 1 && isBitBandable) 418 | { 419 | return volatileLoad(cast(ValueType*)bitBandAddress); 420 | } 421 | // if can access data with perfect halfword alignment 422 | else static if (alignment == Alignment.HalfWord 423 | && (access == Access.Byte_HalfWord_Word || access == Access.HalfWord_Word)) 424 | { 425 | return volatileLoad(cast(ValueType*)halfWordAlignedAddress); 426 | } 427 | // if can access data with perfect byte alignment 428 | else static if (alignment == Alignment.Byte 429 | && (access == Access.Byte_HalfWord_Word || access == Access.Byte_Word)) 430 | { 431 | return volatileLoad(cast(ValueType*)byteAlignedAddress); 432 | } 433 | // catch-all. No optimizations possible, so read and mask and shift 434 | else 435 | { 436 | return cast(ValueType)((volatileLoad(cast(Word*)address) & bitMask) >> leastSignificantBitIndex); 437 | } 438 | } 439 | } 440 | 441 | // If mutability allows setting the bit/bitfield in some way 442 | static if (mutability.canWrite) 443 | { 444 | // Can modify the bit/bitfield's value, but only with a set or clear 445 | static if (mutability.canOnlySetOrClear) 446 | { 447 | static if (mutability == Mutability.rc_w0) 448 | { 449 | /*********************************************************************** 450 | Clears bit by writing a '0' 451 | */ 452 | @inline static void clear() @safe nothrow 453 | { 454 | value = false; 455 | } 456 | } 457 | else static if (mutability == Mutability.rc_w1) 458 | { 459 | /*********************************************************************** 460 | Clears bit by writing a '1' 461 | */ 462 | @inline static void clear() @safe nothrow 463 | { 464 | value = true; 465 | } 466 | } 467 | else static if (mutability == Mutability.rs) 468 | { 469 | /*********************************************************************** 470 | Sets bit by writing a '1' 471 | */ 472 | @inline static void set() @safe nothrow 473 | { 474 | value = true; 475 | } 476 | } 477 | 478 | // 'value' is private as it is enpsulated by the clear/set methods above 479 | private: 480 | } 481 | 482 | /*********************************************************************** 483 | Set this BitField's value 484 | */ 485 | @inline static void value(immutable ValueType value_) @property @trusted nothrow 486 | { 487 | // If only a single bit, use bit banding 488 | static if (numberOfBits == 1 && isBitBandable) 489 | { 490 | volatileStore(cast(ValueType*)bitBandAddress, value_); 491 | } 492 | // if can access data with perfect halfword alignment 493 | else static if (alignment == Alignment.HalfWord 494 | && (access == Access.Byte_HalfWord_Word || access == Access.HalfWord_Word)) 495 | { 496 | volatileStore(cast(ValueType*)halfWordAlignedAddress, value_); 497 | } 498 | // if can access data with perfect byte alignment 499 | else static if (alignment == Alignment.Byte 500 | && (access == Access.Byte_HalfWord_Word || access == Access.Byte_Word)) 501 | { 502 | volatileStore(cast(ValueType*)byteAlignedAddress, value_); 503 | } 504 | // catch-all. No optimizations possible, so just do read-modify-write 505 | else 506 | { 507 | volatileStore(cast(Word*)address, (volatileLoad(cast(Word*)address) & ~bitMask) | ((cast(Word)value_) << leastSignificantBitIndex)); 508 | } 509 | } 510 | } 511 | 512 | // So we don't need to constantly type ".value" every time we want 513 | // to read/write a bitfield 514 | static alias value this; 515 | } 516 | 517 | /*********************************************************************** 518 | Provides access to a limited range of bits in a register. This 519 | version automatically determines the return type based on the size 520 | of the bitfield. 521 | */ 522 | mixin template BitFieldImplementation(BitIndex bitIndex0, BitIndex bitIndex1, Mutability mutability) 523 | { 524 | mixin BitFieldDimensions!(bitIndex0, bitIndex1); 525 | 526 | //TODO: do a test to determine if limiting return type to something less 527 | // than the natural word size results in slower code. Perhaps it's better 528 | // to simply make everything default to Word 529 | 530 | // determine the return type based on the number of bits 531 | static if (numberOfBits <= 1) 532 | { 533 | alias ValueType = bool; 534 | } 535 | else static if (numberOfBits <= (ubyte.sizeof * 8)) 536 | { 537 | alias ValueType = ubyte; 538 | } 539 | else static if (numberOfBits <= (HalfWord.sizeof * 8)) 540 | { 541 | alias ValueType = HalfWord; 542 | } 543 | else static if (numberOfBits <= (Word.sizeof * 8)) 544 | { 545 | alias ValueType = Word; 546 | } 547 | 548 | mixin BitFieldMutation!(mutability, ValueType); 549 | } 550 | 551 | /*********************************************************************** 552 | Provides access to a limited range of bits in a register. User 553 | must specify the return type. 554 | */ 555 | mixin template BitFieldImplementation(BitIndex bitIndex0, BitIndex bitIndex1, Mutability mutability, ValueType) 556 | { 557 | mixin BitFieldDimensions!(bitIndex0, bitIndex1); 558 | mixin BitFieldMutation!(mutability, ValueType); 559 | } 560 | 561 | /*********************************************************************** 562 | For modeling a peripheral register bank 563 | */ 564 | abstract class Peripheral(Address peripheralAddress) 565 | { 566 | /*********************************************************************** 567 | Gets this peripheral's address as specified in the datasheet 568 | */ 569 | static immutable auto address = peripheralAddress; 570 | 571 | /*********************************************************************** 572 | A register for this peripheral 573 | */ 574 | abstract class Register(ptrdiff_t addressOffset, Access access_ = Access.Byte_HalfWord_Word) 575 | { 576 | /*********************************************************************** 577 | Gets this register's address as specified in the datasheet 578 | */ 579 | static immutable auto address = peripheralAddress + addressOffset; 580 | 581 | /*********************************************************************** 582 | Whether or not the address has a bit-banded alias 583 | */ 584 | static immutable auto isBitBandable = 585 | (address >= PeripheralRegionStart && address <= PeripheralRegionEnd) 586 | || (address >= SRAMRegionStart && address <= SRAMRegionEnd); 587 | 588 | 589 | /*********************************************************************** 590 | Gets the data width(byte, half-word, word) access policy for this 591 | register. 592 | */ 593 | static immutable auto access = access_; 594 | 595 | /*********************************************************************** 596 | Gets all bits in the register as a single value. It's only exposed 597 | privately to prevent circumventing the access mutability. 598 | */ 599 | private static auto value() @property @trusted nothrow 600 | { 601 | return volatileLoad(cast(Word*)address); 602 | } 603 | 604 | /*********************************************************************** 605 | Sets all bits in the register as a single value. It's only exposed 606 | privately to prevent circumventing the access mutability. 607 | */ 608 | private static void value(immutable Word value) @property @trusted nothrow 609 | { 610 | volatileStore(cast(Word*)address, value); 611 | } 612 | 613 | /*********************************************************************** 614 | Recursive template to combine values of each bitfield passed to the 615 | setValue function 616 | */ 617 | @inline private static Word combineValues(T...)() @safe nothrow 618 | { 619 | static if (T.length > 0) 620 | { 621 | //TODO: ensure T[0] is a child of this register 622 | // Currently doesn't work due to https://issues.dlang.org/show_bug.cgi?id=12496 623 | //static assert(__traits(isSame, __traits(parent, T[0]), __traits(parent, value)), "Bitfield is not part of this register"); 624 | 625 | //Ensure value assignment is legal 626 | // Need to wrap assignment expression in parentheses due to https://issues.dlang.org/show_bug.cgi?id=17703 627 | static assert(__traits(compiles, (T[0].value = T[1])), "Invalid assignment"); 628 | 629 | // merge all specified bitFields into a single Word value and assign to this 630 | // register's value 631 | return T[0].maskValue(T[1]) | combineValues!(T[2..$])(); 632 | } 633 | else 634 | { 635 | // no more values left to combine 636 | return 0; 637 | } 638 | } 639 | 640 | /*********************************************************************** 641 | Recursive template to combine masks of each bitfield passed to the 642 | setValue function 643 | */ 644 | @inline private static Word combineMasks(T...)() @safe nothrow 645 | { 646 | static if (T.length > 0) 647 | { 648 | // merge all specified bitFields and assign to this register's value 649 | return T[0].bitMask | combineMasks!(T[2..$])(); 650 | } 651 | else 652 | { 653 | // no more values left to combine 654 | return 0; 655 | } 656 | } 657 | 658 | /*********************************************************************** 659 | Sets multiple bit fields simultaneously 660 | */ 661 | @inline static void setValue(T...)() @safe nothrow 662 | { 663 | // number of arguments must be even 664 | static assert(!(T.length & 1), "Wrong number of arguments"); 665 | 666 | value = (value & ~combineMasks!(T)()) | combineValues!(T)(); 667 | } 668 | 669 | /*********************************************************************** 670 | A range of bits in the this register. Return type is automatically 671 | determined. 672 | */ 673 | final abstract class BitField(BitIndex bitIndex0, BitIndex bitIndex1, Mutability mutability) 674 | { 675 | mixin BitFieldImplementation!(bitIndex0, bitIndex1, mutability); 676 | } 677 | 678 | /*********************************************************************** 679 | A range of bits in the this register. User must specify the return 680 | type. 681 | */ 682 | final abstract class BitField(BitIndex bitIndex0, BitIndex bitIndex1, Mutability mutability, ValueType) 683 | { 684 | mixin BitFieldImplementation!(bitIndex0, bitIndex1, mutability, ValueType); 685 | } 686 | 687 | /*********************************************************************** 688 | A special case of BitField (a single bit). Return type is automatically 689 | determined. 690 | */ 691 | final abstract class Bit(BitIndex bitIndex, Mutability mutability) 692 | { 693 | mixin BitFieldImplementation!(bitIndex, bitIndex, mutability); 694 | } 695 | 696 | /*********************************************************************** 697 | A special case of BitField (a single bit). User must specify the return 698 | type. 699 | */ 700 | final abstract class Bit(BitIndex bitIndex, Mutability mutability, ValueType) 701 | { 702 | mixin BitFieldImplementation!(bitIndex, bitIndex, mutability, ValueType); 703 | } 704 | } 705 | } 706 | 707 | --------------------------------------------------------------------------------