├── .gitattributes
├── .mxproject
├── DBUS.ioc
├── Drivers
├── CMSIS
│ ├── Device
│ │ └── ST
│ │ │ └── STM32F4xx
│ │ │ └── Include
│ │ │ ├── stm32f407xx.h
│ │ │ ├── stm32f4xx.h
│ │ │ └── system_stm32f4xx.h
│ └── Include
│ │ ├── cmsis_armcc.h
│ │ ├── cmsis_armclang.h
│ │ ├── cmsis_compiler.h
│ │ ├── cmsis_gcc.h
│ │ ├── cmsis_iccarm.h
│ │ ├── cmsis_version.h
│ │ ├── core_armv8mbl.h
│ │ ├── core_armv8mml.h
│ │ ├── core_cm0.h
│ │ ├── core_cm0plus.h
│ │ ├── core_cm1.h
│ │ ├── core_cm23.h
│ │ ├── core_cm3.h
│ │ ├── core_cm33.h
│ │ ├── core_cm4.h
│ │ ├── core_cm7.h
│ │ ├── core_sc000.h
│ │ ├── core_sc300.h
│ │ ├── mpu_armv7.h
│ │ ├── mpu_armv8.h
│ │ └── tz_context.h
└── STM32F4xx_HAL_Driver
│ ├── Inc
│ ├── Legacy
│ │ └── stm32_hal_legacy.h
│ ├── stm32f4xx_hal.h
│ ├── stm32f4xx_hal_can.h
│ ├── stm32f4xx_hal_cortex.h
│ ├── stm32f4xx_hal_def.h
│ ├── stm32f4xx_hal_dma.h
│ ├── stm32f4xx_hal_dma_ex.h
│ ├── stm32f4xx_hal_exti.h
│ ├── stm32f4xx_hal_flash.h
│ ├── stm32f4xx_hal_flash_ex.h
│ ├── stm32f4xx_hal_flash_ramfunc.h
│ ├── stm32f4xx_hal_gpio.h
│ ├── stm32f4xx_hal_gpio_ex.h
│ ├── stm32f4xx_hal_pwr.h
│ ├── stm32f4xx_hal_pwr_ex.h
│ ├── stm32f4xx_hal_rcc.h
│ ├── stm32f4xx_hal_rcc_ex.h
│ ├── stm32f4xx_hal_tim.h
│ ├── stm32f4xx_hal_tim_ex.h
│ └── stm32f4xx_hal_uart.h
│ └── Src
│ ├── stm32f4xx_hal.c
│ ├── stm32f4xx_hal_can.c
│ ├── stm32f4xx_hal_cortex.c
│ ├── stm32f4xx_hal_dma.c
│ ├── stm32f4xx_hal_dma_ex.c
│ ├── stm32f4xx_hal_exti.c
│ ├── stm32f4xx_hal_flash.c
│ ├── stm32f4xx_hal_flash_ex.c
│ ├── stm32f4xx_hal_flash_ramfunc.c
│ ├── stm32f4xx_hal_gpio.c
│ ├── stm32f4xx_hal_pwr.c
│ ├── stm32f4xx_hal_pwr_ex.c
│ ├── stm32f4xx_hal_rcc.c
│ ├── stm32f4xx_hal_rcc_ex.c
│ ├── stm32f4xx_hal_tim.c
│ ├── stm32f4xx_hal_tim_ex.c
│ └── stm32f4xx_hal_uart.c
├── Inc
├── can.h
├── dma.h
├── gpio.h
├── main.h
├── stm32f4xx_hal_conf.h
├── stm32f4xx_it.h
├── tim.h
└── usart.h
├── MDK-ARM
├── DBUS.uvguix.Johnson
├── DBUS.uvoptx
├── DBUS.uvprojx
├── DBUS
│ ├── DBUS.hex
│ └── DBUS.lnp
├── DebugConfig
│ └── DBUS_STM32F407IGHx.dbgconf
├── EventRecorderStub.scvd
├── RTE
│ └── _DBUS
│ │ └── RTE_Components.h
├── startup_stm32f407xx.lst
└── startup_stm32f407xx.s
├── README.md
├── Src
├── can.c
├── dma.c
├── gpio.c
├── main.c
├── stm32f4xx_hal_msp.c
├── stm32f4xx_it.c
├── system_stm32f4xx.c
├── tim.c
└── usart.c
├── application
├── CAN_receive.c
├── CAN_receive.h
└── struct_typedef.h
├── boards
├── bsp_can.c
└── bsp_can.h
├── keilkilll.bat
└── 课程5、CAN总线与电机.docx
/.gitattributes:
--------------------------------------------------------------------------------
1 | # Auto detect text files and perform LF normalization
2 | * text=auto
3 |
--------------------------------------------------------------------------------
/.mxproject:
--------------------------------------------------------------------------------
1 | [PreviousGenFiles]
2 | HeaderPath=C:/Users/Johnson/Desktop/ControlLesson/lesson5/Inc
3 | HeaderFiles=gpio.h;can.h;dma.h;tim.h;usart.h;stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h;
4 | SourcePath=C:/Users/Johnson/Desktop/ControlLesson/lesson5/Src
5 | SourceFiles=gpio.c;can.c;dma.c;tim.c;usart.c;stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c;
6 |
7 | [PreviousLibFiles]
8 | LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
9 |
10 | [PreviousUsedKeilFiles]
11 | SourceFiles=..\Src\main.c;..\Src\gpio.c;..\Src\can.c;..\Src\dma.c;..\Src\tim.c;..\Src\usart.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;;
12 | HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc;
13 | CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
14 |
15 |
--------------------------------------------------------------------------------
/DBUS.ioc:
--------------------------------------------------------------------------------
1 | #MicroXplorer Configuration settings - do not modify
2 | CAN1.BS1=CAN_BS1_10TQ
3 | CAN1.BS2=CAN_BS2_3TQ
4 | CAN1.CalculateTimeQuantum=71.42857142857143
5 | CAN1.IPParameters=CalculateTimeQuantum,Prescaler,BS1,BS2
6 | CAN1.Prescaler=3
7 | CAN2.BS1=CAN_BS1_10TQ
8 | CAN2.BS2=CAN_BS2_3TQ
9 | CAN2.CalculateTimeQuantum=71.42857142857143
10 | CAN2.IPParameters=CalculateTimeQuantum,BS1,BS2,Prescaler
11 | CAN2.Prescaler=3
12 | Dma.Request0=USART3_RX
13 | Dma.RequestsNb=1
14 | Dma.USART3_RX.0.Direction=DMA_PERIPH_TO_MEMORY
15 | Dma.USART3_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE
16 | Dma.USART3_RX.0.Instance=DMA1_Stream1
17 | Dma.USART3_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
18 | Dma.USART3_RX.0.MemInc=DMA_MINC_ENABLE
19 | Dma.USART3_RX.0.Mode=DMA_CIRCULAR
20 | Dma.USART3_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
21 | Dma.USART3_RX.0.PeriphInc=DMA_PINC_DISABLE
22 | Dma.USART3_RX.0.Priority=DMA_PRIORITY_VERY_HIGH
23 | Dma.USART3_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
24 | File.Version=6
25 | GPIO.groupedBy=Group By Peripherals
26 | KeepUserPlacement=false
27 | Mcu.Family=STM32F4
28 | Mcu.IP0=CAN1
29 | Mcu.IP1=CAN2
30 | Mcu.IP2=DMA
31 | Mcu.IP3=NVIC
32 | Mcu.IP4=RCC
33 | Mcu.IP5=SYS
34 | Mcu.IP6=TIM1
35 | Mcu.IP7=TIM8
36 | Mcu.IP8=USART3
37 | Mcu.IPNb=9
38 | Mcu.Name=STM32F407I(E-G)Hx
39 | Mcu.Package=UFBGA176
40 | Mcu.Pin0=PB5
41 | Mcu.Pin1=PA14
42 | Mcu.Pin10=PH0-OSC_IN
43 | Mcu.Pin11=PH1-OSC_OUT
44 | Mcu.Pin12=PC6
45 | Mcu.Pin13=PE13
46 | Mcu.Pin14=PE9
47 | Mcu.Pin15=PE11
48 | Mcu.Pin16=PE14
49 | Mcu.Pin17=VP_SYS_VS_Systick
50 | Mcu.Pin18=VP_TIM1_VS_ClockSourceINT
51 | Mcu.Pin19=VP_TIM8_VS_ClockSourceINT
52 | Mcu.Pin2=PA13
53 | Mcu.Pin3=PB6
54 | Mcu.Pin4=PD0
55 | Mcu.Pin5=PC11
56 | Mcu.Pin6=PC10
57 | Mcu.Pin7=PI7
58 | Mcu.Pin8=PI6
59 | Mcu.Pin9=PD1
60 | Mcu.PinsNb=20
61 | Mcu.ThirdPartyNb=0
62 | Mcu.UserConstants=
63 | Mcu.UserName=STM32F407IGHx
64 | MxCube.Version=5.6.0
65 | MxDb.Version=DB.5.0.60
66 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
67 | NVIC.CAN1_RX0_IRQn=true\:0\:0\:false\:false\:true\:true\:true
68 | NVIC.CAN2_RX0_IRQn=true\:0\:0\:false\:false\:true\:true\:true
69 | NVIC.DMA1_Stream1_IRQn=true\:0\:0\:false\:false\:true\:false\:true
70 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
71 | NVIC.ForceEnableDMAVector=true
72 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
73 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
74 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
75 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false
76 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
77 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false
78 | NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
79 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
80 | PA13.Mode=Serial_Wire
81 | PA13.Signal=SYS_JTMS-SWDIO
82 | PA14.Mode=Serial_Wire
83 | PA14.Signal=SYS_JTCK-SWCLK
84 | PB5.Mode=Slave
85 | PB5.Signal=CAN2_RX
86 | PB6.Mode=Slave
87 | PB6.Signal=CAN2_TX
88 | PC10.Mode=Asynchronous
89 | PC10.Signal=USART3_TX
90 | PC11.Mode=Asynchronous
91 | PC11.Signal=USART3_RX
92 | PC6.GPIOParameters=GPIO_Speed,GPIO_PuPd
93 | PC6.GPIO_PuPd=GPIO_PULLUP
94 | PC6.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
95 | PC6.Locked=true
96 | PC6.Signal=S_TIM8_CH1
97 | PD0.Locked=true
98 | PD0.Mode=Master
99 | PD0.Signal=CAN1_RX
100 | PD1.Locked=true
101 | PD1.Mode=Master
102 | PD1.Signal=CAN1_TX
103 | PE11.GPIOParameters=GPIO_Speed,GPIO_PuPd
104 | PE11.GPIO_PuPd=GPIO_PULLUP
105 | PE11.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
106 | PE11.Locked=true
107 | PE11.Signal=S_TIM1_CH2
108 | PE13.GPIOParameters=GPIO_Speed,GPIO_PuPd
109 | PE13.GPIO_PuPd=GPIO_PULLUP
110 | PE13.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
111 | PE13.Locked=true
112 | PE13.Signal=S_TIM1_CH3
113 | PE14.GPIOParameters=GPIO_Speed,GPIO_PuPd
114 | PE14.GPIO_PuPd=GPIO_PULLUP
115 | PE14.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
116 | PE14.Locked=true
117 | PE14.Signal=S_TIM1_CH4
118 | PE9.GPIOParameters=GPIO_Speed,GPIO_PuPd
119 | PE9.GPIO_PuPd=GPIO_PULLUP
120 | PE9.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
121 | PE9.Locked=true
122 | PE9.Signal=S_TIM1_CH1
123 | PH0-OSC_IN.Mode=HSE-External-Oscillator
124 | PH0-OSC_IN.Signal=RCC_OSC_IN
125 | PH1-OSC_OUT.Mode=HSE-External-Oscillator
126 | PH1-OSC_OUT.Signal=RCC_OSC_OUT
127 | PI6.GPIOParameters=GPIO_Speed,GPIO_PuPd
128 | PI6.GPIO_PuPd=GPIO_PULLUP
129 | PI6.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
130 | PI6.Signal=S_TIM8_CH2
131 | PI7.GPIOParameters=GPIO_Speed,GPIO_PuPd
132 | PI7.GPIO_PuPd=GPIO_PULLUP
133 | PI7.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
134 | PI7.Locked=true
135 | PI7.Signal=S_TIM8_CH3
136 | PinOutPanel.CurrentBGAView=Top
137 | PinOutPanel.RotationAngle=0
138 | ProjectManager.AskForMigrate=true
139 | ProjectManager.BackupPrevious=false
140 | ProjectManager.CompilerOptimize=6
141 | ProjectManager.ComputerToolchain=false
142 | ProjectManager.CoupleFile=true
143 | ProjectManager.CustomerFirmwarePackage=
144 | ProjectManager.DefaultFWLocation=true
145 | ProjectManager.DeletePrevious=true
146 | ProjectManager.DeviceId=STM32F407IGHx
147 | ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.0
148 | ProjectManager.FreePins=false
149 | ProjectManager.HalAssertFull=false
150 | ProjectManager.HeapSize=0x2000
151 | ProjectManager.KeepUserCode=true
152 | ProjectManager.LastFirmware=true
153 | ProjectManager.LibraryCopy=1
154 | ProjectManager.MainLocation=Src
155 | ProjectManager.NoMain=false
156 | ProjectManager.PreviousToolchain=
157 | ProjectManager.ProjectBuild=false
158 | ProjectManager.ProjectFileName=DBUS.ioc
159 | ProjectManager.ProjectName=DBUS
160 | ProjectManager.StackSize=0x2000
161 | ProjectManager.TargetToolchain=MDK-ARM V5
162 | ProjectManager.ToolChainLocation=
163 | ProjectManager.UnderRoot=false
164 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_TIM8_Init-TIM8-false-HAL-true,5-MX_TIM1_Init-TIM1-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true
165 | RCC.48MHZClocksFreq_Value=48000000
166 | RCC.AHBFreq_Value=168000000
167 | RCC.APB1CLKDivider=RCC_HCLK_DIV4
168 | RCC.APB1Freq_Value=42000000
169 | RCC.APB1TimFreq_Value=84000000
170 | RCC.APB2CLKDivider=RCC_HCLK_DIV2
171 | RCC.APB2Freq_Value=84000000
172 | RCC.APB2TimFreq_Value=168000000
173 | RCC.CortexFreq_Value=168000000
174 | RCC.EthernetFreq_Value=168000000
175 | RCC.FCLKCortexFreq_Value=168000000
176 | RCC.FamilyName=M
177 | RCC.HCLKFreq_Value=168000000
178 | RCC.HSE_VALUE=12000000
179 | RCC.HSI_VALUE=16000000
180 | RCC.I2SClocksFreq_Value=192000000
181 | RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_SourceVirtual,RCC_RTC_Clock_Source_FROM_HSE,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
182 | RCC.LSE_VALUE=32768
183 | RCC.LSI_VALUE=32000
184 | RCC.MCO2PinFreq_Value=168000000
185 | RCC.PLLCLKFreq_Value=168000000
186 | RCC.PLLM=6
187 | RCC.PLLN=168
188 | RCC.PLLQ=7
189 | RCC.PLLQCLKFreq_Value=48000000
190 | RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
191 | RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_HSE_DIV30
192 | RCC.RCC_RTC_Clock_Source_FROM_HSE=RCC_RTCCLKSOURCE_HSE_DIV30
193 | RCC.RTCFreq_Value=400000
194 | RCC.RTCHSEDivFreq_Value=400000
195 | RCC.SYSCLKFreq_VALUE=168000000
196 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
197 | RCC.VCOI2SOutputFreq_Value=384000000
198 | RCC.VCOInputFreq_Value=2000000
199 | RCC.VCOOutputFreq_Value=336000000
200 | RCC.VcooutputI2S=192000000
201 | SH.S_TIM1_CH1.0=TIM1_CH1,PWM Generation1 CH1
202 | SH.S_TIM1_CH1.ConfNb=1
203 | SH.S_TIM1_CH2.0=TIM1_CH2,PWM Generation2 CH2
204 | SH.S_TIM1_CH2.ConfNb=1
205 | SH.S_TIM1_CH3.0=TIM1_CH3,PWM Generation3 CH3
206 | SH.S_TIM1_CH3.ConfNb=1
207 | SH.S_TIM1_CH4.0=TIM1_CH4,PWM Generation4 CH4
208 | SH.S_TIM1_CH4.ConfNb=1
209 | SH.S_TIM8_CH1.0=TIM8_CH1,PWM Generation1 CH1
210 | SH.S_TIM8_CH1.ConfNb=1
211 | SH.S_TIM8_CH2.0=TIM8_CH2,PWM Generation2 CH2
212 | SH.S_TIM8_CH2.ConfNb=1
213 | SH.S_TIM8_CH3.0=TIM8_CH3,PWM Generation3 CH3
214 | SH.S_TIM8_CH3.ConfNb=1
215 | TIM1.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
216 | TIM1.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
217 | TIM1.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
218 | TIM1.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
219 | TIM1.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4,Period,Prescaler,Pulse-PWM Generation1 CH1,Pulse-PWM Generation2 CH2,Pulse-PWM Generation3 CH3,Pulse-PWM Generation4 CH4
220 | TIM1.Period=19999
221 | TIM1.Prescaler=167
222 | TIM1.Pulse-PWM\ Generation1\ CH1=2000
223 | TIM1.Pulse-PWM\ Generation2\ CH2=2000
224 | TIM1.Pulse-PWM\ Generation3\ CH3=2000
225 | TIM1.Pulse-PWM\ Generation4\ CH4=2000
226 | TIM8.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
227 | TIM8.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
228 | TIM8.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
229 | TIM8.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation2 CH2,Channel-PWM Generation1 CH1,Prescaler,Period,Pulse-PWM Generation1 CH1,Pulse-PWM Generation2 CH2,Pulse-PWM Generation3 CH3
230 | TIM8.Period=19999
231 | TIM8.Prescaler=167
232 | TIM8.Pulse-PWM\ Generation1\ CH1=2000
233 | TIM8.Pulse-PWM\ Generation2\ CH2=2000
234 | TIM8.Pulse-PWM\ Generation3\ CH3=2000
235 | USART3.BaudRate=100000
236 | USART3.IPParameters=VirtualMode,BaudRate,Parity,WordLength
237 | USART3.Parity=PARITY_EVEN
238 | USART3.VirtualMode=VM_ASYNC
239 | USART3.WordLength=WORDLENGTH_9B
240 | VP_SYS_VS_Systick.Mode=SysTick
241 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick
242 | VP_TIM1_VS_ClockSourceINT.Mode=Internal
243 | VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
244 | VP_TIM8_VS_ClockSourceINT.Mode=Internal
245 | VP_TIM8_VS_ClockSourceINT.Signal=TIM8_VS_ClockSourceINT
246 | board=custom
247 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/JohnsonGu/TypeC_Lesson4_CANbusAndMotor/6e45f660d0a89b7a1d0ad38be3fa657768792646/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
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/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f4xx.h
4 | * @author MCD Application Team
5 | * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © COPYRIGHT(c) 2017 STMicroelectronics
10 | *
11 | * Redistribution and use in source and binary forms, with or without modification,
12 | * are permitted provided that the following conditions are met:
13 | * 1. Redistributions of source code must retain the above copyright notice,
14 | * this list of conditions and the following disclaimer.
15 | * 2. Redistributions in binary form must reproduce the above copyright notice,
16 | * this list of conditions and the following disclaimer in the documentation
17 | * and/or other materials provided with the distribution.
18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 | * may be used to endorse or promote products derived from this software
20 | * without specific prior written permission.
21 | *
22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 | *
33 | ******************************************************************************
34 | */
35 |
36 | /** @addtogroup CMSIS
37 | * @{
38 | */
39 |
40 | /** @addtogroup stm32f4xx_system
41 | * @{
42 | */
43 |
44 | /**
45 | * @brief Define to prevent recursive inclusion
46 | */
47 | #ifndef __SYSTEM_STM32F4XX_H
48 | #define __SYSTEM_STM32F4XX_H
49 |
50 | #ifdef __cplusplus
51 | extern "C" {
52 | #endif
53 |
54 | /** @addtogroup STM32F4xx_System_Includes
55 | * @{
56 | */
57 |
58 | /**
59 | * @}
60 | */
61 |
62 |
63 | /** @addtogroup STM32F4xx_System_Exported_types
64 | * @{
65 | */
66 | /* This variable is updated in three ways:
67 | 1) by calling CMSIS function SystemCoreClockUpdate()
68 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
69 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
70 | Note: If you use this function to configure the system clock; then there
71 | is no need to call the 2 first functions listed above, since SystemCoreClock
72 | variable is updated automatically.
73 | */
74 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
75 |
76 | extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
77 | extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
78 |
79 | /**
80 | * @}
81 | */
82 |
83 | /** @addtogroup STM32F4xx_System_Exported_Constants
84 | * @{
85 | */
86 |
87 | /**
88 | * @}
89 | */
90 |
91 | /** @addtogroup STM32F4xx_System_Exported_Macros
92 | * @{
93 | */
94 |
95 | /**
96 | * @}
97 | */
98 |
99 | /** @addtogroup STM32F4xx_System_Exported_Functions
100 | * @{
101 | */
102 |
103 | extern void SystemInit(void);
104 | extern void SystemCoreClockUpdate(void);
105 | /**
106 | * @}
107 | */
108 |
109 | #ifdef __cplusplus
110 | }
111 | #endif
112 |
113 | #endif /*__SYSTEM_STM32F4XX_H */
114 |
115 | /**
116 | * @}
117 | */
118 |
119 | /**
120 | * @}
121 | */
122 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
123 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Include/cmsis_compiler.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file cmsis_compiler.h
3 | * @brief CMSIS compiler generic header file
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #ifndef __CMSIS_COMPILER_H
26 | #define __CMSIS_COMPILER_H
27 |
28 | #include
29 |
30 | /*
31 | * Arm Compiler 4/5
32 | */
33 | #if defined ( __CC_ARM )
34 | #include "cmsis_armcc.h"
35 |
36 |
37 | /*
38 | * Arm Compiler 6 (armclang)
39 | */
40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
41 | #include "cmsis_armclang.h"
42 |
43 |
44 | /*
45 | * GNU Compiler
46 | */
47 | #elif defined ( __GNUC__ )
48 | #include "cmsis_gcc.h"
49 |
50 |
51 | /*
52 | * IAR Compiler
53 | */
54 | #elif defined ( __ICCARM__ )
55 | #include
56 |
57 |
58 | /*
59 | * TI Arm Compiler
60 | */
61 | #elif defined ( __TI_ARM__ )
62 | #include
63 |
64 | #ifndef __ASM
65 | #define __ASM __asm
66 | #endif
67 | #ifndef __INLINE
68 | #define __INLINE inline
69 | #endif
70 | #ifndef __STATIC_INLINE
71 | #define __STATIC_INLINE static inline
72 | #endif
73 | #ifndef __STATIC_FORCEINLINE
74 | #define __STATIC_FORCEINLINE __STATIC_INLINE
75 | #endif
76 | #ifndef __NO_RETURN
77 | #define __NO_RETURN __attribute__((noreturn))
78 | #endif
79 | #ifndef __USED
80 | #define __USED __attribute__((used))
81 | #endif
82 | #ifndef __WEAK
83 | #define __WEAK __attribute__((weak))
84 | #endif
85 | #ifndef __PACKED
86 | #define __PACKED __attribute__((packed))
87 | #endif
88 | #ifndef __PACKED_STRUCT
89 | #define __PACKED_STRUCT struct __attribute__((packed))
90 | #endif
91 | #ifndef __PACKED_UNION
92 | #define __PACKED_UNION union __attribute__((packed))
93 | #endif
94 | #ifndef __UNALIGNED_UINT32 /* deprecated */
95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; };
96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
97 | #endif
98 | #ifndef __UNALIGNED_UINT16_WRITE
99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
101 | #endif
102 | #ifndef __UNALIGNED_UINT16_READ
103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
105 | #endif
106 | #ifndef __UNALIGNED_UINT32_WRITE
107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
109 | #endif
110 | #ifndef __UNALIGNED_UINT32_READ
111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
113 | #endif
114 | #ifndef __ALIGNED
115 | #define __ALIGNED(x) __attribute__((aligned(x)))
116 | #endif
117 | #ifndef __RESTRICT
118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
119 | #define __RESTRICT
120 | #endif
121 |
122 |
123 | /*
124 | * TASKING Compiler
125 | */
126 | #elif defined ( __TASKING__ )
127 | /*
128 | * The CMSIS functions have been implemented as intrinsics in the compiler.
129 | * Please use "carm -?i" to get an up to date list of all intrinsics,
130 | * Including the CMSIS ones.
131 | */
132 |
133 | #ifndef __ASM
134 | #define __ASM __asm
135 | #endif
136 | #ifndef __INLINE
137 | #define __INLINE inline
138 | #endif
139 | #ifndef __STATIC_INLINE
140 | #define __STATIC_INLINE static inline
141 | #endif
142 | #ifndef __STATIC_FORCEINLINE
143 | #define __STATIC_FORCEINLINE __STATIC_INLINE
144 | #endif
145 | #ifndef __NO_RETURN
146 | #define __NO_RETURN __attribute__((noreturn))
147 | #endif
148 | #ifndef __USED
149 | #define __USED __attribute__((used))
150 | #endif
151 | #ifndef __WEAK
152 | #define __WEAK __attribute__((weak))
153 | #endif
154 | #ifndef __PACKED
155 | #define __PACKED __packed__
156 | #endif
157 | #ifndef __PACKED_STRUCT
158 | #define __PACKED_STRUCT struct __packed__
159 | #endif
160 | #ifndef __PACKED_UNION
161 | #define __PACKED_UNION union __packed__
162 | #endif
163 | #ifndef __UNALIGNED_UINT32 /* deprecated */
164 | struct __packed__ T_UINT32 { uint32_t v; };
165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
166 | #endif
167 | #ifndef __UNALIGNED_UINT16_WRITE
168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
170 | #endif
171 | #ifndef __UNALIGNED_UINT16_READ
172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
174 | #endif
175 | #ifndef __UNALIGNED_UINT32_WRITE
176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
178 | #endif
179 | #ifndef __UNALIGNED_UINT32_READ
180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
182 | #endif
183 | #ifndef __ALIGNED
184 | #define __ALIGNED(x) __align(x)
185 | #endif
186 | #ifndef __RESTRICT
187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
188 | #define __RESTRICT
189 | #endif
190 |
191 |
192 | /*
193 | * COSMIC Compiler
194 | */
195 | #elif defined ( __CSMC__ )
196 | #include
197 |
198 | #ifndef __ASM
199 | #define __ASM _asm
200 | #endif
201 | #ifndef __INLINE
202 | #define __INLINE inline
203 | #endif
204 | #ifndef __STATIC_INLINE
205 | #define __STATIC_INLINE static inline
206 | #endif
207 | #ifndef __STATIC_FORCEINLINE
208 | #define __STATIC_FORCEINLINE __STATIC_INLINE
209 | #endif
210 | #ifndef __NO_RETURN
211 | // NO RETURN is automatically detected hence no warning here
212 | #define __NO_RETURN
213 | #endif
214 | #ifndef __USED
215 | #warning No compiler specific solution for __USED. __USED is ignored.
216 | #define __USED
217 | #endif
218 | #ifndef __WEAK
219 | #define __WEAK __weak
220 | #endif
221 | #ifndef __PACKED
222 | #define __PACKED @packed
223 | #endif
224 | #ifndef __PACKED_STRUCT
225 | #define __PACKED_STRUCT @packed struct
226 | #endif
227 | #ifndef __PACKED_UNION
228 | #define __PACKED_UNION @packed union
229 | #endif
230 | #ifndef __UNALIGNED_UINT32 /* deprecated */
231 | @packed struct T_UINT32 { uint32_t v; };
232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
233 | #endif
234 | #ifndef __UNALIGNED_UINT16_WRITE
235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
237 | #endif
238 | #ifndef __UNALIGNED_UINT16_READ
239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
241 | #endif
242 | #ifndef __UNALIGNED_UINT32_WRITE
243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
245 | #endif
246 | #ifndef __UNALIGNED_UINT32_READ
247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
249 | #endif
250 | #ifndef __ALIGNED
251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
252 | #define __ALIGNED(x)
253 | #endif
254 | #ifndef __RESTRICT
255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
256 | #define __RESTRICT
257 | #endif
258 |
259 |
260 | #else
261 | #error Unknown compiler.
262 | #endif
263 |
264 |
265 | #endif /* __CMSIS_COMPILER_H */
266 |
267 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Include/cmsis_version.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file cmsis_version.h
3 | * @brief CMSIS Core(M) Version definitions
4 | * @version V5.0.2
5 | * @date 19. April 2017
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef __CMSIS_VERSION_H
32 | #define __CMSIS_VERSION_H
33 |
34 | /* CMSIS Version definitions */
35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
39 | #endif
40 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Include/mpu_armv7.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file mpu_armv7.h
3 | * @brief CMSIS MPU API for Armv7-M MPU
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef ARM_MPU_ARMV7_H
32 | #define ARM_MPU_ARMV7_H
33 |
34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
62 |
63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
69 |
70 | /** MPU Region Base Address Register Value
71 | *
72 | * \param Region The region to be configured, number 0 to 15.
73 | * \param BaseAddress The base address for the region.
74 | */
75 | #define ARM_MPU_RBAR(Region, BaseAddress) \
76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
77 | ((Region) & MPU_RBAR_REGION_Msk) | \
78 | (MPU_RBAR_VALID_Msk))
79 |
80 | /**
81 | * MPU Memory Access Attributes
82 | *
83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
84 | * \param IsShareable Region is shareable between multiple bus masters.
85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
87 | */
88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
93 |
94 | /**
95 | * MPU Region Attribute and Size Register Value
96 | *
97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
100 | * \param SubRegionDisable Sub-region disable field.
101 | * \param Size Region size of the region to be configured, for example 4K, 8K.
102 | */
103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
107 |
108 | /**
109 | * MPU Region Attribute and Size Register Value
110 | *
111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
114 | * \param IsShareable Region is shareable between multiple bus masters.
115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
117 | * \param SubRegionDisable Sub-region disable field.
118 | * \param Size Region size of the region to be configured, for example 4K, 8K.
119 | */
120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
122 |
123 | /**
124 | * MPU Memory Access Attribute for strongly ordered memory.
125 | * - TEX: 000b
126 | * - Shareable
127 | * - Non-cacheable
128 | * - Non-bufferable
129 | */
130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
131 |
132 | /**
133 | * MPU Memory Access Attribute for device memory.
134 | * - TEX: 000b (if non-shareable) or 010b (if shareable)
135 | * - Shareable or non-shareable
136 | * - Non-cacheable
137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable)
138 | *
139 | * \param IsShareable Configures the device memory as shareable or non-shareable.
140 | */
141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
142 |
143 | /**
144 | * MPU Memory Access Attribute for normal memory.
145 | * - TEX: 1BBb (reflecting outer cacheability rules)
146 | * - Shareable or non-shareable
147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules)
148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules)
149 | *
150 | * \param OuterCp Configures the outer cache policy.
151 | * \param InnerCp Configures the inner cache policy.
152 | * \param IsShareable Configures the memory as shareable or non-shareable.
153 | */
154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
155 |
156 | /**
157 | * MPU Memory Access Attribute non-cacheable policy.
158 | */
159 | #define ARM_MPU_CACHEP_NOCACHE 0U
160 |
161 | /**
162 | * MPU Memory Access Attribute write-back, write and read allocate policy.
163 | */
164 | #define ARM_MPU_CACHEP_WB_WRA 1U
165 |
166 | /**
167 | * MPU Memory Access Attribute write-through, no write allocate policy.
168 | */
169 | #define ARM_MPU_CACHEP_WT_NWA 2U
170 |
171 | /**
172 | * MPU Memory Access Attribute write-back, no write allocate policy.
173 | */
174 | #define ARM_MPU_CACHEP_WB_NWA 3U
175 |
176 |
177 | /**
178 | * Struct for a single MPU Region
179 | */
180 | typedef struct {
181 | uint32_t RBAR; //!< The region base address register value (RBAR)
182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
183 | } ARM_MPU_Region_t;
184 |
185 | /** Enable the MPU.
186 | * \param MPU_Control Default access permissions for unconfigured regions.
187 | */
188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
189 | {
190 | __DSB();
191 | __ISB();
192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
195 | #endif
196 | }
197 |
198 | /** Disable the MPU.
199 | */
200 | __STATIC_INLINE void ARM_MPU_Disable(void)
201 | {
202 | __DSB();
203 | __ISB();
204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
206 | #endif
207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
208 | }
209 |
210 | /** Clear and disable the given MPU region.
211 | * \param rnr Region number to be cleared.
212 | */
213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
214 | {
215 | MPU->RNR = rnr;
216 | MPU->RASR = 0U;
217 | }
218 |
219 | /** Configure an MPU region.
220 | * \param rbar Value for RBAR register.
221 | * \param rsar Value for RSAR register.
222 | */
223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
224 | {
225 | MPU->RBAR = rbar;
226 | MPU->RASR = rasr;
227 | }
228 |
229 | /** Configure the given MPU region.
230 | * \param rnr Region number to be configured.
231 | * \param rbar Value for RBAR register.
232 | * \param rsar Value for RSAR register.
233 | */
234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
235 | {
236 | MPU->RNR = rnr;
237 | MPU->RBAR = rbar;
238 | MPU->RASR = rasr;
239 | }
240 |
241 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
242 | * \param dst Destination data is copied to.
243 | * \param src Source data is copied from.
244 | * \param len Amount of data words to be copied.
245 | */
246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
247 | {
248 | uint32_t i;
249 | for (i = 0U; i < len; ++i)
250 | {
251 | dst[i] = src[i];
252 | }
253 | }
254 |
255 | /** Load the given number of MPU regions from a table.
256 | * \param table Pointer to the MPU configuration table.
257 | * \param cnt Amount of regions to be configured.
258 | */
259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
260 | {
261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
262 | while (cnt > MPU_TYPE_RALIASES) {
263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
264 | table += MPU_TYPE_RALIASES;
265 | cnt -= MPU_TYPE_RALIASES;
266 | }
267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
268 | }
269 |
270 | #endif
271 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Include/mpu_armv8.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file mpu_armv8.h
3 | * @brief CMSIS MPU API for Armv8-M MPU
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef ARM_MPU_ARMV8_H
32 | #define ARM_MPU_ARMV8_H
33 |
34 | /** \brief Attribute for device memory (outer only) */
35 | #define ARM_MPU_ATTR_DEVICE ( 0U )
36 |
37 | /** \brief Attribute for non-cacheable, normal memory */
38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
39 |
40 | /** \brief Attribute for normal memory (outer and inner)
41 | * \param NT Non-Transient: Set to 1 for non-transient data.
42 | * \param WB Write-Back: Set to 1 to use write-back update policy.
43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
45 | */
46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
48 |
49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
51 |
52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
54 |
55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
57 |
58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U)
60 |
61 | /** \brief Memory Attribute
62 | * \param O Outer memory attributes
63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
64 | */
65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
66 |
67 | /** \brief Normal memory non-shareable */
68 | #define ARM_MPU_SH_NON (0U)
69 |
70 | /** \brief Normal memory outer shareable */
71 | #define ARM_MPU_SH_OUTER (2U)
72 |
73 | /** \brief Normal memory inner shareable */
74 | #define ARM_MPU_SH_INNER (3U)
75 |
76 | /** \brief Memory access permissions
77 | * \param RO Read-Only: Set to 1 for read-only memory.
78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory.
79 | */
80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
81 |
82 | /** \brief Region Base Address Register value
83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
84 | * \param SH Defines the Shareability domain for this memory region.
85 | * \param RO Read-Only: Set to 1 for a read-only memory region.
86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
88 | */
89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
90 | ((BASE & MPU_RBAR_BASE_Msk) | \
91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
94 |
95 | /** \brief Region Limit Address Register value
96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
97 | * \param IDX The attribute index to be associated with this memory region.
98 | */
99 | #define ARM_MPU_RLAR(LIMIT, IDX) \
100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
102 | (MPU_RLAR_EN_Msk))
103 |
104 | /**
105 | * Struct for a single MPU Region
106 | */
107 | typedef struct {
108 | uint32_t RBAR; /*!< Region Base Address Register value */
109 | uint32_t RLAR; /*!< Region Limit Address Register value */
110 | } ARM_MPU_Region_t;
111 |
112 | /** Enable the MPU.
113 | * \param MPU_Control Default access permissions for unconfigured regions.
114 | */
115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
116 | {
117 | __DSB();
118 | __ISB();
119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
122 | #endif
123 | }
124 |
125 | /** Disable the MPU.
126 | */
127 | __STATIC_INLINE void ARM_MPU_Disable(void)
128 | {
129 | __DSB();
130 | __ISB();
131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
133 | #endif
134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
135 | }
136 |
137 | #ifdef MPU_NS
138 | /** Enable the Non-secure MPU.
139 | * \param MPU_Control Default access permissions for unconfigured regions.
140 | */
141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
142 | {
143 | __DSB();
144 | __ISB();
145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
148 | #endif
149 | }
150 |
151 | /** Disable the Non-secure MPU.
152 | */
153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void)
154 | {
155 | __DSB();
156 | __ISB();
157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
159 | #endif
160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
161 | }
162 | #endif
163 |
164 | /** Set the memory attribute encoding to the given MPU.
165 | * \param mpu Pointer to the MPU to be configured.
166 | * \param idx The attribute index to be set [0-7]
167 | * \param attr The attribute value to be set.
168 | */
169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
170 | {
171 | const uint8_t reg = idx / 4U;
172 | const uint32_t pos = ((idx % 4U) * 8U);
173 | const uint32_t mask = 0xFFU << pos;
174 |
175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
176 | return; // invalid index
177 | }
178 |
179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
180 | }
181 |
182 | /** Set the memory attribute encoding.
183 | * \param idx The attribute index to be set [0-7]
184 | * \param attr The attribute value to be set.
185 | */
186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
187 | {
188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr);
189 | }
190 |
191 | #ifdef MPU_NS
192 | /** Set the memory attribute encoding to the Non-secure MPU.
193 | * \param idx The attribute index to be set [0-7]
194 | * \param attr The attribute value to be set.
195 | */
196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
197 | {
198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
199 | }
200 | #endif
201 |
202 | /** Clear and disable the given MPU region of the given MPU.
203 | * \param mpu Pointer to MPU to be used.
204 | * \param rnr Region number to be cleared.
205 | */
206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
207 | {
208 | mpu->RNR = rnr;
209 | mpu->RLAR = 0U;
210 | }
211 |
212 | /** Clear and disable the given MPU region.
213 | * \param rnr Region number to be cleared.
214 | */
215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
216 | {
217 | ARM_MPU_ClrRegionEx(MPU, rnr);
218 | }
219 |
220 | #ifdef MPU_NS
221 | /** Clear and disable the given Non-secure MPU region.
222 | * \param rnr Region number to be cleared.
223 | */
224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
225 | {
226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr);
227 | }
228 | #endif
229 |
230 | /** Configure the given MPU region of the given MPU.
231 | * \param mpu Pointer to MPU to be used.
232 | * \param rnr Region number to be configured.
233 | * \param rbar Value for RBAR register.
234 | * \param rlar Value for RLAR register.
235 | */
236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
237 | {
238 | mpu->RNR = rnr;
239 | mpu->RBAR = rbar;
240 | mpu->RLAR = rlar;
241 | }
242 |
243 | /** Configure the given MPU region.
244 | * \param rnr Region number to be configured.
245 | * \param rbar Value for RBAR register.
246 | * \param rlar Value for RLAR register.
247 | */
248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
249 | {
250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
251 | }
252 |
253 | #ifdef MPU_NS
254 | /** Configure the given Non-secure MPU region.
255 | * \param rnr Region number to be configured.
256 | * \param rbar Value for RBAR register.
257 | * \param rlar Value for RLAR register.
258 | */
259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
260 | {
261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
262 | }
263 | #endif
264 |
265 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
266 | * \param dst Destination data is copied to.
267 | * \param src Source data is copied from.
268 | * \param len Amount of data words to be copied.
269 | */
270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
271 | {
272 | uint32_t i;
273 | for (i = 0U; i < len; ++i)
274 | {
275 | dst[i] = src[i];
276 | }
277 | }
278 |
279 | /** Load the given number of MPU regions from a table to the given MPU.
280 | * \param mpu Pointer to the MPU registers to be used.
281 | * \param rnr First region number to be configured.
282 | * \param table Pointer to the MPU configuration table.
283 | * \param cnt Amount of regions to be configured.
284 | */
285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
286 | {
287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
288 | if (cnt == 1U) {
289 | mpu->RNR = rnr;
290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
291 | } else {
292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
294 |
295 | mpu->RNR = rnrBase;
296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
299 | table += c;
300 | cnt -= c;
301 | rnrOffset = 0U;
302 | rnrBase += MPU_TYPE_RALIASES;
303 | mpu->RNR = rnrBase;
304 | }
305 |
306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
307 | }
308 | }
309 |
310 | /** Load the given number of MPU regions from a table.
311 | * \param rnr First region number to be configured.
312 | * \param table Pointer to the MPU configuration table.
313 | * \param cnt Amount of regions to be configured.
314 | */
315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
316 | {
317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt);
318 | }
319 |
320 | #ifdef MPU_NS
321 | /** Load the given number of MPU regions from a table to the Non-secure MPU.
322 | * \param rnr First region number to be configured.
323 | * \param table Pointer to the MPU configuration table.
324 | * \param cnt Amount of regions to be configured.
325 | */
326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
327 | {
328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
329 | }
330 | #endif
331 |
332 | #endif
333 |
334 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Include/tz_context.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file tz_context.h
3 | * @brief Context Management for Armv8-M TrustZone
4 | * @version V1.0.1
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef TZ_CONTEXT_H
32 | #define TZ_CONTEXT_H
33 |
34 | #include
35 |
36 | #ifndef TZ_MODULEID_T
37 | #define TZ_MODULEID_T
38 | /// \details Data type that identifies secure software modules called by a process.
39 | typedef uint32_t TZ_ModuleId_t;
40 | #endif
41 |
42 | /// \details TZ Memory ID identifies an allocated memory slot.
43 | typedef uint32_t TZ_MemoryId_t;
44 |
45 | /// Initialize secure context memory system
46 | /// \return execution status (1: success, 0: error)
47 | uint32_t TZ_InitContextSystem_S (void);
48 |
49 | /// Allocate context memory for calling secure software modules in TrustZone
50 | /// \param[in] module identifies software modules called from non-secure mode
51 | /// \return value != 0 id TrustZone memory slot identifier
52 | /// \return value 0 no memory available or internal error
53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
54 |
55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
56 | /// \param[in] id TrustZone memory slot identifier
57 | /// \return execution status (1: success, 0: error)
58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
59 |
60 | /// Load secure context (called on RTOS thread context switch)
61 | /// \param[in] id TrustZone memory slot identifier
62 | /// \return execution status (1: success, 0: error)
63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
64 |
65 | /// Store secure context (called on RTOS thread context switch)
66 | /// \param[in] id TrustZone memory slot identifier
67 | /// \return execution status (1: success, 0: error)
68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
69 |
70 | #endif // TZ_CONTEXT_H
71 |
--------------------------------------------------------------------------------
/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal.h
4 | * @author MCD Application Team
5 | * @brief This file contains all the functions prototypes for the HAL
6 | * module driver.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2017 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F4xx_HAL_H
23 | #define __STM32F4xx_HAL_H
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Includes ------------------------------------------------------------------*/
30 | #include "stm32f4xx_hal_conf.h"
31 |
32 | /** @addtogroup STM32F4xx_HAL_Driver
33 | * @{
34 | */
35 |
36 | /** @addtogroup HAL
37 | * @{
38 | */
39 |
40 | /* Exported types ------------------------------------------------------------*/
41 | /* Exported constants --------------------------------------------------------*/
42 |
43 | /** @defgroup HAL_Exported_Constants HAL Exported Constants
44 | * @{
45 | */
46 |
47 | /** @defgroup HAL_TICK_FREQ Tick Frequency
48 | * @{
49 | */
50 | typedef enum
51 | {
52 | HAL_TICK_FREQ_10HZ = 100U,
53 | HAL_TICK_FREQ_100HZ = 10U,
54 | HAL_TICK_FREQ_1KHZ = 1U,
55 | HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
56 | } HAL_TickFreqTypeDef;
57 | /**
58 | * @}
59 | */
60 |
61 | /**
62 | * @}
63 | */
64 |
65 | /* Exported macro ------------------------------------------------------------*/
66 | /** @defgroup HAL_Exported_Macros HAL Exported Macros
67 | * @{
68 | */
69 |
70 | /** @brief Freeze/Unfreeze Peripherals in Debug mode
71 | */
72 | #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
73 | #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
74 | #define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
75 | #define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
76 | #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
77 | #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
78 | #define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
79 | #define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
80 | #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
81 | #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
82 | #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
83 | #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
84 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
85 | #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
86 | #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
87 | #define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
88 | #define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
89 | #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
90 | #define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
91 | #define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
92 | #define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
93 | #define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
94 |
95 | #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
96 | #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
97 | #define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
98 | #define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
99 | #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
100 | #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
101 | #define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
102 | #define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
103 | #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
104 | #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
105 | #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
106 | #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
107 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
108 | #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
109 | #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
110 | #define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
111 | #define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
112 | #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
113 | #define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
114 | #define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
115 | #define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
116 | #define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
117 |
118 | /** @brief Main Flash memory mapped at 0x00000000
119 | */
120 | #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
121 |
122 | /** @brief System Flash memory mapped at 0x00000000
123 | */
124 | #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
125 | SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
126 | }while(0);
127 |
128 | /** @brief Embedded SRAM mapped at 0x00000000
129 | */
130 | #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
131 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
132 | }while(0);
133 |
134 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
135 | /** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
136 | */
137 | #define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
138 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
139 | }while(0);
140 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
141 |
142 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
143 | defined(STM32F469xx) || defined(STM32F479xx)
144 | /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
145 | */
146 | #define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
147 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
148 | }while(0);
149 |
150 | /** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
151 | */
152 | #define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
153 | SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
154 | }while(0);
155 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
156 |
157 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
158 | /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
159 | * @{
160 | */
161 | /** @brief SYSCFG Break Lockup lock
162 | * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input
163 | * @note The selected configuration is locked and can be unlocked by system reset
164 | */
165 | #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
166 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
167 | }while(0)
168 | /**
169 | * @}
170 | */
171 |
172 | /** @defgroup PVD_Lock_Enable PVD Lock
173 | * @{
174 | */
175 | /** @brief SYSCFG Break PVD lock
176 | * Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
177 | * @note The selected configuration is locked and can be unlocked by system reset
178 | */
179 | #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
180 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
181 | }while(0)
182 | /**
183 | * @}
184 | */
185 | #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
186 | /**
187 | * @}
188 | */
189 |
190 | /** @defgroup HAL_Private_Macros HAL Private Macros
191 | * @{
192 | */
193 | #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
194 | ((FREQ) == HAL_TICK_FREQ_100HZ) || \
195 | ((FREQ) == HAL_TICK_FREQ_1KHZ))
196 | /**
197 | * @}
198 | */
199 |
200 | /* Exported variables --------------------------------------------------------*/
201 |
202 | /** @addtogroup HAL_Exported_Variables
203 | * @{
204 | */
205 | extern __IO uint32_t uwTick;
206 | extern uint32_t uwTickPrio;
207 | extern HAL_TickFreqTypeDef uwTickFreq;
208 | /**
209 | * @}
210 | */
211 |
212 | /* Exported functions --------------------------------------------------------*/
213 | /** @addtogroup HAL_Exported_Functions
214 | * @{
215 | */
216 | /** @addtogroup HAL_Exported_Functions_Group1
217 | * @{
218 | */
219 | /* Initialization and Configuration functions ******************************/
220 | HAL_StatusTypeDef HAL_Init(void);
221 | HAL_StatusTypeDef HAL_DeInit(void);
222 | void HAL_MspInit(void);
223 | void HAL_MspDeInit(void);
224 | HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
225 | /**
226 | * @}
227 | */
228 |
229 | /** @addtogroup HAL_Exported_Functions_Group2
230 | * @{
231 | */
232 | /* Peripheral Control functions ************************************************/
233 | void HAL_IncTick(void);
234 | void HAL_Delay(uint32_t Delay);
235 | uint32_t HAL_GetTick(void);
236 | uint32_t HAL_GetTickPrio(void);
237 | HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
238 | HAL_TickFreqTypeDef HAL_GetTickFreq(void);
239 | void HAL_SuspendTick(void);
240 | void HAL_ResumeTick(void);
241 | uint32_t HAL_GetHalVersion(void);
242 | uint32_t HAL_GetREVID(void);
243 | uint32_t HAL_GetDEVID(void);
244 | void HAL_DBGMCU_EnableDBGSleepMode(void);
245 | void HAL_DBGMCU_DisableDBGSleepMode(void);
246 | void HAL_DBGMCU_EnableDBGStopMode(void);
247 | void HAL_DBGMCU_DisableDBGStopMode(void);
248 | void HAL_DBGMCU_EnableDBGStandbyMode(void);
249 | void HAL_DBGMCU_DisableDBGStandbyMode(void);
250 | void HAL_EnableCompensationCell(void);
251 | void HAL_DisableCompensationCell(void);
252 | uint32_t HAL_GetUIDw0(void);
253 | uint32_t HAL_GetUIDw1(void);
254 | uint32_t HAL_GetUIDw2(void);
255 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
256 | defined(STM32F469xx) || defined(STM32F479xx)
257 | void HAL_EnableMemorySwappingBank(void);
258 | void HAL_DisableMemorySwappingBank(void);
259 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
260 | /**
261 | * @}
262 | */
263 |
264 | /**
265 | * @}
266 | */
267 | /* Private types -------------------------------------------------------------*/
268 | /* Private variables ---------------------------------------------------------*/
269 | /** @defgroup HAL_Private_Variables HAL Private Variables
270 | * @{
271 | */
272 | /**
273 | * @}
274 | */
275 | /* Private constants ---------------------------------------------------------*/
276 | /** @defgroup HAL_Private_Constants HAL Private Constants
277 | * @{
278 | */
279 | /**
280 | * @}
281 | */
282 | /* Private macros ------------------------------------------------------------*/
283 | /* Private functions ---------------------------------------------------------*/
284 | /**
285 | * @}
286 | */
287 |
288 | /**
289 | * @}
290 | */
291 |
292 | #ifdef __cplusplus
293 | }
294 | #endif
295 |
296 | #endif /* __STM32F4xx_HAL_H */
297 |
298 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
299 |
--------------------------------------------------------------------------------
/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_def.h
4 | * @author MCD Application Team
5 | * @brief This file contains HAL common defines, enumeration, macros and
6 | * structures definitions.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2017 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F4xx_HAL_DEF
23 | #define __STM32F4xx_HAL_DEF
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Includes ------------------------------------------------------------------*/
30 | #include "stm32f4xx.h"
31 | #include "Legacy/stm32_hal_legacy.h"
32 | #include
33 |
34 | /* Exported types ------------------------------------------------------------*/
35 |
36 | /**
37 | * @brief HAL Status structures definition
38 | */
39 | typedef enum
40 | {
41 | HAL_OK = 0x00U,
42 | HAL_ERROR = 0x01U,
43 | HAL_BUSY = 0x02U,
44 | HAL_TIMEOUT = 0x03U
45 | } HAL_StatusTypeDef;
46 |
47 | /**
48 | * @brief HAL Lock structures definition
49 | */
50 | typedef enum
51 | {
52 | HAL_UNLOCKED = 0x00U,
53 | HAL_LOCKED = 0x01U
54 | } HAL_LockTypeDef;
55 |
56 | /* Exported macro ------------------------------------------------------------*/
57 |
58 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
59 |
60 | #define HAL_MAX_DELAY 0xFFFFFFFFU
61 |
62 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
63 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
64 |
65 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
66 | do{ \
67 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
68 | (__DMA_HANDLE__).Parent = (__HANDLE__); \
69 | } while(0U)
70 |
71 | /** @brief Reset the Handle's State field.
72 | * @param __HANDLE__ specifies the Peripheral Handle.
73 | * @note This macro can be used for the following purpose:
74 | * - When the Handle is declared as local variable; before passing it as parameter
75 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
76 | * to set to 0 the Handle's "State" field.
77 | * Otherwise, "State" field may have any random value and the first time the function
78 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed
79 | * (i.e. HAL_PPP_MspInit() will not be executed).
80 | * - When there is a need to reconfigure the low level hardware: instead of calling
81 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
82 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function
83 | * HAL_PPP_MspInit() which will reconfigure the low level hardware.
84 | * @retval None
85 | */
86 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
87 |
88 | #if (USE_RTOS == 1U)
89 | /* Reserved for future use */
90 | #error "USE_RTOS should be 0 in the current HAL release"
91 | #else
92 | #define __HAL_LOCK(__HANDLE__) \
93 | do{ \
94 | if((__HANDLE__)->Lock == HAL_LOCKED) \
95 | { \
96 | return HAL_BUSY; \
97 | } \
98 | else \
99 | { \
100 | (__HANDLE__)->Lock = HAL_LOCKED; \
101 | } \
102 | }while (0U)
103 |
104 | #define __HAL_UNLOCK(__HANDLE__) \
105 | do{ \
106 | (__HANDLE__)->Lock = HAL_UNLOCKED; \
107 | }while (0U)
108 | #endif /* USE_RTOS */
109 |
110 | #if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
111 | #ifndef __weak
112 | #define __weak __attribute__((weak))
113 | #endif /* __weak */
114 | #ifndef __packed
115 | #define __packed __attribute__((__packed__))
116 | #endif /* __packed */
117 | #endif /* __GNUC__ */
118 |
119 |
120 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
121 | #if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
122 | #ifndef __ALIGN_END
123 | #define __ALIGN_END __attribute__ ((aligned (4)))
124 | #endif /* __ALIGN_END */
125 | #ifndef __ALIGN_BEGIN
126 | #define __ALIGN_BEGIN
127 | #endif /* __ALIGN_BEGIN */
128 | #else
129 | #ifndef __ALIGN_END
130 | #define __ALIGN_END
131 | #endif /* __ALIGN_END */
132 | #ifndef __ALIGN_BEGIN
133 | #if defined (__CC_ARM) /* ARM Compiler */
134 | #define __ALIGN_BEGIN __align(4)
135 | #elif defined (__ICCARM__) /* IAR Compiler */
136 | #define __ALIGN_BEGIN
137 | #endif /* __CC_ARM */
138 | #endif /* __ALIGN_BEGIN */
139 | #endif /* __GNUC__ */
140 |
141 |
142 | /**
143 | * @brief __RAM_FUNC definition
144 | */
145 | #if defined ( __CC_ARM )
146 | /* ARM Compiler
147 | ------------
148 | RAM functions are defined using the toolchain options.
149 | Functions that are executed in RAM should reside in a separate source module.
150 | Using the 'Options for File' dialog you can simply change the 'Code / Const'
151 | area of a module to a memory space in physical RAM.
152 | Available memory areas are declared in the 'Target' tab of the 'Options for Target'
153 | dialog.
154 | */
155 | #define __RAM_FUNC
156 |
157 | #elif defined ( __ICCARM__ )
158 | /* ICCARM Compiler
159 | ---------------
160 | RAM functions are defined using a specific toolchain keyword "__ramfunc".
161 | */
162 | #define __RAM_FUNC __ramfunc
163 |
164 | #elif defined ( __GNUC__ )
165 | /* GNU Compiler
166 | ------------
167 | RAM functions are defined using a specific toolchain attribute
168 | "__attribute__((section(".RamFunc")))".
169 | */
170 | #define __RAM_FUNC __attribute__((section(".RamFunc")))
171 |
172 | #endif
173 |
174 | /**
175 | * @brief __NOINLINE definition
176 | */
177 | #if defined ( __CC_ARM ) || defined ( __GNUC__ )
178 | /* ARM & GNUCompiler
179 | ----------------
180 | */
181 | #define __NOINLINE __attribute__ ( (noinline) )
182 |
183 | #elif defined ( __ICCARM__ )
184 | /* ICCARM Compiler
185 | ---------------
186 | */
187 | #define __NOINLINE _Pragma("optimize = no_inline")
188 |
189 | #endif
190 |
191 | #ifdef __cplusplus
192 | }
193 | #endif
194 |
195 | #endif /* ___STM32F4xx_HAL_DEF */
196 |
197 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
198 |
--------------------------------------------------------------------------------
/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_dma_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of DMA HAL extension module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_HAL_DMA_EX_H
22 | #define __STM32F4xx_HAL_DMA_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup DMAEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /** @defgroup DMAEx_Exported_Types DMAEx Exported Types
41 | * @brief DMAEx Exported types
42 | * @{
43 | */
44 |
45 | /**
46 | * @brief HAL DMA Memory definition
47 | */
48 | typedef enum
49 | {
50 | MEMORY0 = 0x00U, /*!< Memory 0 */
51 | MEMORY1 = 0x01U /*!< Memory 1 */
52 | }HAL_DMA_MemoryTypeDef;
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /* Exported functions --------------------------------------------------------*/
59 | /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
60 | * @brief DMAEx Exported functions
61 | * @{
62 | */
63 |
64 | /** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
65 | * @brief Extended features functions
66 | * @{
67 | */
68 |
69 | /* IO operation functions *******************************************************/
70 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
71 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
72 | HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
73 |
74 | /**
75 | * @}
76 | */
77 | /**
78 | * @}
79 | */
80 |
81 | /* Private functions ---------------------------------------------------------*/
82 | /** @defgroup DMAEx_Private_Functions DMAEx Private Functions
83 | * @brief DMAEx Private functions
84 | * @{
85 | */
86 | /**
87 | * @}
88 | */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | #ifdef __cplusplus
99 | }
100 | #endif
101 |
102 | #endif /*__STM32F4xx_HAL_DMA_EX_H*/
103 |
104 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
105 |
--------------------------------------------------------------------------------
/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_exti.h
4 | * @author MCD Application Team
5 | * @brief Header file of EXTI HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32f4xx_HAL_EXTI_H
22 | #define STM32f4xx_HAL_EXTI_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @defgroup EXTI EXTI
36 | * @brief EXTI HAL module driver
37 | * @{
38 | */
39 |
40 | /* Exported types ------------------------------------------------------------*/
41 |
42 | /** @defgroup EXTI_Exported_Types EXTI Exported Types
43 | * @{
44 | */
45 | typedef enum
46 | {
47 | HAL_EXTI_COMMON_CB_ID = 0x00U
48 | } EXTI_CallbackIDTypeDef;
49 |
50 | /**
51 | * @brief EXTI Handle structure definition
52 | */
53 | typedef struct
54 | {
55 | uint32_t Line; /*!< Exti line number */
56 | void (* PendingCallback)(void); /*!< Exti pending callback */
57 | } EXTI_HandleTypeDef;
58 |
59 | /**
60 | * @brief EXTI Configuration structure definition
61 | */
62 | typedef struct
63 | {
64 | uint32_t Line; /*!< The Exti line to be configured. This parameter
65 | can be a value of @ref EXTI_Line */
66 | uint32_t Mode; /*!< The Exit Mode to be configured for a core.
67 | This parameter can be a combination of @ref EXTI_Mode */
68 | uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
69 | can be a value of @ref EXTI_Trigger */
70 | uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
71 | This parameter is only possible for line 0 to 15. It
72 | can be a value of @ref EXTI_GPIOSel */
73 | } EXTI_ConfigTypeDef;
74 |
75 | /**
76 | * @}
77 | */
78 |
79 | /* Exported constants --------------------------------------------------------*/
80 | /** @defgroup EXTI_Exported_Constants EXTI Exported Constants
81 | * @{
82 | */
83 |
84 | /** @defgroup EXTI_Line EXTI Line
85 | * @{
86 | */
87 | #define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
88 | #define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
89 | #define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
90 | #define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
91 | #define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
92 | #define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
93 | #define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
94 | #define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
95 | #define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
96 | #define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
97 | #define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
98 | #define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
99 | #define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
100 | #define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
101 | #define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
102 | #define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
103 | #define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
104 | #define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
105 | #if defined(EXTI_IMR_IM18)
106 | #define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
107 | #else
108 | #define EXTI_LINE_18 (EXTI_RESERVED | 0x12u) /*!< No interrupt supported in this line */
109 | #endif /* EXTI_IMR_IM18 */
110 | #if defined(EXTI_IMR_IM19)
111 | #define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
112 | #else
113 | #define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */
114 | #endif /* EXTI_IMR_IM19 */
115 | #if defined(EXTI_IMR_IM20)
116 | #define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
117 | #else
118 | #define EXTI_LINE_20 (EXTI_RESERVED | 0x14u) /*!< No interrupt supported in this line */
119 | #endif /* EXTI_IMR_IM20 */
120 | #define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
121 | #define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
122 | #if defined(EXTI_IMR_IM23)
123 | #define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */
124 | #endif /* EXTI_IMR_IM23 */
125 |
126 | /**
127 | * @}
128 | */
129 |
130 | /** @defgroup EXTI_Mode EXTI Mode
131 | * @{
132 | */
133 | #define EXTI_MODE_NONE 0x00000000u
134 | #define EXTI_MODE_INTERRUPT 0x00000001u
135 | #define EXTI_MODE_EVENT 0x00000002u
136 | /**
137 | * @}
138 | */
139 |
140 | /** @defgroup EXTI_Trigger EXTI Trigger
141 | * @{
142 | */
143 |
144 | #define EXTI_TRIGGER_NONE 0x00000000u
145 | #define EXTI_TRIGGER_RISING 0x00000001u
146 | #define EXTI_TRIGGER_FALLING 0x00000002u
147 | #define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
148 | /**
149 | * @}
150 | */
151 |
152 | /** @defgroup EXTI_GPIOSel EXTI GPIOSel
153 | * @brief
154 | * @{
155 | */
156 | #define EXTI_GPIOA 0x00000000u
157 | #define EXTI_GPIOB 0x00000001u
158 | #define EXTI_GPIOC 0x00000002u
159 | #if defined (GPIOD)
160 | #define EXTI_GPIOD 0x00000003u
161 | #endif /* GPIOD */
162 | #if defined (GPIOE)
163 | #define EXTI_GPIOE 0x00000004u
164 | #endif /* GPIOE */
165 | #if defined (GPIOF)
166 | #define EXTI_GPIOF 0x00000005u
167 | #endif /* GPIOF */
168 | #if defined (GPIOG)
169 | #define EXTI_GPIOG 0x00000006u
170 | #endif /* GPIOG */
171 | #if defined (GPIOH)
172 | #define EXTI_GPIOH 0x00000007u
173 | #endif /* GPIOH */
174 | #if defined (GPIOI)
175 | #define EXTI_GPIOI 0x00000008u
176 | #endif /* GPIOI */
177 | #if defined (GPIOJ)
178 | #define EXTI_GPIOJ 0x00000009u
179 | #endif /* GPIOJ */
180 | #if defined (GPIOK)
181 | #define EXTI_GPIOK 0x0000000Au
182 | #endif /* GPIOK */
183 |
184 | /**
185 | * @}
186 | */
187 |
188 | /**
189 | * @}
190 | */
191 |
192 | /* Exported macro ------------------------------------------------------------*/
193 | /** @defgroup EXTI_Exported_Macros EXTI Exported Macros
194 | * @{
195 | */
196 |
197 | /**
198 | * @}
199 | */
200 |
201 | /* Private constants --------------------------------------------------------*/
202 | /** @defgroup EXTI_Private_Constants EXTI Private Constants
203 | * @{
204 | */
205 | /**
206 | * @brief EXTI Line property definition
207 | */
208 | #define EXTI_PROPERTY_SHIFT 24u
209 | #define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
210 | #define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
211 | #define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
212 | #define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
213 |
214 | /**
215 | * @brief EXTI bit usage
216 | */
217 | #define EXTI_PIN_MASK 0x0000001Fu
218 |
219 | /**
220 | * @brief EXTI Mask for interrupt & event mode
221 | */
222 | #define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
223 |
224 | /**
225 | * @brief EXTI Mask for trigger possibilities
226 | */
227 | #define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
228 |
229 | /**
230 | * @brief EXTI Line number
231 | */
232 | #if defined(EXTI_IMR_IM23)
233 | #define EXTI_LINE_NB 24UL
234 | #else
235 | #define EXTI_LINE_NB 23UL
236 | #endif /* EXTI_IMR_IM23 */
237 |
238 | /**
239 | * @}
240 | */
241 |
242 | /* Private macros ------------------------------------------------------------*/
243 | /** @defgroup EXTI_Private_Macros EXTI Private Macros
244 | * @{
245 | */
246 | #define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
247 | ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
248 | (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
249 | (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
250 |
251 | #define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
252 | (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
253 |
254 | #define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
255 |
256 | #define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
257 |
258 | #define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
259 |
260 | #if !defined (GPIOD)
261 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
262 | ((__PORT__) == EXTI_GPIOB) || \
263 | ((__PORT__) == EXTI_GPIOC) || \
264 | ((__PORT__) == EXTI_GPIOH))
265 | #elif !defined (GPIOE)
266 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
267 | ((__PORT__) == EXTI_GPIOB) || \
268 | ((__PORT__) == EXTI_GPIOC) || \
269 | ((__PORT__) == EXTI_GPIOD) || \
270 | ((__PORT__) == EXTI_GPIOH))
271 | #elif !defined (GPIOF)
272 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
273 | ((__PORT__) == EXTI_GPIOB) || \
274 | ((__PORT__) == EXTI_GPIOC) || \
275 | ((__PORT__) == EXTI_GPIOD) || \
276 | ((__PORT__) == EXTI_GPIOE) || \
277 | ((__PORT__) == EXTI_GPIOH))
278 | #elif !defined (GPIOI)
279 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
280 | ((__PORT__) == EXTI_GPIOB) || \
281 | ((__PORT__) == EXTI_GPIOC) || \
282 | ((__PORT__) == EXTI_GPIOD) || \
283 | ((__PORT__) == EXTI_GPIOE) || \
284 | ((__PORT__) == EXTI_GPIOF) || \
285 | ((__PORT__) == EXTI_GPIOG) || \
286 | ((__PORT__) == EXTI_GPIOH))
287 | #elif !defined (GPIOJ)
288 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
289 | ((__PORT__) == EXTI_GPIOB) || \
290 | ((__PORT__) == EXTI_GPIOC) || \
291 | ((__PORT__) == EXTI_GPIOD) || \
292 | ((__PORT__) == EXTI_GPIOE) || \
293 | ((__PORT__) == EXTI_GPIOF) || \
294 | ((__PORT__) == EXTI_GPIOG) || \
295 | ((__PORT__) == EXTI_GPIOH) || \
296 | ((__PORT__) == EXTI_GPIOI))
297 | #else
298 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
299 | ((__PORT__) == EXTI_GPIOB) || \
300 | ((__PORT__) == EXTI_GPIOC) || \
301 | ((__PORT__) == EXTI_GPIOD) || \
302 | ((__PORT__) == EXTI_GPIOE) || \
303 | ((__PORT__) == EXTI_GPIOF) || \
304 | ((__PORT__) == EXTI_GPIOG) || \
305 | ((__PORT__) == EXTI_GPIOH) || \
306 | ((__PORT__) == EXTI_GPIOI) || \
307 | ((__PORT__) == EXTI_GPIOJ) || \
308 | ((__PORT__) == EXTI_GPIOK))
309 | #endif /* GPIOD */
310 |
311 | #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
312 | /**
313 | * @}
314 | */
315 |
316 | /* Exported functions --------------------------------------------------------*/
317 | /** @defgroup EXTI_Exported_Functions EXTI Exported Functions
318 | * @brief EXTI Exported Functions
319 | * @{
320 | */
321 |
322 | /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
323 | * @brief Configuration functions
324 | * @{
325 | */
326 | /* Configuration functions ****************************************************/
327 | HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
328 | HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
329 | HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
330 | HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
331 | HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
332 | /**
333 | * @}
334 | */
335 |
336 | /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
337 | * @brief IO operation functions
338 | * @{
339 | */
340 | /* IO operation functions *****************************************************/
341 | void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
342 | uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
343 | void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
344 | void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
345 |
346 | /**
347 | * @}
348 | */
349 |
350 | /**
351 | * @}
352 | */
353 |
354 | /**
355 | * @}
356 | */
357 |
358 | /**
359 | * @}
360 | */
361 |
362 | #ifdef __cplusplus
363 | }
364 | #endif
365 |
366 | #endif /* STM32f4xx_HAL_EXTI_H */
367 |
368 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
369 |
--------------------------------------------------------------------------------
/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_flash.h
4 | * @author MCD Application Team
5 | * @brief Header file of FLASH HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_HAL_FLASH_H
22 | #define __STM32F4xx_HAL_FLASH_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup FLASH
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /** @defgroup FLASH_Exported_Types FLASH Exported Types
41 | * @{
42 | */
43 |
44 | /**
45 | * @brief FLASH Procedure structure definition
46 | */
47 | typedef enum
48 | {
49 | FLASH_PROC_NONE = 0U,
50 | FLASH_PROC_SECTERASE,
51 | FLASH_PROC_MASSERASE,
52 | FLASH_PROC_PROGRAM
53 | } FLASH_ProcedureTypeDef;
54 |
55 | /**
56 | * @brief FLASH handle Structure definition
57 | */
58 | typedef struct
59 | {
60 | __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/
61 |
62 | __IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to erase in IT context*/
63 |
64 | __IO uint8_t VoltageForErase; /*Internal variable to provide voltage range selected by user in IT context*/
65 |
66 | __IO uint32_t Sector; /*Internal variable to define the current sector which is erasing*/
67 |
68 | __IO uint32_t Bank; /*Internal variable to save current bank selected during mass erase*/
69 |
70 | __IO uint32_t Address; /*Internal variable to save address selected for program*/
71 |
72 | HAL_LockTypeDef Lock; /* FLASH locking object */
73 |
74 | __IO uint32_t ErrorCode; /* FLASH error code */
75 |
76 | }FLASH_ProcessTypeDef;
77 |
78 | /**
79 | * @}
80 | */
81 |
82 | /* Exported constants --------------------------------------------------------*/
83 | /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
84 | * @{
85 | */
86 | /** @defgroup FLASH_Error_Code FLASH Error Code
87 | * @brief FLASH Error Code
88 | * @{
89 | */
90 | #define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */
91 | #define HAL_FLASH_ERROR_RD 0x00000001U /*!< Read Protection error */
92 | #define HAL_FLASH_ERROR_PGS 0x00000002U /*!< Programming Sequence error */
93 | #define HAL_FLASH_ERROR_PGP 0x00000004U /*!< Programming Parallelism error */
94 | #define HAL_FLASH_ERROR_PGA 0x00000008U /*!< Programming Alignment error */
95 | #define HAL_FLASH_ERROR_WRP 0x00000010U /*!< Write protection error */
96 | #define HAL_FLASH_ERROR_OPERATION 0x00000020U /*!< Operation Error */
97 | /**
98 | * @}
99 | */
100 |
101 | /** @defgroup FLASH_Type_Program FLASH Type Program
102 | * @{
103 | */
104 | #define FLASH_TYPEPROGRAM_BYTE 0x00000000U /*!< Program byte (8-bit) at a specified address */
105 | #define FLASH_TYPEPROGRAM_HALFWORD 0x00000001U /*!< Program a half-word (16-bit) at a specified address */
106 | #define FLASH_TYPEPROGRAM_WORD 0x00000002U /*!< Program a word (32-bit) at a specified address */
107 | #define FLASH_TYPEPROGRAM_DOUBLEWORD 0x00000003U /*!< Program a double word (64-bit) at a specified address */
108 | /**
109 | * @}
110 | */
111 |
112 | /** @defgroup FLASH_Flag_definition FLASH Flag definition
113 | * @brief Flag definition
114 | * @{
115 | */
116 | #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
117 | #define FLASH_FLAG_OPERR FLASH_SR_SOP /*!< FLASH operation Error flag */
118 | #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
119 | #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
120 | #define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */
121 | #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */
122 | #if defined(FLASH_SR_RDERR)
123 | #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read Protection error flag (PCROP) */
124 | #endif /* FLASH_SR_RDERR */
125 | #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
126 | /**
127 | * @}
128 | */
129 |
130 | /** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
131 | * @brief FLASH Interrupt definition
132 | * @{
133 | */
134 | #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
135 | #define FLASH_IT_ERR 0x02000000U /*!< Error Interrupt source */
136 | /**
137 | * @}
138 | */
139 |
140 | /** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
141 | * @{
142 | */
143 | #define FLASH_PSIZE_BYTE 0x00000000U
144 | #define FLASH_PSIZE_HALF_WORD 0x00000100U
145 | #define FLASH_PSIZE_WORD 0x00000200U
146 | #define FLASH_PSIZE_DOUBLE_WORD 0x00000300U
147 | #define CR_PSIZE_MASK 0xFFFFFCFFU
148 | /**
149 | * @}
150 | */
151 |
152 | /** @defgroup FLASH_Keys FLASH Keys
153 | * @{
154 | */
155 | #define RDP_KEY ((uint16_t)0x00A5)
156 | #define FLASH_KEY1 0x45670123U
157 | #define FLASH_KEY2 0xCDEF89ABU
158 | #define FLASH_OPT_KEY1 0x08192A3BU
159 | #define FLASH_OPT_KEY2 0x4C5D6E7FU
160 | /**
161 | * @}
162 | */
163 |
164 | /**
165 | * @}
166 | */
167 |
168 | /* Exported macro ------------------------------------------------------------*/
169 | /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
170 | * @{
171 | */
172 | /**
173 | * @brief Set the FLASH Latency.
174 | * @param __LATENCY__ FLASH Latency
175 | * The value of this parameter depend on device used within the same series
176 | * @retval none
177 | */
178 | #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
179 |
180 | /**
181 | * @brief Get the FLASH Latency.
182 | * @retval FLASH Latency
183 | * The value of this parameter depend on device used within the same series
184 | */
185 | #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
186 |
187 | /**
188 | * @brief Enable the FLASH prefetch buffer.
189 | * @retval none
190 | */
191 | #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
192 |
193 | /**
194 | * @brief Disable the FLASH prefetch buffer.
195 | * @retval none
196 | */
197 | #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
198 |
199 | /**
200 | * @brief Enable the FLASH instruction cache.
201 | * @retval none
202 | */
203 | #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN)
204 |
205 | /**
206 | * @brief Disable the FLASH instruction cache.
207 | * @retval none
208 | */
209 | #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN))
210 |
211 | /**
212 | * @brief Enable the FLASH data cache.
213 | * @retval none
214 | */
215 | #define __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN)
216 |
217 | /**
218 | * @brief Disable the FLASH data cache.
219 | * @retval none
220 | */
221 | #define __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN))
222 |
223 | /**
224 | * @brief Resets the FLASH instruction Cache.
225 | * @note This function must be used only when the Instruction Cache is disabled.
226 | * @retval None
227 | */
228 | #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \
229 | FLASH->ACR &= ~FLASH_ACR_ICRST; \
230 | }while(0U)
231 |
232 | /**
233 | * @brief Resets the FLASH data Cache.
234 | * @note This function must be used only when the data Cache is disabled.
235 | * @retval None
236 | */
237 | #define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \
238 | FLASH->ACR &= ~FLASH_ACR_DCRST; \
239 | }while(0U)
240 | /**
241 | * @brief Enable the specified FLASH interrupt.
242 | * @param __INTERRUPT__ FLASH interrupt
243 | * This parameter can be any combination of the following values:
244 | * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
245 | * @arg FLASH_IT_ERR: Error Interrupt
246 | * @retval none
247 | */
248 | #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
249 |
250 | /**
251 | * @brief Disable the specified FLASH interrupt.
252 | * @param __INTERRUPT__ FLASH interrupt
253 | * This parameter can be any combination of the following values:
254 | * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
255 | * @arg FLASH_IT_ERR: Error Interrupt
256 | * @retval none
257 | */
258 | #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
259 |
260 | /**
261 | * @brief Get the specified FLASH flag status.
262 | * @param __FLAG__ specifies the FLASH flags to check.
263 | * This parameter can be any combination of the following values:
264 | * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
265 | * @arg FLASH_FLAG_OPERR : FLASH operation Error flag
266 | * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
267 | * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
268 | * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
269 | * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
270 | * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)
271 | * @arg FLASH_FLAG_BSY : FLASH Busy flag
272 | * (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices
273 | * @retval The new state of __FLAG__ (SET or RESET).
274 | */
275 | #define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))
276 |
277 | /**
278 | * @brief Clear the specified FLASH flags.
279 | * @param __FLAG__ specifies the FLASH flags to clear.
280 | * This parameter can be any combination of the following values:
281 | * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
282 | * @arg FLASH_FLAG_OPERR : FLASH operation Error flag
283 | * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
284 | * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
285 | * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
286 | * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
287 | * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)
288 | * (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices
289 | * @retval none
290 | */
291 | #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
292 | /**
293 | * @}
294 | */
295 |
296 | /* Include FLASH HAL Extension module */
297 | #include "stm32f4xx_hal_flash_ex.h"
298 | #include "stm32f4xx_hal_flash_ramfunc.h"
299 |
300 | /* Exported functions --------------------------------------------------------*/
301 | /** @addtogroup FLASH_Exported_Functions
302 | * @{
303 | */
304 | /** @addtogroup FLASH_Exported_Functions_Group1
305 | * @{
306 | */
307 | /* Program operation functions ***********************************************/
308 | HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
309 | HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
310 | /* FLASH IRQ handler method */
311 | void HAL_FLASH_IRQHandler(void);
312 | /* Callbacks in non blocking modes */
313 | void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
314 | void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
315 | /**
316 | * @}
317 | */
318 |
319 | /** @addtogroup FLASH_Exported_Functions_Group2
320 | * @{
321 | */
322 | /* Peripheral Control functions **********************************************/
323 | HAL_StatusTypeDef HAL_FLASH_Unlock(void);
324 | HAL_StatusTypeDef HAL_FLASH_Lock(void);
325 | HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
326 | HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
327 | /* Option bytes control */
328 | HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
329 | /**
330 | * @}
331 | */
332 |
333 | /** @addtogroup FLASH_Exported_Functions_Group3
334 | * @{
335 | */
336 | /* Peripheral State functions ************************************************/
337 | uint32_t HAL_FLASH_GetError(void);
338 | HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
339 | /**
340 | * @}
341 | */
342 |
343 | /**
344 | * @}
345 | */
346 | /* Private types -------------------------------------------------------------*/
347 | /* Private variables ---------------------------------------------------------*/
348 | /** @defgroup FLASH_Private_Variables FLASH Private Variables
349 | * @{
350 | */
351 |
352 | /**
353 | * @}
354 | */
355 | /* Private constants ---------------------------------------------------------*/
356 | /** @defgroup FLASH_Private_Constants FLASH Private Constants
357 | * @{
358 | */
359 |
360 | /**
361 | * @brief ACR register byte 0 (Bits[7:0]) base address
362 | */
363 | #define ACR_BYTE0_ADDRESS 0x40023C00U
364 | /**
365 | * @brief OPTCR register byte 0 (Bits[7:0]) base address
366 | */
367 | #define OPTCR_BYTE0_ADDRESS 0x40023C14U
368 | /**
369 | * @brief OPTCR register byte 1 (Bits[15:8]) base address
370 | */
371 | #define OPTCR_BYTE1_ADDRESS 0x40023C15U
372 | /**
373 | * @brief OPTCR register byte 2 (Bits[23:16]) base address
374 | */
375 | #define OPTCR_BYTE2_ADDRESS 0x40023C16U
376 | /**
377 | * @brief OPTCR register byte 3 (Bits[31:24]) base address
378 | */
379 | #define OPTCR_BYTE3_ADDRESS 0x40023C17U
380 |
381 | /**
382 | * @}
383 | */
384 |
385 | /* Private macros ------------------------------------------------------------*/
386 | /** @defgroup FLASH_Private_Macros FLASH Private Macros
387 | * @{
388 | */
389 |
390 | /** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
391 | * @{
392 | */
393 | #define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
394 | ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
395 | ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
396 | ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
397 | /**
398 | * @}
399 | */
400 |
401 | /**
402 | * @}
403 | */
404 |
405 | /* Private functions ---------------------------------------------------------*/
406 | /** @defgroup FLASH_Private_Functions FLASH Private Functions
407 | * @{
408 | */
409 |
410 | /**
411 | * @}
412 | */
413 |
414 | /**
415 | * @}
416 | */
417 |
418 | /**
419 | * @}
420 | */
421 |
422 | #ifdef __cplusplus
423 | }
424 | #endif
425 |
426 | #endif /* __STM32F4xx_HAL_FLASH_H */
427 |
428 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
429 |
--------------------------------------------------------------------------------
/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_flash_ramfunc.h
4 | * @author MCD Application Team
5 | * @brief Header file of FLASH RAMFUNC driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_FLASH_RAMFUNC_H
22 | #define __STM32F4xx_FLASH_RAMFUNC_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
28 | defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f4xx_hal_def.h"
32 |
33 | /** @addtogroup STM32F4xx_HAL_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup FLASH_RAMFUNC
38 | * @{
39 | */
40 |
41 | /* Exported types ------------------------------------------------------------*/
42 | /* Exported macro ------------------------------------------------------------*/
43 | /* Exported functions --------------------------------------------------------*/
44 | /** @addtogroup FLASH_RAMFUNC_Exported_Functions
45 | * @{
46 | */
47 |
48 | /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
49 | * @{
50 | */
51 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void);
52 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void);
53 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void);
54 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void);
55 | /**
56 | * @}
57 | */
58 |
59 | /**
60 | * @}
61 | */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /**
68 | * @}
69 | */
70 |
71 | #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
72 | #ifdef __cplusplus
73 | }
74 | #endif
75 |
76 |
77 | #endif /* __STM32F4xx_FLASH_RAMFUNC_H */
78 |
79 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
80 |
--------------------------------------------------------------------------------
/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_gpio.h
4 | * @author MCD Application Team
5 | * @brief Header file of GPIO HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_HAL_GPIO_H
22 | #define __STM32F4xx_HAL_GPIO_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup GPIO
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /** @defgroup GPIO_Exported_Types GPIO Exported Types
41 | * @{
42 | */
43 |
44 | /**
45 | * @brief GPIO Init structure definition
46 | */
47 | typedef struct
48 | {
49 | uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
50 | This parameter can be any value of @ref GPIO_pins_define */
51 |
52 | uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
53 | This parameter can be a value of @ref GPIO_mode_define */
54 |
55 | uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
56 | This parameter can be a value of @ref GPIO_pull_define */
57 |
58 | uint32_t Speed; /*!< Specifies the speed for the selected pins.
59 | This parameter can be a value of @ref GPIO_speed_define */
60 |
61 | uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
62 | This parameter can be a value of @ref GPIO_Alternate_function_selection */
63 | }GPIO_InitTypeDef;
64 |
65 | /**
66 | * @brief GPIO Bit SET and Bit RESET enumeration
67 | */
68 | typedef enum
69 | {
70 | GPIO_PIN_RESET = 0,
71 | GPIO_PIN_SET
72 | }GPIO_PinState;
73 | /**
74 | * @}
75 | */
76 |
77 | /* Exported constants --------------------------------------------------------*/
78 |
79 | /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
80 | * @{
81 | */
82 |
83 | /** @defgroup GPIO_pins_define GPIO pins define
84 | * @{
85 | */
86 | #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
87 | #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
88 | #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
89 | #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
90 | #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
91 | #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
92 | #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
93 | #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
94 | #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
95 | #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
96 | #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
97 | #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
98 | #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
99 | #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
100 | #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
101 | #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
102 | #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
103 |
104 | #define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */
105 | /**
106 | * @}
107 | */
108 |
109 | /** @defgroup GPIO_mode_define GPIO mode define
110 | * @brief GPIO Configuration Mode
111 | * Elements values convention: 0xX0yz00YZ
112 | * - X : GPIO mode or EXTI Mode
113 | * - y : External IT or Event trigger detection
114 | * - z : IO configuration on External IT or Event
115 | * - Y : Output type (Push Pull or Open Drain)
116 | * - Z : IO Direction mode (Input, Output, Alternate or Analog)
117 | * @{
118 | */
119 | #define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */
120 | #define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */
121 | #define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */
122 | #define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */
123 | #define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */
124 |
125 | #define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */
126 |
127 | #define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */
128 | #define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */
129 | #define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
130 |
131 | #define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */
132 | #define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */
133 | #define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */
134 | /**
135 | * @}
136 | */
137 |
138 | /** @defgroup GPIO_speed_define GPIO speed define
139 | * @brief GPIO Output Maximum frequency
140 | * @{
141 | */
142 | #define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */
143 | #define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
144 | #define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */
145 | #define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */
146 | /**
147 | * @}
148 | */
149 |
150 | /** @defgroup GPIO_pull_define GPIO pull define
151 | * @brief GPIO Pull-Up or Pull-Down Activation
152 | * @{
153 | */
154 | #define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */
155 | #define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */
156 | #define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */
157 | /**
158 | * @}
159 | */
160 |
161 | /**
162 | * @}
163 | */
164 |
165 | /* Exported macro ------------------------------------------------------------*/
166 | /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
167 | * @{
168 | */
169 |
170 | /**
171 | * @brief Checks whether the specified EXTI line flag is set or not.
172 | * @param __EXTI_LINE__ specifies the EXTI line flag to check.
173 | * This parameter can be GPIO_PIN_x where x can be(0..15)
174 | * @retval The new state of __EXTI_LINE__ (SET or RESET).
175 | */
176 | #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
177 |
178 | /**
179 | * @brief Clears the EXTI's line pending flags.
180 | * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
181 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
182 | * @retval None
183 | */
184 | #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
185 |
186 | /**
187 | * @brief Checks whether the specified EXTI line is asserted or not.
188 | * @param __EXTI_LINE__ specifies the EXTI line to check.
189 | * This parameter can be GPIO_PIN_x where x can be(0..15)
190 | * @retval The new state of __EXTI_LINE__ (SET or RESET).
191 | */
192 | #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
193 |
194 | /**
195 | * @brief Clears the EXTI's line pending bits.
196 | * @param __EXTI_LINE__ specifies the EXTI lines to clear.
197 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
198 | * @retval None
199 | */
200 | #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
201 |
202 | /**
203 | * @brief Generates a Software interrupt on selected EXTI line.
204 | * @param __EXTI_LINE__ specifies the EXTI line to check.
205 | * This parameter can be GPIO_PIN_x where x can be(0..15)
206 | * @retval None
207 | */
208 | #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
209 | /**
210 | * @}
211 | */
212 |
213 | /* Include GPIO HAL Extension module */
214 | #include "stm32f4xx_hal_gpio_ex.h"
215 |
216 | /* Exported functions --------------------------------------------------------*/
217 | /** @addtogroup GPIO_Exported_Functions
218 | * @{
219 | */
220 |
221 | /** @addtogroup GPIO_Exported_Functions_Group1
222 | * @{
223 | */
224 | /* Initialization and de-initialization functions *****************************/
225 | void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
226 | void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
227 | /**
228 | * @}
229 | */
230 |
231 | /** @addtogroup GPIO_Exported_Functions_Group2
232 | * @{
233 | */
234 | /* IO operation functions *****************************************************/
235 | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
236 | void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
237 | void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
238 | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
239 | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
240 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
241 |
242 | /**
243 | * @}
244 | */
245 |
246 | /**
247 | * @}
248 | */
249 | /* Private types -------------------------------------------------------------*/
250 | /* Private variables ---------------------------------------------------------*/
251 | /* Private constants ---------------------------------------------------------*/
252 | /** @defgroup GPIO_Private_Constants GPIO Private Constants
253 | * @{
254 | */
255 |
256 | /**
257 | * @}
258 | */
259 |
260 | /* Private macros ------------------------------------------------------------*/
261 | /** @defgroup GPIO_Private_Macros GPIO Private Macros
262 | * @{
263 | */
264 | #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
265 | #define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
266 | #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
267 | ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
268 | ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
269 | ((MODE) == GPIO_MODE_AF_PP) ||\
270 | ((MODE) == GPIO_MODE_AF_OD) ||\
271 | ((MODE) == GPIO_MODE_IT_RISING) ||\
272 | ((MODE) == GPIO_MODE_IT_FALLING) ||\
273 | ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
274 | ((MODE) == GPIO_MODE_EVT_RISING) ||\
275 | ((MODE) == GPIO_MODE_EVT_FALLING) ||\
276 | ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
277 | ((MODE) == GPIO_MODE_ANALOG))
278 | #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
279 | ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
280 | #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
281 | ((PULL) == GPIO_PULLDOWN))
282 | /**
283 | * @}
284 | */
285 |
286 | /* Private functions ---------------------------------------------------------*/
287 | /** @defgroup GPIO_Private_Functions GPIO Private Functions
288 | * @{
289 | */
290 |
291 | /**
292 | * @}
293 | */
294 |
295 | /**
296 | * @}
297 | */
298 |
299 | /**
300 | * @}
301 | */
302 |
303 | #ifdef __cplusplus
304 | }
305 | #endif
306 |
307 | #endif /* __STM32F4xx_HAL_GPIO_H */
308 |
309 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
310 |
--------------------------------------------------------------------------------
/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_pwr.h
4 | * @author MCD Application Team
5 | * @brief Header file of PWR HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_HAL_PWR_H
22 | #define __STM32F4xx_HAL_PWR_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup PWR
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 |
41 | /** @defgroup PWR_Exported_Types PWR Exported Types
42 | * @{
43 | */
44 |
45 | /**
46 | * @brief PWR PVD configuration structure definition
47 | */
48 | typedef struct
49 | {
50 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
51 | This parameter can be a value of @ref PWR_PVD_detection_level */
52 |
53 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
54 | This parameter can be a value of @ref PWR_PVD_Mode */
55 | }PWR_PVDTypeDef;
56 |
57 | /**
58 | * @}
59 | */
60 |
61 | /* Exported constants --------------------------------------------------------*/
62 | /** @defgroup PWR_Exported_Constants PWR Exported Constants
63 | * @{
64 | */
65 |
66 | /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
67 | * @{
68 | */
69 | #define PWR_WAKEUP_PIN1 0x00000100U
70 | /**
71 | * @}
72 | */
73 |
74 | /** @defgroup PWR_PVD_detection_level PWR PVD detection level
75 | * @{
76 | */
77 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
78 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
79 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
80 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
81 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
82 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
83 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
84 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
85 | (Compare internally to VREFINT) */
86 | /**
87 | * @}
88 | */
89 |
90 | /** @defgroup PWR_PVD_Mode PWR PVD Mode
91 | * @{
92 | */
93 | #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
94 | #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
95 | #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
96 | #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
97 | #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
98 | #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
99 | #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
100 | /**
101 | * @}
102 | */
103 |
104 |
105 | /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
106 | * @{
107 | */
108 | #define PWR_MAINREGULATOR_ON 0x00000000U
109 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
110 | /**
111 | * @}
112 | */
113 |
114 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
115 | * @{
116 | */
117 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
118 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
119 | /**
120 | * @}
121 | */
122 |
123 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
124 | * @{
125 | */
126 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
127 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
128 | /**
129 | * @}
130 | */
131 |
132 | /** @defgroup PWR_Flag PWR Flag
133 | * @{
134 | */
135 | #define PWR_FLAG_WU PWR_CSR_WUF
136 | #define PWR_FLAG_SB PWR_CSR_SBF
137 | #define PWR_FLAG_PVDO PWR_CSR_PVDO
138 | #define PWR_FLAG_BRR PWR_CSR_BRR
139 | #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
140 | /**
141 | * @}
142 | */
143 |
144 | /**
145 | * @}
146 | */
147 |
148 | /* Exported macro ------------------------------------------------------------*/
149 | /** @defgroup PWR_Exported_Macro PWR Exported Macro
150 | * @{
151 | */
152 |
153 | /** @brief Check PWR flag is set or not.
154 | * @param __FLAG__ specifies the flag to check.
155 | * This parameter can be one of the following values:
156 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
157 | * was received from the WKUP pin or from the RTC alarm (Alarm A
158 | * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
159 | * An additional wakeup event is detected if the WKUP pin is enabled
160 | * (by setting the EWUP bit) when the WKUP pin level is already high.
161 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
162 | * resumed from StandBy mode.
163 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
164 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
165 | * For this reason, this bit is equal to 0 after Standby or reset
166 | * until the PVDE bit is set.
167 | * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
168 | * when the device wakes up from Standby mode or by a system reset
169 | * or power reset.
170 | * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
171 | * scaling output selection is ready.
172 | * @retval The new state of __FLAG__ (TRUE or FALSE).
173 | */
174 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
175 |
176 | /** @brief Clear the PWR's pending flags.
177 | * @param __FLAG__ specifies the flag to clear.
178 | * This parameter can be one of the following values:
179 | * @arg PWR_FLAG_WU: Wake Up flag
180 | * @arg PWR_FLAG_SB: StandBy flag
181 | */
182 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
183 |
184 | /**
185 | * @brief Enable the PVD Exti Line 16.
186 | * @retval None.
187 | */
188 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
189 |
190 | /**
191 | * @brief Disable the PVD EXTI Line 16.
192 | * @retval None.
193 | */
194 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
195 |
196 | /**
197 | * @brief Enable event on PVD Exti Line 16.
198 | * @retval None.
199 | */
200 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
201 |
202 | /**
203 | * @brief Disable event on PVD Exti Line 16.
204 | * @retval None.
205 | */
206 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
207 |
208 | /**
209 | * @brief Enable the PVD Extended Interrupt Rising Trigger.
210 | * @retval None.
211 | */
212 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
213 |
214 | /**
215 | * @brief Disable the PVD Extended Interrupt Rising Trigger.
216 | * @retval None.
217 | */
218 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
219 |
220 | /**
221 | * @brief Enable the PVD Extended Interrupt Falling Trigger.
222 | * @retval None.
223 | */
224 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
225 |
226 |
227 | /**
228 | * @brief Disable the PVD Extended Interrupt Falling Trigger.
229 | * @retval None.
230 | */
231 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
232 |
233 |
234 | /**
235 | * @brief PVD EXTI line configuration: set rising & falling edge trigger.
236 | * @retval None.
237 | */
238 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
239 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
240 | }while(0U)
241 |
242 | /**
243 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
244 | * This parameter can be:
245 | * @retval None.
246 | */
247 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
248 | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
249 | }while(0U)
250 |
251 | /**
252 | * @brief checks whether the specified PVD Exti interrupt flag is set or not.
253 | * @retval EXTI PVD Line Status.
254 | */
255 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
256 |
257 | /**
258 | * @brief Clear the PVD Exti flag.
259 | * @retval None.
260 | */
261 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
262 |
263 | /**
264 | * @brief Generates a Software interrupt on PVD EXTI line.
265 | * @retval None
266 | */
267 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
268 |
269 | /**
270 | * @}
271 | */
272 |
273 | /* Include PWR HAL Extension module */
274 | #include "stm32f4xx_hal_pwr_ex.h"
275 |
276 | /* Exported functions --------------------------------------------------------*/
277 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions
278 | * @{
279 | */
280 |
281 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
282 | * @{
283 | */
284 | /* Initialization and de-initialization functions *****************************/
285 | void HAL_PWR_DeInit(void);
286 | void HAL_PWR_EnableBkUpAccess(void);
287 | void HAL_PWR_DisableBkUpAccess(void);
288 | /**
289 | * @}
290 | */
291 |
292 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
293 | * @{
294 | */
295 | /* Peripheral Control functions **********************************************/
296 | /* PVD configuration */
297 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
298 | void HAL_PWR_EnablePVD(void);
299 | void HAL_PWR_DisablePVD(void);
300 |
301 | /* WakeUp pins configuration */
302 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
303 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
304 |
305 | /* Low Power modes entry */
306 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
307 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
308 | void HAL_PWR_EnterSTANDBYMode(void);
309 |
310 | /* Power PVD IRQ Handler */
311 | void HAL_PWR_PVD_IRQHandler(void);
312 | void HAL_PWR_PVDCallback(void);
313 |
314 | /* Cortex System Control functions *******************************************/
315 | void HAL_PWR_EnableSleepOnExit(void);
316 | void HAL_PWR_DisableSleepOnExit(void);
317 | void HAL_PWR_EnableSEVOnPend(void);
318 | void HAL_PWR_DisableSEVOnPend(void);
319 | /**
320 | * @}
321 | */
322 |
323 | /**
324 | * @}
325 | */
326 |
327 | /* Private types -------------------------------------------------------------*/
328 | /* Private variables ---------------------------------------------------------*/
329 | /* Private constants ---------------------------------------------------------*/
330 | /** @defgroup PWR_Private_Constants PWR Private Constants
331 | * @{
332 | */
333 |
334 | /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
335 | * @{
336 | */
337 | #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
338 | /**
339 | * @}
340 | */
341 |
342 | /** @defgroup PWR_register_alias_address PWR Register alias address
343 | * @{
344 | */
345 | /* ------------- PWR registers bit address in the alias region ---------------*/
346 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
347 | #define PWR_CR_OFFSET 0x00U
348 | #define PWR_CSR_OFFSET 0x04U
349 | #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
350 | #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
351 | /**
352 | * @}
353 | */
354 |
355 | /** @defgroup PWR_CR_register_alias PWR CR Register alias address
356 | * @{
357 | */
358 | /* --- CR Register ---*/
359 | /* Alias word address of DBP bit */
360 | #define DBP_BIT_NUMBER PWR_CR_DBP_Pos
361 | #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
362 |
363 | /* Alias word address of PVDE bit */
364 | #define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
365 | #define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
366 |
367 | /* Alias word address of VOS bit */
368 | #define VOS_BIT_NUMBER PWR_CR_VOS_Pos
369 | #define CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U))
370 | /**
371 | * @}
372 | */
373 |
374 | /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
375 | * @{
376 | */
377 | /* --- CSR Register ---*/
378 | /* Alias word address of EWUP bit */
379 | #define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos
380 | #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
381 | /**
382 | * @}
383 | */
384 |
385 | /**
386 | * @}
387 | */
388 | /* Private macros ------------------------------------------------------------*/
389 | /** @defgroup PWR_Private_Macros PWR Private Macros
390 | * @{
391 | */
392 |
393 | /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
394 | * @{
395 | */
396 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
397 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
398 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
399 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
400 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
401 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
402 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
403 | ((MODE) == PWR_PVD_MODE_NORMAL))
404 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
405 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
406 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
407 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
408 | /**
409 | * @}
410 | */
411 |
412 | /**
413 | * @}
414 | */
415 |
416 | /**
417 | * @}
418 | */
419 |
420 | /**
421 | * @}
422 | */
423 |
424 | #ifdef __cplusplus
425 | }
426 | #endif
427 |
428 |
429 | #endif /* __STM32F4xx_HAL_PWR_H */
430 |
431 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
432 |
--------------------------------------------------------------------------------
/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_dma_ex.c
4 | * @author MCD Application Team
5 | * @brief DMA Extension HAL module driver
6 | * This file provides firmware functions to manage the following
7 | * functionalities of the DMA Extension peripheral:
8 | * + Extended features functions
9 | *
10 | @verbatim
11 | ==============================================================================
12 | ##### How to use this driver #####
13 | ==============================================================================
14 | [..]
15 | The DMA Extension HAL driver can be used as follows:
16 | (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
17 | for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
18 |
19 | -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
20 | -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
21 | -@- In Multi (Double) buffer mode, it is possible to update the base address for
22 | the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
23 |
24 | @endverbatim
25 | ******************************************************************************
26 | * @attention
27 | *
28 | * © Copyright (c) 2017 STMicroelectronics.
29 | * All rights reserved.
30 | *
31 | * This software component is licensed by ST under BSD 3-Clause license,
32 | * the "License"; You may not use this file except in compliance with the
33 | * License. You may obtain a copy of the License at:
34 | * opensource.org/licenses/BSD-3-Clause
35 | *
36 | ******************************************************************************
37 | */
38 |
39 | /* Includes ------------------------------------------------------------------*/
40 | #include "stm32f4xx_hal.h"
41 |
42 | /** @addtogroup STM32F4xx_HAL_Driver
43 | * @{
44 | */
45 |
46 | /** @defgroup DMAEx DMAEx
47 | * @brief DMA Extended HAL module driver
48 | * @{
49 | */
50 |
51 | #ifdef HAL_DMA_MODULE_ENABLED
52 |
53 | /* Private types -------------------------------------------------------------*/
54 | /* Private variables ---------------------------------------------------------*/
55 | /* Private Constants ---------------------------------------------------------*/
56 | /* Private macros ------------------------------------------------------------*/
57 | /* Private functions ---------------------------------------------------------*/
58 | /** @addtogroup DMAEx_Private_Functions
59 | * @{
60 | */
61 | static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
62 | /**
63 | * @}
64 | */
65 |
66 | /* Exported functions ---------------------------------------------------------*/
67 |
68 | /** @addtogroup DMAEx_Exported_Functions
69 | * @{
70 | */
71 |
72 |
73 | /** @addtogroup DMAEx_Exported_Functions_Group1
74 | *
75 | @verbatim
76 | ===============================================================================
77 | ##### Extended features functions #####
78 | ===============================================================================
79 | [..] This section provides functions allowing to:
80 | (+) Configure the source, destination address and data length and
81 | Start MultiBuffer DMA transfer
82 | (+) Configure the source, destination address and data length and
83 | Start MultiBuffer DMA transfer with interrupt
84 | (+) Change on the fly the memory0 or memory1 address.
85 |
86 | @endverbatim
87 | * @{
88 | */
89 |
90 |
91 | /**
92 | * @brief Starts the multi_buffer DMA Transfer.
93 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
94 | * the configuration information for the specified DMA Stream.
95 | * @param SrcAddress The source memory Buffer address
96 | * @param DstAddress The destination memory Buffer address
97 | * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
98 | * @param DataLength The length of data to be transferred from source to destination
99 | * @retval HAL status
100 | */
101 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
102 | {
103 | HAL_StatusTypeDef status = HAL_OK;
104 |
105 | /* Check the parameters */
106 | assert_param(IS_DMA_BUFFER_SIZE(DataLength));
107 |
108 | /* Memory-to-memory transfer not supported in double buffering mode */
109 | if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
110 | {
111 | hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
112 | status = HAL_ERROR;
113 | }
114 | else
115 | {
116 | /* Process Locked */
117 | __HAL_LOCK(hdma);
118 |
119 | if(HAL_DMA_STATE_READY == hdma->State)
120 | {
121 | /* Change DMA peripheral state */
122 | hdma->State = HAL_DMA_STATE_BUSY;
123 |
124 | /* Enable the double buffer mode */
125 | hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
126 |
127 | /* Configure DMA Stream destination address */
128 | hdma->Instance->M1AR = SecondMemAddress;
129 |
130 | /* Configure the source, destination address and the data length */
131 | DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
132 |
133 | /* Enable the peripheral */
134 | __HAL_DMA_ENABLE(hdma);
135 | }
136 | else
137 | {
138 | /* Return error status */
139 | status = HAL_BUSY;
140 | }
141 | }
142 | return status;
143 | }
144 |
145 | /**
146 | * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
147 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
148 | * the configuration information for the specified DMA Stream.
149 | * @param SrcAddress The source memory Buffer address
150 | * @param DstAddress The destination memory Buffer address
151 | * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
152 | * @param DataLength The length of data to be transferred from source to destination
153 | * @retval HAL status
154 | */
155 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
156 | {
157 | HAL_StatusTypeDef status = HAL_OK;
158 |
159 | /* Check the parameters */
160 | assert_param(IS_DMA_BUFFER_SIZE(DataLength));
161 |
162 | /* Memory-to-memory transfer not supported in double buffering mode */
163 | if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
164 | {
165 | hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
166 | return HAL_ERROR;
167 | }
168 |
169 | /* Check callback functions */
170 | if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
171 | {
172 | hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
173 | return HAL_ERROR;
174 | }
175 |
176 | /* Process locked */
177 | __HAL_LOCK(hdma);
178 |
179 | if(HAL_DMA_STATE_READY == hdma->State)
180 | {
181 | /* Change DMA peripheral state */
182 | hdma->State = HAL_DMA_STATE_BUSY;
183 |
184 | /* Initialize the error code */
185 | hdma->ErrorCode = HAL_DMA_ERROR_NONE;
186 |
187 | /* Enable the Double buffer mode */
188 | hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
189 |
190 | /* Configure DMA Stream destination address */
191 | hdma->Instance->M1AR = SecondMemAddress;
192 |
193 | /* Configure the source, destination address and the data length */
194 | DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
195 |
196 | /* Clear all flags */
197 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
198 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
199 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
200 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
201 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
202 |
203 | /* Enable Common interrupts*/
204 | hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
205 | hdma->Instance->FCR |= DMA_IT_FE;
206 |
207 | if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
208 | {
209 | hdma->Instance->CR |= DMA_IT_HT;
210 | }
211 |
212 | /* Enable the peripheral */
213 | __HAL_DMA_ENABLE(hdma);
214 | }
215 | else
216 | {
217 | /* Process unlocked */
218 | __HAL_UNLOCK(hdma);
219 |
220 | /* Return error status */
221 | status = HAL_BUSY;
222 | }
223 | return status;
224 | }
225 |
226 | /**
227 | * @brief Change the memory0 or memory1 address on the fly.
228 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
229 | * the configuration information for the specified DMA Stream.
230 | * @param Address The new address
231 | * @param memory the memory to be changed, This parameter can be one of
232 | * the following values:
233 | * MEMORY0 /
234 | * MEMORY1
235 | * @note The MEMORY0 address can be changed only when the current transfer use
236 | * MEMORY1 and the MEMORY1 address can be changed only when the current
237 | * transfer use MEMORY0.
238 | * @retval HAL status
239 | */
240 | HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
241 | {
242 | if(memory == MEMORY0)
243 | {
244 | /* change the memory0 address */
245 | hdma->Instance->M0AR = Address;
246 | }
247 | else
248 | {
249 | /* change the memory1 address */
250 | hdma->Instance->M1AR = Address;
251 | }
252 |
253 | return HAL_OK;
254 | }
255 |
256 | /**
257 | * @}
258 | */
259 |
260 | /**
261 | * @}
262 | */
263 |
264 | /** @addtogroup DMAEx_Private_Functions
265 | * @{
266 | */
267 |
268 | /**
269 | * @brief Set the DMA Transfer parameter.
270 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
271 | * the configuration information for the specified DMA Stream.
272 | * @param SrcAddress The source memory Buffer address
273 | * @param DstAddress The destination memory Buffer address
274 | * @param DataLength The length of data to be transferred from source to destination
275 | * @retval HAL status
276 | */
277 | static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
278 | {
279 | /* Configure DMA Stream data length */
280 | hdma->Instance->NDTR = DataLength;
281 |
282 | /* Peripheral to Memory */
283 | if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
284 | {
285 | /* Configure DMA Stream destination address */
286 | hdma->Instance->PAR = DstAddress;
287 |
288 | /* Configure DMA Stream source address */
289 | hdma->Instance->M0AR = SrcAddress;
290 | }
291 | /* Memory to Peripheral */
292 | else
293 | {
294 | /* Configure DMA Stream source address */
295 | hdma->Instance->PAR = SrcAddress;
296 |
297 | /* Configure DMA Stream destination address */
298 | hdma->Instance->M0AR = DstAddress;
299 | }
300 | }
301 |
302 | /**
303 | * @}
304 | */
305 |
306 | #endif /* HAL_DMA_MODULE_ENABLED */
307 | /**
308 | * @}
309 | */
310 |
311 | /**
312 | * @}
313 | */
314 |
315 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
316 |
--------------------------------------------------------------------------------
/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_flash_ramfunc.c
4 | * @author MCD Application Team
5 | * @brief FLASH RAMFUNC module driver.
6 | * This file provides a FLASH firmware functions which should be
7 | * executed from internal SRAM
8 | * + Stop/Start the flash interface while System Run
9 | * + Enable/Disable the flash sleep while System Run
10 | @verbatim
11 | ==============================================================================
12 | ##### APIs executed from Internal RAM #####
13 | ==============================================================================
14 | [..]
15 | *** ARM Compiler ***
16 | --------------------
17 | [..] RAM functions are defined using the toolchain options.
18 | Functions that are be executed in RAM should reside in a separate
19 | source module. Using the 'Options for File' dialog you can simply change
20 | the 'Code / Const' area of a module to a memory space in physical RAM.
21 | Available memory areas are declared in the 'Target' tab of the
22 | Options for Target' dialog.
23 |
24 | *** ICCARM Compiler ***
25 | -----------------------
26 | [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
27 |
28 | *** GNU Compiler ***
29 | --------------------
30 | [..] RAM functions are defined using a specific toolchain attribute
31 | "__attribute__((section(".RamFunc")))".
32 |
33 | @endverbatim
34 | ******************************************************************************
35 | * @attention
36 | *
37 | * © Copyright (c) 2017 STMicroelectronics.
38 | * All rights reserved.
39 | *
40 | * This software component is licensed by ST under BSD 3-Clause license,
41 | * the "License"; You may not use this file except in compliance with the
42 | * License. You may obtain a copy of the License at:
43 | * opensource.org/licenses/BSD-3-Clause
44 | *
45 | ******************************************************************************
46 | */
47 |
48 | /* Includes ------------------------------------------------------------------*/
49 | #include "stm32f4xx_hal.h"
50 |
51 | /** @addtogroup STM32F4xx_HAL_Driver
52 | * @{
53 | */
54 |
55 | /** @defgroup FLASH_RAMFUNC FLASH RAMFUNC
56 | * @brief FLASH functions executed from RAM
57 | * @{
58 | */
59 | #ifdef HAL_FLASH_MODULE_ENABLED
60 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
61 | defined(STM32F412Rx) || defined(STM32F412Cx)
62 |
63 | /* Private typedef -----------------------------------------------------------*/
64 | /* Private define ------------------------------------------------------------*/
65 | /* Private macro -------------------------------------------------------------*/
66 | /* Private variables ---------------------------------------------------------*/
67 | /* Private function prototypes -----------------------------------------------*/
68 | /* Exported functions --------------------------------------------------------*/
69 | /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions
70 | * @{
71 | */
72 |
73 | /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM
74 | * @brief Peripheral Extended features functions
75 | *
76 | @verbatim
77 |
78 | ===============================================================================
79 | ##### ramfunc functions #####
80 | ===============================================================================
81 | [..]
82 | This subsection provides a set of functions that should be executed from RAM
83 | transfers.
84 |
85 | @endverbatim
86 | * @{
87 | */
88 |
89 | /**
90 | * @brief Stop the flash interface while System Run
91 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
92 | * @note This mode couldn't be set while executing with the flash itself.
93 | * It should be done with specific routine executed from RAM.
94 | * @retval HAL status
95 | */
96 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void)
97 | {
98 | /* Enable Power ctrl clock */
99 | __HAL_RCC_PWR_CLK_ENABLE();
100 | /* Stop the flash interface while System Run */
101 | SET_BIT(PWR->CR, PWR_CR_FISSR);
102 |
103 | return HAL_OK;
104 | }
105 |
106 | /**
107 | * @brief Start the flash interface while System Run
108 | * @note This mode is only available for STM32F411xx/STM32F446xx devices.
109 | * @note This mode couldn't be set while executing with the flash itself.
110 | * It should be done with specific routine executed from RAM.
111 | * @retval HAL status
112 | */
113 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void)
114 | {
115 | /* Enable Power ctrl clock */
116 | __HAL_RCC_PWR_CLK_ENABLE();
117 | /* Start the flash interface while System Run */
118 | CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
119 |
120 | return HAL_OK;
121 | }
122 |
123 | /**
124 | * @brief Enable the flash sleep while System Run
125 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
126 | * @note This mode could n't be set while executing with the flash itself.
127 | * It should be done with specific routine executed from RAM.
128 | * @retval HAL status
129 | */
130 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void)
131 | {
132 | /* Enable Power ctrl clock */
133 | __HAL_RCC_PWR_CLK_ENABLE();
134 | /* Enable the flash sleep while System Run */
135 | SET_BIT(PWR->CR, PWR_CR_FMSSR);
136 |
137 | return HAL_OK;
138 | }
139 |
140 | /**
141 | * @brief Disable the flash sleep while System Run
142 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
143 | * @note This mode couldn't be set while executing with the flash itself.
144 | * It should be done with specific routine executed from RAM.
145 | * @retval HAL status
146 | */
147 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void)
148 | {
149 | /* Enable Power ctrl clock */
150 | __HAL_RCC_PWR_CLK_ENABLE();
151 | /* Disable the flash sleep while System Run */
152 | CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
153 |
154 | return HAL_OK;
155 | }
156 |
157 | /**
158 | * @}
159 | */
160 |
161 | /**
162 | * @}
163 | */
164 |
165 | #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
166 | #endif /* HAL_FLASH_MODULE_ENABLED */
167 | /**
168 | * @}
169 | */
170 |
171 | /**
172 | * @}
173 | */
174 |
175 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
176 |
--------------------------------------------------------------------------------
/Inc/can.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : CAN.h
4 | * Description : This file provides code for the configuration
5 | * of the CAN instances.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef __can_H
21 | #define __can_H
22 | #ifdef __cplusplus
23 | extern "C" {
24 | #endif
25 |
26 | /* Includes ------------------------------------------------------------------*/
27 | #include "main.h"
28 |
29 | /* USER CODE BEGIN Includes */
30 |
31 | /* USER CODE END Includes */
32 |
33 | extern CAN_HandleTypeDef hcan1;
34 | extern CAN_HandleTypeDef hcan2;
35 |
36 | /* USER CODE BEGIN Private defines */
37 |
38 | /* USER CODE END Private defines */
39 |
40 | void MX_CAN1_Init(void);
41 | void MX_CAN2_Init(void);
42 |
43 | /* USER CODE BEGIN Prototypes */
44 |
45 | /* USER CODE END Prototypes */
46 |
47 | #ifdef __cplusplus
48 | }
49 | #endif
50 | #endif /*__ can_H */
51 |
52 | /**
53 | * @}
54 | */
55 |
56 | /**
57 | * @}
58 | */
59 |
60 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
61 |
--------------------------------------------------------------------------------
/Inc/dma.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : dma.h
4 | * Description : This file contains all the function prototypes for
5 | * the dma.c file
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef __dma_H
21 | #define __dma_H
22 |
23 | #ifdef __cplusplus
24 | extern "C" {
25 | #endif
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 | #include "main.h"
29 |
30 | /* DMA memory to memory transfer handles -------------------------------------*/
31 |
32 | /* USER CODE BEGIN Includes */
33 |
34 | /* USER CODE END Includes */
35 |
36 | /* USER CODE BEGIN Private defines */
37 |
38 | /* USER CODE END Private defines */
39 |
40 | void MX_DMA_Init(void);
41 |
42 | /* USER CODE BEGIN Prototypes */
43 |
44 | /* USER CODE END Prototypes */
45 |
46 | #ifdef __cplusplus
47 | }
48 | #endif
49 |
50 | #endif /* __dma_H */
51 |
52 | /**
53 | * @}
54 | */
55 |
56 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
57 |
--------------------------------------------------------------------------------
/Inc/gpio.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : gpio.h
4 | * Description : This file contains all the functions prototypes for
5 | * the gpio
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __gpio_H
22 | #define __gpio_H
23 | #ifdef __cplusplus
24 | extern "C" {
25 | #endif
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 | #include "main.h"
29 |
30 | /* USER CODE BEGIN Includes */
31 |
32 | /* USER CODE END Includes */
33 |
34 | /* USER CODE BEGIN Private defines */
35 |
36 | /* USER CODE END Private defines */
37 |
38 | void MX_GPIO_Init(void);
39 |
40 | /* USER CODE BEGIN Prototypes */
41 |
42 | /* USER CODE END Prototypes */
43 |
44 | #ifdef __cplusplus
45 | }
46 | #endif
47 | #endif /*__ pinoutConfig_H */
48 |
49 | /**
50 | * @}
51 | */
52 |
53 | /**
54 | * @}
55 | */
56 |
57 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
58 |
--------------------------------------------------------------------------------
/Inc/main.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file : main.h
5 | * @brief : Header for main.c file.
6 | * This file contains the common defines of the application.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2020 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __MAIN_H
24 | #define __MAIN_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f4xx_hal.h"
32 |
33 | /* Private includes ----------------------------------------------------------*/
34 | /* USER CODE BEGIN Includes */
35 |
36 | /* USER CODE END Includes */
37 |
38 | /* Exported types ------------------------------------------------------------*/
39 | /* USER CODE BEGIN ET */
40 | typedef struct
41 | {
42 | struct
43 | {
44 | unsigned short ch0;
45 | unsigned short ch1;
46 | unsigned short ch2;
47 | unsigned short ch3;
48 | unsigned char s1;
49 | unsigned char s2;
50 | }rc;
51 |
52 | struct
53 | {
54 | unsigned short x;
55 | unsigned short y;
56 | unsigned short z;
57 | unsigned char press_l;
58 | unsigned char press_r;
59 | }mouse;
60 |
61 | struct
62 | {
63 | unsigned short v;
64 | }key;
65 | }RC_Ctl_t;
66 | /* USER CODE END ET */
67 |
68 | /* Exported constants --------------------------------------------------------*/
69 | /* USER CODE BEGIN EC */
70 |
71 | /* USER CODE END EC */
72 |
73 | /* Exported macro ------------------------------------------------------------*/
74 | /* USER CODE BEGIN EM */
75 |
76 | /* USER CODE END EM */
77 |
78 | /* Exported functions prototypes ---------------------------------------------*/
79 | void Error_Handler(void);
80 |
81 | /* USER CODE BEGIN EFP */
82 |
83 | /* USER CODE END EFP */
84 |
85 | /* Private defines -----------------------------------------------------------*/
86 | /* USER CODE BEGIN Private defines */
87 |
88 | /* USER CODE END Private defines */
89 |
90 | #ifdef __cplusplus
91 | }
92 | #endif
93 |
94 | #endif /* __MAIN_H */
95 |
96 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
97 |
--------------------------------------------------------------------------------
/Inc/stm32f4xx_it.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f4xx_it.h
5 | * @brief This file contains the headers of the interrupt handlers.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F4xx_IT_H
23 | #define __STM32F4xx_IT_H
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Private includes ----------------------------------------------------------*/
30 | /* USER CODE BEGIN Includes */
31 |
32 | /* USER CODE END Includes */
33 |
34 | /* Exported types ------------------------------------------------------------*/
35 | /* USER CODE BEGIN ET */
36 |
37 | /* USER CODE END ET */
38 |
39 | /* Exported constants --------------------------------------------------------*/
40 | /* USER CODE BEGIN EC */
41 |
42 | /* USER CODE END EC */
43 |
44 | /* Exported macro ------------------------------------------------------------*/
45 | /* USER CODE BEGIN EM */
46 |
47 | /* USER CODE END EM */
48 |
49 | /* Exported functions prototypes ---------------------------------------------*/
50 | void NMI_Handler(void);
51 | void HardFault_Handler(void);
52 | void MemManage_Handler(void);
53 | void BusFault_Handler(void);
54 | void UsageFault_Handler(void);
55 | void DebugMon_Handler(void);
56 | void SysTick_Handler(void);
57 | void DMA1_Stream1_IRQHandler(void);
58 | void CAN1_RX0_IRQHandler(void);
59 | void CAN2_RX0_IRQHandler(void);
60 | /* USER CODE BEGIN EFP */
61 |
62 | /* USER CODE END EFP */
63 |
64 | #ifdef __cplusplus
65 | }
66 | #endif
67 |
68 | #endif /* __STM32F4xx_IT_H */
69 |
70 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
71 |
--------------------------------------------------------------------------------
/Inc/tim.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : TIM.h
4 | * Description : This file provides code for the configuration
5 | * of the TIM instances.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef __tim_H
21 | #define __tim_H
22 | #ifdef __cplusplus
23 | extern "C" {
24 | #endif
25 |
26 | /* Includes ------------------------------------------------------------------*/
27 | #include "main.h"
28 |
29 | /* USER CODE BEGIN Includes */
30 |
31 | /* USER CODE END Includes */
32 |
33 | extern TIM_HandleTypeDef htim1;
34 | extern TIM_HandleTypeDef htim8;
35 |
36 | /* USER CODE BEGIN Private defines */
37 |
38 | /* USER CODE END Private defines */
39 |
40 | void MX_TIM1_Init(void);
41 | void MX_TIM8_Init(void);
42 |
43 | void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
44 |
45 | /* USER CODE BEGIN Prototypes */
46 |
47 | /* USER CODE END Prototypes */
48 |
49 | #ifdef __cplusplus
50 | }
51 | #endif
52 | #endif /*__ tim_H */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /**
59 | * @}
60 | */
61 |
62 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
63 |
--------------------------------------------------------------------------------
/Inc/usart.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : USART.h
4 | * Description : This file provides code for the configuration
5 | * of the USART instances.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef __usart_H
21 | #define __usart_H
22 | #ifdef __cplusplus
23 | extern "C" {
24 | #endif
25 |
26 | /* Includes ------------------------------------------------------------------*/
27 | #include "main.h"
28 |
29 | /* USER CODE BEGIN Includes */
30 |
31 | /* USER CODE END Includes */
32 |
33 | extern UART_HandleTypeDef huart3;
34 |
35 | /* USER CODE BEGIN Private defines */
36 |
37 | /* USER CODE END Private defines */
38 |
39 | void MX_USART3_UART_Init(void);
40 |
41 | /* USER CODE BEGIN Prototypes */
42 |
43 | /* USER CODE END Prototypes */
44 |
45 | #ifdef __cplusplus
46 | }
47 | #endif
48 | #endif /*__ usart_H */
49 |
50 | /**
51 | * @}
52 | */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
59 |
--------------------------------------------------------------------------------
/MDK-ARM/DBUS/DBUS.lnp:
--------------------------------------------------------------------------------
1 | --cpu=Cortex-M4.fp.sp
2 | "dbus\startup_stm32f407xx.o"
3 | "dbus\main.o"
4 | "dbus\gpio.o"
5 | "dbus\can.o"
6 | "dbus\dma.o"
7 | "dbus\tim.o"
8 | "dbus\usart.o"
9 | "dbus\stm32f4xx_it.o"
10 | "dbus\stm32f4xx_hal_msp.o"
11 | "dbus\stm32f4xx_hal_can.o"
12 | "dbus\stm32f4xx_hal_rcc.o"
13 | "dbus\stm32f4xx_hal_rcc_ex.o"
14 | "dbus\stm32f4xx_hal_flash.o"
15 | "dbus\stm32f4xx_hal_flash_ex.o"
16 | "dbus\stm32f4xx_hal_flash_ramfunc.o"
17 | "dbus\stm32f4xx_hal_gpio.o"
18 | "dbus\stm32f4xx_hal_dma_ex.o"
19 | "dbus\stm32f4xx_hal_dma.o"
20 | "dbus\stm32f4xx_hal_pwr.o"
21 | "dbus\stm32f4xx_hal_pwr_ex.o"
22 | "dbus\stm32f4xx_hal_cortex.o"
23 | "dbus\stm32f4xx_hal.o"
24 | "dbus\stm32f4xx_hal_exti.o"
25 | "dbus\stm32f4xx_hal_tim.o"
26 | "dbus\stm32f4xx_hal_tim_ex.o"
27 | "dbus\stm32f4xx_hal_uart.o"
28 | "dbus\system_stm32f4xx.o"
29 | "dbus\bsp_can.o"
30 | "dbus\can_receive.o"
31 | --library_type=microlib --strict --scatter "DBUS\DBUS.sct"
32 | --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
33 | --info sizes --info totals --info unused --info veneers
34 | --list "DBUS.map" -o DBUS\DBUS.axf
--------------------------------------------------------------------------------
/MDK-ARM/DebugConfig/DBUS_STM32F407IGHx.dbgconf:
--------------------------------------------------------------------------------
1 | // File: STM32F405_415_407_417_427_437_429_439.dbgconf
2 | // Version: 1.0.0
3 | // Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
4 | // refer to STM32F40x STM32F41x datasheets
5 | // refer to STM32F42x STM32F43x datasheets
6 |
7 | // <<< Use Configuration Wizard in Context Menu >>>
8 |
9 | // Debug MCU configuration register (DBGMCU_CR)
10 | // DBG_STANDBY Debug Standby Mode
11 | // DBG_STOP Debug Stop Mode
12 | // DBG_SLEEP Debug Sleep Mode
13 | //
14 | DbgMCU_CR = 0x00000007;
15 |
16 | // Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
17 | // Reserved bits must be kept at reset value
18 | // DBG_CAN2_STOP CAN2 stopped when core is halted
19 | // DBG_CAN1_STOP CAN2 stopped when core is halted
20 | // DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS timeout mode stopped when core is halted
21 | // DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when core is halted
22 | // DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when core is halted
23 | // DBG_IWDG_STOP Independent watchdog stopped when core is halted
24 | // DBG_WWDG_STOP Window watchdog stopped when core is halted
25 | // DBG_RTC_STOP RTC stopped when core is halted
26 | // DBG_TIM14_STOP TIM14 counter stopped when core is halted
27 | // DBG_TIM13_STOP TIM13 counter stopped when core is halted
28 | // DBG_TIM12_STOP TIM12 counter stopped when core is halted
29 | // DBG_TIM7_STOP TIM7 counter stopped when core is halted
30 | // DBG_TIM6_STOP TIM6 counter stopped when core is halted
31 | // DBG_TIM5_STOP TIM5 counter stopped when core is halted
32 | // DBG_TIM4_STOP TIM4 counter stopped when core is halted
33 | // DBG_TIM3_STOP TIM3 counter stopped when core is halted
34 | // DBG_TIM2_STOP TIM2 counter stopped when core is halted
35 | //
36 | DbgMCU_APB1_Fz = 0x00000000;
37 |
38 | // Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
39 | // Reserved bits must be kept at reset value
40 | // DBG_TIM11_STOP TIM11 counter stopped when core is halted
41 | // DBG_TIM10_STOP TIM10 counter stopped when core is halted
42 | // DBG_TIM9_STOP TIM9 counter stopped when core is halted
43 | // DBG_TIM8_STOP TIM8 counter stopped when core is halted
44 | // DBG_TIM1_STOP TIM1 counter stopped when core is halted
45 | //
46 | DbgMCU_APB2_Fz = 0x00000000;
47 |
48 | // <<< end of configuration section >>>
--------------------------------------------------------------------------------
/MDK-ARM/EventRecorderStub.scvd:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
--------------------------------------------------------------------------------
/MDK-ARM/RTE/_DBUS/RTE_Components.h:
--------------------------------------------------------------------------------
1 |
2 | /*
3 | * Auto generated Run-Time-Environment Configuration File
4 | * *** Do not modify ! ***
5 | *
6 | * Project: 'DBUS'
7 | * Target: 'DBUS'
8 | */
9 |
10 | #ifndef RTE_COMPONENTS_H
11 | #define RTE_COMPONENTS_H
12 |
13 |
14 | /*
15 | * Define the Device Header File:
16 | */
17 | #define CMSIS_device_header "stm32f4xx.h"
18 |
19 |
20 |
21 | #endif /* RTE_COMPONENTS_H */
22 |
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | # TypeC_Lesson4_CANbusAndMotor
2 | 电控课程4 CAN总线与电机
3 |
--------------------------------------------------------------------------------
/Src/can.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : CAN.c
4 | * Description : This file provides code for the configuration
5 | * of the CAN instances.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "can.h"
22 |
23 | /* USER CODE BEGIN 0 */
24 |
25 | /* USER CODE END 0 */
26 |
27 | CAN_HandleTypeDef hcan1;
28 | CAN_HandleTypeDef hcan2;
29 |
30 | /* CAN1 init function */
31 | void MX_CAN1_Init(void)
32 | {
33 |
34 | hcan1.Instance = CAN1;
35 | hcan1.Init.Prescaler = 3;
36 | hcan1.Init.Mode = CAN_MODE_NORMAL;
37 | hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ;
38 | hcan1.Init.TimeSeg1 = CAN_BS1_10TQ;
39 | hcan1.Init.TimeSeg2 = CAN_BS2_3TQ;
40 | hcan1.Init.TimeTriggeredMode = DISABLE;
41 | hcan1.Init.AutoBusOff = DISABLE;
42 | hcan1.Init.AutoWakeUp = DISABLE;
43 | hcan1.Init.AutoRetransmission = DISABLE;
44 | hcan1.Init.ReceiveFifoLocked = DISABLE;
45 | hcan1.Init.TransmitFifoPriority = DISABLE;
46 | if (HAL_CAN_Init(&hcan1) != HAL_OK)
47 | {
48 | Error_Handler();
49 | }
50 |
51 | }
52 | /* CAN2 init function */
53 | void MX_CAN2_Init(void)
54 | {
55 |
56 | hcan2.Instance = CAN2;
57 | hcan2.Init.Prescaler = 3;
58 | hcan2.Init.Mode = CAN_MODE_NORMAL;
59 | hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ;
60 | hcan2.Init.TimeSeg1 = CAN_BS1_10TQ;
61 | hcan2.Init.TimeSeg2 = CAN_BS2_3TQ;
62 | hcan2.Init.TimeTriggeredMode = DISABLE;
63 | hcan2.Init.AutoBusOff = DISABLE;
64 | hcan2.Init.AutoWakeUp = DISABLE;
65 | hcan2.Init.AutoRetransmission = DISABLE;
66 | hcan2.Init.ReceiveFifoLocked = DISABLE;
67 | hcan2.Init.TransmitFifoPriority = DISABLE;
68 | if (HAL_CAN_Init(&hcan2) != HAL_OK)
69 | {
70 | Error_Handler();
71 | }
72 |
73 | }
74 |
75 | static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0;
76 |
77 | void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle)
78 | {
79 |
80 | GPIO_InitTypeDef GPIO_InitStruct = {0};
81 | if(canHandle->Instance==CAN1)
82 | {
83 | /* USER CODE BEGIN CAN1_MspInit 0 */
84 |
85 | /* USER CODE END CAN1_MspInit 0 */
86 | /* CAN1 clock enable */
87 | HAL_RCC_CAN1_CLK_ENABLED++;
88 | if(HAL_RCC_CAN1_CLK_ENABLED==1){
89 | __HAL_RCC_CAN1_CLK_ENABLE();
90 | }
91 |
92 | __HAL_RCC_GPIOD_CLK_ENABLE();
93 | /**CAN1 GPIO Configuration
94 | PD0 ------> CAN1_RX
95 | PD1 ------> CAN1_TX
96 | */
97 | GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
98 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
99 | GPIO_InitStruct.Pull = GPIO_NOPULL;
100 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
101 | GPIO_InitStruct.Alternate = GPIO_AF9_CAN1;
102 | HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
103 |
104 | /* CAN1 interrupt Init */
105 | HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0);
106 | HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn);
107 | /* USER CODE BEGIN CAN1_MspInit 1 */
108 |
109 | /* USER CODE END CAN1_MspInit 1 */
110 | }
111 | else if(canHandle->Instance==CAN2)
112 | {
113 | /* USER CODE BEGIN CAN2_MspInit 0 */
114 |
115 | /* USER CODE END CAN2_MspInit 0 */
116 | /* CAN2 clock enable */
117 | __HAL_RCC_CAN2_CLK_ENABLE();
118 | HAL_RCC_CAN1_CLK_ENABLED++;
119 | if(HAL_RCC_CAN1_CLK_ENABLED==1){
120 | __HAL_RCC_CAN1_CLK_ENABLE();
121 | }
122 |
123 | __HAL_RCC_GPIOB_CLK_ENABLE();
124 | /**CAN2 GPIO Configuration
125 | PB5 ------> CAN2_RX
126 | PB6 ------> CAN2_TX
127 | */
128 | GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6;
129 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
130 | GPIO_InitStruct.Pull = GPIO_NOPULL;
131 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
132 | GPIO_InitStruct.Alternate = GPIO_AF9_CAN2;
133 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
134 |
135 | /* CAN2 interrupt Init */
136 | HAL_NVIC_SetPriority(CAN2_RX0_IRQn, 0, 0);
137 | HAL_NVIC_EnableIRQ(CAN2_RX0_IRQn);
138 | /* USER CODE BEGIN CAN2_MspInit 1 */
139 |
140 | /* USER CODE END CAN2_MspInit 1 */
141 | }
142 | }
143 |
144 | void HAL_CAN_MspDeInit(CAN_HandleTypeDef* canHandle)
145 | {
146 |
147 | if(canHandle->Instance==CAN1)
148 | {
149 | /* USER CODE BEGIN CAN1_MspDeInit 0 */
150 |
151 | /* USER CODE END CAN1_MspDeInit 0 */
152 | /* Peripheral clock disable */
153 | HAL_RCC_CAN1_CLK_ENABLED--;
154 | if(HAL_RCC_CAN1_CLK_ENABLED==0){
155 | __HAL_RCC_CAN1_CLK_DISABLE();
156 | }
157 |
158 | /**CAN1 GPIO Configuration
159 | PD0 ------> CAN1_RX
160 | PD1 ------> CAN1_TX
161 | */
162 | HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1);
163 |
164 | /* CAN1 interrupt Deinit */
165 | HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn);
166 | /* USER CODE BEGIN CAN1_MspDeInit 1 */
167 |
168 | /* USER CODE END CAN1_MspDeInit 1 */
169 | }
170 | else if(canHandle->Instance==CAN2)
171 | {
172 | /* USER CODE BEGIN CAN2_MspDeInit 0 */
173 |
174 | /* USER CODE END CAN2_MspDeInit 0 */
175 | /* Peripheral clock disable */
176 | __HAL_RCC_CAN2_CLK_DISABLE();
177 | HAL_RCC_CAN1_CLK_ENABLED--;
178 | if(HAL_RCC_CAN1_CLK_ENABLED==0){
179 | __HAL_RCC_CAN1_CLK_DISABLE();
180 | }
181 |
182 | /**CAN2 GPIO Configuration
183 | PB5 ------> CAN2_RX
184 | PB6 ------> CAN2_TX
185 | */
186 | HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5|GPIO_PIN_6);
187 |
188 | /* CAN2 interrupt Deinit */
189 | HAL_NVIC_DisableIRQ(CAN2_RX0_IRQn);
190 | /* USER CODE BEGIN CAN2_MspDeInit 1 */
191 |
192 | /* USER CODE END CAN2_MspDeInit 1 */
193 | }
194 | }
195 |
196 | /* USER CODE BEGIN 1 */
197 |
198 | /* USER CODE END 1 */
199 |
200 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
201 |
--------------------------------------------------------------------------------
/Src/dma.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : dma.c
4 | * Description : This file provides code for the configuration
5 | * of all the requested memory to memory DMA transfers.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "dma.h"
22 |
23 | /* USER CODE BEGIN 0 */
24 |
25 | /* USER CODE END 0 */
26 |
27 | /*----------------------------------------------------------------------------*/
28 | /* Configure DMA */
29 | /*----------------------------------------------------------------------------*/
30 |
31 | /* USER CODE BEGIN 1 */
32 |
33 | /* USER CODE END 1 */
34 |
35 | /**
36 | * Enable DMA controller clock
37 | */
38 | void MX_DMA_Init(void)
39 | {
40 |
41 | /* DMA controller clock enable */
42 | __HAL_RCC_DMA1_CLK_ENABLE();
43 |
44 | /* DMA interrupt init */
45 | /* DMA1_Stream1_IRQn interrupt configuration */
46 | HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 0, 0);
47 | HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
48 |
49 | }
50 |
51 | /* USER CODE BEGIN 2 */
52 |
53 | /* USER CODE END 2 */
54 |
55 | /**
56 | * @}
57 | */
58 |
59 | /**
60 | * @}
61 | */
62 |
63 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
64 |
--------------------------------------------------------------------------------
/Src/gpio.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : gpio.c
4 | * Description : This file provides code for the configuration
5 | * of all used GPIO pins.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "gpio.h"
22 | /* USER CODE BEGIN 0 */
23 |
24 | /* USER CODE END 0 */
25 |
26 | /*----------------------------------------------------------------------------*/
27 | /* Configure GPIO */
28 | /*----------------------------------------------------------------------------*/
29 | /* USER CODE BEGIN 1 */
30 |
31 | /* USER CODE END 1 */
32 |
33 | /** Configure pins as
34 | * Analog
35 | * Input
36 | * Output
37 | * EVENT_OUT
38 | * EXTI
39 | */
40 | void MX_GPIO_Init(void)
41 | {
42 |
43 | /* GPIO Ports Clock Enable */
44 | __HAL_RCC_GPIOB_CLK_ENABLE();
45 | __HAL_RCC_GPIOA_CLK_ENABLE();
46 | __HAL_RCC_GPIOD_CLK_ENABLE();
47 | __HAL_RCC_GPIOC_CLK_ENABLE();
48 | __HAL_RCC_GPIOI_CLK_ENABLE();
49 | __HAL_RCC_GPIOH_CLK_ENABLE();
50 | __HAL_RCC_GPIOE_CLK_ENABLE();
51 |
52 | }
53 |
54 | /* USER CODE BEGIN 2 */
55 |
56 | /* USER CODE END 2 */
57 |
58 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
59 |
--------------------------------------------------------------------------------
/Src/main.c:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/JohnsonGu/TypeC_Lesson4_CANbusAndMotor/6e45f660d0a89b7a1d0ad38be3fa657768792646/Src/main.c
--------------------------------------------------------------------------------
/Src/stm32f4xx_hal_msp.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * File Name : stm32f4xx_hal_msp.c
5 | * Description : This file provides code for the MSP Initialization
6 | * and de-Initialization codes.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2020 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "main.h"
24 | /* USER CODE BEGIN Includes */
25 |
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN Define */
35 |
36 | /* USER CODE END Define */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN Macro */
40 |
41 | /* USER CODE END Macro */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* External functions --------------------------------------------------------*/
54 | /* USER CODE BEGIN ExternalFunctions */
55 |
56 | /* USER CODE END ExternalFunctions */
57 |
58 | /* USER CODE BEGIN 0 */
59 |
60 | /* USER CODE END 0 */
61 | /**
62 | * Initializes the Global MSP.
63 | */
64 | void HAL_MspInit(void)
65 | {
66 | /* USER CODE BEGIN MspInit 0 */
67 |
68 | /* USER CODE END MspInit 0 */
69 |
70 | __HAL_RCC_SYSCFG_CLK_ENABLE();
71 | __HAL_RCC_PWR_CLK_ENABLE();
72 |
73 | /* System interrupt init*/
74 |
75 | /* USER CODE BEGIN MspInit 1 */
76 |
77 | /* USER CODE END MspInit 1 */
78 | }
79 |
80 | /* USER CODE BEGIN 1 */
81 |
82 | /* USER CODE END 1 */
83 |
84 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
85 |
--------------------------------------------------------------------------------
/Src/stm32f4xx_it.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f4xx_it.c
5 | * @brief Interrupt Service Routines.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "main.h"
23 | #include "stm32f4xx_it.h"
24 | /* Private includes ----------------------------------------------------------*/
25 | /* USER CODE BEGIN Includes */
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN PD */
35 |
36 | /* USER CODE END PD */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN PM */
40 |
41 | /* USER CODE END PM */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* Private user code ---------------------------------------------------------*/
54 | /* USER CODE BEGIN 0 */
55 |
56 | /* USER CODE END 0 */
57 |
58 | /* External variables --------------------------------------------------------*/
59 | extern CAN_HandleTypeDef hcan1;
60 | extern CAN_HandleTypeDef hcan2;
61 | extern DMA_HandleTypeDef hdma_usart3_rx;
62 | /* USER CODE BEGIN EV */
63 |
64 | /* USER CODE END EV */
65 |
66 | /******************************************************************************/
67 | /* Cortex-M4 Processor Interruption and Exception Handlers */
68 | /******************************************************************************/
69 | /**
70 | * @brief This function handles Non maskable interrupt.
71 | */
72 | void NMI_Handler(void)
73 | {
74 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
75 |
76 | /* USER CODE END NonMaskableInt_IRQn 0 */
77 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
78 |
79 | /* USER CODE END NonMaskableInt_IRQn 1 */
80 | }
81 |
82 | /**
83 | * @brief This function handles Hard fault interrupt.
84 | */
85 | void HardFault_Handler(void)
86 | {
87 | /* USER CODE BEGIN HardFault_IRQn 0 */
88 |
89 | /* USER CODE END HardFault_IRQn 0 */
90 | while (1)
91 | {
92 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */
93 | /* USER CODE END W1_HardFault_IRQn 0 */
94 | }
95 | }
96 |
97 | /**
98 | * @brief This function handles Memory management fault.
99 | */
100 | void MemManage_Handler(void)
101 | {
102 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */
103 |
104 | /* USER CODE END MemoryManagement_IRQn 0 */
105 | while (1)
106 | {
107 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
108 | /* USER CODE END W1_MemoryManagement_IRQn 0 */
109 | }
110 | }
111 |
112 | /**
113 | * @brief This function handles Pre-fetch fault, memory access fault.
114 | */
115 | void BusFault_Handler(void)
116 | {
117 | /* USER CODE BEGIN BusFault_IRQn 0 */
118 |
119 | /* USER CODE END BusFault_IRQn 0 */
120 | while (1)
121 | {
122 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */
123 | /* USER CODE END W1_BusFault_IRQn 0 */
124 | }
125 | }
126 |
127 | /**
128 | * @brief This function handles Undefined instruction or illegal state.
129 | */
130 | void UsageFault_Handler(void)
131 | {
132 | /* USER CODE BEGIN UsageFault_IRQn 0 */
133 |
134 | /* USER CODE END UsageFault_IRQn 0 */
135 | while (1)
136 | {
137 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
138 | /* USER CODE END W1_UsageFault_IRQn 0 */
139 | }
140 | }
141 |
142 | /**
143 | * @brief This function handles Debug monitor.
144 | */
145 | void DebugMon_Handler(void)
146 | {
147 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */
148 |
149 | /* USER CODE END DebugMonitor_IRQn 0 */
150 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */
151 |
152 | /* USER CODE END DebugMonitor_IRQn 1 */
153 | }
154 |
155 | /**
156 | * @brief This function handles System tick timer.
157 | */
158 | void SysTick_Handler(void)
159 | {
160 | /* USER CODE BEGIN SysTick_IRQn 0 */
161 |
162 | /* USER CODE END SysTick_IRQn 0 */
163 | HAL_IncTick();
164 | /* USER CODE BEGIN SysTick_IRQn 1 */
165 |
166 | /* USER CODE END SysTick_IRQn 1 */
167 | }
168 |
169 | /******************************************************************************/
170 | /* STM32F4xx Peripheral Interrupt Handlers */
171 | /* Add here the Interrupt Handlers for the used peripherals. */
172 | /* For the available peripheral interrupt handler names, */
173 | /* please refer to the startup file (startup_stm32f4xx.s). */
174 | /******************************************************************************/
175 |
176 | /**
177 | * @brief This function handles DMA1 stream1 global interrupt.
178 | */
179 | void DMA1_Stream1_IRQHandler(void)
180 | {
181 | /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */
182 |
183 | /* USER CODE END DMA1_Stream1_IRQn 0 */
184 | HAL_DMA_IRQHandler(&hdma_usart3_rx);
185 | /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */
186 |
187 | /* USER CODE END DMA1_Stream1_IRQn 1 */
188 | }
189 |
190 | /**
191 | * @brief This function handles CAN1 RX0 interrupts.
192 | */
193 | void CAN1_RX0_IRQHandler(void)
194 | {
195 | /* USER CODE BEGIN CAN1_RX0_IRQn 0 */
196 |
197 | /* USER CODE END CAN1_RX0_IRQn 0 */
198 | HAL_CAN_IRQHandler(&hcan1);
199 | /* USER CODE BEGIN CAN1_RX0_IRQn 1 */
200 |
201 | /* USER CODE END CAN1_RX0_IRQn 1 */
202 | }
203 |
204 | /**
205 | * @brief This function handles CAN2 RX0 interrupts.
206 | */
207 | void CAN2_RX0_IRQHandler(void)
208 | {
209 | /* USER CODE BEGIN CAN2_RX0_IRQn 0 */
210 |
211 | /* USER CODE END CAN2_RX0_IRQn 0 */
212 | HAL_CAN_IRQHandler(&hcan2);
213 | /* USER CODE BEGIN CAN2_RX0_IRQn 1 */
214 |
215 | /* USER CODE END CAN2_RX0_IRQn 1 */
216 | }
217 |
218 | /* USER CODE BEGIN 1 */
219 |
220 | /* USER CODE END 1 */
221 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
222 |
--------------------------------------------------------------------------------
/Src/tim.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : TIM.c
4 | * Description : This file provides code for the configuration
5 | * of the TIM instances.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "tim.h"
22 |
23 | /* USER CODE BEGIN 0 */
24 |
25 | /* USER CODE END 0 */
26 |
27 | TIM_HandleTypeDef htim1;
28 | TIM_HandleTypeDef htim8;
29 |
30 | /* TIM1 init function */
31 | void MX_TIM1_Init(void)
32 | {
33 | TIM_ClockConfigTypeDef sClockSourceConfig = {0};
34 | TIM_MasterConfigTypeDef sMasterConfig = {0};
35 | TIM_OC_InitTypeDef sConfigOC = {0};
36 | TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
37 |
38 | htim1.Instance = TIM1;
39 | htim1.Init.Prescaler = 167;
40 | htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
41 | htim1.Init.Period = 19999;
42 | htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
43 | htim1.Init.RepetitionCounter = 0;
44 | htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
45 | if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
46 | {
47 | Error_Handler();
48 | }
49 | sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
50 | if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
51 | {
52 | Error_Handler();
53 | }
54 | if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
55 | {
56 | Error_Handler();
57 | }
58 | sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
59 | sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
60 | if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
61 | {
62 | Error_Handler();
63 | }
64 | sConfigOC.OCMode = TIM_OCMODE_PWM1;
65 | sConfigOC.Pulse = 2000;
66 | sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
67 | sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
68 | sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
69 | sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
70 | sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
71 | if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
72 | {
73 | Error_Handler();
74 | }
75 | if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
76 | {
77 | Error_Handler();
78 | }
79 | if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
80 | {
81 | Error_Handler();
82 | }
83 | if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
84 | {
85 | Error_Handler();
86 | }
87 | sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
88 | sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
89 | sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
90 | sBreakDeadTimeConfig.DeadTime = 0;
91 | sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
92 | sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
93 | sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
94 | if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
95 | {
96 | Error_Handler();
97 | }
98 | HAL_TIM_MspPostInit(&htim1);
99 |
100 | }
101 | /* TIM8 init function */
102 | void MX_TIM8_Init(void)
103 | {
104 | TIM_ClockConfigTypeDef sClockSourceConfig = {0};
105 | TIM_MasterConfigTypeDef sMasterConfig = {0};
106 | TIM_OC_InitTypeDef sConfigOC = {0};
107 | TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
108 |
109 | htim8.Instance = TIM8;
110 | htim8.Init.Prescaler = 167;
111 | htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
112 | htim8.Init.Period = 19999;
113 | htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
114 | htim8.Init.RepetitionCounter = 0;
115 | htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
116 | if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
117 | {
118 | Error_Handler();
119 | }
120 | sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
121 | if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
122 | {
123 | Error_Handler();
124 | }
125 | if (HAL_TIM_PWM_Init(&htim8) != HAL_OK)
126 | {
127 | Error_Handler();
128 | }
129 | sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
130 | sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
131 | if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
132 | {
133 | Error_Handler();
134 | }
135 | sConfigOC.OCMode = TIM_OCMODE_PWM1;
136 | sConfigOC.Pulse = 2000;
137 | sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
138 | sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
139 | sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
140 | sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
141 | sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
142 | if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
143 | {
144 | Error_Handler();
145 | }
146 | if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
147 | {
148 | Error_Handler();
149 | }
150 | if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
151 | {
152 | Error_Handler();
153 | }
154 | sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
155 | sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
156 | sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
157 | sBreakDeadTimeConfig.DeadTime = 0;
158 | sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
159 | sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
160 | sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
161 | if (HAL_TIMEx_ConfigBreakDeadTime(&htim8, &sBreakDeadTimeConfig) != HAL_OK)
162 | {
163 | Error_Handler();
164 | }
165 | HAL_TIM_MspPostInit(&htim8);
166 |
167 | }
168 |
169 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
170 | {
171 |
172 | if(tim_baseHandle->Instance==TIM1)
173 | {
174 | /* USER CODE BEGIN TIM1_MspInit 0 */
175 |
176 | /* USER CODE END TIM1_MspInit 0 */
177 | /* TIM1 clock enable */
178 | __HAL_RCC_TIM1_CLK_ENABLE();
179 | /* USER CODE BEGIN TIM1_MspInit 1 */
180 |
181 | /* USER CODE END TIM1_MspInit 1 */
182 | }
183 | else if(tim_baseHandle->Instance==TIM8)
184 | {
185 | /* USER CODE BEGIN TIM8_MspInit 0 */
186 |
187 | /* USER CODE END TIM8_MspInit 0 */
188 | /* TIM8 clock enable */
189 | __HAL_RCC_TIM8_CLK_ENABLE();
190 | /* USER CODE BEGIN TIM8_MspInit 1 */
191 |
192 | /* USER CODE END TIM8_MspInit 1 */
193 | }
194 | }
195 | void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
196 | {
197 |
198 | GPIO_InitTypeDef GPIO_InitStruct = {0};
199 | if(timHandle->Instance==TIM1)
200 | {
201 | /* USER CODE BEGIN TIM1_MspPostInit 0 */
202 |
203 | /* USER CODE END TIM1_MspPostInit 0 */
204 | __HAL_RCC_GPIOE_CLK_ENABLE();
205 | /**TIM1 GPIO Configuration
206 | PE13 ------> TIM1_CH3
207 | PE9 ------> TIM1_CH1
208 | PE11 ------> TIM1_CH2
209 | PE14 ------> TIM1_CH4
210 | */
211 | GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_9|GPIO_PIN_11|GPIO_PIN_14;
212 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
213 | GPIO_InitStruct.Pull = GPIO_PULLUP;
214 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
215 | GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
216 | HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
217 |
218 | /* USER CODE BEGIN TIM1_MspPostInit 1 */
219 |
220 | /* USER CODE END TIM1_MspPostInit 1 */
221 | }
222 | else if(timHandle->Instance==TIM8)
223 | {
224 | /* USER CODE BEGIN TIM8_MspPostInit 0 */
225 |
226 | /* USER CODE END TIM8_MspPostInit 0 */
227 |
228 | __HAL_RCC_GPIOI_CLK_ENABLE();
229 | __HAL_RCC_GPIOC_CLK_ENABLE();
230 | /**TIM8 GPIO Configuration
231 | PI7 ------> TIM8_CH3
232 | PI6 ------> TIM8_CH2
233 | PC6 ------> TIM8_CH1
234 | */
235 | GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6;
236 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
237 | GPIO_InitStruct.Pull = GPIO_PULLUP;
238 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
239 | GPIO_InitStruct.Alternate = GPIO_AF3_TIM8;
240 | HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
241 |
242 | GPIO_InitStruct.Pin = GPIO_PIN_6;
243 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
244 | GPIO_InitStruct.Pull = GPIO_PULLUP;
245 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
246 | GPIO_InitStruct.Alternate = GPIO_AF3_TIM8;
247 | HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
248 |
249 | /* USER CODE BEGIN TIM8_MspPostInit 1 */
250 |
251 | /* USER CODE END TIM8_MspPostInit 1 */
252 | }
253 |
254 | }
255 |
256 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
257 | {
258 |
259 | if(tim_baseHandle->Instance==TIM1)
260 | {
261 | /* USER CODE BEGIN TIM1_MspDeInit 0 */
262 |
263 | /* USER CODE END TIM1_MspDeInit 0 */
264 | /* Peripheral clock disable */
265 | __HAL_RCC_TIM1_CLK_DISABLE();
266 | /* USER CODE BEGIN TIM1_MspDeInit 1 */
267 |
268 | /* USER CODE END TIM1_MspDeInit 1 */
269 | }
270 | else if(tim_baseHandle->Instance==TIM8)
271 | {
272 | /* USER CODE BEGIN TIM8_MspDeInit 0 */
273 |
274 | /* USER CODE END TIM8_MspDeInit 0 */
275 | /* Peripheral clock disable */
276 | __HAL_RCC_TIM8_CLK_DISABLE();
277 | /* USER CODE BEGIN TIM8_MspDeInit 1 */
278 |
279 | /* USER CODE END TIM8_MspDeInit 1 */
280 | }
281 | }
282 |
283 | /* USER CODE BEGIN 1 */
284 |
285 | /* USER CODE END 1 */
286 |
287 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
288 |
--------------------------------------------------------------------------------
/Src/usart.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : USART.c
4 | * Description : This file provides code for the configuration
5 | * of the USART instances.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "usart.h"
22 |
23 | /* USER CODE BEGIN 0 */
24 |
25 | /* USER CODE END 0 */
26 |
27 | UART_HandleTypeDef huart3;
28 | DMA_HandleTypeDef hdma_usart3_rx;
29 |
30 | /* USART3 init function */
31 |
32 | void MX_USART3_UART_Init(void)
33 | {
34 |
35 | huart3.Instance = USART3;
36 | huart3.Init.BaudRate = 100000;
37 | huart3.Init.WordLength = UART_WORDLENGTH_9B;
38 | huart3.Init.StopBits = UART_STOPBITS_1;
39 | huart3.Init.Parity = UART_PARITY_EVEN;
40 | huart3.Init.Mode = UART_MODE_TX_RX;
41 | huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
42 | huart3.Init.OverSampling = UART_OVERSAMPLING_16;
43 | if (HAL_UART_Init(&huart3) != HAL_OK)
44 | {
45 | Error_Handler();
46 | }
47 |
48 | }
49 |
50 | void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
51 | {
52 |
53 | GPIO_InitTypeDef GPIO_InitStruct = {0};
54 | if(uartHandle->Instance==USART3)
55 | {
56 | /* USER CODE BEGIN USART3_MspInit 0 */
57 |
58 | /* USER CODE END USART3_MspInit 0 */
59 | /* USART3 clock enable */
60 | __HAL_RCC_USART3_CLK_ENABLE();
61 |
62 | __HAL_RCC_GPIOC_CLK_ENABLE();
63 | /**USART3 GPIO Configuration
64 | PC11 ------> USART3_RX
65 | PC10 ------> USART3_TX
66 | */
67 | GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_10;
68 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
69 | GPIO_InitStruct.Pull = GPIO_NOPULL;
70 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
71 | GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
72 | HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
73 |
74 | /* USART3 DMA Init */
75 | /* USART3_RX Init */
76 | hdma_usart3_rx.Instance = DMA1_Stream1;
77 | hdma_usart3_rx.Init.Channel = DMA_CHANNEL_4;
78 | hdma_usart3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
79 | hdma_usart3_rx.Init.PeriphInc = DMA_PINC_DISABLE;
80 | hdma_usart3_rx.Init.MemInc = DMA_MINC_ENABLE;
81 | hdma_usart3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
82 | hdma_usart3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
83 | hdma_usart3_rx.Init.Mode = DMA_CIRCULAR;
84 | hdma_usart3_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH;
85 | hdma_usart3_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
86 | if (HAL_DMA_Init(&hdma_usart3_rx) != HAL_OK)
87 | {
88 | Error_Handler();
89 | }
90 |
91 | __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart3_rx);
92 |
93 | /* USER CODE BEGIN USART3_MspInit 1 */
94 |
95 | /* USER CODE END USART3_MspInit 1 */
96 | }
97 | }
98 |
99 | void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
100 | {
101 |
102 | if(uartHandle->Instance==USART3)
103 | {
104 | /* USER CODE BEGIN USART3_MspDeInit 0 */
105 |
106 | /* USER CODE END USART3_MspDeInit 0 */
107 | /* Peripheral clock disable */
108 | __HAL_RCC_USART3_CLK_DISABLE();
109 |
110 | /**USART3 GPIO Configuration
111 | PC11 ------> USART3_RX
112 | PC10 ------> USART3_TX
113 | */
114 | HAL_GPIO_DeInit(GPIOC, GPIO_PIN_11|GPIO_PIN_10);
115 |
116 | /* USART3 DMA DeInit */
117 | HAL_DMA_DeInit(uartHandle->hdmarx);
118 | /* USER CODE BEGIN USART3_MspDeInit 1 */
119 |
120 | /* USER CODE END USART3_MspDeInit 1 */
121 | }
122 | }
123 |
124 | /* USER CODE BEGIN 1 */
125 |
126 | /* USER CODE END 1 */
127 |
128 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
129 |
--------------------------------------------------------------------------------
/application/CAN_receive.c:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/JohnsonGu/TypeC_Lesson4_CANbusAndMotor/6e45f660d0a89b7a1d0ad38be3fa657768792646/application/CAN_receive.c
--------------------------------------------------------------------------------
/application/CAN_receive.h:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/JohnsonGu/TypeC_Lesson4_CANbusAndMotor/6e45f660d0a89b7a1d0ad38be3fa657768792646/application/CAN_receive.h
--------------------------------------------------------------------------------
/application/struct_typedef.h:
--------------------------------------------------------------------------------
1 | #ifndef STRUCT_TYPEDEF_H
2 | #define STRUCT_TYPEDEF_H
3 |
4 |
5 | typedef signed char int8_t;
6 | typedef signed short int int16_t;
7 | typedef signed int int32_t;
8 | typedef signed long long int64_t;
9 |
10 | /* exact-width unsigned integer types */
11 | typedef unsigned char uint8_t;
12 | typedef unsigned short int uint16_t;
13 | typedef unsigned int uint32_t;
14 | typedef unsigned long long uint64_t;
15 | typedef unsigned char bool_t;
16 | typedef float fp32;
17 | typedef double fp64;
18 |
19 |
20 | #endif
21 |
22 |
23 |
24 |
--------------------------------------------------------------------------------
/boards/bsp_can.c:
--------------------------------------------------------------------------------
1 | #include "bsp_can.h"
2 | #include "main.h"
3 |
4 |
5 | extern CAN_HandleTypeDef hcan1;
6 | extern CAN_HandleTypeDef hcan2;
7 |
8 | void can_filter_init(void)
9 | {
10 |
11 | CAN_FilterTypeDef can_filter_st;
12 | can_filter_st.FilterActivation = ENABLE;
13 | can_filter_st.FilterMode = CAN_FILTERMODE_IDMASK;
14 | can_filter_st.FilterScale = CAN_FILTERSCALE_32BIT;
15 | can_filter_st.FilterIdHigh = 0x0000;
16 | can_filter_st.FilterIdLow = 0x0000;
17 | can_filter_st.FilterMaskIdHigh = 0x0000;
18 | can_filter_st.FilterMaskIdLow = 0x0000;
19 | can_filter_st.FilterBank = 0;
20 | can_filter_st.FilterFIFOAssignment = CAN_RX_FIFO0;
21 | HAL_CAN_ConfigFilter(&hcan1, &can_filter_st);
22 | HAL_CAN_Start(&hcan1);
23 | HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING);
24 |
25 |
26 | can_filter_st.SlaveStartFilterBank = 14;
27 | can_filter_st.FilterBank = 14;
28 | HAL_CAN_ConfigFilter(&hcan2, &can_filter_st);
29 | HAL_CAN_Start(&hcan2);
30 | HAL_CAN_ActivateNotification(&hcan2, CAN_IT_RX_FIFO0_MSG_PENDING);
31 |
32 |
33 |
34 | }
35 |
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/boards/bsp_can.h:
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1 | #ifndef BSP_CAN_H
2 | #define BSP_CAN_H
3 | #include "struct_typedef.h"
4 |
5 |
6 | extern void can_filter_init(void);
7 |
8 | #endif
9 |
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/keilkilll.bat:
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https://raw.githubusercontent.com/JohnsonGu/TypeC_Lesson4_CANbusAndMotor/6e45f660d0a89b7a1d0ad38be3fa657768792646/keilkilll.bat
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/课程5、CAN总线与电机.docx:
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https://raw.githubusercontent.com/JohnsonGu/TypeC_Lesson4_CANbusAndMotor/6e45f660d0a89b7a1d0ad38be3fa657768792646/课程5、CAN总线与电机.docx
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