├── .gitignore ├── Cpu0_replace_select ├── Cpu0 │ ├── AsmParser │ │ ├── CMakeLists.txt │ │ ├── Cpu0AsmParser.cpp │ │ └── LLVMBuild.txt │ ├── CMakeLists.txt │ ├── Cpu0.h │ ├── Cpu0.td │ ├── Cpu0AnalyzeImmediate.cpp │ ├── Cpu0AnalyzeImmediate.h │ ├── Cpu0AsmPrinter.cpp │ ├── Cpu0AsmPrinter.h │ ├── Cpu0CallingConv.td │ ├── Cpu0DelUselessJMP.cpp │ ├── Cpu0EmitGPRestore.cpp │ ├── Cpu0FrameLowering.cpp │ ├── Cpu0FrameLowering.h │ ├── Cpu0ISelDAGToDAG.cpp │ ├── Cpu0ISelLowering.cpp │ ├── Cpu0ISelLowering.h │ ├── Cpu0InstrFormats.td │ ├── Cpu0InstrInfo.cpp │ ├── Cpu0InstrInfo.h │ ├── Cpu0InstrInfo.td │ ├── Cpu0MCInstLower.cpp │ ├── Cpu0MCInstLower.h │ ├── Cpu0MachineFunction.cpp │ ├── Cpu0MachineFunction.h │ ├── Cpu0RegisterInfo.cpp │ ├── Cpu0RegisterInfo.h │ ├── Cpu0RegisterInfo.td │ ├── Cpu0ReplaceSelect.cpp │ ├── Cpu0Schedule.td │ ├── Cpu0SelectionDAGInfo.cpp │ ├── Cpu0SelectionDAGInfo.h │ ├── Cpu0Subtarget.cpp │ ├── Cpu0Subtarget.h │ ├── Cpu0TargetMachine.cpp │ ├── Cpu0TargetMachine.h │ ├── Cpu0TargetObjectFile.cpp │ ├── Cpu0TargetObjectFile.h │ ├── Disassembler │ │ ├── CMakeLists.txt │ │ ├── Cpu0Disassembler.cpp │ │ └── LLVMBuild.txt │ ├── InstPrinter │ │ ├── CMakeLists.txt │ │ ├── Cpu0InstPrinter.cpp │ │ ├── Cpu0InstPrinter.h │ │ └── LLVMBuild.txt │ ├── LLVMBuild.txt │ ├── MCTargetDesc │ │ ├── CMakeLists.txt │ │ ├── Cpu0AsmBackend.cpp │ │ ├── Cpu0BaseInfo.h │ │ ├── Cpu0ELFObjectWriter.cpp │ │ ├── Cpu0FixupKinds.h │ │ ├── Cpu0MCAsmInfo.cpp │ │ ├── Cpu0MCAsmInfo.h │ │ ├── Cpu0MCCodeEmitter.cpp │ │ ├── Cpu0MCTargetDesc.cpp │ │ ├── Cpu0MCTargetDesc.h │ │ └── LLVMBuild.txt │ └── TargetInfo │ │ ├── CMakeLists.txt │ │ ├── Cpu0TargetInfo.cpp │ │ └── LLVMBuild.txt └── note ├── Fig ├── Author_ChineseName.png ├── README ├── about │ ├── BookContents.odg │ ├── lbd_and_lbt.gv │ └── lbd_and_lbt.png ├── asm │ ├── asmDfd.gv │ ├── asmDfd.png │ ├── asmDfdEx.gv │ ├── asmDfdEx.png │ ├── asmDfdEx2.gv │ ├── asmDfdEx2.png │ ├── asmDfdEx3.gv │ ├── asmDfdEx3.png │ └── asmFlow.gv ├── backendstructure │ ├── 1.png │ ├── 10.png │ ├── 2.png │ ├── 3.png │ ├── 4.png │ ├── 5.png │ ├── Chapter3_2.odg │ ├── asm-emit.gv │ ├── class_access_link.puml │ ├── cpu0-enc-struct.gv │ ├── cpu0-function.gv │ ├── dyn_reg.gv │ ├── dyn_reg.png │ ├── llvm-data-structure.gv │ ├── old.1.png │ ├── old.2.png │ ├── old.3.png │ ├── old.4.png │ └── printAsm.gv ├── c++ │ ├── Fig-19-10-book-dpc++.png │ └── Fig-19-9-book-dpc++.png ├── ctrlflow │ ├── 1.png │ ├── 5_stage_pipeline.png │ ├── cache_banks.png │ ├── ctrlflow_figure.odg │ └── super_pipeline.png ├── elf │ ├── 1.png │ ├── 2.odg │ ├── 2.png │ ├── 3.odg │ ├── 3.png │ └── disas.gv ├── funccall │ ├── 1.png │ ├── 2.png │ ├── 4.odg │ ├── 4.png │ ├── 5.odg │ ├── 5.png │ ├── 6.odg │ ├── 6.png │ ├── incoming-arg-O32.gv │ ├── incoming-arg-O32.png │ ├── incoming-arg-S32.gv │ ├── incoming-arg-S32.png │ ├── outgoing-arg-LowerCall.gv │ ├── outgoing-arg-LowerCall.png │ ├── outgoing-arg-S32.gv │ ├── outgoing-arg-S32.png │ ├── outgoing-arg-tailcall.gv │ ├── outgoing-arg-tailcall.png │ └── outgoing-arg1.png ├── genobj │ ├── 1.png │ ├── 10.png │ ├── 2.png │ ├── 3.png │ ├── 4.png │ ├── 5.png │ ├── 6.png │ ├── 7.png │ ├── 8.png │ ├── 9.png │ ├── callFunctions.gv │ ├── getBinaryCodeForInstr.gv │ ├── instEncodeDfd.gv │ └── obj-emit.gv ├── gpu │ ├── 2d-vector-inward.odt │ ├── 2d-vector-inward.png │ ├── 2d-vector-inward.tex │ ├── 3d-cross-product.png │ ├── 3d-polygon.png │ ├── OpenGL-pipeline.png │ ├── ViewFrustum.png │ ├── additive-colors.key │ ├── additive-colors.png │ ├── animation.key │ ├── animation.png │ ├── cross-product.png │ ├── db-vsync.png │ ├── driverSamplerTable.odg │ ├── driverSamplerTable.png │ ├── glsl-spirv.gv │ ├── gpu-block-diagram.png │ ├── gpu-driver-compiled.odg │ ├── gpu-driver-compiled.png │ ├── gpu-driver-role.key │ ├── gpu-driver-role.png │ ├── gpu-terms.png │ ├── graphic-cpu-gpu.png │ ├── graphic-gpu-csf.png │ ├── graphic-sw-stack.gv │ ├── grid.png │ ├── in-3d-object.png │ ├── inward-edge-normals.odt │ ├── inward-edge-normals.png │ ├── mem-o-hw.gv │ ├── memory.png │ ├── modeling1.png │ ├── ogl-pointing-outwards.key │ ├── ogl-pointing-outwards.png │ ├── opencl-to-spirv-offine-compilation.png │ ├── opencl_ml_graph.key │ ├── opencl_ml_graph.png │ ├── opengl-flow.gv │ ├── opengl_flow.odg │ ├── opengl_flow.png │ ├── polygon.png │ ├── pre-volta-1.png │ ├── rendering_pipeline.png │ ├── sampling_diagram.png │ ├── sampling_diagram_binding.png │ ├── short-rendering-pipeline.png │ ├── sm.png │ ├── sm2.png │ ├── spirv-deploy.gv │ ├── spirv-lang-layers.gv │ ├── sycl.png │ ├── threadblock.jpg │ ├── threads-lanes.png │ ├── trans-steps.png │ ├── volta-1.png │ └── volta-2.png ├── install │ ├── 10.png │ ├── 11.png │ ├── 12.png │ └── 2.png ├── lbdwork.gv ├── lbdwork.png ├── llvmstructure │ ├── 1.png │ ├── 11.png │ ├── 12.png │ ├── 13.png │ ├── 2.png │ ├── 3.png │ ├── 4.png │ ├── 5.png │ ├── 6.png │ ├── 7.png │ ├── 8.png │ ├── 9.png │ ├── DAG.gv │ ├── DAG.odp │ ├── SW.odg │ ├── cfg-ex.cpp │ ├── cfg-ex.dot │ ├── cfg-ex.ll │ ├── cpu0_arch.odp │ ├── dag-ex.gv │ ├── frontendTblGen.gv │ └── llvmTblGen.gv ├── npu │ ├── IREE-Architecture.png │ ├── IREE-Architecture.svg │ ├── conv_onnx.png │ ├── dlcompilersurvey.png │ ├── nnefeco.png │ ├── onnc.jpg │ ├── syclcompiler.png │ └── syclimp.png ├── otherinst │ ├── 1.png │ ├── 2.png │ ├── 3.odg │ ├── 3.png │ ├── 4.png │ ├── test_multv-view-dag-combine1-dags.dot │ ├── test_multv-view-isel-dags.dot │ └── test_multv-view-sched-dags.dot └── verilog │ ├── 1.png │ ├── introduction.odg │ └── verilog.gv ├── FutureWork.rst ├── Makefile ├── README.md ├── RSTQuickstart.rst ├── References ├── 01-triangles.cpp ├── c++ │ └── mem-order-ex1.cpp ├── llvm-ir-vs-gimple.html ├── null_pointer.cpp ├── short-math-guide.pdf ├── triangles.frag └── triangles.vert ├── Table ├── funccall │ └── 1.png └── llvmstructure │ ├── 1.png │ ├── 2.png │ ├── 3.png │ └── cpu0_instructions_table.odt ├── build-output.sh ├── check.sh ├── clean.sh ├── ex-build-test.sh ├── ex-chapters-build-test.sh ├── lbdex ├── Cpu0 │ ├── AsmParser │ │ ├── CMakeLists.txt │ │ └── Cpu0AsmParser.cpp │ ├── CMakeLists.txt │ ├── Cpu0.h │ ├── Cpu0.td │ ├── Cpu0AnalyzeImmediate.cpp │ ├── Cpu0AnalyzeImmediate.h │ ├── Cpu0Asm.td │ ├── Cpu0AsmPrinter.cpp │ ├── Cpu0AsmPrinter.h │ ├── Cpu0CallingConv.td │ ├── Cpu0CondMov.td │ ├── Cpu0Config.h │ ├── Cpu0DelUselessJMP.cpp │ ├── Cpu0DelaySlotFiller.cpp │ ├── Cpu0EmitGPRestore.cpp │ ├── Cpu0FrameLowering.cpp │ ├── Cpu0FrameLowering.h │ ├── Cpu0ISelDAGToDAG.cpp │ ├── Cpu0ISelDAGToDAG.h │ ├── Cpu0ISelLowering.cpp │ ├── Cpu0ISelLowering.h │ ├── Cpu0InstrFormats.td │ ├── Cpu0InstrInfo.cpp │ ├── Cpu0InstrInfo.h │ ├── Cpu0InstrInfo.td │ ├── Cpu0LongBranch.cpp │ ├── Cpu0MCInstLower.cpp │ ├── Cpu0MCInstLower.h │ ├── Cpu0MachineFunction.cpp │ ├── Cpu0MachineFunction.h │ ├── Cpu0Other.td │ ├── Cpu0RegisterInfo.cpp │ ├── Cpu0RegisterInfo.h │ ├── Cpu0RegisterInfo.td │ ├── Cpu0RegisterInfoGPROutForAsm.td │ ├── Cpu0RegisterInfoGPROutForOther.td │ ├── Cpu0SEFrameLowering.cpp │ ├── Cpu0SEFrameLowering.h │ ├── Cpu0SEISelDAGToDAG.cpp │ ├── Cpu0SEISelDAGToDAG.h │ ├── Cpu0SEISelLowering.cpp │ ├── Cpu0SEISelLowering.h │ ├── Cpu0SEInstrInfo.cpp │ ├── Cpu0SEInstrInfo.h │ ├── Cpu0SERegisterInfo.cpp │ ├── Cpu0SERegisterInfo.h │ ├── Cpu0Schedule.td │ ├── Cpu0SetChapter.h │ ├── Cpu0Subtarget.cpp │ ├── Cpu0Subtarget.h │ ├── Cpu0TargetMachine.cpp │ ├── Cpu0TargetMachine.h │ ├── Cpu0TargetObjectFile.cpp │ ├── Cpu0TargetObjectFile.h │ ├── Cpu0TargetStreamer.h │ ├── Disassembler │ │ ├── CMakeLists.txt │ │ └── Cpu0Disassembler.cpp │ ├── InstPrinter │ │ ├── CMakeLists.txt │ │ ├── Cpu0InstPrinter.cpp │ │ └── Cpu0InstPrinter.h │ ├── MCTargetDesc │ │ ├── CMakeLists.txt │ │ ├── Cpu0ABIInfo.cpp │ │ ├── Cpu0ABIInfo.h │ │ ├── Cpu0AsmBackend.cpp │ │ ├── Cpu0AsmBackend.h │ │ ├── Cpu0BaseInfo.h │ │ ├── Cpu0ELFObjectWriter.cpp │ │ ├── Cpu0FixupKinds.h │ │ ├── Cpu0MCAsmInfo.cpp │ │ ├── Cpu0MCAsmInfo.h │ │ ├── Cpu0MCCodeEmitter.cpp │ │ ├── Cpu0MCCodeEmitter.h │ │ ├── Cpu0MCExpr.cpp │ │ ├── Cpu0MCExpr.h │ │ ├── Cpu0MCTargetDesc.cpp │ │ ├── Cpu0MCTargetDesc.h │ │ └── Cpu0TargetStreamer.cpp │ └── TargetInfo │ │ ├── CMakeLists.txt │ │ └── Cpu0TargetInfo.cpp ├── Cpu0Gen │ ├── Cpu0GenAsmMatcher.inc │ ├── Cpu0GenAsmWriter.inc │ ├── Cpu0GenCallingConv.inc │ ├── Cpu0GenCodeEmitter.inc │ ├── Cpu0GenDAGISel.inc │ ├── Cpu0GenDisassemblerTables.inc │ ├── Cpu0GenInstrInfo.inc │ ├── Cpu0GenMCCodeEmitter.inc │ ├── Cpu0GenMCPseudoLowering.inc │ ├── Cpu0GenRegisterInfo.inc │ └── Cpu0GenSubtargetInfo.inc ├── build-cpu0.sh ├── build-llvm-test-suite.sh ├── clean.sh ├── cp-src-orig.sh ├── gen-chapters.sh ├── gen-docs-ref.sh ├── gen-ref-output.sh ├── input │ ├── atomic-ops.c │ ├── atomics-fences.ll │ ├── atomics.ll │ ├── boot.cpp │ ├── build-run_backend.sh │ ├── build-run_backend2.sh │ ├── ch11_1.cpp │ ├── ch11_1_2.cpp │ ├── ch11_2.cpp │ ├── ch12_atomics-fences.cpp │ ├── ch12_atomics-producer-consumer.cpp │ ├── ch12_atomics.cpp │ ├── ch12_atomics_memory_order.cpp │ ├── ch12_c++_atomics.cpp │ ├── ch12_eh.cpp │ ├── ch12_inherit.cpp │ ├── ch12_sema_atomic-fetch.c │ ├── ch12_sema_atomic-ops.c │ ├── ch12_swap.cpp │ ├── ch12_thread_var.cpp │ ├── ch13_1.cpp │ ├── ch3.cpp │ ├── ch3_2.cpp │ ├── ch3_largeframe.cpp │ ├── ch3_localarraylargeimm.cpp │ ├── ch4_1_addsuboverflow.cpp │ ├── ch4_1_div.cpp │ ├── ch4_1_math.cpp │ ├── ch4_1_mod.cpp │ ├── ch4_1_mult.cpp │ ├── ch4_1_mult2.cpp │ ├── ch4_1_rotate.cpp │ ├── ch4_1_sub.cpp │ ├── ch4_2_logic.cpp │ ├── ch4_2_slt_explain.cpp │ ├── ch4_math.ll │ ├── ch4_overflow.ll │ ├── ch6_1.cpp │ ├── ch7_1_array.cpp │ ├── ch7_1_bool.cpp │ ├── ch7_1_bool2.ll │ ├── ch7_1_char_in_struct.cpp │ ├── ch7_1_char_short.cpp │ ├── ch7_1_fmul.c │ ├── ch7_1_globalstructoffset.cpp │ ├── ch7_1_localarrayinit.cpp │ ├── ch7_1_localpointer.cpp │ ├── ch7_1_longlong.cpp │ ├── ch7_1_vector.cpp │ ├── ch8_1_1.cpp │ ├── ch8_1_blockaddr.cpp │ ├── ch8_1_br_jt.cpp │ ├── ch8_1_ctrl.cpp │ ├── ch8_2_deluselessjmp.cpp │ ├── ch8_2_longbranch.cpp │ ├── ch8_2_phinode.cpp │ ├── ch8_2_select.cpp │ ├── ch8_2_select2.cpp │ ├── ch8_2_select_global_pic.cpp │ ├── ch9_1.cpp │ ├── ch9_1_2.cpp │ ├── ch9_1_constructor.cpp │ ├── ch9_1_longlong.cpp │ ├── ch9_1_struct.cpp │ ├── ch9_2_tailcall.cpp │ ├── ch9_3_alloc.cpp │ ├── ch9_3_bswap.cpp │ ├── ch9_3_detect_exception.cpp │ ├── ch9_3_frame_return_addr.cpp │ ├── ch9_3_longlongshift.cpp │ ├── ch9_3_stacksave.cpp │ ├── ch9_3_template.cpp │ ├── ch9_3_vararg.cpp │ ├── ch9_caller_callee_save_registers.cpp │ ├── ch9_gprestore.cpp │ ├── ch9_incoming.cpp │ ├── ch9_outgoing.cpp │ ├── ch_arm-tailcall.cpp │ ├── ch_nolld.cpp │ ├── ch_nolld.h │ ├── ch_nolld2.cpp │ ├── ch_nolld2.h │ ├── ch_run_backend.cpp │ ├── ch_run_backend2.cpp │ ├── ch_srem.ll │ ├── ch_test_7_3.cpp │ ├── clean.sh │ ├── config.h │ ├── cpu0_gcd.ll │ ├── cpu0_gcd_soft.ll │ ├── cpu0_sqrt.ll │ ├── debug.h │ ├── dump_mem.c │ ├── eh-dwarf-cfa.ll │ ├── functions.sh │ ├── hello.c │ ├── itoa.c │ ├── itoa.cpp │ ├── memcpy.cpp │ ├── memcpy.ll │ ├── print.cpp │ ├── print.h │ ├── start.h │ ├── tailcall.ll │ └── test_memcpy.ll ├── install_llvm │ └── build-llvm.sh ├── llvm │ ├── modify │ │ └── llvm │ │ │ ├── CMakeLists.txt │ │ │ ├── cmake │ │ │ └── config-ix.cmake │ │ │ ├── include │ │ │ └── llvm │ │ │ │ ├── ADT │ │ │ │ └── Triple.h │ │ │ │ ├── BinaryFormat │ │ │ │ ├── ELF.h │ │ │ │ └── ELFRelocs │ │ │ │ │ └── Cpu0.def │ │ │ │ ├── IR │ │ │ │ ├── Intrinsics.td │ │ │ │ └── IntrinsicsCpu0.td │ │ │ │ ├── Object │ │ │ │ └── ELFObjectFile.h │ │ │ │ └── module.modulemap │ │ │ ├── lib │ │ │ ├── MC │ │ │ │ └── MCSubtargetInfo.cpp │ │ │ ├── Object │ │ │ │ └── ELF.cpp │ │ │ └── Support │ │ │ │ └── Triple.cpp │ │ │ ├── tools │ │ │ ├── elf2hex │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── elf2hex.cpp │ │ │ │ └── elf2hex.h │ │ │ └── llvm-objdump │ │ │ │ └── llvm-objdump.cpp │ │ │ └── utils │ │ │ └── gn │ │ │ └── secondary │ │ │ └── llvm │ │ │ └── lib │ │ │ └── Target │ │ │ └── targets.gni │ └── orig │ │ └── llvm │ │ ├── CMakeLists.txt │ │ ├── cmake │ │ └── config-ix.cmake │ │ ├── include │ │ └── llvm │ │ │ ├── ADT │ │ │ └── Triple.h │ │ │ ├── BinaryFormat │ │ │ └── ELF.h │ │ │ ├── IR │ │ │ └── Intrinsics.td │ │ │ ├── Object │ │ │ └── ELFObjectFile.h │ │ │ └── module.modulemap │ │ ├── lib │ │ ├── MC │ │ │ └── MCSubtargetInfo.cpp │ │ ├── Object │ │ │ └── ELF.cpp │ │ └── Support │ │ │ └── Triple.cpp │ │ ├── tools │ │ └── llvm-objdump │ │ │ └── llvm-objdump.cpp │ │ └── utils │ │ └── gn │ │ └── secondary │ │ └── llvm │ │ └── lib │ │ └── Target │ │ └── targets.gni ├── opt │ └── add.ll ├── preprocess.cpp ├── readme ├── regression-test │ ├── C++ │ │ ├── ch7_4-longlong-add.cpp │ │ ├── ch7_4-longlong-sub.cpp │ │ ├── ch7_4-signed-int-mul.cpp │ │ ├── ch7_4-signed-longlong-mul.cpp │ │ ├── ch7_4-unsigned-int-mul.cpp │ │ ├── ch7_4-unsigned-longlong-mul.cpp │ │ ├── ch7_5-global-array.cpp │ │ ├── ch7_5-global-struct.cpp │ │ ├── ch9_3-vararg.cpp │ │ ├── ch9_3-vararg.ll │ │ └── ch9_4-alloc.cpp │ ├── Cpu0 │ │ ├── 0_test_result.txt │ │ ├── 2008-06-05-Carry.ll │ │ ├── 2008-07-03-SRet.ll │ │ ├── 2008-07-15-InternalConstant.ll │ │ ├── 2008-07-15-SmallSection.ll │ │ ├── 2008-07-29-icmp.ll │ │ ├── 2008-08-01-AsmInline.ll │ │ ├── 2008-08-06-Alloca.ll │ │ ├── 2008-08-08-bswap.ll │ │ ├── 2008-08-08-ctlz.ll │ │ ├── 2008-10-13-LegalizerBug.ll │ │ ├── 2008-11-10-xint_to_fp.ll │ │ ├── 2010-11-09-CountLeading.ll │ │ ├── 2010-11-09-Mul.ll │ │ ├── addc.ll │ │ ├── addi.ll │ │ ├── addressing-mode.ll │ │ ├── alloca.ll │ │ ├── analyzebranch.ll │ │ ├── and1.ll │ │ ├── asm-large-immediate.ll │ │ ├── atomic-1.ll │ │ ├── atomic-2.ll │ │ ├── atomics-fences.ll │ │ ├── atomics-indexed.ll │ │ ├── atomics.ll │ │ ├── blockaddr.ll │ │ ├── br-jmp.ll │ │ ├── cmov.ll │ │ ├── cprestore.ll │ │ ├── cpu0_gcd.ll │ │ ├── cpu0_gcd_soft.ll │ │ ├── div.ll │ │ ├── div_rem.ll │ │ ├── divrem.ll │ │ ├── divu.ll │ │ ├── divu_remu.ll │ │ ├── double2int.ll │ │ ├── eh-dwarf-cfa.ll │ │ ├── eh-return32.ll │ │ ├── eh.ll │ │ ├── ex2.ll │ │ ├── fastcc.ll │ │ ├── fneg.ll │ │ ├── fp-spill-reload.ll │ │ ├── frame-address.ll │ │ ├── global-address.ll │ │ ├── global-pointer-reg.ll │ │ ├── gprestore.ll │ │ ├── helloworld.ll │ │ ├── hf16_1.ll │ │ ├── i32k.ll │ │ ├── i64arg.ll │ │ ├── imm.ll │ │ ├── indirectcall.ll │ │ ├── init-array.ll │ │ ├── inlineasm-cnstrnt-reg.ll │ │ ├── inlineasm-operand-code.ll │ │ ├── inlineasm_constraint.ll │ │ ├── inlineasmmemop.ll │ │ ├── internalfunc.ll │ │ ├── jtstat.ll │ │ ├── lb1.ll │ │ ├── lbu1.ll │ │ ├── lh1.ll │ │ ├── lhu1.ll │ │ ├── lit.local.cfg │ │ ├── llcarry.ll │ │ ├── longbranch.ll │ │ ├── machineverifier.ll │ │ ├── mipslopat.ll │ │ ├── misha.ll │ │ ├── module-asm-cpu032II.ll │ │ ├── module-asm.ll │ │ ├── mul.ll │ │ ├── mulll.ll │ │ ├── mulull.ll │ │ ├── not1.ll │ │ ├── null.ll │ │ ├── o32_cc_byval.ll │ │ ├── o32_cc_vararg.ll │ │ ├── private.ll │ │ ├── rem.ll │ │ ├── remat-immed-load.ll │ │ ├── remu.ll │ │ ├── return-vector-float4.ll │ │ ├── return-vector.ll │ │ ├── return_address.ll │ │ ├── rotate.ll │ │ ├── sb1.ll │ │ ├── select.ll │ │ ├── seleq.ll │ │ ├── seleqk.ll │ │ ├── selgek.ll │ │ ├── selgt.ll │ │ ├── selle.ll │ │ ├── selltk.ll │ │ ├── selne.ll │ │ ├── selnek.ll │ │ ├── seteq.ll │ │ ├── seteqz.ll │ │ ├── setge.ll │ │ ├── setgek.ll │ │ ├── setle.ll │ │ ├── setlt.ll │ │ ├── setltk.ll │ │ ├── setne.ll │ │ ├── setuge.ll │ │ ├── setugt.ll │ │ ├── setule.ll │ │ ├── setult.ll │ │ ├── setultk.ll │ │ ├── sext_inreg.ll │ │ ├── shift-parts.ll │ │ ├── shl1.ll │ │ ├── shl2.ll │ │ ├── shr1.ll │ │ ├── shr2.ll │ │ ├── sitofp-selectcc-opt.ll │ │ ├── small-section-reserve-gp.ll │ │ ├── sra1.ll │ │ ├── sra2.ll │ │ ├── stacksave-restore.ll │ │ ├── stacksize.ll │ │ ├── stchar.ll │ │ ├── stldst.ll │ │ ├── sub1.ll │ │ ├── sub2.ll │ │ ├── tailcall.ll │ │ ├── tls-alias.ll │ │ ├── tls-models.ll │ │ ├── tls.ll │ │ ├── uitofp.ll │ │ ├── ul1.ll │ │ ├── unalignedload.ll │ │ ├── vector-setcc.ll │ │ ├── weak.ll │ │ ├── xor1.ll │ │ └── zeroreg.ll │ └── ex │ │ ├── ch3-directive.ll │ │ ├── ch3-proepilog.ll │ │ ├── ch3-ret.ll │ │ ├── ch4_1.ll │ │ ├── ch4_2-mod.ll │ │ ├── ch4_2_2-mod.ll │ │ ├── ch4_3-div.ll │ │ ├── ch4_5-andorxornot.ll │ │ ├── ch4_5-setxx.ll │ │ ├── ch6_1-global.ll │ │ ├── ch7_1-localpointer.ll │ │ ├── ch7_2-short-char.ll │ │ ├── ch7_3-bool.ll │ │ ├── ch7_4-longlong-add.ll │ │ ├── ch7_4-longlong-sub.ll │ │ ├── ch7_4-signed-int-mul.ll │ │ ├── ch7_4-signed-longlong-mul.ll │ │ ├── ch7_4-unsigned-int-mul.ll │ │ ├── ch7_4-unsigned-longlong-mul.ll │ │ ├── ch7_5-global-array.ll │ │ ├── ch7_5-global-struct.ll │ │ ├── ch7_5_2-local-array.ll │ │ └── ch8_1_1.ll ├── set-llvm-lit │ ├── README.txt │ ├── modify │ │ ├── bin │ │ │ └── llvm-lit │ │ ├── test │ │ │ ├── Unit │ │ │ │ └── lit.site.cfg.py │ │ │ └── lit.site.cfg.py │ │ ├── tools │ │ │ └── clang │ │ │ │ └── test │ │ │ │ ├── Unit │ │ │ │ └── lit.site.cfg.py │ │ │ │ └── lit.site.cfg.py │ │ └── utils │ │ │ └── lit │ │ │ └── lit.site.cfg │ ├── origin │ │ ├── bin │ │ │ └── llvm-lit │ │ ├── test │ │ │ ├── Unit │ │ │ │ └── lit.site.cfg.py │ │ │ └── lit.site.cfg.py │ │ ├── tools │ │ │ └── clang │ │ │ │ └── test │ │ │ │ ├── Unit │ │ │ │ └── lit.site.cfg.py │ │ │ │ └── lit.site.cfg.py │ │ └── utils │ │ │ └── lit │ │ │ └── lit.site.cfg │ └── set-llvm-lit.diff └── verilog │ ├── Makefile │ ├── cpu0.v │ ├── cpu0.v.jit │ ├── cpu0.v.notwork2 │ ├── cpu0p.v │ ├── cpu0p1.v │ ├── pipeline.v │ └── readme ├── log-include-in-lbd └── ch3.disas.log ├── make.bat ├── note ├── builtin_fabs.c ├── gen-ll.sh ├── gen-s.sh ├── merge-into-llvm-doc.txt ├── mips_adds_a_b.ll ├── mips_mult.ll ├── note.txt ├── note_lbd.txt ├── pipeline-ex │ ├── 305formalreport.pdf │ └── testbenchA_Fibonacci.v └── porting-compiler-rt ├── papers └── dlcompilersurvey.pdf ├── present ├── clang_llvm_intrinsic.ppt ├── lbdContents.odp ├── lbdContents_audio │ └── 3.txt └── lbdOverview.odp ├── source ├── TutorialLLVMBackend.odp ├── _static │ └── dummy ├── _templates │ └── layout.html ├── about.rst ├── asm.rst ├── backendstructure.rst ├── c++.rst ├── conf.py ├── ctrlflow.rst ├── doc.rst ├── elf.rst ├── funccall.rst ├── genobj.rst ├── globalvar.rst ├── gpu.rst ├── index.rst ├── install.rst ├── llvmstructure.rst ├── npu.rst ├── otherinst.rst ├── othertype.rst ├── todo.rst └── verilog.rst └── working ├── DelaySlotFiller ├── Cpu0DelaySlotFiller.cpp ├── Cpu0InstrInfo.cpp └── Cpu0InstrInfo.h ├── Mips3.5_style ├── Cpu0.td ├── Cpu0InstrFormats.td ├── Cpu0InstrInfo.td └── Cpu0Schedule.td ├── atomic ├── 1.cpp ├── 2.cpp ├── 3.cpp ├── 4.cpp ├── Atomics-64.ll ├── Cpu0 │ ├── AsmParser │ │ ├── CMakeLists.txt │ │ ├── Cpu0AsmParser.cpp │ │ └── LLVMBuild.txt │ ├── CMakeLists.txt │ ├── Cpu0.h │ ├── Cpu0.td │ ├── Cpu0AnalyzeImmediate.cpp │ ├── Cpu0AnalyzeImmediate.h │ ├── Cpu0Asm.td │ ├── Cpu0AsmPrinter.cpp │ ├── Cpu0AsmPrinter.h │ ├── Cpu0CallingConv.td │ ├── Cpu0CondMov.td │ ├── Cpu0Config.h │ ├── Cpu0DelUselessJMP.cpp │ ├── Cpu0DelaySlotFiller.cpp │ ├── Cpu0EmitGPRestore.cpp │ ├── Cpu0FrameLowering.cpp │ ├── Cpu0FrameLowering.h │ ├── Cpu0ISelDAGToDAG.cpp │ ├── Cpu0ISelDAGToDAG.h │ ├── Cpu0ISelLowering.cpp │ ├── Cpu0ISelLowering.h │ ├── Cpu0InstrFormats.td │ ├── Cpu0InstrInfo.cpp │ ├── Cpu0InstrInfo.h │ ├── Cpu0InstrInfo.td │ ├── Cpu0MCInstLower.cpp │ ├── Cpu0MCInstLower.h │ ├── Cpu0MachineFunction.cpp │ ├── Cpu0MachineFunction.h │ ├── Cpu0Other.td │ ├── Cpu0RegisterInfo.cpp │ ├── Cpu0RegisterInfo.h │ ├── Cpu0RegisterInfo.td │ ├── Cpu0RegisterInfoGPROutForAsm.td │ ├── Cpu0RegisterInfoGPROutForOther.td │ ├── Cpu0SEFrameLowering.cpp │ ├── Cpu0SEFrameLowering.h │ ├── Cpu0SEISelDAGToDAG.cpp │ ├── Cpu0SEISelDAGToDAG.h │ ├── Cpu0SEISelLowering.cpp │ ├── Cpu0SEISelLowering.h │ ├── Cpu0SEInstrInfo.cpp │ ├── Cpu0SEInstrInfo.h │ ├── Cpu0SERegisterInfo.cpp │ ├── Cpu0SERegisterInfo.h │ ├── Cpu0Schedule.td │ ├── Cpu0SelectionDAGInfo.cpp │ ├── Cpu0SelectionDAGInfo.h │ ├── Cpu0SetChapter.h │ ├── Cpu0Subtarget.cpp │ ├── Cpu0Subtarget.h │ ├── Cpu0TargetMachine.cpp │ ├── Cpu0TargetMachine.h │ ├── Cpu0TargetObjectFile.cpp │ ├── Cpu0TargetObjectFile.h │ ├── Disassembler │ │ ├── CMakeLists.txt │ │ ├── Cpu0Disassembler.cpp │ │ └── LLVMBuild.txt │ ├── InstPrinter │ │ ├── CMakeLists.txt │ │ ├── Cpu0InstPrinter.cpp │ │ ├── Cpu0InstPrinter.h │ │ └── LLVMBuild.txt │ ├── LLVMBuild.txt │ ├── MCTargetDesc │ │ ├── CMakeLists.txt │ │ ├── Cpu0AsmBackend.cpp │ │ ├── Cpu0AsmBackend.h │ │ ├── Cpu0BaseInfo.h │ │ ├── Cpu0ELFObjectWriter.cpp │ │ ├── Cpu0FixupKinds.h │ │ ├── Cpu0MCAsmInfo.cpp │ │ ├── Cpu0MCAsmInfo.h │ │ ├── Cpu0MCCodeEmitter.cpp │ │ ├── Cpu0MCCodeEmitter.h │ │ ├── Cpu0MCTargetDesc.cpp │ │ ├── Cpu0MCTargetDesc.h │ │ └── LLVMBuild.txt │ └── TargetInfo │ │ ├── CMakeLists.txt │ │ ├── Cpu0TargetInfo.cpp │ │ └── LLVMBuild.txt ├── atomic-1.ll ├── atomic-2.ll ├── atomics-fences.ll ├── atomics-indexed.ll └── atomics.ll ├── replace_select └── Cpu0ISelLowering.cpp └── sphinx_numfig-r13 ├── numfig.py └── setup.py /Cpu0_replace_select/Cpu0/AsmParser/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) 2 | add_llvm_library(LLVMCpu0AsmParser 3 | Cpu0AsmParser.cpp 4 | ) 5 | 6 | add_dependencies(LLVMCpu0AsmParser Cpu0CommonTableGen) 7 | -------------------------------------------------------------------------------- /Cpu0_replace_select/Cpu0/AsmParser/LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Mips/AsmParser/LLVMBuild.txt ----------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | 18 | [component_0] 19 | type = Library 20 | name = Cpu0AsmParser 21 | parent = Mips 22 | required_libraries = MC MCParser Support MipsDesc MipsInfo 23 | add_to_library_groups = Cpu0 24 | -------------------------------------------------------------------------------- /Cpu0_replace_select/Cpu0/Cpu0SelectionDAGInfo.cpp: -------------------------------------------------------------------------------- 1 | //===-- Cpu0SelectionDAGInfo.cpp - Cpu0 SelectionDAG Info -----------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file implements the Cpu0SelectionDAGInfo class. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #define DEBUG_TYPE "cpu0-selectiondag-info" 15 | #include "Cpu0TargetMachine.h" 16 | using namespace llvm; 17 | 18 | Cpu0SelectionDAGInfo::Cpu0SelectionDAGInfo(const Cpu0TargetMachine &TM) 19 | : TargetSelectionDAGInfo(TM) { 20 | } 21 | 22 | Cpu0SelectionDAGInfo::~Cpu0SelectionDAGInfo() { 23 | } 24 | -------------------------------------------------------------------------------- /Cpu0_replace_select/Cpu0/Cpu0SelectionDAGInfo.h: -------------------------------------------------------------------------------- 1 | //===-- Cpu0SelectionDAGInfo.h - Cpu0 SelectionDAG Info ---------*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file defines the Cpu0 subclass for TargetSelectionDAGInfo. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #ifndef CPU0SELECTIONDAGINFO_H 15 | #define CPU0SELECTIONDAGINFO_H 16 | 17 | #include "llvm/Target/TargetSelectionDAGInfo.h" 18 | 19 | namespace llvm { 20 | 21 | class Cpu0TargetMachine; 22 | 23 | class Cpu0SelectionDAGInfo : public TargetSelectionDAGInfo { 24 | public: 25 | explicit Cpu0SelectionDAGInfo(const Cpu0TargetMachine &TM); 26 | ~Cpu0SelectionDAGInfo(); 27 | }; 28 | 29 | } 30 | 31 | #endif 32 | -------------------------------------------------------------------------------- /Cpu0_replace_select/Cpu0/Disassembler/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) 2 | 3 | add_llvm_library(LLVMCpu0Disassembler 4 | Cpu0Disassembler.cpp 5 | ) 6 | 7 | # workaround for hanging compilation on MSVC9 and 10 8 | if( MSVC_VERSION EQUAL 1400 OR MSVC_VERSION EQUAL 1500 OR MSVC_VERSION EQUAL 1600 ) 9 | set_property( 10 | SOURCE Cpu0Disassembler.cpp 11 | PROPERTY COMPILE_FLAGS "/Od" 12 | ) 13 | endif() 14 | 15 | add_dependencies(LLVMCpu0Disassembler Cpu0CommonTableGen) 16 | -------------------------------------------------------------------------------- /Cpu0_replace_select/Cpu0/Disassembler/LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Cpu0/Disassembler/LLVMBuild.txt --------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | 18 | [component_0] 19 | type = Library 20 | name = Cpu0Disassembler 21 | parent = Cpu0 22 | required_libraries = MC Support Cpu0Info 23 | add_to_library_groups = Cpu0 24 | -------------------------------------------------------------------------------- /Cpu0_replace_select/Cpu0/InstPrinter/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) 2 | 3 | add_llvm_library(LLVMCpu0AsmPrinter 4 | Cpu0InstPrinter.cpp 5 | ) 6 | 7 | add_dependencies(LLVMCpu0AsmPrinter Cpu0CommonTableGen) 8 | -------------------------------------------------------------------------------- /Cpu0_replace_select/Cpu0/InstPrinter/LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Cpu0/InstPrinter/LLVMBuild.txt --------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | 18 | [component_0] 19 | type = Library 20 | name = Cpu0AsmPrinter 21 | parent = Cpu0 22 | required_libraries = MC Support 23 | add_to_library_groups = Cpu0 24 | -------------------------------------------------------------------------------- /Cpu0_replace_select/Cpu0/MCTargetDesc/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # MCTargetDesc/CMakeLists.txt 2 | add_llvm_library(LLVMCpu0Desc 3 | Cpu0AsmBackend.cpp 4 | Cpu0MCAsmInfo.cpp 5 | Cpu0MCCodeEmitter.cpp 6 | Cpu0MCTargetDesc.cpp 7 | Cpu0ELFObjectWriter.cpp 8 | ) 9 | 10 | add_dependencies(LLVMCpu0Desc Cpu0CommonTableGen) 11 | -------------------------------------------------------------------------------- /Cpu0_replace_select/Cpu0/MCTargetDesc/Cpu0MCAsmInfo.h: -------------------------------------------------------------------------------- 1 | //===-- Cpu0MCAsmInfo.h - Cpu0 Asm Info ------------------------*- C++ -*--===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains the declaration of the Cpu0MCAsmInfo class. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #ifndef CPU0TARGETASMINFO_H 15 | #define CPU0TARGETASMINFO_H 16 | 17 | #include "llvm/MC/MCAsmInfo.h" 18 | 19 | namespace llvm { 20 | class StringRef; 21 | class Target; 22 | 23 | class Cpu0MCAsmInfo : public MCAsmInfo { 24 | virtual void anchor(); 25 | public: 26 | explicit Cpu0MCAsmInfo(const Target &T, StringRef TT); 27 | }; 28 | 29 | } // namespace llvm 30 | 31 | #endif 32 | -------------------------------------------------------------------------------- /Cpu0_replace_select/Cpu0/MCTargetDesc/LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Cpu0/MCTargetDesc/LLVMBuild.txt -------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | # MCTargetDesc/LLVMBuild.txt 18 | [component_0] 19 | type = Library 20 | name = Cpu0Desc 21 | parent = Cpu0 22 | required_libraries = MC Cpu0AsmPrinter Cpu0Info Support 23 | add_to_library_groups = Cpu0 24 | -------------------------------------------------------------------------------- /Cpu0_replace_select/Cpu0/TargetInfo/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) 2 | 3 | add_llvm_library(LLVMCpu0Info 4 | Cpu0TargetInfo.cpp 5 | ) 6 | 7 | add_dependencies(LLVMCpu0Info Cpu0CommonTableGen) 8 | -------------------------------------------------------------------------------- /Cpu0_replace_select/Cpu0/TargetInfo/Cpu0TargetInfo.cpp: -------------------------------------------------------------------------------- 1 | //===-- Cpu0TargetInfo.cpp - Cpu0 Target Implementation -------------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | 10 | #include "Cpu0.h" 11 | #include "llvm/IR/Module.h" 12 | #include "llvm/Support/TargetRegistry.h" 13 | using namespace llvm; 14 | 15 | Target llvm::TheCpu0Target, llvm::TheCpu0elTarget; 16 | 17 | extern "C" void LLVMInitializeCpu0TargetInfo() { 18 | RegisterTarget X(TheCpu0Target, "cpu0", "Cpu0"); 20 | 21 | RegisterTarget Y(TheCpu0elTarget, "cpu0el", "Cpu0el"); 23 | } 24 | -------------------------------------------------------------------------------- /Cpu0_replace_select/Cpu0/TargetInfo/LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Cpu0/TargetInfo/LLVMBuild.txt ---------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | 18 | [component_0] 19 | type = Library 20 | name = Cpu0Info 21 | parent = Cpu0 22 | required_libraries = MC Support Target 23 | add_to_library_groups = Cpu0 24 | -------------------------------------------------------------------------------- /Fig/Author_ChineseName.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/Author_ChineseName.png -------------------------------------------------------------------------------- /Fig/README: -------------------------------------------------------------------------------- 1 | dot -Tpng file.gv -o file.png 2 | 3 | ref. 4 | man dot 5 | -------------------------------------------------------------------------------- /Fig/about/BookContents.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/about/BookContents.odg -------------------------------------------------------------------------------- /Fig/about/lbd_and_lbt.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/about/lbd_and_lbt.png -------------------------------------------------------------------------------- /Fig/asm/asmDfd.gv: -------------------------------------------------------------------------------- 1 | // Free usage license, author: Chung-Shu Chen 陳鍾樞 2 | // dot -tPng asmDfd.gv -oasmDfd.png 3 | 4 | digraph G { 5 | rankdir=LR; 6 | subgraph cluster_0 { 7 | style=filled; 8 | // label = "Assemble flow"; 9 | node [style=filled,color=white]; user, asmParser, encoder, elfobj; 10 | user -> asmParser [ label = "cpu0 assembly" ]; 11 | asmParser -> encoder [ label = "opcode ID & operand IDs" ]; 12 | encoder -> elfobj [ label = "binary" ]; 13 | color=lightgrey 14 | } 15 | } 16 | -------------------------------------------------------------------------------- /Fig/asm/asmDfd.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/asm/asmDfd.png -------------------------------------------------------------------------------- /Fig/asm/asmDfdEx.gv: -------------------------------------------------------------------------------- 1 | // Free usage license, author: Chung-Shu Chen 陳鍾樞 2 | // dot -Tpng asmDfdEx.gv -oasmDfdEx.png 3 | 4 | digraph G { 5 | rankdir=LR; 6 | subgraph cluster_2 { 7 | style=filled; 8 | // label = "Assemble flow, for instance: add $v1, $v0, $at"; 9 | subgraph clusterA { 10 | label = "asmParser"; 11 | node [style=filled,color=white]; ParseInstruction [label="ParseInstruction()"]; 12 | node [style=filled,color=white]; MatchAndEmitInstruction [label="MatchAndEmitInstruction()"]; 13 | ParseInstruction -> MatchAndEmitInstruction [ label = "Operands:\n (Cpu0::ADD, Cpu0::V1,\n Cpu0::AT, Cpu0::V0)" ]; 14 | } 15 | subgraph clusterB { 16 | label = "encoder: Cpu0MCCodeEmitter.cpp"; 17 | node [style=filled,color=white]; encodeInstruction [label="encodeInstruction()"]; 18 | } 19 | MatchAndEmitInstruction -> encodeInstruction [ label = "Inst.Opcode=\nCpu0::ADD,\nInst.Operand[0] = V1,\nInst.Operand[1] = AT,\nInst.Operand[2] = V0" ]; 20 | color=lightgrey 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /Fig/asm/asmDfdEx.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/asm/asmDfdEx.png -------------------------------------------------------------------------------- /Fig/asm/asmDfdEx2.gv: -------------------------------------------------------------------------------- 1 | // Free usage license, author: Chung-Shu Chen 陳鍾樞 2 | // dot -Tpng asmDfdEx2.gv -oasmDfdEx2.png 3 | 4 | digraph G { 5 | rankdir=LR; 6 | subgraph cluster_2 { 7 | style=filled; 8 | // label = "Data flow in MatchAndEmitInstruction(), for instance: add $v1, $v0, $at"; 9 | subgraph clusterA { 10 | label = "MatchAndEmitInstruction()"; 11 | node [style=filled,color=white]; MatchTable0 [label="Start = std::\nbegin(MatchTable0);\nEnd = std::end\n(MatchTable0);"]; 12 | node [style=filled,color=white]; equal_range [label="std::equal_range(Start, End, \nMnemonic, LessOpcode());"]; 13 | node [style=filled,color=white]; convertToMCInst [label="convertToMCInst\n(Kind, ...)"]; 14 | MatchTable0 -> equal_range [ label = "Start,\nEnd" ]; 15 | equal_range -> convertToMCInst [ label = "Kind=\nConvert__Reg1_0__\nReg1_1__Reg1_2" ]; 16 | } 17 | color=lightgrey 18 | } 19 | } 20 | -------------------------------------------------------------------------------- /Fig/asm/asmDfdEx2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/asm/asmDfdEx2.png -------------------------------------------------------------------------------- /Fig/asm/asmDfdEx3.gv: -------------------------------------------------------------------------------- 1 | // Free usage license, author: Chung-Shu Chen 陳鍾樞 2 | // dot -Tpng asmDfdEx3.gv -oasmDfdEx3.png 3 | 4 | digraph G { 5 | rankdir=LR; 6 | subgraph cluster_2 { 7 | style=filled; 8 | // label = "Data flow in and between MatchAndEmitInstruction() and encodeInstruction(), for instance: add $v1, $v0, $at"; 9 | subgraph clusterA { 10 | label = "MatchAndEmitInstruction()"; 11 | node [style=filled,color=white]; convertToMCInst [label="convertToMCInst()"]; 12 | } 13 | subgraph clusterB { 14 | label = "encodeInstruction()"; 15 | node [style=filled,color=white]; getBinaryCodeForInstr [label="getBinaryCodeForInstr()"]; 16 | node [style=filled,color=white]; EmitInstruction [label="EmitInstruction()"]; 17 | getBinaryCodeForInstr -> EmitInstruction [ label = "Binary" ]; 18 | } 19 | convertToMCInst -> getBinaryCodeForInstr [ label = "Inst.Opcode = ADD,\nInst.Operand[0] = V1,\nInst.Operand[1] = AT,\nInst.Operand[2] = V0" ]; 20 | color=lightgrey 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /Fig/asm/asmDfdEx3.png: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- 1 | digraph G { 2 | rankdir=LR; 3 | subgraph clusterDisa { 4 | label = "Disassembler"; 5 | objdump [label="llvm-objdump", shape=record]; 6 | obj_dis [label="binary obj"]; 7 | asm_dis [label="assembly"]; 8 | obj_dis -> objdump; 9 | objdump -> asm_dis [label="-d"]; 10 | } 11 | subgraph clusterAsm { 12 | label = "Assembler"; 13 | llc_asm [label="llc", shape=record]; 14 | asm_asm [label="assembly"]; 15 | obj_asm [label="binary obj"]; 16 | asm_asm -> llc_asm; 17 | llc_asm -> obj_asm [label="-filetype=obj"]; 18 | } 19 | subgraph clusterLlc { 20 | label = "Backend compiler"; 21 | llc_llc [label="llc", shape=record]; 22 | asm_llc [label="assembly"]; 23 | obj_llc [label="binary obj"]; 24 | "llvm-ir" -> llc_llc; 25 | llc_llc -> asm_llc [label="-filetype=asm"]; 26 | llc_llc -> obj_llc [label="-filetype=obj"]; 27 | } 28 | } 29 | -------------------------------------------------------------------------------- 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MI.Opcode"]; 14 | 15 | "getBinaryCodeForInstr()" -> "encodeInstruction()" [label="4. full MI with operands (register number, immediate value, ...)"]; 16 | "getBinaryCodeForInstr()" -> "getMachineOpValue()" [label="2. MI.Operand[n]"]; 17 | 18 | "getMachineOpValue()" -> "getBinaryCodeForInstr()" [label="3. RegNum"]; 19 | 20 | // label = "Figure: DFD flow for instruction encode"; 21 | } 22 | 23 | -------------------------------------------------------------------------------- /Fig/genobj/obj-emit.gv: -------------------------------------------------------------------------------- 1 | digraph G { 2 | rankdir=LR; 3 | MCInst [style="filled,bold", fillcolor=lightgreen]; 4 | "binary obj" [style="filled,bold", fillcolor=lightgreen]; 5 | 6 | MachineInstr -> MCInst -> "binary obj"; 7 | } 8 | -------------------------------------------------------------------------------- /Fig/gpu/2d-vector-inward.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/gpu/2d-vector-inward.odt -------------------------------------------------------------------------------- /Fig/gpu/2d-vector-inward.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/gpu/2d-vector-inward.png -------------------------------------------------------------------------------- /Fig/gpu/2d-vector-inward.tex: -------------------------------------------------------------------------------- 1 | % Drawing angles using the PG 3.0 angles and quotes libraries 2 | % Author: Paul Gaborit 3 | \documentclass[tikz,border=10pt]{standalone} 4 | \usetikzlibrary{quotes,angles} 5 | \begin{document} 6 | \begin{tikzpicture} 7 | \draw 8 | [->, very thick](0,0) coordinate (b) node[left] {$P_i$} 9 | -- (3,3) coordinate (c) node[above right] {$P_{i+1}$}; 10 | \draw [->](2,2) .. controls +(135:1cm) and +(135:1cm) .. (1,1); 11 | \node[above] at (1,2) {$\theta$}; 12 | \node[above] at (0.3,0.3) {$v_i$}; 13 | \draw 14 | [->, very thick](7,3) coordinate (b1) node[above right] {$P_i$} 15 | -- (4,0) coordinate (c1) node[left] {$P_{i+1}$}; 16 | \draw [->](5,1) .. controls +(315:1cm) and +(315:1cm) .. (6,2); 17 | \node[below] at (6,1) {$\theta$}; 18 | \node[above] at (6.5,2.5) {$v_i$}; 19 | \end{tikzpicture} 20 | \end{document} 21 | 22 | -------------------------------------------------------------------------------- /Fig/gpu/3d-cross-product.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/gpu/3d-cross-product.png -------------------------------------------------------------------------------- /Fig/gpu/3d-polygon.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/gpu/3d-polygon.png -------------------------------------------------------------------------------- /Fig/gpu/OpenGL-pipeline.png: -------------------------------------------------------------------------------- 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animation's shaders \n or programmer writing shaders"]; 11 | } 12 | } 13 | subgraph cluster_driver { 14 | label = "Driver" 15 | Compiler [label="On-line Compiler"]; 16 | Obj [label="obj"]; 17 | Linker [label="On-line binding (Linker)"]; 18 | Exe [label="exe"]; 19 | } 20 | Api:a -> Obj [lhead ="cluster_driver"]; 21 | Api:s -> Compiler; 22 | Compiler -> Obj -> Linker -> Exe; 23 | Exe -> GPU; 24 | Exe -> CPU [ltail ="cluster_driver"]; 25 | 26 | // label = "OpenGL Flow"; 27 | } 28 | 29 | -------------------------------------------------------------------------------- /Fig/gpu/opengl_flow.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/gpu/opengl_flow.odg -------------------------------------------------------------------------------- /Fig/gpu/opengl_flow.png: -------------------------------------------------------------------------------- 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GLSL | OpenCL } | SPIR-V | GPU machine code"]; 7 | } 8 | -------------------------------------------------------------------------------- /Fig/gpu/sycl.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/gpu/sycl.png -------------------------------------------------------------------------------- /Fig/gpu/threadblock.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/gpu/threadblock.jpg -------------------------------------------------------------------------------- /Fig/gpu/threads-lanes.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/gpu/threads-lanes.png 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4 | if (a < b) { 5 | a = a + i; 6 | b = b - 1; 7 | } 8 | if (b == 0) { 9 | goto label_1; 10 | } 11 | } 12 | 13 | label_1: 14 | switch (a) { 15 | case 10: 16 | a = a*a-b+2; 17 | a++; 18 | break; 19 | } 20 | 21 | return (a+b); 22 | } 23 | -------------------------------------------------------------------------------- /Fig/llvmstructure/cpu0_arch.odp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/llvmstructure/cpu0_arch.odp -------------------------------------------------------------------------------- /Fig/llvmstructure/frontendTblGen.gv: -------------------------------------------------------------------------------- 1 | digraph G { 2 | rankdir=TB; 3 | subgraph cluster_0 { 4 | node [color=black]; "parser generator such as yacc/lex"; 5 | node [shape=note]; "code gen function embedded in BNF", "regular expression + BNF", "front parser"; 6 | "code gen function embedded in BNF" -> "parser generator such as yacc/lex"; 7 | "regular expression + BNF" -> "parser generator such as yacc/lex"; 8 | "parser generator such as yacc/lex" -> "front parser"; 9 | } 10 | subgraph cluster_1 { 11 | node [color=black]; "yacc/lex"; 12 | node [shape=note]; "*.c, *.cpp", "*.y, *.l", "front parser: *.cpp"; 13 | "*.c, *.cpp" -> "yacc/lex"; 14 | "*.y, *.l" -> "yacc/lex"; 15 | "yacc/lex" -> "front parser: *.cpp"; 16 | } 17 | // label = "Frontend TableGen Flow"; 18 | 19 | } 20 | -------------------------------------------------------------------------------- /Fig/llvmstructure/llvmTblGen.gv: -------------------------------------------------------------------------------- 1 | digraph G { 2 | rankdir=TB; 3 | subgraph cluster_0 { 4 | node [color=black]; "TableGen"; 5 | node [shape=note]; "Hardware/Target Description Language Files", "Pattern Match files in c/c++\nfor IR -> Machine Instructions"; 6 | "Hardware/Target Description Language Files" -> "TableGen"; 7 | "TableGen" -> "Pattern Match files in c/c++\nfor IR -> Machine Instructions"; 8 | } 9 | subgraph cluster_1 { 10 | node [color=black]; "llvm-tblgen"; 11 | node [shape=note]; "*.td", "*.inc"; 12 | "*.td" -> "llvm-tblgen" -> "*.inc"; 13 | } 14 | // label = "llvm TableGen Flow"; 15 | 16 | } 17 | -------------------------------------------------------------------------------- /Fig/npu/IREE-Architecture.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/npu/IREE-Architecture.png -------------------------------------------------------------------------------- /Fig/npu/conv_onnx.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Fig/npu/conv_onnx.png -------------------------------------------------------------------------------- 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[label="obj"]; 7 | "llvm-objdump -d" -> "Verilog machine" [label="hex"]; 8 | 9 | // label = "Figure: Cpu0 backend without linker"; 10 | } 11 | -------------------------------------------------------------------------------- /FutureWork.rst: -------------------------------------------------------------------------------- 1 | Future Work 2 | ============ 3 | 4 | Major issue: 5 | ------------- 6 | 7 | 1. LLVM IDE setup in Xcode or Eclips. We don't know if it possible. 8 | 9 | 2. Cannot display Figure Number by :num:`FigureLink`. 10 | 11 | 3. Cannot display Section Number like Figure Number. 12 | 13 | 14 | Minor issue: 15 | ------------- 16 | 17 | 1. Cannot show figure description at center. 18 | 19 | 2. cannot set **bold** in literalinclude or code-block. 20 | 21 | 3. LaTeX issue: we still don't know the answer 22 | Chinese author name cannot appear in LaTeX, so Jonathan use .png file to 23 | display Chinese name. 24 | Author name can be display on more than one line by \\and, but will shift a 25 | little right on the second line. 26 | The Chinese name size is OK in html but too large in LaTeX. 27 | -------------------------------------------------------------------------------- /References/c++/mem-order-ex1.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | std::atomic data(0); 6 | std::atomic ready(false); 7 | 8 | void producer() { 9 | data.store(42, std::memory_order_relaxed); // Store value 10 | ready.store(true, std::memory_order_release); // Release signal 11 | } 12 | 13 | void consumer() { 14 | while (!ready.load(std::memory_order_acquire)); // Wait for ready signal 15 | 16 | // Ensure that this print sees the correct value of `data` 17 | std::cout << "Data: " << data.load(std::memory_order_relaxed) << std::endl; 18 | } 19 | 20 | int main() { 21 | std::thread t1(producer); 22 | std::thread t2(consumer); 23 | 24 | t1.join(); 25 | t2.join(); 26 | 27 | return 0; 28 | } 29 | 30 | -------------------------------------------------------------------------------- /References/null_pointer.cpp: -------------------------------------------------------------------------------- 1 | // with #define FORGET_SET then both clang -O0 and -O3 are output "hello" 2 | // without then clang -O0 output segmentation fault 3 | 4 | // For undef is only happened in compiler optimization. 5 | 6 | #include 7 | 8 | #define FORGET_SET 9 | 10 | static void (*FP)() = 0; 11 | static void impl() { 12 | printf("hello\n"); 13 | } 14 | void set() { 15 | FP = impl; 16 | } 17 | void call() { 18 | FP(); 19 | } 20 | int main() { 21 | #ifndef FORGET_SET 22 | set(); 23 | #endif 24 | call(); 25 | } 26 | -------------------------------------------------------------------------------- /References/short-math-guide.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/References/short-math-guide.pdf -------------------------------------------------------------------------------- /References/triangles.frag: -------------------------------------------------------------------------------- 1 | #version 450 core 2 | 3 | out vec4 fColor; 4 | 5 | void main() 6 | { 7 | fColor = vec4(0.5, 0.4, 0.8, 1.0); 8 | } 9 | -------------------------------------------------------------------------------- /References/triangles.vert: -------------------------------------------------------------------------------- 1 | 2 | #version 400 core 3 | 4 | layout( location = 0 ) in vec4 vPosition; 5 | 6 | void 7 | main() 8 | { 9 | gl_Position = vPosition; 10 | } 11 | -------------------------------------------------------------------------------- /Table/funccall/1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Table/funccall/1.png -------------------------------------------------------------------------------- /Table/llvmstructure/1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Table/llvmstructure/1.png -------------------------------------------------------------------------------- /Table/llvmstructure/2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Table/llvmstructure/2.png -------------------------------------------------------------------------------- /Table/llvmstructure/3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Table/llvmstructure/3.png -------------------------------------------------------------------------------- /Table/llvmstructure/cpu0_instructions_table.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/Table/llvmstructure/cpu0_instructions_table.odt -------------------------------------------------------------------------------- /check.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | pushd lbdex/input 4 | echo "bash build-run_backend.sh cpu032I eb" 5 | bash build-run_backend.sh cpu032I eb 6 | if [ "$?" != "0" ]; then 7 | echo "FAIL" 8 | exit 1; 9 | fi 10 | pushd ../verilog 11 | make 12 | ./cpu0Is 13 | popd 14 | 15 | echo "bash build-run_backend.sh cpu032I el" 16 | bash build-run_backend.sh cpu032I el 17 | if [ "$?" != "0" ]; then 18 | echo "FAIL" 19 | exit 1; 20 | fi 21 | pushd ../verilog 22 | ./cpu0Is 23 | popd 24 | 25 | echo "bash build-run_backend.sh cpu032II eb" 26 | bash build-run_backend.sh cpu032II eb 27 | if [ "$?" != "0" ]; then 28 | echo "FAIL" 29 | exit 1; 30 | fi 31 | pushd ../verilog 32 | ./cpu0IIs 33 | popd 34 | 35 | echo "bash build-run_backend.sh cpu032II el" 36 | bash build-run_backend.sh cpu032II el 37 | if [ "$?" != "0" ]; then 38 | echo "FAIL" 39 | exit 1; 40 | fi 41 | pushd ../verilog 42 | ./cpu0IIs 43 | popd 44 | 45 | echo "PASS" 46 | popd 47 | -------------------------------------------------------------------------------- /clean.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | pushd lbdex 4 | bash clean.sh 5 | popd 6 | rm -rf build lbdex.tar.gz 7 | rm -f `find . -name \*~` 8 | rm -f `find . -name .DS_Store` -------------------------------------------------------------------------------- /lbdex/Cpu0/AsmParser/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_llvm_component_library(LLVMCpu0AsmParser 2 | Cpu0AsmParser.cpp 3 | 4 | LINK_COMPONENTS 5 | MC 6 | MCParser 7 | Cpu0Desc 8 | Cpu0Info 9 | Support 10 | 11 | ADD_TO_COMPONENT 12 | Cpu0 13 | ) 14 | -------------------------------------------------------------------------------- /lbdex/Cpu0/Cpu0Config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CPU0CONFIG_H_ 2 | #define _CPU0CONFIG_H_ 3 | 4 | #define ENABLE_GPRESTORE 5 | 6 | #define CH2 20 7 | #define CH3_1 31 8 | #define CH3_2 32 9 | #define CH3_3 33 10 | #define CH3_4 34 11 | #define CH3_5 35 12 | #define CH4_1 41 13 | #define CH4_2 42 14 | #define CH5_1 51 15 | #define CH6_1 61 16 | #define CH7_1 71 17 | #define CH8_1 81 18 | #define CH8_2 82 19 | #define CH9_1 91 20 | #define CH9_2 92 21 | #define CH9_3 93 22 | #define CH10_1 101 23 | #define CH11_1 111 24 | #define CH11_2 112 25 | #define CH12_1 121 26 | 27 | #include "Cpu0SetChapter.h" 28 | 29 | #endif 30 | 31 | -------------------------------------------------------------------------------- /lbdex/Cpu0/Cpu0RegisterInfoGPROutForAsm.td: -------------------------------------------------------------------------------- 1 | 2 | //===----------------------------------------------------------------------===// 3 | // Register Classes 4 | //===----------------------------------------------------------------------===// 5 | 6 | def GPROut : RegisterClass<"Cpu0", [i32], 32, (add CPURegs)>; 7 | 8 | -------------------------------------------------------------------------------- /lbdex/Cpu0/Cpu0RegisterInfoGPROutForOther.td: -------------------------------------------------------------------------------- 1 | 2 | //===----------------------------------------------------------------------===// 3 | // Register Classes 4 | //===----------------------------------------------------------------------===// 5 | 6 | def GPROut : RegisterClass<"Cpu0", [i32], 32, (add (sub CPURegs, SW))>; 7 | 8 | -------------------------------------------------------------------------------- /lbdex/Cpu0/Cpu0SERegisterInfo.cpp: -------------------------------------------------------------------------------- 1 | //===-- Cpu0SERegisterInfo.cpp - CPU0 Register Information ------== -------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains the CPU0 implementation of the TargetRegisterInfo 11 | // class. 12 | // 13 | //===----------------------------------------------------------------------===// 14 | 15 | #include "Cpu0SERegisterInfo.h" 16 | #if CH >= CH3_1 17 | 18 | using namespace llvm; 19 | 20 | #define DEBUG_TYPE "cpu0-reg-info" 21 | 22 | Cpu0SERegisterInfo::Cpu0SERegisterInfo(const Cpu0Subtarget &ST) 23 | : Cpu0RegisterInfo(ST) {} 24 | 25 | const TargetRegisterClass * 26 | Cpu0SERegisterInfo::intRegClass(unsigned Size) const { 27 | return &Cpu0::CPURegsRegClass; 28 | } 29 | 30 | #endif 31 | -------------------------------------------------------------------------------- /lbdex/Cpu0/Cpu0SetChapter.h: -------------------------------------------------------------------------------- 1 | #define CH CH12_1 2 | -------------------------------------------------------------------------------- /lbdex/Cpu0/Disassembler/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_llvm_component_library(LLVMCpu0Disassembler 2 | Cpu0Disassembler.cpp 3 | 4 | LINK_COMPONENTS 5 | MCDisassembler 6 | Cpu0Info 7 | Support 8 | 9 | ADD_TO_COMPONENT 10 | Cpu0 11 | ) 12 | -------------------------------------------------------------------------------- /lbdex/Cpu0/InstPrinter/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_llvm_component_library(LLVMCpu0AsmPrinter 2 | Cpu0InstPrinter.cpp 3 | 4 | LINK_COMPONENTS 5 | Support 6 | 7 | ADD_TO_COMPONENT 8 | Cpu0 9 | ) 10 | -------------------------------------------------------------------------------- /lbdex/Cpu0/MCTargetDesc/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # MCTargetDesc/CMakeLists.txt 2 | add_llvm_component_library(LLVMCpu0Desc 3 | #if CH >= CH3_1 4 | Cpu0ABIInfo.cpp 5 | #endif 6 | #if CH >= CH3_2 7 | Cpu0MCAsmInfo.cpp 8 | #endif 9 | #if CH >= CH5_1 10 | Cpu0AsmBackend.cpp 11 | Cpu0MCCodeEmitter.cpp 12 | Cpu0MCExpr.cpp 13 | Cpu0ELFObjectWriter.cpp 14 | Cpu0TargetStreamer.cpp 15 | #endif 16 | Cpu0MCTargetDesc.cpp 17 | 18 | LINK_COMPONENTS 19 | MC 20 | Cpu0Info 21 | #if CH >= CH3_2 2 22 | Cpu0AsmPrinter 23 | #endif 24 | Support 25 | 26 | ADD_TO_COMPONENT 27 | Cpu0 28 | ) 29 | -------------------------------------------------------------------------------- /lbdex/Cpu0/TargetInfo/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # llvm 10.0.0 change from add_llvm_library to add_llvm_component_library 2 | add_llvm_component_library(LLVMCpu0Info 3 | Cpu0TargetInfo.cpp 4 | 5 | LINK_COMPONENTS 6 | Support 7 | 8 | ADD_TO_COMPONENT 9 | Cpu0 10 | ) 11 | -------------------------------------------------------------------------------- /lbdex/Cpu0/TargetInfo/Cpu0TargetInfo.cpp: -------------------------------------------------------------------------------- 1 | //===-- Cpu0TargetInfo.cpp - Cpu0 Target Implementation -------------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | 10 | #include "Cpu0.h" 11 | #include "llvm/IR/Module.h" 12 | #include "llvm/Support/TargetRegistry.h" 13 | using namespace llvm; 14 | 15 | Target llvm::TheCpu0Target, llvm::TheCpu0elTarget; 16 | 17 | extern "C" void LLVMInitializeCpu0TargetInfo() { 18 | RegisterTarget X(TheCpu0Target, "cpu0", "CPU0 (32-bit big endian)", "Cpu0"); 20 | 21 | RegisterTarget Y(TheCpu0elTarget, "cpu0el", "CPU0 (32-bit little endian)", "Cpu0"); 23 | } 24 | -------------------------------------------------------------------------------- /lbdex/clean.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | pushd input 4 | bash clean.sh 5 | popd 6 | pushd verilog 7 | make clean 8 | popd 9 | rm -rf output chapters preprocess tmp.txt 10 | 11 | -------------------------------------------------------------------------------- /lbdex/gen-docs-ref.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | pushd ./lbdex 4 | bash ./gen-chapters.sh 5 | # disable since removing output files of llvm-ir and asm from source/*.rst 6 | #bash ./gen-ref-output.sh 7 | popd 8 | 9 | -------------------------------------------------------------------------------- /lbdex/input/atomics-fences.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc < %s -march=cpu0 -mcpu=cpu032II | FileCheck %s --check-prefix=CHECK 2 | 3 | ; Fences 4 | define void @fence_acquire() { 5 | ; CHECK-LABEL: fence_acquire 6 | ; CHECK: sync 7 | fence acquire 8 | ret void 9 | } 10 | define void @fence_release() { 11 | ; CHECK-LABEL: fence_release 12 | ; CHECK: sync 13 | fence release 14 | ret void 15 | } 16 | define void @fence_seq_cst() { 17 | ; CHECK-LABEL: fence_seq_cst 18 | ; CHECK: sync 19 | fence seq_cst 20 | ret void 21 | } 22 | -------------------------------------------------------------------------------- /lbdex/input/boot.cpp: -------------------------------------------------------------------------------- 1 | 2 | /// start 3 | 4 | #include "start.h" 5 | 6 | // boot: 7 | asm("boot:"); 8 | // asm("_start:"); 9 | asm("jmp 12"); // RESET: jmp RESET_START; 10 | asm("jmp 4"); // ERROR: jmp ERR_HANDLE; 11 | asm("jmp 4"); // IRQ: jmp IRQ_HANDLE; 12 | asm("jmp -4"); // ERR_HANDLE: jmp ERR_HANDLE; (loop forever) 13 | 14 | // RESET_START: 15 | initRegs(); 16 | asm("addiu $gp, $ZERO, 0"); 17 | asm("addiu $lr, $ZERO, -1"); 18 | 19 | INIT_SP; 20 | asm("mfc0 $3, $pc"); 21 | asm("addiu $3, $3, 0x8"); // Assume main() entry point is at the next next 22 | // instruction. 23 | asm("jr $3"); 24 | asm("nop"); 25 | -------------------------------------------------------------------------------- /lbdex/input/ch11_1_2.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch11_1_2.cpp -emit-llvm -o ch11_1_2.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic -filetype=obj ch11_1_2.bc -o ch11_1_2.cpu0.o 3 | 4 | /// start 5 | asm("slt $2, $2, $3"); 6 | asm("beq $2, $3, 20"); 7 | asm("ori $sw, $sw, 0x0020"); 8 | asm("andi $sw, $sw, 0xffdf"); 9 | -------------------------------------------------------------------------------- /lbdex/input/ch12_atomics-fences.cpp: -------------------------------------------------------------------------------- 1 | // clang++ -pthread -std=c++11 -S ch12_atomics-fences.cpp -emit-llvm -o ch12_atomics-fences.ll 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch12_atomics-fences.ll -o - 3 | 4 | // Generate IRs "fence" 5 | 6 | #include // std::cout 7 | #include // std::atomic 8 | #include // std::thread 9 | 10 | int a; 11 | 12 | void func1() 13 | { 14 | for (int i = 0; i < 1000000; ++i) 15 | { 16 | a = i; 17 | // Ensure that changes to a to this point are visible to other threads 18 | atomic_thread_fence(std::memory_order_release); 19 | } 20 | } 21 | 22 | void func2() 23 | { 24 | for (int i = 0; i < 1000000; ++i) 25 | { 26 | // Ensure that this thread's view of a is up to date 27 | atomic_thread_fence(std::memory_order_acquire); 28 | std::cout << a; 29 | } 30 | } 31 | 32 | int main() 33 | { 34 | std::thread t1 (func1); 35 | std::thread t2 (func2); 36 | 37 | t1.join(); t2.join(); 38 | } 39 | 40 | -------------------------------------------------------------------------------- /lbdex/input/ch12_atomics-producer-consumer.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | std::atomic ptr; 7 | int data; 8 | 9 | void producer() 10 | { 11 | std::string* p = new std::string("Hello"); 12 | data = 42; 13 | ptr.store(p, std::memory_order_release); 14 | } 15 | 16 | void consumer() 17 | { 18 | std::string* p2; 19 | while (!(p2 = ptr.load(std::memory_order_consume))) 20 | ; 21 | assert(*p2 == "Hello"); // never fires: *p2 carries dependency from ptr 22 | assert(data == 42); // may or may not fire: data does not carry dependency from ptr 23 | } 24 | 25 | int main() 26 | { 27 | std::thread t1(producer); 28 | std::thread t2(consumer); 29 | t1.join(); t2.join(); 30 | } 31 | -------------------------------------------------------------------------------- /lbdex/input/ch12_c++_atomics.cpp: -------------------------------------------------------------------------------- 1 | // clang -S ch12_c++_atomics.cpp -emit-llvm -o - 2 | // Uses /opt/homebrew/opt/llvm/bin/clang in macOS. 3 | 4 | #include 5 | 6 | std::atomic winner (false); 7 | 8 | int test_atomics() { 9 | int count = 0; 10 | bool res = winner.exchange(true); 11 | if (res) count++; 12 | 13 | return count; 14 | } 15 | -------------------------------------------------------------------------------- /lbdex/input/ch12_eh.cpp: -------------------------------------------------------------------------------- 1 | // clang -c ch12_eh.cpp -emit-llvm -o ch12_eh.bc 2 | // ~/llvm/test/build/bin/llvm-dis ch12_eh.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=static -filetype=asm ch12_eh.bc -o - 4 | 5 | /// start 6 | class Ex1 {}; 7 | void throw_exception(int a, int b) { 8 | Ex1 ex1; 9 | 10 | if (a > b) { 11 | throw ex1; 12 | } 13 | } 14 | 15 | int test_try_catch() { 16 | try { 17 | throw_exception(2, 1); 18 | } 19 | catch(...) { 20 | return 1; 21 | } 22 | return 0; 23 | } 24 | 25 | -------------------------------------------------------------------------------- /lbdex/input/ch12_swap.cpp: -------------------------------------------------------------------------------- 1 | // clang++ -c ch12_swap.cpp -emit-llvm -o ch12_swap.bc 2 | // ~/llvm/test/build/bin/llvm-dis ch12_swap.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch12_swap.bc -o - 4 | 5 | #include 6 | using namespace std; 7 | 8 | int main() 9 | { 10 | int a = 1; 11 | int b = 2; 12 | 13 | swap(a, b); 14 | 15 | return a; 16 | } 17 | -------------------------------------------------------------------------------- /lbdex/input/ch12_thread_var.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch12_thread_var.cpp -emit-llvm -std=c++11 -o ch12_thread_var.bc 2 | // ~/llvm/test/build/bin/llvm-dis ch12_thread_var.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch12_thread_var.bc -o - 4 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=static -filetype=asm ch12_thread_var.bc -o - 5 | 6 | /// start 7 | __thread int a = 0; 8 | thread_local int b = 0; // need option -std=c++11 9 | int test_thread_var() 10 | { 11 | a = 2; 12 | return a; 13 | } 14 | 15 | int test_thread_var_2() 16 | { 17 | b = 3; 18 | return b; 19 | } 20 | 21 | -------------------------------------------------------------------------------- /lbdex/input/ch13_1.cpp: -------------------------------------------------------------------------------- 1 | #include "a.h" 2 | 3 | void ISR() { 4 | asm("ISR:"); 5 | return; 6 | } 7 | 8 | int foo4(void) { 9 | return 5; 10 | } 11 | 12 | int main() { 13 | return foo1(); 14 | } 15 | 16 | -------------------------------------------------------------------------------- /lbdex/input/ch3.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch3.cpp -emit-llvm -o ch3.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch3.bc -o ch3.cpu0.s 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=obj ch3.bc -o ch3.cpu0.o 4 | 5 | /// start 6 | int main() 7 | { 8 | return 0; 9 | } 10 | 11 | -------------------------------------------------------------------------------- /lbdex/input/ch3_2.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch3_2.cpp -emit-llvm -o ch3_2.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch3_2.bc -o - 3 | 4 | /// start 5 | int main() 6 | { 7 | int a = 5; 8 | int b = 2; 9 | 10 | int c = a + b; // c = 7 11 | int d = b + 1; // d = 3 12 | 13 | return (c+d); 14 | } 15 | 16 | -------------------------------------------------------------------------------- /lbdex/input/ch3_largeframe.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch3_largeframe.cpp -emit-llvm -o ch3_largeframe.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch3_largeframe.bc -o - 3 | 4 | /// start 5 | int test_largegframe() { 6 | int a[469753856]; 7 | 8 | return 0; 9 | } 10 | -------------------------------------------------------------------------------- /lbdex/input/ch3_localarraylargeimm.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch3_localarraylargeimm.cpp -emit-llvm -o ch3_localarraylargeimm.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch3_localarraylargeimm.bc -o - 3 | 4 | /// start 5 | int main() 6 | { 7 | int A[100000]; 8 | A[99990] = 6; 9 | int a = 5; 10 | int b = 2; 11 | 12 | int c = a + b; // c = 7 13 | int d = b + 1; // d = 3 14 | 15 | return (c+d); 16 | } 17 | 18 | -------------------------------------------------------------------------------- /lbdex/input/ch4_1_addsuboverflow.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch4_1_addsuboverflow.cpp -emit-llvm -o ch4_1_addsuboverflow.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm -cpu0-enable-overflow=true ch4_1_addsuboverflow.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=obj -cpu0-enable-overflow=true ch4_1_addsuboverflow.bc -o ch4_1_addsuboverflow.cpu0.o 4 | 5 | /// start 6 | #include "debug.h" 7 | 8 | int test_add_overflow() 9 | { 10 | int a = 0x70000000; 11 | int b = 0x20000000; 12 | int c = 0; 13 | 14 | c = a + b; 15 | 16 | return 0; 17 | } 18 | 19 | int test_sub_overflow() 20 | { 21 | int a = -0x70000000; 22 | int b = 0x20000000; 23 | int c = 0; 24 | 25 | c = a - b; 26 | 27 | return 0; 28 | } 29 | -------------------------------------------------------------------------------- /lbdex/input/ch4_1_div.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch4_1_div.cpp -emit-llvm -o ch4_1_div.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch4_1_div.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=obj ch4_1_div.bc -o ch4_1_div.cpu0.o 4 | 5 | /// start 6 | int test_div() 7 | { 8 | int a = -5; 9 | int b = 2; 10 | int c = 0x1000000; 11 | int d = 0; 12 | unsigned int a1 = -5, d1 = 0; 13 | 14 | d = a / b; // d = -2 15 | d1 = a1 / c; // a1 = 0xfffffffb, d1 = 0xff = 255 16 | 17 | return (d+d1); // 253 18 | } 19 | 20 | -------------------------------------------------------------------------------- /lbdex/input/ch4_1_mod.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch4_1_mod.cpp -emit-llvm -o ch4_1_mod.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch4_1_mod.bc -o - 3 | 4 | /// start 5 | int test_mod() 6 | { 7 | int b = 11; 8 | volatile int a = 12; 9 | 10 | b = (b+1)%a; 11 | 12 | return b; 13 | } 14 | -------------------------------------------------------------------------------- /lbdex/input/ch4_1_mult.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch4_1_mult.cpp -emit-llvm -o ch4_1_mult.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch4_1_mult.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -view-isel-dags -view-sched-dags -relocation-model=pic -filetype=asm ch4_1_mult.bc -o - 4 | 5 | /// start 6 | int test_mult() 7 | { 8 | int b = 11; 9 | // unsigned int b = 11; 10 | 11 | b = (b+1)%12; 12 | 13 | return b; 14 | } 15 | -------------------------------------------------------------------------------- /lbdex/input/ch4_1_mult2.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch4_1_mult2.cpp -emit-llvm -o ch4_1_mult2.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch4_1_mult2.bc -o - 3 | 4 | /// start 5 | int test_mult() 6 | { 7 | int b = 11; 8 | int a = 12; 9 | 10 | b = (b+1)%a; 11 | 12 | return b; 13 | } 14 | -------------------------------------------------------------------------------- /lbdex/input/ch4_1_rotate.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch4_1_3.cpp -emit-llvm -o ch4_1_3.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch4_1_3.bc -o - 3 | 4 | /// start 5 | 6 | //#define TEST_ROXV 7 | 8 | int test_rotate_left() 9 | { 10 | unsigned int a = 8; 11 | int result = ((a << 30) | (a >> 2)); 12 | 13 | return result; 14 | } 15 | 16 | #ifdef TEST_ROXV 17 | 18 | int test_rotate_left1() 19 | { 20 | volatile unsigned int a = 4; 21 | volatile int n = 30; 22 | int result = ((a << n) | (a >> (32 - n))); 23 | 24 | return result; 25 | } 26 | 27 | int test_rotate_right() 28 | { 29 | volatile unsigned int a = 1; 30 | volatile int n = 30; 31 | int result = ((a >> n) | (a << (32 - n))); 32 | 33 | return result; 34 | } 35 | 36 | #endif 37 | -------------------------------------------------------------------------------- /lbdex/input/ch4_1_sub.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch4_1_sub.cpp -emit-llvm -o ch4_1_sub.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch4_1_sub.bc -o - 3 | 4 | #include 5 | 6 | int test_sub() 7 | { 8 | int a = 0x7FFFFFFF; 9 | int b = 0x80000001; 10 | 11 | int d = a - b; // d = 3 12 | return d; 13 | } 14 | 15 | int main() { 16 | int res = test_sub(); 17 | printf("res: %d\n", res); 18 | } 19 | -------------------------------------------------------------------------------- /lbdex/input/ch4_2_slt_explain.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch4_2_slt_explain.cpp -emit-llvm -o ch4_2_slt_explain.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -relocation-model=static -filetype=asm ch4_2_slt_explain.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032II -relocation-model=static -filetype=asm ch4_2_slt_explain.bc -o - 4 | 5 | 6 | /// start 7 | int test_OptSlt() 8 | { 9 | int a = 3, b = 1; 10 | int d = 0, e = 0, f = 0; 11 | 12 | d = (a < 1); 13 | e = (b < 2); 14 | f = d + e; 15 | 16 | return (f); 17 | } 18 | -------------------------------------------------------------------------------- /lbdex/input/ch4_math.ll: -------------------------------------------------------------------------------- 1 | 2 | ; Function Attrs: nounwind 3 | define i32 @_Z9test_mathv() #0 { 4 | %a = alloca i32, align 4 5 | %b = alloca i32, align 4 6 | %1 = load i32, i32* %a, align 4 7 | %2 = load i32, i32* %b, align 4 8 | 9 | %3 = add nsw i32 %1, %2 10 | %4 = sub nsw i32 %1, %2 11 | %5 = mul nsw i32 %1, %2 12 | %6 = shl i32 %1, 2 13 | %7 = ashr i32 %1, 2 14 | %8 = lshr i32 %1, 30 15 | %9 = shl i32 1, %2 16 | %10 = ashr i32 128, %2 17 | %11 = ashr i32 %1, %2 18 | 19 | %12 = add nsw i32 %3, %4 20 | %13 = add nsw i32 %12, %5 21 | %14 = add nsw i32 %13, %6 22 | %15 = add nsw i32 %14, %7 23 | %16 = add nsw i32 %15, %8 24 | %17 = add nsw i32 %16, %9 25 | %18 = add nsw i32 %17, %10 26 | %19 = add nsw i32 %18, %11 27 | 28 | ret i32 %19 29 | } 30 | 31 | -------------------------------------------------------------------------------- /lbdex/input/ch4_overflow.ll: -------------------------------------------------------------------------------- 1 | 2 | ; Function Attrs: nounwind 3 | define i32 @_Z17test_add_overflowv() #0 { 4 | %a = alloca i32, align 4 5 | %b = alloca i32, align 4 6 | %1 = load i32* %a, align 4 7 | %2 = load i32* %b, align 4 8 | 9 | %3 = add nsw i32 %1, %2 10 | %4 = sub nsw i32 %1, %2 11 | 12 | %5 = add nsw i32 %3, %4 13 | ret i32 %5 14 | } 15 | 16 | -------------------------------------------------------------------------------- /lbdex/input/ch6_1.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch6_1.cpp -emit-llvm -o ch6_1.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -cpu0-use-small-section=true -filetype=asm ch6_1.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -cpu0-use-small-section=false -filetype=asm ch6_1.bc -o - 4 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=static -cpu0-use-small-section=true -filetype=asm ch6_1.bc -o - 5 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=static -cpu0-use-small-section=false -filetype=asm ch6_1.bc -o - 6 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=static -filetype=obj ch6_1.bc -o ch6_1.cpu0.static.o 7 | // /Applications/Xcode.app/Contents/Developer/usr/bin/lldb -- /Users/Jonathan/llvm/test/build/bin/llc -march=cpu0 -filetype=asm ch6_1.bc -o ch6_1.cpu0.s 8 | 9 | /// start 10 | int gStart = 3; 11 | int gI = 100; 12 | int test_global() 13 | { 14 | int c = 0; 15 | 16 | c = gI; 17 | 18 | return c; 19 | } 20 | -------------------------------------------------------------------------------- /lbdex/input/ch7_1_array.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch7_1_array.cpp -emit-llvm -o ch7_1_array.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=static -filetype=asm ch7_1_array.bc -o - 3 | 4 | /// start 5 | 6 | // Need libc to do array init. ref. http://www.dbp-consulting.com/tutorials/debugging/linuxProgramStartup.html 7 | int ta[][4] = 8 | { 9 | {0x00000000, 0x00000001, 0x00000000} 10 | }; 11 | 12 | int test_array() 13 | { 14 | return ta[0][1]; 15 | } 16 | -------------------------------------------------------------------------------- /lbdex/input/ch7_1_bool.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch7_1_bool.cpp -emit-llvm -o ch7_1_bool.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch7_1_bool.bc -o - 3 | 4 | /// start 5 | bool test_load_bool() 6 | { 7 | int a = 1; 8 | 9 | if (a < 0) 10 | return false; 11 | 12 | return true; 13 | } 14 | 15 | -------------------------------------------------------------------------------- /lbdex/input/ch7_1_bool2.ll: -------------------------------------------------------------------------------- 1 | ; ~/llvm/test/build/Debug/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch7_1_bool2.ll -o - 2 | 3 | ; /// start 4 | define zeroext i1 @verify_load_bool() #0 { 5 | entry: 6 | %retval = alloca i1, align 1 7 | store i1 1, i1* %retval, align 1 8 | %0 = load i1, i1* %retval 9 | ret i1 %0 10 | } 11 | -------------------------------------------------------------------------------- /lbdex/input/ch7_1_char_in_struct.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch7_1_char_in_struct.cpp -emit-llvm -o ch7_1_char_in_struct.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch7_1_char_in_struct.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=static -filetype=asm ch7_1_char_in_struct.bc -o - 4 | 5 | /// start 6 | struct Date 7 | { 8 | short year; 9 | char month; 10 | char day; 11 | char hour; 12 | char minute; 13 | char second; 14 | }; 15 | 16 | unsigned char b[4] = {'a', 'b', 'c', '\0'}; 17 | 18 | int test_char() 19 | { 20 | unsigned char a = b[1]; 21 | char c = (char)b[1]; 22 | Date date1 = {2012, (char)11, (char)25, (char)9, (char)40, (char)15}; 23 | char m = date1.month; 24 | char s = date1.second; 25 | 26 | return 0; 27 | } 28 | 29 | -------------------------------------------------------------------------------- /lbdex/input/ch7_1_fmul.c: -------------------------------------------------------------------------------- 1 | /* 2 | ~/llvm/debug/build/bin/clang -target mips-unknown-linux-gnu -emit-llvm -S ch7_1_fmul.c 3 | ... 4 | %mul = fmul float %0, %1 5 | 6 | ~/llvm/debug/build/bin/llc -march=mips ch7_1_fmul.ll -relocation-model=static -o - 7 | ... 8 | v_log_f32_e32 v1, v0 9 | v_mul_legacy_f32_e32 v0, v0, v1 10 | v_exp_f32_e32 v0, v0 11 | 12 | ~/llvm/test/build/bin/llc -march=cpu0 ch7_1_fmul.ll -relocation-model=static -o - 13 | ... 14 | jsub __mulsf3 15 | */ 16 | 17 | float ch7_1_fmul(float a, float b) { 18 | float c = a * b; 19 | return c; 20 | } 21 | -------------------------------------------------------------------------------- /lbdex/input/ch7_1_globalstructoffset.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch7_1_globalstructoffset.cpp -emit-llvm -o ch7_1_globalstructoffset.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=static -filetype=asm ch7_1_globalstructoffset.bc -o - 3 | 4 | // No need to verify in ch_nolld.cpp since test_func_arg_struct() of ch9_2_1.cpp include the test already 5 | 6 | /// start 7 | struct Date 8 | { 9 | int year; 10 | int month; 11 | int day; 12 | }; 13 | 14 | Date date = {2012, 10, 12}; 15 | int a[3] = {2012, 10, 12}; 16 | 17 | int test_struct() 18 | { 19 | int day = date.day; 20 | int i = a[1]; 21 | 22 | return (i+day); // 10+12=22 23 | } 24 | 25 | -------------------------------------------------------------------------------- /lbdex/input/ch7_1_localarrayinit.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch7_1_localarrayinit.cpp -emit-llvm -o ch7_1_localarrayinit.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch7_1_localarrayinit.bc -o - 3 | 4 | /// start 5 | int main() 6 | { 7 | int a[3]={0, 1, 2}; 8 | 9 | return 0; 10 | } 11 | -------------------------------------------------------------------------------- /lbdex/input/ch7_1_localpointer.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch7_1_localpointer.cpp -emit-llvm -o ch7_1_localpointer.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch7_1_localpointer.bc -o - 3 | 4 | /// start 5 | int test_local_pointer() 6 | { 7 | int b = 3; 8 | 9 | int* p = &b; 10 | 11 | return *p; 12 | } 13 | -------------------------------------------------------------------------------- /lbdex/input/ch7_1_longlong.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -S ch7_1_longlong.cpp -emit-llvm 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -relocation-model=static -filetype=asm ch7_1_longlong.ll 3 | 4 | /// start 5 | long long test_longlong() 6 | { 7 | long long a = 0x300000002; 8 | long long b = 0x100000001; 9 | int a1 = 0x3001000; 10 | int b1 = 0x2001000; 11 | 12 | long long c = a + b; // c = 0x00000004,00000003 13 | long long d = a - b; // d = 0x00000002,00000001 14 | long long e = a * b; // e = 0x00000005,00000002 15 | long long f = (long long)a1 * (long long)b1; // f = 0x00060050,01000000 16 | 17 | long long g = ((-7 * 8) + 1) >> 4; // g = -55/16=-3.4375=-4 18 | 19 | return (c+d+e+f+g); // (0x0006005b,01000002) = (393307,16777218) 20 | } 21 | 22 | -------------------------------------------------------------------------------- /lbdex/input/ch8_1_1.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch8_1_1.cpp -emit-llvm -o ch8_1_1.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -filetype=asm ch8_1_1.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic -filetype=asm ch8_1_1.bc -o - 4 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -view-isel-dags -relocation-model=pic -filetype=asm ch8_1_1.bc -o - 5 | 6 | /// start 7 | int test_ifctrl() 8 | { 9 | unsigned int a = 0; 10 | 11 | if (a == 0) { 12 | a++; // a = 1 13 | } 14 | 15 | return a; 16 | } 17 | -------------------------------------------------------------------------------- /lbdex/input/ch8_1_blockaddr.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch8_1_blockaddr.cpp -emit-llvm -o ch8_1_blockaddr.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=static -filetype=asm ch8_1_blockaddr.bc -o - 3 | 4 | /// start 5 | int test_blockaddress(int x) { 6 | const void *addr = &&FOO; 7 | if (x == 1) 8 | goto *addr; 9 | 10 | return 2; 11 | FOO: 12 | return 1; 13 | } 14 | -------------------------------------------------------------------------------- /lbdex/input/ch8_2_deluselessjmp.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch8_2_deluselessjmp.cpp -emit-llvm -o ch8_2_deluselessjmp.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -relocation-model=static -filetype=asm -enable-cpu0-del-useless-jmp=false ch8_2_deluselessjmp.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -relocation-model=static -filetype=asm -stats ch8_2_deluselessjmp.bc -o - 4 | 5 | /// start 6 | int test_DelUselessJMP() 7 | { 8 | int a = 1; int b = -2; int c = 3; 9 | 10 | if (a == 0) { 11 | a++; 12 | } 13 | if (b == 0) { 14 | a = a + 3; 15 | b++; 16 | } else if (b < 0) { 17 | a = a + b; 18 | b--; 19 | } 20 | if (c > 0) { 21 | a = a + c; 22 | c++; 23 | } 24 | 25 | return a; 26 | } 27 | 28 | -------------------------------------------------------------------------------- /lbdex/input/ch8_2_longbranch.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch8_2_longbranch.cpp -emit-llvm -o ch8_2_longbranch.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic -filetype=asm -force-cpu0-long-branch ch8_2_longbranch.bc -o - 3 | 4 | /// start 5 | int test_longbranch() 6 | { 7 | volatile int a = 2; 8 | volatile int b = 1; 9 | int result = 0; 10 | 11 | if (a < b) 12 | result = 1; 13 | return result; 14 | } 15 | 16 | -------------------------------------------------------------------------------- /lbdex/input/ch8_2_phinode.cpp: -------------------------------------------------------------------------------- 1 | // ~/llvm/debug/build/bin/clang -O3 -target mips-unknown-linux-gnu -c ch8_2_phinode.cpp -emit-llvm -o ch8_2_phinode.bc 2 | // ~/llvm/debug/build/bin/clang -O0 -target mips-unknown-linux-gnu -c ch8_2_phinode.cpp -emit-llvm -o ch8_2_phinode.bc 3 | // ~/llvm/test/build/bin/llvm-dis ch8_2_phinode.bc -o - 4 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -filetype=asm ch8_2_phinode.bc -o - 5 | 6 | /// start 7 | int test_phinode(int a , int b, int c) 8 | { 9 | int d = 2; 10 | 11 | if (a == 0) { 12 | a = a+1; // a = 1 13 | } 14 | else if (b != 0) { 15 | a = a-1; 16 | } 17 | else if (c == 0) { 18 | a = a+2; 19 | } 20 | d = a + b; 21 | 22 | return d; 23 | } 24 | -------------------------------------------------------------------------------- /lbdex/input/ch8_2_select.cpp: -------------------------------------------------------------------------------- 1 | // clang -O0 -c ch8_3.cpp -emit-llvm -o ch8_3.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -relocation-model=static -filetype=asm ch8_3.bc -o - 3 | 4 | /// start 5 | 6 | // The following files will generate IR select even compile with clang -O0. 7 | int test_movx_1() 8 | { 9 | volatile int a = 1; 10 | int c = 0; 11 | 12 | c = !a ? 1:3; 13 | 14 | return c; 15 | } 16 | 17 | int test_movx_2() 18 | { 19 | volatile int a = 1; 20 | int c = 0; 21 | 22 | c = a ? 1:3; 23 | 24 | return c; 25 | } 26 | 27 | -------------------------------------------------------------------------------- /lbdex/input/ch8_2_select2.cpp: -------------------------------------------------------------------------------- 1 | // clang -O1 -c ch8_3_2.cpp -emit-llvm -o ch8_3_2.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -relocation-model=static -filetype=asm ch8_3_2.bc -o - 3 | 4 | /// start 5 | 6 | // The following files will generate IR select when compile with clang -O1 but 7 | // clang -O0 won't generate IR select. 8 | volatile int a = 1; 9 | volatile int b = 2; 10 | 11 | int test_movx_3() 12 | { 13 | int c = 0; 14 | 15 | if (a < b) 16 | return 1; 17 | else 18 | return 2; 19 | } 20 | 21 | int test_movx_4() 22 | { 23 | int c = 0; 24 | 25 | if (a) 26 | c = 1; 27 | else 28 | c = 3; 29 | 30 | return c; 31 | } 32 | 33 | -------------------------------------------------------------------------------- /lbdex/input/ch8_2_select_global_pic.cpp: -------------------------------------------------------------------------------- 1 | // clang -O1 -target mips-unknown-linux-gnu -c ch8_2_select_global_pic.cpp -emit-llvm -o ch8_2_select_global_pic.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -filetype=asm ch8_2_select_global_pic.bc -o - 3 | 4 | // No need to verify. Build test only. 5 | 6 | /// start 7 | volatile int a1 = 1; 8 | volatile int b1 = 2; 9 | 10 | int gI1 = 100; 11 | int gJ1 = 50; 12 | 13 | int test_select_global_pic() 14 | { 15 | if (a1 < b1) 16 | return gI1; 17 | else 18 | return gJ1; 19 | } 20 | -------------------------------------------------------------------------------- /lbdex/input/ch9_1.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch9_1.cpp -emit-llvm -o ch9_1.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch9_1.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=mips -relocation-model=pic -filetype=asm ch9_1.bc -o - 4 | 5 | /// start 6 | int gI = 100; 7 | 8 | int sum_i(int x1, int x2, int x3, int x4, int x5, int x6) 9 | { 10 | int sum = gI + x1 + x2 + x3 + x4 + x5 + x6; 11 | 12 | return sum; 13 | } 14 | 15 | int main() 16 | { 17 | int a = sum_i(1, 2, 3, 4, 5, 6); 18 | 19 | return a; 20 | } 21 | -------------------------------------------------------------------------------- /lbdex/input/ch9_1_2.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch9_1_2.cpp -emit-llvm -o ch9_1_2.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=static -filetype=asm ch9_1_2.bc -o - 3 | 4 | /// start 5 | int main() 6 | { 7 | char str[81] = "Hello world"; 8 | char s[6] = "Hello"; 9 | 10 | return 0; 11 | } 12 | -------------------------------------------------------------------------------- /lbdex/input/ch9_1_longlong.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch9_1_longlong.cpp -emit-llvm -o ch9_1_longlong.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=static -filetype=asm ch9_1_longlong.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=mips -relocation-model=static -filetype=asm ch9_1_longlong.bc -o - 4 | 5 | /// start 6 | 7 | long long sum_longlong(long long x1, long long x2, long long x3, long long x4, long long x5, long long x6) 8 | { 9 | long long sum = x1 + x2 + x3 + x4 + x5 + x6; 10 | 11 | return sum; 12 | } 13 | 14 | int test_sum_longlong() 15 | { 16 | long long a = sum_longlong(1, 2, 3, 4, 5, -6); 17 | 18 | return (int)a; // 9 19 | } 20 | -------------------------------------------------------------------------------- /lbdex/input/ch9_2_tailcall.cpp: -------------------------------------------------------------------------------- 1 | // clang -O1 -target mips-unknown-linux-gnu -c ch9_2_tailcall.cpp -emit-llvm -o ch9_2_tailcall.bc 2 | // ~llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032II -relocation-model=static -filetype=asm -enable-cpu0-tail-calls -view-isel-dags ch9_2_tailcall.bc -stats -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032II -relocation-model=static -filetype=asm -enable-cpu0-tail-calls -view-sched-dags ch9_2_tailcall.bc -stats -o - 4 | 5 | /// start 6 | 7 | int factorial(int x) 8 | { 9 | if (x > 0) 10 | return x*factorial(x-1); 11 | else 12 | return 1; 13 | } 14 | 15 | int test_tailcall(int a) 16 | { 17 | return factorial(a); 18 | } 19 | 20 | -------------------------------------------------------------------------------- /lbdex/input/ch9_3_bswap.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch9_3_bswap.cpp -emit-llvm -o ch9_3_bswap.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -filetype=asm ch9_3_bswap.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic -filetype=asm ch9_3_bswap.bc -o - 4 | 5 | 6 | /// start 7 | int test_bswap16() { 8 | volatile int a = 0x1234; 9 | int result = (__builtin_bswap16(a) ^ 0x3412); 10 | 11 | return result; 12 | } 13 | 14 | int test_bswap32() { 15 | volatile int a = 0x1234; 16 | int result = (__builtin_bswap32(a) ^ 0x34120000); 17 | 18 | return result; 19 | } 20 | 21 | int test_bswap64() { 22 | volatile int a = 0x1234; 23 | int result = (__builtin_bswap64(a) ^ 0x3412000000000000); 24 | 25 | return result; 26 | } 27 | 28 | int test_bswap() { 29 | int result = test_bswap16() + test_bswap32() + test_bswap64(); 30 | 31 | return result; 32 | } 33 | -------------------------------------------------------------------------------- /lbdex/input/ch9_3_frame_return_addr.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch9_3_frame_return_addr.cpp -emit-llvm -o ch9_3_frame_return_addr.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=static -filetype=asm ch9_3_frame_return_addr.bc -o - 3 | 4 | /// start 5 | int display_frameaddress() { 6 | return (int)__builtin_frame_address(0); 7 | } 8 | 9 | extern int fn(); 10 | 11 | int display_returnaddress() { 12 | int a = (int)__builtin_return_address(0); 13 | fn(); 14 | return a; 15 | } 16 | -------------------------------------------------------------------------------- /lbdex/input/ch9_3_longlongshift.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch9_3_longlongshift.cpp -emit-llvm -o ch9_3_longlongshift.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -filetype=asm ch9_3_longlongshift.bc -o - 3 | 4 | // Need soft float point library support 5 | 6 | /// start 7 | #include "debug.h" 8 | 9 | long long test_longlong_shift1() 10 | { 11 | long long a = 4; 12 | long long b = 0x12; 13 | long long c; 14 | long long d; 15 | 16 | c = (b >> a); // cc = 0x1 17 | d = (b << a); // cc = 0x120 18 | 19 | long long e = 0x7FFFFFFFFFFFFFFLL >> 63; 20 | return (c+d+e); // 0x121 = 289 21 | } 22 | 23 | long long test_longlong_shift2() 24 | { 25 | long long a = 48; 26 | long long b = 0x001666660000000a; 27 | long long c; 28 | 29 | c = (b >> a); 30 | 31 | return c; // 22 32 | } 33 | 34 | -------------------------------------------------------------------------------- /lbdex/input/ch9_3_stacksave.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch9_3_stacksave.cpp -emit-llvm -o ch9_3_stacksave.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch9_3_stacksave.bc -o - 3 | 4 | /// start 5 | int test_stacksaverestore(unsigned x) { 6 | // CHECK: call i8* @llvm.stacksave() 7 | char s1[x]; 8 | s1[x] = 5; 9 | 10 | return s1[x]; 11 | // CHECK: call void @llvm.stackrestore(i8* 12 | } -------------------------------------------------------------------------------- /lbdex/input/ch9_3_template.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch9_3_template.cpp -emit-llvm -o ch9_3_template.bc 2 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch9_3_template.bc -o ch9_3_template.cpu0.s 3 | // ~/llvm/test/build/bin/llc -march=mips -relocation-model=pic -filetype=asm ch9_3_template.bc -o ch9_3_template.mips.s 4 | 5 | /// start 6 | #include 7 | 8 | template 9 | T sum(T amount, ...) 10 | { 11 | T i = 0; 12 | T val = 0; 13 | T sum = 0; 14 | 15 | va_list vl; 16 | va_start(vl, amount); 17 | for (i = 0; i < amount; i++) 18 | { 19 | val = va_arg(vl, T); 20 | sum += val; 21 | } 22 | va_end(vl); 23 | 24 | return sum; 25 | } 26 | 27 | int test_template() 28 | { 29 | int a = (int)(sum(6, 0, 1, 2, 3, 4, 5)); 30 | 31 | return a; // 15 32 | } 33 | 34 | long long test_template_ll() 35 | { 36 | long long a = (long long)(sum(6LL, 0LL, 1LL, 2LL, -3LL, 4LL, -5LL)); 37 | 38 | return a; // -1 39 | } 40 | -------------------------------------------------------------------------------- /lbdex/input/ch9_caller_callee_save_registers.cpp: -------------------------------------------------------------------------------- 1 | // clang -O0 -target mips-unknown-linux-gnu -c ch9_caller_callee_save_registers.cpp -emit-llvm -o ch9_caller_callee_save_registers.bc 2 | // ~/llvm/test/build/bin/llc -O0 -march=cpu0 -relocation-model=static -filetype=asm ch9_caller_callee_save_registers.bc -o - 3 | // ~/llvm/debug/build/bin/llc -O0 -march=mips -relocation-model=static -filetype=asm ch9_caller_callee_save_registers.bc -o - 4 | 5 | /// start 6 | extern int add1(int x); 7 | 8 | int callee() 9 | { 10 | int t1 = 3; 11 | int result = add1(t1); 12 | result = result - t1; 13 | 14 | return result; 15 | } 16 | -------------------------------------------------------------------------------- /lbdex/input/ch9_gprestore.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch9_gprestore.cpp -emit-llvm -o ch9_gprestore.bc 2 | // ~/llvm/test/build/bin/llvm-dis ch9_gprestore.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -filetype=asm ch9_gprestore.bc -o - 4 | 5 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic -filetype=asm ch9_gprestore.bc -o - 6 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic -filetype=asm ch9_gprestore.bc -cpu0-no-cpload -cpu0-reserve-gp -o - 7 | 8 | /// start 9 | extern int sum_i(int x1); 10 | 11 | int call_sum_i() { 12 | int a = sum_i(1); 13 | a += sum_i(2); 14 | return a; 15 | } 16 | -------------------------------------------------------------------------------- /lbdex/input/ch9_incoming.cpp: -------------------------------------------------------------------------------- 1 | // clang -O3 -target mips-unknown-linux-gnu -c ch9_incoming.cpp -emit-llvm -o ch9_incoming.bc 2 | // ~/llvm/test/build/bin/llvm-dis ch9_incoming.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032II -view-dag-combine1-dags -relocation-model=pic -filetype=asm ch9_incoming.bc -o - 4 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -view-dag-combine1-dags -relocation-model=pic -filetype=asm ch9_incoming.bc -o - 5 | 6 | /// start 7 | int sum_i(int x1, int x2, int x3) 8 | { 9 | int sum = x1 + x2 + x3; 10 | 11 | return sum; 12 | } 13 | -------------------------------------------------------------------------------- /lbdex/input/ch9_outgoing.cpp: -------------------------------------------------------------------------------- 1 | // clang -O3 -target mips-unknown-linux-gnu -c ch9_outgoing.cpp -emit-llvm -o ch9_outgoing.bc 2 | // ~/llvm/test/build/bin/llvm-dis ch9_outgoing.bc -o - 3 | // ~/llvm/test/build/bin/llc -march=cpu0 -mcpu=cpu032I -view-dag-combine1-dags -relocation-model=static -filetype=asm ch9_outgoing.bc -o - 4 | 5 | /// start 6 | extern int sum_i(int x1); 7 | 8 | int call_sum_i() { 9 | return sum_i(1); 10 | } 11 | -------------------------------------------------------------------------------- /lbdex/input/ch_nolld.h: -------------------------------------------------------------------------------- 1 | 2 | /// start 3 | 4 | #include "debug.h" 5 | #include "boot.cpp" 6 | 7 | #include "print.h" 8 | 9 | int test_nolld(); 10 | -------------------------------------------------------------------------------- /lbdex/input/ch_nolld2.cpp: -------------------------------------------------------------------------------- 1 | 2 | /// start 3 | 4 | #include "print.cpp" 5 | 6 | #include "ch9_3_alloc.cpp" 7 | 8 | int test_nolld2() 9 | { 10 | bool pass = true; 11 | int a = 0; 12 | 13 | a = test_alloc(); 14 | print_integer(a); // a = 31 15 | if (a != 31) pass = false; 16 | return pass; 17 | } 18 | 19 | -------------------------------------------------------------------------------- /lbdex/input/ch_nolld2.h: -------------------------------------------------------------------------------- 1 | 2 | /// start 3 | 4 | #include "debug.h" 5 | #include "boot.cpp" 6 | 7 | #include "print.h" 8 | 9 | int test_nolld2(); 10 | -------------------------------------------------------------------------------- /lbdex/input/ch_run_backend.cpp: -------------------------------------------------------------------------------- 1 | // bash build-run_backend.sh 2 | 3 | /// start 4 | 5 | #include "ch_nolld.h" 6 | 7 | int main() 8 | { 9 | bool pass = true; 10 | pass = test_nolld(); 11 | 12 | return pass; 13 | } 14 | 15 | #include "ch_nolld.cpp" 16 | -------------------------------------------------------------------------------- /lbdex/input/ch_run_backend2.cpp: -------------------------------------------------------------------------------- 1 | // bash build-run_backend2.sh cpu032I le 2 | // bash build-run_backend2.sh cpu032II be 3 | 4 | /// start 5 | 6 | #include "ch_nolld2.h" 7 | 8 | int main() 9 | { 10 | bool pass = true; 11 | pass = test_nolld2(); 12 | 13 | return pass; 14 | } 15 | 16 | #include "ch_nolld2.cpp" 17 | -------------------------------------------------------------------------------- /lbdex/input/ch_srem.ll: -------------------------------------------------------------------------------- 1 | 2 | /// start 3 | define i32 @srem(i32 %b) nounwind readnone { 4 | entry: 5 | %rem = srem i32 %b, 12 6 | ret i32 %rem 7 | } 8 | 9 | -------------------------------------------------------------------------------- /lbdex/input/ch_test_7_3.cpp: -------------------------------------------------------------------------------- 1 | // Set break point at MipsEmitGPRestore.cpp:70, it will stop at mips of llc. 2 | 3 | // clang -c ch7_3.cpp -o ch7_3.bc -o ch7_3.bc 4 | // ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch7_3.bc -o ch7_3.cpu0.s 5 | // ~/llvm/test/build/bin/llc -march=mips -relocation-model=pic -filetype=asm ch7_3.bc -o ch7_3.mips.s 6 | 7 | /// start 8 | #include 9 | 10 | using namespace std; 11 | 12 | int gI = 100; 13 | 14 | int sum_i(int x1, int x2, int x3, int x4, int x5, int x6) 15 | { 16 | int sum = gI + x1 + x2 + x3 + x4 + x5 + x6; 17 | 18 | return sum; 19 | } 20 | 21 | int main() 22 | { 23 | vector v; 24 | 25 | try { 26 | v.push_back(2); 27 | } 28 | catch (...) { 29 | return 1; 30 | } 31 | 32 | int a = sum_i(1, 2, 3, 4, 5, 6); 33 | 34 | 35 | return a; 36 | } 37 | -------------------------------------------------------------------------------- /lbdex/input/clean.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | PWD=`pwd` 4 | pushd ${PWD} 5 | rm -rf a.out ../verilog/dlconfig cpu0.hex *~ libfoobar.cpu0.so *.o *.bc *.s *.S 6 | popd 7 | 8 | -------------------------------------------------------------------------------- /lbdex/input/config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CONFIG_H_ 2 | #define _CONFIG_H_ 3 | 4 | // defined in cpu0.v 5 | #define IOADDR 0xff000000 6 | 7 | // $sp begin at mem less than MEMSIZE of cpu0.v 8 | #define INIT_SP \ 9 | asm("addiu $sp, $zero, 0x0000"); \ 10 | asm("lui $sp, 0xff"); 11 | 12 | // default test part of 1 in 10 for udivmoddi4_test.c 13 | //#define TEST_FULL 14 | //#define TEST_HALF 15 | 16 | // TEST_FULL in udivmoddi4_test.c 17 | #ifdef TEST_FULL 18 | #define PART_2_IN_10 19 | #define PART_HALF 20 | #else 21 | #ifdef TEST_HALF 22 | #define PART_HALF 23 | #endif 24 | #endif 25 | 26 | #endif 27 | -------------------------------------------------------------------------------- /lbdex/input/cpu0_gcd.ll: -------------------------------------------------------------------------------- 1 | ; ~/llvm/test/build/bin/llc -debug -print-after-all -march=cpu0 -mcpu=cpu032II -relocation-model=pic cpu0_gcd.ll -o - 2 | 3 | define i32 @llvm_cpu0_gcd_test(i32 %a, i32 %b) nounwind { 4 | entry: 5 | %res = tail call i32 @llvm.cpu0.gcd(i32 %a, i32 %b) 6 | ret i32 %res 7 | } 8 | 9 | declare i32 @llvm.cpu0.gcd(i32, i32) nounwind 10 | 11 | -------------------------------------------------------------------------------- /lbdex/input/cpu0_gcd_soft.ll: -------------------------------------------------------------------------------- 1 | ; ~/llvm/test/build/bin/llc -debug -print-after-all -march=cpu0 -mcpu=cpu032II -relocation-model=pic cpu0_gcd_soft.ll -o - 2 | 3 | define i32 @llvm_cpu0_gcd_soft_test(i32 %a, i32 %b) nounwind { 4 | entry: 5 | %res = tail call i32 @cpu0_gcd_soft(i32 %a, i32 %b) 6 | ret i32 %res 7 | } 8 | 9 | declare i32 @cpu0_gcd_soft(i32, i32) nounwind 10 | 11 | -------------------------------------------------------------------------------- /lbdex/input/cpu0_sqrt.ll: -------------------------------------------------------------------------------- 1 | ; ~/llvm/test/build/bin/llc -debug -march=cpu0 -mcpu=cpu0II -relocation-model=pic cpu0_sqrt.ll -o - 2 | 3 | define i32 @llvm_cpu0_sqrt_test(i32 %a, i32 %b) nounwind { 4 | entry: 5 | %res = tail call i32 @llvm.cpu0.sqrt(i32 %a, i32 %b) 6 | ret i32 %res 7 | } 8 | 9 | declare i32 @llvm.cpu0.sqrt(i32, i32) nounwind 10 | 11 | -------------------------------------------------------------------------------- /lbdex/input/dump_mem.c: -------------------------------------------------------------------------------- 1 | 2 | /// start 3 | // Not work at this point 4 | void dump_mem(unsigned char *str, int n) 5 | { 6 | int i = 0; 7 | const unsigned char *p; 8 | 9 | for (i = 0, p = str; i < n; i++, p++) { 10 | unsigned char x = (*p >> 4); 11 | if (x > 0x0f) print_string("Err"); 12 | if (x <= 0x09) 13 | print_char(x+'0'); 14 | else 15 | print_char(x+'a'); 16 | x = (*p & 0x0f); 17 | if (x > 0x0f) print_string("Err"); 18 | if (x <= 0x09) 19 | print_char(x+'0'); 20 | else 21 | print_char(x+'a'); 22 | } 23 | print_char('\n'); 24 | 25 | return; 26 | } 27 | -------------------------------------------------------------------------------- /lbdex/input/hello.c: -------------------------------------------------------------------------------- 1 | 2 | // clang -c hello.c -emit-llvm -I/Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.8.sdk/usr/include/ -o hello.bc 3 | // llc hello.bc -o hello.s 4 | // gcc hello.s -o hello.native 5 | 6 | /// start 7 | #include 8 | 9 | int main() { 10 | printf("hello world\n"); 11 | return 0; 12 | } 13 | -------------------------------------------------------------------------------- /lbdex/input/memcpy.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c memcpy.cpp -emit-llvm -o - | llvm-dis -o memcpy.1.ll 2 | // Then modify memcpy.ll from memcpy.1.ll 3 | 4 | /// start 5 | void memcpy(char* dest, char* source, int size) 6 | { 7 | return; 8 | } 9 | 10 | -------------------------------------------------------------------------------- /lbdex/input/memcpy.ll: -------------------------------------------------------------------------------- 1 | ; ~/llvm/test/cmake_debug_build/bin/Debug/llc -march=cpu0 -relocation-model=static < memcpy.ll 2 | 3 | ; /// start 4 | ; ModuleID = 'memcpy.bc' 5 | target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" 6 | target triple = "mips-unknown-linux-gnu" 7 | 8 | ; Function Attrs: nounwind 9 | define void @memcpy(i8* %dest, i8* %source, i32 %size) #0 { 10 | entry: 11 | %dest.addr = alloca i8*, align 4 12 | %source.addr = alloca i8*, align 4 13 | %size.addr = alloca i32, align 4 14 | store i8* %dest, i8** %dest.addr, align 4 15 | store i8* %source, i8** %source.addr, align 4 16 | store i32 %size, i32* %size.addr, align 4 17 | ret void 18 | } 19 | 20 | attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 21 | -------------------------------------------------------------------------------- /lbdex/input/print.cpp: -------------------------------------------------------------------------------- 1 | 2 | /// start 3 | #include "print.h" 4 | #include "itoa.cpp" 5 | 6 | // For memory IO 7 | void print_char(const char c) 8 | { 9 | char *p = (char*)IOADDR; 10 | *p = c; 11 | 12 | return; 13 | } 14 | 15 | void print_string(const char *str) 16 | { 17 | const char *p; 18 | 19 | for (p = str; *p != '\0'; p++) 20 | print_char(*p); 21 | print_char(*p); 22 | print_char('\n'); 23 | 24 | return; 25 | } 26 | 27 | // For memory IO 28 | void print_integer(int x) 29 | { 30 | char str[INT_DIGITS + 2]; 31 | itoa(str, x); 32 | print_string(str); 33 | 34 | return; 35 | } 36 | 37 | -------------------------------------------------------------------------------- /lbdex/input/print.h: -------------------------------------------------------------------------------- 1 | 2 | /// start 3 | #ifndef _PRINT_H_ 4 | #define _PRINT_H_ 5 | 6 | #include "start.h" 7 | 8 | void print_char(const char c); 9 | void dump_mem(unsigned char *str, int n); 10 | void print_string(const char *str); 11 | void print_integer(int x); 12 | #endif 13 | -------------------------------------------------------------------------------- /lbdex/input/start.h: -------------------------------------------------------------------------------- 1 | 2 | /// start 3 | 4 | #ifndef _START_H_ 5 | #define _START_H_ 6 | 7 | #include "config.h" 8 | 9 | #define SET_SW \ 10 | asm("andi $sw, $zero, 0"); \ 11 | asm("ori $sw, $sw, 0x1e00"); // enable all interrupts 12 | 13 | #define initRegs() \ 14 | asm("addiu $1, $zero, 0"); \ 15 | asm("addiu $2, $zero, 0"); \ 16 | asm("addiu $3, $zero, 0"); \ 17 | asm("addiu $4, $zero, 0"); \ 18 | asm("addiu $5, $zero, 0"); \ 19 | asm("addiu $t9, $zero, 0"); \ 20 | asm("addiu $7, $zero, 0"); \ 21 | asm("addiu $8, $zero, 0"); \ 22 | asm("addiu $9, $zero, 0"); \ 23 | asm("addiu $10, $zero, 0"); \ 24 | SET_SW; \ 25 | asm("addiu $fp, $zero, 0"); 26 | 27 | #endif 28 | -------------------------------------------------------------------------------- /lbdex/llvm/modify/llvm/include/llvm/IR/IntrinsicsCpu0.td: -------------------------------------------------------------------------------- 1 | //===- IntrinsicsCpu0.td - Defines Mips intrinsics ---------*- tablegen -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file defines all of the CPU0-specific intrinsics. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | // __builtin_cpu0_gcd defined in 15 | // https://github.com/Jonathan2251/lbt/blob/master/exlbt/clang/include/clang/Basic/BuiltinsCpu0.def 16 | def int_cpu0_gcd : GCCBuiltin<"__builtin_cpu0_gcd">, 17 | Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 18 | [Commutative, IntrNoMem]>; 19 | -------------------------------------------------------------------------------- /lbdex/llvm/modify/llvm/tools/elf2hex/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # elf2hex.cpp needs backend related functions, like 2 | # LLVMInitializeCpu0TargetInfo and LLVMInitializeCpu0Disassembler ... etc. 3 | # Set LLVM_LINK_COMPONENTS then it can link them during the link stage. 4 | set(LLVM_LINK_COMPONENTS 5 | # AllTargetsAsmPrinters 6 | AllTargetsDescs 7 | AllTargetsDisassemblers 8 | AllTargetsInfos 9 | BinaryFormat 10 | CodeGen 11 | DebugInfoDWARF 12 | DebugInfoPDB 13 | Demangle 14 | MC 15 | MCDisassembler 16 | Object 17 | Support 18 | Symbolize 19 | ) 20 | 21 | add_llvm_tool(elf2hex 22 | elf2hex.cpp 23 | ) 24 | 25 | if(HAVE_LIBXAR) 26 | target_link_libraries(elf2hex PRIVATE ${XAR_LIB}) 27 | endif() 28 | 29 | if(LLVM_INSTALL_BINUTILS_SYMLINKS) 30 | add_llvm_tool_symlink(elf2hex elf2hex) 31 | endif() 32 | 33 | -------------------------------------------------------------------------------- /lbdex/opt/add.ll: -------------------------------------------------------------------------------- 1 | ; ~/llvm/debug/build/bin/opt -O3 -S add.ll -o - 2 | 3 | define i32 @add(i32 %a, i32 %b) nounwind { 4 | entry: 5 | %add = add i32 %a, %b 6 | ret i32 %add 7 | } 8 | 9 | define i32 @test() nounwind { 10 | entry: 11 | %call1 = call i32 @add(i32 1, i32 2) 12 | ret i32 %call1 13 | } 14 | -------------------------------------------------------------------------------- /lbdex/readme: -------------------------------------------------------------------------------- 1 | Build procedure: 2 | Explain in Appendix A. 3 | -------------------------------------------------------------------------------- /lbdex/regression-test/C++/ch7_4-longlong-add.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch7_4-longlong-add.cpp -emit-llvm -o ch7_4-longlong-add.bc 2 | // /Users/Jonathan/llvm/test/cmake_debug_build/bin/Debug/llvm-dis ch7_4-longlong-add.bc -o ch7_4-longlong-add.ll 3 | 4 | /// start 5 | long long test_longlong() 6 | { 7 | long long a = 0x300000002; 8 | long long b = 0x100000001; 9 | 10 | long long c = a + b; // c = 0x00000004,00000003 11 | 12 | return c; // c = 0x00000004,00000003 13 | } 14 | 15 | -------------------------------------------------------------------------------- /lbdex/regression-test/C++/ch7_4-longlong-sub.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch7_4-longlong-sub.cpp -emit-llvm -o ch7_4-longlong-sub.bc 2 | // /Users/Jonathan/llvm/test/cmake_debug_build/bin/Debug/llvm-dis ch7_4-longlong-sub.bc -o ch7_4-longlong-sub.ll 3 | 4 | /// start 5 | long long test_longlong() 6 | { 7 | long long a = 0x300000002; 8 | long long b = 0x100000001; 9 | 10 | long long c = a - b; // c = 0x00000004,00000003 11 | 12 | return c; // c = 0x00000002,00000001 13 | } 14 | 15 | -------------------------------------------------------------------------------- /lbdex/regression-test/C++/ch7_4-signed-int-mul.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch7_4-signed-int-mul.cpp -emit-llvm -o ch7_4-signed-int-mul.bc 2 | // /Users/Jonathan/llvm/test/cmake_debug_build/bin/Debug/llvm-dis ch7_4-signed-int-mul.bc -o ch7_4-signed-int-mul.ll 3 | 4 | /// start 5 | long long test_longlong() 6 | { 7 | int a1 = 0x3001000; 8 | int b1 = 0x2001000; 9 | 10 | long long f = (long long)a1 * (long long)b1; // f = 0x00060050,01000000 11 | 12 | return f; // f = 0x00060050,01000000 13 | } 14 | 15 | -------------------------------------------------------------------------------- /lbdex/regression-test/C++/ch7_4-signed-longlong-mul.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch7_4-signed-longlong-mul.cpp -emit-llvm -o ch7_4-signed-longlong-mul.bc 2 | // /Users/Jonathan/llvm/test/cmake_debug_build/bin/Debug/llvm-dis ch7_4-signed-longlong-mul.bc -o ch7_4-signed-longlong-mul.ll 3 | 4 | /// start 5 | long long test_longlong() 6 | { 7 | long long a = 0x300000002; 8 | long long b = 0x100000001; 9 | 10 | long long e = a * b; // e = 0x00000005,00000002 11 | 12 | return e; // e = 0x00000005,00000002 13 | } 14 | 15 | -------------------------------------------------------------------------------- /lbdex/regression-test/C++/ch7_4-unsigned-int-mul.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch7_4-unsigned-int-mul.cpp -emit-llvm -o ch7_4-unsigned-int-mul.bc 2 | // /Users/Jonathan/llvm/test/cmake_debug_build/bin/Debug/llvm-dis ch7_4-unsigned-int-mul.bc -o ch7_4-unsigned-int-mul.ll 3 | 4 | /// start 5 | long long test_longlong() 6 | { 7 | unsigned int a1 = 0x3001000; 8 | unsigned int b1 = 0x2001000; 9 | 10 | long long f = (long long)a1 * (long long)b1; // f = 0x00060050,01000000 11 | 12 | return f; // f = 0x00060050,01000000 13 | } 14 | 15 | -------------------------------------------------------------------------------- /lbdex/regression-test/C++/ch7_4-unsigned-longlong-mul.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch7_4-unsigned-longlong-mul.cpp -emit-llvm -o ch7_4-unsigned-longlong-mul.bc 2 | // /Users/Jonathan/llvm/test/cmake_debug_build/bin/Debug/llvm-dis ch7_4-unsigned-longlong-mul.bc -o ch7_4-unsigned-longlong-mul.ll 3 | 4 | /// start 5 | long long test_longlong() 6 | { 7 | unsigned long long a = 0x300000002; 8 | unsigned long long b = 0x400000001; 9 | 10 | unsigned long long e = a * b; // e = 0xc0000005,00000002 11 | 12 | return e; // e = 0x00000005,00000002 13 | } 14 | 15 | -------------------------------------------------------------------------------- /lbdex/regression-test/C++/ch7_5-global-array.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch7_5-global-array.cpp -emit-llvm -o ch7_5-global-array.bc 2 | // /Users/Jonathan/llvm/test/cmake_debug_build/bin/Debug/llvm-dis ch7_5-global-array.bc -o ch7_5-global-array.ll 3 | 4 | /// start 5 | int a[3] = {2012, 10, 12}; 6 | 7 | int test_struct() 8 | { 9 | int i = a[1]; 10 | 11 | return i; // 10 12 | } 13 | 14 | -------------------------------------------------------------------------------- /lbdex/regression-test/C++/ch7_5-global-struct.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -c ch7_5-global-struct.cpp -emit-llvm -o ch7_5-global-struct.bc 2 | // /Users/Jonathan/llvm/test/cmake_debug_build/bin/Debug/llvm-dis ch7_5-global-struct.bc -o ch7_5-global-struct.ll 3 | 4 | /// start 5 | struct Date 6 | { 7 | int year; 8 | int month; 9 | int day; 10 | }; 11 | 12 | Date date = {2012, 10, 12}; 13 | 14 | int test_struct() 15 | { 16 | int day = date.day; 17 | 18 | return day; // 2012 19 | } 20 | 21 | -------------------------------------------------------------------------------- /lbdex/regression-test/C++/ch9_3-vararg.cpp: -------------------------------------------------------------------------------- 1 | // clang -target mips-unknown-linux-gnu -S ch9_3-vararg.cpp -emit-llvm -O3 -o ch9_3-vararg.ll 2 | 3 | /// start 4 | #include 5 | 6 | int sum_i(int amount, ...) 7 | { 8 | int i = 0; 9 | int val = 0; 10 | int sum = 0; 11 | 12 | va_list vl; 13 | va_start(vl, amount); 14 | for (i = 0; i < amount; i++) 15 | { 16 | val = va_arg(vl, int); 17 | sum += val; 18 | } 19 | va_end(vl); 20 | 21 | return sum; 22 | } 23 | 24 | int test_vararg() 25 | { 26 | int a = sum_i(6, 0, 1, 2, 3, 4, 5); 27 | 28 | return a; 29 | } 30 | -------------------------------------------------------------------------------- /lbdex/regression-test/C++/ch9_4-alloc.cpp: -------------------------------------------------------------------------------- 1 | // Don't use -target mips-unknown-linux-gnu option in clang since my PC is 64 bits computer. 2 | 3 | // clang -S ch9_4-alloc.cpp -emit-llvm -O3 -o ch9_4-alloc.ll 4 | 5 | /// start 6 | //#include 7 | #include 8 | 9 | int sum(int x1, int x2, int x3, int x4, int x5, int x6) 10 | { 11 | int sum = x1 + x2 + x3 + x4 + x5 + x6; 12 | 13 | return sum; 14 | } 15 | 16 | int weight_sum(int x1, int x2, int x3, int x4, int x5, int x6) 17 | { 18 | int *b = (int*)alloca(sizeof(int) * x1); 19 | *b = 1111; 20 | int weight = sum(6*x1, x2, x3, x4, 2*x5, x6); 21 | 22 | return weight; 23 | } 24 | 25 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/2008-06-05-Carry.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -cpu0-s32-calls=true < %s | FileCheck %s 2 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -cpu0-s32-calls=false < %s | FileCheck %s -check-prefix=cpu032II 3 | 4 | define i64 @add64(i64 %u, i64 %v) nounwind { 5 | entry: 6 | ; CHECK: addu 7 | ; CHECK: cmp 8 | ; CHECK: andi 9 | ; CHECK: addu 10 | ; cpu032II: sltu 11 | ; cpu032II: addu 12 | %tmp2 = add i64 %u, %v 13 | ret i64 %tmp2 14 | } 15 | 16 | define i64 @sub64(i64 %u, i64 %v) nounwind { 17 | entry: 18 | ; CHECK: cmp 19 | ; CHECK: andi 20 | ; CHECK: subu 21 | ; CHECK: subu 22 | ; cpu032II: sltu 23 | ; cpu032II: subu 24 | %tmp2 = sub i64 %u, %v 25 | ret i64 %tmp2 26 | } 27 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/2008-07-03-SRet.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -cpu0-s32-calls=true < %s | FileCheck %s 2 | 3 | %struct.sret0 = type { i32, i32, i32 } 4 | 5 | define void @test0(%struct.sret0* noalias sret(%struct.sret0) %agg.result, i32 %dummy) nounwind { 6 | entry: 7 | ; Support by section "Structure type support" of chapter "Function call' 8 | ; CHECK: ld ${{[0-9]+|t9}}, 0($sp) 9 | ; CHECK: ld ${{[0-9]+|t9}}, 4($sp) 10 | ; CHECK: st ${{[0-9]+|t9}}, 8($2) 11 | ; CHECK: st ${{[0-9]+|t9}}, 4($2) 12 | ; CHECK: st ${{[0-9]+|t9}}, 0($2) 13 | getelementptr %struct.sret0, %struct.sret0* %agg.result, i32 0, i32 0 ; :0 [#uses=1] 14 | store i32 %dummy, i32* %0, align 4 15 | getelementptr %struct.sret0, %struct.sret0* %agg.result, i32 0, i32 1 ; :1 [#uses=1] 16 | store i32 %dummy, i32* %1, align 4 17 | getelementptr %struct.sret0, %struct.sret0* %agg.result, i32 0, i32 2 ; :2 [#uses=1] 18 | store i32 %dummy, i32* %2, align 4 19 | ret void 20 | } 21 | 22 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/2008-07-15-InternalConstant.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -relocation-model=static < %s | FileCheck %s 2 | 3 | @.str = internal unnamed_addr constant [10 x i8] c"AAAAAAAAA\00" 4 | @i0 = internal unnamed_addr constant [5 x i32] [ i32 0, i32 1, i32 2, i32 3, i32 4 ] 5 | 6 | define i8* @foo() nounwind { 7 | entry: 8 | ; Support in chapter Global vaiarables 9 | ; CHECK: foo 10 | ; CHECK: %hi(.str) 11 | ; CHECK: %lo(.str) 12 | ret i8* getelementptr ([10 x i8], [10 x i8]* @.str, i32 0, i32 0) 13 | } 14 | 15 | define i32* @bar() nounwind { 16 | entry: 17 | ; CHECK: bar 18 | ; CHECK: %hi(i0) 19 | ; CHECK: %lo(i0) 20 | ret i32* getelementptr ([5 x i32], [5 x i32]* @i0, i32 0, i32 0) 21 | } 22 | 23 | ; CHECK: rodata.str1.4,"aMS",@progbits 24 | ; CHECK: rodata,"a",@progbits 25 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/2008-07-29-icmp.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic < %s | FileCheck %s 2 | 3 | ; CHECK: movn 4 | 5 | target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" 6 | target triple = "mipsallegrexel-unknown-psp-elf" 7 | 8 | define float @A(float %a, float %b, i32 %j) nounwind { 9 | entry: 10 | icmp sgt i32 %j, 1 ; :0 [#uses=1] 11 | %.0 = select i1 %0, float %a, float %b ; [#uses=1] 12 | ret float %.0 13 | } 14 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/2008-08-01-AsmInline.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 < %s | FileCheck %s 2 | 3 | %struct.DWstruct = type { i32, i32 } 4 | 5 | define i32 @A0(i32 %u, i32 %v) nounwind { 6 | entry: 7 | ; CHECK: multu 8 | ; CHECK: mflo 9 | ; CHECK: mfhi 10 | %asmtmp = tail call %struct.DWstruct asm "multu $2,$3", "={lo},={hi},r,r"( i32 %u, i32 %v ) nounwind 11 | %asmresult = extractvalue %struct.DWstruct %asmtmp, 0 12 | %asmresult1 = extractvalue %struct.DWstruct %asmtmp, 1 ; [#uses=1] 13 | %res = add i32 %asmresult, %asmresult1 14 | ret i32 %res 15 | } 16 | 17 | @gi2 = external global i32 18 | @gi1 = external global i32 19 | @gi0 = external global i32 20 | 21 | define void @foo0() nounwind { 22 | entry: 23 | ; CHECK: addu 24 | %0 = load i32, i32* @gi1, align 4 25 | %1 = load i32, i32* @gi0, align 4 26 | %2 = tail call i32 asm "addu $0, $1, $2", "=r,r,r"(i32 %0, i32 %1) nounwind 27 | store i32 %2, i32* @gi2, align 4 28 | ret void 29 | } 30 | 31 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/2008-08-06-Alloca.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic < %s | FileCheck %s 2 | 3 | define i32 @twoalloca(i32 %size) nounwind { 4 | entry: 5 | ; CHECK: subu ${{[0-9]+|t9}}, $sp 6 | ; CHECK: subu ${{[0-9]+|t9}}, $sp 7 | alloca i8, i32 %size ; :0 [#uses=1] 8 | alloca i8, i32 %size ; :1 [#uses=1] 9 | call i32 @foo( i8* %0 ) nounwind ; :2 [#uses=1] 10 | call i32 @foo( i8* %1 ) nounwind ; :3 [#uses=1] 11 | add i32 %3, %2 ; :4 [#uses=1] 12 | ret i32 %4 13 | } 14 | 15 | declare i32 @foo(i8*) 16 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/2008-08-08-bswap.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic < %s | FileCheck %s 2 | 3 | target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" 4 | target triple = "psp" 5 | 6 | define i32 @__bswapsi2(i32 %u) nounwind { 7 | entry: 8 | ; CHECK: shr ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, 8 9 | tail call i32 @llvm.bswap.i32( i32 %u ) ; :0 [#uses=1] 10 | ret i32 %0 11 | } 12 | 13 | declare i32 @llvm.bswap.i32(i32) nounwind readnone 14 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/2008-08-08-ctlz.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 < %s | FileCheck %s 2 | 3 | define i32 @A0(i32 %u) nounwind { 4 | entry: 5 | ; CHECK: clz 6 | call i32 @llvm.ctlz.i32( i32 %u, i1 true ) 7 | ret i32 %0 8 | } 9 | 10 | declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone 11 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/2010-11-09-CountLeading.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic < %s | FileCheck %s 2 | 3 | ; CHECK: clz $2, $4 4 | define i32 @t1(i32 %X) nounwind readnone { 5 | entry: 6 | %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true) 7 | ret i32 %tmp1 8 | } 9 | 10 | declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone 11 | 12 | ; CHECK: clz $2, $4 13 | define i32 @t2(i32 %X) nounwind readnone { 14 | entry: 15 | %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true) 16 | ret i32 %tmp1 17 | } 18 | 19 | ; CHECK: clo $2, $4 20 | define i32 @t3(i32 %X) nounwind readnone { 21 | entry: 22 | %neg = xor i32 %X, -1 23 | %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true) 24 | ret i32 %tmp1 25 | } 26 | 27 | ; CHECK: clo $2, $4 28 | define i32 @t4(i32 %X) nounwind readnone { 29 | entry: 30 | %neg = xor i32 %X, -1 31 | %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true) 32 | ret i32 %tmp1 33 | } 34 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/2010-11-09-Mul.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032II < %s | FileCheck %s 2 | 3 | ; CHECK: mul $2, $5, $4 4 | define i32 @mul1(i32 %a, i32 %b) nounwind readnone { 5 | entry: 6 | %mul = mul i32 %b, %a 7 | ret i32 %mul 8 | } 9 | 10 | ; CHECK: mul $2, $5, $4 11 | define i32 @mul2(i32 %a, i32 %b) nounwind readnone { 12 | entry: 13 | %mul = mul nsw i32 %b, %a 14 | ret i32 %mul 15 | } 16 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/addc.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc < %s -march=cpu0el -mcpu=cpu032I -cpu0-s32-calls=true | FileCheck %s 2 | ; RUN: llc < %s -march=cpu0 -mcpu=cpu032I -cpu0-s32-calls=true | FileCheck %s 3 | 4 | define void @f(i64 %l, i64* nocapture %p) nounwind { 5 | entry: 6 | ; CHECK: lui ${{[0-9]+|t9}}, 37035 7 | ; CHECK: ori ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, 52719 8 | ; CHECK: cmpu $sw, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 9 | ; CHECK: andi ${{[0-9]+|t9}}, $sw, 1 10 | ; CHECK: lui ${{[0-9]+|t9}}, 4660 11 | ; CHECK: ori ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, 22136 12 | ; CHECK: addu 13 | %add = add i64 %l, 1311768467294899695 14 | store i64 %add, i64* %p, align 4 15 | ret void 16 | } 17 | 18 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/and1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @x = global i32 65504, align 4 4 | @y = global i32 60929, align 4 5 | @.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1 6 | 7 | define i32 @main() nounwind { 8 | entry: 9 | %0 = load i32, i32* @x, align 4 10 | %1 = load i32, i32* @y, align 4 11 | %and = and i32 %0, %1 12 | ; 16: and ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 13 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and) 14 | ret i32 0 15 | } 16 | 17 | declare i32 @printf(i8*, ...) 18 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/asm-large-immediate.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -no-integrated-as < %s | FileCheck %s 2 | define void @test() { 3 | entry: 4 | ; CHECK: /* result: 68719476738 */ 5 | tail call void asm sideeffect "/* result: ${0:c} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 ) 6 | ; CHECK: /* result: -68719476738 */ 7 | tail call void asm sideeffect "/* result: ${0:n} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 ) 8 | ret void 9 | } 10 | 11 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/atomic-1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc < %s -march=cpu0 -mcpu=cpu032II | FileCheck %s 2 | 3 | define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind { 4 | ; CHECK-LABEL: exchange_and_add: 5 | ; CHECK: ll 6 | ; CHECK: sc 7 | %tmp = atomicrmw add i32* %mem, i32 %val monotonic 8 | ret i32 %tmp 9 | } 10 | 11 | define i32 @exchange_and_cmp(i32* %mem) nounwind { 12 | ; CHECK-LABEL: exchange_and_cmp: 13 | ; CHECK: ll 14 | ; CHECK: sc 15 | %tmppair = cmpxchg i32* %mem, i32 0, i32 1 monotonic monotonic 16 | %tmp = extractvalue { i32, i1 } %tmppair, 0 17 | ret i32 %tmp 18 | } 19 | 20 | define i32 @exchange(i32* %mem, i32 %val) nounwind { 21 | ; CHECK-LABEL: exchange: 22 | ; CHECK: ll 23 | ; CHECK: sc 24 | %tmp = atomicrmw xchg i32* %mem, i32 1 monotonic 25 | ret i32 %tmp 26 | } 27 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/atomics-fences.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc < %s -march=cpu0 -mcpu=cpu032II | FileCheck %s --check-prefix=CHECK 2 | 3 | ; Fences 4 | define void @fence_acquire() { 5 | ; CHECK-LABEL: fence_acquire 6 | ; CHECK: sync 7 | fence acquire 8 | ret void 9 | } 10 | define void @fence_release() { 11 | ; CHECK-LABEL: fence_release 12 | ; CHECK: sync 13 | fence release 14 | ret void 15 | } 16 | define void @fence_seq_cst() { 17 | ; CHECK-LABEL: fence_seq_cst 18 | ; CHECK: sync 19 | fence seq_cst 20 | ret void 21 | } 22 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/br-jmp.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -relocation-model=pic < %s | FileCheck %s 2 | 3 | define void @count(i32 %x, i32 %y, i32 %z) noreturn nounwind readnone { 4 | entry: 5 | br label %bosco 6 | 7 | bosco: ; preds = %bosco, %entry 8 | br label %bosco 9 | } 10 | 11 | ; CHECK: jmp 12 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/cprestore.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -relocation-model=pic < %s | FileCheck %s 2 | 3 | ; CHECK: .set nomacro 4 | ; CHECK: .cprestore 5 | ; CHECK: .set macro 6 | 7 | %struct.S = type { [1024 x i32] } 8 | 9 | ;declare void @foo1(%struct.S* byval align 8 %s(%struct.S)) 10 | 11 | define void @foo2() nounwind { 12 | entry: 13 | %s = alloca %struct.S, align 4 14 | call void @foo1(%struct.S* byval(%struct.S) %s) 15 | ; %s = alloca %struct.S, align 8 16 | ; call void @foo1(%struct.S* byval align 8 (%struct.S)%s) 17 | ret void 18 | } 19 | 20 | declare void @foo1(%struct.S* byval(%struct.S)) 21 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/cpu0_gcd.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic < %s | FileCheck %s 2 | ; ~/llvm/test/build/bin/llc -debug -print-after-all -march=cpu0 -mcpu=cpu032II -relocation-model=pic cpu0_gcd.ll -o - 3 | 4 | define i32 @llvm_cpu0_gcd_test(i32 %a, i32 %b) nounwind { 5 | entry: 6 | ; CHECK: gcd $2, $4, $5 7 | %res = tail call i32 @llvm.cpu0.gcd(i32 %a, i32 %b) 8 | ret i32 %res 9 | } 10 | 11 | declare i32 @llvm.cpu0.gcd(i32, i32) nounwind 12 | 13 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/cpu0_gcd_soft.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic < %s | FileCheck %s 2 | ; ~/llvm/test/build/bin/llc -debug -print-after-all -march=cpu0 -mcpu=cpu032II -relocation-model=pic cpu0_gcd_soft.ll -o - 3 | 4 | define i32 @llvm_cpu0_gcd_soft_test(i32 %a, i32 %b) nounwind { 5 | entry: 6 | ; CHECK: ld $t9, %call16(llvm.cpu0.gcd.soft)($gp) 7 | %res = tail call i32 @llvm.cpu0.gcd.soft(i32 %a, i32 %b) 8 | ret i32 %res 9 | } 10 | 11 | declare i32 @llvm.cpu0.gcd.soft(i32, i32) nounwind 12 | 13 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/div.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -relocation-model=pic < %s | FileCheck %s 2 | 3 | @iiii = global i32 100, align 4 4 | @jjjj = global i32 -4, align 4 5 | @kkkk = common global i32 0, align 4 6 | 7 | define void @test() nounwind { 8 | entry: 9 | %0 = load i32, i32* @iiii, align 4 10 | %1 = load i32, i32* @jjjj, align 4 11 | %div = sdiv i32 %0, %1 12 | ; CHECK: div ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 13 | ; CHECK: mflo ${{[0-9]+|t9}} 14 | store i32 %div, i32* @kkkk, align 4 15 | ret void 16 | } 17 | 18 | 19 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/div_rem.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @iiii = global i32 103, align 4 4 | @jjjj = global i32 -4, align 4 5 | @kkkk = common global i32 0, align 4 6 | @llll = common global i32 0, align 4 7 | 8 | define void @test() nounwind { 9 | entry: 10 | %0 = load i32, i32* @iiii, align 4 11 | %1 = load i32, i32* @jjjj, align 4 12 | %div = sdiv i32 %0, %1 13 | store i32 %div, i32* @kkkk, align 4 14 | %rem = srem i32 %0, %1 15 | ; 16: div ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 16 | ; 16: mflo ${{[0-9]+|t9}} 17 | ; 16: mfhi ${{[0-9]+|t9}} 18 | store i32 %rem, i32* @llll, align 4 19 | ret void 20 | } 21 | 22 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/divu.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @iiii = global i32 100, align 4 4 | @jjjj = global i32 4, align 4 5 | @kkkk = common global i32 0, align 4 6 | 7 | define void @test() nounwind { 8 | entry: 9 | %0 = load i32, i32* @iiii, align 4 10 | %1 = load i32, i32* @jjjj, align 4 11 | %div = udiv i32 %0, %1 12 | ; 16: divu ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 13 | ; 16: mflo ${{[0-9]+|t9}} 14 | store i32 %div, i32* @kkkk, align 4 15 | ret void 16 | } 17 | 18 | 19 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/divu_remu.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @iiii = global i32 103, align 4 4 | @jjjj = global i32 4, align 4 5 | @kkkk = common global i32 0, align 4 6 | @llll = common global i32 0, align 4 7 | 8 | 9 | define void @test() nounwind { 10 | entry: 11 | %0 = load i32, i32* @iiii, align 4 12 | %1 = load i32, i32* @jjjj, align 4 13 | %div = udiv i32 %0, %1 14 | store i32 %div, i32* @kkkk, align 4 15 | %rem = urem i32 %0, %1 16 | ; 16: divu ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 17 | ; 16: mflo ${{[0-9]+|t9}} 18 | ; 16: mfhi ${{[0-9]+|t9}} 19 | store i32 %rem, i32* @llll, align 4 20 | ret void 21 | } 22 | 23 | 24 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/double2int.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -relocation-model=pic < %s | FileCheck %s 2 | 3 | define i32 @f1(double %d) nounwind readnone { 4 | entry: 5 | ; CHECK: %call16(__fixdfsi) 6 | %conv = fptosi double %d to i32 7 | ret i32 %conv 8 | } 9 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/eh-dwarf-cfa.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032II < %s | FileCheck %s 2 | 3 | declare i8* @llvm.eh.dwarf.cfa(i32) nounwind 4 | declare i8* @llvm.frameaddress(i32) nounwind readnone 5 | 6 | define i8* @f1() nounwind { 7 | entry: 8 | %x = alloca [32 x i8], align 1 9 | %0 = call i8* @llvm.eh.dwarf.cfa(i32 0) 10 | ret i8* %0 11 | 12 | ; CHECK: addiu $sp, $sp, -40 13 | ; CHECK: addu $2, $zero, $fp 14 | } 15 | 16 | define i32 @f3() nounwind { 17 | entry: 18 | %x = alloca [32 x i8], align 1 19 | %0 = call i8* @llvm.eh.dwarf.cfa(i32 0) 20 | %1 = ptrtoint i8* %0 to i32 21 | %2 = call i8* @llvm.frameaddress(i32 0) 22 | %3 = ptrtoint i8* %2 to i32 23 | %add = add i32 %1, %3 24 | ret i32 %add 25 | 26 | ; CHECK: addiu $sp, $sp, -40 27 | 28 | ; check return value ($fp + stack size + $fp) 29 | ; CHECK: move $fp, $sp 30 | ; CHECK: addu $2, $fp, $fp 31 | } 32 | 33 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/ex2.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -relocation-model=pic < %s | FileCheck %s -check-prefix=16 2 | 3 | @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 4 | @_ZTIPKc = external constant i8* 5 | 6 | define i32 @main() { 7 | ; 16: main: 8 | ; 16: .cfi_startproc 9 | ; 16: st $lr, 10 | ; 16: .cfi_offset 14, -4 11 | ; 16: .cfi_offset 12 | ; 16: .cprestore 13 | entry: 14 | %retval = alloca i32, align 4 15 | store i32 0, i32* %retval 16 | %exception = call i8* @__cxa_allocate_exception(i32 4) nounwind 17 | %0 = bitcast i8* %exception to i8** 18 | store i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), i8** %0 19 | call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIPKc to i8*), i8* null) noreturn 20 | unreachable 21 | 22 | return: ; No predecessors! 23 | %1 = load i32, i32* %retval 24 | ret i32 %1 25 | } 26 | 27 | declare i8* @__cxa_allocate_exception(i32) 28 | 29 | declare void @__cxa_throw(i8*, i8*, i8*) 30 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/fneg.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc < %s -march=cpu0el | FileCheck %s 2 | 3 | define float @foo0(i32 %a, float %d) nounwind readnone { 4 | entry: 5 | ; CHECK-NOT: neg.s 6 | %sub = fsub float -0.000000e+00, %d 7 | ret float %sub 8 | } 9 | 10 | define double @foo1(i32 %a, double %d) nounwind readnone { 11 | entry: 12 | ; CHECK: foo1 13 | ; CHECK-NOT: neg.d 14 | ; CHECK: ret 15 | %sub = fsub double -0.000000e+00, %d 16 | ret double %sub 17 | } 18 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/frame-address.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el < %s | FileCheck %s 2 | 3 | declare i8* @llvm.frameaddress(i32) nounwind readnone 4 | 5 | define i8* @f() nounwind { 6 | entry: 7 | %0 = call i8* @llvm.frameaddress(i32 0) 8 | ret i8* %0 9 | 10 | ; CHECK: addu $2, $zero, $fp 11 | } 12 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/global-pointer-reg.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc < %s -march=cpu0el -relocation-model=pic | FileCheck %s 2 | 3 | @g0 = external global i32 4 | @g1 = external global i32 5 | @g2 = external global i32 6 | 7 | define void @foo1() nounwind { 8 | entry: 9 | ; CHECK: .cpload 10 | ; CHECK: .cprestore 11 | 12 | tail call void @foo2(i32* @g0) nounwind 13 | tail call void @foo2(i32* @g1) nounwind 14 | tail call void @foo2(i32* @g2) nounwind 15 | ret void 16 | } 17 | 18 | declare void @foo2(i32*) 19 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/i32k.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -relocation-model=pic < %s | FileCheck %s 2 | 3 | @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 4 | 5 | define i32 @main() nounwind { 6 | entry: 7 | %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 1075344593) nounwind 8 | ; CHECK: lui ${{[0-9]+|t9}}, 16408 9 | ; CHECK: ori ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, 29905 10 | %call1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 -1075344593) nounwind 11 | ; CHECK: lui ${{[0-9]+|t9}}, 49127 12 | ; CHECK: ori ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, 35631 13 | ret i32 0 14 | } 15 | 16 | declare i32 @printf(i8* nocapture, ...) nounwind 17 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/i64arg.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -relocation-model=pic < %s | FileCheck %s 2 | 3 | define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind { 4 | entry: 5 | ; CHECK: lui $[[R0:[0-9]+|t9]], 4660 6 | ; CHECK: ori ${{[0-9]+|t9}}, $[[R0]], 22136 7 | ; CHECK: lui $[[R0:[0-9]+|t9]], 3855 8 | ; CHECK: ori ${{[0-9]+|t9}}, $[[R0]], 3855 9 | ; CHECK: ld $t9, %call16(ff1)($gp) 10 | ; CHECK: jalr $t9 11 | tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind 12 | ; CHECK: ld $t9, %call16(ff2)($gp) 13 | ; CHECK: jalr $t9 14 | tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind 15 | %sub = add nsw i32 %i, -1 16 | ; CHECK: ld $t9, %call16(ff3)($gp) 17 | ; CHECK: jalr $t9 18 | tail call void @ff3(i32 %i, i64 %ll, i32 %sub, i64 %ll1) nounwind 19 | ret void 20 | } 21 | 22 | declare void @ff1(i32, i64) 23 | 24 | declare void @ff2(i64, double) 25 | 26 | declare void @ff3(i32, i64, i32, i64) 27 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/imm.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 < %s | FileCheck %s 2 | 3 | define i32 @foo0() nounwind readnone { 4 | entry: 5 | ; CHECK: foo0 6 | ; CHECK: lui $[[R0:[0-9]+|t9]], 4660 7 | ; CHECK: ori ${{[0-9]+|t9}}, $[[R0]], 22136 8 | ret i32 305419896 9 | } 10 | 11 | define i32 @foo1() nounwind readnone { 12 | entry: 13 | ; CHECK: foo1 14 | ; CHECK: lui ${{[0-9]+|t9}}, 4660 15 | ; CHECK-NOT: ori 16 | ret i32 305397760 17 | } 18 | 19 | define i32 @foo2() nounwind readnone { 20 | entry: 21 | ; CHECK: foo2 22 | ; CHECK: addiu ${{[0-9]+|t9}}, $zero, 4660 23 | ret i32 4660 24 | } 25 | 26 | define i32 @foo17() nounwind readnone { 27 | entry: 28 | ; CHECK: foo17 29 | ; CHECK: addiu ${{[0-9]+|t9}}, $zero, -32204 30 | ret i32 -32204 31 | } 32 | 33 | define i32 @foo18() nounwind readnone { 34 | entry: 35 | ; CHECK: foo18 36 | ; CHECK: ori ${{[0-9]+|t9}}, $zero, 33332 37 | ret i32 33332 38 | } 39 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/indirectcall.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc < %s -march=cpu0el -relocation-model=static | FileCheck %s 2 | 3 | define void @foo0(void (i32)* nocapture %f1) nounwind { 4 | entry: 5 | ; CHECK: jalr $t9 6 | tail call void %f1(i32 13) nounwind 7 | ret void 8 | } 9 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/init-array.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el < %s | FileCheck %s 2 | 3 | target triple = "mipsel-unknown-linux" 4 | 5 | @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @test, i8* null }] 6 | ; CHECK: .section 7 | ; CHECK: .init_array 8 | ; CHECK-NOT: .ctors 9 | ; CHECK: .4byte test 10 | 11 | define internal void @test() section ".text.startup" { 12 | entry: 13 | ret void 14 | } 15 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/lb1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @c = global i8 -1, align 1 4 | @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 5 | 6 | define i32 @main() nounwind { 7 | entry: 8 | %i = alloca i32, align 4 9 | %0 = load i8, i8* @c, align 1 10 | %conv = sext i8 %0 to i32 11 | ; 16: lb ${{[0-9]+|t9}}, 0(${{[0-9]+|t9}}) 12 | store i32 %conv, i32* %i, align 4 13 | %1 = load i32, i32* %i, align 4 14 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %1) 15 | ret i32 0 16 | } 17 | 18 | declare i32 @printf(i8*, ...) 19 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/lbu1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @c = global i8 97, align 1 4 | @.str = private unnamed_addr constant [5 x i8] c"%c \0A\00", align 1 5 | 6 | define i32 @main() nounwind { 7 | entry: 8 | %i = alloca i32, align 4 9 | %0 = load i8, i8* @c, align 1 10 | %conv = zext i8 %0 to i32 11 | ; 16: lbu ${{[0-9]+|t9}}, 0(${{[0-9]+|t9}}) 12 | store i32 %conv, i32* %i, align 4 13 | %1 = load i8, i8* @c, align 1 14 | %conv1 = zext i8 %1 to i32 15 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %conv1) 16 | ret i32 0 17 | } 18 | 19 | declare i32 @printf(i8*, ...) 20 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/lh1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @s = global i16 -1, align 2 4 | @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 5 | 6 | define i32 @main() nounwind { 7 | entry: 8 | %i = alloca i32, align 4 9 | %0 = load i16, i16* @s, align 2 10 | %conv = sext i16 %0 to i32 11 | ; 16: lh ${{[0-9]+|t9}}, 0(${{[0-9]+|t9}}) 12 | store i32 %conv, i32* %i, align 4 13 | %1 = load i32, i32* %i, align 4 14 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %1) 15 | ret i32 0 16 | } 17 | 18 | declare i32 @printf(i8*, ...) 19 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/lhu1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | 4 | @s = global i16 255, align 2 5 | @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 6 | 7 | define i32 @main() nounwind { 8 | entry: 9 | %i = alloca i32, align 4 10 | %0 = load i16, i16* @s, align 2 11 | %conv = zext i16 %0 to i32 12 | ; 16: lhu ${{[0-9]+|t9}}, 0(${{[0-9]+|t9}}) 13 | store i32 %conv, i32* %i, align 4 14 | %1 = load i32, i32* %i, align 4 15 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %1) 16 | ret i32 0 17 | } 18 | 19 | declare i32 @printf(i8*, ...) 20 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/lit.local.cfg: -------------------------------------------------------------------------------- 1 | config.suffixes = ['.ll', '.c', '.cpp'] 2 | 3 | targets = set(config.root.targets_to_build.split()) 4 | if not 'Cpu0' in targets: 5 | config.unsupported = True 6 | 7 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/machineverifier.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc < %s -march=cpu0el 2 | ; Make sure machine verifier understands the last instruction of a basic block 3 | ; is not the terminator instruction after delay slot filler pass is run. 4 | 5 | @g = external global i32 6 | 7 | define void @foo() nounwind { 8 | entry: 9 | %0 = load i32, i32* @g, align 4 10 | %tobool = icmp eq i32 %0, 0 11 | br i1 %tobool, label %if.end, label %if.then 12 | 13 | if.then: ; preds = %entry 14 | %add = add nsw i32 %0, 10 15 | store i32 %add, i32* @g, align 4 16 | br label %if.end 17 | 18 | if.end: ; preds = %entry, %if.then 19 | ret void 20 | } 21 | 22 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/mipslopat.ll: -------------------------------------------------------------------------------- 1 | ; This test does not check the machine code output. 2 | ; RUN: llc -march=cpu0 < %s 3 | 4 | @stat_vol_ptr_int = internal global i32* null, align 4 5 | @stat_ptr_vol_int = internal global i32* null, align 4 6 | 7 | define void @simple_vol_file() nounwind { 8 | entry: 9 | %tmp = load volatile i32*, i32** @stat_vol_ptr_int, align 4 10 | %0 = bitcast i32* %tmp to i8* 11 | call void @llvm.prefetch(i8* %0, i32 0, i32 0, i32 1) 12 | %tmp1 = load i32*, i32** @stat_ptr_vol_int, align 4 13 | %1 = bitcast i32* %tmp1 to i8* 14 | call void @llvm.prefetch(i8* %1, i32 0, i32 0, i32 1) 15 | ret void 16 | } 17 | 18 | declare void @llvm.prefetch(i8* nocapture, i32, i32, i32) nounwind 19 | 20 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/mul.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032II -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @iiii = global i32 5, align 4 4 | @jjjj = global i32 -6, align 4 5 | @kkkk = common global i32 0, align 4 6 | 7 | define void @test() nounwind { 8 | entry: 9 | %0 = load i32, i32* @iiii, align 4 10 | %1 = load i32, i32* @jjjj, align 4 11 | %mul = mul nsw i32 %1, %0 12 | ; 16: mul ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 13 | 14 | store i32 %mul, i32* @kkkk, align 4 15 | ret void 16 | } 17 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/mulll.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032II -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @iiii = global i64 5, align 8 4 | @jjjj = global i64 -6, align 8 5 | @kkkk = common global i64 0, align 8 6 | 7 | define void @test() nounwind { 8 | entry: 9 | %0 = load i64, i64* @iiii, align 8 10 | %1 = load i64, i64* @jjjj, align 8 11 | %mul = mul nsw i64 %1, %0 12 | store i64 %mul, i64* @kkkk, align 8 13 | ; 16: multu ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 14 | ; 16: mflo ${{[0-9]+|t9}} 15 | ; 16: mfhi ${{[0-9]+|t9}} 16 | ; 16: mul ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 17 | ; 16: mul ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 18 | 19 | ret void 20 | } 21 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/mulull.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032II -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @iiii = global i64 5, align 8 4 | @jjjj = global i64 6, align 8 5 | @kkkk = common global i64 0, align 8 6 | @.str = private unnamed_addr constant [20 x i8] c"%lld * %lld = %lld\0A\00", align 1 7 | 8 | define void @test() nounwind { 9 | entry: 10 | %0 = load i64, i64* @iiii, align 8 11 | %1 = load i64, i64* @jjjj, align 8 12 | %mul = mul nsw i64 %1, %0 13 | store i64 %mul, i64* @kkkk, align 8 14 | ; 16: multu ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 15 | ; 16: mflo ${{[0-9]+|t9}} 16 | ; 16: mfhi ${{[0-9]+|t9}} 17 | ; 16: mul ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 18 | ; 16: mul ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 19 | ret void 20 | } 21 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/not1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032II -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @x = global i32 65504, align 4 4 | @y = global i32 60929, align 4 5 | @.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1 6 | 7 | define i32 @main() nounwind { 8 | entry: 9 | %0 = load i32, i32* @x, align 4 10 | %neg = xor i32 %0, -1 11 | ; 16: nor ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, $zero 12 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %neg) 13 | ret i32 0 14 | } 15 | 16 | declare i32 @printf(i8*, ...) 17 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/null.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032II < %s | FileCheck %s -check-prefix=16 2 | 3 | 4 | define i32 @main() nounwind { 5 | entry: 6 | ret i32 0 7 | 8 | ; 16: ret $lr 9 | 10 | } 11 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/private.ll: -------------------------------------------------------------------------------- 1 | ; Test to make sure that the 'private' is used correctly. 2 | ; 3 | ; RUN: llc -march=cpu0el -mcpu=cpu032II -relocation-model=pic < %s | FileCheck %s 4 | 5 | define private void @foo() { 6 | ; CHECK: foo: 7 | ret void 8 | } 9 | 10 | @baz = private global i32 4 11 | 12 | define i32 @bar() { 13 | ; CHECK: bar: 14 | ; CHECK: call16($foo) 15 | ; CHECK: ld $[[R0:[0-9]+|t9]], %got($baz)($gp) 16 | ; CHECK: ori ${{[0-9]+|t9}}, $[[R0]], %lo($baz) 17 | call void @foo() 18 | %1 = load i32, i32* @baz, align 4 19 | ret i32 %1 20 | } 21 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/rem.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @iiii = global i32 103, align 4 4 | @jjjj = global i32 -4, align 4 5 | @kkkk = common global i32 0, align 4 6 | 7 | 8 | define void @test() nounwind { 9 | entry: 10 | %0 = load i32, i32* @iiii, align 4 11 | %1 = load i32, i32* @jjjj, align 4 12 | %rem = srem i32 %0, %1 13 | ; 16: div ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 14 | ; 16: mfhi ${{[0-9]+|t9}} 15 | store i32 %rem, i32* @kkkk, align 4 16 | ret void 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/remu.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @iiii = global i32 103, align 4 4 | @jjjj = global i32 4, align 4 5 | @kkkk = common global i32 0, align 4 6 | @.str = private unnamed_addr constant [15 x i8] c"%u = %u %% %u\0A\00", align 1 7 | 8 | define void @test() nounwind { 9 | entry: 10 | %0 = load i32, i32* @iiii, align 4 11 | %1 = load i32, i32* @jjjj, align 4 12 | %rem = urem i32 %0, %1 13 | ; 16: divu ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 14 | ; 16: mfhi ${{[0-9]+|t9}} 15 | store i32 %rem, i32* @kkkk, align 4 16 | ret void 17 | } 18 | 19 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/return-vector-float4.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic < %s | FileCheck %s 2 | 3 | define <4 x float> @retvec4() nounwind readnone { 4 | entry: 5 | ; CHECK: lui $2, 16256 6 | ; CHECK: lui $3, 16384 7 | ; CHECK: lui $4, 16448 8 | ; CHECK: $5, 16512 9 | 10 | ret <4 x float> 11 | } 12 | 13 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/return_address.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic < %s | FileCheck %s 2 | 3 | define i8* @f1() nounwind { 4 | entry: 5 | %0 = call i8* @llvm.returnaddress(i32 0) 6 | ret i8* %0 7 | 8 | ; CHECK: addu $2, $zero, $lr 9 | } 10 | 11 | define i8* @f2() nounwind { 12 | entry: 13 | call void @g() 14 | %0 = call i8* @llvm.returnaddress(i32 0) 15 | ret i8* %0 16 | 17 | ; CHECK: jalr 18 | ; CHECK: addu $2, $zero, $lr 19 | } 20 | 21 | declare i8* @llvm.returnaddress(i32) nounwind readnone 22 | declare void @g() 23 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/rotate.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -cpu0-s32-calls=false < %s | FileCheck %s 2 | 3 | ; CHECK: rolv $2, $4, $5 4 | define i32 @rot0(i32 %a, i32 %b) nounwind readnone { 5 | entry: 6 | %shl = shl i32 %a, %b 7 | %sub = sub i32 32, %b 8 | %shr = lshr i32 %a, %sub 9 | %or = or i32 %shr, %shl 10 | ret i32 %or 11 | } 12 | 13 | ; CHECK: rol $2, $4, 30 14 | define i32 @rot1(i32 %a) nounwind readnone { 15 | entry: 16 | %shl = shl i32 %a, 30 17 | %shr = lshr i32 %a, 2 18 | %or = or i32 %shl, %shr 19 | ret i32 %or 20 | } 21 | 22 | ; CHECK: rorv $2, $4, $5 23 | define i32 @rot2(i32 %a, i32 %b) nounwind readnone { 24 | entry: 25 | %shr = lshr i32 %a, %b 26 | %sub = sub i32 32, %b 27 | %shl = shl i32 %a, %sub 28 | %or = or i32 %shl, %shr 29 | ret i32 %or 30 | } 31 | 32 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/sb1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032II -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @i = global i32 97, align 4 4 | @c = common global i8 0, align 1 5 | @.str = private unnamed_addr constant [8 x i8] c"%i %c \0A\00", align 1 6 | 7 | define i32 @main() nounwind { 8 | entry: 9 | %0 = load i32, i32* @i, align 4 10 | %conv = trunc i32 %0 to i8 11 | store i8 %conv, i8* @c, align 1 12 | ; 16: sb ${{[0-9]+|t9}}, 0(${{[0-9]+|t9}}) 13 | %1 = load i32, i32* @i, align 4 14 | %2 = load i8, i8* @c, align 1 15 | %conv1 = sext i8 %2 to i32 16 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), i32 %1, i32 %conv1) 17 | ret i32 0 18 | } 19 | 20 | declare i32 @printf(i8*, ...) 21 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/seteqz.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032I 2 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032II 3 | 4 | @i = global i32 0, align 4 5 | @r1 = common global i32 0, align 4 6 | 7 | define void @test() nounwind { 8 | entry: 9 | %0 = load i32, i32* @i, align 4 10 | %cmp = icmp eq i32 %0, 0 11 | %conv = zext i1 %cmp to i32 12 | store i32 %conv, i32* @r1, align 4 13 | ; cpu032I: cmp $sw, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 14 | ; cpu032I: andi $[[T1:[0-9]+|t9]], $sw, 2 15 | ; cpu032I: shr ${{[0-9]+|t9}}, $[[T1]], 1 16 | ; cpu032II: xor $[[T0:[0-9]+|t9]], ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 17 | ; cpu032II: sltiu ${{[0-9]+|t9}}, $[[T0]], 1 18 | 19 | ret void 20 | } 21 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/setgek.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032I 2 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032II 3 | 4 | @k = global i32 10, align 4 5 | @r1 = common global i32 0, align 4 6 | @r2 = common global i32 0, align 4 7 | @r3 = common global i32 0, align 4 8 | 9 | define void @test() nounwind { 10 | entry: 11 | %0 = load i32, i32* @k, align 4 12 | %cmp = icmp sgt i32 %0, -32769 13 | %conv = zext i1 %cmp to i32 14 | store i32 %conv, i32* @r1, align 4 15 | ; cpu032I: cmp $sw, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 16 | ; cpu032I: andi $[[T1:[0-9]+|t9]], $sw, 1 17 | ; cpu032II: slt ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 18 | ret void 19 | } 20 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/setlt.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032I 2 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032II 3 | 4 | @j = global i32 -5, align 4 5 | @k = global i32 10, align 4 6 | @l = global i32 20, align 4 7 | @m = global i32 10, align 4 8 | @r1 = common global i32 0, align 4 9 | @r2 = common global i32 0, align 4 10 | @r3 = common global i32 0, align 4 11 | 12 | define void @test() nounwind { 13 | entry: 14 | %0 = load i32, i32* @j, align 4 15 | %1 = load i32, i32* @k, align 4 16 | %cmp = icmp slt i32 %0, %1 17 | %conv = zext i1 %cmp to i32 18 | store i32 %conv, i32* @r1, align 4 19 | ; cpu032I: cmp $sw, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 20 | ; cpu032I: andi $[[T1:[0-9]+|t9]], $sw, 1 21 | ; cpu032II: slt ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 22 | 23 | ret void 24 | } 25 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/setltk.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032I 2 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032II 3 | 4 | @j = global i32 -5, align 4 5 | @k = global i32 10, align 4 6 | @l = global i32 20, align 4 7 | @m = global i32 10, align 4 8 | @r1 = common global i32 0, align 4 9 | @r2 = common global i32 0, align 4 10 | @r3 = common global i32 0, align 4 11 | 12 | define void @test() nounwind { 13 | entry: 14 | %0 = load i32, i32* @j, align 4 15 | %cmp = icmp slt i32 %0, 10 16 | %conv = zext i1 %cmp to i32 17 | store i32 %conv, i32* @r1, align 4 18 | ; cpu032I: cmp $sw, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 19 | ; cpu032I: andi $[[T1:[0-9]+|t9]], $sw, 1 20 | ; cpu032II: slti ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, 1 21 | 22 | ret void 23 | } 24 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/setne.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032I 2 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032II 3 | 4 | @i = global i32 1, align 4 5 | @j = global i32 10, align 4 6 | @k = global i32 1, align 4 7 | @r1 = common global i32 0, align 4 8 | @r2 = common global i32 0, align 4 9 | 10 | define void @test() nounwind { 11 | entry: 12 | %0 = load i32, i32* @i, align 4 13 | %1 = load i32, i32* @k, align 4 14 | %cmp = icmp ne i32 %0, %1 15 | %conv = zext i1 %cmp to i32 16 | store i32 %conv, i32* @r1, align 4 17 | ; cpu032I: cmp $sw, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 18 | ; cpu032I: andi $[[T1:[0-9]+|t9]], $sw, 2 19 | ; cpu032I: shr $[[T2:[0-9]+|t9]], $[[T1]], 1 20 | ; cpu032I: xori ${{[0-9]+|t9}}, $[[T2]], 1 21 | ; cpu032II: xor $[[T0:[0-9]+|t9]], ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 22 | ; cpu032II: sltu ${{[0-9]+|t9}}, $zero, $[[T0]] 23 | ret void 24 | } 25 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/setugt.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032I 2 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032II 3 | 4 | @j = global i32 5, align 4 5 | @k = global i32 10, align 4 6 | @l = global i32 20, align 4 7 | @m = global i32 10, align 4 8 | @r1 = common global i32 0, align 4 9 | @r2 = common global i32 0, align 4 10 | @r3 = common global i32 0, align 4 11 | 12 | define void @test() nounwind { 13 | entry: 14 | %0 = load i32, i32* @k, align 4 15 | %1 = load i32, i32* @j, align 4 16 | %cmp = icmp ugt i32 %0, %1 17 | %conv = zext i1 %cmp to i32 18 | store i32 %conv, i32* @r1, align 4 19 | ; cpu032I: cmpu $sw, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 20 | ; cpu032I: andi $[[T1:[0-9]+|t9]], $sw, 1 21 | ; cpu032II: sltu ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 22 | ret void 23 | } 24 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/setult.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032I 2 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032II 3 | 4 | @j = global i32 5, align 4 5 | @k = global i32 10, align 4 6 | @l = global i32 20, align 4 7 | @m = global i32 10, align 4 8 | @r1 = common global i32 0, align 4 9 | @r2 = common global i32 0, align 4 10 | @r3 = common global i32 0, align 4 11 | 12 | define void @test() nounwind { 13 | entry: 14 | %0 = load i32, i32* @j, align 4 15 | %1 = load i32, i32* @k, align 4 16 | %cmp = icmp ult i32 %0, %1 17 | %conv = zext i1 %cmp to i32 18 | store i32 %conv, i32* @r1, align 4 19 | ; cpu032I: cmpu $sw, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 20 | ; cpu032I: andi $[[T1:[0-9]+|t9]], $sw, 1 21 | ; cpu032II: sltu ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 22 | ret void 23 | } 24 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/setultk.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032I 2 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic -O3 %s -o - | FileCheck %s -check-prefix=cpu032II 3 | 4 | @j = global i32 5, align 4 5 | @k = global i32 10, align 4 6 | @l = global i32 20, align 4 7 | @m = global i32 10, align 4 8 | @r1 = common global i32 0, align 4 9 | @r2 = common global i32 0, align 4 10 | @r3 = common global i32 0, align 4 11 | 12 | define void @test() nounwind { 13 | entry: 14 | %0 = load i32, i32* @j, align 4 15 | %cmp = icmp ult i32 %0, 10 16 | %conv = zext i1 %cmp to i32 17 | store i32 %conv, i32* @r1, align 4 18 | ; cpu032I: cmpu $sw, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 19 | ; cpu032I: andi $[[T1:[0-9]+|t9]], $sw, 1 20 | ; cpu032II: sltiu ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, 10 21 | ret void 22 | } 23 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/sext_inreg.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -relocation-model=pic < %s | FileCheck %s 2 | 3 | define i32 @test_sext_inreg_from_32(i32 %in) { 4 | ; CHECK: test_sext_inreg_from_32: 5 | 6 | %small = trunc i32 %in to i1 7 | %ext = sext i1 %small to i32 8 | ; CHECK: andi $[[T1:[0-9]+|t9]], $4, 1 9 | ; CHECK: addiu $[[T2:[0-9]+|t9]], $zero, 0 10 | ; CHECK: subu ${{[0-9]+|t9}}, $[[T2]], $[[T1]] 11 | ret i32 %ext 12 | } 13 | 14 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/shift-parts.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -relocation-model=pic < %s | FileCheck %s 2 | 3 | define i64 @shl0(i64 %a, i32 %b) nounwind readnone { 4 | entry: 5 | ; CHECK: shl0 6 | ; CHECK: ld $t9, %call16 7 | %sh_prom = zext i32 %b to i64 8 | %shl = shl i64 %a, %sh_prom 9 | ret i64 %shl 10 | } 11 | 12 | define i64 @shr1(i64 %a, i32 %b) nounwind readnone { 13 | entry: 14 | ; CHECK: shr1 15 | ; CHECK: ld $t9, %call16 16 | %sh_prom = zext i32 %b to i64 17 | %shr = lshr i64 %a, %sh_prom 18 | ret i64 %shr 19 | } 20 | 21 | define i64 @sra2(i64 %a, i32 %b) nounwind readnone { 22 | entry: 23 | ; CHECK: sra2 24 | ; CHECK: ld $t9, %call16 25 | %sh_prom = zext i32 %b to i64 26 | %shr = ashr i64 %a, %sh_prom 27 | ret i64 %shr 28 | } 29 | 30 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/shl1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @i = global i32 10, align 4 4 | @j = global i32 0, align 4 5 | @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 6 | 7 | define i32 @main() nounwind { 8 | entry: 9 | ; 16: shl ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, {{[0-9]+|t9}} 10 | %0 = load i32, i32* @i, align 4 11 | %shl = shl i32 %0, 4 12 | store i32 %shl, i32* @j, align 4 13 | %1 = load i32, i32* @j, align 4 14 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %1) 15 | ret i32 0 16 | } 17 | 18 | declare i32 @printf(i8*, ...) 19 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/shl2.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @i = global i32 10, align 4 4 | @j = global i32 4, align 4 5 | @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 6 | 7 | define i32 @main() nounwind { 8 | entry: 9 | %0 = load i32, i32* @i, align 4 10 | %1 = load i32, i32* @j, align 4 11 | %shl = shl i32 %0, %1 12 | ; 16: shlv ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 13 | store i32 %shl, i32* @i, align 4 14 | %2 = load i32, i32* @j, align 4 15 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %2) 16 | ret i32 0 17 | } 18 | 19 | declare i32 @printf(i8*, ...) 20 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/shr1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @i = global i32 10654, align 4 4 | @j = global i32 0, align 4 5 | @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 6 | 7 | define i32 @main() nounwind { 8 | entry: 9 | %0 = load i32, i32* @i, align 4 10 | %shr = lshr i32 %0, 4 11 | ; 16: shr ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, {{[0-9]+|t9}} 12 | store i32 %shr, i32* @j, align 4 13 | %1 = load i32, i32* @j, align 4 14 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %1) 15 | ret i32 0 16 | } 17 | 18 | declare i32 @printf(i8*, ...) 19 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/shr2.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @i = global i32 10654, align 4 4 | @j = global i32 0, align 4 5 | @k = global i32 4, align 4 6 | @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 7 | 8 | define i32 @main() nounwind { 9 | entry: 10 | %0 = load i32, i32* @i, align 4 11 | %1 = load i32, i32* @k, align 4 12 | %shr = lshr i32 %0, %1 13 | ; 16: shrv ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 14 | store i32 %shr, i32* @j, align 4 15 | %2 = load i32, i32* @j, align 4 16 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %2) 17 | ret i32 0 18 | } 19 | 20 | declare i32 @printf(i8*, ...) 21 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/sitofp-selectcc-opt.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el < %s | FileCheck %s 2 | 3 | @foo12.d4 = internal unnamed_addr global double 0.000000e+00, align 8 4 | 5 | define double @foo12(i32 %a, i32, i64 %b) nounwind { 6 | entry: 7 | ; check that this transformation doesn't happen: 8 | ; (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 9 | ; 10 | ; CHECK-NOT: # double -1.000000e+00 11 | 12 | %tobool1 = icmp ne i32 %a, 0 13 | %not.tobool = icmp ne i64 %b, 0 14 | %tobool1. = or i1 %tobool1, %not.tobool 15 | %lor.ext = zext i1 %tobool1. to i32 16 | %conv = sitofp i32 %lor.ext to double 17 | %1 = load double, double* @foo12.d4, align 8 18 | %add = fadd double %conv, %1 19 | store double %add, double* @foo12.d4, align 8 20 | ret double %add 21 | } 22 | 23 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/small-section-reserve-gp.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -relocation-model=static -cpu0-use-small-section=true \ 2 | ; RUN: < %s | FileCheck %s -check-prefix=STATIC 3 | 4 | @i = internal unnamed_addr global i32 0, align 4 5 | 6 | define i32 @geti() nounwind readonly { 7 | entry: 8 | ; STATIC: ori $[[R0:[0-9]+|t9]], $gp, %gp_rel(i) 9 | ; STATIC: ld ${{[0-9]+|t9}}, 0($[[R0]]) 10 | %0 = load i32, i32* @i, align 4 11 | ret i32 %0 12 | } 13 | 14 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/sra1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @i = global i32 -354, align 4 4 | @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 5 | 6 | define i32 @main() nounwind { 7 | entry: 8 | %0 = load i32, i32* @i, align 4 9 | %shr = ashr i32 %0, 3 10 | ; 16: sra ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, {{[0-9]+|t9}} 11 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %shr) 12 | ret i32 0 13 | } 14 | 15 | declare i32 @printf(i8*, ...) 16 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/sra2.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @i = global i32 -354, align 4 4 | @j = global i32 3, align 4 5 | @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 6 | 7 | define i32 @main() nounwind { 8 | entry: 9 | %0 = load i32, i32* @i, align 4 10 | %1 = load i32, i32* @j, align 4 11 | %shr = ashr i32 %0, %1 12 | ; 16: srav ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 13 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 %shr) 14 | ret i32 0 15 | } 16 | 17 | declare i32 @printf(i8*, ...) 18 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/stacksave-restore.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -relocation-model=static < %s | FileCheck %s 2 | 3 | declare i8* @llvm.stacksave() 4 | 5 | declare void @llvm.stackrestore(i8*) 6 | 7 | define i32* @test(i32 %N) { 8 | ; CHECK: move $fp, $sp 9 | %tmp = call i8* @llvm.stacksave( ) ; [#uses=1] 10 | %P = alloca i32, i32 %N ; [#uses=1] 11 | call void @llvm.stackrestore( i8* %tmp ) 12 | %Q = alloca i32, i32 %N ; [#uses=0] 13 | ret i32* %P 14 | } 15 | 16 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/stacksize.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -relocation-model=static < %s | FileCheck %s 2 | 3 | define i32 @foo(i32 %a) nounwind readnone { 4 | entry: 5 | ; check that stack size is zero. 6 | ; CHECK-NOT: addiu $sp, $sp 7 | %add = add nsw i32 %a, 1 8 | ret i32 %add 9 | } 10 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/sub1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @i = global i32 10, align 4 4 | @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 5 | 6 | define i32 @main() nounwind { 7 | entry: 8 | %0 = load i32, i32* @i, align 4 9 | %sub = sub nsw i32 %0, 5 10 | ; 16: addiu ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, -5 11 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %sub) 12 | ret i32 0 13 | } 14 | 15 | declare i32 @printf(i8*, ...) 16 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/sub2.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @i = global i32 10, align 4 4 | @j = global i32 20, align 4 5 | @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 6 | 7 | define i32 @main() nounwind { 8 | entry: 9 | %0 = load i32, i32* @j, align 4 10 | %1 = load i32, i32* @i, align 4 11 | %sub = sub nsw i32 %0, %1 12 | ; 16: subu ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 13 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %sub) 14 | ret i32 0 15 | } 16 | 17 | declare i32 @printf(i8*, ...) 18 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/tls-alias.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -relocation-model=pic < %s | FileCheck %s 2 | 3 | @foo = thread_local global i32 42 4 | @bar = hidden thread_local alias i32, i32* @foo 5 | 6 | define i32* @zed() { 7 | ; CHECK-DAG: __tls_get_addr 8 | ; CHECK-DAG: %tlsldm(bar) 9 | ret i32* @bar 10 | } 11 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/uitofp.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=static < %s | FileCheck %s 2 | 3 | define void @f0() nounwind { 4 | entry: 5 | %b = alloca i32, align 4 6 | %a = alloca float, align 4 7 | store volatile i32 1, i32* %b, align 4 8 | %0 = load volatile i32, i32* %b, align 4 9 | %conv = uitofp i32 %0 to float 10 | store float %conv, float* %a, align 4 11 | ret void 12 | ; CHECK: jsub __floatunsisf 13 | } 14 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/ul1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | %struct.ua = type <{ i16, i32 }> 3 | 4 | @foo = common global %struct.ua zeroinitializer, align 1 5 | 6 | define i32 @main() nounwind { 7 | entry: 8 | store i32 10, i32* getelementptr inbounds (%struct.ua, %struct.ua* @foo, i32 0, i32 1), align 1 9 | ; 16: sb ${{[0-9]+|t9}}, {{[0-9]+|t9}}(${{[0-9]+|t9}}) 10 | ; 16: sb ${{[0-9]+|t9}}, {{[0-9]+|t9}}(${{[0-9]+|t9}}) 11 | ; 16: sb ${{[0-9]+|t9}}, {{[0-9]+|t9}}(${{[0-9]+|t9}}) 12 | ; 16: sb ${{[0-9]+|t9}}, {{[0-9]+|t9}}(${{[0-9]+|t9}}) 13 | ret i32 0 14 | } 15 | 16 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/vector-setcc.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 < %s 2 | 3 | @a = common global <4 x i32> zeroinitializer, align 16 4 | @b = common global <4 x i32> zeroinitializer, align 16 5 | @g0 = common global <4 x i32> zeroinitializer, align 16 6 | 7 | define void @foo0() nounwind { 8 | entry: 9 | %0 = load <4 x i32>, <4 x i32>* @a, align 16 10 | %1 = load <4 x i32>, <4 x i32>* @b, align 16 11 | %cmp = icmp slt <4 x i32> %0, %1 12 | %sext = sext <4 x i1> %cmp to <4 x i32> 13 | store <4 x i32> %sext, <4 x i32>* @g0, align 16 14 | ret void 15 | } 16 | 17 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/weak.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 < %s | FileCheck %s 2 | 3 | @t = common global i32 (...)* null, align 4 4 | 5 | define void @f() nounwind { 6 | entry: 7 | store i32 (...)* @test_weak, i32 (...)** @t, align 4 8 | ret void 9 | } 10 | 11 | ; CHECK: .weak test_weak 12 | declare extern_weak i32 @test_weak(...) 13 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/xor1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032I -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 2 | 3 | @x = global i32 65504, align 4 4 | @y = global i32 60929, align 4 5 | @.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1 6 | 7 | define i32 @main() nounwind { 8 | entry: 9 | %0 = load i32, i32* @x, align 4 10 | %1 = load i32, i32* @y, align 4 11 | %xor = xor i32 %0, %1 12 | ; 16: xor ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 13 | %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %xor) 14 | ret i32 0 15 | } 16 | 17 | declare i32 @printf(i8*, ...) 18 | -------------------------------------------------------------------------------- /lbdex/regression-test/Cpu0/zeroreg.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc < %s -march=cpu0 -mcpu=cpu032I | FileCheck %s 2 | 3 | @g1 = external global i32 4 | 5 | define i32 @foo0(i32 %s) nounwind readonly { 6 | entry: 7 | ; CHECK: addiu ${{[0-9]+|t9}}, $zero, 0 8 | ; CHECK: movn ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 9 | %tobool = icmp ne i32 %s, 0 10 | %0 = load i32, i32* @g1, align 4 11 | %cond = select i1 %tobool, i32 0, i32 %0 12 | ret i32 %cond 13 | } 14 | 15 | define i32 @foo1(i32 %s) nounwind readonly { 16 | entry: 17 | ; CHECK: addiu ${{[0-9]+|t9}}, $zero, 0 18 | ; CHECK: movn ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 19 | %tobool = icmp ne i32 %s, 0 20 | %0 = load i32, i32* @g1, align 4 21 | %cond = select i1 %tobool, i32 %0, i32 0 22 | ret i32 %cond 23 | } 24 | 25 | -------------------------------------------------------------------------------- /lbdex/regression-test/ex/ch3-directive.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el -mcpu=cpu032I < %s | FileCheck %s 2 | 3 | define i32 @main() #0 { 4 | entry: 5 | ; CHECK: .text 6 | ; CHECK: .section .mdebug.abi32 7 | ; CHECK: .previous 8 | ; CHECK: .file "" 9 | ; CHECK: .globl main 10 | ; CHECK: .align 2 11 | ; CHECK: .type main,@function 12 | ; CHECK: .ent main # @main 13 | ; CHECK: main: 14 | ; CHECK: .cfi_startproc 15 | ; CHECK: .frame $sp,8,$lr 16 | ; CHECK: .mask 0x00000000,0 17 | ; CHECK: .set noreorder 18 | ; CHECK: .set nomacro 19 | ; CHECK: .cfi_def_cfa_offset 8 20 | ; CHECK: .size main, ($tmp1)-main 21 | ; CHECK: .cfi_endproc 22 | 23 | %retval = alloca i32, align 4 24 | store i32 0, i32* %retval 25 | ret i32 0 26 | } 27 | 28 | -------------------------------------------------------------------------------- /lbdex/regression-test/ex/ch3-ret.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0el < %s | FileCheck %s 2 | 3 | define i32 @main() #0 { 4 | entry: 5 | ; CHECK: addiu $2, $zero, 0 6 | ; CHECK: ret $lr 7 | %retval = alloca i32, align 4 8 | store i32 0, i32* %retval 9 | ret i32 0 10 | } 11 | 12 | define void @_Z1fd() { 13 | entry: 14 | ; CHECK: ret $lr 15 | ret void 16 | } 17 | 18 | -------------------------------------------------------------------------------- /lbdex/regression-test/ex/ch7_3-bool.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -relocation-model=pic -filetype=asm < %s | FileCheck %s 2 | 3 | ; /// start 4 | define zeroext i1 @verify_load_bool() #0 { 5 | entry: 6 | %retval = alloca i1, align 1 7 | store i1 1, i1* %retval, align 1 8 | %0 = load i1* %retval 9 | ret i1 %0 10 | ; CHECK: addiu $[[T0:[0-9]+|t9]], $zero, 1 11 | ; CHECK: sb $[[T0]], 7($sp) 12 | ; CHECK: lbu $2, 7($sp) 13 | } 14 | -------------------------------------------------------------------------------- /lbdex/regression-test/ex/ch7_4-signed-int-mul.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic %s -o - | FileCheck %s 2 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic %s -o - | FileCheck %s 3 | 4 | ; ModuleID = 'ch7_4-signed-int-mul.bc' 5 | 6 | ; Function Attrs: nounwind 7 | define i64 @_Z13test_longlongv() { 8 | entry: 9 | %a1 = alloca i32, align 4 10 | %b1 = alloca i32, align 4 11 | %f = alloca i64, align 8 12 | store i32 50335744, i32* %a1, align 4 13 | store i32 33558528, i32* %b1, align 4 14 | %0 = load i32* %a1, align 4 15 | %conv = sext i32 %0 to i64 16 | %1 = load i32* %b1, align 4 17 | %conv1 = sext i32 %1 to i64 18 | %mul = mul nsw i64 %conv, %conv1 19 | store i64 %mul, i64* %f, align 8 20 | ; CHECK: mult ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 21 | ; CHECK: mflo ${{[0-9]+|t9}} 22 | ; CHECK: mfhi ${{[0-9]+|t9}} 23 | %2 = load i64* %f, align 8 24 | ret i64 %2 25 | } 26 | 27 | -------------------------------------------------------------------------------- /lbdex/regression-test/ex/ch7_4-signed-longlong-mul.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic %s -o - | FileCheck %s 2 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic %s -o - | FileCheck %s 3 | 4 | ; ModuleID = 'ch7_4-signed-longlong-mul.bc' 5 | 6 | ; Function Attrs: nounwind 7 | define i64 @_Z13test_longlongv() #0 { 8 | entry: 9 | %a = alloca i64, align 8 10 | %b = alloca i64, align 8 11 | %e = alloca i64, align 8 12 | store i64 12884901890, i64* %a, align 8 13 | store i64 4294967297, i64* %b, align 8 14 | %0 = load i64* %a, align 8 15 | %1 = load i64* %b, align 8 16 | %mul = mul nsw i64 %0, %1 17 | store i64 %mul, i64* %e, align 8 18 | ; CHECK: multu ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 19 | ; CHECK: mflo ${{[0-9]+|t9}} 20 | ; CHECK: mfhi ${{[0-9]+|t9}} 21 | ; CHECK: addu ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 22 | ; CHECK: addu ${{[0-9]+|t9}}, ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 23 | 24 | %2 = load i64* %e, align 8 25 | ret i64 %2 26 | } 27 | 28 | -------------------------------------------------------------------------------- /lbdex/regression-test/ex/ch7_4-unsigned-int-mul.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc -march=cpu0 -mcpu=cpu032I -relocation-model=pic %s -o - | FileCheck %s 2 | ; RUN: llc -march=cpu0 -mcpu=cpu032II -relocation-model=pic %s -o - | FileCheck %s 3 | 4 | ; ModuleID = 'ch7_4-unsigned-int-mul.bc' 5 | 6 | ; Function Attrs: nounwind 7 | define i64 @_Z13test_longlongv() { 8 | entry: 9 | %a1 = alloca i32, align 4 10 | %b1 = alloca i32, align 4 11 | %f = alloca i64, align 8 12 | store i32 50335744, i32* %a1, align 4 13 | store i32 33558528, i32* %b1, align 4 14 | %0 = load i32* %a1, align 4 15 | %conv = zext i32 %0 to i64 16 | %1 = load i32* %b1, align 4 17 | %conv1 = zext i32 %1 to i64 18 | %mul = mul nsw i64 %conv, %conv1 19 | store i64 %mul, i64* %f, align 8 20 | ; CHECK: multu ${{[0-9]+|t9}}, ${{[0-9]+|t9}} 21 | ; CHECK: mflo ${{[0-9]+|t9}} 22 | ; CHECK: mfhi ${{[0-9]+|t9}} 23 | %2 = load i64* %f, align 8 24 | ret i64 %2 25 | } 26 | 27 | -------------------------------------------------------------------------------- /lbdex/set-llvm-lit/README.txt: -------------------------------------------------------------------------------- 1 | llvm-lit can be changed to support the installed clang/llvm. Then llvm-lit can 2 | be run directly without build the clang/llvm. 3 | 4 | ## Run llvm-lit without building llvm-project 5 | 6 | $ pwd 7 | $ $HOME/test/llvm/llvm/test/CodeGen/Cpu0 8 | // change the following to dir for your llvm-project 9 | $ export LLVM_DIR=$HOME/test/llvm 10 | $ export LLVM_INSTALLED_DIR=$HOME/llvm-installed 11 | $ ~/llvm-installed/bin/llvm-lit addc.ll -a 12 | $ ~/llvm-installed/bin/llvm-lit . 13 | ~/test/llvm/clang/test/CodeGen/Cpu0$ ~/riscv/riscv_newlib/bin/llvm-lit . -a 14 | 15 | 16 | -------------------------------------------------------------------------------- /lbdex/verilog/Makefile: -------------------------------------------------------------------------------- 1 | #TRACE=-D TRACE 2 | all: 3 | iverilog ${TRACE} -o cpu0Is cpu0.v 4 | iverilog ${TRACE} -D CPU0II -o cpu0IIs cpu0.v 5 | 6 | .PHONY: clean 7 | clean: 8 | rm -rf cpu0.hex cpu0Is cpu0IIs 9 | rm -f *~ cpu0.config 10 | 11 | -------------------------------------------------------------------------------- /lbdex/verilog/readme: -------------------------------------------------------------------------------- 1 | The side effect as follows, 2 | 1. After bash buid-dlinker.sh, you must run "bash clean.sh" before "build-printf-stdarg-2.sh". Otherwise, the "run iverilog" will have incorrect code in output. 3 | 4 | -------------------------------------------------------------------------------- /note/builtin_fabs.c: -------------------------------------------------------------------------------- 1 | // ~/llvm/debug/build/bin/clang -emit-llvm -S builtin_fabs.c -o - 2 | 3 | // CHECK-LABEL: define{{.*}} void @test_float_builtin_ops 4 | void test_float_builtin_ops(float F, double D, long double LD) { 5 | volatile float resf; 6 | volatile double resd; 7 | volatile long double resld; 8 | 9 | resf = __builtin_fabsf(F); 10 | resd = __builtin_fabs(D); 11 | resld = __builtin_fabsl(LD); 12 | // CHECK: call float @llvm.fabs.f32(float 13 | // CHECK: call double @llvm.fabs.f64(double 14 | // CHECK: call x86_fp80 @llvm.fabs.f80(x86_fp80 15 | } 16 | -------------------------------------------------------------------------------- /note/gen-ll.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | CFILES=`ls *.c | sort -f` 4 | for file in $CFILES 5 | do 6 | clang -S $file -emit-llvm 7 | done 8 | 9 | -------------------------------------------------------------------------------- /note/gen-s.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | CFILES=`ls *.ll | sort -f` 4 | for file in $CFILES 5 | do 6 | ~/llvm/test/build/bin/llc -march=cpu0 -relocation-model=pic -filetype=asm $file 7 | # ~/llvm/debug/build/bin/llc -march=mips -relocation-model=pic -filetype=asm $file 8 | done 9 | 10 | -------------------------------------------------------------------------------- /note/mips_mult.ll: -------------------------------------------------------------------------------- 1 | ; ~/llvm/debug/build/bin/llc -debug -print-after-all -march=mipsel -mcpu=mips32 -mattr=+dsp -verify-machineinstrs 1.ll -o - 2 | 3 | define i64 @test__builtin_mips_mult1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 4 | entry: 5 | ; CHECK: mult $ac{{[0-9]}} 6 | 7 | %0 = tail call i64 @llvm.mips.mult(i32 %a0, i32 %a1) 8 | ret i64 %0 9 | } 10 | 11 | declare i64 @llvm.mips.mult(i32, i32) nounwind readnone 12 | -------------------------------------------------------------------------------- /note/note.txt: -------------------------------------------------------------------------------- 1 | mips_adds_a_b.ll in this folder is an example of intrinsic @llvm.mips.adds.a.b 2 | The intrinsic is (int_mips_adds_a_b defined in include/llvm/IR/IntrinsicsMips.td) and do instruction selection according to "int_mips_adds_a_b defined in MipsMSAInstrInfo.td". 3 | 4 | mips_mult.ll is the intrinsic function @llvm.mips.mult which processed by Lowering (MipsSEISelLowering.cpp) before do instruction selection. 5 | 6 | // my xcode-select setting 7 | $ xcode-select -p 8 | /Applications/Xcode.app/Contents/Developer 9 | -------------------------------------------------------------------------------- /note/note_lbd.txt: -------------------------------------------------------------------------------- 1 | 1. web: 2 | My llvmbook: 3 | github: https://github.com/Jonathan2251/lbd 4 | gh-pages: http://jonathan2251.github.io/lbd/index.html 5 | 6 | git clone https://github.com/Jonathan2251/lbd.git 7 | 8 | 2. Copy gen-ll.sh and gen-s.sh to src/tools/clang/test/CodeGen, and run it to 9 | get .ll and see those .ll can be compiled by Cpu0. 10 | 11 | 3. Pipeline example: 12 | https://github.com/jmahler/mips-cpu 13 | http://www.csie.ntu.edu.tw/~b98902125/305formalreport.pdf 14 | 15 | -------------------------------------------------------------------------------- /note/pipeline-ex/305formalreport.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/note/pipeline-ex/305formalreport.pdf -------------------------------------------------------------------------------- /papers/dlcompilersurvey.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/papers/dlcompilersurvey.pdf -------------------------------------------------------------------------------- /present/clang_llvm_intrinsic.ppt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/present/clang_llvm_intrinsic.ppt -------------------------------------------------------------------------------- /present/lbdContents.odp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/present/lbdContents.odp -------------------------------------------------------------------------------- /present/lbdOverview.odp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/present/lbdOverview.odp -------------------------------------------------------------------------------- /source/TutorialLLVMBackend.odp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/source/TutorialLLVMBackend.odp -------------------------------------------------------------------------------- /source/_static/dummy: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Jonathan2251/lbd/4fa0d580f18ef4c4e9048f15602723925e858cb9/source/_static/dummy -------------------------------------------------------------------------------- /source/_templates/layout.html: -------------------------------------------------------------------------------- 1 | {% extends "!layout.html" %} 2 | -------------------------------------------------------------------------------- /source/todo.rst: -------------------------------------------------------------------------------- 1 | Todo List 2 | ========= 3 | 4 | .. todolist:: 5 | -------------------------------------------------------------------------------- /working/atomic/2.cpp: -------------------------------------------------------------------------------- 1 | // clang++ -pthread -std=c++11 -S 2.cpp -emit-llvm -o 2.ll 2 | // atomic::load/store example 3 | #include // std::cout 4 | #include // std::atomic, std::memory_order_relaxed 5 | #include // std::thread 6 | 7 | std::atomic foo (0); 8 | 9 | void set_foo(int x) { 10 | foo.store(x,std::memory_order_relaxed); // set value atomically 11 | } 12 | 13 | void print_foo() { 14 | int x; 15 | do { 16 | x = foo.load(std::memory_order_relaxed); // get value atomically 17 | } while (x==0); 18 | std::cout << "foo: " << x << '\n'; 19 | } 20 | 21 | int main () 22 | { 23 | std::thread first (print_foo); 24 | std::thread second (set_foo,10); 25 | first.join(); 26 | second.join(); 27 | return 0; 28 | } 29 | 30 | -------------------------------------------------------------------------------- /working/atomic/4.cpp: -------------------------------------------------------------------------------- 1 | // clang++ -pthread -std=c++11 -S 4.cpp -emit-llvm -o 4.ll 2 | // Generate IRs "fence" 3 | 4 | #include // std::cout 5 | #include // std::atomic 6 | #include // std::thread 7 | 8 | int a; 9 | 10 | void func1() 11 | { 12 | for(int i = 0; i < 1000000; ++i) 13 | { 14 | a = i; 15 | // Ensure that changes to a to this point are visible to other threads 16 | atomic_thread_fence(std::memory_order_release); 17 | } 18 | } 19 | 20 | void func2() 21 | { 22 | for(int i = 0; i < 1000000; ++i) 23 | { 24 | // Ensure that this thread's view of a is up to date 25 | atomic_thread_fence(std::memory_order_acquire); 26 | std::cout << a; 27 | } 28 | } 29 | 30 | int main() 31 | { 32 | std::thread t1 (func1); 33 | std::thread t2 (func2); 34 | 35 | t1.join(); t2.join(); 36 | } 37 | 38 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/AsmParser/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_llvm_library(LLVMCpu0AsmParser 2 | Cpu0AsmParser.cpp 3 | ) -------------------------------------------------------------------------------- /working/atomic/Cpu0/AsmParser/LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Cpu0/AsmParser/LLVMBuild.txt ----------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | 18 | [component_0] 19 | type = Library 20 | name = Cpu0AsmParser 21 | parent = Cpu0 22 | required_libraries = Cpu0Desc Cpu0Info MC MCParser Support 23 | add_to_library_groups = Cpu0 24 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/Cpu0Config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CPU0CONFIG_H_ 2 | #define _CPU0CONFIG_H_ 3 | 4 | #define ENABLE_GPRESTORE 5 | 6 | #define CH2 20 7 | #define CH3_1 31 8 | #define CH3_2 32 9 | #define CH3_3 33 10 | #define CH3_4 34 11 | #define CH3_5 35 12 | #define CH4_1 41 13 | #define CH4_2 42 14 | #define CH5_1 51 15 | #define CH6_1 61 16 | #define CH7_1 71 17 | #define CH8_1 81 18 | #define CH8_2 82 19 | #define CH9_1 91 20 | #define CH9_2 92 21 | #define CH9_3 93 22 | #define CH10_1 101 23 | #define CH11_1 111 24 | #define CH11_2 112 25 | #define CH12_1 121 26 | 27 | #include "Cpu0SetChapter.h" 28 | 29 | #endif 30 | 31 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/Cpu0RegisterInfoGPROutForAsm.td: -------------------------------------------------------------------------------- 1 | 2 | //===----------------------------------------------------------------------===// 3 | // Register Classes 4 | //===----------------------------------------------------------------------===// 5 | 6 | def GPROut : RegisterClass<"Cpu0", [i32], 32, (add CPURegs)>; 7 | 8 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/Cpu0RegisterInfoGPROutForOther.td: -------------------------------------------------------------------------------- 1 | 2 | //===----------------------------------------------------------------------===// 3 | // Register Classes 4 | //===----------------------------------------------------------------------===// 5 | 6 | def GPROut : RegisterClass<"Cpu0", [i32], 32, (add (sub CPURegs, SW, PC, EPC))>; 7 | 8 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/Cpu0SERegisterInfo.cpp: -------------------------------------------------------------------------------- 1 | //===-- Cpu0SERegisterInfo.cpp - CPU0 Register Information ------== -------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains the CPU0 implementation of the TargetRegisterInfo 11 | // class. 12 | // 13 | //===----------------------------------------------------------------------===// 14 | 15 | #include "Cpu0SERegisterInfo.h" 16 | #if CH >= CH3_1 17 | 18 | using namespace llvm; 19 | 20 | #define DEBUG_TYPE "cpu0-reg-info" 21 | 22 | Cpu0SERegisterInfo::Cpu0SERegisterInfo(const Cpu0Subtarget &ST) 23 | : Cpu0RegisterInfo(ST) {} 24 | 25 | const TargetRegisterClass * 26 | Cpu0SERegisterInfo::intRegClass(unsigned Size) const { 27 | return &Cpu0::CPURegsRegClass; 28 | } 29 | 30 | #endif 31 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/Cpu0SelectionDAGInfo.cpp: -------------------------------------------------------------------------------- 1 | //===-- Cpu0SelectionDAGInfo.cpp - Cpu0 SelectionDAG Info -----------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file implements the Cpu0SelectionDAGInfo class. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #include "Cpu0SelectionDAGInfo.h" 15 | #if CH >= CH3_1 16 | 17 | #include "Cpu0TargetMachine.h" 18 | 19 | using namespace llvm; 20 | 21 | #define DEBUG_TYPE "cpu0-selectiondag-info" 22 | 23 | Cpu0SelectionDAGInfo::Cpu0SelectionDAGInfo(const DataLayout &DL) 24 | : TargetSelectionDAGInfo(&DL) {} 25 | 26 | Cpu0SelectionDAGInfo::~Cpu0SelectionDAGInfo() { 27 | } 28 | 29 | #endif 30 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/Cpu0SetChapter.h: -------------------------------------------------------------------------------- 1 | #define CH CH12_1 2 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/Disassembler/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_llvm_library(LLVMCpu0Disassembler 2 | Cpu0Disassembler.cpp 3 | ) 4 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/Disassembler/LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Cpu0/Disassembler/LLVMBuild.txt --------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | 18 | [component_0] 19 | type = Library 20 | name = Cpu0Disassembler 21 | parent = Cpu0 22 | required_libraries = MCDisassembler Support Cpu0Info 23 | add_to_library_groups = Cpu0 24 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/InstPrinter/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_llvm_library(LLVMCpu0AsmPrinter 2 | Cpu0InstPrinter.cpp 3 | ) 4 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/InstPrinter/LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Cpu0/InstPrinter/LLVMBuild.txt --------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | 18 | [component_0] 19 | type = Library 20 | name = Cpu0AsmPrinter 21 | parent = Cpu0 22 | required_libraries = MC Support 23 | add_to_library_groups = Cpu0 24 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/MCTargetDesc/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # MCTargetDesc/CMakeLists.txt 2 | add_llvm_library(LLVMCpu0Desc 3 | #if CH >= CH3_2 4 | Cpu0MCAsmInfo.cpp 5 | #endif 6 | #if CH >= CH5_1 7 | Cpu0AsmBackend.cpp 8 | Cpu0MCCodeEmitter.cpp 9 | Cpu0ELFObjectWriter.cpp 10 | #endif 11 | Cpu0MCTargetDesc.cpp 12 | ) 13 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/MCTargetDesc/LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Cpu0/MCTargetDesc/LLVMBuild.txt -------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | # MCTargetDesc/LLVMBuild.txt 18 | [component_0] 19 | type = Library 20 | name = Cpu0Desc 21 | parent = Cpu0 22 | required_libraries = MC 23 | #if CH >= CH3_2 24 | Cpu0AsmPrinter 25 | #endif 26 | Cpu0Info 27 | Support 28 | add_to_library_groups = Cpu0 29 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/TargetInfo/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_llvm_library(LLVMCpu0Info 2 | Cpu0TargetInfo.cpp 3 | ) 4 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/TargetInfo/Cpu0TargetInfo.cpp: -------------------------------------------------------------------------------- 1 | //===-- Cpu0TargetInfo.cpp - Cpu0 Target Implementation -------------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | 10 | #include "Cpu0.h" 11 | #include "llvm/IR/Module.h" 12 | #include "llvm/Support/TargetRegistry.h" 13 | using namespace llvm; 14 | 15 | Target llvm::TheCpu0Target, llvm::TheCpu0elTarget; 16 | 17 | extern "C" void LLVMInitializeCpu0TargetInfo() { 18 | RegisterTarget X(TheCpu0Target, "cpu0", "Cpu0"); 20 | 21 | RegisterTarget Y(TheCpu0elTarget, "cpu0el", "Cpu0el"); 23 | } 24 | -------------------------------------------------------------------------------- /working/atomic/Cpu0/TargetInfo/LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Cpu0/TargetInfo/LLVMBuild.txt ---------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | 18 | [component_0] 19 | type = Library 20 | name = Cpu0Info 21 | parent = Cpu0 22 | required_libraries = MC Support Target 23 | add_to_library_groups = Cpu0 24 | -------------------------------------------------------------------------------- /working/atomic/atomic-1.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc < %s -march=cpu0 -mcpu=cpu032II | FileCheck %s 2 | 3 | define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind { 4 | ; CHECK-LABEL: exchange_and_add: 5 | ; CHECK: ll 6 | ; CHECK: sc 7 | %tmp = atomicrmw add i32* %mem, i32 %val monotonic 8 | ret i32 %tmp 9 | } 10 | 11 | define i32 @exchange_and_cmp(i32* %mem) nounwind { 12 | ; CHECK-LABEL: exchange_and_cmp: 13 | ; CHECK: ll 14 | ; CHECK: sc 15 | %tmppair = cmpxchg i32* %mem, i32 0, i32 1 monotonic monotonic 16 | %tmp = extractvalue { i32, i1 } %tmppair, 0 17 | ret i32 %tmp 18 | } 19 | 20 | define i32 @exchange(i32* %mem, i32 %val) nounwind { 21 | ; CHECK-LABEL: exchange: 22 | ; CHECK: ll 23 | ; CHECK: sc 24 | %tmp = atomicrmw xchg i32* %mem, i32 1 monotonic 25 | ret i32 %tmp 26 | } 27 | -------------------------------------------------------------------------------- /working/atomic/atomics-fences.ll: -------------------------------------------------------------------------------- 1 | ; RUN: llc < %s -march=cpu0 -mcpu=cpu032II | FileCheck %s --check-prefix=CHECK 2 | 3 | ; Fences 4 | define void @fence_acquire() { 5 | ; CHECK-LABEL: fence_acquire 6 | ; CHECK: sync 7 | fence acquire 8 | ret void 9 | } 10 | define void @fence_release() { 11 | ; CHECK-LABEL: fence_release 12 | ; CHECK: sync 13 | fence release 14 | ret void 15 | } 16 | define void @fence_seq_cst() { 17 | ; CHECK-LABEL: fence_seq_cst 18 | ; CHECK: sync 19 | fence seq_cst 20 | ret void 21 | } 22 | --------------------------------------------------------------------------------