├── BUILD.md ├── Makefile ├── README.md ├── TODO.md ├── bitstreams ├── digilent_arty.bit ├── digilent_arty_100t_1080p_12bpp_vga_pmodbc.bit └── gsd_orangecrab.dfu ├── c_compat.h ├── custom_float.h ├── doc ├── Sphery-vs-Shapes.pdf └── sphery.tex ├── donut.cpp ├── fixed_div.h ├── fixed_type.h ├── float_e_m_t_helper.h ├── float_type.h ├── fp_overloads.c ├── gateware ├── CSRTransform.py ├── lcd.py └── lcdif.py ├── litex_soc.py ├── main.cpp ├── mandel.c ├── msponge.cpp ├── opt_primitives.c ├── pattern_gen.cpp ├── pipelinec_app.c ├── pipelinec_compat.h ├── pipelinec_float_type.h ├── pipelinec_litex.c ├── power.cpp ├── rt.c ├── simplert.cpp ├── simulator_main.cpp ├── tr.cpp ├── tr.h ├── tr_base.cpp ├── tr_pipelinec.cpp ├── typesperf.h ├── uart_buttons_demo.c ├── verilog ├── top-donut.v └── top-gsd_orangecrab.v └── vhd └── all_vhdl_files ├── BIN_OP_AND_int16_t_int2_t_1CLK_3c61c972.vhd ├── BIN_OP_AND_int16_t_int2_t_1CLK_882ca8ab.vhd ├── BIN_OP_AND_uint16_t_uint16_t_1CLK_90dbb3c4.vhd ├── BIN_OP_AND_uint16_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_AND_uint1_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_AND_uint1_t_uint1_t_1CLK_0dcc764a.vhd ├── BIN_OP_AND_uint8_t_uint6_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_int22_t_int2_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint10_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint11_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint12_t_uint11_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint12_t_uint12_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint12_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint13_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint14_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint15_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint16_t_uint11_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint16_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint17_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint18_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint19_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint1_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint1_t_uint1_t_1CLK_047da1d7.vhd ├── BIN_OP_EQ_uint1_t_uint1_t_1CLK_3b5c2478.vhd ├── BIN_OP_EQ_uint20_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint21_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint22_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint2_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint2_t_uint2_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint32_t_uint4_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint3_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint4_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint4_t_uint4_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint5_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint6_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint6_t_uint5_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint7_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint8_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint8_t_uint1_t_1CLK_b70c7a85.vhd ├── BIN_OP_EQ_uint9_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint9_t_uint1_t_1CLK_1d20f134.vhd ├── BIN_OP_EQ_uint9_t_uint1_t_1CLK_1f38c835.vhd ├── BIN_OP_EQ_uint9_t_uint1_t_1CLK_3b8f6eaf.vhd ├── BIN_OP_EQ_uint9_t_uint1_t_1CLK_7de091c9.vhd ├── BIN_OP_EQ_uint9_t_uint1_t_1CLK_9f7700da.vhd ├── BIN_OP_EQ_uint9_t_uint1_t_1CLK_b02c3a8b.vhd ├── BIN_OP_EQ_uint9_t_uint1_t_1CLK_bfb8e1f3.vhd ├── BIN_OP_EQ_uint9_t_uint1_t_1CLK_c7e994bb.vhd ├── BIN_OP_EQ_uint9_t_uint1_t_1CLK_cbaf6cb5.vhd ├── BIN_OP_EQ_uint9_t_uint1_t_1CLK_dadba55c.vhd ├── BIN_OP_EQ_uint9_t_uint8_t_0CLK_de264c78.vhd ├── BIN_OP_EQ_uint9_t_uint8_t_1CLK_0043f8e0.vhd ├── BIN_OP_EQ_uint9_t_uint8_t_1CLK_47bad9cd.vhd ├── BIN_OP_EQ_uint9_t_uint8_t_1CLK_7440327c.vhd ├── BIN_OP_EQ_uint9_t_uint8_t_1CLK_7444c060.vhd ├── BIN_OP_EQ_uint9_t_uint8_t_1CLK_791b4635.vhd ├── BIN_OP_EQ_uint9_t_uint8_t_1CLK_7edbbb05.vhd ├── BIN_OP_EQ_uint9_t_uint8_t_1CLK_9e55c9b8.vhd ├── BIN_OP_EQ_uint9_t_uint8_t_1CLK_ba59811e.vhd ├── BIN_OP_EQ_uint9_t_uint8_t_1CLK_bbffcd0e.vhd ├── BIN_OP_EQ_uint9_t_uint8_t_1CLK_fba60e93.vhd ├── BIN_OP_GTE_float_8_14_t_float_8_14_t_0CLK_36723c85.vhd ├── BIN_OP_GTE_int8_t_int2_t_0CLK_de264c78.vhd ├── BIN_OP_GTE_uint12_t_uint12_t_0CLK_de264c78.vhd ├── BIN_OP_GTE_uint16_t_uint14_t_0CLK_de264c78.vhd ├── BIN_OP_GTE_uint16_t_uint16_t_0CLK_de264c78.vhd ├── BIN_OP_GTE_uint16_t_uint4_t_1CLK_52497a46.vhd ├── BIN_OP_GTE_uint16_t_uint9_t_1CLK_c580f7b9.vhd ├── BIN_OP_GTE_uint22_t_uint22_t_0CLK_de264c78.vhd ├── BIN_OP_GT_float_8_14_t_float_8_14_t_0CLK_36723c85.vhd ├── BIN_OP_GT_float_8_14_t_float_8_14_t_1CLK_19c51486.vhd ├── BIN_OP_GT_int22_t_int22_t_0CLK_de264c78.vhd ├── BIN_OP_GT_uint16_t_uint14_t_0CLK_de264c78.vhd ├── BIN_OP_GT_uint16_t_uint4_t_1CLK_52497a46.vhd ├── BIN_OP_GT_uint22_t_uint22_t_0CLK_de264c78.vhd ├── BIN_OP_GT_uint6_t_uint5_t_0CLK_de264c78.vhd ├── BIN_OP_GT_uint8_t_uint5_t_1CLK_18ce96cc.vhd ├── BIN_OP_GT_uint8_t_uint8_t_0CLK_de264c78.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_0713e065.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_148e92aa.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_17fff553.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_1abfd622.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_225e1378.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_59d99157.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_7eaccd18.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_7f854316.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_85689e35.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_9ae42a5f.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_9e06a5b2.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_a4b38ed6.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_cdbe6a23.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_ce95deba.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_da193f47.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_2CLK_e6088fbf.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_0116d580.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_079db660.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_1c05bdb6.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_1c29d299.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_21487fd1.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_26fca48e.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_31c4be6a.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_3e9fd25e.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_429910ba.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_58295ff6.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_58b43a5e.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_61d56c8d.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_6f881e97.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_7e87cfab.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_80c26621.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_891eb221.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_8e695e7e.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_900b2182.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_977e22b4.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_9878c1a3.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_9912251f.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_9e3d748c.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_a262d211.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_a317babb.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_a92614b0.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_b44a7817.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_b7f61fd3.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_bb1d1126.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_bcbdfe9b.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_ce6c9415.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_cfe18897.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_d209a25e.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_de099f0e.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_e1b773f3.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_e43a05b5.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_e4db71ea.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_e721a410.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_f01625e3.vhd ├── BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t_3CLK_f86a86fc.vhd ├── BIN_OP_INFERRED_MULT_int22_t_int22_t_0CLK_de264c78.vhd ├── BIN_OP_INFERRED_MULT_int22_t_int22_t_5CLK_1fe629b3.vhd ├── BIN_OP_INFERRED_MULT_uint15_t_uint15_t_2CLK_d9e4e3ca.vhd ├── BIN_OP_INFERRED_MULT_uint16_t_uint16_t_0CLK_de264c78.vhd ├── BIN_OP_INFERRED_MULT_uint16_t_uint16_t_2CLK_d9e4e3ca.vhd ├── BIN_OP_INFERRED_MULT_uint23_t_uint16_t_2CLK_d9e4e3ca.vhd ├── BIN_OP_LTE_int8_t_int6_t_0CLK_de264c78.vhd ├── BIN_OP_LTE_uint22_t_uint22_t_0CLK_de264c78.vhd ├── BIN_OP_LTE_uint22_t_uint22_t_1CLK_069bf858.vhd ├── BIN_OP_LTE_uint22_t_uint22_t_1CLK_599f7a5a.vhd ├── BIN_OP_LTE_uint22_t_uint22_t_1CLK_81e2dec4.vhd ├── BIN_OP_LT_float_8_14_t_float_8_14_t_0CLK_36723c85.vhd ├── BIN_OP_LT_float_8_14_t_float_8_14_t_1CLK_6a161d44.vhd ├── BIN_OP_LT_float_8_14_t_float_8_14_t_1CLK_7a8500e0.vhd ├── BIN_OP_LT_float_8_14_t_float_8_14_t_1CLK_b24ad8a3.vhd ├── BIN_OP_LT_float_8_14_t_float_8_14_t_1CLK_c48f5a28.vhd ├── BIN_OP_LT_float_8_14_t_float_8_14_t_1CLK_cd1d7bda.vhd ├── BIN_OP_LT_float_8_14_t_float_8_14_t_2CLK_30080f87.vhd ├── BIN_OP_LT_int17_t_int17_t_0CLK_de264c78.vhd ├── BIN_OP_LT_int22_t_int22_t_1CLK_9adc70c6.vhd ├── BIN_OP_LT_int22_t_int2_t_0CLK_de264c78.vhd ├── BIN_OP_LT_int8_t_int2_t_0CLK_de264c78.vhd ├── BIN_OP_LT_uint12_t_uint11_t_0CLK_de264c78.vhd ├── BIN_OP_LT_uint12_t_uint13_t_0CLK_de264c78.vhd ├── BIN_OP_LT_uint16_t_uint17_t_1CLK_8ed726ba.vhd ├── BIN_OP_LT_uint16_t_uint6_t_1CLK_52497a46.vhd ├── BIN_OP_LT_uint22_t_uint22_t_0CLK_de264c78.vhd ├── BIN_OP_LT_uint22_t_uint22_t_1CLK_66a4166e.vhd ├── BIN_OP_MINUS_float_8_14_t_float_8_14_t_6CLK_ab6afdf3.vhd ├── BIN_OP_MINUS_float_8_14_t_float_8_14_t_7CLK_19c83a8c.vhd ├── BIN_OP_MINUS_float_8_14_t_float_8_14_t_7CLK_4a51b6c6.vhd ├── BIN_OP_MINUS_float_8_14_t_float_8_14_t_7CLK_56590bdb.vhd ├── BIN_OP_MINUS_float_8_14_t_float_8_14_t_7CLK_6919dfde.vhd ├── BIN_OP_MINUS_float_8_14_t_float_8_14_t_7CLK_69b948f7.vhd ├── BIN_OP_MINUS_float_8_14_t_float_8_14_t_7CLK_adccce0a.vhd ├── BIN_OP_MINUS_float_8_14_t_float_8_14_t_7CLK_f27c380f.vhd ├── BIN_OP_MINUS_int13_t_int16_t_1CLK_c9fe58b1.vhd ├── BIN_OP_MINUS_int16_t_int13_t_1CLK_c9fe58b1.vhd ├── BIN_OP_MINUS_int22_t_int22_t_0CLK_de264c78.vhd ├── BIN_OP_MINUS_int22_t_int22_t_1CLK_7bf6179a.vhd ├── BIN_OP_MINUS_int22_t_int22_t_1CLK_cc0c0104.vhd ├── BIN_OP_MINUS_int22_t_int22_t_1CLK_cf8d5eff.vhd ├── BIN_OP_MINUS_int9_t_int8_t_0CLK_de264c78.vhd ├── BIN_OP_MINUS_uint22_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_MINUS_uint22_t_uint23_t_0CLK_de264c78.vhd ├── BIN_OP_MINUS_uint22_t_uint23_t_1CLK_21f30ba8.vhd ├── BIN_OP_MINUS_uint22_t_uint23_t_1CLK_287421ff.vhd ├── BIN_OP_MINUS_uint22_t_uint23_t_1CLK_91f011d1.vhd ├── BIN_OP_MINUS_uint22_t_uint23_t_1CLK_bb6b1022.vhd ├── BIN_OP_MINUS_uint22_t_uint23_t_1CLK_dcac6ef8.vhd ├── BIN_OP_MINUS_uint22_t_uint23_t_1CLK_f0c3059b.vhd ├── BIN_OP_MINUS_uint23_t_uint1_t_1CLK_a95d2991.vhd ├── BIN_OP_MINUS_uint5_t_uint6_t_0CLK_de264c78.vhd ├── BIN_OP_MINUS_uint8_t_uint4_t_0CLK_de264c78.vhd ├── BIN_OP_MINUS_uint8_t_uint8_t_1CLK_b70c7a85.vhd ├── BIN_OP_MINUS_uint9_t_uint7_t_0CLK_de264c78.vhd ├── BIN_OP_MINUS_uint9_t_uint7_t_1CLK_0895a02d.vhd ├── BIN_OP_MINUS_uint9_t_uint7_t_1CLK_348ec861.vhd ├── BIN_OP_MINUS_uint9_t_uint7_t_1CLK_70b42fa9.vhd ├── BIN_OP_MINUS_uint9_t_uint7_t_1CLK_a1607f01.vhd ├── BIN_OP_MINUS_uint9_t_uint7_t_1CLK_aabacb4e.vhd ├── BIN_OP_MINUS_uint9_t_uint7_t_1CLK_ab6709d8.vhd ├── BIN_OP_MINUS_uint9_t_uint7_t_1CLK_af61d77a.vhd ├── BIN_OP_MINUS_uint9_t_uint7_t_1CLK_bd21438f.vhd ├── BIN_OP_MINUS_uint9_t_uint7_t_1CLK_c0208366.vhd ├── BIN_OP_MINUS_uint9_t_uint7_t_1CLK_d7ffd5ad.vhd ├── BIN_OP_MINUS_uint9_t_uint7_t_1CLK_f55fa603.vhd ├── BIN_OP_MINUS_uint9_t_uint7_t_1CLK_f9bb3ad5.vhd ├── BIN_OP_MINUS_uint9_t_uint7_t_1CLK_fe548b65.vhd ├── BIN_OP_NEQ_float_8_14_t_float_8_14_t_0CLK_de264c78.vhd ├── BIN_OP_NEQ_int16_t_int2_t_0CLK_de264c78.vhd ├── BIN_OP_NEQ_int17_t_int2_t_0CLK_de264c78.vhd ├── BIN_OP_NEQ_uint16_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_NEQ_uint1_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_NEQ_uint1_t_uint1_t_1CLK_2bdb950a.vhd ├── BIN_OP_NEQ_uint1_t_uint1_t_1CLK_541f6485.vhd ├── BIN_OP_NEQ_uint1_t_uint1_t_1CLK_ceb57ac8.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_0634d84a.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_07058cbb.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_2910ae70.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_3b31bc23.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_461124c5.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_47d6272a.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_4d385481.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_4da6766b.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_66e54d54.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_68da2db1.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_9e1336f2.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_a014d77c.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_ae33126e.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_b4df007d.vhd ├── BIN_OP_NEQ_uint8_t_uint1_t_1CLK_de7dbec0.vhd ├── BIN_OP_OR_uint1_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_OR_uint1_t_uint1_t_1CLK_0766335b.vhd ├── BIN_OP_OR_uint1_t_uint1_t_1CLK_0f161a66.vhd ├── BIN_OP_OR_uint1_t_uint1_t_1CLK_154dd632.vhd ├── BIN_OP_OR_uint1_t_uint1_t_1CLK_43831663.vhd ├── BIN_OP_OR_uint1_t_uint1_t_1CLK_5c7e3048.vhd ├── BIN_OP_OR_uint1_t_uint1_t_1CLK_9695376d.vhd ├── BIN_OP_OR_uint1_t_uint1_t_1CLK_9b6b4a7e.vhd ├── BIN_OP_OR_uint1_t_uint1_t_1CLK_e6927340.vhd ├── BIN_OP_OR_uint1_t_uint2_t_0CLK_de264c78.vhd ├── BIN_OP_OR_uint2_t_uint3_t_0CLK_de264c78.vhd ├── BIN_OP_OR_uint32_t_uint32_t_0CLK_de264c78.vhd ├── BIN_OP_OR_uint3_t_uint3_t_0CLK_de264c78.vhd ├── BIN_OP_OR_uint3_t_uint4_t_0CLK_de264c78.vhd ├── BIN_OP_OR_uint4_t_uint4_t_0CLK_de264c78.vhd ├── BIN_OP_OR_uint4_t_uint5_t_0CLK_de264c78.vhd ├── BIN_OP_OR_uint5_t_uint5_t_0CLK_de264c78.vhd ├── BIN_OP_OR_uint5_t_uint5_t_1CLK_212a91c4.vhd ├── BIN_OP_PLUS_float_8_14_t_float_8_14_t_6CLK_d5d58814.vhd ├── BIN_OP_PLUS_int16_t_int11_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_int22_t_int22_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_int22_t_int22_t_1CLK_04bf1fff.vhd ├── BIN_OP_PLUS_int22_t_int22_t_1CLK_0752e6b6.vhd ├── BIN_OP_PLUS_int22_t_int22_t_1CLK_966d2e60.vhd ├── BIN_OP_PLUS_int22_t_int22_t_1CLK_de5e3cda.vhd ├── BIN_OP_PLUS_int22_t_int22_t_1CLK_f74d32f0.vhd ├── BIN_OP_PLUS_int22_t_int22_t_1CLK_fccaa695.vhd ├── BIN_OP_PLUS_int9_t_int2_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_int9_t_int2_t_1CLK_19c13487.vhd ├── BIN_OP_PLUS_int9_t_int2_t_1CLK_a8c0fa4e.vhd ├── BIN_OP_PLUS_int9_t_int2_t_1CLK_bb246301.vhd ├── BIN_OP_PLUS_int9_t_int2_t_1CLK_ca3d4f14.vhd ├── BIN_OP_PLUS_int9_t_int2_t_1CLK_d399d482.vhd ├── BIN_OP_PLUS_int9_t_int2_t_1CLK_fd0c1906.vhd ├── BIN_OP_PLUS_int9_t_int3_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_int9_t_int4_t_1CLK_dc6b5ebe.vhd ├── BIN_OP_PLUS_int9_t_int5_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_int9_t_int5_t_1CLK_6728bbdf.vhd ├── BIN_OP_PLUS_int9_t_int5_t_1CLK_78d9e61c.vhd ├── BIN_OP_PLUS_int9_t_int5_t_1CLK_e3bedfa2.vhd ├── BIN_OP_PLUS_uint12_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_uint16_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_uint17_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_uint22_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_uint32_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_uint4_t_uint16_t_1CLK_ab623c35.vhd ├── BIN_OP_PLUS_uint4_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_uint5_t_uint1_t_1CLK_168e1cee.vhd ├── BIN_OP_PLUS_uint8_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_uint8_t_uint1_t_1CLK_d90a86e5.vhd ├── BIN_OP_PLUS_uint8_t_uint4_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_uint8_t_uint4_t_1CLK_48f438b2.vhd ├── BIN_OP_PLUS_uint8_t_uint4_t_1CLK_5de55159.vhd ├── BIN_OP_PLUS_uint8_t_uint4_t_1CLK_6cb98092.vhd ├── BIN_OP_PLUS_uint8_t_uint4_t_1CLK_df5077d8.vhd ├── BIN_OP_PLUS_uint8_t_uint4_t_1CLK_dfc4886a.vhd ├── BIN_OP_PLUS_uint8_t_uint7_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_uint9_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_uint9_t_uint1_t_1CLK_072a065e.vhd ├── BIN_OP_PLUS_uint9_t_uint1_t_1CLK_13755ada.vhd ├── BIN_OP_PLUS_uint9_t_uint1_t_1CLK_4cdce0f1.vhd ├── BIN_OP_PLUS_uint9_t_uint1_t_1CLK_7be9fb62.vhd ├── BIN_OP_PLUS_uint9_t_uint1_t_1CLK_a5f1df5f.vhd ├── BIN_OP_PLUS_uint9_t_uint1_t_1CLK_a9511f60.vhd ├── BIN_OP_PLUS_uint9_t_uint1_t_1CLK_b5220df6.vhd ├── BIN_OP_PLUS_uint9_t_uint1_t_1CLK_bb0758bb.vhd ├── BIN_OP_PLUS_uint9_t_uint1_t_1CLK_be70ba50.vhd ├── BIN_OP_PLUS_uint9_t_uint1_t_1CLK_c90f2cbb.vhd ├── BIN_OP_PLUS_uint9_t_uint1_t_1CLK_edf748ad.vhd ├── BIN_OP_PLUS_uint9_t_uint9_t_0CLK_de264c78.vhd ├── BIN_OP_PLUS_uint9_t_uint9_t_1CLK_1d20f134.vhd ├── BIN_OP_PLUS_uint9_t_uint9_t_1CLK_1f38c835.vhd ├── BIN_OP_PLUS_uint9_t_uint9_t_1CLK_3b8f6eaf.vhd ├── BIN_OP_PLUS_uint9_t_uint9_t_1CLK_7de091c9.vhd ├── BIN_OP_PLUS_uint9_t_uint9_t_1CLK_9f7700da.vhd ├── BIN_OP_PLUS_uint9_t_uint9_t_1CLK_b02c3a8b.vhd ├── BIN_OP_PLUS_uint9_t_uint9_t_1CLK_bfb8e1f3.vhd ├── BIN_OP_PLUS_uint9_t_uint9_t_1CLK_c7e994bb.vhd ├── BIN_OP_PLUS_uint9_t_uint9_t_1CLK_cbaf6cb5.vhd ├── BIN_OP_PLUS_uint9_t_uint9_t_1CLK_dadba55c.vhd ├── BIN_OP_SL_float_8_14_t_int2_t_0CLK_e595f783.vhd ├── BIN_OP_SL_float_8_14_t_int2_t_1CLK_241c222a.vhd ├── BIN_OP_SL_float_8_14_t_int2_t_1CLK_614886e9.vhd ├── BIN_OP_SL_float_8_14_t_int2_t_1CLK_98ff0db6.vhd ├── BIN_OP_SL_float_8_14_t_int2_t_1CLK_b63c798d.vhd ├── BIN_OP_SL_float_8_14_t_int2_t_1CLK_d604ecb6.vhd ├── BIN_OP_SL_float_8_14_t_int2_t_1CLK_ed8bd892.vhd ├── BIN_OP_SL_float_8_14_t_int2_t_1CLK_f139d42d.vhd ├── BIN_OP_SL_float_8_14_t_int3_t_0CLK_e595f783.vhd ├── BIN_OP_SL_float_8_14_t_int4_t_1CLK_71d30f8d.vhd ├── BIN_OP_SL_float_8_14_t_int5_t_0CLK_e595f783.vhd ├── BIN_OP_SL_float_8_14_t_int5_t_1CLK_0de31430.vhd ├── BIN_OP_SL_float_8_14_t_int5_t_1CLK_11756a99.vhd ├── BIN_OP_SL_float_8_14_t_int5_t_1CLK_9d8547c8.vhd ├── BIN_OP_SL_float_8_14_t_uint1_t_0CLK_e595f783.vhd ├── BIN_OP_SL_float_8_14_t_uint1_t_1CLK_fce1fa37.vhd ├── BIN_OP_SL_float_8_14_t_uint4_t_0CLK_e595f783.vhd ├── BIN_OP_SL_float_8_14_t_uint4_t_1CLK_1f4e2525.vhd ├── BIN_OP_SL_float_8_14_t_uint4_t_1CLK_2e0f70db.vhd ├── BIN_OP_SL_float_8_14_t_uint4_t_1CLK_5ecdda54.vhd ├── BIN_OP_SL_float_8_14_t_uint4_t_1CLK_7683d857.vhd ├── BIN_OP_SL_float_8_14_t_uint4_t_1CLK_fce4b983.vhd ├── BIN_OP_SL_uint21_t_uint4_t_0CLK_25d197a7.vhd ├── BIN_OP_SL_uint22_t_uint6_t_0CLK_9d359dd9.vhd ├── BIN_OP_SL_uint36_t_uint5_t_0CLK_295015b8.vhd ├── BIN_OP_SR_int22_t_uint6_t_0CLK_4e6656cf.vhd ├── BIN_OP_SR_int22_t_uint8_t_1CLK_57b0e109.vhd ├── BIN_OP_XOR_int16_t_int16_t_0CLK_de264c78.vhd ├── BIN_OP_XOR_uint16_t_uint16_t_0CLK_de264c78.vhd ├── BIN_OP_XOR_uint1_t_uint1_t_0CLK_de264c78.vhd ├── BIN_OP_XOR_uint1_t_uint1_t_1CLK_325af60c.vhd ├── BIN_OP_XOR_uint1_t_uint1_t_1CLK_40870500.vhd ├── BIN_OP_XOR_uint1_t_uint1_t_1CLK_7007d036.vhd ├── BIN_OP_XOR_uint1_t_uint1_t_1CLK_79814df2.vhd ├── BIN_OP_XOR_uint1_t_uint1_t_1CLK_a46e9a73.vhd ├── BIN_OP_XOR_uint1_t_uint1_t_1CLK_d8b99818.vhd ├── BIN_OP_XOR_uint1_t_uint1_t_1CLK_dbe39375.vhd ├── BIN_OP_XOR_uint1_t_uint1_t_1CLK_ebcfd9ea.vhd ├── BIN_OP_XOR_uint32_t_uint32_t_0CLK_de264c78.vhd ├── CAST_TO_float_8_14_t_int22_t_3CLK_489e4d91.vhd ├── CAST_TO_int22_t_float_8_14_t_0CLK_3e95be9f.vhd ├── CAST_TO_int22_t_float_8_14_t_2CLK_eee4f554.vhd ├── CONST_SL_10_int22_t_0CLK_de264c78.vhd ├── CONST_SL_10_int32_t_0CLK_de264c78.vhd ├── CONST_SL_16_uint22_t_0CLK_de264c78.vhd ├── CONST_SL_16_uint36_t_0CLK_de264c78.vhd ├── CONST_SL_1_int16_t_0CLK_de264c78.vhd ├── CONST_SL_1_uint21_t_0CLK_de264c78.vhd ├── CONST_SL_1_uint22_t_0CLK_de264c78.vhd ├── CONST_SL_1_uint36_t_0CLK_de264c78.vhd ├── CONST_SL_2_uint21_t_0CLK_de264c78.vhd ├── CONST_SL_2_uint22_t_0CLK_de264c78.vhd ├── CONST_SL_2_uint36_t_0CLK_de264c78.vhd ├── CONST_SL_4_uint21_t_0CLK_de264c78.vhd ├── CONST_SL_4_uint22_t_0CLK_de264c78.vhd ├── CONST_SL_4_uint36_t_0CLK_de264c78.vhd ├── CONST_SL_8_uint21_t_0CLK_de264c78.vhd ├── CONST_SL_8_uint22_t_0CLK_de264c78.vhd ├── CONST_SL_8_uint36_t_0CLK_de264c78.vhd ├── CONST_SL_9_uint32_t_0CLK_de264c78.vhd ├── CONST_SR_0_uint4_t_0CLK_de264c78.vhd ├── CONST_SR_0_uint8_t_0CLK_de264c78.vhd ├── CONST_SR_10_int17_t_0CLK_de264c78.vhd ├── CONST_SR_10_int22_t_0CLK_de264c78.vhd ├── CONST_SR_10_int44_t_0CLK_de264c78.vhd ├── CONST_SR_11_uint39_t_0CLK_de264c78.vhd ├── CONST_SR_13_uint16_t_0CLK_de264c78.vhd ├── CONST_SR_16_int22_t_0CLK_de264c78.vhd ├── CONST_SR_1_int22_t_0CLK_de264c78.vhd ├── CONST_SR_1_uint16_t_0CLK_de264c78.vhd ├── CONST_SR_1_uint23_t_0CLK_de264c78.vhd ├── CONST_SR_1_uint8_t_0CLK_de264c78.vhd ├── CONST_SR_23_uint32_t_0CLK_de264c78.vhd ├── CONST_SR_2_int22_t_0CLK_de264c78.vhd ├── CONST_SR_2_uint16_t_0CLK_de264c78.vhd ├── CONST_SR_2_uint8_t_0CLK_de264c78.vhd ├── CONST_SR_3_uint4_t_0CLK_de264c78.vhd ├── CONST_SR_3_uint8_t_0CLK_de264c78.vhd ├── CONST_SR_4_int22_t_0CLK_de264c78.vhd ├── CONST_SR_4_uint8_t_0CLK_de264c78.vhd ├── CONST_SR_5_uint16_t_0CLK_de264c78.vhd ├── CONST_SR_5_uint8_t_0CLK_de264c78.vhd ├── CONST_SR_6_uint8_t_0CLK_de264c78.vhd ├── CONST_SR_7_uint32_t_0CLK_de264c78.vhd ├── CONST_SR_7_uint8_t_0CLK_de264c78.vhd ├── CONST_SR_8_int22_t_0CLK_de264c78.vhd ├── MUX_uint1_t_ext_vga_state_t_ext_vga_state_t_0CLK_de264c78.vhd ├── MUX_uint1_t_fixed3_fixed3_0CLK_de264c78.vhd ├── MUX_uint1_t_fixed3_fixed3_1CLK_43022cd0.vhd ├── MUX_uint1_t_fixed3_fixed3_1CLK_6065287d.vhd ├── MUX_uint1_t_fixed3_fixed3_1CLK_88f3c62f.vhd ├── MUX_uint1_t_fixed3_fixed3_1CLK_b60b22dc.vhd ├── MUX_uint1_t_fixed3_fixed3_1CLK_dafad20f.vhd ├── MUX_uint1_t_fixed_fixed_0CLK_de264c78.vhd ├── MUX_uint1_t_fixed_fixed_1CLK_6b87fe4c.vhd ├── MUX_uint1_t_fixed_fixed_1CLK_b7b0a9f1.vhd ├── MUX_uint1_t_fixed_fixed_1CLK_bdf9d400.vhd ├── MUX_uint1_t_fixed_fixed_1CLK_d913c7cc.vhd ├── MUX_uint1_t_fixed_fixed_1CLK_f8a95ef5.vhd ├── MUX_uint1_t_float_8_14_t_float_8_14_t_0CLK_de264c78.vhd ├── MUX_uint1_t_float_8_14_t_float_8_14_t_1CLK_51a8450f.vhd ├── MUX_uint1_t_float_8_14_t_float_8_14_t_1CLK_5718387d.vhd ├── MUX_uint1_t_float_8_14_t_float_8_14_t_1CLK_99fabe20.vhd ├── MUX_uint1_t_full_state_t_full_state_t_0CLK_de264c78.vhd ├── MUX_uint1_t_hit_out_hit_out_0CLK_de264c78.vhd ├── MUX_uint1_t_hit_out_hit_out_1CLK_3d2f1477.vhd ├── MUX_uint1_t_hit_out_hit_out_1CLK_9dccc308.vhd ├── MUX_uint1_t_hit_out_hit_out_1CLK_f8a95ef5.vhd ├── MUX_uint1_t_int16_t_int16_t_0CLK_de264c78.vhd ├── MUX_uint1_t_int22_t_int22_t_0CLK_de264c78.vhd ├── MUX_uint1_t_int22_t_int22_t_1CLK_d20ad696.vhd ├── MUX_uint1_t_material_t_material_t_0CLK_de264c78.vhd ├── MUX_uint1_t_material_t_material_t_1CLK_3d2f1477.vhd ├── MUX_uint1_t_pixel_t_pixel_t_0CLK_de264c78.vhd ├── MUX_uint1_t_point_and_dir_point_and_dir_0CLK_de264c78.vhd ├── MUX_uint1_t_uart_rx_mac_state_t_uart_rx_mac_state_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uart_tx_mac_state_t_uart_tx_mac_state_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint12_t_uint12_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint14_t_uint14_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_0f18bc33.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_15baf9ef.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_193120d4.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_1a47ada0.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_1b734da6.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_1cc15a1b.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_1f86995a.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_2dd83b1d.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_33071957.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_377188ee.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_3b6e58f6.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_5e0e9452.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_616a4a0c.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_65609b6d.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_6c7643f5.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_801c3813.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_80d2db1b.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_84ba0e3a.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_8e73927f.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_a6a233d0.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_ab50972e.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_adc1beb1.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_c1a8be2c.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_d5667486.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_f55e052d.vhd ├── MUX_uint1_t_uint14_t_uint14_t_1CLK_f73c88b8.vhd ├── MUX_uint1_t_uint16_t_uint16_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint1_t_8_uint1_t_8_0CLK_de264c78.vhd ├── MUX_uint1_t_uint1_t_uint1_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_0bcb399a.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_0f1657d7.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_20830c27.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_24d10924.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_29a72679.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_357e765c.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_3cb0a365.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_3fc39e8d.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_4896d58f.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_4c0a2699.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_5d63f80d.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_6069a755.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_6311c908.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_6714f46f.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_7a9d37b4.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_90050f10.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_99330d44.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_9dd07569.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_a1537cdf.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_b301c8f8.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_bc6abea1.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_d539089d.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_de1df097.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_f964e092.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_fbfd5db3.vhd ├── MUX_uint1_t_uint1_t_uint1_t_1CLK_feab4394.vhd ├── MUX_uint1_t_uint21_t_uint21_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint22_t_uint22_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint23_t_uint23_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint2_t_uint2_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint32_t_uint32_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint36_t_uint36_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint3_t_uint3_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint4_t_uint4_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint5_t_uint5_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint8_t_uint8_t_0CLK_de264c78.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_0048e4e7.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_0865ab4c.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_16883554.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_1b6c3041.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_27b2954a.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_2f798d40.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_46e601b3.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_5a5c4ba6.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_60a0f81c.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_632d7826.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_95a2cf47.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_97dd14d7.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_9bab4883.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_a9a2737d.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_c45bae38.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_dd78bbdc.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_f7fa3caf.vhd ├── MUX_uint1_t_uint8_t_uint8_t_1CLK_fc57febd.vhd ├── UNARY_OP_NEGATE_float_8_14_t_0CLK_de264c78.vhd ├── UNARY_OP_NEGATE_float_8_14_t_1CLK_2e182bc4.vhd ├── UNARY_OP_NEGATE_int16_t_0CLK_23f04728.vhd ├── UNARY_OP_NOT_uint16_t_0CLK_de264c78.vhd ├── UNARY_OP_NOT_uint17_t_0CLK_de264c78.vhd ├── UNARY_OP_NOT_uint1_t_0CLK_de264c78.vhd ├── UNARY_OP_NOT_uint1_t_1CLK_27c1eb25.vhd ├── UNARY_OP_NOT_uint1_t_1CLK_2e182bc4.vhd ├── UNARY_OP_NOT_uint1_t_1CLK_5e0622e1.vhd ├── UNARY_OP_NOT_uint1_t_1CLK_63bf66d5.vhd ├── UNARY_OP_NOT_uint1_t_1CLK_76af35ca.vhd ├── UNARY_OP_NOT_uint1_t_1CLK_79701017.vhd ├── UNARY_OP_NOT_uint1_t_1CLK_7dfdaa5a.vhd ├── UNARY_OP_NOT_uint1_t_1CLK_86d91fcf.vhd ├── UNARY_OP_NOT_uint1_t_1CLK_92435ca2.vhd ├── UNARY_OP_NOT_uint1_t_1CLK_dda94d2c.vhd ├── UNARY_OP_NOT_uint1_t_1CLK_e123f016.vhd ├── UNARY_OP_NOT_uint22_t_0CLK_de264c78.vhd ├── UNARY_OP_NOT_uint23_t_0CLK_de264c78.vhd ├── background_color_5CLK_599ed504.vhd ├── background_color_5CLK_890b8db0.vhd ├── buttons_module_0CLK_380ecc95.vhd ├── c_structs_pkg.pkg.vhd ├── cast_ray_323CLK_f2c1ab37.vhd ├── cast_ray_nested_145CLK_96264b07.vhd ├── clk_cross_entities.vhd ├── color_max_1CLK_71e85ea2.vhd ├── color_select_0CLK_bd739e88.vhd ├── color_select_6CLK_20edd937.vhd ├── color_select_6CLK_94dcec9d.vhd ├── count0s_uint21_1CLK_63b787db.vhd ├── count0s_uint22_0CLK_0852fa80.vhd ├── dot_14CLK_df312d50.vhd ├── dot_15CLK_071a0e92.vhd ├── dot_15CLK_5e5aa800.vhd ├── dot_15CLK_71dbfa04.vhd ├── dot_15CLK_8a2d9ff3.vhd ├── dot_15CLK_972c4363.vhd ├── dvi_active_DEBUG_0CLK_de264c78.vhd ├── dvi_blue_DEBUG_0CLK_de264c78.vhd ├── dvi_green_DEBUG_0CLK_de264c78.vhd ├── dvi_red_DEBUG_0CLK_de264c78.vhd ├── dvi_x_DEBUG_0CLK_de264c78.vhd ├── dvi_y_DEBUG_0CLK_de264c78.vhd ├── ext_vga_0CLK_83e31706.vhd ├── fixed3_add_0CLK_f982eca9.vhd ├── fixed3_add_1CLK_ed170dad.vhd ├── fixed3_make_0CLK_b45f1687.vhd ├── fixed3_make_from_fixed_0CLK_b45f1687.vhd ├── fixed3_mul_5CLK_40e12b03.vhd ├── fixed3_mul_fixed_0CLK_4f51ce12.vhd ├── fixed3_mul_fixed_5CLK_c4855664.vhd ├── fixed3_sub_0CLK_f982eca9.vhd ├── fixed3_sub_1CLK_0feb4a39.vhd ├── fixed_abs_0CLK_d57786e6.vhd ├── fixed_abs_1CLK_6e07f203.vhd ├── fixed_abs_1CLK_a350f942.vhd ├── fixed_add_0CLK_6f2c5aad.vhd ├── fixed_add_1CLK_1ae6ac2b.vhd ├── fixed_add_1CLK_333e197e.vhd ├── fixed_add_1CLK_419e1dd2.vhd ├── fixed_add_1CLK_425d4a27.vhd ├── fixed_add_1CLK_4aa0a483.vhd ├── fixed_add_1CLK_abe8811b.vhd ├── fixed_gt_0CLK_380ecc95.vhd ├── fixed_is_negative_0CLK_23f04728.vhd ├── fixed_lt_1CLK_966fd94d.vhd ├── fixed_make_from_double_0CLK_38477f9e.vhd ├── fixed_make_from_float_2CLK_c0caf0ba.vhd ├── fixed_make_from_float_3CLK_2e839a7e.vhd ├── fixed_make_from_float_3CLK_ab228133.vhd ├── fixed_make_from_float_3CLK_d2470dc7.vhd ├── fixed_make_from_float_3CLK_d3afc3d1.vhd ├── fixed_make_from_float_3CLK_ddf017a3.vhd ├── fixed_make_from_int_0CLK_23f04728.vhd ├── fixed_make_from_short_0CLK_23f04728.vhd ├── fixed_mul_0CLK_5af1a430.vhd ├── fixed_mul_5CLK_70b28c19.vhd ├── fixed_shr_0CLK_6a3d4cae.vhd ├── fixed_shr_signed_char_0CLK_b5fe87e2.vhd ├── fixed_sub_0CLK_6f2c5aad.vhd ├── fixed_sub_1CLK_812f84af.vhd ├── fixed_sub_1CLK_adafaef6.vhd ├── fixed_sub_1CLK_edc1c8e1.vhd ├── fixed_to_float_3CLK_adafa2ea.vhd ├── fixed_to_float_4CLK_4a0c67e4.vhd ├── fixed_to_float_4CLK_9e6fce61.vhd ├── fixed_to_short_0CLK_380ecc95.vhd ├── float3_add_6CLK_561c4913.vhd ├── float3_mul_float_3CLK_0658e9f7.vhd ├── float3_mul_float_3CLK_16f88777.vhd ├── float3_mul_float_3CLK_201c64b4.vhd ├── float3_mul_float_3CLK_2dd35d55.vhd ├── float3_mul_float_3CLK_973cbba9.vhd ├── float3_mul_float_3CLK_f8bfc33d.vhd ├── float3_mul_float_3CLK_fa61dc19.vhd ├── float3_mul_float_3CLK_fb4628d5.vhd ├── float3_sub_6CLK_b52374ea.vhd ├── float3_sub_7CLK_10b65775.vhd ├── float3_sub_7CLK_4e79e5ee.vhd ├── float3_sub_7CLK_8157f68a.vhd ├── float3_sub_7CLK_e9ed9c34.vhd ├── float_fast_div_u_20CLK_66d884cf.vhd ├── float_fast_div_u_22CLK_a76cd96b.vhd ├── float_fast_reciprocal_u_17CLK_a45512a3.vhd ├── float_fast_reciprocal_u_19CLK_4f1e3aa0.vhd ├── float_rsqrt_12CLK_8189899b.vhd ├── float_rsqrt_13CLK_902e4797.vhd ├── float_rsqrt_14CLK_25a48b71.vhd ├── float_rsqrt_14CLK_3e419fbd.vhd ├── float_rsqrt_15CLK_3bd7a4c1.vhd ├── float_rsqrt_15CLK_d880de3c.vhd ├── float_rsqrt_16CLK_4cd4050a.vhd ├── float_rsqrt_16CLK_dce01ac2.vhd ├── float_rsqrt_17CLK_27cd1573.vhd ├── frame_clock_0CLK_de264c78.vhd ├── frame_clock_logic_0CLK_fc74e538.vhd ├── frame_logic_0CLK_3b45510c.vhd ├── full_update_0CLK_1832bdba.vhd ├── get_user_input_0CLK_380ecc95.vhd ├── global_wires_pkg.pkg.vhd ├── hash16_0CLK_b45f1687.vhd ├── hash16_2CLK_4e804713.vhd ├── hashf_2CLK_f336b191.vhd ├── hsync_DEBUG_0CLK_de264c78.vhd ├── int22_abs_0CLK_a5a1cd4e.vhd ├── int23_abs_1CLK_5e56e2f8.vhd ├── is_star_3CLK_12481b31.vhd ├── light_intensity_34CLK_55880f91.vhd ├── light_intensity_34CLK_f814a112.vhd ├── normalize_30CLK_dd685f50.vhd ├── normalize_33CLK_80c5594a.vhd ├── normalize_34CLK_495496ce.vhd ├── object_coord_to_float3_3CLK_9d26212c.vhd ├── object_coord_to_float3_4CLK_50bc2401.vhd ├── pixel_0CLK_de264c78.vhd ├── pixel_logic_368CLK_e22c77be.vhd ├── plane_effect_12CLK_917a7b84.vhd ├── plane_effect_13CLK_7362f855.vhd ├── plane_has_hole_0CLK_20e09e5a.vhd ├── plane_has_hole_2CLK_eec5c658.vhd ├── plane_has_hole_4CLK_d7ca7ae3.vhd ├── pmod_register_outputs_0CLK_25d197a7.vhd ├── ray_plane_intersect_53CLK_da3e346a.vhd ├── ray_plane_intersect_58CLK_dea4d88e.vhd ├── ray_sphere_intersect_101CLK_0beb6017.vhd ├── ray_sphere_intersect_109CLK_198e5ba5.vhd ├── reflect_26CLK_48b4560d.vhd ├── render_pixel_368CLK_a505fdde.vhd ├── render_pixel_internal_360CLK_987815b4.vhd ├── reset_state_0CLK_93ad8460.vhd ├── round16_0CLK_a193dced.vhd ├── round16_1CLK_9709124b.vhd ├── scene_colors_0CLK_5af1a430.vhd ├── shade_183CLK_f33a2411.vhd ├── sphere_effect_28CLK_ac0691c9.vhd ├── sphere_hit_46CLK_3095e505.vhd ├── sphere_hit_48CLK_c9304c7f.vhd ├── sqrt_14CLK_45ea7844.vhd ├── sqrt_20CLK_2303e114.vhd ├── top.v ├── top.vhd ├── uart_buttons_rx_0CLK_380ecc95.vhd ├── uart_buttons_tx_0CLK_380ecc95.vhd ├── uart_deserializer_0CLK_f2389995.vhd ├── uart_module_0CLK_380ecc95.vhd ├── uart_rx_mac_0CLK_b7ac2955.vhd ├── uart_serializer_0CLK_1ef564a5.vhd ├── uart_tx_mac_0CLK_1172510e.vhd ├── uint15_negate_0CLK_23f04728.vhd ├── uint21_negate_0CLK_23f04728.vhd ├── vga_timing_0CLK_62591bf8.vhd └── vsync_DEBUG_0CLK_de264c78.vhd /BUILD.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | DEBIAN 11 INSTALL 4 | ===================== 5 | 6 | #for "make sim" 7 | sudo apt install make g++ libsdl2 8 | 9 | #for "make gen" 10 | sudo apt install python3-dev python3-pip 11 | pip3 install cython 12 | sudo apt install software-properties-common #for add-apt-repository 13 | bash -c "$(wget -O - https://apt.llvm.org/llvm.sh)" #latest llvm 14 | pip3 install clang #not libclang!, it may need to create a symlink libclang-14.so in /usr/lib/x86_64-linux-gnu/ 15 | 16 | #for "make verilator" 17 | sudo apt install verilator gnat 18 | build & install yosys #make; sudo make install 19 | build & install ghdl #make; sudo make install 20 | build & install ghdl-yosys-plugin #make; sudo make install 21 | 22 | #for "make fullsynth" 23 | install vivado 24 | bash settings64.sh 25 | 26 | -------------------------------------------------------------------------------- /bitstreams/digilent_arty.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JulianKemmerer/PipelineC-Graphics/94e961b5d53479456771a9c320976270e88498c7/bitstreams/digilent_arty.bit -------------------------------------------------------------------------------- /bitstreams/digilent_arty_100t_1080p_12bpp_vga_pmodbc.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JulianKemmerer/PipelineC-Graphics/94e961b5d53479456771a9c320976270e88498c7/bitstreams/digilent_arty_100t_1080p_12bpp_vga_pmodbc.bit -------------------------------------------------------------------------------- /bitstreams/gsd_orangecrab.dfu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JulianKemmerer/PipelineC-Graphics/94e961b5d53479456771a9c320976270e88498c7/bitstreams/gsd_orangecrab.dfu -------------------------------------------------------------------------------- /c_compat.h: -------------------------------------------------------------------------------- 1 | // (C) 2021 Victor Suarez Rovere 2 | #ifndef __C_COMPAT_H__ 3 | #define __C_COMPAT_H__ 4 | 5 | #ifndef __cplusplus 6 | #define inline 7 | #define constexpr 8 | typedef unsigned char bool; 9 | #endif 10 | #define true 1 11 | #define false 0 12 | typedef signed char int8_t; 13 | typedef unsigned char uint8_t; 14 | typedef unsigned short uint16_t; 15 | typedef unsigned uint32_t; 16 | typedef short int16_t; 17 | typedef int int32_t; 18 | 19 | #include "float_type.h" 20 | 21 | #ifdef CCOMPILE 22 | #ifndef __PIPELINEC__ 23 | #ifndef CUSTOM_FLOAT_MANTISSA 24 | typedef union { struct { float_type x, y, z; }; struct { float_type r, g, b; }; } float3; 25 | #endif //CUSTOM_FLOAT_MANTISSA 26 | #else 27 | typedef struct { float_type x, y; } float2; //like extension vectors 28 | typedef struct float3 { float_type x, y, z; } float3; //like extension vectors 29 | typedef struct { float_type x, y, z, w; } float4; 30 | #endif 31 | 32 | 33 | inline /*constexpr*/ float3 float3_make_from_float(float_type a) { float3 r = { a, a, a }; return r; } 34 | inline /*constexpr*/ float3 float3_make_from_double(double a) { return float3_make_from_float(a); } 35 | inline /*constexpr*/ float3 float3_make(float_type x, float_type y, float_type z) { float3 r = {x, y, z }; return r; } //constructor 36 | 37 | #define float3_op(op) \ 38 | inline float3 float3_##op(float3 left, float3 right) { float3 r = { float_##op(left.x, right.x), float_##op(left.y, right.y), float_##op(left.z, right.z) }; return r; } 39 | #define float3_op_float(op) \ 40 | inline float3 float3_##op##_float(float3 left, float_type right) { float3 r = { float_##op(left.x, right), float_##op(left.y, right), float_##op(left.z, right) }; return r; } 41 | float3_op(add) 42 | float3_op(sub) 43 | float3_op(mul) 44 | float3_op_float(add) 45 | float3_op_float(sub) 46 | float3_op_float(mul) 47 | 48 | #else // CCOMPILE = false 49 | 50 | #ifndef CUSTOM_FLOAT_MANTISSA 51 | //typedef float vec2 __attribute__((vector_size(2*4))); 52 | //typedef float vec3 __attribute__((vector_size(3*4))); 53 | //typedef float vec4 __attribute__((vector_size(4*4))); 54 | typedef float_type __attribute__((ext_vector_type(2))) float2; 55 | typedef float_type __attribute__((ext_vector_type(3))) float3; 56 | typedef float_type __attribute__((ext_vector_type(4))) float4; 57 | #endif 58 | 59 | #endif //CCOMPILE 60 | 61 | #ifdef PARSING 62 | #define IN(t) t 63 | #define INOUT(t) t 64 | #else 65 | #define IN(t) const t& 66 | #define INOUT(t) t& 67 | #endif 68 | 69 | #define shift_t int6_t 70 | 71 | 72 | #endif //__C_COMPAT_H__ 73 | -------------------------------------------------------------------------------- /doc/Sphery-vs-Shapes.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/JulianKemmerer/PipelineC-Graphics/94e961b5d53479456771a9c320976270e88498c7/doc/Sphery-vs-Shapes.pdf -------------------------------------------------------------------------------- /fixed_div.h: -------------------------------------------------------------------------------- 1 | //optimized fixed point division 2 | // Copyright (C) 2022 Victor Suarez Rovere 3 | // inspired on // https://en.wikipedia.org/wiki/Division_algorithm 4 | 5 | #ifndef __FIXED_DIV_H__ 6 | #define __FIXED_DIV_H__ 7 | 8 | #ifdef CCOMPILE//__PIPELINEC__ 9 | inline fixed_basetype fixed_div_u(fixed_basetype N, fixed_basetype D) 10 | { 11 | fixed_basetype Q = 0; 12 | fixed_basetype R = 0; 13 | fixed_basetype RD = 0; 14 | uint32_t BIT; 15 | 16 | int6_t i; 17 | for(i=31; i>=0; i-=1) 18 | { 19 | BIT = ((uint32_t)1) << i; 20 | R = R << 1; 21 | if((N & (BIT>>FIXED_FRACTIONBITS)) != 0) 22 | R = R | 1; 23 | RD = R - D; 24 | if (((int32_t)RD >> 31) == 0) //checks sign bit 25 | { 26 | R = RD; 27 | Q = Q | BIT; 28 | } 29 | } 30 | return Q; 31 | } 32 | #ifdef __PIPELINEC__ 33 | #define __CFLEXHDL_SYNTH__ 34 | #warning move this to another location 35 | #endif 36 | #include "optimized_div.h" 37 | 38 | inline fixed_basetype fixed_div_newton(fixed_basetype a, fixed_basetype b) 39 | { 40 | #if 1 41 | return fixed16_div_aprox_32(a,b)>>(16-FIXED_FRACTIONBITS); 42 | #else 43 | return (a< 0 ? x * (1<(b)) 30 | #define float_eq(a, b) ((a)==(b)) 31 | #define float_neq(a, b) ((a)!=(b)) 32 | 33 | #define float_mul_double(a, b) float_mul(a, b) 34 | #define float_sub_double(a, b) float_sub(a, b) 35 | #define float_neq_double(a, b) float_neq(a, b) 36 | #define float_lt_double(a, b) float_lt(a, b) 37 | #define float_gt_double(a, b) float_gt(a, b) 38 | #define double_div_float(a, b) float_div(a, b) 39 | 40 | #include "custom_float.h" //may redefine float 41 | 42 | #ifndef __PIPELINEC__ 43 | typedef float float_type; 44 | #else 45 | #define float_type float 46 | #endif 47 | 48 | #endif //__FLOAT_TYPE_H__ 49 | -------------------------------------------------------------------------------- /fp_overloads.c: -------------------------------------------------------------------------------- 1 | float_8_14_t BIN_OP_INFERRED_MULT_float_8_14_t_float_8_14_t(float_8_14_t left, float_8_14_t right) 2 | { 3 | // Get mantissa exponent and sign for both 4 | // LEFT 5 | uint14_t x_mantissa; 6 | x_mantissa = float_8_14_t_13_0(left); 7 | uint9_t x_exponent_wide; 8 | x_exponent_wide = float_8_14_t_21_14(left); 9 | uint1_t x_sign; 10 | x_sign = float_8_14_t_22_22(left); 11 | // RIGHT 12 | uint14_t y_mantissa; 13 | y_mantissa = float_8_14_t_13_0(right); 14 | uint9_t y_exponent_wide; 15 | y_exponent_wide = float_8_14_t_21_14(right); 16 | uint1_t y_sign; 17 | y_sign = float_8_14_t_22_22(right); 18 | 19 | // Declare the output portions 20 | uint14_t z_mantissa; 21 | uint8_t z_exponent; 22 | uint1_t z_sign; 23 | 24 | // Sign 25 | z_sign = x_sign ^ y_sign; 26 | 27 | // Multiplication with infinity = inf 28 | if((x_exponent_wide==255) | (y_exponent_wide==255)) 29 | { 30 | z_exponent = 255; 31 | z_mantissa = 0; 32 | } 33 | // Multiplication with zero = zero 34 | else if((x_exponent_wide==0) | (y_exponent_wide==0)) 35 | { 36 | z_exponent = 0; 37 | z_mantissa = 0; 38 | z_sign = 0; 39 | } 40 | // Normal non zero|inf mult 41 | else 42 | { 43 | // Delcare intermediates 44 | uint1_t aux; 45 | uint15_t aux2_x; 46 | uint15_t aux2_y; 47 | uint30_t aux2; 48 | uint7_t BIAS; 49 | BIAS = 127; 50 | 51 | //aux2_x = uint1_uint14(1, x_mantissa); 52 | //aux2_y = uint1_uint14(1, y_mantissa); 53 | //uint16_t upper16 = mult15x15_upper16(aux2_x, aux2_y); 54 | //uint16_t upper16 = mult15x15_upper16_alt(aux2_x, aux2_y); 55 | uint16_t upper16 = mult14x14_upper14_alt(x_mantissa, y_mantissa) + x_mantissa + y_mantissa + 0x4000; 56 | aux = uint16_15_15(upper16); 57 | if(aux) 58 | { 59 | z_mantissa = uint16_14_1(upper16); 60 | } 61 | else 62 | { 63 | z_mantissa = uint16_13_0(upper16); 64 | } 65 | 66 | // calculate exponent in parts 67 | // do sequential unsigned adds and subs to avoid signed numbers for now 68 | // X and Y exponent are already 1 bit wider than needed 69 | // (0 & x_exponent) + (0 & y_exponent); 70 | uint9_t exponent_sum = x_exponent_wide + y_exponent_wide; 71 | exponent_sum = exponent_sum + aux; 72 | exponent_sum = exponent_sum - BIAS; 73 | 74 | // HACKY NOT CHECKING 75 | // if (exponent_sum(8)='1') then 76 | z_exponent = uint9_7_0(exponent_sum); 77 | } 78 | 79 | 80 | // Assemble output 81 | return float_uint8_uint14(z_sign, z_exponent, z_mantissa); 82 | } 83 | 84 | -------------------------------------------------------------------------------- /mandel.c: -------------------------------------------------------------------------------- 1 | #ifndef SHADER 2 | float dot2(vec2 a, vec2 b) { return a.x*b.x + a.y*b.y; } 3 | #endif 4 | 5 | #define ITER 12 6 | #define ESCAPE 4. 7 | #ifndef float_lshift 8 | #define float_lshift float_shift 9 | #endif 10 | 11 | float mandelbrot(vec2 c) 12 | { 13 | bool b = true; 14 | uint16_t n = 2; 15 | #if 0 16 | vec2 z = vec2(0.); 17 | for(uint16_t i=0; i> mandel_shift; 42 | Zii = (Zi * Zi) >> mandel_shift; 43 | b = b && Zrr + Zii <= norm_max; 44 | n += uint16_t(b); 45 | if(b) 46 | { 47 | Zri = (Zr * Zi) >> (mandel_shift - 1); 48 | Zr = Cr + Zrr - Zii; 49 | Zi = Ci + Zri; 50 | } 51 | } 52 | float sl = float(n) - log2(log2(float(Zrr+Zii))-float(mandel_shift)); 53 | #endif 54 | return b ? 0.: sl/float(ITER); 55 | } 56 | 57 | color render_pixel_internal(screen_coord_t x, screen_coord_t y) 58 | { 59 | vec2 v = vec2(x, y); 60 | return vec3(mandelbrot(v*4.)); 61 | } 62 | 63 | struct scene_t { uint32_t frame; }; 64 | struct full_state_t { scene_t scene; }; 65 | -------------------------------------------------------------------------------- /pattern_gen.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | Pattern generator 3 | Copyright (C) 2022 Victor Suarez Rovere 4 | */ 5 | 6 | #include "tr.h" 7 | full_state_t state; 8 | 9 | 10 | full_state_t full_update(INOUT(full_state_t) state, bool reset, bool button_state) 11 | { 12 | state.scene.frame = state.scene.frame + 1; 13 | state.won = button_state; 14 | return state; 15 | } 16 | 17 | inline pixel_t render_pixel(uint16_t i, uint16_t j) 18 | { 19 | uint16_t frame = state.scene.frame; 20 | bool button = state.won; 21 | 22 | pixel_t pix; 23 | pix.r = button ? i + j : i - j; 24 | pix.g = i ^ (j + frame); 25 | pix.b = frame; 26 | return pix; 27 | } 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /pipelinec_compat.h: -------------------------------------------------------------------------------- 1 | #ifndef __PIPELINEC_COMPAT_H_ 2 | #define __PIPELINEC_COMPAT_H_ 3 | 4 | #include "c_compat.h" 5 | 6 | #ifdef __PIPELINEC__ 7 | 8 | #define float_type float 9 | // Float is variable size 10 | #include "float_e_m_t_helper.h" 11 | #define inversesqrt float_rsqrt 12 | // Shift is built in 13 | #define float_shift(x,shift) ((x)<<(shift)) 14 | 15 | #define double float 16 | #else 17 | typedef uint16_t uint12_t; 18 | typedef uint16_t uint9_t, uint10_t; 19 | typedef uint8_t uint1_t, uint2_t; 20 | typedef uint8_t uint3_t, uint5_t, uint6_t; 21 | typedef int32_t int20_t, int21_t, int22_t, int26_t; 22 | typedef int16_t int9_t, int12_t; 23 | typedef int8_t int2_t, int6_t; 24 | 25 | 26 | #endif 27 | #endif //__PIPELINEC_COMPAT_H_ 28 | -------------------------------------------------------------------------------- /pipelinec_float_type.h: -------------------------------------------------------------------------------- 1 | #ifndef __PIPELINEC_FLOAT_TYPE_H__ 2 | #define __PIPELINEC_FLOAT_TYPE_H__ 3 | 4 | #ifndef float_mul 5 | float float_mul(float a, float b) { return a*b; } 6 | #endif 7 | #ifndef float_add 8 | float float_add(float a, float b) { return a+b; } 9 | #endif 10 | #ifndef float_sub 11 | float float_sub(float a, float b) { return a-b; } 12 | #endif 13 | #ifndef float_div 14 | float float_div(float a, float b) { return a/b; } 15 | #endif 16 | 17 | #endif //__PIPELINEC_FLOAT_TYPE_H__ 18 | -------------------------------------------------------------------------------- /pipelinec_litex.c: -------------------------------------------------------------------------------- 1 | #define LITEX_INTEGRATION 2 | #include "pipelinec_app.c" 3 | -------------------------------------------------------------------------------- /power.cpp: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2022 Victor Suarez Rovere 2 | // Code portions Copyright (c) 2018-2020 Ondrej Čerman with MIT License 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | 9 | #define SYSFS_DIR_CPUS "/sys/devices/system/cpu" 10 | 11 | 12 | static int msr_file; 13 | 14 | static int open_msr(short devid) { 15 | char msr_path[20]; 16 | sprintf(msr_path, "/dev/cpu/%d/msr", devid); 17 | return open(msr_path, O_RDONLY); 18 | } 19 | 20 | static bool read_msr(int file, unsigned index, unsigned long *data) { 21 | if (file < 0) 22 | return false; 23 | 24 | return pread(file, data, sizeof *data, index) == sizeof *data; 25 | } 26 | 27 | double get_energy_unit() { 28 | unsigned long data; 29 | // AMD OSRR: page 139 - MSRC001_0299 30 | if (!read_msr(msr_file, 0xC0010299, &data)) 31 | return 0.0; 32 | 33 | return pow(1.0/2.0, (double)((data >> 8) & 0x1F)); 34 | } 35 | 36 | unsigned long get_package_energy() { 37 | unsigned long data; 38 | // AMD OSRR: page 139 - MSRC001_029B 39 | if (!read_msr(msr_file, 0xC001029B, &data)) 40 | return 0; 41 | 42 | return data; 43 | } 44 | 45 | bool power_init() 46 | { 47 | const short cpuid = 0; 48 | msr_file = open_msr(cpuid); 49 | return msr_file >= 0; 50 | } 51 | 52 | #ifndef POWER_BENCH 53 | int main() 54 | { 55 | 56 | if(!power_init()) 57 | { 58 | perror("Cannot open MSR file. Try using sudo and have the msr module loaded. Error"); 59 | exit(1); 60 | } 61 | 62 | double unit = get_energy_unit(); 63 | unsigned long e0 = get_package_energy(); 64 | 65 | const unsigned interval_us = 500*1000; 66 | for(;;) 67 | { 68 | usleep(interval_us); 69 | unsigned long e1 = get_package_energy(); 70 | long energy = e1 - e0; 71 | e0 = e1; 72 | printf("package energy: %f watts\n", energy*unit/(interval_us*1e-6)); 73 | } 74 | return 0; 75 | } 76 | #endif 77 | -------------------------------------------------------------------------------- /typesperf.h: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022 Victor Suarez Rovere 2 | // this is part of the CflexHDL project 3 | 4 | #ifndef __TYPES_PERF_H 5 | #define __TYPES_PERF_H 6 | 7 | #ifndef PARSING 8 | //#define FP_DEBUG 9 | #endif 10 | 11 | #ifdef FP_DEBUG 12 | //see: cflexhdl cfloatops.h 13 | struct perfcount 14 | { 15 | int mul, add, div, sub, cmp, unary_minus, inttofp, fptoint, fmuladd; 16 | int fptofix, fixtofp, fixtoint, inttofix; 17 | perfcount() { clear(); mul = -1; } 18 | 19 | void clear(); 20 | void dump(); 21 | }; 22 | 23 | #define LOG_PERF(m) ++perf->m 24 | #define LOG_PERF2(p, m) ++(p)->m 25 | #else 26 | #define LOG_PERF(m) 27 | #define LOG_PERF2(p, m) 0 28 | #endif 29 | 30 | 31 | #endif // __TYPES_PERF_H 32 | 33 | -------------------------------------------------------------------------------- /uart_buttons_demo.c: -------------------------------------------------------------------------------- 1 | // gcc uart_buttons_demo.c -o uart_buttons_demo -I ../PipelineC 2 | // sudo ./uart_buttons_demo 3 | 4 | // 'Software' side of uart pipelinec helper include 5 | #include "uart/uart_sw.c" 6 | 7 | // Init + do some work + close 8 | int main(int argc, char **argv) 9 | { 10 | // Settings 11 | int n_sec = 20; 12 | int n_frames = n_sec * 60; 13 | char file_name[] = "buttons-recorded.bin"; 14 | 15 | // Init uart to/from FPGA 16 | init_uart(); 17 | 18 | // Open output file 19 | FILE * fp = fopen(file_name, "wb"); 20 | if(fp == NULL) 21 | { 22 | printf("Open error!"); 23 | exit(-1); 24 | } 25 | 26 | printf("Recording...\n"); 27 | 28 | // Read N frames of data and write to file 29 | int frame = 0; 30 | uint8_t the_byte; 31 | while(frame < n_frames) 32 | { 33 | // Read 1 byte 34 | uart_read(&the_byte, 1); 35 | // Write 1 byte 36 | size_t n_bytes = fwrite(&the_byte, 1, 1, fp); 37 | if(n_bytes != 1) 38 | { 39 | printf("Write error!"); 40 | exit(-1); 41 | } 42 | frame++; 43 | } 44 | 45 | // Close output file 46 | fclose(fp); 47 | 48 | // Close uart to/from FPGA 49 | close_uart(); 50 | 51 | printf("Done...\n"); 52 | } 53 | 54 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/BIN_OP_AND_uint1_t_uint1_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity BIN_OP_AND_uint1_t_uint1_t_0CLK_de264c78 is 15 | port( 16 | left : in unsigned(0 downto 0); 17 | right : in unsigned(0 downto 0); 18 | return_output : out unsigned(0 downto 0)); 19 | end BIN_OP_AND_uint1_t_uint1_t_0CLK_de264c78; 20 | architecture arch of BIN_OP_AND_uint1_t_uint1_t_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | 26 | -- One struct to represent this modules variables 27 | type raw_hdl_variables_t is record 28 | -- All of the wires in function 29 | 30 | left_resized : unsigned(0 downto 0); 31 | right_resized : unsigned(0 downto 0); 32 | return_output : unsigned(0 downto 0); 33 | right : unsigned(0 downto 0); 34 | left : unsigned(0 downto 0); 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | left, 48 | right) 49 | is 50 | -- Read and write variables to do register transfers per clock 51 | -- from the previous to next stage 52 | variable read_pipe : raw_hdl_variables_t; 53 | variable write_pipe : raw_hdl_variables_t; 54 | 55 | -- This modules self pipeline registers read once per clock 56 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 57 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | begin 59 | 60 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 61 | -- LATENCY=0 is combinational Logic 62 | for STAGE in 0 to PIPELINE_LATENCY loop 63 | -- Input to first stage are inputs to function 64 | if STAGE=0 then 65 | -- Mux in inputs 66 | read_pipe.left := left; 67 | read_pipe.right := right; 68 | else 69 | -- Default read from previous stage 70 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 71 | end if; 72 | -- Default write contents of previous stage 73 | write_pipe := read_pipe; 74 | 75 | 76 | if STAGE = 0 then 77 | write_pipe.left_resized := resize(write_pipe.left, 1); 78 | write_pipe.right_resized := resize(write_pipe.right, 1); 79 | write_pipe.return_output := write_pipe.left_resized and write_pipe.right_resized; 80 | end if; 81 | -- Write to stage reg 82 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 83 | end loop; 84 | 85 | -- Last stage of pipeline return wire to return port/reg 86 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 87 | end process; 88 | 89 | end arch; 90 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/BIN_OP_AND_uint8_t_uint6_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity BIN_OP_AND_uint8_t_uint6_t_0CLK_de264c78 is 15 | port( 16 | left : in unsigned(7 downto 0); 17 | right : in unsigned(5 downto 0); 18 | return_output : out unsigned(7 downto 0)); 19 | end BIN_OP_AND_uint8_t_uint6_t_0CLK_de264c78; 20 | architecture arch of BIN_OP_AND_uint8_t_uint6_t_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | 26 | -- One struct to represent this modules variables 27 | type raw_hdl_variables_t is record 28 | -- All of the wires in function 29 | 30 | left_resized : unsigned(7 downto 0); 31 | right_resized : unsigned(7 downto 0); 32 | return_output : unsigned(7 downto 0); 33 | right : unsigned(5 downto 0); 34 | left : unsigned(7 downto 0); 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | left, 48 | right) 49 | is 50 | -- Read and write variables to do register transfers per clock 51 | -- from the previous to next stage 52 | variable read_pipe : raw_hdl_variables_t; 53 | variable write_pipe : raw_hdl_variables_t; 54 | 55 | -- This modules self pipeline registers read once per clock 56 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 57 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | begin 59 | 60 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 61 | -- LATENCY=0 is combinational Logic 62 | for STAGE in 0 to PIPELINE_LATENCY loop 63 | -- Input to first stage are inputs to function 64 | if STAGE=0 then 65 | -- Mux in inputs 66 | read_pipe.left := left; 67 | read_pipe.right := right; 68 | else 69 | -- Default read from previous stage 70 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 71 | end if; 72 | -- Default write contents of previous stage 73 | write_pipe := read_pipe; 74 | 75 | 76 | if STAGE = 0 then 77 | write_pipe.left_resized := resize(write_pipe.left, 8); 78 | write_pipe.right_resized := resize(write_pipe.right, 8); 79 | write_pipe.return_output := write_pipe.left_resized and write_pipe.right_resized; 80 | end if; 81 | -- Write to stage reg 82 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 83 | end loop; 84 | 85 | -- Last stage of pipeline return wire to return port/reg 86 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 87 | end process; 88 | 89 | end arch; 90 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/BIN_OP_INFERRED_MULT_int22_t_int22_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity BIN_OP_INFERRED_MULT_int22_t_int22_t_0CLK_de264c78 is 15 | port( 16 | left : in signed(21 downto 0); 17 | right : in signed(21 downto 0); 18 | return_output : out signed(43 downto 0)); 19 | end BIN_OP_INFERRED_MULT_int22_t_int22_t_0CLK_de264c78; 20 | architecture arch of BIN_OP_INFERRED_MULT_int22_t_int22_t_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | 26 | -- One struct to represent this modules variables 27 | type raw_hdl_variables_t is record 28 | -- All of the wires in function 29 | 30 | left : signed(21 downto 0); 31 | right : signed(21 downto 0); 32 | return_output : signed(43 downto 0); 33 | end record; 34 | 35 | -- Type for this modules register pipeline 36 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 37 | 38 | begin 39 | 40 | 41 | 42 | -- Combinatorial process for pipeline stages 43 | process ( 44 | -- Inputs 45 | left, 46 | right) 47 | is 48 | -- Read and write variables to do register transfers per clock 49 | -- from the previous to next stage 50 | variable read_pipe : raw_hdl_variables_t; 51 | variable write_pipe : raw_hdl_variables_t; 52 | 53 | -- This modules self pipeline registers read once per clock 54 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 55 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 56 | begin 57 | 58 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 59 | -- LATENCY=0 is combinational Logic 60 | for STAGE in 0 to PIPELINE_LATENCY loop 61 | -- Input to first stage are inputs to function 62 | if STAGE=0 then 63 | -- Mux in inputs 64 | read_pipe.left := left; 65 | read_pipe.right := right; 66 | else 67 | -- Default read from previous stage 68 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 69 | end if; 70 | -- Default write contents of previous stage 71 | write_pipe := read_pipe; 72 | 73 | 74 | if STAGE = 0 then 75 | write_pipe.return_output := write_pipe.left * write_pipe.right; 76 | end if; 77 | -- Write to stage reg 78 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 79 | end loop; 80 | 81 | -- Last stage of pipeline return wire to return port/reg 82 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 83 | end process; 84 | 85 | end arch; 86 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/BIN_OP_INFERRED_MULT_uint16_t_uint16_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity BIN_OP_INFERRED_MULT_uint16_t_uint16_t_0CLK_de264c78 is 15 | port( 16 | left : in unsigned(15 downto 0); 17 | right : in unsigned(15 downto 0); 18 | return_output : out unsigned(31 downto 0)); 19 | end BIN_OP_INFERRED_MULT_uint16_t_uint16_t_0CLK_de264c78; 20 | architecture arch of BIN_OP_INFERRED_MULT_uint16_t_uint16_t_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | 26 | -- One struct to represent this modules variables 27 | type raw_hdl_variables_t is record 28 | -- All of the wires in function 29 | 30 | left : unsigned(15 downto 0); 31 | right : unsigned(15 downto 0); 32 | return_output : unsigned(31 downto 0); 33 | end record; 34 | 35 | -- Type for this modules register pipeline 36 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 37 | 38 | begin 39 | 40 | 41 | 42 | -- Combinatorial process for pipeline stages 43 | process ( 44 | -- Inputs 45 | left, 46 | right) 47 | is 48 | -- Read and write variables to do register transfers per clock 49 | -- from the previous to next stage 50 | variable read_pipe : raw_hdl_variables_t; 51 | variable write_pipe : raw_hdl_variables_t; 52 | 53 | -- This modules self pipeline registers read once per clock 54 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 55 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 56 | begin 57 | 58 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 59 | -- LATENCY=0 is combinational Logic 60 | for STAGE in 0 to PIPELINE_LATENCY loop 61 | -- Input to first stage are inputs to function 62 | if STAGE=0 then 63 | -- Mux in inputs 64 | read_pipe.left := left; 65 | read_pipe.right := right; 66 | else 67 | -- Default read from previous stage 68 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 69 | end if; 70 | -- Default write contents of previous stage 71 | write_pipe := read_pipe; 72 | 73 | 74 | if STAGE = 0 then 75 | write_pipe.return_output := write_pipe.left * write_pipe.right; 76 | end if; 77 | -- Write to stage reg 78 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 79 | end loop; 80 | 81 | -- Last stage of pipeline return wire to return port/reg 82 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 83 | end process; 84 | 85 | end arch; 86 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/BIN_OP_OR_uint1_t_uint1_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity BIN_OP_OR_uint1_t_uint1_t_0CLK_de264c78 is 15 | port( 16 | left : in unsigned(0 downto 0); 17 | right : in unsigned(0 downto 0); 18 | return_output : out unsigned(0 downto 0)); 19 | end BIN_OP_OR_uint1_t_uint1_t_0CLK_de264c78; 20 | architecture arch of BIN_OP_OR_uint1_t_uint1_t_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | 26 | -- One struct to represent this modules variables 27 | type raw_hdl_variables_t is record 28 | -- All of the wires in function 29 | 30 | left_resized : unsigned(0 downto 0); 31 | right_resized : unsigned(0 downto 0); 32 | return_output : unsigned(0 downto 0); 33 | right : unsigned(0 downto 0); 34 | left : unsigned(0 downto 0); 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | left, 48 | right) 49 | is 50 | -- Read and write variables to do register transfers per clock 51 | -- from the previous to next stage 52 | variable read_pipe : raw_hdl_variables_t; 53 | variable write_pipe : raw_hdl_variables_t; 54 | 55 | -- This modules self pipeline registers read once per clock 56 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 57 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | begin 59 | 60 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 61 | -- LATENCY=0 is combinational Logic 62 | for STAGE in 0 to PIPELINE_LATENCY loop 63 | -- Input to first stage are inputs to function 64 | if STAGE=0 then 65 | -- Mux in inputs 66 | read_pipe.left := left; 67 | read_pipe.right := right; 68 | else 69 | -- Default read from previous stage 70 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 71 | end if; 72 | -- Default write contents of previous stage 73 | write_pipe := read_pipe; 74 | 75 | 76 | if STAGE = 0 then 77 | write_pipe.left_resized := resize(write_pipe.left, 1); 78 | write_pipe.right_resized := resize(write_pipe.right, 1); 79 | write_pipe.return_output := write_pipe.left_resized or write_pipe.right_resized; 80 | end if; 81 | -- Write to stage reg 82 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 83 | end loop; 84 | 85 | -- Last stage of pipeline return wire to return port/reg 86 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 87 | end process; 88 | 89 | end arch; 90 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/BIN_OP_OR_uint1_t_uint2_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity BIN_OP_OR_uint1_t_uint2_t_0CLK_de264c78 is 15 | port( 16 | left : in unsigned(0 downto 0); 17 | right : in unsigned(1 downto 0); 18 | return_output : out unsigned(1 downto 0)); 19 | end BIN_OP_OR_uint1_t_uint2_t_0CLK_de264c78; 20 | architecture arch of BIN_OP_OR_uint1_t_uint2_t_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | 26 | -- One struct to represent this modules variables 27 | type raw_hdl_variables_t is record 28 | -- All of the wires in function 29 | 30 | left_resized : unsigned(1 downto 0); 31 | right_resized : unsigned(1 downto 0); 32 | return_output : unsigned(1 downto 0); 33 | right : unsigned(1 downto 0); 34 | left : unsigned(0 downto 0); 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | left, 48 | right) 49 | is 50 | -- Read and write variables to do register transfers per clock 51 | -- from the previous to next stage 52 | variable read_pipe : raw_hdl_variables_t; 53 | variable write_pipe : raw_hdl_variables_t; 54 | 55 | -- This modules self pipeline registers read once per clock 56 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 57 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | begin 59 | 60 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 61 | -- LATENCY=0 is combinational Logic 62 | for STAGE in 0 to PIPELINE_LATENCY loop 63 | -- Input to first stage are inputs to function 64 | if STAGE=0 then 65 | -- Mux in inputs 66 | read_pipe.left := left; 67 | read_pipe.right := right; 68 | else 69 | -- Default read from previous stage 70 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 71 | end if; 72 | -- Default write contents of previous stage 73 | write_pipe := read_pipe; 74 | 75 | 76 | if STAGE = 0 then 77 | write_pipe.left_resized := resize(write_pipe.left, 2); 78 | write_pipe.right_resized := resize(write_pipe.right, 2); 79 | write_pipe.return_output := write_pipe.left_resized or write_pipe.right_resized; 80 | end if; 81 | -- Write to stage reg 82 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 83 | end loop; 84 | 85 | -- Last stage of pipeline return wire to return port/reg 86 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 87 | end process; 88 | 89 | end arch; 90 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/BIN_OP_OR_uint2_t_uint3_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity BIN_OP_OR_uint2_t_uint3_t_0CLK_de264c78 is 15 | port( 16 | left : in unsigned(1 downto 0); 17 | right : in unsigned(2 downto 0); 18 | return_output : out unsigned(2 downto 0)); 19 | end BIN_OP_OR_uint2_t_uint3_t_0CLK_de264c78; 20 | architecture arch of BIN_OP_OR_uint2_t_uint3_t_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | 26 | -- One struct to represent this modules variables 27 | type raw_hdl_variables_t is record 28 | -- All of the wires in function 29 | 30 | left_resized : unsigned(2 downto 0); 31 | right_resized : unsigned(2 downto 0); 32 | return_output : unsigned(2 downto 0); 33 | right : unsigned(2 downto 0); 34 | left : unsigned(1 downto 0); 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | left, 48 | right) 49 | is 50 | -- Read and write variables to do register transfers per clock 51 | -- from the previous to next stage 52 | variable read_pipe : raw_hdl_variables_t; 53 | variable write_pipe : raw_hdl_variables_t; 54 | 55 | -- This modules self pipeline registers read once per clock 56 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 57 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | begin 59 | 60 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 61 | -- LATENCY=0 is combinational Logic 62 | for STAGE in 0 to PIPELINE_LATENCY loop 63 | -- Input to first stage are inputs to function 64 | if STAGE=0 then 65 | -- Mux in inputs 66 | read_pipe.left := left; 67 | read_pipe.right := right; 68 | else 69 | -- Default read from previous stage 70 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 71 | end if; 72 | -- Default write contents of previous stage 73 | write_pipe := read_pipe; 74 | 75 | 76 | if STAGE = 0 then 77 | write_pipe.left_resized := resize(write_pipe.left, 3); 78 | write_pipe.right_resized := resize(write_pipe.right, 3); 79 | write_pipe.return_output := write_pipe.left_resized or write_pipe.right_resized; 80 | end if; 81 | -- Write to stage reg 82 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 83 | end loop; 84 | 85 | -- Last stage of pipeline return wire to return port/reg 86 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 87 | end process; 88 | 89 | end arch; 90 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/BIN_OP_OR_uint3_t_uint3_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity BIN_OP_OR_uint3_t_uint3_t_0CLK_de264c78 is 15 | port( 16 | left : in unsigned(2 downto 0); 17 | right : in unsigned(2 downto 0); 18 | return_output : out unsigned(2 downto 0)); 19 | end BIN_OP_OR_uint3_t_uint3_t_0CLK_de264c78; 20 | architecture arch of BIN_OP_OR_uint3_t_uint3_t_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | 26 | -- One struct to represent this modules variables 27 | type raw_hdl_variables_t is record 28 | -- All of the wires in function 29 | 30 | left_resized : unsigned(2 downto 0); 31 | right_resized : unsigned(2 downto 0); 32 | return_output : unsigned(2 downto 0); 33 | right : unsigned(2 downto 0); 34 | left : unsigned(2 downto 0); 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | left, 48 | right) 49 | is 50 | -- Read and write variables to do register transfers per clock 51 | -- from the previous to next stage 52 | variable read_pipe : raw_hdl_variables_t; 53 | variable write_pipe : raw_hdl_variables_t; 54 | 55 | -- This modules self pipeline registers read once per clock 56 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 57 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | begin 59 | 60 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 61 | -- LATENCY=0 is combinational Logic 62 | for STAGE in 0 to PIPELINE_LATENCY loop 63 | -- Input to first stage are inputs to function 64 | if STAGE=0 then 65 | -- Mux in inputs 66 | read_pipe.left := left; 67 | read_pipe.right := right; 68 | else 69 | -- Default read from previous stage 70 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 71 | end if; 72 | -- Default write contents of previous stage 73 | write_pipe := read_pipe; 74 | 75 | 76 | if STAGE = 0 then 77 | write_pipe.left_resized := resize(write_pipe.left, 3); 78 | write_pipe.right_resized := resize(write_pipe.right, 3); 79 | write_pipe.return_output := write_pipe.left_resized or write_pipe.right_resized; 80 | end if; 81 | -- Write to stage reg 82 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 83 | end loop; 84 | 85 | -- Last stage of pipeline return wire to return port/reg 86 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 87 | end process; 88 | 89 | end arch; 90 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/BIN_OP_OR_uint3_t_uint4_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity BIN_OP_OR_uint3_t_uint4_t_0CLK_de264c78 is 15 | port( 16 | left : in unsigned(2 downto 0); 17 | right : in unsigned(3 downto 0); 18 | return_output : out unsigned(3 downto 0)); 19 | end BIN_OP_OR_uint3_t_uint4_t_0CLK_de264c78; 20 | architecture arch of BIN_OP_OR_uint3_t_uint4_t_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | 26 | -- One struct to represent this modules variables 27 | type raw_hdl_variables_t is record 28 | -- All of the wires in function 29 | 30 | left_resized : unsigned(3 downto 0); 31 | right_resized : unsigned(3 downto 0); 32 | return_output : unsigned(3 downto 0); 33 | right : unsigned(3 downto 0); 34 | left : unsigned(2 downto 0); 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | left, 48 | right) 49 | is 50 | -- Read and write variables to do register transfers per clock 51 | -- from the previous to next stage 52 | variable read_pipe : raw_hdl_variables_t; 53 | variable write_pipe : raw_hdl_variables_t; 54 | 55 | -- This modules self pipeline registers read once per clock 56 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 57 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | begin 59 | 60 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 61 | -- LATENCY=0 is combinational Logic 62 | for STAGE in 0 to PIPELINE_LATENCY loop 63 | -- Input to first stage are inputs to function 64 | if STAGE=0 then 65 | -- Mux in inputs 66 | read_pipe.left := left; 67 | read_pipe.right := right; 68 | else 69 | -- Default read from previous stage 70 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 71 | end if; 72 | -- Default write contents of previous stage 73 | write_pipe := read_pipe; 74 | 75 | 76 | if STAGE = 0 then 77 | write_pipe.left_resized := resize(write_pipe.left, 4); 78 | write_pipe.right_resized := resize(write_pipe.right, 4); 79 | write_pipe.return_output := write_pipe.left_resized or write_pipe.right_resized; 80 | end if; 81 | -- Write to stage reg 82 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 83 | end loop; 84 | 85 | -- Last stage of pipeline return wire to return port/reg 86 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 87 | end process; 88 | 89 | end arch; 90 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/BIN_OP_OR_uint4_t_uint4_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity BIN_OP_OR_uint4_t_uint4_t_0CLK_de264c78 is 15 | port( 16 | left : in unsigned(3 downto 0); 17 | right : in unsigned(3 downto 0); 18 | return_output : out unsigned(3 downto 0)); 19 | end BIN_OP_OR_uint4_t_uint4_t_0CLK_de264c78; 20 | architecture arch of BIN_OP_OR_uint4_t_uint4_t_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | 26 | -- One struct to represent this modules variables 27 | type raw_hdl_variables_t is record 28 | -- All of the wires in function 29 | 30 | left_resized : unsigned(3 downto 0); 31 | right_resized : unsigned(3 downto 0); 32 | return_output : unsigned(3 downto 0); 33 | right : unsigned(3 downto 0); 34 | left : unsigned(3 downto 0); 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | left, 48 | right) 49 | is 50 | -- Read and write variables to do register transfers per clock 51 | -- from the previous to next stage 52 | variable read_pipe : raw_hdl_variables_t; 53 | variable write_pipe : raw_hdl_variables_t; 54 | 55 | -- This modules self pipeline registers read once per clock 56 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 57 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | begin 59 | 60 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 61 | -- LATENCY=0 is combinational Logic 62 | for STAGE in 0 to PIPELINE_LATENCY loop 63 | -- Input to first stage are inputs to function 64 | if STAGE=0 then 65 | -- Mux in inputs 66 | read_pipe.left := left; 67 | read_pipe.right := right; 68 | else 69 | -- Default read from previous stage 70 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 71 | end if; 72 | -- Default write contents of previous stage 73 | write_pipe := read_pipe; 74 | 75 | 76 | if STAGE = 0 then 77 | write_pipe.left_resized := resize(write_pipe.left, 4); 78 | write_pipe.right_resized := resize(write_pipe.right, 4); 79 | write_pipe.return_output := write_pipe.left_resized or write_pipe.right_resized; 80 | end if; 81 | -- Write to stage reg 82 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 83 | end loop; 84 | 85 | -- Last stage of pipeline return wire to return port/reg 86 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 87 | end process; 88 | 89 | end arch; 90 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/BIN_OP_OR_uint4_t_uint5_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity BIN_OP_OR_uint4_t_uint5_t_0CLK_de264c78 is 15 | port( 16 | left : in unsigned(3 downto 0); 17 | right : in unsigned(4 downto 0); 18 | return_output : out unsigned(4 downto 0)); 19 | end BIN_OP_OR_uint4_t_uint5_t_0CLK_de264c78; 20 | architecture arch of BIN_OP_OR_uint4_t_uint5_t_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | 26 | -- One struct to represent this modules variables 27 | type raw_hdl_variables_t is record 28 | -- All of the wires in function 29 | 30 | left_resized : unsigned(4 downto 0); 31 | right_resized : unsigned(4 downto 0); 32 | return_output : unsigned(4 downto 0); 33 | right : unsigned(4 downto 0); 34 | left : unsigned(3 downto 0); 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | left, 48 | right) 49 | is 50 | -- Read and write variables to do register transfers per clock 51 | -- from the previous to next stage 52 | variable read_pipe : raw_hdl_variables_t; 53 | variable write_pipe : raw_hdl_variables_t; 54 | 55 | -- This modules self pipeline registers read once per clock 56 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 57 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | begin 59 | 60 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 61 | -- LATENCY=0 is combinational Logic 62 | for STAGE in 0 to PIPELINE_LATENCY loop 63 | -- Input to first stage are inputs to function 64 | if STAGE=0 then 65 | -- Mux in inputs 66 | read_pipe.left := left; 67 | read_pipe.right := right; 68 | else 69 | -- Default read from previous stage 70 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 71 | end if; 72 | -- Default write contents of previous stage 73 | write_pipe := read_pipe; 74 | 75 | 76 | if STAGE = 0 then 77 | write_pipe.left_resized := resize(write_pipe.left, 5); 78 | write_pipe.right_resized := resize(write_pipe.right, 5); 79 | write_pipe.return_output := write_pipe.left_resized or write_pipe.right_resized; 80 | end if; 81 | -- Write to stage reg 82 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 83 | end loop; 84 | 85 | -- Last stage of pipeline return wire to return port/reg 86 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 87 | end process; 88 | 89 | end arch; 90 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/BIN_OP_OR_uint5_t_uint5_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity BIN_OP_OR_uint5_t_uint5_t_0CLK_de264c78 is 15 | port( 16 | left : in unsigned(4 downto 0); 17 | right : in unsigned(4 downto 0); 18 | return_output : out unsigned(4 downto 0)); 19 | end BIN_OP_OR_uint5_t_uint5_t_0CLK_de264c78; 20 | architecture arch of BIN_OP_OR_uint5_t_uint5_t_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | 26 | -- One struct to represent this modules variables 27 | type raw_hdl_variables_t is record 28 | -- All of the wires in function 29 | 30 | left_resized : unsigned(4 downto 0); 31 | right_resized : unsigned(4 downto 0); 32 | return_output : unsigned(4 downto 0); 33 | right : unsigned(4 downto 0); 34 | left : unsigned(4 downto 0); 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | left, 48 | right) 49 | is 50 | -- Read and write variables to do register transfers per clock 51 | -- from the previous to next stage 52 | variable read_pipe : raw_hdl_variables_t; 53 | variable write_pipe : raw_hdl_variables_t; 54 | 55 | -- This modules self pipeline registers read once per clock 56 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 57 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | begin 59 | 60 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 61 | -- LATENCY=0 is combinational Logic 62 | for STAGE in 0 to PIPELINE_LATENCY loop 63 | -- Input to first stage are inputs to function 64 | if STAGE=0 then 65 | -- Mux in inputs 66 | read_pipe.left := left; 67 | read_pipe.right := right; 68 | else 69 | -- Default read from previous stage 70 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 71 | end if; 72 | -- Default write contents of previous stage 73 | write_pipe := read_pipe; 74 | 75 | 76 | if STAGE = 0 then 77 | write_pipe.left_resized := resize(write_pipe.left, 5); 78 | write_pipe.right_resized := resize(write_pipe.right, 5); 79 | write_pipe.return_output := write_pipe.left_resized or write_pipe.right_resized; 80 | end if; 81 | -- Write to stage reg 82 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 83 | end loop; 84 | 85 | -- Last stage of pipeline return wire to return port/reg 86 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 87 | end process; 88 | 89 | end arch; 90 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/BIN_OP_XOR_int16_t_int16_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity BIN_OP_XOR_int16_t_int16_t_0CLK_de264c78 is 15 | port( 16 | left : in signed(15 downto 0); 17 | right : in signed(15 downto 0); 18 | return_output : out signed(15 downto 0)); 19 | end BIN_OP_XOR_int16_t_int16_t_0CLK_de264c78; 20 | architecture arch of BIN_OP_XOR_int16_t_int16_t_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | 26 | -- One struct to represent this modules variables 27 | type raw_hdl_variables_t is record 28 | -- All of the wires in function 29 | 30 | left_resized : signed(15 downto 0); 31 | right_resized : signed(15 downto 0); 32 | return_output : signed(15 downto 0); 33 | right : signed(15 downto 0); 34 | left : signed(15 downto 0); 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | left, 48 | right) 49 | is 50 | -- Read and write variables to do register transfers per clock 51 | -- from the previous to next stage 52 | variable read_pipe : raw_hdl_variables_t; 53 | variable write_pipe : raw_hdl_variables_t; 54 | 55 | -- This modules self pipeline registers read once per clock 56 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 57 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | begin 59 | 60 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 61 | -- LATENCY=0 is combinational Logic 62 | for STAGE in 0 to PIPELINE_LATENCY loop 63 | -- Input to first stage are inputs to function 64 | if STAGE=0 then 65 | -- Mux in inputs 66 | read_pipe.left := left; 67 | read_pipe.right := right; 68 | else 69 | -- Default read from previous stage 70 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 71 | end if; 72 | -- Default write contents of previous stage 73 | write_pipe := read_pipe; 74 | 75 | 76 | if STAGE = 0 then 77 | write_pipe.left_resized := resize(write_pipe.left, 16); 78 | write_pipe.right_resized := resize(write_pipe.right, 16); 79 | write_pipe.return_output := write_pipe.left_resized xor write_pipe.right_resized; 80 | end if; 81 | -- Write to stage reg 82 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 83 | end loop; 84 | 85 | -- Last stage of pipeline return wire to return port/reg 86 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 87 | end process; 88 | 89 | end arch; 90 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/BIN_OP_XOR_uint1_t_uint1_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity BIN_OP_XOR_uint1_t_uint1_t_0CLK_de264c78 is 15 | port( 16 | left : in unsigned(0 downto 0); 17 | right : in unsigned(0 downto 0); 18 | return_output : out unsigned(0 downto 0)); 19 | end BIN_OP_XOR_uint1_t_uint1_t_0CLK_de264c78; 20 | architecture arch of BIN_OP_XOR_uint1_t_uint1_t_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | 26 | -- One struct to represent this modules variables 27 | type raw_hdl_variables_t is record 28 | -- All of the wires in function 29 | 30 | left_resized : unsigned(0 downto 0); 31 | right_resized : unsigned(0 downto 0); 32 | return_output : unsigned(0 downto 0); 33 | right : unsigned(0 downto 0); 34 | left : unsigned(0 downto 0); 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | left, 48 | right) 49 | is 50 | -- Read and write variables to do register transfers per clock 51 | -- from the previous to next stage 52 | variable read_pipe : raw_hdl_variables_t; 53 | variable write_pipe : raw_hdl_variables_t; 54 | 55 | -- This modules self pipeline registers read once per clock 56 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 57 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | begin 59 | 60 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 61 | -- LATENCY=0 is combinational Logic 62 | for STAGE in 0 to PIPELINE_LATENCY loop 63 | -- Input to first stage are inputs to function 64 | if STAGE=0 then 65 | -- Mux in inputs 66 | read_pipe.left := left; 67 | read_pipe.right := right; 68 | else 69 | -- Default read from previous stage 70 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 71 | end if; 72 | -- Default write contents of previous stage 73 | write_pipe := read_pipe; 74 | 75 | 76 | if STAGE = 0 then 77 | write_pipe.left_resized := resize(write_pipe.left, 1); 78 | write_pipe.right_resized := resize(write_pipe.right, 1); 79 | write_pipe.return_output := write_pipe.left_resized xor write_pipe.right_resized; 80 | end if; 81 | -- Write to stage reg 82 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 83 | end loop; 84 | 85 | -- Last stage of pipeline return wire to return port/reg 86 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 87 | end process; 88 | 89 | end arch; 90 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_10_int22_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_10_int22_t_0CLK_de264c78 is 15 | port( 16 | x : in signed(21 downto 0); 17 | return_output : out signed(21 downto 0)); 18 | end CONST_SL_10_int22_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_10_int22_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : signed(21 downto 0); 30 | return_output : signed(21 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 10); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_10_int32_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_10_int32_t_0CLK_de264c78 is 15 | port( 16 | x : in signed(31 downto 0); 17 | return_output : out signed(31 downto 0)); 18 | end CONST_SL_10_int32_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_10_int32_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : signed(31 downto 0); 30 | return_output : signed(31 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 10); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_16_uint22_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_16_uint22_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(21 downto 0); 17 | return_output : out unsigned(21 downto 0)); 18 | end CONST_SL_16_uint22_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_16_uint22_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(21 downto 0); 30 | return_output : unsigned(21 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 16); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_16_uint36_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_16_uint36_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(35 downto 0); 17 | return_output : out unsigned(35 downto 0)); 18 | end CONST_SL_16_uint36_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_16_uint36_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(35 downto 0); 30 | return_output : unsigned(35 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 16); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_1_int16_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_1_int16_t_0CLK_de264c78 is 15 | port( 16 | x : in signed(15 downto 0); 17 | return_output : out signed(15 downto 0)); 18 | end CONST_SL_1_int16_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_1_int16_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : signed(15 downto 0); 30 | return_output : signed(15 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 1); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_1_uint21_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_1_uint21_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(20 downto 0); 17 | return_output : out unsigned(20 downto 0)); 18 | end CONST_SL_1_uint21_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_1_uint21_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(20 downto 0); 30 | return_output : unsigned(20 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 1); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_1_uint22_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_1_uint22_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(21 downto 0); 17 | return_output : out unsigned(21 downto 0)); 18 | end CONST_SL_1_uint22_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_1_uint22_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(21 downto 0); 30 | return_output : unsigned(21 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 1); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_1_uint36_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_1_uint36_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(35 downto 0); 17 | return_output : out unsigned(35 downto 0)); 18 | end CONST_SL_1_uint36_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_1_uint36_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(35 downto 0); 30 | return_output : unsigned(35 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 1); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_2_uint21_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_2_uint21_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(20 downto 0); 17 | return_output : out unsigned(20 downto 0)); 18 | end CONST_SL_2_uint21_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_2_uint21_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(20 downto 0); 30 | return_output : unsigned(20 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 2); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_2_uint22_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_2_uint22_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(21 downto 0); 17 | return_output : out unsigned(21 downto 0)); 18 | end CONST_SL_2_uint22_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_2_uint22_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(21 downto 0); 30 | return_output : unsigned(21 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 2); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_2_uint36_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_2_uint36_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(35 downto 0); 17 | return_output : out unsigned(35 downto 0)); 18 | end CONST_SL_2_uint36_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_2_uint36_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(35 downto 0); 30 | return_output : unsigned(35 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 2); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_4_uint21_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_4_uint21_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(20 downto 0); 17 | return_output : out unsigned(20 downto 0)); 18 | end CONST_SL_4_uint21_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_4_uint21_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(20 downto 0); 30 | return_output : unsigned(20 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 4); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_4_uint22_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_4_uint22_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(21 downto 0); 17 | return_output : out unsigned(21 downto 0)); 18 | end CONST_SL_4_uint22_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_4_uint22_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(21 downto 0); 30 | return_output : unsigned(21 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 4); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_4_uint36_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_4_uint36_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(35 downto 0); 17 | return_output : out unsigned(35 downto 0)); 18 | end CONST_SL_4_uint36_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_4_uint36_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(35 downto 0); 30 | return_output : unsigned(35 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 4); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_8_uint21_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_8_uint21_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(20 downto 0); 17 | return_output : out unsigned(20 downto 0)); 18 | end CONST_SL_8_uint21_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_8_uint21_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(20 downto 0); 30 | return_output : unsigned(20 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 8); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_8_uint22_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_8_uint22_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(21 downto 0); 17 | return_output : out unsigned(21 downto 0)); 18 | end CONST_SL_8_uint22_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_8_uint22_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(21 downto 0); 30 | return_output : unsigned(21 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 8); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_8_uint36_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_8_uint36_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(35 downto 0); 17 | return_output : out unsigned(35 downto 0)); 18 | end CONST_SL_8_uint36_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_8_uint36_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(35 downto 0); 30 | return_output : unsigned(35 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 8); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SL_9_uint32_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SL_9_uint32_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(31 downto 0); 17 | return_output : out unsigned(31 downto 0)); 18 | end CONST_SL_9_uint32_t_0CLK_de264c78; 19 | architecture arch of CONST_SL_9_uint32_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(31 downto 0); 30 | return_output : unsigned(31 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_left(write_pipe.x, 9); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_0_uint4_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_0_uint4_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(3 downto 0); 17 | return_output : out unsigned(3 downto 0)); 18 | end CONST_SR_0_uint4_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_0_uint4_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(3 downto 0); 30 | return_output : unsigned(3 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 0); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_0_uint8_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_0_uint8_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(7 downto 0); 17 | return_output : out unsigned(7 downto 0)); 18 | end CONST_SR_0_uint8_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_0_uint8_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(7 downto 0); 30 | return_output : unsigned(7 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 0); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_10_int17_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_10_int17_t_0CLK_de264c78 is 15 | port( 16 | x : in signed(16 downto 0); 17 | return_output : out signed(16 downto 0)); 18 | end CONST_SR_10_int17_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_10_int17_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : signed(16 downto 0); 30 | return_output : signed(16 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 10); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_10_int22_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_10_int22_t_0CLK_de264c78 is 15 | port( 16 | x : in signed(21 downto 0); 17 | return_output : out signed(21 downto 0)); 18 | end CONST_SR_10_int22_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_10_int22_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : signed(21 downto 0); 30 | return_output : signed(21 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 10); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_10_int44_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_10_int44_t_0CLK_de264c78 is 15 | port( 16 | x : in signed(43 downto 0); 17 | return_output : out signed(43 downto 0)); 18 | end CONST_SR_10_int44_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_10_int44_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : signed(43 downto 0); 30 | return_output : signed(43 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 10); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_11_uint39_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_11_uint39_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(38 downto 0); 17 | return_output : out unsigned(38 downto 0)); 18 | end CONST_SR_11_uint39_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_11_uint39_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(38 downto 0); 30 | return_output : unsigned(38 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 11); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_13_uint16_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_13_uint16_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(15 downto 0); 17 | return_output : out unsigned(15 downto 0)); 18 | end CONST_SR_13_uint16_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_13_uint16_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(15 downto 0); 30 | return_output : unsigned(15 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 13); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_16_int22_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_16_int22_t_0CLK_de264c78 is 15 | port( 16 | x : in signed(21 downto 0); 17 | return_output : out signed(21 downto 0)); 18 | end CONST_SR_16_int22_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_16_int22_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : signed(21 downto 0); 30 | return_output : signed(21 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 16); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_1_int22_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_1_int22_t_0CLK_de264c78 is 15 | port( 16 | x : in signed(21 downto 0); 17 | return_output : out signed(21 downto 0)); 18 | end CONST_SR_1_int22_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_1_int22_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : signed(21 downto 0); 30 | return_output : signed(21 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 1); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_1_uint16_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_1_uint16_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(15 downto 0); 17 | return_output : out unsigned(15 downto 0)); 18 | end CONST_SR_1_uint16_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_1_uint16_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(15 downto 0); 30 | return_output : unsigned(15 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 1); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_1_uint23_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_1_uint23_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(22 downto 0); 17 | return_output : out unsigned(22 downto 0)); 18 | end CONST_SR_1_uint23_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_1_uint23_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(22 downto 0); 30 | return_output : unsigned(22 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 1); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_1_uint8_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_1_uint8_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(7 downto 0); 17 | return_output : out unsigned(7 downto 0)); 18 | end CONST_SR_1_uint8_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_1_uint8_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(7 downto 0); 30 | return_output : unsigned(7 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 1); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_23_uint32_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_23_uint32_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(31 downto 0); 17 | return_output : out unsigned(31 downto 0)); 18 | end CONST_SR_23_uint32_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_23_uint32_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(31 downto 0); 30 | return_output : unsigned(31 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 23); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_2_int22_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_2_int22_t_0CLK_de264c78 is 15 | port( 16 | x : in signed(21 downto 0); 17 | return_output : out signed(21 downto 0)); 18 | end CONST_SR_2_int22_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_2_int22_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : signed(21 downto 0); 30 | return_output : signed(21 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 2); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_2_uint16_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_2_uint16_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(15 downto 0); 17 | return_output : out unsigned(15 downto 0)); 18 | end CONST_SR_2_uint16_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_2_uint16_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(15 downto 0); 30 | return_output : unsigned(15 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 2); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_2_uint8_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_2_uint8_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(7 downto 0); 17 | return_output : out unsigned(7 downto 0)); 18 | end CONST_SR_2_uint8_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_2_uint8_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(7 downto 0); 30 | return_output : unsigned(7 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 2); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_3_uint4_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_3_uint4_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(3 downto 0); 17 | return_output : out unsigned(3 downto 0)); 18 | end CONST_SR_3_uint4_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_3_uint4_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(3 downto 0); 30 | return_output : unsigned(3 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 3); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_3_uint8_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_3_uint8_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(7 downto 0); 17 | return_output : out unsigned(7 downto 0)); 18 | end CONST_SR_3_uint8_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_3_uint8_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(7 downto 0); 30 | return_output : unsigned(7 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 3); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_4_int22_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_4_int22_t_0CLK_de264c78 is 15 | port( 16 | x : in signed(21 downto 0); 17 | return_output : out signed(21 downto 0)); 18 | end CONST_SR_4_int22_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_4_int22_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : signed(21 downto 0); 30 | return_output : signed(21 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 4); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_4_uint8_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_4_uint8_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(7 downto 0); 17 | return_output : out unsigned(7 downto 0)); 18 | end CONST_SR_4_uint8_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_4_uint8_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(7 downto 0); 30 | return_output : unsigned(7 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 4); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_5_uint16_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_5_uint16_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(15 downto 0); 17 | return_output : out unsigned(15 downto 0)); 18 | end CONST_SR_5_uint16_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_5_uint16_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(15 downto 0); 30 | return_output : unsigned(15 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 5); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_5_uint8_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_5_uint8_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(7 downto 0); 17 | return_output : out unsigned(7 downto 0)); 18 | end CONST_SR_5_uint8_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_5_uint8_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(7 downto 0); 30 | return_output : unsigned(7 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 5); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_6_uint8_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_6_uint8_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(7 downto 0); 17 | return_output : out unsigned(7 downto 0)); 18 | end CONST_SR_6_uint8_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_6_uint8_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(7 downto 0); 30 | return_output : unsigned(7 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 6); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_7_uint32_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_7_uint32_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(31 downto 0); 17 | return_output : out unsigned(31 downto 0)); 18 | end CONST_SR_7_uint32_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_7_uint32_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(31 downto 0); 30 | return_output : unsigned(31 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 7); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_7_uint8_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_7_uint8_t_0CLK_de264c78 is 15 | port( 16 | x : in unsigned(7 downto 0); 17 | return_output : out unsigned(7 downto 0)); 18 | end CONST_SR_7_uint8_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_7_uint8_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : unsigned(7 downto 0); 30 | return_output : unsigned(7 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 7); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/CONST_SR_8_int22_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity CONST_SR_8_int22_t_0CLK_de264c78 is 15 | port( 16 | x : in signed(21 downto 0); 17 | return_output : out signed(21 downto 0)); 18 | end CONST_SR_8_int22_t_0CLK_de264c78; 19 | architecture arch of CONST_SR_8_int22_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | x : signed(21 downto 0); 30 | return_output : signed(21 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | x) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.x := x; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | write_pipe.return_output := shift_right(write_pipe.x, 8); -- Write to stage reg 71 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 72 | end loop; 73 | 74 | -- Last stage of pipeline return wire to return port/reg 75 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 76 | end process; 77 | 78 | end arch; 79 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/MUX_uint1_t_fixed3_fixed3_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity MUX_uint1_t_fixed3_fixed3_0CLK_de264c78 is 15 | port( 16 | cond : in unsigned(0 downto 0); 17 | iftrue : in fixed3; 18 | iffalse : in fixed3; 19 | return_output : out fixed3); 20 | end MUX_uint1_t_fixed3_fixed3_0CLK_de264c78; 21 | architecture arch of MUX_uint1_t_fixed3_fixed3_0CLK_de264c78 is 22 | -- Types and such 23 | -- Declarations 24 | attribute mark_debug : string; 25 | constant PIPELINE_LATENCY : integer := 0; 26 | 27 | -- One struct to represent this modules variables 28 | type raw_hdl_variables_t is record 29 | -- All of the wires in function 30 | 31 | return_output : fixed3; 32 | cond : unsigned(0 downto 0); 33 | iftrue : fixed3; 34 | iffalse : fixed3; 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | cond, 48 | iftrue, 49 | iffalse) 50 | is 51 | -- Read and write variables to do register transfers per clock 52 | -- from the previous to next stage 53 | variable read_pipe : raw_hdl_variables_t; 54 | variable write_pipe : raw_hdl_variables_t; 55 | 56 | -- This modules self pipeline registers read once per clock 57 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 59 | begin 60 | 61 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 62 | -- LATENCY=0 is combinational Logic 63 | for STAGE in 0 to PIPELINE_LATENCY loop 64 | -- Input to first stage are inputs to function 65 | if STAGE=0 then 66 | -- Mux in inputs 67 | read_pipe.cond := cond; 68 | read_pipe.iftrue := iftrue; 69 | read_pipe.iffalse := iffalse; 70 | else 71 | -- Default read from previous stage 72 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 73 | end if; 74 | -- Default write contents of previous stage 75 | write_pipe := read_pipe; 76 | 77 | 78 | if STAGE = 0 then 79 | -- Assign output based on range for this stage 80 | if write_pipe.cond=1 then 81 | write_pipe.return_output := write_pipe.iftrue; 82 | else 83 | write_pipe.return_output := write_pipe.iffalse; 84 | end if; 85 | end if; 86 | -- Write to stage reg 87 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 88 | end loop; 89 | 90 | -- Last stage of pipeline return wire to return port/reg 91 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 92 | end process; 93 | 94 | end arch; 95 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/MUX_uint1_t_fixed_fixed_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity MUX_uint1_t_fixed_fixed_0CLK_de264c78 is 15 | port( 16 | cond : in unsigned(0 downto 0); 17 | iftrue : in fixed; 18 | iffalse : in fixed; 19 | return_output : out fixed); 20 | end MUX_uint1_t_fixed_fixed_0CLK_de264c78; 21 | architecture arch of MUX_uint1_t_fixed_fixed_0CLK_de264c78 is 22 | -- Types and such 23 | -- Declarations 24 | attribute mark_debug : string; 25 | constant PIPELINE_LATENCY : integer := 0; 26 | 27 | -- One struct to represent this modules variables 28 | type raw_hdl_variables_t is record 29 | -- All of the wires in function 30 | 31 | return_output : fixed; 32 | cond : unsigned(0 downto 0); 33 | iftrue : fixed; 34 | iffalse : fixed; 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | cond, 48 | iftrue, 49 | iffalse) 50 | is 51 | -- Read and write variables to do register transfers per clock 52 | -- from the previous to next stage 53 | variable read_pipe : raw_hdl_variables_t; 54 | variable write_pipe : raw_hdl_variables_t; 55 | 56 | -- This modules self pipeline registers read once per clock 57 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 59 | begin 60 | 61 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 62 | -- LATENCY=0 is combinational Logic 63 | for STAGE in 0 to PIPELINE_LATENCY loop 64 | -- Input to first stage are inputs to function 65 | if STAGE=0 then 66 | -- Mux in inputs 67 | read_pipe.cond := cond; 68 | read_pipe.iftrue := iftrue; 69 | read_pipe.iffalse := iffalse; 70 | else 71 | -- Default read from previous stage 72 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 73 | end if; 74 | -- Default write contents of previous stage 75 | write_pipe := read_pipe; 76 | 77 | 78 | if STAGE = 0 then 79 | -- Assign output based on range for this stage 80 | if write_pipe.cond=1 then 81 | write_pipe.return_output := write_pipe.iftrue; 82 | else 83 | write_pipe.return_output := write_pipe.iffalse; 84 | end if; 85 | end if; 86 | -- Write to stage reg 87 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 88 | end loop; 89 | 90 | -- Last stage of pipeline return wire to return port/reg 91 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 92 | end process; 93 | 94 | end arch; 95 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/MUX_uint1_t_hit_out_hit_out_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity MUX_uint1_t_hit_out_hit_out_0CLK_de264c78 is 15 | port( 16 | cond : in unsigned(0 downto 0); 17 | iftrue : in hit_out; 18 | iffalse : in hit_out; 19 | return_output : out hit_out); 20 | end MUX_uint1_t_hit_out_hit_out_0CLK_de264c78; 21 | architecture arch of MUX_uint1_t_hit_out_hit_out_0CLK_de264c78 is 22 | -- Types and such 23 | -- Declarations 24 | attribute mark_debug : string; 25 | constant PIPELINE_LATENCY : integer := 0; 26 | 27 | -- One struct to represent this modules variables 28 | type raw_hdl_variables_t is record 29 | -- All of the wires in function 30 | 31 | return_output : hit_out; 32 | cond : unsigned(0 downto 0); 33 | iftrue : hit_out; 34 | iffalse : hit_out; 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | cond, 48 | iftrue, 49 | iffalse) 50 | is 51 | -- Read and write variables to do register transfers per clock 52 | -- from the previous to next stage 53 | variable read_pipe : raw_hdl_variables_t; 54 | variable write_pipe : raw_hdl_variables_t; 55 | 56 | -- This modules self pipeline registers read once per clock 57 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 59 | begin 60 | 61 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 62 | -- LATENCY=0 is combinational Logic 63 | for STAGE in 0 to PIPELINE_LATENCY loop 64 | -- Input to first stage are inputs to function 65 | if STAGE=0 then 66 | -- Mux in inputs 67 | read_pipe.cond := cond; 68 | read_pipe.iftrue := iftrue; 69 | read_pipe.iffalse := iffalse; 70 | else 71 | -- Default read from previous stage 72 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 73 | end if; 74 | -- Default write contents of previous stage 75 | write_pipe := read_pipe; 76 | 77 | 78 | if STAGE = 0 then 79 | -- Assign output based on range for this stage 80 | if write_pipe.cond=1 then 81 | write_pipe.return_output := write_pipe.iftrue; 82 | else 83 | write_pipe.return_output := write_pipe.iffalse; 84 | end if; 85 | end if; 86 | -- Write to stage reg 87 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 88 | end loop; 89 | 90 | -- Last stage of pipeline return wire to return port/reg 91 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 92 | end process; 93 | 94 | end arch; 95 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/MUX_uint1_t_pixel_t_pixel_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity MUX_uint1_t_pixel_t_pixel_t_0CLK_de264c78 is 15 | port( 16 | cond : in unsigned(0 downto 0); 17 | iftrue : in pixel_t; 18 | iffalse : in pixel_t; 19 | return_output : out pixel_t); 20 | end MUX_uint1_t_pixel_t_pixel_t_0CLK_de264c78; 21 | architecture arch of MUX_uint1_t_pixel_t_pixel_t_0CLK_de264c78 is 22 | -- Types and such 23 | -- Declarations 24 | attribute mark_debug : string; 25 | constant PIPELINE_LATENCY : integer := 0; 26 | 27 | -- One struct to represent this modules variables 28 | type raw_hdl_variables_t is record 29 | -- All of the wires in function 30 | 31 | return_output : pixel_t; 32 | cond : unsigned(0 downto 0); 33 | iftrue : pixel_t; 34 | iffalse : pixel_t; 35 | end record; 36 | 37 | -- Type for this modules register pipeline 38 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 39 | 40 | begin 41 | 42 | 43 | 44 | -- Combinatorial process for pipeline stages 45 | process ( 46 | -- Inputs 47 | cond, 48 | iftrue, 49 | iffalse) 50 | is 51 | -- Read and write variables to do register transfers per clock 52 | -- from the previous to next stage 53 | variable read_pipe : raw_hdl_variables_t; 54 | variable write_pipe : raw_hdl_variables_t; 55 | 56 | -- This modules self pipeline registers read once per clock 57 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 58 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 59 | begin 60 | 61 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 62 | -- LATENCY=0 is combinational Logic 63 | for STAGE in 0 to PIPELINE_LATENCY loop 64 | -- Input to first stage are inputs to function 65 | if STAGE=0 then 66 | -- Mux in inputs 67 | read_pipe.cond := cond; 68 | read_pipe.iftrue := iftrue; 69 | read_pipe.iffalse := iffalse; 70 | else 71 | -- Default read from previous stage 72 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 73 | end if; 74 | -- Default write contents of previous stage 75 | write_pipe := read_pipe; 76 | 77 | 78 | if STAGE = 0 then 79 | -- Assign output based on range for this stage 80 | if write_pipe.cond=1 then 81 | write_pipe.return_output := write_pipe.iftrue; 82 | else 83 | write_pipe.return_output := write_pipe.iffalse; 84 | end if; 85 | end if; 86 | -- Write to stage reg 87 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 88 | end loop; 89 | 90 | -- Last stage of pipeline return wire to return port/reg 91 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 92 | end process; 93 | 94 | end arch; 95 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/UNARY_OP_NEGATE_float_8_14_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity UNARY_OP_NEGATE_float_8_14_t_0CLK_de264c78 is 15 | port( 16 | expr : in std_logic_vector(22 downto 0); 17 | return_output : out std_logic_vector(22 downto 0)); 18 | end UNARY_OP_NEGATE_float_8_14_t_0CLK_de264c78; 19 | architecture arch of UNARY_OP_NEGATE_float_8_14_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | return_output : std_logic_vector(22 downto 0); 30 | expr : std_logic_vector(22 downto 0); 31 | end record; 32 | 33 | -- Type for this modules register pipeline 34 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 35 | 36 | begin 37 | 38 | 39 | 40 | -- Combinatorial process for pipeline stages 41 | process ( 42 | -- Inputs 43 | expr) 44 | is 45 | -- Read and write variables to do register transfers per clock 46 | -- from the previous to next stage 47 | variable read_pipe : raw_hdl_variables_t; 48 | variable write_pipe : raw_hdl_variables_t; 49 | 50 | -- This modules self pipeline registers read once per clock 51 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 52 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | begin 54 | 55 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 56 | -- LATENCY=0 is combinational Logic 57 | for STAGE in 0 to PIPELINE_LATENCY loop 58 | -- Input to first stage are inputs to function 59 | if STAGE=0 then 60 | -- Mux in inputs 61 | read_pipe.expr := expr; 62 | else 63 | -- Default read from previous stage 64 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 65 | end if; 66 | -- Default write contents of previous stage 67 | write_pipe := read_pipe; 68 | 69 | 70 | if STAGE = 0 then 71 | -- Same value 72 | write_pipe.return_output := write_pipe.expr; 73 | -- With left most sign bit inverted 74 | write_pipe.return_output(write_pipe.return_output'left) := not write_pipe.expr(write_pipe.expr'left); 75 | end if; 76 | -- Write to stage reg 77 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 78 | end loop; 79 | 80 | -- Last stage of pipeline return wire to return port/reg 81 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 82 | end process; 83 | 84 | end arch; 85 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/UNARY_OP_NOT_uint16_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity UNARY_OP_NOT_uint16_t_0CLK_de264c78 is 15 | port( 16 | expr : in unsigned(15 downto 0); 17 | return_output : out unsigned(15 downto 0)); 18 | end UNARY_OP_NOT_uint16_t_0CLK_de264c78; 19 | architecture arch of UNARY_OP_NOT_uint16_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | expr_resized : unsigned(15 downto 0); 30 | return_output : unsigned(15 downto 0); 31 | expr : unsigned(15 downto 0); 32 | end record; 33 | 34 | -- Type for this modules register pipeline 35 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 36 | 37 | begin 38 | 39 | 40 | 41 | -- Combinatorial process for pipeline stages 42 | process ( 43 | -- Inputs 44 | expr) 45 | is 46 | -- Read and write variables to do register transfers per clock 47 | -- from the previous to next stage 48 | variable read_pipe : raw_hdl_variables_t; 49 | variable write_pipe : raw_hdl_variables_t; 50 | 51 | -- This modules self pipeline registers read once per clock 52 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 54 | begin 55 | 56 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 57 | -- LATENCY=0 is combinational Logic 58 | for STAGE in 0 to PIPELINE_LATENCY loop 59 | -- Input to first stage are inputs to function 60 | if STAGE=0 then 61 | -- Mux in inputs 62 | read_pipe.expr := expr; 63 | else 64 | -- Default read from previous stage 65 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 66 | end if; 67 | -- Default write contents of previous stage 68 | write_pipe := read_pipe; 69 | 70 | 71 | if STAGE = 0 then 72 | write_pipe.expr_resized := resize(write_pipe.expr, 16); 73 | write_pipe.return_output := not write_pipe.expr_resized; 74 | end if; 75 | -- Write to stage reg 76 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 77 | end loop; 78 | 79 | -- Last stage of pipeline return wire to return port/reg 80 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 81 | end process; 82 | 83 | end arch; 84 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/UNARY_OP_NOT_uint17_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity UNARY_OP_NOT_uint17_t_0CLK_de264c78 is 15 | port( 16 | expr : in unsigned(16 downto 0); 17 | return_output : out unsigned(16 downto 0)); 18 | end UNARY_OP_NOT_uint17_t_0CLK_de264c78; 19 | architecture arch of UNARY_OP_NOT_uint17_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | expr_resized : unsigned(16 downto 0); 30 | return_output : unsigned(16 downto 0); 31 | expr : unsigned(16 downto 0); 32 | end record; 33 | 34 | -- Type for this modules register pipeline 35 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 36 | 37 | begin 38 | 39 | 40 | 41 | -- Combinatorial process for pipeline stages 42 | process ( 43 | -- Inputs 44 | expr) 45 | is 46 | -- Read and write variables to do register transfers per clock 47 | -- from the previous to next stage 48 | variable read_pipe : raw_hdl_variables_t; 49 | variable write_pipe : raw_hdl_variables_t; 50 | 51 | -- This modules self pipeline registers read once per clock 52 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 54 | begin 55 | 56 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 57 | -- LATENCY=0 is combinational Logic 58 | for STAGE in 0 to PIPELINE_LATENCY loop 59 | -- Input to first stage are inputs to function 60 | if STAGE=0 then 61 | -- Mux in inputs 62 | read_pipe.expr := expr; 63 | else 64 | -- Default read from previous stage 65 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 66 | end if; 67 | -- Default write contents of previous stage 68 | write_pipe := read_pipe; 69 | 70 | 71 | if STAGE = 0 then 72 | write_pipe.expr_resized := resize(write_pipe.expr, 17); 73 | write_pipe.return_output := not write_pipe.expr_resized; 74 | end if; 75 | -- Write to stage reg 76 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 77 | end loop; 78 | 79 | -- Last stage of pipeline return wire to return port/reg 80 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 81 | end process; 82 | 83 | end arch; 84 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/UNARY_OP_NOT_uint1_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity UNARY_OP_NOT_uint1_t_0CLK_de264c78 is 15 | port( 16 | expr : in unsigned(0 downto 0); 17 | return_output : out unsigned(0 downto 0)); 18 | end UNARY_OP_NOT_uint1_t_0CLK_de264c78; 19 | architecture arch of UNARY_OP_NOT_uint1_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | expr_resized : unsigned(0 downto 0); 30 | return_output : unsigned(0 downto 0); 31 | expr : unsigned(0 downto 0); 32 | end record; 33 | 34 | -- Type for this modules register pipeline 35 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 36 | 37 | begin 38 | 39 | 40 | 41 | -- Combinatorial process for pipeline stages 42 | process ( 43 | -- Inputs 44 | expr) 45 | is 46 | -- Read and write variables to do register transfers per clock 47 | -- from the previous to next stage 48 | variable read_pipe : raw_hdl_variables_t; 49 | variable write_pipe : raw_hdl_variables_t; 50 | 51 | -- This modules self pipeline registers read once per clock 52 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 54 | begin 55 | 56 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 57 | -- LATENCY=0 is combinational Logic 58 | for STAGE in 0 to PIPELINE_LATENCY loop 59 | -- Input to first stage are inputs to function 60 | if STAGE=0 then 61 | -- Mux in inputs 62 | read_pipe.expr := expr; 63 | else 64 | -- Default read from previous stage 65 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 66 | end if; 67 | -- Default write contents of previous stage 68 | write_pipe := read_pipe; 69 | 70 | 71 | if STAGE = 0 then 72 | write_pipe.expr_resized := resize(write_pipe.expr, 1); 73 | write_pipe.return_output := not write_pipe.expr_resized; 74 | end if; 75 | -- Write to stage reg 76 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 77 | end loop; 78 | 79 | -- Last stage of pipeline return wire to return port/reg 80 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 81 | end process; 82 | 83 | end arch; 84 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/UNARY_OP_NOT_uint22_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity UNARY_OP_NOT_uint22_t_0CLK_de264c78 is 15 | port( 16 | expr : in unsigned(21 downto 0); 17 | return_output : out unsigned(21 downto 0)); 18 | end UNARY_OP_NOT_uint22_t_0CLK_de264c78; 19 | architecture arch of UNARY_OP_NOT_uint22_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | expr_resized : unsigned(21 downto 0); 30 | return_output : unsigned(21 downto 0); 31 | expr : unsigned(21 downto 0); 32 | end record; 33 | 34 | -- Type for this modules register pipeline 35 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 36 | 37 | begin 38 | 39 | 40 | 41 | -- Combinatorial process for pipeline stages 42 | process ( 43 | -- Inputs 44 | expr) 45 | is 46 | -- Read and write variables to do register transfers per clock 47 | -- from the previous to next stage 48 | variable read_pipe : raw_hdl_variables_t; 49 | variable write_pipe : raw_hdl_variables_t; 50 | 51 | -- This modules self pipeline registers read once per clock 52 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 54 | begin 55 | 56 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 57 | -- LATENCY=0 is combinational Logic 58 | for STAGE in 0 to PIPELINE_LATENCY loop 59 | -- Input to first stage are inputs to function 60 | if STAGE=0 then 61 | -- Mux in inputs 62 | read_pipe.expr := expr; 63 | else 64 | -- Default read from previous stage 65 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 66 | end if; 67 | -- Default write contents of previous stage 68 | write_pipe := read_pipe; 69 | 70 | 71 | if STAGE = 0 then 72 | write_pipe.expr_resized := resize(write_pipe.expr, 22); 73 | write_pipe.return_output := not write_pipe.expr_resized; 74 | end if; 75 | -- Write to stage reg 76 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 77 | end loop; 78 | 79 | -- Last stage of pipeline return wire to return port/reg 80 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 81 | end process; 82 | 83 | end arch; 84 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/UNARY_OP_NOT_uint23_t_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 0 14 | entity UNARY_OP_NOT_uint23_t_0CLK_de264c78 is 15 | port( 16 | expr : in unsigned(22 downto 0); 17 | return_output : out unsigned(22 downto 0)); 18 | end UNARY_OP_NOT_uint23_t_0CLK_de264c78; 19 | architecture arch of UNARY_OP_NOT_uint23_t_0CLK_de264c78 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | 25 | -- One struct to represent this modules variables 26 | type raw_hdl_variables_t is record 27 | -- All of the wires in function 28 | 29 | expr_resized : unsigned(22 downto 0); 30 | return_output : unsigned(22 downto 0); 31 | expr : unsigned(22 downto 0); 32 | end record; 33 | 34 | -- Type for this modules register pipeline 35 | type raw_hdl_register_pipeline_t is array(0 to PIPELINE_LATENCY) of raw_hdl_variables_t; 36 | 37 | begin 38 | 39 | 40 | 41 | -- Combinatorial process for pipeline stages 42 | process ( 43 | -- Inputs 44 | expr) 45 | is 46 | -- Read and write variables to do register transfers per clock 47 | -- from the previous to next stage 48 | variable read_pipe : raw_hdl_variables_t; 49 | variable write_pipe : raw_hdl_variables_t; 50 | 51 | -- This modules self pipeline registers read once per clock 52 | variable read_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 53 | variable write_raw_hdl_pipeline_regs : raw_hdl_register_pipeline_t; 54 | begin 55 | 56 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 57 | -- LATENCY=0 is combinational Logic 58 | for STAGE in 0 to PIPELINE_LATENCY loop 59 | -- Input to first stage are inputs to function 60 | if STAGE=0 then 61 | -- Mux in inputs 62 | read_pipe.expr := expr; 63 | else 64 | -- Default read from previous stage 65 | read_pipe := read_raw_hdl_pipeline_regs(STAGE-1); 66 | end if; 67 | -- Default write contents of previous stage 68 | write_pipe := read_pipe; 69 | 70 | 71 | if STAGE = 0 then 72 | write_pipe.expr_resized := resize(write_pipe.expr, 23); 73 | write_pipe.return_output := not write_pipe.expr_resized; 74 | end if; 75 | -- Write to stage reg 76 | write_raw_hdl_pipeline_regs(STAGE) := write_pipe; 77 | end loop; 78 | 79 | -- Last stage of pipeline return wire to return port/reg 80 | return_output <= write_raw_hdl_pipeline_regs(PIPELINE_LATENCY).return_output; 81 | end process; 82 | 83 | end arch; 84 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/clk_cross_entities.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | use ieee.numeric_std.all; 5 | use work.c_structs_pkg.all; -- User types 6 | 7 | entity clk_cross_external_vga_timing_feedback is 8 | port( 9 | in_clk : in std_logic; 10 | 11 | in_clk_en : in unsigned(0 downto 0); 12 | 13 | in_data : in vga_signals_t_array_1_t; 14 | 15 | out_clk : in std_logic; 16 | 17 | rd_return_output : out vga_signals_t_array_1_t 18 | 19 | ); 20 | end clk_cross_external_vga_timing_feedback; 21 | architecture arch of clk_cross_external_vga_timing_feedback is 22 | 23 | constant CLK_RATIO : integer := 1; 24 | constant CLK_RATIO_MINUS1 : integer := 0; 25 | 26 | signal clock_disabled_value_r : vga_signals_t_array_1_t := vga_signals_t_array_1_t_NULL; 27 | begin 28 | 29 | -- Same clock with clock disabled past value holding reg 30 | process(in_clk, in_clk_en) is 31 | begin 32 | if rising_edge(in_clk) and in_clk_en(0) = '1' then 33 | clock_disabled_value_r <= in_data; 34 | end if; 35 | end process; 36 | 37 | -- Mux current in value or past value 38 | process(in_data,in_clk_en,clock_disabled_value_r) is 39 | begin 40 | if in_clk_en(0) = '1' then 41 | rd_return_output <= in_data; 42 | else 43 | rd_return_output <= clock_disabled_value_r; 44 | end if; 45 | end process; 46 | 47 | end arch; 48 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/dvi_active_DEBUG_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | use work.global_wires_pkg.all; 14 | -- Submodules: 0 15 | entity dvi_active_DEBUG_0CLK_de264c78 is 16 | port( 17 | global_to_module : in dvi_active_DEBUG_global_to_module_t; 18 | return_output : out unsigned(0 downto 0)); 19 | end dvi_active_DEBUG_0CLK_de264c78; 20 | architecture arch of dvi_active_DEBUG_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | -- All of the wires/regs in function 26 | 27 | begin 28 | 29 | 30 | 31 | -- Combinatorial process for pipeline stages 32 | process ( 33 | -- Clock cross input 34 | global_to_module) 35 | is 36 | -- All of the wires in function 37 | variable VAR_CLOCK_ENABLE : unsigned(0 downto 0); 38 | variable VAR_return_output : unsigned(0 downto 0); 39 | variable VAR_dvi_active : unsigned(0 downto 0); 40 | begin 41 | -- Reads from global variables 42 | VAR_dvi_active := global_to_module.dvi_active; 43 | -- Submodule level 0 44 | VAR_return_output := VAR_dvi_active; 45 | 46 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 47 | -- LATENCY=0 is combinational Logic 48 | for STAGE in 0 to PIPELINE_LATENCY loop 49 | if STAGE = 0 then 50 | 51 | -- Last stage of pipeline return wire to return port/reg 52 | return_output <= VAR_return_output; 53 | end if; 54 | end loop; 55 | 56 | end process; 57 | 58 | end arch; 59 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/dvi_blue_DEBUG_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | use work.global_wires_pkg.all; 14 | -- Submodules: 0 15 | entity dvi_blue_DEBUG_0CLK_de264c78 is 16 | port( 17 | global_to_module : in dvi_blue_DEBUG_global_to_module_t; 18 | return_output : out unsigned(7 downto 0)); 19 | end dvi_blue_DEBUG_0CLK_de264c78; 20 | architecture arch of dvi_blue_DEBUG_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | -- All of the wires/regs in function 26 | 27 | begin 28 | 29 | 30 | 31 | -- Combinatorial process for pipeline stages 32 | process ( 33 | -- Clock cross input 34 | global_to_module) 35 | is 36 | -- All of the wires in function 37 | variable VAR_CLOCK_ENABLE : unsigned(0 downto 0); 38 | variable VAR_return_output : unsigned(7 downto 0); 39 | variable VAR_dvi_blue : unsigned(7 downto 0); 40 | begin 41 | -- Reads from global variables 42 | VAR_dvi_blue := global_to_module.dvi_blue; 43 | -- Submodule level 0 44 | VAR_return_output := VAR_dvi_blue; 45 | 46 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 47 | -- LATENCY=0 is combinational Logic 48 | for STAGE in 0 to PIPELINE_LATENCY loop 49 | if STAGE = 0 then 50 | 51 | -- Last stage of pipeline return wire to return port/reg 52 | return_output <= VAR_return_output; 53 | end if; 54 | end loop; 55 | 56 | end process; 57 | 58 | end arch; 59 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/dvi_green_DEBUG_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | use work.global_wires_pkg.all; 14 | -- Submodules: 0 15 | entity dvi_green_DEBUG_0CLK_de264c78 is 16 | port( 17 | global_to_module : in dvi_green_DEBUG_global_to_module_t; 18 | return_output : out unsigned(7 downto 0)); 19 | end dvi_green_DEBUG_0CLK_de264c78; 20 | architecture arch of dvi_green_DEBUG_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | -- All of the wires/regs in function 26 | 27 | begin 28 | 29 | 30 | 31 | -- Combinatorial process for pipeline stages 32 | process ( 33 | -- Clock cross input 34 | global_to_module) 35 | is 36 | -- All of the wires in function 37 | variable VAR_CLOCK_ENABLE : unsigned(0 downto 0); 38 | variable VAR_return_output : unsigned(7 downto 0); 39 | variable VAR_dvi_green : unsigned(7 downto 0); 40 | begin 41 | -- Reads from global variables 42 | VAR_dvi_green := global_to_module.dvi_green; 43 | -- Submodule level 0 44 | VAR_return_output := VAR_dvi_green; 45 | 46 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 47 | -- LATENCY=0 is combinational Logic 48 | for STAGE in 0 to PIPELINE_LATENCY loop 49 | if STAGE = 0 then 50 | 51 | -- Last stage of pipeline return wire to return port/reg 52 | return_output <= VAR_return_output; 53 | end if; 54 | end loop; 55 | 56 | end process; 57 | 58 | end arch; 59 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/dvi_red_DEBUG_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | use work.global_wires_pkg.all; 14 | -- Submodules: 0 15 | entity dvi_red_DEBUG_0CLK_de264c78 is 16 | port( 17 | global_to_module : in dvi_red_DEBUG_global_to_module_t; 18 | return_output : out unsigned(7 downto 0)); 19 | end dvi_red_DEBUG_0CLK_de264c78; 20 | architecture arch of dvi_red_DEBUG_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | -- All of the wires/regs in function 26 | 27 | begin 28 | 29 | 30 | 31 | -- Combinatorial process for pipeline stages 32 | process ( 33 | -- Clock cross input 34 | global_to_module) 35 | is 36 | -- All of the wires in function 37 | variable VAR_CLOCK_ENABLE : unsigned(0 downto 0); 38 | variable VAR_return_output : unsigned(7 downto 0); 39 | variable VAR_dvi_red : unsigned(7 downto 0); 40 | begin 41 | -- Reads from global variables 42 | VAR_dvi_red := global_to_module.dvi_red; 43 | -- Submodule level 0 44 | VAR_return_output := VAR_dvi_red; 45 | 46 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 47 | -- LATENCY=0 is combinational Logic 48 | for STAGE in 0 to PIPELINE_LATENCY loop 49 | if STAGE = 0 then 50 | 51 | -- Last stage of pipeline return wire to return port/reg 52 | return_output <= VAR_return_output; 53 | end if; 54 | end loop; 55 | 56 | end process; 57 | 58 | end arch; 59 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/dvi_x_DEBUG_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | use work.global_wires_pkg.all; 14 | -- Submodules: 0 15 | entity dvi_x_DEBUG_0CLK_de264c78 is 16 | port( 17 | global_to_module : in dvi_x_DEBUG_global_to_module_t; 18 | return_output : out unsigned(11 downto 0)); 19 | end dvi_x_DEBUG_0CLK_de264c78; 20 | architecture arch of dvi_x_DEBUG_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | -- All of the wires/regs in function 26 | 27 | begin 28 | 29 | 30 | 31 | -- Combinatorial process for pipeline stages 32 | process ( 33 | -- Clock cross input 34 | global_to_module) 35 | is 36 | -- All of the wires in function 37 | variable VAR_CLOCK_ENABLE : unsigned(0 downto 0); 38 | variable VAR_return_output : unsigned(11 downto 0); 39 | variable VAR_dvi_x : unsigned(11 downto 0); 40 | begin 41 | -- Reads from global variables 42 | VAR_dvi_x := global_to_module.dvi_x; 43 | -- Submodule level 0 44 | VAR_return_output := VAR_dvi_x; 45 | 46 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 47 | -- LATENCY=0 is combinational Logic 48 | for STAGE in 0 to PIPELINE_LATENCY loop 49 | if STAGE = 0 then 50 | 51 | -- Last stage of pipeline return wire to return port/reg 52 | return_output <= VAR_return_output; 53 | end if; 54 | end loop; 55 | 56 | end process; 57 | 58 | end arch; 59 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/dvi_y_DEBUG_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | use work.global_wires_pkg.all; 14 | -- Submodules: 0 15 | entity dvi_y_DEBUG_0CLK_de264c78 is 16 | port( 17 | global_to_module : in dvi_y_DEBUG_global_to_module_t; 18 | return_output : out unsigned(11 downto 0)); 19 | end dvi_y_DEBUG_0CLK_de264c78; 20 | architecture arch of dvi_y_DEBUG_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | -- All of the wires/regs in function 26 | 27 | begin 28 | 29 | 30 | 31 | -- Combinatorial process for pipeline stages 32 | process ( 33 | -- Clock cross input 34 | global_to_module) 35 | is 36 | -- All of the wires in function 37 | variable VAR_CLOCK_ENABLE : unsigned(0 downto 0); 38 | variable VAR_return_output : unsigned(11 downto 0); 39 | variable VAR_dvi_y : unsigned(11 downto 0); 40 | begin 41 | -- Reads from global variables 42 | VAR_dvi_y := global_to_module.dvi_y; 43 | -- Submodule level 0 44 | VAR_return_output := VAR_dvi_y; 45 | 46 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 47 | -- LATENCY=0 is combinational Logic 48 | for STAGE in 0 to PIPELINE_LATENCY loop 49 | if STAGE = 0 then 50 | 51 | -- Last stage of pipeline return wire to return port/reg 52 | return_output <= VAR_return_output; 53 | end if; 54 | end loop; 55 | 56 | end process; 57 | 58 | end arch; 59 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/fixed3_make_0CLK_b45f1687.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 1 14 | entity fixed3_make_0CLK_b45f1687 is 15 | port( 16 | x : in fixed; 17 | y : in fixed; 18 | z : in fixed; 19 | return_output : out fixed3); 20 | end fixed3_make_0CLK_b45f1687; 21 | architecture arch of fixed3_make_0CLK_b45f1687 is 22 | -- Types and such 23 | -- Declarations 24 | attribute mark_debug : string; 25 | constant PIPELINE_LATENCY : integer := 0; 26 | -- All of the wires/regs in function 27 | -- Each function instance gets signals 28 | function CONST_REF_RD_fixed3_fixed3_7d4c( ref_toks_0 : fixed; 29 | ref_toks_1 : fixed; 30 | ref_toks_2 : fixed) return fixed3 is 31 | 32 | variable base : fixed3; 33 | variable return_output : fixed3; 34 | begin 35 | base.x := ref_toks_0; 36 | base.y := ref_toks_1; 37 | base.z := ref_toks_2; 38 | 39 | return_output := base; 40 | return return_output; 41 | end function; 42 | 43 | 44 | begin 45 | 46 | -- SUBMODULE INSTANCES 47 | 48 | 49 | -- Combinatorial process for pipeline stages 50 | process ( 51 | -- Inputs 52 | x, 53 | y, 54 | z) 55 | is 56 | -- All of the wires in function 57 | variable VAR_CLOCK_ENABLE : unsigned(0 downto 0); 58 | variable VAR_return_output : fixed3; 59 | variable VAR_x : fixed; 60 | variable VAR_y : fixed; 61 | variable VAR_z : fixed; 62 | variable VAR_r : fixed3; 63 | variable VAR_CONST_REF_RD_fixed3_fixed3_7d4c_fixed_type_h_l214_c79_9591_return_output : fixed3; 64 | begin 65 | 66 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 67 | -- LATENCY=0 is combinational Logic 68 | for STAGE in 0 to PIPELINE_LATENCY loop 69 | if STAGE = 0 then 70 | -- Mux in inputs 71 | VAR_x := x; 72 | VAR_y := y; 73 | VAR_z := z; 74 | 75 | -- Submodule level 0 76 | -- CONST_REF_RD_fixed3_fixed3_7d4c[fixed_type_h_l214_c79_9591] LATENCY=0 77 | VAR_CONST_REF_RD_fixed3_fixed3_7d4c_fixed_type_h_l214_c79_9591_return_output := CONST_REF_RD_fixed3_fixed3_7d4c( 78 | VAR_x, 79 | VAR_y, 80 | VAR_z); 81 | 82 | -- Submodule level 1 83 | VAR_return_output := VAR_CONST_REF_RD_fixed3_fixed3_7d4c_fixed_type_h_l214_c79_9591_return_output; 84 | -- Last stage of pipeline return wire to return port/reg 85 | return_output <= VAR_return_output; 86 | end if; 87 | end loop; 88 | 89 | end process; 90 | 91 | end arch; 92 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/fixed3_make_from_fixed_0CLK_b45f1687.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | -- Submodules: 1 14 | entity fixed3_make_from_fixed_0CLK_b45f1687 is 15 | port( 16 | left : in fixed; 17 | return_output : out fixed3); 18 | end fixed3_make_from_fixed_0CLK_b45f1687; 19 | architecture arch of fixed3_make_from_fixed_0CLK_b45f1687 is 20 | -- Types and such 21 | -- Declarations 22 | attribute mark_debug : string; 23 | constant PIPELINE_LATENCY : integer := 0; 24 | -- All of the wires/regs in function 25 | -- Each function instance gets signals 26 | function CONST_REF_RD_fixed3_fixed3_7d4c( ref_toks_0 : fixed; 27 | ref_toks_1 : fixed; 28 | ref_toks_2 : fixed) return fixed3 is 29 | 30 | variable base : fixed3; 31 | variable return_output : fixed3; 32 | begin 33 | base.x := ref_toks_0; 34 | base.y := ref_toks_1; 35 | base.z := ref_toks_2; 36 | 37 | return_output := base; 38 | return return_output; 39 | end function; 40 | 41 | 42 | begin 43 | 44 | -- SUBMODULE INSTANCES 45 | 46 | 47 | -- Combinatorial process for pipeline stages 48 | process ( 49 | -- Inputs 50 | left) 51 | is 52 | -- All of the wires in function 53 | variable VAR_CLOCK_ENABLE : unsigned(0 downto 0); 54 | variable VAR_return_output : fixed3; 55 | variable VAR_left : fixed; 56 | variable VAR_r : fixed3; 57 | variable VAR_CONST_REF_RD_fixed3_fixed3_7d4c_fixed_type_h_l216_c86_cae3_return_output : fixed3; 58 | begin 59 | 60 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 61 | -- LATENCY=0 is combinational Logic 62 | for STAGE in 0 to PIPELINE_LATENCY loop 63 | if STAGE = 0 then 64 | -- Mux in inputs 65 | VAR_left := left; 66 | 67 | -- Submodule level 0 68 | -- CONST_REF_RD_fixed3_fixed3_7d4c[fixed_type_h_l216_c86_cae3] LATENCY=0 69 | VAR_CONST_REF_RD_fixed3_fixed3_7d4c_fixed_type_h_l216_c86_cae3_return_output := CONST_REF_RD_fixed3_fixed3_7d4c( 70 | VAR_left, 71 | VAR_left, 72 | VAR_left); 73 | 74 | -- Submodule level 1 75 | VAR_return_output := VAR_CONST_REF_RD_fixed3_fixed3_7d4c_fixed_type_h_l216_c86_cae3_return_output; 76 | -- Last stage of pipeline return wire to return port/reg 77 | return_output <= VAR_return_output; 78 | end if; 79 | end loop; 80 | 81 | end process; 82 | 83 | end arch; 84 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/frame_clock_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | use work.global_wires_pkg.all; 14 | -- Submodules: 0 15 | entity frame_clock_0CLK_de264c78 is 16 | port( 17 | global_to_module : in frame_clock_global_to_module_t; 18 | return_output : out unsigned(0 downto 0)); 19 | end frame_clock_0CLK_de264c78; 20 | architecture arch of frame_clock_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | -- All of the wires/regs in function 26 | 27 | begin 28 | 29 | 30 | 31 | -- Combinatorial process for pipeline stages 32 | process ( 33 | -- Clock cross input 34 | global_to_module) 35 | is 36 | -- All of the wires in function 37 | variable VAR_CLOCK_ENABLE : unsigned(0 downto 0); 38 | variable VAR_return_output : unsigned(0 downto 0); 39 | variable VAR_frame_clock : unsigned(0 downto 0); 40 | begin 41 | -- Reads from global variables 42 | VAR_frame_clock := global_to_module.frame_clock; 43 | -- Submodule level 0 44 | VAR_return_output := VAR_frame_clock; 45 | 46 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 47 | -- LATENCY=0 is combinational Logic 48 | for STAGE in 0 to PIPELINE_LATENCY loop 49 | if STAGE = 0 then 50 | 51 | -- Last stage of pipeline return wire to return port/reg 52 | return_output <= VAR_return_output; 53 | end if; 54 | end loop; 55 | 56 | end process; 57 | 58 | end arch; 59 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/hsync_DEBUG_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | use work.global_wires_pkg.all; 14 | -- Submodules: 0 15 | entity hsync_DEBUG_0CLK_de264c78 is 16 | port( 17 | global_to_module : in hsync_DEBUG_global_to_module_t; 18 | return_output : out unsigned(0 downto 0)); 19 | end hsync_DEBUG_0CLK_de264c78; 20 | architecture arch of hsync_DEBUG_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | -- All of the wires/regs in function 26 | 27 | begin 28 | 29 | 30 | 31 | -- Combinatorial process for pipeline stages 32 | process ( 33 | -- Clock cross input 34 | global_to_module) 35 | is 36 | -- All of the wires in function 37 | variable VAR_CLOCK_ENABLE : unsigned(0 downto 0); 38 | variable VAR_return_output : unsigned(0 downto 0); 39 | variable VAR_hsync : unsigned(0 downto 0); 40 | begin 41 | -- Reads from global variables 42 | VAR_hsync := global_to_module.hsync; 43 | -- Submodule level 0 44 | VAR_return_output := VAR_hsync; 45 | 46 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 47 | -- LATENCY=0 is combinational Logic 48 | for STAGE in 0 to PIPELINE_LATENCY loop 49 | if STAGE = 0 then 50 | 51 | -- Last stage of pipeline return wire to return port/reg 52 | return_output <= VAR_return_output; 53 | end if; 54 | end loop; 55 | 56 | end process; 57 | 58 | end arch; 59 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/pixel_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | use work.global_wires_pkg.all; 14 | -- Submodules: 0 15 | entity pixel_0CLK_de264c78 is 16 | port( 17 | module_to_global : out pixel_module_to_global_t; 18 | clock : in unsigned(0 downto 0)); 19 | end pixel_0CLK_de264c78; 20 | architecture arch of pixel_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | -- All of the wires/regs in function 26 | 27 | begin 28 | 29 | 30 | 31 | -- Combinatorial process for pipeline stages 32 | process ( 33 | -- Inputs 34 | clock) 35 | is 36 | -- All of the wires in function 37 | variable VAR_CLOCK_ENABLE : unsigned(0 downto 0); 38 | variable VAR_clock : unsigned(0 downto 0); 39 | variable VAR_pixel_clock : unsigned(0 downto 0); 40 | begin 41 | 42 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 43 | -- LATENCY=0 is combinational Logic 44 | for STAGE in 0 to PIPELINE_LATENCY loop 45 | if STAGE = 0 then 46 | -- Mux in inputs 47 | VAR_clock := clock; 48 | 49 | -- Submodule level 0 50 | VAR_pixel_clock := VAR_clock; 51 | end if; 52 | end loop; 53 | 54 | -- Global wires driven various places in pipeline 55 | module_to_global.pixel_clock <= VAR_pixel_clock; 56 | end process; 57 | 58 | end arch; 59 | -------------------------------------------------------------------------------- /vhd/all_vhdl_files/vsync_DEBUG_0CLK_de264c78.vhd: -------------------------------------------------------------------------------- 1 | -- Timing params: 2 | -- Fixed?: False 3 | -- Pipeline Slices: [] 4 | -- Input regs?: False 5 | -- Output regs?: False 6 | library std; 7 | use std.textio.all; 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | use ieee.numeric_std.all; 11 | use ieee.float_pkg.all; 12 | use work.c_structs_pkg.all; 13 | use work.global_wires_pkg.all; 14 | -- Submodules: 0 15 | entity vsync_DEBUG_0CLK_de264c78 is 16 | port( 17 | global_to_module : in vsync_DEBUG_global_to_module_t; 18 | return_output : out unsigned(0 downto 0)); 19 | end vsync_DEBUG_0CLK_de264c78; 20 | architecture arch of vsync_DEBUG_0CLK_de264c78 is 21 | -- Types and such 22 | -- Declarations 23 | attribute mark_debug : string; 24 | constant PIPELINE_LATENCY : integer := 0; 25 | -- All of the wires/regs in function 26 | 27 | begin 28 | 29 | 30 | 31 | -- Combinatorial process for pipeline stages 32 | process ( 33 | -- Clock cross input 34 | global_to_module) 35 | is 36 | -- All of the wires in function 37 | variable VAR_CLOCK_ENABLE : unsigned(0 downto 0); 38 | variable VAR_return_output : unsigned(0 downto 0); 39 | variable VAR_vsync : unsigned(0 downto 0); 40 | begin 41 | -- Reads from global variables 42 | VAR_vsync := global_to_module.vsync; 43 | -- Submodule level 0 44 | VAR_return_output := VAR_vsync; 45 | 46 | -- Loop to construct simultaneous register transfers for each of the pipeline stages 47 | -- LATENCY=0 is combinational Logic 48 | for STAGE in 0 to PIPELINE_LATENCY loop 49 | if STAGE = 0 then 50 | 51 | -- Last stage of pipeline return wire to return port/reg 52 | return_output <= VAR_return_output; 53 | end if; 54 | end loop; 55 | 56 | end process; 57 | 58 | end arch; 59 | --------------------------------------------------------------------------------