├── LICENSE ├── README.md ├── aes_128128_unrolled ├── aes.vhd ├── aes_enc.vhd ├── aes_key.vhd ├── aes_mix.vhd ├── aes_sbox.vhd ├── aes_shift.vhd ├── aes_tb.vhd └── constants.vhd ├── katan_3280_unrolled ├── constants.vhd ├── katan.vhd ├── katan_enc.vhd ├── katan_key.vhd └── katan_tb.vhd ├── katan_6480_unrolled ├── constants.vhd ├── katan.vhd ├── katan_enc.vhd ├── katan_key.vhd └── katan_tb.vhd ├── present_64128_unrolled ├── constants.vhd ├── present.vhd ├── present_enc.vhd ├── present_key.vhd ├── present_p.vhd ├── present_sbox.vhd └── present_tb.vhd ├── present_6480_unrolled ├── constants.vhd ├── present.vhd ├── present_enc.vhd ├── present_key.vhd ├── present_p.vhd ├── present_sbox.vhd └── present_tb.vhd ├── prince_unrolled ├── constants.vhd ├── prince.vhd ├── prince_matrix.vhd ├── prince_round.vhd ├── prince_sbox.vhd ├── prince_tb.vhd └── prince_wrapper.vhd ├── simon_3264_unrolled ├── constants.vhd ├── simon.vhd ├── simon_enc.vhd ├── simon_key.vhd └── simon_tb.vhd ├── simon_64128_unrolled ├── constants.vhd ├── simon.vhd ├── simon_enc.vhd ├── simon_key.vhd └── simon_tb.vhd ├── speck_3264_unrolled ├── constants.vhd ├── speck.vhd ├── speck_enc.vhd ├── speck_key.vhd └── speck_tb.vhd └── speck_64128_unrolled ├── constants.vhd ├── speck.vhd ├── speck_enc.vhd ├── speck_key.vhd └── speck_tb.vhd /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2016 KU Leuven 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Single-Cycle Implementations of Block Ciphers 2 | 3 | Security mechanisms to protect our systems and data from malicious adversaries have become essential. Strong encryption algorithms are an important building block of these solutions. However, each application has its own requirements and it is not always possible to find a cipher that meets them all. This work compares unrolled combinational hardware implementations of six lightweight block ciphers, along with an AES implementation as a baseline. Up until now, the majority of such ciphers were designed for area-constrained environments where speed is often not crucial, but recently the need for single-cycle, low-latency block ciphers with limited area requirements has arisen to build security architectures for embedded systems. Our comparison shows that some designers are already on this track, but a lot of work still remains to be done. 4 | 5 | ## Ciphers 6 | 7 | This repository has fully unrolled implementations of the following ciphers in VHDL: 8 | 9 | | Cipher | Block Size | Key Size | 10 | |---------|------------|----------| 11 | | AES | 128 | 128 | 12 | | KATAN | 32 | 80 | 13 | | KATAN | 64 | 80 | 14 | | PRESENT | 64 | 80 | 15 | | PRINCE | 64 | 128 | 16 | | SIMON | 32 | 64 | 17 | | SIMON | 64 | 128 | 18 | | SPECK | 32 | 64 | 19 | | SPECK | 64 | 128 | 20 | 21 | ## Further Reading 22 | 23 | These ciphers were analyzed and compared in the paper "Single-Cycle Implementations of Block Ciphers", available at https://eprint.iacr.org/2015/658.pdf. 24 | 25 | ## Acknowledgements 26 | 27 | This work was supported in part by the Research Council KU Leuven: GOA TENSE (GOA/11/007). In addition, this work is supported in part by the Flemish Government through FWO G.0130.13N and FWO G.0876.14N. We would like to thank Kimmo Järvinen for his valued advice. Pieter Maene is supported by a doctoral grant of the Research Foundation - Flanders (FWO). 28 | -------------------------------------------------------------------------------- /aes_128128_unrolled/aes.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use work.constants.all; 4 | 5 | entity aes is 6 | port ( 7 | key : in std_logic_vector(127 downto 0); 8 | plaintext : in std_logic_vector(127 downto 0); 9 | 10 | ciphertext : out std_logic_vector(127 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of aes is 15 | signal keys : key_array; 16 | signal cts : ct_array; 17 | 18 | signal sboxo : std_logic_vector(127 downto 0); 19 | signal shifto : std_logic_vector(127 downto 0); 20 | 21 | component aes_key is 22 | generic ( 23 | round_ctr : integer 24 | ); 25 | port ( 26 | keyi : in std_logic_vector(127 downto 0); 27 | keyo : out std_logic_vector(127 downto 0) 28 | ); 29 | end component aes_key; 30 | 31 | component aes_enc is 32 | port ( 33 | key : in std_logic_vector(127 downto 0); 34 | datai : in std_logic_vector(127 downto 0); 35 | 36 | datao : out std_logic_vector(127 downto 0) 37 | ); 38 | end component aes_enc; 39 | 40 | component aes_sbox is 41 | port ( 42 | datai : in std_logic_vector(7 downto 0); 43 | datao : out std_logic_vector(7 downto 0) 44 | ); 45 | end component aes_sbox; 46 | 47 | component aes_shift is 48 | port ( 49 | datai : in std_logic_vector(127 downto 0); 50 | datao : out std_logic_vector(127 downto 0) 51 | ); 52 | end component aes_shift; 53 | begin 54 | enc_generate : for i in 0 to 8 generate 55 | enc0 : aes_enc 56 | port map ( 57 | key => keys(i+1), 58 | datai => cts(i), 59 | 60 | datao => cts(i+1) 61 | ); 62 | end generate; 63 | 64 | key_generate : for i in 0 to 9 generate 65 | key0 : aes_key 66 | generic map ( 67 | round_ctr => i+1 68 | ) 69 | port map ( 70 | keyi => keys(i), 71 | keyo => keys(i+1) 72 | ); 73 | end generate; 74 | 75 | sbox_generate : for i in 0 to 15 generate 76 | sbox0 : aes_sbox 77 | port map ( 78 | datai => cts(9)(8*i+7 downto 8*i), 79 | datao => sboxo(8*i+7 downto 8*i) 80 | ); 81 | end generate; 82 | 83 | shift0 : aes_shift 84 | port map ( 85 | datai => sboxo, 86 | datao => shifto 87 | ); 88 | 89 | enc_process : process(key, plaintext) is 90 | begin 91 | keys(0) <= key; 92 | cts(0) <= plaintext xor key; 93 | end process enc_process; 94 | 95 | ciphertext <= shifto xor keys(10); 96 | end architecture rtl; 97 | -------------------------------------------------------------------------------- /aes_128128_unrolled/aes_enc.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity aes_enc is 6 | port ( 7 | key : in std_logic_vector(127 downto 0); 8 | datai : in std_logic_vector(127 downto 0); 9 | 10 | datao : out std_logic_vector(127 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of aes_enc is 15 | signal sboxo : std_logic_vector(127 downto 0); 16 | signal shifto : std_logic_vector(127 downto 0); 17 | signal mixo : std_logic_vector(127 downto 0); 18 | 19 | component aes_sbox 20 | port ( 21 | datai : in std_logic_vector(7 downto 0); 22 | datao : out std_logic_vector(7 downto 0) 23 | ); 24 | end component aes_sbox; 25 | 26 | component aes_shift 27 | port ( 28 | datai : in std_logic_vector(127 downto 0); 29 | datao : out std_logic_vector(127 downto 0) 30 | ); 31 | end component aes_shift; 32 | 33 | component aes_mix 34 | port ( 35 | datai : in std_logic_vector(127 downto 0); 36 | datao : out std_logic_vector(127 downto 0) 37 | ); 38 | end component aes_mix; 39 | begin 40 | sbox_generate : for i in 0 to 15 generate 41 | sbox0 : aes_sbox 42 | port map ( 43 | datai => datai(8*i+7 downto 8*i), 44 | datao => sboxo(8*i+7 downto 8*i) 45 | ); 46 | end generate; 47 | 48 | shift0 : aes_shift 49 | port map ( 50 | datai => sboxo, 51 | datao => shifto 52 | ); 53 | 54 | mix0 : aes_mix 55 | port map ( 56 | datai => shifto, 57 | datao => mixo 58 | ); 59 | 60 | datao <= mixo xor key; 61 | end architecture rtl; 62 | -------------------------------------------------------------------------------- /aes_128128_unrolled/aes_key.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | use work.constants.all; 5 | 6 | entity aes_key is 7 | generic ( 8 | round_ctr : integer 9 | ); 10 | port ( 11 | keyi : in std_logic_vector(127 downto 0); 12 | keyo : out std_logic_vector(127 downto 0) 13 | ); 14 | end entity; 15 | 16 | architecture rtl of aes_key is 17 | signal rcon : std_logic_vector(7 downto 0); 18 | 19 | signal sbox0i : std_logic_vector(7 downto 0); 20 | signal sbox1i : std_logic_vector(7 downto 0); 21 | signal sbox2i : std_logic_vector(7 downto 0); 22 | signal sbox3i : std_logic_vector(7 downto 0); 23 | 24 | signal sbox0o : std_logic_vector(7 downto 0); 25 | signal sbox1o : std_logic_vector(7 downto 0); 26 | signal sbox2o : std_logic_vector(7 downto 0); 27 | signal sbox3o : std_logic_vector(7 downto 0); 28 | 29 | signal keyo_s : std_logic_vector(127 downto 0); 30 | 31 | component aes_sbox is 32 | port ( 33 | datai : in std_logic_vector(7 downto 0); 34 | datao : out std_logic_vector(7 downto 0) 35 | ); 36 | end component aes_sbox; 37 | begin 38 | sbox0 : aes_sbox 39 | port map ( 40 | datai => keyi(23 downto 16), 41 | datao => sbox0o 42 | ); 43 | 44 | sbox1 : aes_sbox 45 | port map ( 46 | datai => keyi(15 downto 8), 47 | datao => sbox1o 48 | ); 49 | 50 | sbox2 : aes_sbox 51 | port map ( 52 | datai => keyi(7 downto 0), 53 | datao => sbox2o 54 | ); 55 | 56 | sbox3 : aes_sbox 57 | port map ( 58 | datai => keyi(31 downto 24), 59 | datao => sbox3o 60 | ); 61 | 62 | expand_process : process (keyi) is 63 | begin 64 | rcon_case : case round_ctr is 65 | when 1 => rcon <= x"01"; 66 | when 2 => rcon <= x"02"; 67 | when 3 => rcon <= x"04"; 68 | when 4 => rcon <= x"08"; 69 | when 5 => rcon <= x"10"; 70 | when 6 => rcon <= x"20"; 71 | when 7 => rcon <= x"40"; 72 | when 8 => rcon <= x"80"; 73 | when 9 => rcon <= x"1b"; 74 | when 10 => rcon <= x"36"; 75 | 76 | when others => rcon <= (others => 'X'); 77 | end case rcon_case; 78 | end process expand_process; 79 | 80 | keyo_s(127 downto 120) <= (sbox0o xor rcon) xor keyi(127 downto 120); 81 | keyo_s(119 downto 112) <= sbox1o xor keyi(119 downto 112); 82 | keyo_s(111 downto 104) <= sbox2o xor keyi(111 downto 104); 83 | keyo_s(103 downto 96) <= sbox3o xor keyi(103 downto 96); 84 | 85 | keyo_s(95 downto 64) <= keyo_s(127 downto 96) xor keyi(95 downto 64); 86 | keyo_s(63 downto 32) <= keyo_s(95 downto 64) xor keyi(63 downto 32); 87 | keyo_s(31 downto 0) <= keyo_s(63 downto 32) xor keyi(31 downto 0); 88 | 89 | keyo <= keyo_s; 90 | end architecture rtl; 91 | -------------------------------------------------------------------------------- /aes_128128_unrolled/aes_mix.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity aes_mix is 5 | port ( 6 | datai : in std_logic_vector(127 downto 0); 7 | datao : out std_logic_vector(127 downto 0) 8 | ); 9 | end entity; 10 | 11 | architecture rtl of aes_mix is 12 | function mul(x : std_logic_vector(7 downto 0); y : std_logic_vector(7 downto 0)) return std_logic_vector is 13 | variable tmp : std_logic_vector(7 downto 0); 14 | variable mask : std_logic_vector(7 downto 0); 15 | begin 16 | -- If the MSB is 1, an overflow will occur when multiplied by 2 or 3. 17 | -- mask will be 0xFF if MSB is 1, and a conditional XOR will be applied. 18 | mask := y(7) & y(7) & y(7) & y(7) & y(7) & y(7) & y(7) & y(7); 19 | 20 | mul_case : case x(3 downto 0) is 21 | when x"2" => tmp := (y(6 downto 0) & '0') xor (x"1B" and mask); 22 | when x"3" => tmp := (y(6 downto 0) & '0') xor y xor (x"1B" and mask); 23 | 24 | when others => tmp := (others => '0'); 25 | end case mul_case; 26 | 27 | return tmp; 28 | end function mul; 29 | begin 30 | mix_process : process (datai) is 31 | begin 32 | datao(127 downto 120) <= mul(x"02", datai(127 downto 120)) xor mul(x"03", datai(119 downto 112)) xor datai(111 downto 104) xor datai(103 downto 96); 33 | datao(119 downto 112) <= datai(127 downto 120) xor mul(x"02", datai(119 downto 112)) xor mul(x"03", datai(111 downto 104)) xor datai(103 downto 96); 34 | datao(111 downto 104) <= datai(127 downto 120) xor datai(119 downto 112) xor mul(x"02", datai(111 downto 104)) xor mul(x"03", datai(103 downto 96)); 35 | datao(103 downto 96) <= mul(x"03", datai(127 downto 120)) xor datai(119 downto 112) xor datai(111 downto 104) xor mul(x"02", datai(103 downto 96)); 36 | 37 | datao(95 downto 88) <= mul(x"02", datai(95 downto 88)) xor mul(x"03", datai(87 downto 80)) xor datai(79 downto 72) xor datai(71 downto 64); 38 | datao(87 downto 80) <= datai(95 downto 88) xor mul(x"02", datai(87 downto 80)) xor mul(x"03", datai(79 downto 72)) xor datai(71 downto 64); 39 | datao(79 downto 72) <= datai(95 downto 88) xor datai(87 downto 80) xor mul(x"02", datai(79 downto 72)) xor mul(x"03", datai(71 downto 64)); 40 | datao(71 downto 64) <= mul(x"03", datai(95 downto 88)) xor datai(87 downto 80) xor datai(79 downto 72) xor mul(x"02", datai(71 downto 64)); 41 | 42 | datao(63 downto 56) <= mul(x"02", datai(63 downto 56)) xor mul(x"03", datai(55 downto 48)) xor datai(47 downto 40) xor datai(39 downto 32); 43 | datao(55 downto 48) <= datai(63 downto 56) xor mul(x"02", datai(55 downto 48)) xor mul(x"03", datai(47 downto 40)) xor datai(39 downto 32); 44 | datao(47 downto 40) <= datai(63 downto 56) xor datai(55 downto 48) xor mul(x"02", datai(47 downto 40)) xor mul(x"03", datai(39 downto 32)); 45 | datao(39 downto 32) <= mul(x"03", datai(63 downto 56)) xor datai(55 downto 48) xor datai(47 downto 40) xor mul(x"02", datai(39 downto 32)); 46 | 47 | datao(31 downto 24) <= mul(x"02", datai(31 downto 24)) xor mul(x"03", datai(23 downto 16)) xor datai(15 downto 8) xor datai(7 downto 0); 48 | datao(23 downto 16) <= datai(31 downto 24) xor mul(x"02", datai(23 downto 16)) xor mul(x"03", datai(15 downto 8)) xor datai(7 downto 0); 49 | datao(15 downto 8) <= datai(31 downto 24) xor datai(23 downto 16) xor mul(x"02", datai(15 downto 8)) xor mul(x"03", datai(7 downto 0)); 50 | datao(7 downto 0) <= mul(x"03", datai(31 downto 24)) xor datai(23 downto 16) xor datai(15 downto 8) xor mul(x"02", datai(7 downto 0)); 51 | end process mix_process; 52 | end architecture rtl; 53 | -------------------------------------------------------------------------------- /aes_128128_unrolled/aes_sbox.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity aes_sbox is 5 | port ( 6 | datai : in std_logic_vector(7 downto 0); 7 | datao : out std_logic_vector(7 downto 0) 8 | ); 9 | end entity; 10 | 11 | architecture rtl of aes_sbox is 12 | begin 13 | lookup_process : process (datai) is 14 | begin 15 | lookup_case : case datai is 16 | when x"00" => datao <= x"63"; 17 | when x"01" => datao <= x"7C"; 18 | when x"02" => datao <= x"77"; 19 | when x"03" => datao <= x"7B"; 20 | when x"04" => datao <= x"F2"; 21 | when x"05" => datao <= x"6B"; 22 | when x"06" => datao <= x"6F"; 23 | when x"07" => datao <= x"C5"; 24 | when x"08" => datao <= x"30"; 25 | when x"09" => datao <= x"01"; 26 | when x"0A" => datao <= x"67"; 27 | when x"0B" => datao <= x"2B"; 28 | when x"0C" => datao <= x"FE"; 29 | when x"0D" => datao <= x"D7"; 30 | when x"0E" => datao <= x"AB"; 31 | when x"0F" => datao <= x"76"; 32 | 33 | when x"10" => datao <= x"CA"; 34 | when x"11" => datao <= x"82"; 35 | when x"12" => datao <= x"C9"; 36 | when x"13" => datao <= x"7D"; 37 | when x"14" => datao <= x"FA"; 38 | when x"15" => datao <= x"59"; 39 | when x"16" => datao <= x"47"; 40 | when x"17" => datao <= x"F0"; 41 | when x"18" => datao <= x"AD"; 42 | when x"19" => datao <= x"D4"; 43 | when x"1A" => datao <= x"A2"; 44 | when x"1B" => datao <= x"AF"; 45 | when x"1C" => datao <= x"9C"; 46 | when x"1D" => datao <= x"A4"; 47 | when x"1E" => datao <= x"72"; 48 | when x"1F" => datao <= x"C0"; 49 | 50 | when x"20" => datao <= x"B7"; 51 | when x"21" => datao <= x"FD"; 52 | when x"22" => datao <= x"93"; 53 | when x"23" => datao <= x"26"; 54 | when x"24" => datao <= x"36"; 55 | when x"25" => datao <= x"3F"; 56 | when x"26" => datao <= x"F7"; 57 | when x"27" => datao <= x"CC"; 58 | when x"28" => datao <= x"34"; 59 | when x"29" => datao <= x"A5"; 60 | when x"2A" => datao <= x"E5"; 61 | when x"2B" => datao <= x"F1"; 62 | when x"2C" => datao <= x"71"; 63 | when x"2D" => datao <= x"D8"; 64 | when x"2E" => datao <= x"31"; 65 | when x"2F" => datao <= x"15"; 66 | 67 | when x"30" => datao <= x"04"; 68 | when x"31" => datao <= x"C7"; 69 | when x"32" => datao <= x"23"; 70 | when x"33" => datao <= x"C3"; 71 | when x"34" => datao <= x"18"; 72 | when x"35" => datao <= x"96"; 73 | when x"36" => datao <= x"05"; 74 | when x"37" => datao <= x"9A"; 75 | when x"38" => datao <= x"07"; 76 | when x"39" => datao <= x"12"; 77 | when x"3A" => datao <= x"80"; 78 | when x"3B" => datao <= x"E2"; 79 | when x"3C" => datao <= x"EB"; 80 | when x"3D" => datao <= x"27"; 81 | when x"3E" => datao <= x"B2"; 82 | when x"3F" => datao <= x"75"; 83 | 84 | when x"40" => datao <= x"09"; 85 | when x"41" => datao <= x"83"; 86 | when x"42" => datao <= x"2C"; 87 | when x"43" => datao <= x"1A"; 88 | when x"44" => datao <= x"1B"; 89 | when x"45" => datao <= x"6E"; 90 | when x"46" => datao <= x"5A"; 91 | when x"47" => datao <= x"A0"; 92 | when x"48" => datao <= x"52"; 93 | when x"49" => datao <= x"3B"; 94 | when x"4A" => datao <= x"D6"; 95 | when x"4B" => datao <= x"B3"; 96 | when x"4C" => datao <= x"29"; 97 | when x"4D" => datao <= x"E3"; 98 | when x"4E" => datao <= x"2F"; 99 | when x"4F" => datao <= x"84"; 100 | 101 | when x"50" => datao <= x"53"; 102 | when x"51" => datao <= x"D1"; 103 | when x"52" => datao <= x"00"; 104 | when x"53" => datao <= x"ED"; 105 | when x"54" => datao <= x"20"; 106 | when x"55" => datao <= x"FC"; 107 | when x"56" => datao <= x"B1"; 108 | when x"57" => datao <= x"5B"; 109 | when x"58" => datao <= x"6A"; 110 | when x"59" => datao <= x"CB"; 111 | when x"5A" => datao <= x"BE"; 112 | when x"5B" => datao <= x"39"; 113 | when x"5C" => datao <= x"4A"; 114 | when x"5D" => datao <= x"4C"; 115 | when x"5E" => datao <= x"58"; 116 | when x"5F" => datao <= x"CF"; 117 | 118 | when x"60" => datao <= x"D0"; 119 | when x"61" => datao <= x"EF"; 120 | when x"62" => datao <= x"AA"; 121 | when x"63" => datao <= x"FB"; 122 | when x"64" => datao <= x"43"; 123 | when x"65" => datao <= x"4D"; 124 | when x"66" => datao <= x"33"; 125 | when x"67" => datao <= x"85"; 126 | when x"68" => datao <= x"45"; 127 | when x"69" => datao <= x"F9"; 128 | when x"6A" => datao <= x"02"; 129 | when x"6B" => datao <= x"7F"; 130 | when x"6C" => datao <= x"50"; 131 | when x"6D" => datao <= x"3C"; 132 | when x"6E" => datao <= x"9F"; 133 | when x"6F" => datao <= x"A8"; 134 | 135 | when x"70" => datao <= x"51"; 136 | when x"71" => datao <= x"A3"; 137 | when x"72" => datao <= x"40"; 138 | when x"73" => datao <= x"8F"; 139 | when x"74" => datao <= x"92"; 140 | when x"75" => datao <= x"9D"; 141 | when x"76" => datao <= x"38"; 142 | when x"77" => datao <= x"F5"; 143 | when x"78" => datao <= x"BC"; 144 | when x"79" => datao <= x"B6"; 145 | when x"7A" => datao <= x"DA"; 146 | when x"7B" => datao <= x"21"; 147 | when x"7C" => datao <= x"10"; 148 | when x"7D" => datao <= x"FF"; 149 | when x"7E" => datao <= x"F3"; 150 | when x"7F" => datao <= x"D2"; 151 | 152 | when x"80" => datao <= x"CD"; 153 | when x"81" => datao <= x"0C"; 154 | when x"82" => datao <= x"13"; 155 | when x"83" => datao <= x"EC"; 156 | when x"84" => datao <= x"5F"; 157 | when x"85" => datao <= x"97"; 158 | when x"86" => datao <= x"44"; 159 | when x"87" => datao <= x"17"; 160 | when x"88" => datao <= x"C4"; 161 | when x"89" => datao <= x"A7"; 162 | when x"8A" => datao <= x"7E"; 163 | when x"8B" => datao <= x"3D"; 164 | when x"8C" => datao <= x"64"; 165 | when x"8D" => datao <= x"5D"; 166 | when x"8E" => datao <= x"19"; 167 | when x"8F" => datao <= x"73"; 168 | 169 | when x"90" => datao <= x"60"; 170 | when x"91" => datao <= x"81"; 171 | when x"92" => datao <= x"4F"; 172 | when x"93" => datao <= x"DC"; 173 | when x"94" => datao <= x"22"; 174 | when x"95" => datao <= x"2A"; 175 | when x"96" => datao <= x"90"; 176 | when x"97" => datao <= x"88"; 177 | when x"98" => datao <= x"46"; 178 | when x"99" => datao <= x"EE"; 179 | when x"9A" => datao <= x"B8"; 180 | when x"9B" => datao <= x"14"; 181 | when x"9C" => datao <= x"DE"; 182 | when x"9D" => datao <= x"5E"; 183 | when x"9E" => datao <= x"0B"; 184 | when x"9F" => datao <= x"DB"; 185 | 186 | when x"A0" => datao <= x"E0"; 187 | when x"A1" => datao <= x"32"; 188 | when x"A2" => datao <= x"3A"; 189 | when x"A3" => datao <= x"0A"; 190 | when x"A4" => datao <= x"49"; 191 | when x"A5" => datao <= x"06"; 192 | when x"A6" => datao <= x"24"; 193 | when x"A7" => datao <= x"5C"; 194 | when x"A8" => datao <= x"C2"; 195 | when x"A9" => datao <= x"D3"; 196 | when x"AA" => datao <= x"AC"; 197 | when x"AB" => datao <= x"62"; 198 | when x"AC" => datao <= x"91"; 199 | when x"AD" => datao <= x"95"; 200 | when x"AE" => datao <= x"E4"; 201 | when x"AF" => datao <= x"79"; 202 | 203 | when x"B0" => datao <= x"E7"; 204 | when x"B1" => datao <= x"C8"; 205 | when x"B2" => datao <= x"37"; 206 | when x"B3" => datao <= x"6D"; 207 | when x"B4" => datao <= x"8D"; 208 | when x"B5" => datao <= x"D5"; 209 | when x"B6" => datao <= x"4E"; 210 | when x"B7" => datao <= x"A9"; 211 | when x"B8" => datao <= x"6C"; 212 | when x"B9" => datao <= x"56"; 213 | when x"BA" => datao <= x"F4"; 214 | when x"BB" => datao <= x"EA"; 215 | when x"BC" => datao <= x"65"; 216 | when x"BD" => datao <= x"7A"; 217 | when x"BE" => datao <= x"AE"; 218 | when x"BF" => datao <= x"08"; 219 | 220 | when x"C0" => datao <= x"BA"; 221 | when x"C1" => datao <= x"78"; 222 | when x"C2" => datao <= x"25"; 223 | when x"C3" => datao <= x"2E"; 224 | when x"C4" => datao <= x"1C"; 225 | when x"C5" => datao <= x"A6"; 226 | when x"C6" => datao <= x"B4"; 227 | when x"C7" => datao <= x"C6"; 228 | when x"C8" => datao <= x"E8"; 229 | when x"C9" => datao <= x"DD"; 230 | when x"CA" => datao <= x"74"; 231 | when x"CB" => datao <= x"1F"; 232 | when x"CC" => datao <= x"4B"; 233 | when x"CD" => datao <= x"BD"; 234 | when x"CE" => datao <= x"8B"; 235 | when x"CF" => datao <= x"8A"; 236 | 237 | when x"D0" => datao <= x"70"; 238 | when x"D1" => datao <= x"3E"; 239 | when x"D2" => datao <= x"B5"; 240 | when x"D3" => datao <= x"66"; 241 | when x"D4" => datao <= x"48"; 242 | when x"D5" => datao <= x"03"; 243 | when x"D6" => datao <= x"F6"; 244 | when x"D7" => datao <= x"0E"; 245 | when x"D8" => datao <= x"61"; 246 | when x"D9" => datao <= x"35"; 247 | when x"DA" => datao <= x"57"; 248 | when x"DB" => datao <= x"B9"; 249 | when x"DC" => datao <= x"86"; 250 | when x"DD" => datao <= x"C1"; 251 | when x"DE" => datao <= x"1D"; 252 | when x"DF" => datao <= x"9E"; 253 | 254 | when x"E0" => datao <= x"E1"; 255 | when x"E1" => datao <= x"F8"; 256 | when x"E2" => datao <= x"98"; 257 | when x"E3" => datao <= x"11"; 258 | when x"E4" => datao <= x"69"; 259 | when x"E5" => datao <= x"D9"; 260 | when x"E6" => datao <= x"8E"; 261 | when x"E7" => datao <= x"94"; 262 | when x"E8" => datao <= x"9B"; 263 | when x"E9" => datao <= x"1E"; 264 | when x"EA" => datao <= x"87"; 265 | when x"EB" => datao <= x"E9"; 266 | when x"EC" => datao <= x"CE"; 267 | when x"ED" => datao <= x"55"; 268 | when x"EE" => datao <= x"28"; 269 | when x"EF" => datao <= x"DF"; 270 | 271 | when x"F0" => datao <= x"8C"; 272 | when x"F1" => datao <= x"A1"; 273 | when x"F2" => datao <= x"89"; 274 | when x"F3" => datao <= x"0D"; 275 | when x"F4" => datao <= x"BF"; 276 | when x"F5" => datao <= x"E6"; 277 | when x"F6" => datao <= x"42"; 278 | when x"F7" => datao <= x"68"; 279 | when x"F8" => datao <= x"41"; 280 | when x"F9" => datao <= x"99"; 281 | when x"FA" => datao <= x"2D"; 282 | when x"FB" => datao <= x"0F"; 283 | when x"FC" => datao <= x"B0"; 284 | when x"FD" => datao <= x"54"; 285 | when x"FE" => datao <= x"BB"; 286 | when x"FF" => datao <= x"16"; 287 | 288 | when others => datao <= (others => 'X'); 289 | end case lookup_case; 290 | end process lookup_process; 291 | end architecture rtl; 292 | -------------------------------------------------------------------------------- /aes_128128_unrolled/aes_shift.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity aes_shift is 5 | port ( 6 | datai : in std_logic_vector(127 downto 0); 7 | datao : out std_logic_vector(127 downto 0) 8 | ); 9 | end entity; 10 | 11 | architecture rtl of aes_shift is 12 | begin 13 | shift_process : process (datai) is 14 | begin 15 | datao(127 downto 120) <= datai(127 downto 120); 16 | datao(119 downto 112) <= datai(87 downto 80); 17 | datao(111 downto 104) <= datai(47 downto 40); 18 | datao(103 downto 96) <= datai(7 downto 0); 19 | 20 | datao(95 downto 88) <= datai(95 downto 88); 21 | datao(87 downto 80) <= datai(55 downto 48); 22 | datao(79 downto 72) <= datai(15 downto 8); 23 | datao(71 downto 64) <= datai(103 downto 96); 24 | 25 | datao(63 downto 56) <= datai(63 downto 56); 26 | datao(55 downto 48) <= datai(23 downto 16); 27 | datao(47 downto 40) <= datai(111 downto 104); 28 | datao(39 downto 32) <= datai(71 downto 64); 29 | 30 | datao(31 downto 24) <= datai(31 downto 24); 31 | datao(23 downto 16) <= datai(119 downto 112); 32 | datao(15 downto 8) <= datai(79 downto 72); 33 | datao(7 downto 0) <= datai(39 downto 32); 34 | end process shift_process; 35 | end architecture rtl; 36 | -------------------------------------------------------------------------------- /aes_128128_unrolled/aes_tb.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity aes_tb is 5 | end entity; 6 | 7 | architecture test of aes_tb is 8 | signal r_key : std_logic_vector(127 downto 0); 9 | signal r_plaintext : std_logic_vector(127 downto 0); 10 | 11 | signal r_ciphertext : std_logic_vector(127 downto 0); 12 | 13 | component aes is 14 | port ( 15 | key : in std_logic_vector(127 downto 0); 16 | plaintext : in std_logic_vector(127 downto 0); 17 | 18 | ciphertext : out std_logic_vector(127 downto 0) 19 | ); 20 | end component aes; 21 | begin 22 | dut : aes 23 | port map ( 24 | key => r_key, 25 | plaintext => r_plaintext, 26 | 27 | ciphertext => r_ciphertext 28 | ); 29 | 30 | process 31 | begin 32 | r_key <= x"000102030405060708090a0b0c0d0e0f"; 33 | r_plaintext <= x"00112233445566778899aabbccddeeff"; 34 | 35 | wait; 36 | end process; 37 | end architecture; 38 | -------------------------------------------------------------------------------- /aes_128128_unrolled/constants.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package constants is 5 | type key_array is array(10 downto 0) of std_logic_vector(127 downto 0); 6 | type ct_array is array(9 downto 0) of std_logic_vector(127 downto 0); 7 | end package; 8 | -------------------------------------------------------------------------------- /katan_3280_unrolled/constants.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package constants is 5 | type ctr_array is array(254 downto 0) of std_logic_vector(7 downto 0); 6 | type key_array is array(254 downto 0) of std_logic_vector(79 downto 0); 7 | type l1_array is array(254 downto 0) of std_logic_vector(12 downto 0); 8 | type l2_array is array(254 downto 0) of std_logic_vector(18 downto 0); 9 | end package; 10 | -------------------------------------------------------------------------------- /katan_3280_unrolled/katan.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use work.constants.all; 4 | 5 | entity katan is 6 | port ( 7 | key : in std_logic_vector(79 downto 0); 8 | plaintext : in std_logic_vector(31 downto 0); 9 | 10 | ciphertext : out std_logic_vector(31 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of katan is 15 | signal keys : key_array; 16 | signal ctrs : ctr_array; 17 | signal l1s : l1_array; 18 | signal l2s : l2_array; 19 | 20 | component katan_key is 21 | port ( 22 | keyi : in std_logic_vector(79 downto 0); 23 | keyo : out std_logic_vector(79 downto 0) 24 | ); 25 | end component katan_key; 26 | 27 | component katan_enc is 28 | port ( 29 | key : in std_logic_vector(79 downto 0); 30 | ctri : in std_logic_vector(7 downto 0); 31 | l1i : in std_logic_vector(12 downto 0); 32 | l2i : in std_logic_vector(18 downto 0); 33 | 34 | ctro : out std_logic_vector(7 downto 0); 35 | l1o : out std_logic_vector(12 downto 0); 36 | l2o : out std_logic_vector(18 downto 0) 37 | ); 38 | end component katan_enc; 39 | begin 40 | enc_generate : for i in 0 to 253 generate 41 | enc0 : katan_enc 42 | port map ( 43 | ctri => ctrs(i), 44 | l1i => l1s(i), 45 | l2i => l2s(i), 46 | key => keys(i), 47 | 48 | ctro => ctrs(i+1), 49 | l1o => l1s(i+1), 50 | l2o => l2s(i+1) 51 | ); 52 | end generate; 53 | 54 | key_generate : for i in 0 to 253 generate 55 | key0 : katan_key 56 | port map ( 57 | keyi => keys(i), 58 | keyo => keys(i+1) 59 | ); 60 | end generate; 61 | 62 | enc_process : process(key, plaintext) is 63 | begin 64 | ctrs(0) <= "11111110"; 65 | keys(0) <= key; 66 | l1s(0) <= plaintext(31 downto 19); 67 | l2s(0) <= plaintext(18 downto 0); 68 | end process enc_process; 69 | 70 | ciphertext <= l1s(254) & l2s(254); 71 | end architecture rtl; 72 | -------------------------------------------------------------------------------- /katan_3280_unrolled/katan_enc.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity katan_enc is 5 | port ( 6 | key : in std_logic_vector(79 downto 0); 7 | ctri : in std_logic_vector(7 downto 0); 8 | l1i : in std_logic_vector(12 downto 0); 9 | l2i : in std_logic_vector(18 downto 0); 10 | 11 | ctro : out std_logic_vector(7 downto 0); 12 | l1o : out std_logic_vector(12 downto 0); 13 | l2o : out std_logic_vector(18 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture rtl of katan_enc is 18 | begin 19 | encrypt_process : process (key, ctri, l1i, l2i) is 20 | begin 21 | ctro <= ctri(6 downto 0) & (ctri(7) xor ctri(6) xor ctri(4) xor ctri(2)); 22 | 23 | l1o <= l1i(11 downto 0) & (l2i(18) xor l2i(7) xor (l2i(12) and l2i(10)) xor (l2i(8) and l2i(3)) xor key(78)); 24 | l2o <= l2i(17 downto 0) & (l1i(12) xor l1i(7) xor (l1i(8) and l1i(5)) xor (l1i(3) and ctri(7)) xor key(79)); 25 | end process encrypt_process; 26 | end architecture rtl; 27 | -------------------------------------------------------------------------------- /katan_3280_unrolled/katan_key.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use work.constants.all; 4 | 5 | entity katan_key is 6 | port ( 7 | keyi : in std_logic_vector(79 downto 0); 8 | keyo : out std_logic_vector(79 downto 0) 9 | ); 10 | end entity; 11 | 12 | architecture rtl of katan_key is 13 | begin 14 | lfsr_process : process (keyi) is 15 | begin 16 | keyo <= keyi(77 downto 0) & (keyi(79) xor keyi(60) xor keyi(49) xor keyi(12)) & (keyi(78) xor keyi(59) xor keyi(48) xor keyi(11)); 17 | end process lfsr_process; 18 | end architecture rtl; 19 | -------------------------------------------------------------------------------- /katan_3280_unrolled/katan_tb.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity katan_tb is 5 | end entity; 6 | 7 | architecture test of katan_tb is 8 | signal r_key : std_logic_vector(79 downto 0); 9 | signal r_plaintext : std_logic_vector(31 downto 0); 10 | 11 | signal r_ciphertext : std_logic_vector(31 downto 0); 12 | 13 | component katan is 14 | port ( 15 | key : in std_logic_vector(79 downto 0); 16 | plaintext : in std_logic_vector(31 downto 0); 17 | 18 | ciphertext : out std_logic_vector(31 downto 0) 19 | ); 20 | end component katan; 21 | begin 22 | dut : katan 23 | port map ( 24 | key => r_key, 25 | plaintext => r_plaintext, 26 | 27 | ciphertext => r_ciphertext 28 | ); 29 | 30 | process 31 | begin 32 | r_key <= x"ffffffffffffffffffff"; 33 | r_plaintext <= x"00000000"; 34 | 35 | wait; 36 | end process; 37 | end architecture; 38 | -------------------------------------------------------------------------------- /katan_6480_unrolled/constants.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package constants is 5 | type ctr_array is array(254 downto 0) of std_logic_vector(7 downto 0); 6 | type key_array is array(254 downto 0) of std_logic_vector(79 downto 0); 7 | type l1_array is array(254 downto 0) of std_logic_vector(24 downto 0); 8 | type l2_array is array(254 downto 0) of std_logic_vector(38 downto 0); 9 | end package; 10 | -------------------------------------------------------------------------------- /katan_6480_unrolled/katan.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use work.constants.all; 4 | 5 | entity katan is 6 | port ( 7 | key : in std_logic_vector(79 downto 0); 8 | plaintext : in std_logic_vector(63 downto 0); 9 | 10 | ciphertext : out std_logic_vector(63 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of katan is 15 | signal keys : key_array; 16 | signal ctrs : ctr_array; 17 | signal l1s : l1_array; 18 | signal l2s : l2_array; 19 | 20 | component katan_key is 21 | port ( 22 | keyi : in std_logic_vector(79 downto 0); 23 | keyo : out std_logic_vector(79 downto 0) 24 | ); 25 | end component katan_key; 26 | 27 | component katan_enc is 28 | port ( 29 | key : in std_logic_vector(79 downto 0); 30 | ctri : in std_logic_vector(7 downto 0); 31 | l1i : in std_logic_vector(24 downto 0); 32 | l2i : in std_logic_vector(38 downto 0); 33 | 34 | ctro : out std_logic_vector(7 downto 0); 35 | l1o : out std_logic_vector(24 downto 0); 36 | l2o : out std_logic_vector(38 downto 0) 37 | ); 38 | end component katan_enc; 39 | begin 40 | enc_generate : for i in 0 to 253 generate 41 | enc0 : katan_enc 42 | port map ( 43 | ctri => ctrs(i), 44 | l1i => l1s(i), 45 | l2i => l2s(i), 46 | key => keys(i), 47 | 48 | ctro => ctrs(i+1), 49 | l1o => l1s(i+1), 50 | l2o => l2s(i+1) 51 | ); 52 | end generate; 53 | 54 | key_generate : for i in 0 to 253 generate 55 | key0 : katan_key 56 | port map ( 57 | keyi => keys(i), 58 | keyo => keys(i+1) 59 | ); 60 | end generate; 61 | 62 | enc_process : process(key, plaintext) is 63 | begin 64 | ctrs(0) <= "11111110"; 65 | keys(0) <= key; 66 | l1s(0) <= plaintext(63 downto 39); 67 | l2s(0) <= plaintext(38 downto 0); 68 | end process enc_process; 69 | 70 | ciphertext <= l1s(254) & l2s(254); 71 | end architecture rtl; 72 | -------------------------------------------------------------------------------- /katan_6480_unrolled/katan_enc.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity katan_enc is 5 | port ( 6 | key : in std_logic_vector(79 downto 0); 7 | ctri : in std_logic_vector(7 downto 0); 8 | l1i : in std_logic_vector(24 downto 0); 9 | l2i : in std_logic_vector(38 downto 0); 10 | 11 | ctro : out std_logic_vector(7 downto 0); 12 | l1o : out std_logic_vector(24 downto 0); 13 | l2o : out std_logic_vector(38 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture rtl of katan_enc is 18 | begin 19 | encrypt_process : process (key, ctri, l1i, l2i) is 20 | begin 21 | ctro <= ctri(6 downto 0) & (ctri(7) xor ctri(6) xor ctri(4) xor ctri(2)); 22 | 23 | l1o <= l1i(21 downto 0) 24 | & (l2i(38) xor l2i(25) xor (l2i(33) and l2i(21)) xor (l2i(14) and l2i(9)) xor key(78)) 25 | & (l2i(37) xor l2i(24) xor (l2i(32) and l2i(20)) xor (l2i(13) and l2i(8)) xor key(78)) 26 | & (l2i(36) xor l2i(23) xor (l2i(31) and l2i(19)) xor (l2i(12) and l2i(7)) xor key(78)); 27 | l2o <= l2i(35 downto 0) 28 | & (l1i(24) xor l1i(15) xor (l1i(20) and l1i(11)) xor (l1i(9) and ctri(7)) xor key(79)) 29 | & (l1i(23) xor l1i(14) xor (l1i(19) and l1i(10)) xor (l1i(8) and ctri(7)) xor key(79)) 30 | & (l1i(22) xor l1i(13) xor (l1i(18) and l1i(9)) xor (l1i(7) and ctri(7)) xor key(79)); 31 | end process encrypt_process; 32 | end architecture rtl; 33 | -------------------------------------------------------------------------------- /katan_6480_unrolled/katan_key.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use work.constants.all; 4 | 5 | entity katan_key is 6 | port ( 7 | keyi : in std_logic_vector(79 downto 0); 8 | keyo : out std_logic_vector(79 downto 0) 9 | ); 10 | end entity; 11 | 12 | architecture rtl of katan_key is 13 | begin 14 | lfsr_process : process (keyi) is 15 | begin 16 | keyo <= keyi(77 downto 0) & (keyi(79) xor keyi(60) xor keyi(49) xor keyi(12)) & (keyi(78) xor keyi(59) xor keyi(48) xor keyi(11)); 17 | end process lfsr_process; 18 | end architecture rtl; 19 | -------------------------------------------------------------------------------- /katan_6480_unrolled/katan_tb.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity katan_tb is 5 | end entity; 6 | 7 | architecture test of katan_tb is 8 | signal r_key : std_logic_vector(79 downto 0); 9 | signal r_plaintext : std_logic_vector(63 downto 0); 10 | 11 | signal r_ciphertext : std_logic_vector(63 downto 0); 12 | 13 | component katan is 14 | port ( 15 | key : in std_logic_vector(79 downto 0); 16 | plaintext : in std_logic_vector(63 downto 0); 17 | 18 | ciphertext : out std_logic_vector(63 downto 0) 19 | ); 20 | end component katan; 21 | begin 22 | dut : katan 23 | port map ( 24 | key => r_key, 25 | plaintext => r_plaintext, 26 | 27 | ciphertext => r_ciphertext 28 | ); 29 | 30 | process 31 | begin 32 | r_key <= x"ffffffffffffffffffff"; 33 | r_plaintext <= x"0000000000000000"; 34 | 35 | wait; 36 | end process; 37 | end architecture; 38 | -------------------------------------------------------------------------------- /present_64128_unrolled/constants.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package constants is 5 | type key_array is array(31 downto 0) of std_logic_vector(127 downto 0); 6 | type ct_array is array(31 downto 0) of std_logic_vector(63 downto 0); 7 | end package; 8 | -------------------------------------------------------------------------------- /present_64128_unrolled/present.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use work.constants.all; 4 | 5 | entity present is 6 | port ( 7 | key : in std_logic_vector(127 downto 0); 8 | plaintext : in std_logic_vector(63 downto 0); 9 | 10 | ciphertext : out std_logic_vector(63 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of present is 15 | signal keys : key_array; 16 | signal cts : ct_array; 17 | 18 | component present_key is 19 | generic ( 20 | round_ctr : integer 21 | ); 22 | port ( 23 | keyi : in std_logic_vector(127 downto 0); 24 | keyo : out std_logic_vector(127 downto 0) 25 | ); 26 | end component present_key; 27 | 28 | component present_enc is 29 | port ( 30 | key : in std_logic_vector(127 downto 0); 31 | datai : in std_logic_vector(63 downto 0); 32 | 33 | datao : out std_logic_vector(63 downto 0) 34 | ); 35 | end component present_enc; 36 | begin 37 | enc_generate : for i in 0 to 30 generate 38 | enc0 : present_enc 39 | port map ( 40 | key => keys(i), 41 | datai => cts(i), 42 | 43 | datao => cts(i+1) 44 | ); 45 | end generate; 46 | 47 | key_generate : for i in 0 to 30 generate 48 | key0 : present_key 49 | generic map ( 50 | round_ctr => i+1 51 | ) 52 | port map ( 53 | keyi => keys(i), 54 | keyo => keys(i+1) 55 | ); 56 | end generate; 57 | 58 | enc_process : process(key, plaintext) is 59 | begin 60 | keys(0) <= key; 61 | cts(0) <= plaintext; 62 | end process enc_process; 63 | 64 | ciphertext <= cts(31) xor keys(31)(127 downto 64); 65 | end architecture rtl; 66 | -------------------------------------------------------------------------------- /present_64128_unrolled/present_enc.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity present_enc is 6 | port ( 7 | key : in std_logic_vector(127 downto 0); 8 | datai : in std_logic_vector(63 downto 0); 9 | 10 | datao : out std_logic_vector(63 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of present_enc is 15 | signal sboxi : std_logic_vector(63 downto 0); 16 | signal sboxo : std_logic_vector(63 downto 0); 17 | 18 | component present_sbox 19 | port ( 20 | datai : in std_logic_vector(3 downto 0); 21 | datao : out std_logic_vector(3 downto 0) 22 | ); 23 | end component present_sbox; 24 | 25 | component present_p 26 | port ( 27 | datai : in std_logic_vector(63 downto 0); 28 | datao : out std_logic_vector(63 downto 0) 29 | ); 30 | end component present_p; 31 | begin 32 | sbox_generate : for i in 0 to 15 generate 33 | sbox0 : present_sbox 34 | port map ( 35 | datai => sboxi(4*i+3 downto 4*i), 36 | datao => sboxo(4*i+3 downto 4*i) 37 | ); 38 | end generate; 39 | 40 | p0 : present_p 41 | port map ( 42 | datai => sboxo, 43 | datao => datao 44 | ); 45 | 46 | encrypt_process : process (key, datai) is 47 | begin 48 | sboxi <= datai xor key(127 downto 64); 49 | end process encrypt_process; 50 | end architecture rtl; 51 | -------------------------------------------------------------------------------- /present_64128_unrolled/present_key.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | use work.constants.all; 5 | 6 | entity present_key is 7 | generic ( 8 | round_ctr : integer 9 | ); 10 | port ( 11 | keyi : in std_logic_vector(127 downto 0); 12 | keyo : out std_logic_vector(127 downto 0) 13 | ); 14 | end entity; 15 | 16 | architecture rtl of present_key is 17 | component present_sbox is 18 | port ( 19 | datai : in std_logic_vector(3 downto 0); 20 | datao : out std_logic_vector(3 downto 0) 21 | ); 22 | end component present_sbox; 23 | begin 24 | sbox0 : present_sbox 25 | port map ( 26 | datai => keyi(66 downto 63), 27 | datao => keyo(127 downto 124) 28 | ); 29 | 30 | sbox1 : present_sbox 31 | port map ( 32 | datai => keyi(62 downto 59), 33 | datao => keyo(123 downto 120) 34 | ); 35 | 36 | expand_process : process (keyi) is 37 | begin 38 | keyo(119 downto 0) <= keyi(58 downto 6) & (keyi(5 downto 1) xor std_logic_vector(to_unsigned(round_ctr, 5))) & keyi(0) & keyi(127 downto 67); 39 | end process expand_process; 40 | end architecture rtl; 41 | -------------------------------------------------------------------------------- /present_64128_unrolled/present_p.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity present_p is 5 | port ( 6 | datai : in std_logic_vector(63 downto 0); 7 | datao : out std_logic_vector(63 downto 0) 8 | ); 9 | end entity; 10 | 11 | architecture rtl of present_p is 12 | begin 13 | permute_process : process (datai) is 14 | begin 15 | datao(0) <= datai(0); 16 | datao(16) <= datai(1); 17 | datao(32) <= datai(2); 18 | datao(48) <= datai(3); 19 | datao(1) <= datai(4); 20 | datao(17) <= datai(5); 21 | datao(33) <= datai(6); 22 | datao(49) <= datai(7); 23 | datao(2) <= datai(8); 24 | datao(18) <= datai(9); 25 | datao(34) <= datai(10); 26 | datao(50) <= datai(11); 27 | datao(3) <= datai(12); 28 | datao(19) <= datai(13); 29 | datao(35) <= datai(14); 30 | datao(51) <= datai(15); 31 | datao(4) <= datai(16); 32 | datao(20) <= datai(17); 33 | datao(36) <= datai(18); 34 | datao(52) <= datai(19); 35 | datao(5) <= datai(20); 36 | datao(21) <= datai(21); 37 | datao(37) <= datai(22); 38 | datao(53) <= datai(23); 39 | datao(6) <= datai(24); 40 | datao(22) <= datai(25); 41 | datao(38) <= datai(26); 42 | datao(54) <= datai(27); 43 | datao(7) <= datai(28); 44 | datao(23) <= datai(29); 45 | datao(39) <= datai(30); 46 | datao(55) <= datai(31); 47 | datao(8) <= datai(32); 48 | datao(24) <= datai(33); 49 | datao(40) <= datai(34); 50 | datao(56) <= datai(35); 51 | datao(9) <= datai(36); 52 | datao(25) <= datai(37); 53 | datao(41) <= datai(38); 54 | datao(57) <= datai(39); 55 | datao(10) <= datai(40); 56 | datao(26) <= datai(41); 57 | datao(42) <= datai(42); 58 | datao(58) <= datai(43); 59 | datao(11) <= datai(44); 60 | datao(27) <= datai(45); 61 | datao(43) <= datai(46); 62 | datao(59) <= datai(47); 63 | datao(12) <= datai(48); 64 | datao(28) <= datai(49); 65 | datao(44) <= datai(50); 66 | datao(60) <= datai(51); 67 | datao(13) <= datai(52); 68 | datao(29) <= datai(53); 69 | datao(45) <= datai(54); 70 | datao(61) <= datai(55); 71 | datao(14) <= datai(56); 72 | datao(30) <= datai(57); 73 | datao(46) <= datai(58); 74 | datao(62) <= datai(59); 75 | datao(15) <= datai(60); 76 | datao(31) <= datai(61); 77 | datao(47) <= datai(62); 78 | datao(63) <= datai(63); 79 | end process permute_process; 80 | end architecture rtl; 81 | -------------------------------------------------------------------------------- /present_64128_unrolled/present_sbox.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity present_sbox is 5 | port ( 6 | datai : in std_logic_vector(3 downto 0); 7 | datao : out std_logic_vector(3 downto 0) 8 | ); 9 | end entity; 10 | 11 | architecture rtl of present_sbox is 12 | begin 13 | lookup_process : process (datai) is 14 | begin 15 | lookup_case : case datai is 16 | when x"0" => datao <= x"C"; 17 | when x"1" => datao <= x"5"; 18 | when x"2" => datao <= x"6"; 19 | when x"3" => datao <= x"B"; 20 | when x"4" => datao <= x"9"; 21 | when x"5" => datao <= x"0"; 22 | when x"6" => datao <= x"A"; 23 | when x"7" => datao <= x"D"; 24 | when x"8" => datao <= x"3"; 25 | when x"9" => datao <= x"E"; 26 | when x"A" => datao <= x"F"; 27 | when x"B" => datao <= x"8"; 28 | when x"C" => datao <= x"4"; 29 | when x"D" => datao <= x"7"; 30 | when x"E" => datao <= x"1"; 31 | when x"F" => datao <= x"2"; 32 | 33 | when others => datao <= (others => 'X'); 34 | end case lookup_case; 35 | end process lookup_process; 36 | end architecture rtl; 37 | -------------------------------------------------------------------------------- /present_64128_unrolled/present_tb.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity present_tb is 5 | end entity; 6 | 7 | architecture test of present_tb is 8 | signal r_key : std_logic_vector(127 downto 0); 9 | signal r_plaintext : std_logic_vector(63 downto 0); 10 | 11 | signal r_ciphertext : std_logic_vector(63 downto 0); 12 | 13 | component present is 14 | port ( 15 | key : in std_logic_vector(127 downto 0); 16 | plaintext : in std_logic_vector(63 downto 0); 17 | 18 | ciphertext : out std_logic_vector(63 downto 0) 19 | ); 20 | end component present; 21 | begin 22 | dut : present 23 | port map ( 24 | key => r_key, 25 | plaintext => r_plaintext, 26 | 27 | ciphertext => r_ciphertext 28 | ); 29 | 30 | process 31 | begin 32 | r_key <= x"00000000000000000000000000000000"; 33 | r_plaintext <= x"0000000000000000"; 34 | 35 | wait; 36 | end process; 37 | end architecture; 38 | -------------------------------------------------------------------------------- /present_6480_unrolled/constants.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package constants is 5 | type key_array is array(31 downto 0) of std_logic_vector(79 downto 0); 6 | type ct_array is array(31 downto 0) of std_logic_vector(63 downto 0); 7 | end package; 8 | -------------------------------------------------------------------------------- /present_6480_unrolled/present.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use work.constants.all; 4 | 5 | entity present is 6 | port ( 7 | key : in std_logic_vector(79 downto 0); 8 | plaintext : in std_logic_vector(63 downto 0); 9 | 10 | ciphertext : out std_logic_vector(63 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of present is 15 | signal keys : key_array; 16 | signal cts : ct_array; 17 | 18 | component present_key is 19 | generic ( 20 | round_ctr : integer 21 | ); 22 | port ( 23 | keyi : in std_logic_vector(79 downto 0); 24 | keyo : out std_logic_vector(79 downto 0) 25 | ); 26 | end component present_key; 27 | 28 | component present_enc is 29 | port ( 30 | key : in std_logic_vector(79 downto 0); 31 | datai : in std_logic_vector(63 downto 0); 32 | 33 | datao : out std_logic_vector(63 downto 0) 34 | ); 35 | end component present_enc; 36 | begin 37 | enc_generate : for i in 0 to 30 generate 38 | enc0 : present_enc 39 | port map ( 40 | key => keys(i), 41 | datai => cts(i), 42 | 43 | datao => cts(i+1) 44 | ); 45 | end generate; 46 | 47 | key_generate : for i in 0 to 30 generate 48 | key0 : present_key 49 | generic map ( 50 | round_ctr => i+1 51 | ) 52 | port map ( 53 | keyi => keys(i), 54 | keyo => keys(i+1) 55 | ); 56 | end generate; 57 | 58 | enc_process : process(key, plaintext) is 59 | begin 60 | keys(0) <= key; 61 | cts(0) <= plaintext; 62 | end process enc_process; 63 | 64 | ciphertext <= cts(31) xor keys(31)(79 downto 16); 65 | end architecture rtl; 66 | -------------------------------------------------------------------------------- /present_6480_unrolled/present_enc.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity present_enc is 6 | port ( 7 | key : in std_logic_vector(79 downto 0); 8 | datai : in std_logic_vector(63 downto 0); 9 | 10 | datao : out std_logic_vector(63 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of present_enc is 15 | signal sboxi : std_logic_vector(63 downto 0); 16 | signal sboxo : std_logic_vector(63 downto 0); 17 | 18 | component present_sbox 19 | port ( 20 | datai : in std_logic_vector(3 downto 0); 21 | datao : out std_logic_vector(3 downto 0) 22 | ); 23 | end component present_sbox; 24 | 25 | component present_p 26 | port ( 27 | datai : in std_logic_vector(63 downto 0); 28 | datao : out std_logic_vector(63 downto 0) 29 | ); 30 | end component present_p; 31 | begin 32 | sbox_generate : for i in 0 to 15 generate 33 | sbox0 : present_sbox 34 | port map ( 35 | datai => sboxi(4*i+3 downto 4*i), 36 | datao => sboxo(4*i+3 downto 4*i) 37 | ); 38 | end generate; 39 | 40 | p0 : present_p 41 | port map ( 42 | datai => sboxo, 43 | datao => datao 44 | ); 45 | 46 | encrypt_process : process (key, datai) is 47 | begin 48 | sboxi <= datai xor key(79 downto 16); 49 | end process encrypt_process; 50 | end architecture rtl; 51 | -------------------------------------------------------------------------------- /present_6480_unrolled/present_key.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | use work.constants.all; 5 | 6 | entity present_key is 7 | generic ( 8 | round_ctr : integer 9 | ); 10 | port ( 11 | keyi : in std_logic_vector(79 downto 0); 12 | keyo : out std_logic_vector(79 downto 0) 13 | ); 14 | end entity; 15 | 16 | architecture rtl of present_key is 17 | component present_sbox is 18 | port ( 19 | datai : in std_logic_vector(3 downto 0); 20 | datao : out std_logic_vector(3 downto 0) 21 | ); 22 | end component present_sbox; 23 | begin 24 | sbox0 : present_sbox 25 | port map ( 26 | datai => keyi(18 downto 15), 27 | datao => keyo(79 downto 76) 28 | ); 29 | 30 | expand_process : process (keyi) is 31 | begin 32 | keyo(75 downto 0) <= keyi(14 downto 0) & keyi(79 downto 39) & (keyi(38 downto 34) xor std_logic_vector(to_unsigned(round_ctr, 5))) & keyi(33 downto 19); 33 | end process expand_process; 34 | end architecture rtl; 35 | -------------------------------------------------------------------------------- /present_6480_unrolled/present_p.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity present_p is 5 | port ( 6 | datai : in std_logic_vector(63 downto 0); 7 | datao : out std_logic_vector(63 downto 0) 8 | ); 9 | end entity; 10 | 11 | architecture rtl of present_p is 12 | begin 13 | permute_process : process (datai) is 14 | begin 15 | datao(0) <= datai(0); 16 | datao(16) <= datai(1); 17 | datao(32) <= datai(2); 18 | datao(48) <= datai(3); 19 | datao(1) <= datai(4); 20 | datao(17) <= datai(5); 21 | datao(33) <= datai(6); 22 | datao(49) <= datai(7); 23 | datao(2) <= datai(8); 24 | datao(18) <= datai(9); 25 | datao(34) <= datai(10); 26 | datao(50) <= datai(11); 27 | datao(3) <= datai(12); 28 | datao(19) <= datai(13); 29 | datao(35) <= datai(14); 30 | datao(51) <= datai(15); 31 | datao(4) <= datai(16); 32 | datao(20) <= datai(17); 33 | datao(36) <= datai(18); 34 | datao(52) <= datai(19); 35 | datao(5) <= datai(20); 36 | datao(21) <= datai(21); 37 | datao(37) <= datai(22); 38 | datao(53) <= datai(23); 39 | datao(6) <= datai(24); 40 | datao(22) <= datai(25); 41 | datao(38) <= datai(26); 42 | datao(54) <= datai(27); 43 | datao(7) <= datai(28); 44 | datao(23) <= datai(29); 45 | datao(39) <= datai(30); 46 | datao(55) <= datai(31); 47 | datao(8) <= datai(32); 48 | datao(24) <= datai(33); 49 | datao(40) <= datai(34); 50 | datao(56) <= datai(35); 51 | datao(9) <= datai(36); 52 | datao(25) <= datai(37); 53 | datao(41) <= datai(38); 54 | datao(57) <= datai(39); 55 | datao(10) <= datai(40); 56 | datao(26) <= datai(41); 57 | datao(42) <= datai(42); 58 | datao(58) <= datai(43); 59 | datao(11) <= datai(44); 60 | datao(27) <= datai(45); 61 | datao(43) <= datai(46); 62 | datao(59) <= datai(47); 63 | datao(12) <= datai(48); 64 | datao(28) <= datai(49); 65 | datao(44) <= datai(50); 66 | datao(60) <= datai(51); 67 | datao(13) <= datai(52); 68 | datao(29) <= datai(53); 69 | datao(45) <= datai(54); 70 | datao(61) <= datai(55); 71 | datao(14) <= datai(56); 72 | datao(30) <= datai(57); 73 | datao(46) <= datai(58); 74 | datao(62) <= datai(59); 75 | datao(15) <= datai(60); 76 | datao(31) <= datai(61); 77 | datao(47) <= datai(62); 78 | datao(63) <= datai(63); 79 | end process permute_process; 80 | end architecture rtl; 81 | -------------------------------------------------------------------------------- /present_6480_unrolled/present_sbox.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity present_sbox is 5 | port ( 6 | datai : in std_logic_vector(3 downto 0); 7 | datao : out std_logic_vector(3 downto 0) 8 | ); 9 | end entity; 10 | 11 | architecture rtl of present_sbox is 12 | begin 13 | lookup_process : process (datai) is 14 | begin 15 | lookup_case : case datai is 16 | when x"0" => datao <= x"C"; 17 | when x"1" => datao <= x"5"; 18 | when x"2" => datao <= x"6"; 19 | when x"3" => datao <= x"B"; 20 | when x"4" => datao <= x"9"; 21 | when x"5" => datao <= x"0"; 22 | when x"6" => datao <= x"A"; 23 | when x"7" => datao <= x"D"; 24 | when x"8" => datao <= x"3"; 25 | when x"9" => datao <= x"E"; 26 | when x"A" => datao <= x"F"; 27 | when x"B" => datao <= x"8"; 28 | when x"C" => datao <= x"4"; 29 | when x"D" => datao <= x"7"; 30 | when x"E" => datao <= x"1"; 31 | when x"F" => datao <= x"2"; 32 | 33 | when others => datao <= (others => 'X'); 34 | end case lookup_case; 35 | end process lookup_process; 36 | end architecture rtl; 37 | -------------------------------------------------------------------------------- /present_6480_unrolled/present_tb.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity present_tb is 5 | end entity; 6 | 7 | architecture test of present_tb is 8 | signal r_key : std_logic_vector(79 downto 0); 9 | signal r_plaintext : std_logic_vector(63 downto 0); 10 | 11 | signal r_ciphertext : std_logic_vector(63 downto 0); 12 | 13 | component present is 14 | port ( 15 | key : in std_logic_vector(79 downto 0); 16 | plaintext : in std_logic_vector(63 downto 0); 17 | 18 | ciphertext : out std_logic_vector(63 downto 0) 19 | ); 20 | end component present; 21 | begin 22 | dut : present 23 | port map ( 24 | key => r_key, 25 | plaintext => r_plaintext, 26 | 27 | ciphertext => r_ciphertext 28 | ); 29 | 30 | process 31 | begin 32 | r_key <= x"00000000000000000000"; 33 | r_plaintext <= x"0000000000000000"; 34 | 35 | wait; 36 | end process; 37 | end architecture; 38 | -------------------------------------------------------------------------------- /prince_unrolled/constants.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package constants is 5 | type round_array is array(5 downto 0) of std_logic_vector(63 downto 0); 6 | end package; 7 | -------------------------------------------------------------------------------- /prince_unrolled/prince.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use work.constants.all; 4 | 5 | entity prince is 6 | port ( 7 | key : in std_logic_vector(127 downto 0); 8 | plaintext : in std_logic_vector(63 downto 0); 9 | 10 | ciphertext : out std_logic_vector(63 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of prince is 15 | signal k_1 : std_logic_vector(63 downto 0); 16 | 17 | signal round : round_array; 18 | signal matrixi : std_logic_vector(63 downto 0); 19 | signal matrixo : std_logic_vector(63 downto 0); 20 | signal round_i : round_array; 21 | 22 | component prince_round is 23 | generic ( 24 | round_ctr : integer 25 | ); 26 | port ( 27 | key : in std_logic_vector(63 downto 0); 28 | datai : in std_logic_vector(63 downto 0); 29 | 30 | datao : out std_logic_vector(63 downto 0) 31 | ); 32 | end component prince_round; 33 | 34 | component prince_sbox is 35 | port ( 36 | datai : in std_logic_vector(3 downto 0); 37 | datao : out std_logic_vector(3 downto 0) 38 | ); 39 | end component prince_sbox; 40 | 41 | component prince_matrix_p is 42 | port ( 43 | datai : in std_logic_vector(63 downto 0); 44 | datao : out std_logic_vector(63 downto 0) 45 | ); 46 | end component prince_matrix_p; 47 | 48 | component prince_sbox_i is 49 | port ( 50 | datai : in std_logic_vector(3 downto 0); 51 | datao : out std_logic_vector(3 downto 0) 52 | ); 53 | end component prince_sbox_i; 54 | 55 | component prince_round_i is 56 | generic ( 57 | round_ctr : integer 58 | ); 59 | port ( 60 | key : in std_logic_vector(63 downto 0); 61 | datai : in std_logic_vector(63 downto 0); 62 | 63 | datao : out std_logic_vector(63 downto 0) 64 | ); 65 | end component prince_round_i; 66 | begin 67 | round_generate : for i in 1 to 5 generate 68 | round0 : prince_round 69 | generic map ( 70 | round_ctr => i 71 | ) 72 | port map ( 73 | key => k_1, 74 | datai => round(i-1), 75 | 76 | datao => round(i) 77 | ); 78 | end generate; 79 | 80 | sbox_generate : for i in 0 to 15 generate 81 | sbox0 : prince_sbox 82 | port map ( 83 | datai => round(5)(4*i+3 downto 4*i), 84 | datao => matrixi(4*i+3 downto 4*i) 85 | ); 86 | end generate; 87 | 88 | matrix0 : prince_matrix_p 89 | port map ( 90 | datai => matrixi, 91 | datao => matrixo 92 | ); 93 | 94 | sbox_i_generate : for i in 0 to 15 generate 95 | sbox_i0 : prince_sbox_i 96 | port map ( 97 | datai => matrixo(4*i+3 downto 4*i), 98 | datao => round_i(0)(4*i+3 downto 4*i) 99 | ); 100 | end generate; 101 | 102 | round_i_generate : for i in 6 to 10 generate 103 | round0 : prince_round_i 104 | generic map ( 105 | round_ctr => i 106 | ) 107 | port map ( 108 | key => k_1, 109 | datai => round_i(i-6), 110 | 111 | datao => round_i(i-5) 112 | ); 113 | end generate; 114 | 115 | enc_process : process(key, plaintext) is 116 | begin 117 | k_1 <= key(63 downto 0); 118 | round(0) <= plaintext xor key(127 downto 64) xor key(63 downto 0) xor x"0000000000000000"; 119 | end process enc_process; 120 | 121 | ciphertext <= round_i(5) xor x"c0ac29b7c97c50dd" xor key(63 downto 0) xor (key(64) & key(127 downto 66) & (key(65) xor key(127))); 122 | end architecture rtl; 123 | -------------------------------------------------------------------------------- /prince_unrolled/prince_matrix.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity prince_matrix_p is 5 | port ( 6 | datai : in std_logic_vector(63 downto 0); 7 | datao : out std_logic_vector(63 downto 0) 8 | ); 9 | end entity; 10 | 11 | architecture rtl of prince_matrix_p is 12 | begin 13 | mul_process : process (datai) is 14 | begin 15 | datao(63) <= datai(59) xor datai(55) xor datai(51); 16 | datao(62) <= datai(62) xor datai(54) xor datai(50); 17 | datao(61) <= datai(61) xor datai(57) xor datai(49); 18 | datao(60) <= datai(60) xor datai(56) xor datai(52); 19 | datao(59) <= datai(63) xor datai(59) xor datai(55); 20 | datao(58) <= datai(58) xor datai(54) xor datai(50); 21 | datao(57) <= datai(61) xor datai(53) xor datai(49); 22 | datao(56) <= datai(60) xor datai(56) xor datai(48); 23 | datao(55) <= datai(63) xor datai(59) xor datai(51); 24 | datao(54) <= datai(62) xor datai(58) xor datai(54); 25 | datao(53) <= datai(57) xor datai(53) xor datai(49); 26 | datao(52) <= datai(60) xor datai(52) xor datai(48); 27 | datao(51) <= datai(63) xor datai(55) xor datai(51); 28 | datao(50) <= datai(62) xor datai(58) xor datai(50); 29 | datao(49) <= datai(61) xor datai(57) xor datai(53); 30 | datao(48) <= datai(56) xor datai(52) xor datai(48); 31 | datao(47) <= datai(47) xor datai(43) xor datai(39); 32 | datao(46) <= datai(42) xor datai(38) xor datai(34); 33 | datao(45) <= datai(45) xor datai(37) xor datai(33); 34 | datao(44) <= datai(44) xor datai(40) xor datai(32); 35 | datao(43) <= datai(47) xor datai(43) xor datai(35); 36 | datao(42) <= datai(46) xor datai(42) xor datai(38); 37 | datao(41) <= datai(41) xor datai(37) xor datai(33); 38 | datao(40) <= datai(44) xor datai(36) xor datai(32); 39 | datao(39) <= datai(47) xor datai(39) xor datai(35); 40 | datao(38) <= datai(46) xor datai(42) xor datai(34); 41 | datao(37) <= datai(45) xor datai(41) xor datai(37); 42 | datao(36) <= datai(40) xor datai(36) xor datai(32); 43 | datao(35) <= datai(43) xor datai(39) xor datai(35); 44 | datao(34) <= datai(46) xor datai(38) xor datai(34); 45 | datao(33) <= datai(45) xor datai(41) xor datai(33); 46 | datao(32) <= datai(44) xor datai(40) xor datai(36); 47 | datao(31) <= datai(31) xor datai(27) xor datai(23); 48 | datao(30) <= datai(26) xor datai(22) xor datai(18); 49 | datao(29) <= datai(29) xor datai(21) xor datai(17); 50 | datao(28) <= datai(28) xor datai(24) xor datai(16); 51 | datao(27) <= datai(31) xor datai(27) xor datai(19); 52 | datao(26) <= datai(30) xor datai(26) xor datai(22); 53 | datao(25) <= datai(25) xor datai(21) xor datai(17); 54 | datao(24) <= datai(28) xor datai(20) xor datai(16); 55 | datao(23) <= datai(31) xor datai(23) xor datai(19); 56 | datao(22) <= datai(30) xor datai(26) xor datai(18); 57 | datao(21) <= datai(29) xor datai(25) xor datai(21); 58 | datao(20) <= datai(24) xor datai(20) xor datai(16); 59 | datao(19) <= datai(27) xor datai(23) xor datai(19); 60 | datao(18) <= datai(30) xor datai(22) xor datai(18); 61 | datao(17) <= datai(29) xor datai(25) xor datai(17); 62 | datao(16) <= datai(28) xor datai(24) xor datai(20); 63 | datao(15) <= datai(11) xor datai(7) xor datai(3); 64 | datao(14) <= datai(14) xor datai(6) xor datai(2); 65 | datao(13) <= datai(13) xor datai(9) xor datai(1); 66 | datao(12) <= datai(12) xor datai(8) xor datai(4); 67 | datao(11) <= datai(15) xor datai(11) xor datai(7); 68 | datao(10) <= datai(10) xor datai(6) xor datai(2); 69 | datao(9) <= datai(13) xor datai(5) xor datai(1); 70 | datao(8) <= datai(12) xor datai(8) xor datai(0); 71 | datao(7) <= datai(15) xor datai(11) xor datai(3); 72 | datao(6) <= datai(14) xor datai(10) xor datai(6); 73 | datao(5) <= datai(9) xor datai(5) xor datai(1); 74 | datao(4) <= datai(12) xor datai(4) xor datai(0); 75 | datao(3) <= datai(15) xor datai(7) xor datai(3); 76 | datao(2) <= datai(14) xor datai(10) xor datai(2); 77 | datao(1) <= datai(13) xor datai(9) xor datai(5); 78 | datao(0) <= datai(8) xor datai(4) xor datai(0); 79 | end process mul_process; 80 | end architecture rtl; 81 | 82 | library ieee; 83 | use ieee.std_logic_1164.all; 84 | 85 | entity prince_matrix is 86 | port ( 87 | datai : in std_logic_vector(63 downto 0); 88 | datao : out std_logic_vector(63 downto 0) 89 | ); 90 | end entity; 91 | 92 | architecture rtl of prince_matrix is 93 | begin 94 | mul_process : process (datai) is 95 | begin 96 | datao(63) <= datai(59) xor datai(55) xor datai(51); 97 | datao(62) <= datai(62) xor datai(54) xor datai(50); 98 | datao(61) <= datai(61) xor datai(57) xor datai(49); 99 | datao(60) <= datai(60) xor datai(56) xor datai(52); 100 | datao(59) <= datai(47) xor datai(43) xor datai(35); 101 | datao(58) <= datai(46) xor datai(42) xor datai(38); 102 | datao(57) <= datai(41) xor datai(37) xor datai(33); 103 | datao(56) <= datai(44) xor datai(36) xor datai(32); 104 | datao(55) <= datai(31) xor datai(23) xor datai(19); 105 | datao(54) <= datai(30) xor datai(26) xor datai(18); 106 | datao(53) <= datai(29) xor datai(25) xor datai(21); 107 | datao(52) <= datai(24) xor datai(20) xor datai(16); 108 | datao(51) <= datai(15) xor datai(7) xor datai(3); 109 | datao(50) <= datai(14) xor datai(10) xor datai(2); 110 | datao(49) <= datai(13) xor datai(9) xor datai(5); 111 | datao(48) <= datai(8) xor datai(4) xor datai(0); 112 | datao(47) <= datai(47) xor datai(43) xor datai(39); 113 | datao(46) <= datai(42) xor datai(38) xor datai(34); 114 | datao(45) <= datai(45) xor datai(37) xor datai(33); 115 | datao(44) <= datai(44) xor datai(40) xor datai(32); 116 | datao(43) <= datai(31) xor datai(27) xor datai(19); 117 | datao(42) <= datai(30) xor datai(26) xor datai(22); 118 | datao(41) <= datai(25) xor datai(21) xor datai(17); 119 | datao(40) <= datai(28) xor datai(20) xor datai(16); 120 | datao(39) <= datai(15) xor datai(11) xor datai(3); 121 | datao(38) <= datai(14) xor datai(10) xor datai(6); 122 | datao(37) <= datai(9) xor datai(5) xor datai(1); 123 | datao(36) <= datai(12) xor datai(4) xor datai(0); 124 | datao(35) <= datai(63) xor datai(55) xor datai(51); 125 | datao(34) <= datai(62) xor datai(58) xor datai(50); 126 | datao(33) <= datai(61) xor datai(57) xor datai(53); 127 | datao(32) <= datai(56) xor datai(52) xor datai(48); 128 | datao(31) <= datai(31) xor datai(27) xor datai(23); 129 | datao(30) <= datai(26) xor datai(22) xor datai(18); 130 | datao(29) <= datai(29) xor datai(21) xor datai(17); 131 | datao(28) <= datai(28) xor datai(24) xor datai(16); 132 | datao(27) <= datai(15) xor datai(11) xor datai(7); 133 | datao(26) <= datai(10) xor datai(6) xor datai(2); 134 | datao(25) <= datai(13) xor datai(5) xor datai(1); 135 | datao(24) <= datai(12) xor datai(8) xor datai(0); 136 | datao(23) <= datai(63) xor datai(59) xor datai(51); 137 | datao(22) <= datai(62) xor datai(58) xor datai(54); 138 | datao(21) <= datai(57) xor datai(53) xor datai(49); 139 | datao(20) <= datai(60) xor datai(52) xor datai(48); 140 | datao(19) <= datai(43) xor datai(39) xor datai(35); 141 | datao(18) <= datai(46) xor datai(38) xor datai(34); 142 | datao(17) <= datai(45) xor datai(41) xor datai(33); 143 | datao(16) <= datai(44) xor datai(40) xor datai(36); 144 | datao(15) <= datai(11) xor datai(7) xor datai(3); 145 | datao(14) <= datai(14) xor datai(6) xor datai(2); 146 | datao(13) <= datai(13) xor datai(9) xor datai(1); 147 | datao(12) <= datai(12) xor datai(8) xor datai(4); 148 | datao(11) <= datai(63) xor datai(59) xor datai(55); 149 | datao(10) <= datai(58) xor datai(54) xor datai(50); 150 | datao(9) <= datai(61) xor datai(53) xor datai(49); 151 | datao(8) <= datai(60) xor datai(56) xor datai(48); 152 | datao(7) <= datai(47) xor datai(39) xor datai(35); 153 | datao(6) <= datai(46) xor datai(42) xor datai(34); 154 | datao(5) <= datai(45) xor datai(41) xor datai(37); 155 | datao(4) <= datai(40) xor datai(36) xor datai(32); 156 | datao(3) <= datai(27) xor datai(23) xor datai(19); 157 | datao(2) <= datai(30) xor datai(22) xor datai(18); 158 | datao(1) <= datai(29) xor datai(25) xor datai(17); 159 | datao(0) <= datai(28) xor datai(24) xor datai(20); 160 | end process mul_process; 161 | end architecture rtl; 162 | 163 | library ieee; 164 | use ieee.std_logic_1164.all; 165 | 166 | entity prince_matrix_i is 167 | port ( 168 | datai : in std_logic_vector(63 downto 0); 169 | datao : out std_logic_vector(63 downto 0) 170 | ); 171 | end entity; 172 | 173 | architecture rtl of prince_matrix_i is 174 | begin 175 | mul_process : process (datai) is 176 | begin 177 | datao(63) <= datai(35) xor datai(23) xor datai(11); 178 | datao(62) <= datai(62) xor datai(34) xor datai(22); 179 | datao(61) <= datai(61) xor datai(33) xor datai(9); 180 | datao(60) <= datai(60) xor datai(20) xor datai(8); 181 | datao(59) <= datai(63) xor datai(23) xor datai(11); 182 | datao(58) <= datai(34) xor datai(22) xor datai(10); 183 | datao(57) <= datai(61) xor datai(33) xor datai(21); 184 | datao(56) <= datai(60) xor datai(32) xor datai(8); 185 | datao(55) <= datai(63) xor datai(35) xor datai(11); 186 | datao(54) <= datai(62) xor datai(22) xor datai(10); 187 | datao(53) <= datai(33) xor datai(21) xor datai(9); 188 | datao(52) <= datai(60) xor datai(32) xor datai(20); 189 | datao(51) <= datai(63) xor datai(35) xor datai(23); 190 | datao(50) <= datai(62) xor datai(34) xor datai(10); 191 | datao(49) <= datai(61) xor datai(21) xor datai(9); 192 | datao(48) <= datai(32) xor datai(20) xor datai(8); 193 | datao(47) <= datai(59) xor datai(47) xor datai(7); 194 | datao(46) <= datai(58) xor datai(18) xor datai(6); 195 | datao(45) <= datai(45) xor datai(17) xor datai(5); 196 | datao(44) <= datai(56) xor datai(44) xor datai(16); 197 | datao(43) <= datai(59) xor datai(47) xor datai(19); 198 | datao(42) <= datai(58) xor datai(46) xor datai(6); 199 | datao(41) <= datai(57) xor datai(17) xor datai(5); 200 | datao(40) <= datai(44) xor datai(16) xor datai(4); 201 | datao(39) <= datai(47) xor datai(19) xor datai(7); 202 | datao(38) <= datai(58) xor datai(46) xor datai(18); 203 | datao(37) <= datai(57) xor datai(45) xor datai(5); 204 | datao(36) <= datai(56) xor datai(16) xor datai(4); 205 | datao(35) <= datai(59) xor datai(19) xor datai(7); 206 | datao(34) <= datai(46) xor datai(18) xor datai(6); 207 | datao(33) <= datai(57) xor datai(45) xor datai(17); 208 | datao(32) <= datai(56) xor datai(44) xor datai(4); 209 | datao(31) <= datai(55) xor datai(43) xor datai(31); 210 | datao(30) <= datai(54) xor datai(42) xor datai(2); 211 | datao(29) <= datai(53) xor datai(29) xor datai(1); 212 | datao(28) <= datai(40) xor datai(28) xor datai(0); 213 | datao(27) <= datai(43) xor datai(31) xor datai(3); 214 | datao(26) <= datai(54) xor datai(42) xor datai(30); 215 | datao(25) <= datai(53) xor datai(41) xor datai(1); 216 | datao(24) <= datai(52) xor datai(28) xor datai(0); 217 | datao(23) <= datai(55) xor datai(31) xor datai(3); 218 | datao(22) <= datai(42) xor datai(30) xor datai(2); 219 | datao(21) <= datai(53) xor datai(41) xor datai(29); 220 | datao(20) <= datai(52) xor datai(40) xor datai(0); 221 | datao(19) <= datai(55) xor datai(43) xor datai(3); 222 | datao(18) <= datai(54) xor datai(30) xor datai(2); 223 | datao(17) <= datai(41) xor datai(29) xor datai(1); 224 | datao(16) <= datai(52) xor datai(40) xor datai(28); 225 | datao(15) <= datai(51) xor datai(39) xor datai(27); 226 | datao(14) <= datai(50) xor datai(38) xor datai(14); 227 | datao(13) <= datai(49) xor datai(25) xor datai(13); 228 | datao(12) <= datai(36) xor datai(24) xor datai(12); 229 | datao(11) <= datai(39) xor datai(27) xor datai(15); 230 | datao(10) <= datai(50) xor datai(38) xor datai(26); 231 | datao(9) <= datai(49) xor datai(37) xor datai(13); 232 | datao(8) <= datai(48) xor datai(24) xor datai(12); 233 | datao(7) <= datai(51) xor datai(27) xor datai(15); 234 | datao(6) <= datai(38) xor datai(26) xor datai(14); 235 | datao(5) <= datai(49) xor datai(37) xor datai(25); 236 | datao(4) <= datai(48) xor datai(36) xor datai(12); 237 | datao(3) <= datai(51) xor datai(39) xor datai(15); 238 | datao(2) <= datai(50) xor datai(26) xor datai(14); 239 | datao(1) <= datai(37) xor datai(25) xor datai(13); 240 | datao(0) <= datai(48) xor datai(36) xor datai(24); 241 | end process mul_process; 242 | end architecture rtl; 243 | -------------------------------------------------------------------------------- /prince_unrolled/prince_round.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity prince_round is 5 | generic ( 6 | round_ctr : integer 7 | ); 8 | port ( 9 | key : in std_logic_vector(63 downto 0); 10 | datai : in std_logic_vector(63 downto 0); 11 | 12 | datao : out std_logic_vector(63 downto 0) 13 | ); 14 | end entity; 15 | 16 | architecture rtl of prince_round is 17 | signal sbox : std_logic_vector(63 downto 0); 18 | signal matrix : std_logic_vector(63 downto 0); 19 | 20 | signal rc : std_logic_vector(63 downto 0); 21 | 22 | component prince_sbox is 23 | port ( 24 | datai : in std_logic_vector(3 downto 0); 25 | datao : out std_logic_vector(3 downto 0) 26 | ); 27 | end component prince_sbox; 28 | 29 | component prince_matrix is 30 | port ( 31 | datai : in std_logic_vector(63 downto 0); 32 | datao : out std_logic_vector(63 downto 0) 33 | ); 34 | end component prince_matrix; 35 | begin 36 | sbox_generate : for i in 0 to 15 generate 37 | sbox0 : prince_sbox 38 | port map ( 39 | datai => datai(4*i+3 downto 4*i), 40 | datao => sbox(4*i+3 downto 4*i) 41 | ); 42 | end generate; 43 | 44 | matrix0 : prince_matrix 45 | port map ( 46 | datai => sbox, 47 | datao => matrix 48 | ); 49 | 50 | round_process : process (datai) is 51 | begin 52 | rc_case : case round_ctr is 53 | when 1 => rc <= x"13198a2e03707344"; 54 | when 2 => rc <= x"a4093822299f31d0"; 55 | when 3 => rc <= x"082efa98ec4e6c89"; 56 | when 4 => rc <= x"452821e638d01377"; 57 | when 5 => rc <= x"be5466cf34e90c6c"; 58 | 59 | when others => rc <= (others => 'X'); 60 | end case rc_case; 61 | end process round_process; 62 | 63 | datao <= matrix xor rc xor key; 64 | end architecture rtl; 65 | 66 | library ieee; 67 | use ieee.std_logic_1164.all; 68 | 69 | entity prince_round_i is 70 | generic ( 71 | round_ctr : integer 72 | ); 73 | port ( 74 | key : in std_logic_vector(63 downto 0); 75 | datai : in std_logic_vector(63 downto 0); 76 | 77 | datao : out std_logic_vector(63 downto 0) 78 | ); 79 | end entity; 80 | 81 | architecture rtl of prince_round_i is 82 | signal matrixi : std_logic_vector(63 downto 0); 83 | signal matrixo : std_logic_vector(63 downto 0); 84 | 85 | signal rc : std_logic_vector(63 downto 0); 86 | 87 | component prince_sbox_i is 88 | port ( 89 | datai : in std_logic_vector(3 downto 0); 90 | datao : out std_logic_vector(3 downto 0) 91 | ); 92 | end component prince_sbox_i; 93 | 94 | component prince_matrix_i is 95 | port ( 96 | datai : in std_logic_vector(63 downto 0); 97 | datao : out std_logic_vector(63 downto 0) 98 | ); 99 | end component prince_matrix_i; 100 | begin 101 | sbox_i_generate : for i in 0 to 15 generate 102 | sbox_i0 : prince_sbox_i 103 | port map ( 104 | datai => matrixo(4*i+3 downto 4*i), 105 | datao => datao(4*i+3 downto 4*i) 106 | ); 107 | end generate; 108 | 109 | matrix0 : prince_matrix_i 110 | port map ( 111 | datai => matrixi, 112 | datao => matrixo 113 | ); 114 | 115 | round_process : process (datai) is 116 | begin 117 | rc_case : case round_ctr is 118 | when 6 => rc <= x"7ef84f78fd955cb1"; 119 | when 7 => rc <= x"85840851f1ac43aa"; 120 | when 8 => rc <= x"c882d32f25323c54"; 121 | when 9 => rc <= x"64a51195e0e3610d"; 122 | when 10 => rc <= x"d3b5a399ca0c2399"; 123 | 124 | when others => rc <= (others => 'X'); 125 | end case rc_case; 126 | end process round_process; 127 | 128 | matrixi <= datai xor key xor rc; 129 | end architecture rtl; 130 | -------------------------------------------------------------------------------- /prince_unrolled/prince_sbox.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity prince_sbox is 5 | port ( 6 | datai : in std_logic_vector(3 downto 0); 7 | datao : out std_logic_vector(3 downto 0) 8 | ); 9 | end entity; 10 | 11 | architecture rtl of prince_sbox is 12 | begin 13 | lookup_process : process (datai) is 14 | begin 15 | lookup_case : case datai is 16 | when x"0" => datao <= x"B"; 17 | when x"1" => datao <= x"F"; 18 | when x"2" => datao <= x"3"; 19 | when x"3" => datao <= x"2"; 20 | when x"4" => datao <= x"A"; 21 | when x"5" => datao <= x"C"; 22 | when x"6" => datao <= x"9"; 23 | when x"7" => datao <= x"1"; 24 | when x"8" => datao <= x"6"; 25 | when x"9" => datao <= x"7"; 26 | when x"A" => datao <= x"8"; 27 | when x"B" => datao <= x"0"; 28 | when x"C" => datao <= x"E"; 29 | when x"D" => datao <= x"5"; 30 | when x"E" => datao <= x"D"; 31 | when x"F" => datao <= x"4"; 32 | 33 | when others => datao <= (others => 'X'); 34 | end case lookup_case; 35 | end process lookup_process; 36 | end architecture rtl; 37 | 38 | library ieee; 39 | use ieee.std_logic_1164.all; 40 | 41 | entity prince_sbox_i is 42 | port ( 43 | datai : in std_logic_vector(3 downto 0); 44 | datao : out std_logic_vector(3 downto 0) 45 | ); 46 | end entity; 47 | 48 | architecture rtl of prince_sbox_i is 49 | begin 50 | lookup_process : process (datai) is 51 | begin 52 | lookup_case : case datai is 53 | when x"0" => datao <= x"B"; 54 | when x"1" => datao <= x"7"; 55 | when x"2" => datao <= x"3"; 56 | when x"3" => datao <= x"2"; 57 | when x"4" => datao <= x"F"; 58 | when x"5" => datao <= x"D"; 59 | when x"6" => datao <= x"8"; 60 | when x"7" => datao <= x"9"; 61 | when x"8" => datao <= x"A"; 62 | when x"9" => datao <= x"6"; 63 | when x"A" => datao <= x"4"; 64 | when x"B" => datao <= x"0"; 65 | when x"C" => datao <= x"5"; 66 | when x"D" => datao <= x"E"; 67 | when x"E" => datao <= x"C"; 68 | when x"F" => datao <= x"1"; 69 | 70 | when others => datao <= (others => 'X'); 71 | end case lookup_case; 72 | end process lookup_process; 73 | end architecture rtl; 74 | -------------------------------------------------------------------------------- /prince_unrolled/prince_tb.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity prince_tb is 5 | end entity; 6 | 7 | architecture test of prince_tb is 8 | signal r_key : std_logic_vector(127 downto 0); 9 | signal r_plaintext : std_logic_vector(63 downto 0); 10 | 11 | signal r_ciphertext : std_logic_vector(63 downto 0); 12 | 13 | component prince is 14 | port ( 15 | key : in std_logic_vector(127 downto 0); 16 | plaintext : in std_logic_vector(63 downto 0); 17 | 18 | ciphertext : out std_logic_vector(63 downto 0) 19 | ); 20 | end component prince; 21 | begin 22 | dut : prince 23 | port map ( 24 | key => r_key, 25 | plaintext => r_plaintext, 26 | 27 | ciphertext => r_ciphertext 28 | ); 29 | 30 | process 31 | begin 32 | r_key <= x"00000000000000000000000000000000"; 33 | r_plaintext <= x"0000000000000000"; 34 | 35 | wait; 36 | end process; 37 | end architecture; 38 | -------------------------------------------------------------------------------- /prince_unrolled/prince_wrapper.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity prince_wrapper is 5 | end entity; 6 | 7 | architecture rtl of prince_wrapper is 8 | signal r_key : std_logic_vector(127 downto 0); 9 | signal r_plaintext : std_logic_vector(63 downto 0); 10 | 11 | signal r_ciphertext : std_logic_vector(63 downto 0); 12 | 13 | component prince is 14 | port ( 15 | key : in std_logic_vector(127 downto 0); 16 | plaintext : in std_logic_vector(63 downto 0); 17 | 18 | ciphertext : out std_logic_vector(63 downto 0) 19 | ); 20 | end component prince; 21 | begin 22 | prince0 : prince 23 | port map ( 24 | key => r_key, 25 | plaintext => r_plaintext, 26 | 27 | ciphertext => r_ciphertext 28 | ); 29 | end architecture; 30 | -------------------------------------------------------------------------------- /simon_3264_unrolled/constants.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package constants is 5 | type key_array is array(31 downto 0) of std_logic_vector(15 downto 0); 6 | type ct_array is array(32 downto 0) of std_logic_vector(31 downto 0); 7 | end package; 8 | -------------------------------------------------------------------------------- /simon_3264_unrolled/simon.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use work.constants.all; 4 | 5 | entity simon is 6 | port ( 7 | key : in std_logic_vector(63 downto 0); 8 | plaintext : in std_logic_vector(31 downto 0); 9 | 10 | ciphertext : out std_logic_vector(31 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of simon is 15 | signal keys : key_array; 16 | signal cts : ct_array; 17 | 18 | component simon_key is 19 | generic ( 20 | round_ctr : integer 21 | ); 22 | port ( 23 | k_0, k_1, k_3 : in std_logic_vector(15 downto 0); 24 | key : out std_logic_vector(15 downto 0) 25 | ); 26 | end component simon_key; 27 | 28 | component simon_enc is 29 | port ( 30 | key : in std_logic_vector(15 downto 0); 31 | xy : in std_logic_vector(31 downto 0); 32 | 33 | yx : out std_logic_vector(31 downto 0) 34 | ); 35 | end component simon_enc; 36 | begin 37 | enc_generate : for i in 0 to 31 generate 38 | enc0 : simon_enc 39 | port map ( 40 | xy => cts(i), 41 | key => keys(i), 42 | 43 | yx => cts(i+1) 44 | ); 45 | end generate; 46 | 47 | key_generate : for i in 4 to 31 generate 48 | key0 : simon_key 49 | generic map ( 50 | round_ctr => i-4 51 | ) 52 | port map ( 53 | k_0 => keys(i-4), 54 | k_1 => keys(i-3), 55 | k_3 => keys(i-1), 56 | 57 | key => keys(i) 58 | ); 59 | end generate; 60 | 61 | enc_process : process(key, plaintext) is 62 | begin 63 | keys(0) <= key(15 downto 0); 64 | keys(1) <= key(31 downto 16); 65 | keys(2) <= key(47 downto 32); 66 | keys(3) <= key(63 downto 48); 67 | 68 | cts(0) <= plaintext; 69 | end process enc_process; 70 | 71 | ciphertext <= cts(32); 72 | end architecture rtl; 73 | -------------------------------------------------------------------------------- /simon_3264_unrolled/simon_enc.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity simon_enc is 5 | port ( 6 | key : in std_logic_vector(15 downto 0); 7 | xy : in std_logic_vector(31 downto 0); 8 | 9 | yx : out std_logic_vector(31 downto 0) 10 | ); 11 | end entity; 12 | 13 | architecture rtl of simon_enc is 14 | function rotl(value: std_logic_vector(15 downto 0); places: integer) return std_logic_vector is 15 | begin 16 | return value(15-places downto 0) & value(15 downto 15-(places-1)); 17 | end function rotl; 18 | begin 19 | encrypt_process : process (key, xy) is 20 | begin 21 | yx(15 downto 0) <= xy(31 downto 16); 22 | yx(31 downto 16) <= xy(15 downto 0) xor (rotl(xy(31 downto 16), 1) and rotl(xy(31 downto 16), 8)) xor rotl(xy(31 downto 16), 2) xor key; 23 | end process encrypt_process; 24 | end architecture rtl; 25 | -------------------------------------------------------------------------------- /simon_3264_unrolled/simon_key.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use work.constants.all; 4 | 5 | entity simon_key is 6 | generic ( 7 | round_ctr : integer 8 | ); 9 | port ( 10 | k_0, k_1, k_3 : in std_logic_vector(15 downto 0); 11 | key : out std_logic_vector(15 downto 0) 12 | ); 13 | end entity; 14 | 15 | architecture rtl of simon_key is 16 | function rotr(value: std_logic_vector(15 downto 0); places: integer) return std_logic_vector is 17 | begin 18 | return value(places-1 downto 0) & value(15 downto places); 19 | end function rotr; 20 | begin 21 | expand_process : process (k_0, k_1, k_3) is 22 | -- 23 | -- Note 24 | -- ---- 25 | -- The value given in the paper is longer (62 bits), but was truncated 26 | -- to the length needed for 32-bit blocks. The shortened string was also 27 | -- reversed so that (27-round_ctr) could be changed into round_ctr 28 | -- on line 27. 29 | -- 30 | constant Z : std_logic_vector(27 downto 0) := b"0011100001101010010001011111"; 31 | 32 | variable tmp : std_logic_vector(15 downto 0); 33 | variable vec_z : std_logic_vector(15 downto 0); 34 | variable three : std_logic_vector(15 downto 0); 35 | begin 36 | tmp := rotr(k_3, 3) xor k_1; 37 | tmp := tmp xor rotr(tmp, 1); 38 | 39 | vec_z := (0 => Z(round_ctr), others => '0'); 40 | three := (0 => '1', 1 => '1', others => '0'); 41 | 42 | key <= (not k_0) xor vec_z xor tmp xor three; 43 | end process expand_process; 44 | end architecture rtl; 45 | -------------------------------------------------------------------------------- /simon_3264_unrolled/simon_tb.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity simon_tb is 5 | end entity; 6 | 7 | architecture test of simon_tb is 8 | signal r_key : std_logic_vector(63 downto 0); 9 | signal r_plaintext : std_logic_vector(31 downto 0); 10 | 11 | signal r_ciphertext : std_logic_vector(31 downto 0); 12 | 13 | component simon is 14 | port ( 15 | key : in std_logic_vector(63 downto 0); 16 | plaintext : in std_logic_vector(31 downto 0); 17 | 18 | ciphertext : out std_logic_vector(31 downto 0) 19 | ); 20 | end component simon; 21 | begin 22 | dut : simon 23 | port map ( 24 | key => r_key, 25 | plaintext => r_plaintext, 26 | 27 | ciphertext => r_ciphertext 28 | ); 29 | 30 | process 31 | begin 32 | r_key <= x"1918111009080100"; 33 | r_plaintext <= x"65656877"; 34 | 35 | wait; 36 | end process; 37 | end architecture; 38 | -------------------------------------------------------------------------------- /simon_64128_unrolled/constants.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package constants is 5 | type key_array is array(43 downto 0) of std_logic_vector(31 downto 0); 6 | type ct_array is array(44 downto 0) of std_logic_vector(63 downto 0); 7 | end package; 8 | -------------------------------------------------------------------------------- /simon_64128_unrolled/simon.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use work.constants.all; 4 | 5 | entity simon is 6 | port ( 7 | key : in std_logic_vector(127 downto 0); 8 | plaintext : in std_logic_vector(63 downto 0); 9 | 10 | ciphertext : out std_logic_vector(63 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of simon is 15 | signal keys : key_array; 16 | signal cts : ct_array; 17 | 18 | component simon_key is 19 | generic ( 20 | round_ctr : integer 21 | ); 22 | port ( 23 | k_0, k_1, k_3 : in std_logic_vector(31 downto 0); 24 | key : out std_logic_vector(31 downto 0) 25 | ); 26 | end component simon_key; 27 | 28 | component simon_enc is 29 | port ( 30 | key : in std_logic_vector(31 downto 0); 31 | xy : in std_logic_vector(63 downto 0); 32 | 33 | yx : out std_logic_vector(63 downto 0) 34 | ); 35 | end component simon_enc; 36 | begin 37 | enc_generate : for i in 0 to 43 generate 38 | enc0 : simon_enc 39 | port map ( 40 | xy => cts(i), 41 | key => keys(i), 42 | 43 | yx => cts(i+1) 44 | ); 45 | end generate; 46 | 47 | key_generate : for i in 4 to 43 generate 48 | key0 : simon_key 49 | generic map ( 50 | round_ctr => i-4 51 | ) 52 | port map ( 53 | k_0 => keys(i-4), 54 | k_1 => keys(i-3), 55 | k_3 => keys(i-1), 56 | 57 | key => keys(i) 58 | ); 59 | end generate; 60 | 61 | enc_process : process(key, plaintext) is 62 | begin 63 | keys(0) <= key(31 downto 0); 64 | keys(1) <= key(63 downto 32); 65 | keys(2) <= key(95 downto 64); 66 | keys(3) <= key(127 downto 96); 67 | 68 | cts(0) <= plaintext; 69 | end process enc_process; 70 | 71 | ciphertext <= cts(44); 72 | end architecture rtl; 73 | -------------------------------------------------------------------------------- /simon_64128_unrolled/simon_enc.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity simon_enc is 5 | port ( 6 | key : in std_logic_vector(31 downto 0); 7 | xy : in std_logic_vector(63 downto 0); 8 | 9 | yx : out std_logic_vector(63 downto 0) 10 | ); 11 | end entity; 12 | 13 | architecture rtl of simon_enc is 14 | function rotl(value: std_logic_vector(31 downto 0); places: integer) return std_logic_vector is 15 | begin 16 | return value(31-places downto 0) & value(31 downto 31-(places-1)); 17 | end function rotl; 18 | begin 19 | encrypt_process : process (key, xy) is 20 | begin 21 | yx(31 downto 0) <= xy(63 downto 32); 22 | yx(63 downto 32) <= xy(31 downto 0) xor (rotl(xy(63 downto 32), 1) and rotl(xy(63 downto 32), 8)) xor rotl(xy(63 downto 32), 2) xor key; 23 | end process encrypt_process; 24 | end architecture rtl; 25 | -------------------------------------------------------------------------------- /simon_64128_unrolled/simon_key.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use work.constants.all; 4 | 5 | entity simon_key is 6 | generic ( 7 | round_ctr : integer 8 | ); 9 | port ( 10 | k_0, k_1, k_3 : in std_logic_vector(31 downto 0); 11 | key : out std_logic_vector(31 downto 0) 12 | ); 13 | end entity; 14 | 15 | architecture rtl of simon_key is 16 | function rotr(value: std_logic_vector(31 downto 0); places: integer) return std_logic_vector is 17 | begin 18 | return value(places-1 downto 0) & value(31 downto places); 19 | end function rotr; 20 | begin 21 | expand_process : process (k_0, k_1, k_3) is 22 | -- 23 | -- Note 24 | -- ---- 25 | -- The value given in the paper is longer (62 bits), but was truncated 26 | -- to the length needed for 64-bit blocks. The shortened string was also 27 | -- reversed so that (39-round_ctr) could be changed into round_ctr 28 | -- on line 27. 29 | -- 30 | constant Z : std_logic_vector(39 downto 0) := b"0001001000000111101001100011010111011011"; 31 | 32 | variable tmp : std_logic_vector(31 downto 0); 33 | variable vec_z : std_logic_vector(31 downto 0); 34 | variable three : std_logic_vector(31 downto 0); 35 | begin 36 | tmp := rotr(k_3, 3) xor k_1; 37 | tmp := tmp xor rotr(tmp, 1); 38 | 39 | vec_z := (0 => Z(round_ctr), others => '0'); 40 | three := (0 => '1', 1 => '1', others => '0'); 41 | 42 | key <= (not k_0) xor vec_z xor tmp xor three; 43 | end process expand_process; 44 | end architecture rtl; 45 | -------------------------------------------------------------------------------- /simon_64128_unrolled/simon_tb.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity simon_tb is 5 | end entity; 6 | 7 | architecture test of simon_tb is 8 | signal r_key : std_logic_vector(127 downto 0); 9 | signal r_plaintext : std_logic_vector(63 downto 0); 10 | 11 | signal r_ciphertext : std_logic_vector(63 downto 0); 12 | 13 | component simon is 14 | port ( 15 | key : in std_logic_vector(127 downto 0); 16 | plaintext : in std_logic_vector(63 downto 0); 17 | 18 | ciphertext : out std_logic_vector(63 downto 0) 19 | ); 20 | end component simon; 21 | begin 22 | dut : simon 23 | port map ( 24 | key => r_key, 25 | plaintext => r_plaintext, 26 | 27 | ciphertext => r_ciphertext 28 | ); 29 | 30 | process 31 | begin 32 | r_key <= x"1b1a1918131211100b0a090803020100"; 33 | r_plaintext <= x"656b696c20646e75"; 34 | 35 | wait; 36 | end process; 37 | end architecture; 38 | -------------------------------------------------------------------------------- /speck_3264_unrolled/constants.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package constants is 5 | type key_array is array(22 downto 0) of std_logic_vector(15 downto 0); 6 | type l_array is array(23 downto 0) of std_logic_vector(15 downto 0); 7 | type ct_array is array(22 downto 0) of std_logic_vector(31 downto 0); 8 | end package; 9 | -------------------------------------------------------------------------------- /speck_3264_unrolled/speck.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use work.constants.all; 4 | 5 | entity speck is 6 | port ( 7 | key : in std_logic_vector(63 downto 0); 8 | plaintext : in std_logic_vector(31 downto 0); 9 | 10 | ciphertext : out std_logic_vector(31 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of speck is 15 | signal keys : key_array; 16 | signal ls : l_array; 17 | signal cts : ct_array; 18 | 19 | component speck_key is 20 | generic ( 21 | round_ctr : integer 22 | ); 23 | port ( 24 | keyi, li : in std_logic_vector(15 downto 0); 25 | keyo, lo : out std_logic_vector(15 downto 0) 26 | ); 27 | end component speck_key; 28 | 29 | component speck_enc is 30 | port ( 31 | key : in std_logic_vector(15 downto 0); 32 | xy : in std_logic_vector(31 downto 0); 33 | 34 | yx : out std_logic_vector(31 downto 0) 35 | ); 36 | end component speck_enc; 37 | begin 38 | enc_generate : for i in 0 to 21 generate 39 | enc0 : speck_enc 40 | port map ( 41 | xy => cts(i), 42 | key => keys(i), 43 | 44 | yx => cts(i+1) 45 | ); 46 | end generate; 47 | 48 | key_generate : for i in 0 to 20 generate 49 | key0 : speck_key 50 | generic map ( 51 | round_ctr => i 52 | ) 53 | port map ( 54 | keyi => keys(i), 55 | li => ls(i), 56 | 57 | keyo => keys(i+1), 58 | lo => ls(i+3) 59 | ); 60 | end generate; 61 | 62 | enc_process : process(key, plaintext) is 63 | begin 64 | keys(0) <= key(15 downto 0); 65 | 66 | ls(0) <= key(31 downto 16); 67 | ls(1) <= key(47 downto 32); 68 | ls(2) <= key(63 downto 48); 69 | 70 | cts(0) <= plaintext; 71 | end process enc_process; 72 | 73 | ciphertext <= cts(22); 74 | end architecture rtl; 75 | -------------------------------------------------------------------------------- /speck_3264_unrolled/speck_enc.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity speck_enc is 6 | port ( 7 | key : in std_logic_vector(15 downto 0); 8 | xy : in std_logic_vector(31 downto 0); 9 | 10 | yx : out std_logic_vector(31 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of speck_enc is 15 | function rotl(value: std_logic_vector(15 downto 0); places: integer) return std_logic_vector is 16 | begin 17 | return value(15-places downto 0) & value(15 downto 15-(places-1)); 18 | end function rotl; 19 | 20 | function rotr(value: std_logic_vector(15 downto 0); places: integer) return std_logic_vector is 21 | begin 22 | return value(places-1 downto 0) & value(15 downto places); 23 | end function rotr; 24 | begin 25 | encrypt_process : process (key, xy) is 26 | variable x_z : std_logic_vector(15 downto 0); 27 | begin 28 | x_z := std_logic_vector(unsigned(rotr(xy(31 downto 16), 7)) + unsigned(xy(15 downto 0))) xor key; 29 | 30 | yx(31 downto 16) <= x_z; 31 | yx(15 downto 0) <= rotl(xy(15 downto 0), 2) xor x_z; 32 | end process encrypt_process; 33 | end architecture rtl; 34 | -------------------------------------------------------------------------------- /speck_3264_unrolled/speck_key.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | use work.constants.all; 5 | 6 | entity speck_key is 7 | generic ( 8 | round_ctr : integer 9 | ); 10 | port ( 11 | keyi, li : in std_logic_vector(15 downto 0); 12 | keyo, lo : out std_logic_vector(15 downto 0) 13 | ); 14 | end entity; 15 | 16 | architecture rtl of speck_key is 17 | function rotl(value: std_logic_vector(15 downto 0); places: integer) return std_logic_vector is 18 | begin 19 | return value(15-places downto 0) & value(15 downto 15-(places-1)); 20 | end function rotl; 21 | 22 | function rotr(value: std_logic_vector(15 downto 0); places: integer) return std_logic_vector is 23 | begin 24 | return value(places-1 downto 0) & value(15 downto places); 25 | end function rotr; 26 | begin 27 | expand_process : process (keyi, li) is 28 | variable lo_z : std_logic_vector(15 downto 0); 29 | begin 30 | lo_z := std_logic_vector(unsigned(keyi) + unsigned(rotr(li, 7))) xor std_logic_vector(to_unsigned(round_ctr, 16)); 31 | 32 | lo <= lo_z; 33 | keyo <= rotl(keyi, 2) xor lo_z; 34 | end process expand_process; 35 | end architecture rtl; 36 | -------------------------------------------------------------------------------- /speck_3264_unrolled/speck_tb.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity speck_tb is 5 | end entity; 6 | 7 | architecture test of speck_tb is 8 | signal r_key : std_logic_vector(63 downto 0); 9 | signal r_plaintext : std_logic_vector(31 downto 0); 10 | 11 | signal r_ciphertext : std_logic_vector(31 downto 0); 12 | 13 | component speck is 14 | port ( 15 | key : in std_logic_vector(63 downto 0); 16 | plaintext : in std_logic_vector(31 downto 0); 17 | 18 | ciphertext : out std_logic_vector(31 downto 0) 19 | ); 20 | end component speck; 21 | begin 22 | dut : speck 23 | port map ( 24 | key => r_key, 25 | plaintext => r_plaintext, 26 | 27 | ciphertext => r_ciphertext 28 | ); 29 | 30 | process 31 | begin 32 | r_key <= x"1918111009080100"; 33 | r_plaintext <= x"6574694c"; 34 | 35 | wait; 36 | end process; 37 | end architecture; 38 | -------------------------------------------------------------------------------- /speck_64128_unrolled/constants.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | package constants is 5 | type key_array is array(27 downto 0) of std_logic_vector(31 downto 0); 6 | type l_array is array(28 downto 0) of std_logic_vector(31 downto 0); 7 | type ct_array is array(27 downto 0) of std_logic_vector(63 downto 0); 8 | end package; 9 | -------------------------------------------------------------------------------- /speck_64128_unrolled/speck.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use work.constants.all; 4 | 5 | entity speck is 6 | port ( 7 | key : in std_logic_vector(127 downto 0); 8 | plaintext : in std_logic_vector(63 downto 0); 9 | 10 | ciphertext : out std_logic_vector(63 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of speck is 15 | signal keys : key_array; 16 | signal ls : l_array; 17 | signal cts : ct_array; 18 | 19 | component speck_key is 20 | generic ( 21 | round_ctr : integer 22 | ); 23 | port ( 24 | keyi, li : in std_logic_vector(31 downto 0); 25 | keyo, lo : out std_logic_vector(31 downto 0) 26 | ); 27 | end component speck_key; 28 | 29 | component speck_enc is 30 | port ( 31 | key : in std_logic_vector(31 downto 0); 32 | xy : in std_logic_vector(63 downto 0); 33 | 34 | yx : out std_logic_vector(63 downto 0) 35 | ); 36 | end component speck_enc; 37 | begin 38 | enc_generate : for i in 0 to 26 generate 39 | enc0 : speck_enc 40 | port map ( 41 | xy => cts(i), 42 | key => keys(i), 43 | 44 | yx => cts(i+1) 45 | ); 46 | end generate; 47 | 48 | key_generate : for i in 0 to 25 generate 49 | key0 : speck_key 50 | generic map ( 51 | round_ctr => i 52 | ) 53 | port map ( 54 | keyi => keys(i), 55 | li => ls(i), 56 | 57 | keyo => keys(i+1), 58 | lo => ls(i+3) 59 | ); 60 | end generate; 61 | 62 | enc_process : process(key, plaintext) is 63 | begin 64 | keys(0) <= key(31 downto 0); 65 | 66 | ls(0) <= key(63 downto 32); 67 | ls(1) <= key(95 downto 64); 68 | ls(2) <= key(127 downto 96); 69 | 70 | cts(0) <= plaintext; 71 | end process enc_process; 72 | 73 | ciphertext <= cts(27); 74 | end architecture rtl; 75 | -------------------------------------------------------------------------------- /speck_64128_unrolled/speck_enc.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity speck_enc is 6 | port ( 7 | key : in std_logic_vector(31 downto 0); 8 | xy : in std_logic_vector(63 downto 0); 9 | 10 | yx : out std_logic_vector(63 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture rtl of speck_enc is 15 | function rotl(value: std_logic_vector(31 downto 0); places: integer) return std_logic_vector is 16 | begin 17 | return value(31-places downto 0) & value(31 downto 31-(places-1)); 18 | end function rotl; 19 | 20 | function rotr(value: std_logic_vector(31 downto 0); places: integer) return std_logic_vector is 21 | begin 22 | return value(places-1 downto 0) & value(31 downto places); 23 | end function rotr; 24 | begin 25 | encrypt_process : process (key, xy) is 26 | variable x_z : std_logic_vector(31 downto 0); 27 | begin 28 | x_z := std_logic_vector(unsigned(rotr(xy(63 downto 32), 8)) + unsigned(xy(31 downto 0))) xor key; 29 | 30 | yx(63 downto 32) <= x_z; 31 | yx(31 downto 0) <= rotl(xy(31 downto 0), 3) xor x_z; 32 | end process encrypt_process; 33 | end architecture rtl; 34 | -------------------------------------------------------------------------------- /speck_64128_unrolled/speck_key.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | use work.constants.all; 5 | 6 | entity speck_key is 7 | generic ( 8 | round_ctr : integer 9 | ); 10 | port ( 11 | keyi, li : in std_logic_vector(31 downto 0); 12 | keyo, lo : out std_logic_vector(31 downto 0) 13 | ); 14 | end entity; 15 | 16 | architecture rtl of speck_key is 17 | function rotl(value: std_logic_vector(31 downto 0); places: integer) return std_logic_vector is 18 | begin 19 | return value(31-places downto 0) & value(31 downto 31-(places-1)); 20 | end function rotl; 21 | 22 | function rotr(value: std_logic_vector(31 downto 0); places: integer) return std_logic_vector is 23 | begin 24 | return value(places-1 downto 0) & value(31 downto places); 25 | end function rotr; 26 | begin 27 | expand_process : process (keyi, li) is 28 | variable lo_z : std_logic_vector(31 downto 0); 29 | begin 30 | lo_z := std_logic_vector(unsigned(keyi) + unsigned(rotr(li, 8))) xor std_logic_vector(to_unsigned(round_ctr, 32)); 31 | 32 | lo <= lo_z; 33 | keyo <= rotl(keyi, 3) xor lo_z; 34 | end process expand_process; 35 | end architecture rtl; 36 | -------------------------------------------------------------------------------- /speck_64128_unrolled/speck_tb.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity speck_tb is 5 | end entity; 6 | 7 | architecture test of speck_tb is 8 | signal r_key : std_logic_vector(127 downto 0); 9 | signal r_plaintext : std_logic_vector(63 downto 0); 10 | 11 | signal r_ciphertext : std_logic_vector(63 downto 0); 12 | 13 | component speck is 14 | port ( 15 | key : in std_logic_vector(127 downto 0); 16 | plaintext : in std_logic_vector(63 downto 0); 17 | 18 | ciphertext : out std_logic_vector(63 downto 0) 19 | ); 20 | end component speck; 21 | begin 22 | dut : speck 23 | port map ( 24 | key => r_key, 25 | plaintext => r_plaintext, 26 | 27 | ciphertext => r_ciphertext 28 | ); 29 | 30 | process 31 | begin 32 | r_key <= x"1b1a1918131211100b0a090803020100"; 33 | r_plaintext <= x"3b7265747475432d"; 34 | 35 | wait; 36 | end process; 37 | end architecture; 38 | --------------------------------------------------------------------------------