├── .gitignore ├── LICENSE.txt ├── README.md ├── build.sh ├── requirements.txt ├── rtl ├── mc_simlib.v ├── mc_techlib.v └── timing.jsonc ├── src ├── assembly.py ├── fit.py ├── utils.py └── yosys_techmap.py ├── structures ├── mc_a0dff1_cell.nbt ├── mc_a1dff1_cell.nbt ├── mc_adff_input.nbt ├── mc_dff31.nbt ├── mc_uand16.nbt ├── mc_unor16.nbt ├── mc_uor16.nbt ├── mc_uxor16.nbt ├── mc_uxor4.nbt ├── mc_uxor8.nbt └── mc_xor.nbt ├── tests └── rtl │ ├── test_techmap_dff.sv │ └── test_techmap_ureduce.sv ├── typings └── pyosys │ └── libyosys │ └── __init__.pyi └── v2mc.ys /.gitignore: -------------------------------------------------------------------------------- 1 | build/ 2 | show/ 3 | *.log 4 | *.pyc 5 | .venv/ 6 | __pycache__/ 7 | -------------------------------------------------------------------------------- /LICENSE.txt: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Verilog to Minecraft Redstone 2 | This project provides Minecraft redstone as a synthesis target for Verilog 3 | 4 | ## Goal 5 | Fully synthesize all synthesizable Verilog. This includes both combinational and sequential logic - flip-flops and all that jazz. 6 | 7 | This project is purely for technology mapping, placement, routing, or some combination thereof. Analysis & elaboration of Verilog is done by Yosys, and technology mapping is done with Yosys. 8 | 9 | ## Dependencies 10 | The following must be in your `PATH`: 11 | * Python 3 12 | * Yosys 0.47 built with Python support (`make ENABLE_PYOSYS=1 && make install`) 13 | 14 | We require pyosys (`python3 setup.py install` at root of Yosys repository, which you should already have from building it) in order to access the Yosys internal representation of RTL designs. 15 | 16 | We require the dependencies in `requirements.txt` in order to manipulate NBT structures. 17 | 18 | ## I/O Format 19 | For input, we take one or more Verilog HDL design files. For output, we produce a Minecraft structure file. 20 | 21 | ## Technology mapping 22 | Currently we map the following [Yosys internal cells](https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/formats/cell_library.html#rtl-cells) to custom primitives: 23 | * `$dff, $sdff, $sdffe` → `MC_DFF31` 24 | * `$adff, $adffe` → `MC_ADFF31` 25 | 26 | Redstone signal strength is the main factor leading to the limitation of `WIDTH` to 31 (15 signal strength, in two directions, separated by a hard-powered block) when any input/output is a number of bits independent of `WIDTH`. The technology mapping process reduces, for example, a 64-bit `$dff` to two 31-bit and one 2-bit `MC_DFF31`s. 27 | 28 | All others we allow `techmap` to map to [Yosys internal gates](https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/formats/cell_library.html#gates), which we then map to custom primitives: 29 | -------------------------------------------------------------------------------- /build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | if [ $# -lt 2 ]; then 4 | echo "usage: $0 " >&2 5 | exit 1 6 | fi 7 | 8 | TOP=$1 9 | shift 10 | 11 | mkdir -p build show 12 | 13 | echo "read_verilog -sv $*" > tmp.ys 14 | echo "hierarchy -check -top $TOP" >> tmp.ys 15 | cat v2mc.ys >> tmp.ys 16 | yosys -s tmp.ys 17 | rm tmp.ys 18 | -------------------------------------------------------------------------------- /requirements.txt: -------------------------------------------------------------------------------- 1 | nbt-structure-utils 2 | -------------------------------------------------------------------------------- /rtl/mc_simlib.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | // 100ms = 1 redstone tick 3 | // 50ms = 1 game tick, but the integer can only be 1, 10, or 100 4 | `timescale 100ms/10ms 5 | 6 | // CLK: positive-edge 7 | // tech mapping converts negedge to posedge with an inverter 8 | module MC_DFF31 (CLK, D, Q); 9 | parameter WIDTH = 1; 10 | 11 | input wire CLK; 12 | input wire [WIDTH-1:0] D; 13 | output reg [WIDTH-1:0] Q; 14 | 15 | always @(posedge CLK) begin 16 | Q <= D; 17 | end 18 | endmodule 19 | 20 | // CLK: positive-edge 21 | // ARST: active-high 22 | // ARST_VALUE: any arbitrary bit pattern of correct WIDTH 23 | // tech mapping converts from negedge and active-low with inverters 24 | module MC_ADFF31 (CLK, ARST, D, Q); 25 | parameter WIDTH = 1; 26 | parameter ARST_VALUE = {WIDTH{1'b0}}; 27 | 28 | input wire CLK, ARST; 29 | input wire [WIDTH-1:0] D; 30 | output reg [WIDTH-1:0] Q; 31 | 32 | always @(posedge CLK or posedge ARST) begin 33 | if (ARST) begin 34 | Q <= ARST_VALUE; 35 | end else begin 36 | Q <= D; 37 | end 38 | end 39 | endmodule 40 | 41 | module MC_UAND16 (A, Y); 42 | parameter WIDTH = 2; 43 | 44 | input wire [WIDTH-1:0] A; 45 | output wire Y; 46 | 47 | assign Y = &A; 48 | endmodule 49 | 50 | module MC_UNOR16 (A, Y); 51 | parameter WIDTH = 2; 52 | 53 | input wire [WIDTH-1:0] A; 54 | output wire Y; 55 | 56 | assign Y = !A; 57 | endmodule 58 | 59 | module MC_UOR16 (A, Y); 60 | parameter WIDTH = 2; 61 | 62 | input wire [WIDTH-1:0] A; 63 | output wire Y; 64 | 65 | assign Y = |A; 66 | endmodule 67 | 68 | module MC_UXOR2 (A, Y); 69 | input wire [1:0] A; 70 | output wire Y; 71 | 72 | assign Y = ^A; 73 | endmodule 74 | 75 | module MC_UXOR4 (A, Y); 76 | parameter WIDTH = 3; 77 | 78 | input wire [WIDTH-1:0] A; 79 | output wire Y; 80 | 81 | assign Y = ^A; 82 | endmodule 83 | 84 | module MC_UXOR8 (A, Y); 85 | parameter WIDTH = 5; 86 | 87 | input wire [WIDTH-1:0] A; 88 | output wire Y; 89 | 90 | assign Y = ^A; 91 | endmodule 92 | 93 | module MC_UXOR16 (A, Y); 94 | parameter WIDTH = 7; 95 | 96 | input wire [WIDTH-1:0] A; 97 | output wire Y; 98 | 99 | assign Y = ^A; 100 | endmodule 101 | -------------------------------------------------------------------------------- /rtl/mc_techlib.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module \$dff (CLK, D, Q); 4 | parameter WIDTH = 1; 5 | parameter CLK_POLARITY = 1'b1; 6 | 7 | input wire CLK; 8 | (* force_downto *) 9 | input wire [WIDTH-1:0] D; 10 | (* force_downto *) 11 | output wire [WIDTH-1:0] Q; 12 | 13 | wire _TECHMAP_FAIL_ = WIDTH < 1; 14 | 15 | function integer min; 16 | input integer a, b; 17 | begin 18 | if (a < b) min = a; 19 | else min = b; 20 | end 21 | endfunction 22 | 23 | wire _clk; 24 | 25 | genvar i; 26 | generate 27 | if (CLK_POLARITY) begin 28 | assign _clk = CLK; 29 | end else begin 30 | assign _clk = ~CLK; 31 | end 32 | 33 | for (i = 0; i <= WIDTH/31; i++) begin 34 | MC_DFF31 #( 35 | .WIDTH(min(WIDTH - (31 * i), 31)), 36 | ) dff ( 37 | .CLK(_clk), 38 | .D(D[31 * i +: min(WIDTH - (31 * i), 31)]), 39 | .Q(Q[31 * i +: min(WIDTH - (31 * i), 31)]) 40 | ); 41 | end 42 | endgenerate 43 | endmodule 44 | 45 | module \$adff (CLK, ARST, D, Q); 46 | parameter WIDTH = 1; 47 | parameter CLK_POLARITY = 1'b1; 48 | parameter ARST_POLARITY = 1'b1; 49 | parameter ARST_VALUE = {WIDTH{1'b0}}; 50 | 51 | input wire CLK, ARST; 52 | (* force_downto *) 53 | input wire [WIDTH-1:0] D; 54 | (* force_downto *) 55 | output wire [WIDTH-1:0] Q; 56 | 57 | wire _TECHMAP_FAIL_ = WIDTH < 1; 58 | 59 | function integer min; 60 | input integer a, b; 61 | begin 62 | if (a < b) min = a; 63 | else min = b; 64 | end 65 | endfunction 66 | 67 | wire _clk, _arst; 68 | 69 | genvar i; 70 | generate 71 | if (CLK_POLARITY) begin 72 | assign _clk = CLK; 73 | end else begin 74 | assign _clk = ~CLK; 75 | end 76 | if (ARST_POLARITY) begin 77 | assign _arst = ARST; 78 | end else begin 79 | assign _arst = ~ARST; 80 | end 81 | 82 | for (i = 0; i <= WIDTH/31; i++) begin 83 | MC_ADFF31 #( 84 | .WIDTH(min(WIDTH - (31 * i), 31)), 85 | .ARST_VALUE(ARST_VALUE) 86 | ) dff ( 87 | .CLK(_clk), 88 | .ARST(_arst), 89 | .D(D[31 * i +: min(WIDTH - (31 * i), 31)]), 90 | .Q(Q[31 * i +: min(WIDTH - (31 * i), 31)]) 91 | ); 92 | end 93 | endgenerate 94 | endmodule 95 | 96 | module \$sdff (CLK, SRST, D, Q); 97 | parameter WIDTH = 1; 98 | parameter CLK_POLARITY = 1'b1; 99 | parameter SRST_POLARITY = 1'b1; 100 | parameter SRST_VALUE = {WIDTH{1'b0}}; 101 | 102 | input wire CLK, SRST; 103 | (* force_downto *) 104 | input wire [WIDTH-1:0] D; 105 | (* force_downto *) 106 | output wire [WIDTH-1:0] Q; 107 | 108 | wire _srst; 109 | 110 | generate 111 | if (SRST_POLARITY) begin 112 | assign _srst = SRST; 113 | end else begin 114 | assign _srst = ~SRST; 115 | end 116 | endgenerate 117 | 118 | \$dff #( 119 | .WIDTH(WIDTH), 120 | .CLK_POLARITY(CLK_POLARITY) 121 | ) dff ( 122 | .CLK(CLK), 123 | .D(_srst ? SRST_VALUE : D), 124 | .Q(Q) 125 | ); 126 | endmodule 127 | 128 | module \$sdffe (CLK, SRST, EN, D, Q); 129 | parameter WIDTH = 1; 130 | parameter CLK_POLARITY = 1'b1; 131 | parameter SRST_POLARITY = 1'b1; 132 | parameter SRST_VALUE = {WIDTH{1'b0}}; 133 | parameter EN_POLARITY = 1'b1; 134 | 135 | input wire CLK, SRST, EN; 136 | (* force_downto *) 137 | input wire [WIDTH-1:0] D; 138 | (* force_downto *) 139 | output wire [WIDTH-1:0] Q; 140 | 141 | wire _en; 142 | 143 | generate 144 | if (EN_POLARITY) begin 145 | assign _en = EN; 146 | end else begin 147 | assign _en = ~EN; 148 | end 149 | endgenerate 150 | 151 | \$sdff #( 152 | .WIDTH(WIDTH), 153 | .CLK_POLARITY(CLK_POLARITY), 154 | .SRST_POLARITY(SRST_POLARITY), 155 | .SRST_VALUE(SRST_VALUE) 156 | ) sdff ( 157 | .CLK(CLK), 158 | .SRST(SRST), 159 | .D(_en ? D : Q), 160 | .Q(Q) 161 | ); 162 | endmodule 163 | 164 | module \$adffe (CLK, ARST, EN, D, Q); 165 | parameter WIDTH = 1; 166 | parameter CLK_POLARITY = 1'b1; 167 | parameter ARST_POLARITY = 1'b1; 168 | parameter ARST_VALUE = {WIDTH{1'b0}}; 169 | parameter EN_POLARITY = 1'b1; 170 | 171 | input wire CLK, ARST, EN; 172 | (* force_downto *) 173 | input wire [WIDTH-1:0] D; 174 | (* force_downto *) 175 | output wire [WIDTH-1:0] Q; 176 | 177 | wire _en; 178 | 179 | generate 180 | if (EN_POLARITY) begin 181 | assign _en = EN; 182 | end else begin 183 | assign _en = ~EN; 184 | end 185 | endgenerate 186 | 187 | \$adff #( 188 | .WIDTH(WIDTH), 189 | .CLK_POLARITY(CLK_POLARITY), 190 | .ARST_POLARITY(ARST_POLARITY), 191 | .ARST_VALUE(ARST_VALUE) 192 | ) adff ( 193 | .CLK(CLK), 194 | .ARST(ARST), 195 | .D(_en ? D : Q), 196 | .Q(Q) 197 | ); 198 | endmodule 199 | 200 | module \$reduce_and (A, Y); 201 | parameter A_SIGNED = 0; 202 | parameter A_WIDTH = 2; 203 | parameter Y_WIDTH = 1; 204 | 205 | (* force_downto *) 206 | input wire [A_WIDTH-1:0] A; 207 | (* force_downto *) 208 | output wire [Y_WIDTH-1:0] Y; 209 | 210 | wire _TECHMAP_FAIL_ = (A_WIDTH < 1) || (Y_WIDTH < 1); 211 | wire [1023:0] _TECHMAP_DO_ = "opt"; 212 | 213 | function integer min; 214 | input integer a, b; 215 | begin 216 | if (a < b) min = a; 217 | else min = b; 218 | end 219 | endfunction 220 | 221 | genvar i; 222 | generate 223 | if (Y_WIDTH > 1) begin 224 | assign Y[Y_WIDTH-1:1] = 1'b0; 225 | end 226 | 227 | if (A_WIDTH == 1) begin 228 | assign Y[0] = A[0]; 229 | end else if (A_WIDTH == 2) begin 230 | assign Y[0] = A[0] & A[1]; 231 | end else if (A_WIDTH <= 16) begin 232 | MC_UAND16 #( 233 | .WIDTH(A_WIDTH), 234 | ) _TECHMAP_REPLACE_ ( 235 | .A(A), 236 | .Y(Y[0]) 237 | ); 238 | end else begin 239 | wire [0:A_WIDTH/16] _collate; 240 | for (i = 0; i <= A_WIDTH/16; i++) begin 241 | \$reduce_and #( 242 | .A_SIGNED(0), 243 | .A_WIDTH(min(A_WIDTH - (16 * i), 16)), 244 | .Y_WIDTH(1), 245 | ) reduce_and ( 246 | .A(A[16 * i +: min(A_WIDTH - (16 * i), 16)]), 247 | .Y(_collate[i]) 248 | ); 249 | end 250 | assign Y[0] = &_collate; 251 | end 252 | endgenerate 253 | endmodule 254 | 255 | module \$reduce_or (A, Y); 256 | parameter A_SIGNED = 0; 257 | parameter A_WIDTH = 2; 258 | parameter Y_WIDTH = 1; 259 | 260 | (* force_downto *) 261 | input wire [A_WIDTH-1:0] A; 262 | (* force_downto *) 263 | output wire [Y_WIDTH-1:0] Y; 264 | 265 | wire _TECHMAP_FAIL_ = (A_WIDTH < 1) || (Y_WIDTH < 1); 266 | wire [1023:0] _TECHMAP_DO_ = "opt"; 267 | 268 | function integer min; 269 | input integer a, b; 270 | begin 271 | if (a < b) min = a; 272 | else min = b; 273 | end 274 | endfunction 275 | 276 | genvar i; 277 | generate 278 | if (Y_WIDTH > 1) begin 279 | assign Y[Y_WIDTH-1:1] = 1'b0; 280 | end 281 | 282 | if (A_WIDTH == 1) begin 283 | assign Y[0] = A[0]; 284 | end else if (A_WIDTH == 2) begin 285 | assign Y[0] = A[0] | A[1]; 286 | end else if (A_WIDTH <= 16) begin 287 | MC_UOR16 #( 288 | .WIDTH(A_WIDTH), 289 | ) _TECHMAP_REPLACE_ ( 290 | .A(A), 291 | .Y(Y[0]) 292 | ); 293 | end else begin 294 | wire [0:A_WIDTH/16] _collate; 295 | for (i = 0; i <= A_WIDTH/16; i++) begin 296 | \$reduce_or #( 297 | .A_SIGNED(0), 298 | .A_WIDTH(min(A_WIDTH - (16 * i), 16)), 299 | .Y_WIDTH(1), 300 | ) reduce_or ( 301 | .A(A[16 * i +: min(A_WIDTH - (16 * i), 16)]), 302 | .Y(_collate[i]) 303 | ); 304 | end 305 | assign Y[0] = |_collate; 306 | end 307 | endgenerate 308 | endmodule 309 | 310 | module \$reduce_xor (A, Y); 311 | parameter A_SIGNED = 0; 312 | parameter A_WIDTH = 2; 313 | parameter Y_WIDTH = 1; 314 | 315 | (* force_downto *) 316 | input wire [A_WIDTH-1:0] A; 317 | (* force_downto *) 318 | output wire [Y_WIDTH-1:0] Y; 319 | 320 | wire _TECHMAP_FAIL_ = (A_WIDTH < 1) || (Y_WIDTH < 1); 321 | wire [1023:0] _TECHMAP_DO_ = "opt"; 322 | 323 | function integer min; 324 | input integer a, b; 325 | begin 326 | if (a < b) min = a; 327 | else min = b; 328 | end 329 | endfunction 330 | 331 | genvar i; 332 | generate 333 | if (Y_WIDTH > 1) begin 334 | assign Y[Y_WIDTH-1:1] = 1'b0; 335 | end 336 | 337 | if (A_WIDTH == 1) begin 338 | assign Y[0] = A; 339 | end else if (A_WIDTH == 2) begin 340 | assign Y[0] = A[0] ^ A[1]; 341 | end else if (A_WIDTH <= 4) begin 342 | MC_UXOR4 #( 343 | .WIDTH(A_WIDTH), 344 | ) _TECHMAP_REPLACE_ ( 345 | .A(A), 346 | .Y(Y[0]) 347 | ); 348 | end else if (A_WIDTH <= 8) begin 349 | MC_UXOR8 #( 350 | .WIDTH(A_WIDTH), 351 | ) _TECHMAP_REPLACE_ ( 352 | .A(A), 353 | .Y(Y[0]) 354 | ); 355 | end else if (A_WIDTH <= 16) begin 356 | MC_UXOR16 #( 357 | .WIDTH(A_WIDTH), 358 | ) _TECHMAP_REPLACE_ ( 359 | .A(A), 360 | .Y(Y[0]) 361 | ); 362 | end else begin 363 | wire [0:A_WIDTH/16] _collate; 364 | for (i = 0; i <= A_WIDTH/16; i++) begin 365 | \$reduce_xor #( 366 | .A_SIGNED(0), 367 | .A_WIDTH(min(A_WIDTH - (16 * i), 16)), 368 | .Y_WIDTH(1), 369 | ) reduce_xor ( 370 | .A(A[16 * i +: min(A_WIDTH - (16 * i), 16)]), 371 | .Y(_collate[i]) 372 | ); 373 | end 374 | assign Y[0] = ^_collate; 375 | end 376 | endgenerate 377 | endmodule 378 | 379 | module \$reduce_xnor (A, Y); 380 | parameter A_SIGNED = 0; 381 | parameter A_WIDTH = 2; 382 | parameter Y_WIDTH = 1; 383 | 384 | (* force_downto *) 385 | input wire [A_WIDTH-1:0] A; 386 | (* force_downto *) 387 | output wire [Y_WIDTH-1:0] Y; 388 | 389 | (* force_downto *) 390 | wire [Y_WIDTH-1:0] Y_n; 391 | 392 | wire [1023:0] _TECHMAP_DO_ = "opt"; 393 | 394 | \$reduce_xor #( 395 | .A_SIGNED(0), 396 | .A_WIDTH(A_WIDTH), 397 | .Y_WIDTH(Y_WIDTH), 398 | ) _TECHMAP_REPLACE_ ( 399 | .A(A), 400 | .Y(Y_n) 401 | ); 402 | 403 | generate 404 | if (Y_WIDTH > 1) begin 405 | assign Y = {Y_n[Y_WIDTH-1:1], ~Y_n[0]}; 406 | end else begin 407 | assign Y = ~Y_n; 408 | end 409 | endgenerate 410 | endmodule 411 | 412 | module \$reduce_bool (A, Y); 413 | parameter A_SIGNED = 0; 414 | parameter A_WIDTH = 2; 415 | parameter Y_WIDTH = 1; 416 | 417 | (* force_downto *) 418 | input wire [A_WIDTH-1:0] A; 419 | (* force_downto *) 420 | output wire [Y_WIDTH-1:0] Y; 421 | 422 | wire [1023:0] _TECHMAP_DO_ = "opt"; 423 | 424 | \$reduce_or #( 425 | .A_SIGNED(0), 426 | .A_WIDTH(A_WIDTH), 427 | .Y_WIDTH(Y_WIDTH), 428 | ) _TECHMAP_REPLACE_ ( 429 | .A(A), 430 | .Y(Y) 431 | ); 432 | endmodule 433 | 434 | module \$logic_not (A, Y); 435 | parameter A_SIGNED = 0; 436 | parameter A_WIDTH = 2; 437 | parameter Y_WIDTH = 1; 438 | 439 | (* force_downto *) 440 | input wire [A_WIDTH-1:0] A; 441 | (* force_downto *) 442 | output wire [Y_WIDTH-1:0] Y; 443 | 444 | wire _TECHMAP_FAIL_ = (A_WIDTH < 1) || (Y_WIDTH < 1); 445 | wire [1023:0] _TECHMAP_DO_ = "opt"; 446 | 447 | function integer min; 448 | input integer a, b; 449 | begin 450 | if (a < b) min = a; 451 | else min = b; 452 | end 453 | endfunction 454 | 455 | genvar i; 456 | generate 457 | if (Y_WIDTH > 1) begin 458 | assign Y[Y_WIDTH-1:1] = 1'b0; 459 | end 460 | 461 | if (A_WIDTH == 1) begin 462 | assign Y[0] = ~A[0]; 463 | end else if (A_WIDTH <= 16) begin 464 | // note dedicated NOR cell 465 | MC_UNOR16 #( 466 | .WIDTH(A_WIDTH), 467 | ) _TECHMAP_REPLACE_ ( 468 | .A(A), 469 | .Y(Y[0]) 470 | ); 471 | end else begin 472 | wire [0:A_WIDTH/16] _collate; 473 | // if we need multiple cells, regular ORs are more efficient... 474 | for (i = 0; i <= A_WIDTH/16; i++) begin 475 | \$reduce_or #( 476 | .A_SIGNED(0), 477 | .A_WIDTH(min(A_WIDTH - (16 * i), 16)), 478 | .Y_WIDTH(1), 479 | ) reduce_or ( 480 | .A(A[16 * i +: min(A_WIDTH - (16 * i), 16)]), 481 | .Y(_collate[i]) 482 | ); 483 | end 484 | // ...and this can use NOR if it works out that way 485 | assign Y[0] = !_collate; 486 | end 487 | endgenerate 488 | endmodule 489 | -------------------------------------------------------------------------------- /rtl/timing.jsonc: -------------------------------------------------------------------------------- 1 | { 2 | "MC_DFF31": { 3 | // CLK port to cell clock: 5 4 | // D port to cell input: 6 5 | // cell clock to Q port: 2 6 | // TODO hold time 7 | "t_cq": 7, // CLK port to cell clock delay (5) + cell clock to Q port delay (2) 8 | "t_setup": 1 // D port to cell input delay (6) - CLK port to cell clock delay (5) 9 | }, 10 | "MC_ADFF31": { 11 | // CLK port to cell clock: 8 12 | // D port to cell input: 6 13 | // cell clock to Q port: 6 14 | // TODO hold time 15 | "t_rq": 8, // ARST port to Q port delay 16 | "t_cq": 14, // CLK port to cell clock delay (8) + cell clock to Q port delay (6) 17 | "t_setup": -2 // D port to cell input delay (6) - CLK port to cell clock delay (8) 18 | } 19 | } 20 | -------------------------------------------------------------------------------- /src/assembly.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | from pathlib import Path 3 | import re 4 | from collections.abc import Iterator 5 | from typing import cast 6 | from nbt_structure_utils import Cuboid, NBTStructure, Vector 7 | 8 | STRUCTS: dict[str, NBTStructure] = {} 9 | 10 | def get_struct_ref(name: str) -> NBTStructure: 11 | """Get a reference to a structure loaded from disk. 12 | The structure is only loaded from disk once. 13 | 14 | Do not modify this reference. If you need a modifiable copy of this 15 | reference, use get_struct(). 16 | 17 | Parameters: 18 | name: The MC_* name of the structure to get. 19 | 20 | Returns: 21 | The named structure. 22 | """ 23 | name = name.casefold() 24 | if name not in STRUCTS: 25 | STRUCTS[name] = NBTStructure(str(Path('structures', name + '.nbt'))) 26 | return STRUCTS[name] 27 | 28 | def get_struct(name: str) -> NBTStructure: 29 | """Get a copy of a structure loaded from disk. 30 | The structure is only loaded from disk once. 31 | 32 | Parameters: 33 | name: The MC_* name of the structure to get. 34 | 35 | Returns: 36 | A copy of the named structure. 37 | """ 38 | return get_struct_ref(name).copy() 39 | 40 | def clone_clamp(struct: NBTStructure, name: str, width: int) -> NBTStructure: 41 | """Truncate the named structure to z=width and clone it into struct. 42 | 43 | Parameters: 44 | struct: The structure to clone into. 45 | name: The MC_* name of the structure to clone from. 46 | width: The width in the z-axis to clamp to. 47 | 48 | Returns: 49 | The given struct, with modifications. 50 | """ 51 | loaded = get_struct_ref(name) 52 | max_coords = loaded.get_max_coords() 53 | max_coords.z = width - 1 54 | volume = cast(Iterator[Vector], Cuboid(Vector(0, 0, 0), max_coords)) 55 | struct.clone_structure(loaded, Vector(0, 0, 0), volume) 56 | return struct 57 | 58 | def MC_DFF31(WIDTH: int) -> NBTStructure: 59 | width = WIDTH * 2 + 1 # 2 blocks per bit + 2 blocks per clk - 1 60 | return clone_clamp(NBTStructure(), 'mc_dff31', width) 61 | 62 | def MC_ADFF31(WIDTH: int, ARST_VALUE: int) -> NBTStructure: 63 | # load structures 64 | a0dff1_cell = get_struct_ref('mc_a0dff1_cell') 65 | a1dff1_cell = get_struct_ref('mc_a1dff1_cell') 66 | # assemble structures together 67 | width = WIDTH * 2 + 3 # 2 blocks per bit + 2 blocks per (clk, arst) - 1 68 | struct = clone_clamp(NBTStructure(), 'mc_adff_input', width) 69 | input_max_coords = struct.get_max_coords() 70 | for z in range(WIDTH): 71 | bit = WIDTH - 1 - z 72 | struct.clone_structure( 73 | a1dff1_cell if ARST_VALUE & (1 << bit) else a0dff1_cell, 74 | Vector(input_max_coords.x + 1, 0, z) 75 | ) 76 | return struct 77 | 78 | def MC_UAND16(WIDTH: int) -> NBTStructure: 79 | width = max(2, WIDTH * 2 - 1) # 2 blocks per bit - 1, but 1 bit needs 2 80 | return clone_clamp(NBTStructure(), 'mc_uand16', width) 81 | 82 | def MC_UNOR16(WIDTH: int) -> NBTStructure: 83 | width = WIDTH * 2 - 1 # 2 blocks per bit - 1 84 | return clone_clamp(NBTStructure(), 'mc_unor16', width) 85 | 86 | def MC_UOR16(WIDTH: int) -> NBTStructure: 87 | width = WIDTH * 2 - 1 # 2 blocks per bit - 1 88 | return clone_clamp(NBTStructure(), 'mc_uor16', width) 89 | 90 | def MC_XOR() -> NBTStructure: 91 | return get_struct('mc_xor') 92 | 93 | def MC_UXOR4(WIDTH: int) -> NBTStructure: 94 | width = WIDTH * 2 - 1 # 2 blocks per bit - 1 95 | return clone_clamp(NBTStructure(), 'mc_uxor4', width) 96 | 97 | def MC_UXOR8(WIDTH: int) -> NBTStructure: 98 | width = WIDTH * 2 - 1 # 2 blocks per bit - 1 99 | return clone_clamp(NBTStructure(), 'mc_uxor8', width) 100 | 101 | def MC_UXOR16(WIDTH: int) -> NBTStructure: 102 | width = WIDTH * 2 - 1 # 2 blocks per bit - 1 103 | return clone_clamp(NBTStructure(), 'mc_uxor16', width) 104 | 105 | if __name__ == '__main__': 106 | module = input('Module: ').upper() 107 | if module == 'MC_ADFF31': 108 | width = int(input('WIDTH = ')) 109 | arst_value = int(input('ARST_VALUE = '), 0) 110 | struct = MC_ADFF31(width, arst_value) 111 | arst_value = format(arst_value, f'0{width}b') 112 | struct.get_nbt().write_file(f'structures/mc_a{arst_value}dff{width}_out.nbt') 113 | elif module in set( 114 | 'MC_DFF31 MC_UAND16 MC_UNOR16 MC_UOR16 ' 115 | 'MC_UXOR4 MC_UXOR8 MC_UXOR16'.split() 116 | ): 117 | width = int(input('WIDTH = ')) 118 | struct: NBTStructure = globals()[module](width) 119 | name = re.sub(r'\d+$', '', module.lower()) 120 | struct.get_nbt().write_file(f'structures/{name}{width}_out.nbt') 121 | elif module in set( 122 | 'MC_XOR'.split() 123 | ): 124 | struct: NBTStructure = globals()[module]() 125 | struct.get_nbt().write_file(f'structures/{module.lower()}_out.nbt') 126 | -------------------------------------------------------------------------------- /src/fit.py: -------------------------------------------------------------------------------- 1 | from collections import deque 2 | from typing import Optional 3 | 4 | from pyosys.libyosys import Design, IdString, escape_id, run_pass 5 | 6 | from yosys_techmap import Node, cell_graph 7 | 8 | def place(techmap: str, module: str) -> list[list[Node]]: 9 | """Perform preliminary placement of cells in a module. 10 | 11 | Parameters: 12 | techmap: JSON file containing Yosys technology mapper output. 13 | module: Name of top level module to place. 14 | 15 | Returns: 16 | Structure containing placed cells. 17 | """ 18 | design = Design() 19 | run_pass(f'read_rtlil {techmap}', design) 20 | mod = design.module(IdString(escape_id(module))) 21 | 22 | origins = cell_graph(mod) 23 | 24 | q = deque[Optional[Node]]() 25 | seen: set[Node] = set() 26 | rows: list[list[Node]] = [[]] 27 | for node in origins: 28 | q.append(node) 29 | q.append(None) 30 | 31 | while q: 32 | node = q.popleft() 33 | if node is None: 34 | if q: 35 | q.append(None) 36 | rows.append([]) 37 | continue 38 | rows[-1].append(node) 39 | seen.add(node) 40 | for neighbor in node.neighbors: 41 | if neighbor in seen: 42 | continue 43 | q.append(node) 44 | return rows 45 | 46 | if __name__ == '__main__': 47 | path = input('Path: ') 48 | module = input('Module: ') 49 | from pprint import pprint 50 | placement = place(path, module) 51 | try: 52 | pprint(placement) 53 | print(list(map(len, placement))) 54 | except BrokenPipeError: 55 | pass # `more`/`less` quit 56 | -------------------------------------------------------------------------------- /src/utils.py: -------------------------------------------------------------------------------- 1 | import re 2 | import json 3 | 4 | def load_jsonc(s: str): 5 | return json.loads(re.sub(r'//.*$', '', s, re.M)) 6 | -------------------------------------------------------------------------------- /src/yosys_techmap.py: -------------------------------------------------------------------------------- 1 | from __future__ import annotations 2 | from dataclasses import dataclass, field 3 | from typing import Union, cast 4 | 5 | from pyosys.libyosys import Cell, IdString, Module, SigSpec, Wire 6 | 7 | @dataclass 8 | class Node: 9 | driver: Union[Wire, Cell] 10 | neighbors: set[Node] = field(default_factory=set) 11 | input: bool = False 12 | 13 | def __hash__(self) -> int: 14 | return hash(self.driver.name) 15 | 16 | def sigspec_to_wire(sig: SigSpec) -> Wire: 17 | if sig.is_wire(): 18 | return sig.as_wire() 19 | elif sig.is_chunk() and sig.as_chunk().is_wire(): 20 | return sig.as_chunk().wire 21 | elif sig.is_bit() and sig.as_bit().is_wire(): 22 | return sig.as_bit().wire 23 | else: 24 | raise ValueError(f'{sig!r} is not a wire in any capacity') 25 | 26 | def cell_graph(module: Module) -> list[Node]: # list of input nodes 27 | nodes = {name.str(): Node(cell) for name, cell in module.cells_.items()} \ 28 | | {name.str(): Node(wire) for name, wire in module.wires_.items() 29 | if wire.port_input or wire.port_output} 30 | for node in nodes.values(): 31 | if not hasattr(node.driver, 'connections'): 32 | continue 33 | cell = cast(Cell, node.driver) 34 | for name, spec in cell.connections().items(): 35 | wire = sigspec_to_wire(spec) 36 | if wire.port_id: 37 | if wire.port_input: 38 | node.input = True 39 | driver = wire 40 | else: 41 | driver = wire.driverCell() 42 | other = nodes[driver.name.str()] 43 | node.neighbors.add(other) 44 | other.neighbors.add(node) 45 | return [node for node in nodes.values() if node.input] 46 | -------------------------------------------------------------------------------- /structures/mc_a0dff1_cell.nbt: -------------------------------------------------------------------------------- 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reset) begin 13 | if (reset) en_acount <= RST_VALUE; 14 | else if (en) en_acount <= en_acount + 1'b1; 15 | end 16 | 17 | always_ff @(posedge clk or posedge reset) begin 18 | if (reset) acount <= RST_VALUE; 19 | else acount <= acount + 1'b1; 20 | end 21 | 22 | always_ff @(posedge clk) begin 23 | if (reset) en_scount <= RST_VALUE; 24 | else if (en) en_scount <= en_scount + 1'b1; 25 | end 26 | 27 | always_ff @(posedge clk) begin 28 | if (reset) scount <= RST_VALUE; 29 | else scount <= scount + 1'b1; 30 | end 31 | endmodule 32 | -------------------------------------------------------------------------------- /tests/rtl/test_techmap_ureduce.sv: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | // used to test techmapping to MC_U* 4 | 5 | module reductions ( 6 | i_in, o_and, o_or, 7 | o_xor2, o_xor3, o_xor7, o_xor15, o_xor, 8 | o_xnor, o_bool, o_not15, o_not 9 | ); 10 | parameter W = 20; 11 | 12 | input logic [W-1:0] i_in; 13 | output logic o_and, o_or, o_xor2, o_xor3, o_xor7, o_xor15, o_xor, 14 | o_xnor, o_bool, o_not15, o_not; 15 | 16 | assign o_and = &i_in; 17 | assign o_or = |i_in; 18 | assign o_xor2 = ^i_in[1:0]; 19 | assign o_xor3 = ^i_in[2:0]; 20 | assign o_xor7 = ^i_in[6:0]; 21 | assign o_xor15 = ^i_in[14:0]; 22 | assign o_xor = ^i_in; 23 | assign o_xnor = ~^i_in; 24 | assign o_bool = i_in ? 1'b1 : 1'b0; 25 | assign o_not15 = !i_in[14:0]; 26 | assign o_not = !i_in; 27 | endmodule 28 | -------------------------------------------------------------------------------- /typings/pyosys/libyosys/__init__.pyi: -------------------------------------------------------------------------------- 1 | from _typeshed import Incomplete 2 | from enum import IntEnum 3 | from typing import Generic, TypeVar, overload 4 | 5 | def __getattr__(name: str, /) -> Incomplete: ... 6 | 7 | class State(IntEnum): 8 | S0 = 0 9 | S1 = 1 10 | Sx = 2 # undefined value or conflict 11 | Sz = 3 # high-impedance / not-connected 12 | Sa = 4 # don't care (used only in cases, /) 13 | Sm = 5 # marker (used internally by some passes, /) 14 | 15 | class SyncType(IntEnum): 16 | ST0 = 0 # level sensitive: 0 17 | ST1 = 1 # level sensitive: 1 18 | STp = 2 # edge sensitive: posedge 19 | STn = 3 # edge sensitive: negedge 20 | STe = 4 # edge sensitive: both edges 21 | STa = 5 # always active 22 | STg = 6 # global clock 23 | STi = 7 # init 24 | 25 | class ConstFlags(IntEnum): 26 | CONST_FLAG_NONE = 0 27 | CONST_FLAG_STRING = 1 28 | CONST_FLAG_SIGNED = 2 # only used for parameters 29 | CONST_FLAG_REAL = 4 # only used for parameters 30 | 31 | SigSig = tuple[SigSpec, SigSpec] 32 | 33 | class IdString: 34 | index_: int 35 | 36 | @overload 37 | def __init__(self, /) -> None: ... 38 | @overload 39 | def __init__(self, str: str | IdString, /) -> None: ... 40 | def __del__(self, /) -> None: ... 41 | 42 | def __lt__(self, rhs: IdString, /) -> bool: ... 43 | def __eq__(self, rhs: IdString | str, /) -> bool: ... 44 | def __ne__(self, rhs: IdString | str, /) -> bool: ... 45 | 46 | def hash(self, /) -> int: ... 47 | def __hash__(self, /) -> int: ... 48 | 49 | def __str__(self, /) -> str: ... 50 | 51 | def c_str(self, /) -> str: ... 52 | def str(self, /) -> str: ... 53 | 54 | def isPublic(self, /) -> bool: ... 55 | 56 | def __getattr__(self, name: str, /) -> Incomplete: ... 57 | 58 | def escape_id(str: str, /) -> str: ... 59 | 60 | def unescape_id(str: str | IdString, /) -> str: ... 61 | 62 | def id2cstr(str: IdString, /) -> str: ... 63 | 64 | def encode_filename(filename: str, /) -> str: ... 65 | 66 | class Const: 67 | flags: int 68 | 69 | @overload 70 | def __init__(self, /) -> None: ... 71 | @overload 72 | def __init__(self, str: str, /) -> None: ... 73 | @overload 74 | def __init__(self, bit: State, width: int, /) -> None: ... 75 | @overload 76 | def __init__(self, bits: list[State], /) -> None: ... 77 | @overload 78 | def __init__(self, other: Const, /) -> None: ... 79 | def __del__(self, /) -> None: ... 80 | 81 | def __lt__(self, other: Const, /) -> bool: ... 82 | def __eq__(self, other: Const, /) -> bool: ... 83 | def __ne__(self, other: Const, /) -> bool: ... 84 | 85 | def bits(self, /) -> list[State]: ... 86 | def as_bool(self, /) -> bool: ... 87 | def as_int(self, is_signed: bool = False, /) -> int: ... 88 | def as_string(self, any: str, /) -> str: ... 89 | @classmethod 90 | def from_string(cls, str: str, /) -> Const: ... 91 | def to_bits(self, /) -> list[State]: ... 92 | 93 | def decode_string(self, /) -> str: ... 94 | def size(self, /) -> int: ... 95 | def empty(self, /) -> bool: ... 96 | def bitvectorize(self, /) -> None: ... 97 | 98 | def is_fully_zero(self, /) -> bool: ... 99 | def is_fully_ones(self, /) -> bool: ... 100 | def is_fully_def(self, /) -> bool: ... 101 | def is_fully_undef(self, /) -> bool: ... 102 | def is_fully_undef_x_only(self, /) -> bool: ... 103 | def is_onehot(self, pos=None, /) -> bool: ... 104 | 105 | def extract(self, offset: int, len: int = 1, padding: State = State.S0, /) -> Const: ... 106 | 107 | def get_min_size(self, is_signed: bool, /) -> int: ... 108 | 109 | def compress(self, is_signed: bool = False, /) -> None: ... 110 | 111 | def extu(self, width: int, /) -> None: ... 112 | def exts(self, width: int, /) -> None: ... 113 | 114 | def hash(self, /) -> int: ... 115 | def __hash__(self, /) -> int: ... 116 | 117 | def __getattr__(self, name: str, /) -> Incomplete: ... 118 | 119 | class AttrObject: 120 | attributes: dict[IdString, Const] 121 | 122 | def has_attribute(self, id: IdString, /) -> bool: ... 123 | 124 | def set_bool_attribute(self, id: IdString, value: bool = True, /) -> None: ... 125 | def get_bool_attribute(self, id: IdString, /) -> bool: ... 126 | 127 | def get_blackbox_attribute(self, ignore_wb: bool = False, /) -> bool: ... 128 | 129 | def set_string_attribute(self, id: IdString, value: str, /) -> None: ... 130 | def get_string_attribute(self, id: IdString, /) -> str: ... 131 | 132 | def set_strpool_attribute(self, id: IdString, data: list[str], /) -> None: ... 133 | def add_strpool_attribute(self, id: IdString, data: list[str], /) -> None: ... 134 | def get_strpool_attribute(self, id: IdString, /) -> list[str]: ... 135 | 136 | def set_src_attribute(self, src: str, /) -> None: ... 137 | def get_src_attribute(self, /) -> str: ... 138 | 139 | def set_hdlname_attribute(self, hierarchy: list[str], /) -> None: ... 140 | def get_hdlname_attribute(self, /) -> list[str]: ... 141 | 142 | def set_intvec_attribute(self, id: IdString, data: list[int], /) -> None: ... 143 | def get_intvec_attribute(self, id: IdString, /) -> list[int]: ... 144 | 145 | class SigChunk: 146 | wire: Wire 147 | data: list[State] 148 | width: int 149 | offset: int 150 | 151 | @overload 152 | def __init__(self, /) -> None: ... 153 | @overload 154 | def __init__(self, value: Const, /) -> None: ... 155 | @overload 156 | def __init__(self, wire: Wire, offset: int = ..., width: int = 1, /) -> None: ... 157 | @overload 158 | def __init__(self, str: str, /) -> None: ... 159 | @overload 160 | def __init__(self, val: int, width: int = 32, /) -> None: ... 161 | @overload 162 | def __init__(self, bit: State, width: int = 1, /) -> None: ... 163 | @overload 164 | def __init__(self, bit: SigBit, /) -> None: ... 165 | 166 | def extract(self, offset: int, length: int, /) -> SigChunk: ... 167 | def size(self, /) -> int: ... 168 | def is_wire(self, /) -> bool: ... 169 | 170 | def __lt__(self, other: SigChunk, /) -> bool: ... 171 | def __eq__(self, other: SigChunk, /) -> bool: ... 172 | def __ne__(self, other: SigChunk, /) -> bool: ... 173 | 174 | def __getattr__(self, name: str, /) -> Incomplete: ... 175 | 176 | class SigBit: 177 | wire: Wire 178 | data: State 179 | offset: int 180 | 181 | @overload 182 | def __init__(self, /) -> None: ... 183 | @overload 184 | def __init__(self, bit: State | bool, /) -> None: ... 185 | @overload 186 | def __init__(self, wire: Wire, offset: int = ..., /) -> None: ... 187 | @overload 188 | def __init__(self, chunk: SigChunk, index: int = ..., /) -> None: ... 189 | @overload 190 | def __init__(self, sig: SigSpec, /) -> None: ... 191 | @overload 192 | def __init__(self, sigbit: SigBit, /) -> None: ... 193 | 194 | def is_wire(self, /) -> bool: ... 195 | 196 | def __lt__(self, other: SigBit, /) -> bool: ... 197 | def __eq__(self, other: SigBit, /) -> bool: ... 198 | def __ne__(self, other: SigBit, /) -> bool: ... 199 | def hash(self, /) -> int: ... 200 | def __hash__(self, /) -> int: ... 201 | 202 | def __getattr__(self, name: str, /) -> Incomplete: ... 203 | 204 | class SigSpec: 205 | @overload 206 | def __init__(self, /) -> None: ... 207 | @overload 208 | def __init__(self, value: Const, /) -> None: ... 209 | @overload 210 | def __init__(self, chunk: SigChunk, /) -> None: ... 211 | @overload 212 | def __init__(self, wire: Wire, offset: int = ..., width: int = 1, /) -> None: ... 213 | @overload 214 | def __init__(self, str: str, /) -> None: ... 215 | @overload 216 | def __init__(self, val: int, width: int = 32, /) -> None: ... 217 | @overload 218 | def __init__(self, bit: State | SigBit, width: int = 1, /) -> None: ... 219 | @overload 220 | def __init__(self, chunks: list[SigChunk], /) -> None: ... 221 | @overload 222 | def __init__(self, bits: list[SigBit], /) -> None: ... 223 | @overload 224 | def __init__(self, bit: bool, /) -> None: ... 225 | 226 | def get_hash(self, /) -> int: ... 227 | def __hash__(self, /) -> int: ... 228 | 229 | def chunks(self, /) -> list[SigChunk]: ... 230 | def bits(self, /) -> list[SigBit]: ... 231 | 232 | def size(self, /) -> int: ... 233 | def empty(self, /) -> bool: ... 234 | 235 | def __getitem__(self, index: int, /) -> SigBit: ... 236 | 237 | def sort(self, /) -> None: ... 238 | def sort_and_unify(self, /) -> None: ... 239 | 240 | @overload 241 | def replace(self, pattern: SigSpec, with_: SigSpec, other: SigSpec = ..., /) -> None: ... 242 | @overload 243 | def replace(self, rules: dict[SigBit, SigBit], other: SigSpec = ..., /) -> None: ... 244 | @overload 245 | def replace(self, offset: int, with_: SigSpec, /) -> None: ... 246 | 247 | @overload 248 | def remove(self, pattern: SigSpec | list[SigBit], other: SigSpec = ..., /) -> None: ... 249 | @overload 250 | def remove(self, offset: int, length: int = 1, /) -> None: ... 251 | 252 | def remove2(self, pattern: SigSpec, other: SigSpec, /) -> None: ... 253 | 254 | def remove_const(self, /) -> None: ... 255 | 256 | @overload 257 | def extract(self, pattern: SigSpec | list[SigBit], other: SigSpec, /) -> SigSpec: ... 258 | @overload 259 | def extract(self, offset: int, length: int = 1, /) -> SigSpec: ... 260 | def extract_end(self, offset: int, /) -> SigSpec: ... 261 | 262 | def lsb(self, /) -> SigBit: ... 263 | def msb(self, /) -> SigBit: ... 264 | 265 | def append(self, arg: SigSpec | Wire | SigChunk | Const | SigBit | State | bool, /) -> None: ... 266 | 267 | def extend_u0(self, width: int, is_signed: bool = False, /) -> None: ... 268 | 269 | def repeat(self, num: int, /) -> SigSpec: ... 270 | 271 | def reverse(self, /) -> None: ... 272 | 273 | def __lt__(self, other: SigSpec, /) -> bool: ... 274 | def __eq__(self, other: SigSpec, /) -> bool: ... 275 | def __ne__(self, other: SigSpec, /) -> bool: ... 276 | 277 | def is_wire(self, /) -> bool: ... 278 | def is_chunk(self, /) -> bool: ... 279 | def is_bit(self, /) -> bool: ... 280 | 281 | def is_fully_const(self, /) -> bool: ... 282 | def is_fully_zero(self, /) -> bool: ... 283 | def is_fully_ones(self, /) -> bool: ... 284 | def is_fully_def(self, /) -> bool: ... 285 | def is_fully_undef(self, /) -> bool: ... 286 | def has_const(self, /) -> bool: ... 287 | def has_marked_bits(self, /) -> bool: ... 288 | def is_onehot(self, pos=None, /) -> bool: ... 289 | 290 | def as_bool(self, /) -> bool: ... 291 | def as_int(self, is_signed: bool = False, /) -> int: ... 292 | def as_string(self, /) -> str: ... 293 | def as_const(self, /) -> Const: ... 294 | def as_wire(self, /) -> Wire: ... 295 | def as_chunk(self, /) -> SigChunk: ... 296 | def as_bit(self, /) -> SigBit: ... 297 | 298 | def match(self, pattern: str, /) -> bool: ... 299 | 300 | def to_sigbit_set(self, /) -> list[SigBit]: ... 301 | def to_sigbit_pool(self, /) -> list[SigBit]: ... 302 | def to_sigbit_vector(self, /) -> list[SigBit]: ... 303 | def to_sigbit_map(self, other: SigSpec, /) -> dict[SigBit, SigBit]: ... 304 | def to_sigbit_dict(self, other: SigSpec, /) -> dict[SigBit, SigBit]: ... 305 | 306 | @staticmethod 307 | def parse(sig: SigSpec, module: Module, str: str, /) -> bool: ... 308 | @staticmethod 309 | def parse_sel(sig: SigSpec, design: Design, module: Module, str: str, /) -> bool: ... 310 | @staticmethod 311 | def parse_rhs(lhs: SigSpec, sig: SigSpec, module: Module, str: str, /) -> bool: ... 312 | 313 | def at(self, offset: int, defval: SigBit, /) -> SigBit: ... 314 | 315 | def hash(self, /) -> int: ... 316 | 317 | def check(self, mod: Module, /) -> None: ... 318 | 319 | def __getattr__(self, name: str, /) -> Incomplete: ... 320 | 321 | class Selection: 322 | full_selection: bool 323 | selected_modules: list[IdString] 324 | selected_members: dict[IdString, list[IdString]] 325 | 326 | def __init__(self, full: bool, /) -> None: ... 327 | 328 | def selected_module(self, mod_name: IdString, /) -> bool: ... 329 | def selected_whole_module(self, mod_name: IdString, /) -> bool: ... 330 | def selected_member(self, mod_name: IdString, memb_name: IdString, /) -> bool: ... 331 | def optimize(self, design: Design, /) -> None: ... 332 | 333 | def empty(self, /) -> bool: ... 334 | 335 | class Monitor: 336 | hashidx_: int 337 | def hash(self, /) -> int: ... 338 | def __hash__(self, /) -> int: ... 339 | 340 | def __init__(self, /) -> None: ... 341 | 342 | def __del__(self, /) -> None: ... 343 | def notify_module_add(self, arg: Module, /) -> None: ... 344 | def notify_module_del(self, arg: Module, /) -> None: ... 345 | @overload 346 | def notify_connect(self, arg1: Cell, arg2: IdString, arg3: SigSpec, arg4: SigSpec, /) -> None: ... 347 | @overload 348 | def notify_connect(self, arg1: Module, arg2: SigSig | list[SigSig], /) -> None: ... 349 | def notify_blackout(self, arg: Module, /) -> None: ... 350 | 351 | class Design: 352 | hashidx_: int 353 | def hash(self, /) -> int: ... 354 | def __hash__(self, /) -> int: ... 355 | 356 | monitors: list[Monitor] 357 | scratchpad: dict[str, str] 358 | 359 | def bufNormalize(self, enable: bool = True, /) -> None: ... 360 | 361 | modules_: dict[IdString, Module] 362 | 363 | selection_stack: list[Selection] 364 | selection_vars: dict[IdString, Selection] 365 | selected_active_module: str 366 | 367 | def __init__(self, /) -> None: ... 368 | def __del__(self, /) -> None: ... 369 | 370 | def module(self, name: IdString, /) -> Module: ... 371 | def top_module(self, /) -> Module: ... 372 | 373 | def has(self, id: IdString, /) -> bool: ... 374 | 375 | def add(self, module: Module, /) -> None: ... 376 | 377 | def addModule(self, name: IdString, /) -> Module: ... 378 | def remove(self, module: Module, /) -> None: ... 379 | def rename(self, module: Module, new_name: IdString, /) -> None: ... 380 | 381 | def scratchpad_unset(self, varname: str, /) -> None: ... 382 | 383 | def scratchpad_set_int(self, varname: str, value: int, /) -> None: ... 384 | def scratchpad_set_bool(self, varname: str, value: bool, /) -> None: ... 385 | def scratchpad_set_string(self, varname: str, value: str, /) -> None: ... 386 | 387 | def scratchpad_get_int(self, varname: str, default_value: int = 0, /) -> int: ... 388 | def scratchpad_get_bool(self, varname: str, default_value: bool = False, /) -> bool: ... 389 | def scratchpad_get_string(self, varname: str, default_value: str = '', /) -> str: ... 390 | 391 | def sort(self, /) -> None: ... 392 | def check(self, /) -> None: ... 393 | def optimize(self, /) -> None: ... 394 | 395 | def selected_module(self, mod_name: IdString | Module, /) -> bool: ... 396 | def selected_whole_module(self, mod_name: IdString | Module, /) -> bool: ... 397 | def selected_member(self, mod_name: IdString, memb_name: IdString, /) -> bool: ... 398 | 399 | def selection(self, /) -> Selection: ... 400 | 401 | def full_selection(self, /) -> bool: ... 402 | 403 | def selected_modules(self, /) -> list[Module]: ... 404 | def selected_whole_modules(self, /) -> list[Module]: ... 405 | def selected_whole_modules_warn(self, include_wb: bool = False, /) -> list[Module]: ... 406 | @staticmethod 407 | def get_all_designs() -> dict[int, Design]: ... 408 | 409 | _T = TypeVar('_T') 410 | 411 | class idict(dict, Generic[_T]): 412 | @overload 413 | def __getitem__(self, key: _T) -> int: ... 414 | @overload 415 | def __getitem__(self, key: int) -> _T: ... 416 | 417 | class Module(AttrObject): 418 | hashidx_: int 419 | def hash(self, /) -> int: ... 420 | def __hash__(self, /) -> int: ... 421 | 422 | def add(self, arg: Wire | Cell | Process, /) -> None: ... 423 | 424 | design: Design 425 | monitors: list[Monitor] 426 | 427 | wires_: dict[IdString, Wire] 428 | cells_: dict[IdString, Cell] 429 | 430 | connections_: list[SigSig] 431 | 432 | name: IdString 433 | avail_parameters: idict[IdString] 434 | parameter_default_values: dict[IdString, Const] 435 | memories: dict[IdString, Memory] 436 | processes: dict[IdString, Process] 437 | 438 | def __init__(self, /) -> None: ... 439 | def __del__(self, /) -> None: ... 440 | @overload 441 | def derive(self, design: Design, parameters: dict[IdString, Const], mayfail: bool = False, /) -> IdString: ... 442 | @overload 443 | def derive(self, design: Design, parameters: dict[IdString, Const], interfaces: dict[IdString, Module], modports: dict[IdString, IdString], mayfail: bool = False, /) -> IdString: ... 444 | def count_id(self, id: IdString, /) -> int: ... 445 | def expand_interfaces(self, design: Design, local_interfaces: dict[IdString, Module], /) -> None: ... 446 | def reprocess_if_necessary(self, design: Design, /) -> bool: ... 447 | 448 | def sort(self, /) -> None: ... 449 | def check(self, /) -> None: ... 450 | def optimize(self, /) -> None: ... 451 | def makeblackbox(self, /) -> None: ... 452 | 453 | @overload 454 | def connect(self, conn: SigSig, /) -> None: ... 455 | @overload 456 | def connect(self, lhs: SigSpec, rhs: SigSpec, /) -> None: ... 457 | def new_connections(self, new_conn: list[SigSig], /) -> None: ... 458 | def connections(self, /) -> list[SigSig]: ... 459 | 460 | ports: list[IdString] 461 | def fixup_ports(self, /) -> None: ... 462 | 463 | bufNormQueue: list[tuple[Cell, IdString]] 464 | def bufNormalize(self, /) -> None: ... 465 | 466 | def cloneInto(self, new_mod: Module, /) -> None: ... 467 | def clone(self, /) -> Module: ... 468 | 469 | def has_memories(self, /) -> bool: ... 470 | def has_processes(self, /) -> bool: ... 471 | 472 | def has_memories_warn(self, /) -> bool: ... 473 | def has_processes_warn(self, /) -> bool: ... 474 | 475 | def selected_wires(self, /) -> list[Wire]: ... 476 | def selected_cells(self, /) -> list[Cell]: ... 477 | 478 | def wire(self, id: IdString, /) -> Wire: ... 479 | def cell(self, id: IdString, /) -> Cell: ... 480 | 481 | def remove(self, arg: list[Wire] | Cell | Process, /) -> None: ... 482 | 483 | def rename(self, arg: Wire | Cell | IdString, new_name: IdString, /) -> None: ... 484 | 485 | @overload 486 | def swap_names(self, w1: Wire, w2: Wire, /) -> None: ... 487 | @overload 488 | def swap_names(self, c1: Cell, c2: Cell, /) -> None: ... 489 | 490 | def uniquify(self, name: IdString, index: int = ..., /) -> IdString: ... 491 | 492 | def addWire(self, name: IdString, arg: int | Wire = 1, /) -> Wire: ... 493 | 494 | def addCell(self, name: IdString, arg: IdString | Cell, /) -> Cell: ... 495 | 496 | def addMemory(self, name: IdString, other: Memory) -> Memory: ... 497 | 498 | def addProcess(self, name: IdString, other: Process = ...) -> Process: ... 499 | 500 | @staticmethod 501 | def get_all_modules() -> dict[int, Module]: ... 502 | 503 | class Wire(AttrObject): 504 | hashidx_: int 505 | def hash(self, /) -> int: ... 506 | def __hash__(self, /) -> int: ... 507 | 508 | def __init__(self, /) -> None: ... 509 | def __del__(self, /) -> None: ... 510 | 511 | module: Module 512 | name: IdString 513 | width: int 514 | start_offset: int 515 | port_id: int 516 | port_input: bool 517 | port_output: bool 518 | upto: bool 519 | is_signed: bool 520 | 521 | def driverCell(self, /) -> Cell: ... 522 | def driverPort(self, /) -> IdString: ... 523 | 524 | @staticmethod 525 | def get_all_wires() -> dict[int, Wire]: ... 526 | 527 | class Memory(AttrObject): 528 | hashidx_: int 529 | def hash(self, /) -> int: ... 530 | def __hash__(self, /) -> int: ... 531 | 532 | def __init__(self, /) -> None: ... 533 | 534 | name: IdString 535 | width: int 536 | start_offset: int 537 | size: int 538 | def __del__(self, /) -> None: ... 539 | @staticmethod 540 | def get_all_memorys() -> dict[int, Memory]: ... 541 | 542 | class Cell(AttrObject): 543 | hashidx_: int 544 | def hash(self, /) -> int: ... 545 | def __hash__(self, /) -> int: ... 546 | 547 | def __init__(self, /) -> None: ... 548 | def __del__(self, /) -> None: ... 549 | 550 | module: Module 551 | name: IdString 552 | type: IdString 553 | connections_: dict[IdString, SigSpec] 554 | parameters: dict[IdString, Const] 555 | 556 | def hasPort(self, portname: IdString, /) -> bool: ... 557 | def unsetPort(self, portname: IdString, /) -> None: ... 558 | def setPort(self, portname: IdString, signal: SigSpec, /) -> None: ... 559 | def getPort(self, portname: IdString, /) -> SigSpec: ... 560 | def connections(self, /) -> dict[IdString, SigSpec]: ... 561 | 562 | def known(self, /) -> bool: ... 563 | def input(self, portname: IdString, /) -> bool: ... 564 | def output(self, portname: IdString, /) -> bool: ... 565 | 566 | def hasParam(self, paramname: IdString, /) -> bool: ... 567 | def unsetParam(self, paramname: IdString, /) -> None: ... 568 | def setParam(self, paramname: IdString, value: Const, /) -> None: ... 569 | def getParam(self, paramname: IdString, /) -> Const: ... 570 | 571 | def sort(self, /) -> None: ... 572 | def check(self, /) -> None: ... 573 | def fixup_parameters(self, set_a_signed: bool = False, set_b_signed: bool = False, /) -> None: ... 574 | 575 | def has_keep_attr(self, /) -> bool: ... 576 | 577 | @staticmethod 578 | def get_all_cells() -> dict[int, Cell]: ... 579 | 580 | def has_memid(self, /) -> bool: ... 581 | def is_mem_cell(self, /) -> bool: ... 582 | 583 | class CaseRule(AttrObject): 584 | compare: list[SigSpec] 585 | actions: list[SigSig] 586 | switches: list[SwitchRule] 587 | 588 | def __del__(self, /) -> None: ... 589 | 590 | def empty(self, /) -> bool: ... 591 | 592 | def clone(self, /) -> CaseRule: ... 593 | 594 | class SwitchRule(AttrObject): 595 | signal: SigSpec 596 | cases: list[CaseRule] 597 | 598 | def __del__(self, /) -> None: ... 599 | 600 | def empty(self, /) -> bool: ... 601 | 602 | def clone(self, /) -> SwitchRule: ... 603 | 604 | class MemWriteAction(AttrObject): 605 | memid: IdString 606 | address: SigSpec 607 | data: SigSpec 608 | enable: SigSpec 609 | priority_mask: Const 610 | 611 | class SyncRule: 612 | type: SyncType 613 | signal: SigSpec 614 | actions: list[SigSig] 615 | mem_write_actions: list[MemWriteAction] 616 | 617 | def clone(self, /) -> SyncRule: ... 618 | 619 | class Process(AttrObject): 620 | hashidx_: int 621 | def hash(self, /) -> int: ... 622 | def __hash__(self, /) -> int: ... 623 | 624 | def __init__(self, /) -> None: ... 625 | def __del__(self, /) -> None: ... 626 | 627 | name: IdString 628 | module: Module 629 | root_case: CaseRule 630 | syncs: list[SyncRule] 631 | 632 | def clone(self, /) -> Process: ... 633 | 634 | def run_pass(command: str, design: Design) -> None: ... 635 | -------------------------------------------------------------------------------- /v2mc.ys: -------------------------------------------------------------------------------- 1 | # the following lines are prepended by build.sh: 2 | # read_verilog -sv $* 3 | # hierarchy -check -top $TOP 4 | 5 | # boilerplate analysis & elaboration 6 | read_verilog -lib rtl/mc_simlib.v 7 | proc; opt; fsm; opt; memory; opt 8 | 9 | # techmap to coarse-grained MC_* primitives 10 | techmap -map rtl/mc_techlib.v 11 | splitnets 12 | opt 13 | json -o build/mc_techmap.json 14 | write_rtlil build/mc_techmap.rtlil 15 | show -width -colors 1 -format svg -prefix show/mc_techmap 16 | 17 | # techmap simple cells to Yosys internal gates 18 | simplemap 19 | opt 20 | json -o build/mc_simplemap.json 21 | write_rtlil build/mc_simplemap.rtlil 22 | show -width -colors 1 -format svg -prefix show/mc_simplemap 23 | 24 | # techmap the rest of the cells to Yosys internal gates 25 | techmap; opt 26 | json -o build/techmap.json 27 | write_rtlil build/techmap.rtlil 28 | show -width -colors 1 -format svg -prefix show/techmap 29 | --------------------------------------------------------------------------------