├── .gitattributes
├── .gitignore
├── DEPENDENCIES
├── LICENSE
├── README.md
├── disassembler
├── .gitattributes
├── .gitignore
└── disassembler.lua
├── emulator
├── README.md
├── meson.build
└── src
│ ├── Chipset
│ ├── CPU.cpp
│ ├── CPU.hpp
│ ├── CPUArithmetic.cpp
│ ├── CPUControl.cpp
│ ├── CPULoadStore.cpp
│ ├── CPUPushPop.cpp
│ ├── Chipset.cpp
│ ├── Chipset.hpp
│ ├── InterruptSource.cpp
│ ├── InterruptSource.hpp
│ ├── MMU.cpp
│ ├── MMU.hpp
│ ├── MMURegion.cpp
│ └── MMURegion.hpp
│ ├── Config.hpp
│ ├── Data
│ ├── ColourInfo.hpp
│ ├── EventCode.hpp
│ ├── ModelInfo.cpp
│ ├── ModelInfo.hpp
│ └── SpriteInfo.hpp
│ ├── Emulator.cpp
│ ├── Emulator.hpp
│ ├── Logger.cpp
│ ├── Logger.hpp
│ ├── Peripheral
│ ├── BatteryBackedRAM.cpp
│ ├── BatteryBackedRAM.hpp
│ ├── Keyboard.cpp
│ ├── Keyboard.hpp
│ ├── Miscellaneous.cpp
│ ├── Miscellaneous.hpp
│ ├── Peripheral.cpp
│ ├── Peripheral.hpp
│ ├── ROMWindow.cpp
│ ├── ROMWindow.hpp
│ ├── Screen.cpp
│ ├── Screen.hpp
│ ├── StandbyControl.cpp
│ ├── StandbyControl.hpp
│ ├── Timer.cpp
│ └── Timer.hpp
│ └── casioemu.cpp
└── models
└── fx570esplus
├── interface.png
├── interface.svg
├── model.lua
└── readme.txt
/.gitattributes:
--------------------------------------------------------------------------------
1 | Makefile linguist-vendored
2 |
--------------------------------------------------------------------------------
/.gitignore:
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1 | *~
2 | *.log
3 | *.geany
4 | *.sublime-*
5 | models/*/*.bin
6 | models/*/*.asm
7 | models/*/*.names
8 | ignore/
9 | build/
10 | test/
11 |
--------------------------------------------------------------------------------
/DEPENDENCIES:
--------------------------------------------------------------------------------
1 | libsdl2-dev
2 | libsdl2-image-dev
3 | liblua5.3-0-dev
4 |
5 |
--------------------------------------------------------------------------------
/LICENSE:
--------------------------------------------------------------------------------
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529 | parties who would receive the covered work from you, a discriminatory
530 | patent license (a) in connection with copies of the covered work
531 | conveyed by you (or copies made from those copies), or (b) primarily
532 | for and in connection with specific products or compilations that
533 | contain the covered work, unless you entered into that arrangement,
534 | or that patent license was granted, prior to 28 March 2007.
535 |
536 | Nothing in this License shall be construed as excluding or limiting
537 | any implied license or other defenses to infringement that may
538 | otherwise be available to you under applicable patent law.
539 |
540 | 12. No Surrender of Others' Freedom.
541 |
542 | If conditions are imposed on you (whether by court order, agreement or
543 | otherwise) that contradict the conditions of this License, they do not
544 | excuse you from the conditions of this License. If you cannot convey a
545 | covered work so as to satisfy simultaneously your obligations under this
546 | License and any other pertinent obligations, then as a consequence you may
547 | not convey it at all. For example, if you agree to terms that obligate you
548 | to collect a royalty for further conveying from those to whom you convey
549 | the Program, the only way you could satisfy both those terms and this
550 | License would be to refrain entirely from conveying the Program.
551 |
552 | 13. Use with the GNU Affero General Public License.
553 |
554 | Notwithstanding any other provision of this License, you have
555 | permission to link or combine any covered work with a work licensed
556 | under version 3 of the GNU Affero General Public License into a single
557 | combined work, and to convey the resulting work. The terms of this
558 | License will continue to apply to the part which is the covered work,
559 | but the special requirements of the GNU Affero General Public License,
560 | section 13, concerning interaction through a network will apply to the
561 | combination as such.
562 |
563 | 14. Revised Versions of this License.
564 |
565 | The Free Software Foundation may publish revised and/or new versions of
566 | the GNU General Public License from time to time. Such new versions will
567 | be similar in spirit to the present version, but may differ in detail to
568 | address new problems or concerns.
569 |
570 | Each version is given a distinguishing version number. If the
571 | Program specifies that a certain numbered version of the GNU General
572 | Public License "or any later version" applies to it, you have the
573 | option of following the terms and conditions either of that numbered
574 | version or of any later version published by the Free Software
575 | Foundation. If the Program does not specify a version number of the
576 | GNU General Public License, you may choose any version ever published
577 | by the Free Software Foundation.
578 |
579 | If the Program specifies that a proxy can decide which future
580 | versions of the GNU General Public License can be used, that proxy's
581 | public statement of acceptance of a version permanently authorizes you
582 | to choose that version for the Program.
583 |
584 | Later license versions may give you additional or different
585 | permissions. However, no additional obligations are imposed on any
586 | author or copyright holder as a result of your choosing to follow a
587 | later version.
588 |
589 | 15. Disclaimer of Warranty.
590 |
591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
592 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
593 | HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
594 | OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
595 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
596 | PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
597 | IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
598 | ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
599 |
600 | 16. Limitation of Liability.
601 |
602 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
603 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
604 | THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
605 | GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
606 | USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
607 | DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
608 | PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
609 | EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
610 | SUCH DAMAGES.
611 |
612 | 17. Interpretation of Sections 15 and 16.
613 |
614 | If the disclaimer of warranty and limitation of liability provided
615 | above cannot be given local legal effect according to their terms,
616 | reviewing courts shall apply local law that most closely approximates
617 | an absolute waiver of all civil liability in connection with the
618 | Program, unless a warranty or assumption of liability accompanies a
619 | copy of the Program in return for a fee.
620 |
621 | END OF TERMS AND CONDITIONS
622 |
623 | How to Apply These Terms to Your New Programs
624 |
625 | If you develop a new program, and you want it to be of the greatest
626 | possible use to the public, the best way to achieve this is to make it
627 | free software which everyone can redistribute and change under these terms.
628 |
629 | To do so, attach the following notices to the program. It is safest
630 | to attach them to the start of each source file to most effectively
631 | state the exclusion of warranty; and each file should have at least
632 | the "copyright" line and a pointer to where the full notice is found.
633 |
634 |
635 | Copyright (C)
636 |
637 | This program is free software: you can redistribute it and/or modify
638 | it under the terms of the GNU General Public License as published by
639 | the Free Software Foundation, either version 3 of the License, or
640 | (at your option) any later version.
641 |
642 | This program is distributed in the hope that it will be useful,
643 | but WITHOUT ANY WARRANTY; without even the implied warranty of
644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
645 | GNU General Public License for more details.
646 |
647 | You should have received a copy of the GNU General Public License
648 | along with this program. If not, see .
649 |
650 | Also add information on how to contact you by electronic and paper mail.
651 |
652 | If the program does terminal interaction, make it output a short
653 | notice like this when it starts in an interactive mode:
654 |
655 | Copyright (C)
656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
657 | This is free software, and you are welcome to redistribute it
658 | under certain conditions; type `show c' for details.
659 |
660 | The hypothetical commands `show w' and `show c' should show the appropriate
661 | parts of the General Public License. Of course, your program's commands
662 | might be different; for a GUI interface, you would use an "about box".
663 |
664 | You should also get your employer (if you work as a programmer) or school,
665 | if any, to sign a "copyright disclaimer" for the program, if necessary.
666 | For more information on this, and how to apply and follow the GNU GPL, see
667 | .
668 |
669 | The GNU General Public License does not permit incorporating your program
670 | into proprietary programs. If your program is a subroutine library, you
671 | may consider it more useful to permit linking proprietary applications with
672 | the library. If this is what you want to do, use the GNU Lesser General
673 | Public License instead of this License. But first, please read
674 | .
675 |
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | # CasioEmu
2 |
3 | I'm too lazy to add a fancy readme. The emulator has its own readme in its
4 | directory `emulator/`, check that one for instructions on building it.
5 |
--------------------------------------------------------------------------------
/disassembler/.gitattributes:
--------------------------------------------------------------------------------
1 | *.sh linguist-vendored
2 |
--------------------------------------------------------------------------------
/disassembler/.gitignore:
--------------------------------------------------------------------------------
1 | all.sh
2 |
--------------------------------------------------------------------------------
/disassembler/disassembler.lua:
--------------------------------------------------------------------------------
1 | #! /usr/bin/env luajit
2 |
3 | if not bit then
4 | bit = {}
5 |
6 | local function normalize(r)
7 | r = r % 0x100000000
8 | if r >= 0x80000000 then
9 | r = r - 0x100000000
10 | end
11 | return r
12 | end
13 |
14 | local function loopfunc(a, b, t, u)
15 | a = a % 0x100000000
16 | b = b % 0x100000000
17 | local r = 0
18 | for ix = 31, 0, -1 do
19 | local v = 2 ^ ix
20 | local m = 0
21 | if a >= v then
22 | a = a - v
23 | m = m + 1
24 | end
25 | if b >= v then
26 | b = b - v
27 | m = m + 1
28 | end
29 | if m == t or m == u then
30 | r = r + v
31 | end
32 | end
33 | return normalize(r)
34 | end
35 |
36 | function bit.band(a, b)
37 | return loopfunc(a, b, 2)
38 | end
39 |
40 | function bit.bor(a, b)
41 | return loopfunc(a, b, 1, 2)
42 | end
43 |
44 | function bit.bxor(a, b)
45 | return loopfunc(a, b, 1)
46 | end
47 |
48 | function bit.lshift(a, b)
49 | return normalize(a * 2 ^ b)
50 | end
51 |
52 | function bit.rshift(a, b)
53 | return normalize(math.floor((a % 0x100000000) / 2 ^ b))
54 | end
55 |
56 | function bit.arshift(a, b) -- for completeness?
57 | return math.floor(normalize(a) / 2 ^ b)
58 | end
59 | end
60 |
61 | local args_assoc = {
62 | input = "/dev/stdin",
63 | output = "/dev/stdout",
64 | entry = "",
65 | complement_entries = false,
66 | strict = false,
67 | addresses = false,
68 | rom_window = 0
69 | }
70 |
71 | for ix, arg in next, {...} do
72 | local key, value = arg:match("^([^=]+)=(.+)$")
73 | if key then
74 | args_assoc[key] = value
75 | else
76 | args_assoc.input = arg
77 | end
78 | end
79 |
80 | args_assoc.rom_window = tonumber(args_assoc.rom_window)
81 |
82 | local DATA_LABEL_FORMAT = "d_%05X"
83 | local GLOBAL_LABEL_FORMAT = "f_%05X"
84 | local LOCAL_LABEL_FORMAT = ".l_%03X"
85 |
86 | local function print(thing, ...)
87 | io.stderr:write(tostring(thing))
88 | if ... then
89 | io.stderr:write(", ")
90 | print(...)
91 | else
92 | io.stderr:write("\n")
93 | end
94 | end
95 |
96 | local function printf(...)
97 | print(string.format(...))
98 | end
99 |
100 | local function panic(...)
101 | io.stderr:write("PANIC: ")
102 | printf(...)
103 | os.exit(1)
104 | end
105 |
106 | local function panic2(...)
107 | io.stderr:write("PANIC: ")
108 | printf(...)
109 | if args_assoc.strict then
110 | os.exit(1)
111 | end
112 | end
113 |
114 | local handle = io.open(args_assoc.input, "rb")
115 | if not handle then
116 | panic("Failed to open \"%s\"", args_assoc.input)
117 | end
118 | local binary_source = handle:read("*a")
119 | handle:close()
120 |
121 | local binary_source_length = #binary_source
122 | printf("Read %i bytes", binary_source_length)
123 |
124 | local formats
125 | do
126 | local condition_names = {"ge", "lt", "gt", "le", "ges", "lts", "gts", "les", "ne", "eq", "nv", "ov", "ps", "ns", "al"}
127 | formats = {
128 | [ "lab"] = {format = function(self, value, instr)
129 | if instr.context ~= value.context and not value.context_head then
130 | if not value.context then
131 | return value.name
132 | end
133 | return value.context.name .. value.name
134 | end
135 | return value.name
136 | end},
137 | ["dlab"] = {format = function(self, value, instr)
138 | if value.ref_instr then
139 | return ("%s+%i"):format(formats.lab:format(value.ref_instr.under_label, instr), value.address - value.ref_instr.under_label.address)
140 | end
141 | return value.name
142 | end},
143 | [ "str"] = "%s",
144 | [ "r"] = "r%i",
145 | [ "er"] = "er%i",
146 | [ "xr"] = "xr%i",
147 | [ "qr"] = "qr%i",
148 | [ "cr"] = "cr%i",
149 | [ "cer"] = "cer%i",
150 | [ "cxr"] = "cxr%i",
151 | [ "cqr"] = "cqr%i",
152 | [ "dsr"] = "dsr",
153 | [ "ea"] = "ea",
154 | [ "eap"] = "ea+",
155 | [ "im"] = "%i",
156 | [ "bo"] = "%i",
157 | [ "elr"] = "elr",
158 | [ "lr"] = "lr",
159 | [ "psw"] = "psw",
160 | ["epsw"] = "epsw",
161 | ["ecsr"] = "ecsr",
162 | [ "sp"] = "sp",
163 | [ "pc"] = "pc",
164 | [ "co"] = {format = function(self, value)
165 | return condition_names[value + 1]
166 | end},
167 | [ "jo"] = {format = function(self, value, instr)
168 | return ("%i"):format((instr.address + instr.length + value * 2) % 0x10000)
169 | end}
170 | }
171 | end
172 |
173 | print("Generating instruction lookup table...")
174 | local instruction_lookup = {}
175 | do
176 | local instruction_source = {
177 | {{ "add", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x8001, false, 0},
178 | {{ "add", { "r", 8, 0x000F}, { "im", 0, 0x00FF} }, 0x1000, false, 0},
179 | {{ "add", { "er", 8, 0x000E}, { "er", 4, 0x000E} }, 0xF006, false, 0},
180 | {{ "add", { "er", 8, 0x000E}, { "im", 0, -0x007F} }, 0xE080, false, 0},
181 | {{ "addc", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x8006, false, 0},
182 | {{ "addc", { "r", 8, 0x000F}, { "im", 0, 0x00FF} }, 0x6000, false, 0},
183 | {{ "and", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x8002, false, 0},
184 | {{ "and", { "r", 8, 0x000F}, { "im", 0, 0x00FF} }, 0x2000, false, 0},
185 | {{ "cmp", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x8007, false, 0},
186 | {{ "cmp", { "r", 8, 0x000F}, { "im", 0, 0x00FF} }, 0x7000, false, 0},
187 | {{ "cmpc", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x8005, false, 0},
188 | {{ "cmpc", { "r", 8, 0x000F}, { "im", 0, 0x00FF} }, 0x5000, false, 0},
189 | {{ "mov", { "er", 8, 0x000E}, { "er", 4, 0x000E} }, 0xF005, false, 0},
190 | {{ "mov", { "er", 8, 0x000E}, { "im", 0, -0x007F} }, 0xE000, false, 0},
191 | {{ "mov", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x8000, false, 0},
192 | {{ "mov", { "r", 8, 0x000F}, { "im", 0, 0x00FF} }, 0x0000, false, 0},
193 | {{ "or", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x8003, false, 0},
194 | {{ "or", { "r", 8, 0x000F}, { "im", 0, 0x00FF} }, 0x3000, false, 0},
195 | {{ "xor", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x8004, false, 0},
196 | {{ "xor", { "r", 8, 0x000F}, { "im", 0, 0x00FF} }, 0x4000, false, 0},
197 | {{ "cmp", { "er", 8, 0x000E}, { "er", 4, 0x000E} }, 0xF007, false, 0},
198 | {{ "sub", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x8008, false, 0},
199 | {{ "subc", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x8009, false, 0},
200 | {{ "sll", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x800A, false, 0},
201 | {{ "sll", { "r", 8, 0x000F}, { "im", 4, 0x0007} }, 0x900A, false, 0},
202 | {{ "sllc", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x800B, false, 0},
203 | {{ "sllc", { "r", 8, 0x000F}, { "im", 4, 0x0007} }, 0x900B, false, 0},
204 | {{ "sra", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x800E, false, 0},
205 | {{ "sra", { "r", 8, 0x000F}, { "im", 4, 0x0007} }, 0x900E, false, 0},
206 | {{ "srl", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x800C, false, 0},
207 | {{ "srl", { "r", 8, 0x000F}, { "im", 4, 0x0007} }, 0x900C, false, 0},
208 | {{ "srlc", { "r", 8, 0x000F}, { "r", 4, 0x000F} }, 0x800D, false, 0},
209 | {{ "srlc", { "r", 8, 0x000F}, { "im", 4, 0x0007} }, 0x900D, false, 0},
210 | {{ "l", { "er", 8, 0x000E}, { "ea", 0, 0x0000} }, 0x9032, false, 2},
211 | {{ "l", { "er", 8, 0x000E}, { "eap", 0, 0x0000} }, 0x9052, false, 2},
212 | {{ "l", { "er", 8, 0x000E}, { "er", 4, 0x000E} }, 0x9002, false, 2},
213 | {{ "l", { "er", 8, 0x000E}, { "er", 4, 0x000E}, {"im", 16, 0xFFFF}}, 0xA008, true, 2},
214 | {{ "l", { "er", 8, 0x000E}, { "er", -1, 0x000C}, {"im", 0, -0x003F}}, 0xB000, false, 2},
215 | {{ "l", { "er", 8, 0x000E}, { "er", -1, 0x000E}, {"im", 0, -0x003F}}, 0xB040, false, 2},
216 | {{ "l", { "er", 8, 0x000E}, { "im", 16, 0xFFFF} }, 0x9012, true, 2},
217 | {{ "l", { "r", 8, 0x000F}, { "ea", 0, 0x0000} }, 0x9030, false, 2},
218 | {{ "l", { "r", 8, 0x000F}, { "eap", 0, 0x0000} }, 0x9050, false, 2},
219 | {{ "l", { "r", 8, 0x000F}, { "er", 4, 0x000E} }, 0x9000, false, 2},
220 | {{ "l", { "r", 8, 0x000F}, { "er", 4, 0x000E}, {"im", 16, 0xFFFF}}, 0x9008, true, 2},
221 | {{ "l", { "r", 8, 0x000F}, { "er", -1, 0x000C}, {"im", 0, -0x003F}}, 0xD000, false, 2},
222 | {{ "l", { "r", 8, 0x000F}, { "er", -1, 0x000E}, {"im", 0, -0x003F}}, 0xD040, false, 2},
223 | {{ "l", { "r", 8, 0x000F}, { "im", 16, 0xFFFF} }, 0x9010, true, 2},
224 | {{ "l", { "xr", 8, 0x000C}, { "ea", 0, 0x0000} }, 0x9034, false, 2},
225 | {{ "l", { "xr", 8, 0x000C}, { "eap", 0, 0x0000} }, 0x9054, false, 2},
226 | {{ "l", { "qr", 8, 0x0008}, { "ea", 0, 0x0000} }, 0x9036, false, 2},
227 | {{ "l", { "qr", 8, 0x0008}, { "eap", 0, 0x0000} }, 0x9056, false, 2},
228 | {{ "st", { "er", 8, 0x000E}, { "ea", 0, 0x0000} }, 0x9033, false, 2},
229 | {{ "st", { "er", 8, 0x000E}, { "eap", 0, 0x0000} }, 0x9053, false, 2},
230 | {{ "st", { "er", 8, 0x000E}, { "er", 4, 0x000E} }, 0x9003, false, 2},
231 | {{ "st", { "er", 8, 0x000E}, { "er", 4, 0x000E}, {"im", 16, 0xFFFF}}, 0xA009, true, 2},
232 | {{ "st", { "er", 8, 0x000E}, { "er", -1, 0x000C}, {"im", 0, -0x003F}}, 0xB080, false, 2},
233 | {{ "st", { "er", 8, 0x000E}, { "er", -1, 0x000E}, {"im", 0, -0x003F}}, 0xB0C0, false, 2},
234 | {{ "st", { "er", 8, 0x000E}, { "im", 16, 0xFFFF} }, 0x9013, true, 2},
235 | {{ "st", { "r", 8, 0x000F}, { "ea", 0, 0x0000} }, 0x9031, false, 2},
236 | {{ "st", { "r", 8, 0x000F}, { "eap", 0, 0x0000} }, 0x9051, false, 2},
237 | {{ "st", { "r", 8, 0x000F}, { "er", 4, 0x000E} }, 0x9001, false, 2},
238 | {{ "st", { "r", 8, 0x000F}, { "er", 4, 0x000E}, {"im", 16, 0xFFFF}}, 0x9009, true, 2},
239 | {{ "st", { "r", 8, 0x000F}, { "er", -1, 0x000C}, {"im", 0, -0x003F}}, 0xD080, false, 2},
240 | {{ "st", { "r", 8, 0x000F}, { "er", -1, 0x000E}, {"im", 0, -0x003F}}, 0xD0C0, false, 2},
241 | {{ "st", { "r", 8, 0x000F}, { "im", 16, 0xFFFF} }, 0x9011, true, 2},
242 | {{ "st", { "xr", 8, 0x000C}, { "ea", 0, 0x0000} }, 0x9035, false, 2},
243 | {{ "st", { "xr", 8, 0x000C}, { "eap", 0, 0x0000} }, 0x9055, false, 2},
244 | {{ "st", { "qr", 8, 0x0008}, { "ea", 0, 0x0000} }, 0x9037, false, 2},
245 | {{ "st", { "qr", 8, 0x0008}, { "eap", 0, 0x0000} }, 0x9057, false, 2},
246 | {{ "add", { "sp", 0, 0x0000}, { "im", 0, -0x00FF} }, 0xE100, false, 0},
247 | {{ "mov", {"ecsr", 0, 0x0000}, { "r", 4, 0x000F} }, 0xA00F, false, 0},
248 | {{ "mov", { "elr", 0, 0x0000}, { "er", 8, 0x000E} }, 0xA00D, false, 0},
249 | {{ "mov", {"epsw", 0, 0x0000}, { "r", 4, 0x000F} }, 0xA00C, false, 0},
250 | {{ "mov", { "er", 8, 0x000E}, { "elr", 0, 0x0000} }, 0xA005, false, 0},
251 | {{ "mov", { "er", 8, 0x000E}, { "sp", 0, 0x0000} }, 0xA01A, false, 0},
252 | {{ "mov", { "psw", 0, 0x0000}, { "r", 4, 0x000F} }, 0xA00B, false, 0},
253 | {{ "mov", { "psw", 0, 0x0000}, { "im", 0, 0x00FF} }, 0xE900, false, 0},
254 | {{ "mov", { "r", 8, 0x000F}, {"ecsr", 0, 0x0000} }, 0xA007, false, 0},
255 | {{ "mov", { "r", 8, 0x000F}, {"epsw", 0, 0x0000} }, 0xA004, false, 0},
256 | {{ "mov", { "r", 8, 0x000F}, { "psw", 0, 0x0000} }, 0xA003, false, 0},
257 | {{ "mov", { "sp", 0, 0x0000}, { "er", 4, 0x000E} }, 0xA10A, false, 0},
258 | {{ "push", { "er", 8, 0x000E} }, 0xF05E, false, 0},
259 | {{ "push", { "qr", 8, 0x0008} }, 0xF07E, false, 0},
260 | {{ "push", { "r", 8, 0x000F} }, 0xF04E, false, 0},
261 | {{ "push", { "xr", 8, 0x000C} }, 0xF06E, false, 0},
262 | {{ "push", {"push", 8, 0x000F} }, 0xF0CE, false, 0},
263 | {{ "pop", { "er", 8, 0x000E} }, 0xF01E, false, 0},
264 | {{ "pop", { "qr", 8, 0x0008} }, 0xF03E, false, 0},
265 | {{ "pop", { "r", 8, 0x000F} }, 0xF00E, false, 0},
266 | {{ "pop", { "xr", 8, 0x000C} }, 0xF02E, false, 0},
267 | {{ "pop", { "pop", 8, 0x000F} }, 0xF08E, false, 0},
268 | {{ "mov", { "cr", 8, 0x000F}, { "r", 4, 0x000F} }, 0xA00E, false, 0},
269 | {{ "mov", { "cer", 8, 0x000E}, { "ea", 0, 0x0000} }, 0xF02D, false, 2},
270 | {{ "mov", { "cer", 8, 0x000E}, { "eap", 0, 0x0000} }, 0xF03D, false, 2},
271 | {{ "mov", { "cr", 8, 0x000F}, { "ea", 0, 0x0000} }, 0xF00D, false, 2},
272 | {{ "mov", { "cr", 8, 0x000F}, { "eap", 0, 0x0000} }, 0xF01D, false, 2},
273 | {{ "mov", { "cxr", 8, 0x000C}, { "ea", 0, 0x0000} }, 0xF04D, false, 2},
274 | {{ "mov", { "cxr", 8, 0x000C}, { "eap", 0, 0x0000} }, 0xF05D, false, 2},
275 | {{ "mov", { "cqr", 8, 0x0008}, { "ea", 0, 0x0000} }, 0xF06D, false, 2},
276 | {{ "mov", { "cqr", 8, 0x0008}, { "eap", 0, 0x0000} }, 0xF07D, false, 2},
277 | {{ "mov", { "r", 4, 0x000F}, { "cr", 8, 0x000F} }, 0xA006, false, 0},
278 | {{ "mov", { "ea", 0, 0x0000}, { "cer", 8, 0x000E} }, 0xF0AD, false, 1},
279 | {{ "mov", { "eap", 0, 0x0000}, { "cer", 8, 0x000E} }, 0xF0BD, false, 1},
280 | {{ "mov", { "ea", 0, 0x0000}, { "cr", 8, 0x000F} }, 0xF08D, false, 1},
281 | {{ "mov", { "eap", 0, 0x0000}, { "cr", 8, 0x000F} }, 0xF09D, false, 1},
282 | {{ "mov", { "ea", 0, 0x0000}, { "cxr", 8, 0x000C} }, 0xF0CD, false, 1},
283 | {{ "mov", { "eap", 0, 0x0000}, { "cxr", 8, 0x000C} }, 0xF0DD, false, 1},
284 | {{ "mov", { "ea", 0, 0x0000}, { "cqr", 8, 0x0008} }, 0xF0ED, false, 1},
285 | {{ "mov", { "eap", 0, 0x0000}, { "cqr", 8, 0x0008} }, 0xF0FD, false, 1},
286 | {{ "lea", { "er", 4, 0x000E} }, 0xF00A, false, 1},
287 | {{ "lea", { "er", 4, 0x000E}, { "im", 16, 0xFFFF} }, 0xF00B, true, 1},
288 | {{ "lea", { "im", 16, 0xFFFF} }, 0xF00C, true, 1},
289 | {{ "daa", { "r", 8, 0x000F} }, 0x801F, false, 0},
290 | {{ "das", { "r", 8, 0x000F} }, 0x803F, false, 0},
291 | {{ "neg", { "r", 8, 0x000F} }, 0x805F, false, 0},
292 | {{ "sb", { "r", 8, 0x000F}, { "bo", 4, 0x0007} }, 0xA000, false, 0},
293 | {{ "sb", { "im", 16, 0xFFFF}, { "bo", 4, 0x0007} }, 0xA080, true, 1},
294 | {{ "rb", { "r", 8, 0x000F}, { "bo", 4, 0x0007} }, 0xA002, false, 0},
295 | {{ "rb", { "im", 16, 0xFFFF}, { "bo", 4, 0x0007} }, 0xA082, true, 1},
296 | {{ "tb", { "r", 8, 0x000F}, { "bo", 4, 0x0007} }, 0xA001, false, 0},
297 | {{ "tb", { "im", 16, 0xFFFF}, { "bo", 4, 0x0007} }, 0xA081, true, 1},
298 | {{ "ei", }, 0xED08, false, 0},
299 | {{ "di", }, 0xEBF7, false, 0},
300 | {{ "sc", }, 0xED80, false, 0},
301 | {{ "rc", }, 0xEB7F, false, 0},
302 | {{ "clpc", }, 0xFECF, false, 0},
303 | {{ "bc", { "co", 8, 0x000F}, { "jo", 0, -0x00FF} }, 0xC000, false, 0},
304 | {{"extbw", { "er", -1, 0x0000} }, 0x810F, false, 0},
305 | {{"extbw", { "er", -1, 0x0002} }, 0x832F, false, 0},
306 | {{"extbw", { "er", -1, 0x0004} }, 0x854F, false, 0},
307 | {{"extbw", { "er", -1, 0x0006} }, 0x876F, false, 0},
308 | {{"extbw", { "er", -1, 0x0008} }, 0x898F, false, 0},
309 | {{"extbw", { "er", -1, 0x000A} }, 0x8BAF, false, 0},
310 | {{"extbw", { "er", -1, 0x000C} }, 0x8DCF, false, 0},
311 | {{"extbw", { "er", -1, 0x000E} }, 0x8FEF, false, 0},
312 | {{ "swi", { "im", 0, 0x003F} }, 0xE500, false, 0},
313 | {{ "brk", }, 0xFFFF, false, 0},
314 | {{ "b", { "im", 8, 0x000F}, { "im", 16, 0xFFFF} }, 0xF000, true, 0},
315 | {{ "b", { "er", 4, 0x000E} }, 0xF002, false, 0},
316 | {{ "bl", { "im", 8, 0x000F}, { "im", 16, 0xFFFF} }, 0xF001, true, 0},
317 | {{ "bl", { "er", 4, 0x000E} }, 0xF003, false, 0},
318 | {{ "mul", { "er", 8, 0x000E}, { "r", 4, 0x000F} }, 0xF004, false, 0},
319 | {{ "div", { "er", 8, 0x000E}, { "r", 4, 0x000F} }, 0xF009, false, 0},
320 | {{ "inc", { "ea", 0, 0x0000} }, 0xFE2F, false, 1},
321 | {{ "dec", { "ea", 0, 0x0000} }, 0xFE3F, false, 1},
322 | {{ "rt", }, 0xFE1F, false, 0},
323 | {{ "rti", }, 0xFE0F, false, 0},
324 | {{ "nop", }, 0xFE8F, false, 0},
325 | {{ "dsr", { "dsr", -1, 0xFFFF} }, 0xFE9F, false, 0},
326 | {{ "dsr", { "r", 4, 0x000F} }, 0x900F, false, 0},
327 | {{ "dsr", { "im", 0, 0x00FF} }, 0xE300, false, 0},
328 | }
329 |
330 | for ix, def in next, instruction_source do
331 | local repr, imask, has_imm, addr = def[1], def[2], def[3], def[4]
332 | local function instruction_emit_func(instruction, imm16)
333 | local params_out = {}
334 | for ix = 2, #repr do
335 | local fmt, shift, pmask = unpack(repr[ix])
336 | local signed = pmask < 0
337 | pmask = math.abs(pmask)
338 | local fmtvalue = instruction
339 | if shift == 16 then
340 | shift = 0
341 | fmtvalue = imm16
342 | end
343 | if shift < 0 then
344 | shift = 0
345 | fmtvalue = pmask
346 | pmask = -1
347 | end
348 | fmtvalue = bit.band(bit.rshift(fmtvalue, shift), pmask)
349 | if signed then
350 | if bit.band(fmtvalue, bit.rshift(pmask + 1, 1)) ~= 0 then
351 | fmtvalue = bit.bor(bit.bxor(-1, pmask), fmtvalue)
352 | end
353 | end
354 | table.insert(params_out, {fmtvalue, fmt})
355 | end
356 | local result = {
357 | mnemonic = repr[1],
358 | instruction = instruction,
359 | imm16 = imm16,
360 | params = params_out,
361 | offsetable = addr
362 | }
363 | return result
364 | end
365 | local vmask = 0
366 | for ix = 2, #repr do
367 | local shift, pmask = repr[ix][2], math.abs(repr[ix][3])
368 | if shift >= 0 then
369 | vmask = bit.bor(vmask, bit.lshift(pmask, shift))
370 | end
371 | end
372 | local maskvariants = {[0] = true}
373 | for ix = 0, 15 do
374 | local cbit = bit.lshift(1, ix)
375 | if bit.band(vmask, cbit) ~= 0 then
376 | local newmaskvariants = {}
377 | for key in next, maskvariants do
378 | newmaskvariants[key] = true
379 | newmaskvariants[bit.bor(key, cbit)] = true
380 | end
381 | maskvariants = newmaskvariants
382 | end
383 | end
384 | local instruction_stub = {
385 | has_imm,
386 | instruction_emit_func
387 | }
388 | for key in next, maskvariants do
389 | local lkey = bit.bor(imask, key) + 1
390 | if instruction_lookup[lkey] then
391 | printf("%04X, %04X, %04X", imask, key, lkey - 1)
392 | panic("lookupgen: clash")
393 | end
394 | instruction_lookup[lkey] = instruction_stub
395 | end
396 | end
397 | do
398 | local instruction_stub = {
399 | false,
400 | function(instruction, imm16)
401 | return {
402 | mnemonic = "?",
403 | instruction = instruction,
404 | imm16 = imm16,
405 | params = {},
406 | offsetable = 0,
407 | opcode = {instruction}
408 | }
409 | end
410 | }
411 | for ix = 0x0000, 0xFFFF do
412 | if not instruction_lookup[ix + 1] then
413 | instruction_lookup[ix + 1] = instruction_stub
414 | end
415 | end
416 | end
417 | end
418 | print(" Done.")
419 |
420 | local function fetch(address)
421 | return binary_source:byte(address + 1) + 0x100 * binary_source:byte(address + 2)
422 | end
423 |
424 | local instruction_by_address = {}
425 | local function disassemble(segment, address)
426 | local full_address = segment + address
427 | local fetch_addr = address
428 | if instruction_by_address[full_address] then
429 | if instruction_by_address[full_address].head then
430 | panic("disassemble: requesting tail at %01X:%04X", bit.rshift(segment, 16), address)
431 | end
432 | return instruction_by_address[full_address], true
433 | end
434 | local instruction_data = {}
435 |
436 | local state = {}
437 | local instruction_stub
438 |
439 | local length = 0
440 | local opcode, imm16, dsr, result
441 | local opcode_data = {}
442 | while true do
443 | local word = fetch(segment + fetch_addr)
444 | table.insert(opcode_data, word)
445 | fetch_addr = bit.band(fetch_addr + 2, 0xFFFF)
446 | length = length + 2
447 | if imm16 == true then
448 | imm16 = word
449 | end
450 | if not opcode then
451 | opcode = word
452 | instruction_stub = instruction_lookup[opcode + 1]
453 | if instruction_stub[1] then
454 | imm16 = true
455 | end
456 | end
457 | if imm16 ~= true then
458 | result = instruction_stub[2](opcode, imm16)
459 | end
460 | if result then
461 | if result.mnemonic == "dsr" then
462 | if dsr then
463 | panic("disassemble: double dsr at %01X:%04X", bit.rshift(segment, 16), address)
464 | end
465 | dsr = result.params[1]
466 | opcode = false
467 | imm16 = false
468 | result = false
469 | elseif result.mnemonic == "push" and result.params[1][2] == "push" then
470 | local mask = result.params[1][1]
471 | result.params = {}
472 | if bit.band(mask, 2) ~= 0 then table.insert(result.params, {0, "elr"}) end
473 | if bit.band(mask, 4) ~= 0 then table.insert(result.params, {0, "epsw"}) end
474 | if bit.band(mask, 8) ~= 0 then table.insert(result.params, {0, "lr"}) end
475 | if bit.band(mask, 1) ~= 0 then table.insert(result.params, {0, "ea"}) end
476 | elseif result.mnemonic == "pop" and result.params[1][2] == "pop" then
477 | local mask = result.params[1][1]
478 | result.params = {}
479 | if bit.band(mask, 1) ~= 0 then table.insert(result.params, {0, "ea"}) end
480 | if bit.band(mask, 8) ~= 0 then table.insert(result.params, {0, "lr"}) end
481 | if bit.band(mask, 4) ~= 0 then table.insert(result.params, {0, "psw"}) end
482 | if bit.band(mask, 2) ~= 0 then table.insert(result.params, {0, "pc"}) end
483 | end
484 | end
485 | if result then
486 | break
487 | end
488 | end
489 | result.address = full_address
490 | result.dsr = dsr
491 | result.length = length
492 | result.opcode = opcode_data
493 | instruction_by_address[full_address] = result
494 | for ix = 2, length - 2 do
495 | instruction_by_address[full_address + ix] = {
496 | head = result
497 | }
498 | end
499 | return result
500 | end
501 |
502 | local datalabel_by_address = {}
503 | local function add_data_label(address, xref)
504 | local label_obj = datalabel_by_address[address]
505 | if not label_obj then
506 | label_obj = {
507 | address = address,
508 | name = DATA_LABEL_FORMAT:format(address),
509 | xrefs = {}
510 | }
511 | datalabel_by_address[address] = label_obj
512 | end
513 | if xref then
514 | label_obj.xrefs[xref] = true
515 | end
516 | return label_obj
517 | end
518 |
519 | local label_by_address = {}
520 | local function add_label(streak, address, xref)
521 | local label_obj = label_by_address[address]
522 | if not label_obj then
523 | label_obj = {
524 | address = address,
525 | name = GLOBAL_LABEL_FORMAT:format(address),
526 | xrefs = {},
527 | streak = streak
528 | }
529 | label_by_address[address] = label_obj
530 | end
531 | if xref then
532 | label_obj.xrefs[xref] = true
533 | end
534 | return label_obj
535 | end
536 |
537 | local comments_by_address = {}
538 | local function add_comment(address, comment)
539 | comments_by_address[address] = comments_by_address[address] or {}
540 | table.insert(comments_by_address[address], comment)
541 | end
542 | local function add_jt_comment(address, ix, label_obj)
543 | add_comment(address, {
544 | type = "jt",
545 | ix = ix,
546 | label = label_obj
547 | })
548 | end
549 |
550 | local function make_streak()
551 | return {
552 | friends = {}
553 | }
554 | end
555 |
556 | local image_iterator
557 | do
558 | local function image_next(st, address)
559 | if address >= st.length then
560 | return
561 | end
562 | local instr = st.store[address]
563 | local next_address
564 | if instr then
565 | next_address = address + instr.length
566 | else
567 | next_address = address + 2
568 | end
569 | return next_address, address, instr, st.label[address]
570 | end
571 |
572 | function image_iterator()
573 | return image_next, {
574 | length = binary_source_length,
575 | store = instruction_by_address,
576 | label = label_by_address
577 | }, 0
578 | end
579 | end
580 |
581 | print("Disassembling binary...")
582 | local to_disassemble = {}
583 | do
584 | local entry_ords_in = {}
585 | for entry in args_assoc.entry:gmatch("[^,]+") do
586 | local entry_ord = tonumber(entry)
587 | if not entry_ord then
588 | panic("invalid entry ordinal %s", entry)
589 | end
590 | entry_ords_in[entry_ord] = true
591 | end
592 | if args_assoc.complement_entries then
593 | for entry_ord = 1, 127 do
594 | entry_ords_in[entry_ord] = not entry_ords_in[entry_ord] and true or nil
595 | end
596 | end
597 | for entry_ord in next, entry_ords_in do
598 | local address = fetch(math.floor(2 * entry_ord))
599 | if address % 2 == 0 then
600 | local new_streak = make_streak()
601 | local label_obj = add_label(new_streak, address)
602 | to_disassemble[{0, address, new_streak}] = true
603 | else
604 | printf("ignoring entry %s (%04X)", entry_ord, address)
605 | end
606 | end
607 | end
608 |
609 | local resolve_variable_branch
610 | do
611 | local function prev_instr(instr)
612 | local result = instruction_by_address[bit.band(instr.address, 0xF0000) + bit.band(instr.address - 2, 0xFFFF)]
613 | if not result then
614 | return
615 | end
616 | return result.head or result
617 | end
618 |
619 | local function instruction_match(instr, mnemonic, ...)
620 | if not instr then
621 | return
622 | end
623 | if instr.mnemonic ~= mnemonic then
624 | return
625 | end
626 | return true
627 | end
628 |
629 | function resolve_variable_branch(bl_instr, new_to_disassemble, streak)
630 | --[[
631 | cmp A, B
632 | cmpc A, B
633 | bc A
634 | b A
635 | (
636 | cmp A, B
637 | cmpc A, B
638 | bc A
639 | b A
640 | )?
641 | (
642 | add A, B
643 | addc A, B
644 | )?
645 | sllc A
646 | sll A
647 | l A, (B:)?C[D]
648 | ]]
649 |
650 | local l_instr = prev_instr(bl_instr)
651 | if not instruction_match(l_instr, "l") then
652 | return
653 | end
654 | if l_instr.dsr then
655 | return
656 | end
657 | if not l_instr.params[3] or l_instr.params[3][2] ~= "dlab" then
658 | return
659 | end
660 | local map_base = l_instr.params[3][1].address
661 |
662 | local sll_instr = prev_instr(l_instr)
663 | if not instruction_match(sll_instr, "sll") then
664 | return
665 | end
666 | local sllc_instr = prev_instr(sll_instr)
667 | if not instruction_match(sllc_instr, "sllc") then
668 | return
669 | end
670 | local offset_instr = prev_instr(sllc_instr)
671 |
672 | local offset = 0
673 |
674 | local offset_instr_2 = prev_instr(offset_instr)
675 | if instruction_match(offset_instr, "addc") then
676 | offset = offset + bit.lshift(offset_instr.params[2][1], 8)
677 | else
678 | offset_instr_2 = offset_instr
679 | end
680 |
681 | local branch_4 = prev_instr(offset_instr_2)
682 | if instruction_match(offset_instr_2, "add") then
683 | offset = offset + offset_instr_2.params[2][1]
684 | else
685 | branch_4 = offset_instr_2
686 | end
687 |
688 | local branch_3, branch_1, cmp_1, cmpc_1, cmp_2, cmpc_2
689 | repeat
690 | branch_3 = prev_instr(branch_4)
691 | if not instruction_match(branch_4, "b") then
692 | branch_3 = branch_4
693 | end
694 | if not instruction_match(branch_3, "bc") then
695 | return
696 | end
697 | cmpc_2 = prev_instr(branch_3)
698 |
699 | if not instruction_match(cmpc_2, "cmpc") then
700 | return
701 | end
702 | cmp_2 = prev_instr(cmpc_2)
703 | if not instruction_match(cmp_2, "cmp") then
704 | return
705 | end
706 | local branch_2 = prev_instr(cmp_2)
707 |
708 | branch_1 = prev_instr(branch_2)
709 | if not instruction_match(branch_2, "b") then
710 | branch_1 = branch_2
711 | end
712 | if not instruction_match(branch_1, "bc") then
713 | break
714 | end
715 | if branch_1.params[1][1] > 3 then
716 | break
717 | end
718 | cmpc_1 = prev_instr(branch_1)
719 |
720 | if not instruction_match(cmpc_1, "cmpc") then
721 | return
722 | end
723 | cmp_1 = prev_instr(cmpc_1)
724 | if not instruction_match(cmp_1, "cmp") then
725 | return
726 | end
727 | until true
728 |
729 | local cmp_value, cmp_cond = {}, {}
730 | if cmp_1 then
731 | cmp_value[1] = cmp_1.params[2][1] + bit.lshift(cmpc_1.params[2][1], 8)
732 | cmp_cond[1] = branch_1.params[1][1]
733 | end
734 | cmp_value[2] = cmp_2.params[2][1] + bit.lshift(cmpc_2.params[2][1], 8)
735 | cmp_cond[2] = branch_3.params[1][1]
736 |
737 | local min, max
738 | for ix = 1, 2 do
739 | if cmp_cond[ix] then
740 | if cmp_cond[ix] == 0 then
741 | min = cmp_value[ix]
742 | end
743 | if cmp_cond[ix] == 1 then
744 | max = cmp_value[ix] - 1
745 | end
746 | if cmp_cond[ix] == 2 then
747 | min = cmp_value[ix] + 1
748 | end
749 | if cmp_cond[ix] == 3 then
750 | max = cmp_value[ix]
751 | end
752 | end
753 | end
754 |
755 | if not max and min then
756 | max = min - 1
757 | min = 0
758 | end
759 | if not min and max then
760 | min = 0
761 | end
762 |
763 | if not min or not max then
764 | printf("fail %05X", bl_instr.address)
765 | return
766 | end
767 | min = min + offset
768 | max = max + offset
769 |
770 | if max < min then
771 | min, max = max + 1, min - 1
772 | end
773 |
774 | min, max = bit.band(min, 0xFFFF), bit.band(max, 0xFFFF)
775 |
776 | add_comment(bl_instr.address, "Jump table")
777 | local td_segment = bit.band(bl_instr.address, 0xF0000)
778 | for ix = min, max do
779 | local td_address = fetch(bit.band(map_base + ix * 2, 0xFFFF))
780 | new_to_disassemble[{td_segment, td_address, streak}] = true
781 | local label_obj = add_label(streak, td_segment + td_address, bl_instr)
782 | add_jt_comment(bl_instr.address, ix, label_obj)
783 | end
784 |
785 | return true
786 | end
787 | end
788 |
789 | while next(to_disassemble) do
790 | local variable_branches = {}
791 | while next(to_disassemble) do
792 | local new_to_disassemble = {}
793 | for address_tuple in next, to_disassemble do
794 | local segment, address, streak = unpack(address_tuple)
795 | if segment + address >= binary_source_length then
796 | panic2("runloop: out of data at %01X:%04X", bit.rshift(segment, 16), address)
797 | break
798 | end
799 | while true do
800 | local instr, seen = disassemble(segment, address)
801 | if seen then
802 | break
803 | end
804 | if instr.mnemonic == "?" then
805 | panic2("runloop: unknown instruction at %01X:%04X", bit.rshift(segment, 16), address)
806 | break
807 | end
808 | address = bit.band(address + instr.length, 0xFFFF)
809 | if instr.mnemonic == "rt"
810 | or instr.mnemonic == "rti"
811 | or (instr.mnemonic == "pop" and (
812 | (instr.params[1] and instr.params[1][2] == "pc") or
813 | (instr.params[2] and instr.params[2][2] == "pc") or
814 | (instr.params[3] and instr.params[3][2] == "pc") or
815 | (instr.params[4] and instr.params[4][2] == "pc")
816 | )) then
817 | instr.break_streak = true
818 | end
819 | if instr.mnemonic == "bc" then
820 | local td_segment = segment
821 | local td_address = bit.band(address + instr.params[2][1] * 2, 0xFFFF)
822 | local label_obj = add_label(streak, td_segment + td_address, instr)
823 | new_to_disassemble[{td_segment, td_address, streak}] = true
824 | instr.params[2] = {label_obj, "lab"}
825 | if instr.params[1][1] == 0x000E then
826 | instr.break_streak = true
827 | end
828 | end
829 | if instr.mnemonic == "b" or instr.mnemonic == "bl" then
830 | if instr.params[1][2] == "im" then
831 | local td_segment = bit.lshift(instr.params[1][1], 16)
832 | local td_address = instr.params[2][1]
833 | local new_streak = make_streak()
834 | local label_obj = add_label(new_streak, td_segment + td_address, instr)
835 | new_to_disassemble[{td_segment, td_address, new_streak}] = true
836 | instr.params[2] = nil
837 | instr.params[1] = {label_obj, "lab"}
838 | else
839 | variable_branches[instr] = streak
840 | end
841 | if instr.mnemonic == "b" then
842 | instr.break_streak = true
843 | end
844 | end
845 | if (instr.mnemonic == "l"
846 | or instr.mnemonic == "st"
847 | or instr.mnemonic == "lea"
848 | or instr.mnemonic == "sb"
849 | or instr.mnemonic == "tb"
850 | or instr.mnemonic == "rb")
851 | and (not instr.dsr or (instr.dsr and instr.dsr[2] == "im")) then
852 | local td_segment = instr.dsr and instr.dsr[1] or 0
853 | for ix = 1, #instr.params do
854 | if instr.params[ix][2] == "im" and instr.params[ix][1] >= 0x100 and instr.params[ix][1] < 0xFF00 then
855 | local td_address = instr.params[ix][1]
856 | local label_obj = add_data_label(td_segment + td_address, instr)
857 | instr.params[ix] = {label_obj, "dlab"}
858 | end
859 | end
860 | end
861 | if instr.break_streak then
862 | break
863 | end
864 | end
865 | end
866 | to_disassemble = new_to_disassemble
867 | end
868 |
869 | for instr, streak in next, variable_branches do
870 | local segment = bit.band(instr.address, 0xF0000)
871 | local address = bit.band(instr.address, 0xFFFF)
872 | if not resolve_variable_branch(instr, to_disassemble, streak) then
873 | printf("runloop: failed to resolve variable branch at %01X:%04X", bit.rshift(segment, 16), address)
874 | add_comment(instr.address, "Failed to resolve variable branch")
875 | end
876 | end
877 | end
878 | print(" Done.")
879 |
880 | print("Discovering contexts...")
881 | do
882 | local function make_streak_friends(one, other)
883 | if other.streak ~= one.streak then
884 | one.streak.friends[other.streak] = true
885 | other.streak.friends[one.streak] = true
886 | end
887 | end
888 |
889 | local streaks = {}
890 | local last_label
891 | for next_address, address, instr, label_obj in image_iterator() do
892 | if instr and label_obj then
893 | if last_label then
894 | make_streak_friends(last_label, label_obj)
895 | end
896 | last_label = label_obj
897 | streaks[last_label.streak] = true
898 | end
899 | if instr then
900 | if instr.mnemonic == "bc" or (instr.mnemonic == "b" and instr.params[1][2] == "lab") then
901 | local other_label_obj = instr.params[2] and instr.params[2][1] or instr.params[1][1]
902 | make_streak_friends(other_label_obj, last_label)
903 | end
904 | if instr.break_streak then
905 | last_label = nil
906 | end
907 | end
908 | end
909 | for streak in next, streaks do
910 | if not streak.seen then
911 | local friend_streaks = {}
912 | local streaks_to_check = {[streak] = true}
913 | streak.seen = true
914 | while next(streaks_to_check) do
915 | local new_streaks_to_check = {}
916 | for next_streak in next, streaks_to_check do
917 | friend_streaks[next_streak] = true
918 | for friend_streak in next, next_streak.friends do
919 | if not friend_streak.seen then
920 | new_streaks_to_check[friend_streak] = true
921 | friend_streak.seen = true
922 | end
923 | end
924 | end
925 | streaks_to_check = new_streaks_to_check
926 | end
927 | local new_context = {}
928 | for streak in next, friend_streaks do
929 | streak.context = new_context
930 | end
931 | end
932 | end
933 | end
934 | for next_address, address, instr, label in image_iterator() do
935 | if instr and label then
936 | label.context = label.streak.context
937 | label.streak = nil
938 | end
939 | end
940 | do
941 | local contexts_seen = {}
942 | local rewrite_from, rewrite_to
943 | local last_label
944 | for next_address, address, instr, label in image_iterator() do
945 | if instr and label then
946 | if last_label and label.context ~= last_label.context and contexts_seen[label.context] then
947 | if label.context ~= rewrite_from then
948 | rewrite_from, rewrite_to = label.context, {}
949 | end
950 | label.context = rewrite_to
951 | else
952 | rewrite_from = nil
953 | end
954 | contexts_seen[label.context] = true
955 | last_label = label
956 | end
957 | end
958 | end
959 | do
960 | local last_label
961 | for next_address, address, instr, label in image_iterator() do
962 | if instr and label then
963 | last_label = label
964 | if label.context.name then
965 | label.name = LOCAL_LABEL_FORMAT:format(label.address - label.context.head.address)
966 | else
967 | label.context.name = label.name
968 | label.context.head = label
969 | label.context_head = true
970 | end
971 | end
972 | if instr then
973 | instr.context = last_label.context
974 | instr.under_label = last_label
975 | end
976 | end
977 | for address, datalabel in next, datalabel_by_address do
978 | if address >= 0x10000 or address < args_assoc.rom_window then
979 | local instr = instruction_by_address[address]
980 | instr = instr and instr.head or instr
981 | if instr then
982 | datalabel.ref_instr = instr
983 | printf("context: warning: data label pointing into code at %01X:%04X", bit.rshift(address, 16), bit.band(address, 0xFFFF))
984 | end
985 | end
986 | end
987 | end
988 | print(" Done.")
989 |
990 | if args_assoc.names then
991 | print("Renaming labels...")
992 | local handle = io.open(args_assoc.names, "r")
993 | if not handle then
994 | panic("Failed to open \"%s\"", args_assoc.names)
995 | end
996 | local name_content = handle:read("*a")
997 | handle:close()
998 | local raw_to_real = {}
999 | local last_global_label
1000 | for line in name_content:gmatch("[^\n]+") do
1001 | local raw, real = line:match("([%w_%.]+)%s+([%w_%.]+)")
1002 | if raw then
1003 | if raw:find("^%.") then
1004 | if not last_global_label then
1005 | panic("rename: fix that rename list pls")
1006 | end
1007 | raw_to_real[last_global_label .. raw] = real
1008 | else
1009 | last_global_label = raw
1010 | raw_to_real[raw] = real
1011 | end
1012 | end
1013 | end
1014 | for address, label in next, label_by_address do
1015 | local raw = label.name:find("^%.") and (label.context.name .. label.name) or label.name
1016 | local real = raw_to_real[raw]
1017 | if real then
1018 | label.name = real
1019 | end
1020 | end
1021 | for address, datalabel in next, datalabel_by_address do
1022 | local raw = datalabel.name
1023 | local real = raw_to_real[raw]
1024 | if real then
1025 | datalabel.name = real
1026 | end
1027 | end
1028 | print(" Done.")
1029 | end
1030 |
1031 | print("Writing disassembly...")
1032 | local handle = io.open(args_assoc.output, "w")
1033 | if not handle then
1034 | panic("Failed to open \"%s\"", args_assoc.output)
1035 | end
1036 | do
1037 | local last_instr
1038 | for next_address, address, instr, label in image_iterator() do
1039 | local instr = instruction_by_address[address]
1040 | if ((not last_instr) ~= (not instr)) or (last_instr and instr and last_instr.context ~= instr.context) then
1041 | handle:write("\n\n\n")
1042 | end
1043 |
1044 | local comments = comments_by_address[address]
1045 | if comments then
1046 | for ix = 1, #comments do
1047 | handle:write("; ")
1048 | if comments[ix].type == "jt" then
1049 | handle:write((" %4i | %s"):format(comments[ix].ix, formats.lab:format(comments[ix].label, instr)))
1050 | else
1051 | handle:write(comments[ix])
1052 | end
1053 | handle:write("\n")
1054 | end
1055 | end
1056 | if label then
1057 | handle:write(("%s:\n"):format(label.name))
1058 | end
1059 |
1060 | local out_head = {}
1061 | local out_body = {}
1062 | local out_tail
1063 | if args_assoc.addresses then
1064 | out_tail = {("; %05X |"):format(address)}
1065 | end
1066 |
1067 | if instr then
1068 | table.insert(out_head, instr.mnemonic)
1069 | for ix = 1, #instr.params do
1070 | if instr.offsetable ~= 0 and instr.offsetable == ix - 1 and (instr.params[ix][2] == "dlab" or instr.params[ix][2] == "im") then
1071 | if instr.params[ix][2] == "im" and instr.params[ix][1] >= 0xFF00 then
1072 | instr.params[ix][1] = instr.params[ix][1] - 0x10000
1073 | end
1074 | out_body[#out_body] = out_body[#out_body]:gsub("%[", formats[instr.params[ix][2]]:format(instr.params[ix][1], instr) .. "[")
1075 | else
1076 | local paramtbl = {}
1077 | if instr.offsetable == ix then
1078 | if instr.dsr then
1079 | table.insert(paramtbl, formats[instr.dsr[2]]:format(instr.dsr[1], instr))
1080 | table.insert(paramtbl, ":")
1081 | end
1082 | table.insert(paramtbl, "[")
1083 | end
1084 | table.insert(paramtbl, formats[instr.params[ix][2]]:format(instr.params[ix][1], instr))
1085 | if instr.offsetable == ix then
1086 | table.insert(paramtbl, "]")
1087 | end
1088 | table.insert(out_body, table.concat(paramtbl))
1089 | end
1090 | end
1091 | if args_assoc.addresses then
1092 | for ix = 1, instr.length / 2 do
1093 | table.insert(out_tail, ("%04X"):format(instr.opcode[ix]))
1094 | end
1095 | end
1096 | else
1097 | if address >= 0x10000 or address < args_assoc.rom_window then
1098 | local datalabel = datalabel_by_address[address]
1099 | if datalabel then
1100 | handle:write(("%s:\n"):format(datalabel.name))
1101 | end
1102 | end
1103 | table.insert(out_head, "dw")
1104 | local data = fetch(address)
1105 | table.insert(out_body, ("0x%04X"):format(data))
1106 | if args_assoc.addresses then
1107 | table.insert(out_tail, ("%04X"):format(data))
1108 | end
1109 | end
1110 |
1111 | table.insert(out_head, table.concat(out_body, ", "))
1112 |
1113 | if args_assoc.addresses then
1114 | handle:write(("\t%-30s %s\n"):format(
1115 | table.concat(out_head, " "),
1116 | table.concat(out_tail, " ")
1117 | ))
1118 | else
1119 | handle:write(("\t%s\n"):format(
1120 | table.concat(out_head, " ")
1121 | ))
1122 | end
1123 |
1124 |
1125 | last_instr = instr
1126 | end
1127 | end
1128 | handle:close()
1129 | print(" Done.")
1130 |
1131 |
1132 |
1133 |
1134 |
--------------------------------------------------------------------------------
/emulator/README.md:
--------------------------------------------------------------------------------
1 | # Emulator
2 |
3 | Assuming your current directory is this one, you have
4 | [meson](https://mesonbuild.com/) and [ninja](https://ninja-build.org/) installed
5 | and you have the proper ROM in `../../models/fx570esplus`:
6 |
7 | ```
8 | $ meson build && cd build
9 | $ meson configure -Dwerror=true -Dwarning_level=3 -Dcpp_std=c++11
10 | $ ninja
11 | $ ./emulator ../../models/fx570esplus
12 | ```
13 |
14 | Unlike the previous, terrible excuse of a build system, this one is likely to
15 | work well on platforms other than unices with coreutils and other shady stuff
16 | installed.
17 |
--------------------------------------------------------------------------------
/emulator/meson.build:
--------------------------------------------------------------------------------
1 | project('emulator', 'cpp', version: '1.0.0')
2 |
3 | executable('emulator', sources: [
4 | 'src/Logger.cpp',
5 | 'src/Peripheral/ROMWindow.cpp',
6 | 'src/Peripheral/Timer.cpp',
7 | 'src/Peripheral/Screen.cpp',
8 | 'src/Peripheral/StandbyControl.cpp',
9 | 'src/Peripheral/Keyboard.cpp',
10 | 'src/Peripheral/Miscellaneous.cpp',
11 | 'src/Peripheral/Peripheral.cpp',
12 | 'src/Peripheral/BatteryBackedRAM.cpp',
13 | 'src/Data/ModelInfo.cpp',
14 | 'src/casioemu.cpp',
15 | 'src/Emulator.cpp',
16 | 'src/Chipset/CPUPushPop.cpp',
17 | 'src/Chipset/CPU.cpp',
18 | 'src/Chipset/InterruptSource.cpp',
19 | 'src/Chipset/Chipset.cpp',
20 | 'src/Chipset/CPUArithmetic.cpp',
21 | 'src/Chipset/MMU.cpp',
22 | 'src/Chipset/CPUControl.cpp',
23 | 'src/Chipset/MMURegion.cpp',
24 | 'src/Chipset/CPULoadStore.cpp',
25 | ], dependencies: [
26 | dependency('threads'),
27 | dependency('SDL2'),
28 | dependency('SDL2_image'),
29 | dependency('lua53'),
30 | ])
31 |
--------------------------------------------------------------------------------
/emulator/src/Chipset/CPU.cpp:
--------------------------------------------------------------------------------
1 | #include "CPU.hpp"
2 |
3 | #include "../Emulator.hpp"
4 | #include "Chipset.hpp"
5 | #include "MMU.hpp"
6 | #include "../Logger.hpp"
7 |
8 | #include
9 |
10 | namespace casioemu
11 | {
12 | CPU::OpcodeSource CPU::opcode_sources[] = {
13 | // function, hints, main mask, operand {size, mask, shift} x2
14 | // * Arithmetic Instructions
15 | {&CPU::OP_ADD , H_WB , 0x8001, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
16 | {&CPU::OP_ADD , H_WB , 0x1000, {{1, 0x000F, 8}, {0, 0x00FF, 0}}},
17 | {&CPU::OP_ADD16 , H_WB , 0xF006, {{2, 0x000E, 8}, {2, 0x000E, 4}}},
18 | {&CPU::OP_ADD16 , H_WB | H_IE, 0xE080, {{2, 0x000E, 8}, {0, 0x007F, 0}}},
19 | {&CPU::OP_ADDC , H_WB , 0x8006, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
20 | {&CPU::OP_ADDC , H_WB , 0x6000, {{1, 0x000F, 8}, {0, 0x00FF, 0}}},
21 | {&CPU::OP_AND , H_WB , 0x8002, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
22 | {&CPU::OP_AND , H_WB , 0x2000, {{1, 0x000F, 8}, {0, 0x00FF, 0}}},
23 | {&CPU::OP_SUB , 0, 0x8007, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
24 | {&CPU::OP_SUB , 0, 0x7000, {{1, 0x000F, 8}, {0, 0x00FF, 0}}},
25 | {&CPU::OP_SUBC , 0, 0x8005, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
26 | {&CPU::OP_SUBC , 0, 0x5000, {{1, 0x000F, 8}, {0, 0x00FF, 0}}},
27 | {&CPU::OP_MOV16 , H_WB , 0xF005, {{2, 0x000E, 8}, {2, 0x000E, 4}}},
28 | {&CPU::OP_MOV16 , H_WB | H_IE, 0xE000, {{2, 0x000E, 8}, {0, 0x007F, 0}}},
29 | {&CPU::OP_MOV , H_WB , 0x8000, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
30 | {&CPU::OP_MOV , H_WB , 0x0000, {{1, 0x000F, 8}, {0, 0x00FF, 0}}},
31 | {&CPU::OP_OR , H_WB , 0x8003, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
32 | {&CPU::OP_OR , H_WB , 0x3000, {{1, 0x000F, 8}, {0, 0x00FF, 0}}},
33 | {&CPU::OP_XOR , H_WB , 0x8004, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
34 | {&CPU::OP_XOR , H_WB , 0x4000, {{1, 0x000F, 8}, {0, 0x00FF, 0}}},
35 | {&CPU::OP_CMP16 , 0, 0xF007, {{2, 0x000E, 8}, {2, 0x000E, 4}}},
36 | {&CPU::OP_SUB , H_WB , 0x8008, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
37 | {&CPU::OP_SUBC , H_WB , 0x8009, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
38 | // * Shift Instructions
39 | {&CPU::OP_SLL , H_WB , 0x800A, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
40 | {&CPU::OP_SLL , H_WB , 0x900A, {{1, 0x000F, 8}, {0, 0x0007, 4}}},
41 | {&CPU::OP_SLLC , H_WB , 0x800B, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
42 | {&CPU::OP_SLLC , H_WB , 0x900B, {{1, 0x000F, 8}, {0, 0x0007, 4}}},
43 | {&CPU::OP_SRA , H_WB , 0x800E, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
44 | {&CPU::OP_SRA , H_WB , 0x900E, {{1, 0x000F, 8}, {0, 0x0007, 4}}},
45 | {&CPU::OP_SRL , H_WB , 0x800C, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
46 | {&CPU::OP_SRL , H_WB , 0x900C, {{1, 0x000F, 8}, {0, 0x0007, 4}}},
47 | {&CPU::OP_SRLC , H_WB , 0x800D, {{1, 0x000F, 8}, {1, 0x000F, 4}}},
48 | {&CPU::OP_SRLC , H_WB , 0x900D, {{1, 0x000F, 8}, {0, 0x0007, 4}}},
49 | // * Load/Store Instructions
50 | {&CPU::OP_LS_EA , 2 << 8 , 0x9032, {{0, 0x000E, 8}, {0, 0, 0}}},
51 | {&CPU::OP_LS_EA , 2 << 8 | H_IA , 0x9052, {{0, 0x000E, 8}, {0, 0, 0}}},
52 | {&CPU::OP_LS_R , 2 << 8 , 0x9002, {{0, 0x000E, 8}, {2, 0x000E, 4}}},
53 | {&CPU::OP_LS_I_R , 2 << 8 | H_TI , 0xA008, {{0, 0x000E, 8}, {2, 0x000E, 4}}},
54 | {&CPU::OP_LS_BP , 2 << 8 | 0, 0xB000, {{0, 0x000E, 8}, {0, 0x003F, 0}}},
55 | {&CPU::OP_LS_FP , 2 << 8 | 0, 0xB040, {{0, 0x000E, 8}, {0, 0x003F, 0}}},
56 | {&CPU::OP_LS_I , 2 << 8 | H_TI , 0x9012, {{0, 0x000E, 8}, {0, 0, 0}}},
57 | {&CPU::OP_LS_EA , 1 << 8 , 0x9030, {{0, 0x000F, 8}, {0, 0, 0}}},
58 | {&CPU::OP_LS_EA , 1 << 8 | H_IA , 0x9050, {{0, 0x000F, 8}, {0, 0, 0}}},
59 | {&CPU::OP_LS_R , 1 << 8 , 0x9000, {{0, 0x000F, 8}, {2, 0x000E, 4}}},
60 | {&CPU::OP_LS_I_R , 1 << 8 | H_TI , 0x9008, {{0, 0x000F, 8}, {2, 0x000E, 4}}},
61 | {&CPU::OP_LS_BP , 1 << 8 | 0, 0xD000, {{0, 0x000F, 8}, {0, 0x003F, 0}}},
62 | {&CPU::OP_LS_FP , 1 << 8 | 0, 0xD040, {{0, 0x000F, 8}, {0, 0x003F, 0}}},
63 | {&CPU::OP_LS_I , 1 << 8 | H_TI , 0x9010, {{0, 0x000F, 8}, {0, 0, 0}}},
64 | {&CPU::OP_LS_EA , 4 << 8 , 0x9034, {{0, 0x000C, 8}, {0, 0, 0}}},
65 | {&CPU::OP_LS_EA , 4 << 8 | H_IA , 0x9054, {{0, 0x000C, 8}, {0, 0, 0}}},
66 | {&CPU::OP_LS_EA , 8 << 8 , 0x9036, {{0, 0x0008, 8}, {0, 0, 0}}},
67 | {&CPU::OP_LS_EA , 8 << 8 | H_IA , 0x9056, {{0, 0x0008, 8}, {0, 0, 0}}},
68 | {&CPU::OP_LS_EA , 2 << 8 | H_ST, 0x9033, {{0, 0x000E, 8}, {0, 0, 0}}},
69 | {&CPU::OP_LS_EA , 2 << 8 | H_IA | H_ST, 0x9053, {{0, 0x000E, 8}, {0, 0, 0}}},
70 | {&CPU::OP_LS_R , 2 << 8 | H_ST, 0x9003, {{0, 0x000E, 8}, {2, 0x000E, 4}}},
71 | {&CPU::OP_LS_I_R , 2 << 8 | H_TI | H_ST, 0xA009, {{0, 0x000E, 8}, {2, 0x000E, 4}}},
72 | {&CPU::OP_LS_BP , 2 << 8 | H_ST, 0xB080, {{0, 0x000E, 8}, {0, 0x003F, 0}}},
73 | {&CPU::OP_LS_FP , 2 << 8 | H_ST, 0xB0C0, {{0, 0x000E, 8}, {0, 0x003F, 0}}},
74 | {&CPU::OP_LS_I , 2 << 8 | H_TI | H_ST, 0x9013, {{0, 0x000E, 8}, {0, 0, 0}}},
75 | {&CPU::OP_LS_EA , 1 << 8 | H_ST, 0x9031, {{0, 0x000F, 8}, {0, 0, 0}}},
76 | {&CPU::OP_LS_EA , 1 << 8 | H_IA | H_ST, 0x9051, {{0, 0x000F, 8}, {0, 0, 0}}},
77 | {&CPU::OP_LS_R , 1 << 8 | H_ST, 0x9001, {{0, 0x000F, 8}, {2, 0x000E, 4}}},
78 | {&CPU::OP_LS_I_R , 1 << 8 | H_TI | H_ST, 0x9009, {{0, 0x000F, 8}, {2, 0x000E, 4}}},
79 | {&CPU::OP_LS_BP , 1 << 8 | H_ST, 0xD080, {{0, 0x000F, 8}, {0, 0x003F, 0}}},
80 | {&CPU::OP_LS_FP , 1 << 8 | H_ST, 0xD0C0, {{0, 0x000F, 8}, {0, 0x003F, 0}}},
81 | {&CPU::OP_LS_I , 1 << 8 | H_TI | H_ST, 0x9011, {{0, 0x000F, 8}, {0, 0, 0}}},
82 | {&CPU::OP_LS_EA , 4 << 8 | H_ST, 0x9035, {{0, 0x000C, 8}, {0, 0, 0}}},
83 | {&CPU::OP_LS_EA , 4 << 8 | H_IA | H_ST, 0x9055, {{0, 0x000C, 8}, {0, 0, 0}}},
84 | {&CPU::OP_LS_EA , 8 << 8 | H_ST, 0x9037, {{0, 0x0008, 8}, {0, 0, 0}}},
85 | {&CPU::OP_LS_EA , 8 << 8 | H_IA | H_ST, 0x9057, {{0, 0x0008, 8}, {0, 0, 0}}},
86 | // * Control Register Access Instructions
87 | {&CPU::OP_ADDSP , 0, 0xE100, {{0, 0x00FF, 0}, {0, 0, 0}}},
88 | {&CPU::OP_CTRL , 1 << 8, 0xA00F, {{0, 0, 0}, {1, 0x000F, 4}}},
89 | {&CPU::OP_CTRL , 2 << 8, 0xA00D, {{0, 0, 0}, {2, 0x000E, 8}}},
90 | {&CPU::OP_CTRL , 3 << 8, 0xA00C, {{0, 0, 0}, {1, 0x000F, 4}}},
91 | {&CPU::OP_CTRL , H_WB | 4 << 8, 0xA005, {{2, 0x000E, 8}, {0, 0, 0}}},
92 | {&CPU::OP_CTRL , H_WB | 5 << 8, 0xA01A, {{2, 0x000E, 8}, {0, 0, 0}}},
93 | {&CPU::OP_CTRL , 6 << 8, 0xA00B, {{0, 0, 0}, {1, 0x000F, 4}}},
94 | {&CPU::OP_CTRL , 7 << 8, 0xE900, {{0, 0, 0}, {0, 0x00FF, 0}}},
95 | {&CPU::OP_CTRL , H_WB | 8 << 8, 0xA007, {{1, 0x000F, 8}, {0, 0, 0}}},
96 | {&CPU::OP_CTRL , H_WB | 9 << 8, 0xA004, {{1, 0x000F, 8}, {0, 0, 0}}},
97 | {&CPU::OP_CTRL , H_WB | 10 << 8, 0xA003, {{1, 0x000F, 8}, {0, 0, 0}}},
98 | {&CPU::OP_CTRL , 11 << 8, 0xA10A, {{0, 0, 0}, {2, 0x000E, 4}}},
99 | // * PUSH/POP Instructions
100 | {&CPU::OP_PUSH , 0, 0xF05E, {{0, 0, 0}, {2, 0x000E, 8}}},
101 | {&CPU::OP_PUSH , 0, 0xF07E, {{0, 0, 0}, {8, 0x0008, 8}}},
102 | {&CPU::OP_PUSH , 0, 0xF04E, {{0, 0, 0}, {1, 0x000F, 8}}},
103 | {&CPU::OP_PUSH , 0, 0xF06E, {{0, 0, 0}, {4, 0x000C, 8}}},
104 | {&CPU::OP_PUSHL , 0, 0xF0CE, {{0, 0, 0}, {0, 0x000F, 8}}},
105 | {&CPU::OP_POP , H_WB , 0xF01E, {{2, 0x000E, 8}, {0, 0, 0}}},
106 | {&CPU::OP_POP , H_WB , 0xF03E, {{8, 0x0008, 8}, {0, 0, 0}}},
107 | {&CPU::OP_POP , H_WB , 0xF00E, {{1, 0x000F, 8}, {0, 0, 0}}},
108 | {&CPU::OP_POP , H_WB , 0xF02E, {{4, 0x000C, 8}, {0, 0, 0}}},
109 | {&CPU::OP_POPL , 0, 0xF08E, {{0, 0x000F, 8}, {0, 0, 0}}},
110 | // * Coprocessor Data Transfer Instructions
111 | {&CPU::OP_CR_R , 0, 0xA00E, {{0, 0x000F, 8}, {0, 0x000F, 4}}},
112 | {&CPU::OP_CR_EA , 2 << 8 | 0, 0xF02D, {{0, 0, 0}, {0, 0x000E, 8}}},
113 | {&CPU::OP_CR_EA , 2 << 8 | H_IA , 0xF03D, {{0, 0, 0}, {0, 0x000E, 8}}},
114 | {&CPU::OP_CR_EA , 1 << 8 | 0, 0xF00D, {{0, 0, 0}, {0, 0x000F, 8}}},
115 | {&CPU::OP_CR_EA , 1 << 8 | H_IA , 0xF01D, {{0, 0, 0}, {0, 0x000F, 8}}},
116 | {&CPU::OP_CR_EA , 4 << 8 | 0, 0xF04D, {{0, 0, 0}, {0, 0x000C, 8}}},
117 | {&CPU::OP_CR_EA , 4 << 8 | H_IA , 0xF05D, {{0, 0, 0}, {0, 0x000C, 8}}},
118 | {&CPU::OP_CR_EA , 8 << 8 | 0, 0xF06D, {{0, 0, 0}, {0, 0x0008, 8}}},
119 | {&CPU::OP_CR_EA , 8 << 8 | H_IA , 0xF07D, {{0, 0, 0}, {0, 0x0008, 8}}},
120 | {&CPU::OP_CR_R , H_ST, 0xA006, {{0, 0x000F, 8}, {0, 0x000F, 4}}},
121 | {&CPU::OP_CR_EA , 2 << 8 | H_ST, 0xF0AD, {{0, 0x000E, 8}, {0, 0, 0}}},
122 | {&CPU::OP_CR_EA , 2 << 8 | H_IA | H_ST, 0xF0BD, {{0, 0x000E, 8}, {0, 0, 0}}},
123 | {&CPU::OP_CR_EA , 1 << 8 | H_ST, 0xF08D, {{0, 0x000F, 8}, {0, 0, 0}}},
124 | {&CPU::OP_CR_EA , 1 << 8 | H_IA | H_ST, 0xF09D, {{0, 0x000F, 8}, {0, 0, 0}}},
125 | {&CPU::OP_CR_EA , 4 << 8 | H_ST, 0xF0CD, {{0, 0x000C, 8}, {0, 0, 0}}},
126 | {&CPU::OP_CR_EA , 4 << 8 | H_IA | H_ST, 0xF0DD, {{0, 0x000C, 8}, {0, 0, 0}}},
127 | {&CPU::OP_CR_EA , 8 << 8 | H_ST, 0xF0ED, {{0, 0x0008, 8}, {0, 0, 0}}},
128 | {&CPU::OP_CR_EA , 8 << 8 | H_IA | H_ST, 0xF0FD, {{0, 0x0008, 8}, {0, 0, 0}}},
129 | // * EA Register Data Transfer Instructions
130 | {&CPU::OP_LEA , 0, 0xF00A, {{0, 0, 0}, {2, 0x000E, 4}}},
131 | {&CPU::OP_LEA , H_TI , 0xF00B, {{0, 0, 0}, {2, 0x000E, 4}}},
132 | {&CPU::OP_LEA , H_TI , 0xF00C, {{0, 0, 0}, {0, 0, 0}}},
133 | // * ALU Instructions
134 | {&CPU::OP_DAA , H_WB , 0x801F, {{1, 0x000F, 8}, {0, 0, 0}}},
135 | {&CPU::OP_DAS , H_WB , 0x803F, {{1, 0x000F, 8}, {0, 0, 0}}},
136 | {&CPU::OP_NEG , H_WB , 0x805F, {{1, 0x000F, 8}, {0, 0, 0}}},
137 | // * Bit Access Instructions
138 | {&CPU::OP_BITMOD , 0, 0xA000, {{0, 0x000F, 8}, {0, 0x0007, 4}}},
139 | {&CPU::OP_BITMOD , H_TI , 0xA080, {{0, 0, 0}, {0, 0x0007, 4}}},
140 | {&CPU::OP_BITMOD , 0, 0xA002, {{0, 0x000F, 8}, {0, 0x0007, 4}}},
141 | {&CPU::OP_BITMOD , H_TI , 0xA082, {{0, 0, 0}, {0, 0x0007, 4}}},
142 | {&CPU::OP_BITMOD , 0, 0xA001, {{0, 0x000F, 8}, {0, 0x0007, 4}}},
143 | {&CPU::OP_BITMOD , H_TI , 0xA081, {{0, 0, 0}, {0, 0x0007, 4}}},
144 | // * PSW Access Instructions
145 | {&CPU::OP_PSW_OR , 0, 0xED08, {{0, 0, 0}, {0, 0, 0}}},
146 | {&CPU::OP_PSW_AND , 0, 0xEBF7, {{0, 0, 0}, {0, 0, 0}}},
147 | {&CPU::OP_PSW_OR , 0, 0xED80, {{0, 0, 0}, {0, 0, 0}}},
148 | {&CPU::OP_PSW_AND , 0, 0xEB7F, {{0, 0, 0}, {0, 0, 0}}},
149 | {&CPU::OP_CPLC , 0, 0xFECF, {{0, 0, 0}, {0, 0, 0}}},
150 | // * Conditional Relative Branch Instructions
151 | {&CPU::OP_BC , 0, 0xC000, {{0, 0x00FF, 0}, {0, 0, 0}}},
152 | {&CPU::OP_BC , 0, 0xC100, {{0, 0x00FF, 0}, {0, 0, 0}}},
153 | {&CPU::OP_BC , 0, 0xC200, {{0, 0x00FF, 0}, {0, 0, 0}}},
154 | {&CPU::OP_BC , 0, 0xC300, {{0, 0x00FF, 0}, {0, 0, 0}}},
155 | {&CPU::OP_BC , 0, 0xC400, {{0, 0x00FF, 0}, {0, 0, 0}}},
156 | {&CPU::OP_BC , 0, 0xC500, {{0, 0x00FF, 0}, {0, 0, 0}}},
157 | {&CPU::OP_BC , 0, 0xC600, {{0, 0x00FF, 0}, {0, 0, 0}}},
158 | {&CPU::OP_BC , 0, 0xC700, {{0, 0x00FF, 0}, {0, 0, 0}}},
159 | {&CPU::OP_BC , 0, 0xC800, {{0, 0x00FF, 0}, {0, 0, 0}}},
160 | {&CPU::OP_BC , 0, 0xC900, {{0, 0x00FF, 0}, {0, 0, 0}}},
161 | {&CPU::OP_BC , 0, 0xCA00, {{0, 0x00FF, 0}, {0, 0, 0}}},
162 | {&CPU::OP_BC , 0, 0xCB00, {{0, 0x00FF, 0}, {0, 0, 0}}},
163 | {&CPU::OP_BC , 0, 0xCC00, {{0, 0x00FF, 0}, {0, 0, 0}}},
164 | {&CPU::OP_BC , 0, 0xCD00, {{0, 0x00FF, 0}, {0, 0, 0}}},
165 | {&CPU::OP_BC , 0, 0xCE00, {{0, 0x00FF, 0}, {0, 0, 0}}},
166 | // * Sign Extension Instruction
167 | {&CPU::OP_EXTBW , 0, 0x810F, {{0, 0, 0}, {0, 0, 0}}},
168 | {&CPU::OP_EXTBW , 0, 0x832F, {{0, 0, 0}, {0, 0, 0}}},
169 | {&CPU::OP_EXTBW , 0, 0x854F, {{0, 0, 0}, {0, 0, 0}}},
170 | {&CPU::OP_EXTBW , 0, 0x876F, {{0, 0, 0}, {0, 0, 0}}},
171 | {&CPU::OP_EXTBW , 0, 0x898F, {{0, 0, 0}, {0, 0, 0}}},
172 | {&CPU::OP_EXTBW , 0, 0x8BAF, {{0, 0, 0}, {0, 0, 0}}},
173 | {&CPU::OP_EXTBW , 0, 0x8DCF, {{0, 0, 0}, {0, 0, 0}}},
174 | {&CPU::OP_EXTBW , 0, 0x8FEF, {{0, 0, 0}, {0, 0, 0}}},
175 | // * Software Interrupt Instructions
176 | {&CPU::OP_SWI , 0, 0xE500, {{0, 0x003F, 0}, {0, 0, 0}}},
177 | {&CPU::OP_BRK , 0, 0xFFFF, {{0, 0, 0}, {0, 0, 0}}},
178 | // * Branch Instructions
179 | {&CPU::OP_B , H_TI , 0xF000, {{0, 0, 0}, {0, 0x000F, 8}}},
180 | {&CPU::OP_B , 0, 0xF002, {{0, 0, 0}, {2, 0x000E, 4}}},
181 | {&CPU::OP_BL , H_TI , 0xF001, {{0, 0, 0}, {0, 0x000F, 8}}},
182 | {&CPU::OP_BL , 0, 0xF003, {{0, 0, 0}, {2, 0x000E, 4}}},
183 | // * Multiplication and Division Instructions
184 | {&CPU::OP_MUL , H_WB , 0xF004, {{2, 0x000E, 8}, {1, 0x000F, 4}}},
185 | {&CPU::OP_DIV , H_WB , 0xF009, {{2, 0x000E, 8}, {1, 0x000F, 4}}},
186 | // * Miscellaneous Instructions
187 | {&CPU::OP_INC_EA , 0, 0xFE2F, {{0, 0, 0}, {0, 0, 0}}},
188 | {&CPU::OP_DEC_EA , 0, 0xFE3F, {{0, 0, 0}, {0, 0, 0}}},
189 | {&CPU::OP_RT , 0, 0xFE1F, {{0, 0, 0}, {0, 0, 0}}},
190 | {&CPU::OP_RTI , 0, 0xFE0F, {{0, 0, 0}, {0, 0, 0}}},
191 | {&CPU::OP_NOP , 0, 0xFE8F, {{0, 0, 0}, {0, 0, 0}}},
192 | {&CPU::OP_DSR , H_DS , 0xFE9F, {{0, 0, 0}, {0, 0, 0}}},
193 | {&CPU::OP_DSR , H_DS | H_DW, 0xE300, {{0, 0x00FF, 0}, {0, 0, 0}}},
194 | {&CPU::OP_DSR , H_DS | H_DW, 0x900F, {{1, 0x000F, 4}, {0, 0, 0}}}
195 | };
196 |
197 | CPU::RegisterRecord CPU::register_record_sources[] = {
198 | { "r", 16, 0, nullptr, (RegisterStubArrayPointer)&CPU::reg_r},
199 | { "cr", 16, 0, nullptr, (RegisterStubArrayPointer)&CPU::reg_cr},
200 | { "pc", 1, 0, (RegisterStubPointer)&CPU::reg_pc, nullptr},
201 | { "csr", 1, 0, (RegisterStubPointer)&CPU::reg_csr, nullptr},
202 | { "lr", 1, 0, nullptr, (RegisterStubArrayPointer)&CPU::reg_elr},
203 | { "elr1", 1, 1, nullptr, (RegisterStubArrayPointer)&CPU::reg_elr},
204 | { "elr2", 1, 2, nullptr, (RegisterStubArrayPointer)&CPU::reg_elr},
205 | { "elr3", 1, 3, nullptr, (RegisterStubArrayPointer)&CPU::reg_elr},
206 | { "lcsr", 1, 0, nullptr, (RegisterStubArrayPointer)&CPU::reg_ecsr},
207 | {"ecsr1", 1, 1, nullptr, (RegisterStubArrayPointer)&CPU::reg_ecsr},
208 | {"ecsr2", 1, 2, nullptr, (RegisterStubArrayPointer)&CPU::reg_ecsr},
209 | {"ecsr3", 1, 3, nullptr, (RegisterStubArrayPointer)&CPU::reg_ecsr},
210 | { "psw", 1, 0, nullptr, (RegisterStubArrayPointer)&CPU::reg_epsw},
211 | {"epsw1", 1, 1, nullptr, (RegisterStubArrayPointer)&CPU::reg_epsw},
212 | {"epsw2", 1, 2, nullptr, (RegisterStubArrayPointer)&CPU::reg_epsw},
213 | {"epsw3", 1, 3, nullptr, (RegisterStubArrayPointer)&CPU::reg_epsw},
214 | { "sp", 1, 0, (RegisterStubPointer)&CPU::reg_sp, nullptr},
215 | { "ea", 1, 0, (RegisterStubPointer)&CPU::reg_ea, nullptr},
216 | { "dsr", 1, 0, (RegisterStubPointer)&CPU::reg_dsr, nullptr}
217 | };
218 |
219 | void CPU::OP_NOP()
220 | {
221 | }
222 |
223 | void CPU::OP_DSR()
224 | {
225 | if (impl_hint & H_DW)
226 | impl_last_dsr = impl_operands[0].value;
227 |
228 | reg_dsr = impl_last_dsr;
229 | }
230 |
231 | CPU::CPU(Emulator &_emulator) : emulator(_emulator), reg_lr(reg_elr[0]), reg_lcsr(reg_ecsr[0]), reg_psw(reg_epsw[0])
232 | {
233 | opcode_dispatch = new OpcodeSource *[0x10000];
234 | for (size_t ix = 0; ix != 0x10000; ++ix)
235 | opcode_dispatch[ix] = nullptr;
236 | }
237 |
238 | CPU::~CPU()
239 | {
240 | delete[] opcode_dispatch;
241 | }
242 |
243 | void CPU::SetupInternals()
244 | {
245 | SetupOpcodeDispatch();
246 | SetupRegisterProxies();
247 |
248 | impl_csr_mask = emulator.GetModelInfo("csr_mask");
249 | }
250 |
251 | void CPU::SetupOpcodeDispatch()
252 | {
253 | uint16_t *permutation_buffer = new uint16_t[0x10000];
254 | for (size_t ix = 0; ix != sizeof(opcode_sources) / sizeof(opcode_sources[0]); ++ix)
255 | {
256 | OpcodeSource &handler_stub = opcode_sources[ix];
257 |
258 | uint16_t varying_bits = 0;
259 | for (size_t ox = 0; ox != sizeof(impl_operands) / sizeof(impl_operands[0]); ++ox)
260 | varying_bits |= handler_stub.operands[ox].mask << handler_stub.operands[ox].shift;
261 |
262 | size_t permutation_count = 1;
263 | permutation_buffer[0] = handler_stub.opcode;
264 | for (uint16_t checkbit = 0x8000; checkbit; checkbit >>= 1)
265 | {
266 | if (varying_bits & checkbit)
267 | {
268 | for (size_t px = 0; px != permutation_count; ++px)
269 | permutation_buffer[px + permutation_count] = permutation_buffer[px] | checkbit;
270 | permutation_count <<= 1;
271 | }
272 | }
273 |
274 | for (size_t px = 0; px != permutation_count; ++px)
275 | {
276 | if (opcode_dispatch[permutation_buffer[px]])
277 | PANIC("clashing opcode %04X\n", permutation_buffer[px]);
278 | opcode_dispatch[permutation_buffer[px]] = &handler_stub;
279 | }
280 | }
281 | delete[] permutation_buffer;
282 | }
283 |
284 | void CPU::SetupRegisterProxies()
285 | {
286 | for (size_t ix = 0; ix != sizeof(register_record_sources) / sizeof(register_record_sources[0]); ++ix)
287 | {
288 | RegisterRecord &record = register_record_sources[ix];
289 |
290 | if (record.stub)
291 | {
292 | RegisterStub *register_stub = &(this->*record.stub);
293 | register_stub->name = record.name;
294 | register_proxies[record.name] = register_stub;
295 | }
296 |
297 | if (record.stub_array)
298 | {
299 | if (record.array_size == 1)
300 | {
301 | RegisterStub *register_stub = &(this->*record.stub_array)[record.array_base];
302 | register_stub->name = record.name;
303 | register_proxies[record.name] = register_stub;
304 | }
305 | else
306 | {
307 | for (size_t rx = 0; rx != record.array_size; ++rx)
308 | {
309 | std::stringstream ss;
310 | ss << record.name << rx;
311 | RegisterStub *register_stub = &(this->*record.stub_array)[rx];
312 | register_stub->name = ss.str();
313 | register_proxies[ss.str()] = register_stub;
314 | }
315 | }
316 | }
317 | }
318 |
319 | *(CPU **)lua_newuserdata(emulator.lua_state, sizeof(CPU *)) = this;
320 | lua_newtable(emulator.lua_state);
321 | lua_pushcfunction(emulator.lua_state, [](lua_State *lua_state) {
322 | CPU *cpu = *(CPU **)lua_topointer(lua_state, 1);
323 | auto it = cpu->register_proxies.find(lua_tostring(lua_state, 2));
324 | if (it == cpu->register_proxies.end())
325 | return 0;
326 | RegisterStub *reg_stub = it->second;
327 | if (reg_stub->type_size == 1)
328 | lua_pushinteger(lua_state, (uint8_t)reg_stub->raw);
329 | else
330 | lua_pushinteger(lua_state, (uint16_t)reg_stub->raw);
331 | return 1;
332 | });
333 | lua_setfield(emulator.lua_state, -2, "__index");
334 | lua_pushcfunction(emulator.lua_state, [](lua_State *lua_state) {
335 | CPU *cpu = *(CPU **)lua_topointer(lua_state, 1);
336 | auto it = cpu->register_proxies.find(lua_tostring(lua_state, 2));
337 | if (it == cpu->register_proxies.end())
338 | return 0;
339 | RegisterStub *reg_stub = it->second;
340 | if (reg_stub->type_size == 1)
341 | reg_stub->raw = (uint8_t)lua_tointeger(lua_state, 3);
342 | else
343 | reg_stub->raw = (uint16_t)lua_tointeger(lua_state, 3);
344 | return 0;
345 | });
346 | lua_setfield(emulator.lua_state, -2, "__newindex");
347 | lua_setmetatable(emulator.lua_state, -2);
348 | lua_setglobal(emulator.lua_state, "cpu");
349 | }
350 |
351 | uint16_t CPU::Fetch()
352 | {
353 | if (reg_csr.raw & ~impl_csr_mask)
354 | {
355 | logger::Info("warning: CSR masked bits set\n");
356 | reg_csr.raw &= impl_csr_mask;
357 | }
358 | if (reg_pc.raw & 1)
359 | {
360 | logger::Info("warning: PC LSB set\n");
361 | reg_pc.raw &= ~1;
362 | }
363 | uint16_t opcode = emulator.chipset.mmu.ReadCode((reg_csr.raw << 16) | reg_pc.raw);
364 | reg_pc.raw = (uint16_t)(reg_pc.raw + 2);
365 | return opcode;
366 | }
367 |
368 | void CPU::Next()
369 | {
370 | /**
371 | * `reg_dsr` only affects the current instruction. The old DSR is stored in
372 | * `impl_last_dsr` and is recalled every time a DSR instruction is encountered
373 | * that activates DSR addressing without actually changing DSR.
374 | */
375 | reg_dsr = 0;
376 |
377 | for (auto &proxy : register_proxies)
378 | {
379 | proxy.second->read = false;
380 | proxy.second->written = false;
381 | }
382 |
383 | while (1)
384 | {
385 | impl_opcode = Fetch();
386 | OpcodeSource *handler = opcode_dispatch[impl_opcode];
387 |
388 | if (!handler)
389 | PANIC("unrecognized instruction %04X at %06zX\n", impl_opcode, (((size_t)reg_csr.raw) << 16) | (reg_pc.raw - 2));
390 |
391 | impl_long_imm = 0;
392 | if (handler->hint & H_TI)
393 | impl_long_imm = Fetch();
394 |
395 | for (size_t ix = 0; ix != sizeof(impl_operands) / sizeof(impl_operands[0]); ++ix)
396 | {
397 | impl_operands[ix].value = (impl_opcode >> handler->operands[ix].shift) & handler->operands[ix].mask;
398 | impl_operands[ix].register_index = impl_operands[ix].value;
399 | impl_operands[ix].register_size = handler->operands[ix].register_size;
400 |
401 | if (impl_operands[ix].register_size)
402 | {
403 | impl_operands[ix].value = 0;
404 | for (size_t bx = 0; bx != impl_operands[ix].register_size; ++bx)
405 | impl_operands[ix].value |= (uint64_t)(reg_r[impl_operands[ix].register_index + bx]) << (bx * 8);
406 | }
407 | }
408 | impl_hint = handler->hint;
409 |
410 | impl_flags_changed = 0;
411 | impl_flags_in = reg_psw;
412 | /**
413 | * Yes, Z is always set to 1. While `impl_flags_changed` may not have
414 | * PSW_Z set, `impl_flags_out` does as most of the time Z is calculated
415 | * by one or more calls to `ZSCheck`. `ZSCheck` only changes Z if the
416 | * value it checks is non-zero, otherwise it leaves it alone.
417 | */
418 | impl_flags_out = PSW_Z;
419 | (this->*(handler->handler_function))();
420 | reg_psw &= ~impl_flags_changed;
421 | reg_psw |= impl_flags_out & impl_flags_changed;
422 |
423 | if (handler->hint & H_WB && impl_operands[0].register_size)
424 | for (size_t bx = 0; bx != impl_operands[0].register_size; ++bx)
425 | reg_r[impl_operands[0].register_index + bx] = (uint8_t)(impl_operands[0].value >> (bx * 8));
426 |
427 | if (!(handler->hint & H_DS))
428 | break;
429 | }
430 | }
431 |
432 | void CPU::SetMemoryModel(MemoryModel _memory_model)
433 | {
434 | memory_model = _memory_model;
435 | }
436 |
437 | void CPU::Reset()
438 | {
439 | reg_sp = emulator.chipset.mmu.ReadCode(0);
440 | reg_dsr = 0;
441 | reg_psw = 0;
442 | }
443 |
444 | void CPU::Raise(size_t exception_level, size_t index)
445 | {
446 | if (exception_level == 1)
447 | reg_psw.raw &= ~PSW_MIE;
448 | reg_psw.raw = (reg_psw.raw & ~PSW_ELEVEL) | exception_level;
449 |
450 | reg_elr[exception_level].raw = reg_pc.raw;
451 | reg_ecsr[exception_level].raw = reg_csr.raw;
452 |
453 | reg_csr.raw = 0;
454 | reg_pc.raw = emulator.chipset.mmu.ReadCode(index * 2);
455 | }
456 |
457 | size_t CPU::GetExceptionLevel()
458 | {
459 | return reg_psw.raw & PSW_ELEVEL;
460 | }
461 |
462 | bool CPU::GetMasterInterruptEnable()
463 | {
464 | return reg_psw & PSW_MIE;
465 | }
466 | }
467 |
468 |
--------------------------------------------------------------------------------
/emulator/src/Chipset/CPU.hpp:
--------------------------------------------------------------------------------
1 | #pragma once
2 | #include "../Config.hpp"
3 |
4 | #include "../Logger.hpp"
5 |
6 | #include
7 | #include
8 | #include