└── README.md /README.md: -------------------------------------------------------------------------------- 1 | # EDA-info 2 | the awesome work, project and lab of EDA (Electronic Design Automation). continue update... 3 | (Because of personal reasons, we will not continue update...) 4 | 5 | - Main EDA lab and open-source project： 6 | - [Bei Yu, The Chinese University of Hong Kong](http://www.cse.cuhk.edu.hk/~byu/) 7 | - [Evangeline F.Y. Young, The Chinese University of Hong Kong](https://www.cse.cuhk.edu.hk/~fyyoung/) 8 | - [Yibo Lin, The Peking Unbiversity](https://yibolin.com/) 9 | - [The UT Design Automation Laboratory (UTDA)](https://www.cerc.utexas.edu/utda/) 10 | - [iEDA](https://github.com/OSCC-Project/iEDA) 11 | - [Xuan Zeng, The Fudan Unbiversity](https://ieeexplore.ieee.org/author/37272246100?history=no&highlight=true&returnType=SEARCH&sortType=newest&searchWithin=%22Author%20Ids%22:37272246100&returnFacets=ALL) 12 | 13 | - Overview: 14 | - [Machine learning and algorithms: Let us team up for EDA](https://ieeexplore.ieee.org/abstract/document/9682429/) 15 | - Placement and Routing 16 | - Routing: 17 | - [FastRoute](https://github.com/The-OpenROAD-Project-Attic/FastRoute) 18 | : A Step to Integrate Global Routing into Placement 19 | - [NTHU](https://github.com/luckyrantanplan/nthu-route) 20 | : A New Global Router for Modern Designs 21 | - [SAGERoute](https://github.com/PKU-IDEA/SAGERoute/tree/main) 22 | : Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility 23 | - [Dr.CU](https://github.com/cuhk-eda/dr-cu) 24 | : Dr. CU is a VLSI detailed routing tool 25 | - [Dr.GR](https://github.com/cuhk-eda/cu-gr) 26 | : Dr. CU is a VLSI global routing tool 27 | - [Align](https://github.com/ALIGN-analoglayout/AnalogDetailedRouter) 28 | : analog detailed router 29 | - [Electromigration- and Parasitic-Aware ILP-Based Analog Router](https://ieeexplore.ieee.org/abstract/document/8378047/) 30 | : analog global router 31 | - [Efficient ILP-Based Variant-Grid Analog Router](https://ieeexplore.ieee.org/abstract/document/7527478/) 32 | : analog global router 33 | - Reinforcement Learning Guided Detailed Routing for Custom Circuits 34 | - [Pathfinding Model and Lagrangian-Based Global Routing](https://doi.org/10.1109/DAC56929.2023.10247969) 35 | - [PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning](https://doi.org/10.1109/TCAD.2022.3168259) 36 | - [GAMER: GPU-Accelerated Maze Routing](https://doi.org/10.1109/TCAD.2022.3184281) 37 | - [COALA: Concurrently Assigning Wire Segments to Layers for 2-D Global Routing](https://doi.org/10.1109/TCAD.2022.3178353) 38 | - [Incremental 3-D Global Routing Considering Cell Movement and Complex Routing Constraints](https://doi.org/10.1109/TCAD.2022.3210493) 39 | - placement: 40 | - [Xplace](https://github.com/cuhk-eda/Xplace) 41 | : An Extremely Fast and Extensible Global Placement Framework 42 | - [RePlace](https://github.com/The-OpenROAD-Project/RePlAce) 43 | : Advancing Solution Quality and Routability Validation in Global Placement 44 | - [DreamPlace](https://github.com/limbo018/DREAMPlace) 45 | : Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement 46 | - [ePlace](https://github.com/ApeachM/ePlacePractice) 47 | : Electrostatics based Placement using Fast Fourier Transform and Nesterov’s Method 48 | - [MacroPlacement](https://github.com/TILOS-AI-Institute/MacroPlacement) 49 | : Assessment of Reinforcement Learning for Macro Placement 50 | - [MaskPlace](https://github.com/laiyao1/maskplace) 51 | : Fast Chip Placement via Reinforced Visual Representation Learning 52 | - [RLPlace: Deep RL Guided Heuristics for Detailed Placement Optimization](https://doi.org/10.23919/DATE54114.2022.9774684) 53 | - [Parallel Global Placement on CPU via Parallel Reduction](https://ieeexplore.ieee.org/document/8983444/) 54 | - analog layout generation 55 | - [Laygo](https://laygo2.github.io/) 56 | : A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies 57 | - [BAG](https://github.com/sdaudlin/BAG_framework) 58 | : A Process-Portable Framework for Generator-based AMS Circuit Design 59 | - [MAGICAL](https://github.com/magical-eda/MAGICAL) 60 | : Machine Generated Analog IC Layout 61 | - [ALIGN](https://github.com/ALIGN-analoglayout/ALIGN-public) 62 | : Analog Layout, Intelligently Generated from Netlists 63 | - [Symmetry Annotation Extraction](https://doi.org/10.1145/3394885.3431545) 64 | : Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks 65 | - [Interactive Analog Layout Editing With Instant Placement and Routing Legalization](https://ieeexplore.ieee.org/document/9826897) 66 | 67 | 68 | - Analog Circuit Design Optimization 69 | - [Multi-objective Bayesian Optimization for Analog/RF Circuit Synthesis](https://dl.acm.org/doi/abs/10.1145/3195970.3196078) 70 | - [Automated Design of Analog Circuits Using Reinforcement Learning](https://ieeexplore.ieee.org/abstract/document/9576505) 71 | - [code](https://github.com/ksettaluri6/AutoCkt) 72 | - [DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks](https://ieeexplore.ieee.org/abstract/document/9586139) 73 | - [MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors](https://ieeexplore.ieee.org/abstract/document/10136894) 74 | - [DC-Model: A New Method for Assisting the Analog Circuit Optimization](https://ieeexplore.ieee.org/abstract/document/10129366) 75 | - [An efficient batch-constrained bayesian optimization approach for analog circuit synthesis via multiobjective acquisition ensemble](https://ieeexplore.ieee.org/abstract/document/9336041) 76 | - [Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design](http://proceedings.mlr.press/v80/lyu18a.html?ref=https://githubhelp.com) 77 | - [code](https://github.com/Alaya-in-Matrix/MACE) 78 | - [Geometric programming for circuit optimization](https://dl.acm.org/doi/abs/10.1145/1055137.1055148) 79 | - [A tutorial on geometric programming](https://link.springer.com/article/10.1007/s11081-007-9001-7) 80 | - [Late Breaking Results: Analog Circuit Generator based on Deep Neural Network enhanced Combinatorial Optimization](https://dl.acm.org/doi/abs/10.1145/3316781.3322468) 81 | - [Learning to Design Circuits](https://arxiv.org/abs/1812.02734) 82 | - [GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning](https://ieeexplore.ieee.org/abstract/document/9218757/) 83 | - [Closing the Design Loop: Bayesian Optimization AssistedHierarchical Analog Layout Synthesis](https://ieeexplore.ieee.org/abstract/document/9218621/) 84 | - [Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization](https://ieeexplore.ieee.org/abstract/document/9474253) 85 | - [Joint optimization of sizing and layout for AMS designs: Challenges and opportunities](https://dl.acm.org/doi/abs/10.1145/3569052.3578929) 86 | - [Analog circuit sizing based on Evolutionary Algorithms and deep learning](https://www.sciencedirect.com/science/article/pii/S0957417423019826) 87 | - [Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for Sizing](https://ieeexplore.ieee.org/document/10247739) 88 | - [Automated Design of Complex Analog Circuits with Multiagent based Reinforcement Learning](https://ieeexplore.ieee.org/document/10247909) 89 | - [Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards](https://dl.acm.org/doi/10.1145/3551901.3556474) 90 | - [code](https://github.com/electronics-and-drives/MLCAD22) 91 | - [LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces](https://dl.acm.org/doi/10.1145/3551901.3556496) 92 | - [RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL](https://dl.acm.org/doi/10.1145/3551901.3556487) 93 | - [Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits](https://ieeexplore.ieee.org/document/9045614) 94 | - [Bayesian optimization approach for analog circuit synthesis using neural network](https://ieeexplore.ieee.org/abstract/document/8714788) 95 | - [A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench](https://ieeexplore.ieee.org/document/9712590/) 96 | - [High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure](https://ieeexplore.ieee.org/document/9620425) 97 | - [A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization](https://ieeexplore.ieee.org/document/9371542) 98 | - [An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis](https://ieeexplore.ieee.org/document/9218592) 99 | - [A Mixed-Variable Bayesian Optimization Approach for Analog Circuit Synthesis](https://ieeexplore.ieee.org/document/9181162) 100 | - [APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors using DNN Learning](https://dl.acm.org/doi/abs/10.1145/3566097.3567880) 101 | 102 | - Layout Pattern Generation 103 | - [DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder](https://dl.acm.org/doi/abs/10.1145/3316781.3317795) 104 | - [Layout Pattern Generation and Legalization with Generative Learning Models](https://dl.acm.org/doi/abs/10.1145/3400302.3415607) 105 | - [LayouTransformer: Generating Layout Patterns with Transformer via Sequential Pattern Modeling](https://dl.acm.org/doi/abs/10.1145/3508352.3549350) 106 | - [DiffPattern : Layout Pattern Generation via Discrete Diffusion](https://arxiv.org/abs/2303.13060) 107 | - [WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout](https://dl.acm.org/doi/10.1145/3316781.3317930) 108 | 109 | - Pattern Layout Hotspot Dectection 110 | - [Efficient Hotspot Detection via Graph Neural Network](https://ieeexplore.ieee.org/document/9774579) 111 | - [Efficient Layout Hotspot Detection via Neural Architecture Search](https://dl.acm.org/doi/10.1145/3517130) 112 | - [Hotspot Detection via Attention-Based Deep Layout Metric Learning](https://doi.org/10.1145/3517130) 113 | - [Faster Region-based Hotspot Detection](https://doi.org/10.1145/3316781.3317824) 114 | - [code](https://github.com/Lanselott/R-HSD) 115 | - [Efficient Layout Hotspot Detection via Binarized Residual Neural Network](https://doi.org/10.1145/3316781.3317811) 116 | - [Hotspot Detection using Squish-Net](https://doi.org/10.1117/12.2515172) 117 | - [Detecting multi-layer layout hotspots with adaptive squish patterns](https://dl.acm.org/doi/10.1145/3287624.3288747) 118 | - [Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning](https://ieeexplore.ieee.org/document/8360060/) 119 | - [code](https://github.com/phdyang007/dlhsd) 120 | - [Lithography Hotspot Detection: From Shallow To Deep Learning](https://doi.org/10.1109/SOCC.2017.8226047) 121 | - [Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning](https://dl.acm.org/doi/10.1145/3061639.3062270) 122 | - [Bilinear Lithography Hotspot Detection](https://dl.acm.org/doi/10.1145/3036669.3036673) 123 | - [ADAPT: An Adaptive Machine Learning Framework with Application to Lithography Hotspot Detection](https://ieeexplore.ieee.org/abstract/document/9531210/) 124 | - [Many-Layer Hotspot Detection by Layer-Attentioned Visual Question Answering](https://doi.org/10.23919/DATE54114.2022.9774622) 125 | - [Efficient Layout Hotspot Detection via Binarized Residual Neural Network](https://ieeexplore.ieee.org/document/8806978/) 126 | 127 | 128 | 129 | --------------------------------------------------------------------------------