├── cores └── .empty ├── integrated_cores └── .empty ├── integration_files └── SweRV_EH1 │ ├── cover.cfg │ ├── directed_tests │ ├── c │ │ ├── cmark_dccm.c │ │ ├── cmark_dccm.ld │ │ ├── cmark_iccm.ld │ │ ├── c_sample.c │ │ └── defines.h │ └── asm │ │ ├── hello_world_dccm.s │ │ ├── hello_world_dccm.ld │ │ ├── hello_world2.s │ │ ├── hello_world.s │ │ └── defines.h │ ├── riscv_dv_extension │ ├── link.ld │ ├── linker_scripts │ │ ├── cmark.ld │ │ ├── cmark_dccm.ld │ │ ├── hello_world_dccm.ld │ │ ├── link_comp.ld │ │ ├── cmark_iccm.ld │ │ ├── riscv_rand_instr_test.ld │ │ ├── riscv_rand_jump_test.ld │ │ └── riscv_load_store_instr_dccm_test.ld │ ├── nb_postfix.py │ ├── testlist.yaml │ ├── riscv_core_setting.sv │ └── core_log_to_trace_csv.py │ ├── testbench_veri.f │ ├── snapshots │ └── default │ │ ├── pd_defines.vh │ │ ├── pic_map_auto.h │ │ ├── defines.h │ │ ├── common_defines.vh │ │ ├── common_defines_verilator.vh │ │ └── pic_ctrl_verilator_unroll.sv │ ├── flist_verilator.f │ ├── riscv-target │ ├── testlists │ │ ├── testlist_Zifencei.yaml │ │ ├── testlist_M.yaml │ │ ├── testlist_privilege.yaml │ │ ├── testlist_C.yaml │ │ └── testlist_I.yaml │ └── model_test.h │ ├── SweRV_EH1_flist.f │ ├── waves.tcl │ ├── yaml │ └── rtl_simulation.yaml │ ├── google_riscv_dv │ ├── riscv_instr_base_test.py │ └── scripts │ │ └── spike_log_to_trace_csv.py │ └── testbench │ ├── test_tb_top.cpp │ ├── ahb_sif.sv │ ├── tracer_pkg.sv │ └── pkg.sv ├── docs ├── img │ ├── csv.png │ ├── fcov.png │ ├── spike.png │ ├── post_sim.png │ ├── thumbnail.png │ ├── trace_log.png │ ├── Post_compare.jpg │ ├── Post_compare.png │ ├── google_rv_dv.png │ ├── youtube_thumb.png │ ├── Google_RISCV_DV_Flow_Random.png │ └── Google_RISCV_DV_Flow_Directed.png ├── jumps_branches_loops.md ├── nonblock_load_issue.md ├── functional_coverage.md ├── spike.md ├── exceptions_interrupts.md ├── post_compare.md ├── load_store_dccm.md ├── SweRV_Tracer.md ├── document_csr_test.md └── SweRV_setup_with_RVDV.md ├── Contributors ├── .gitignore ├── scripts ├── toolchain_paths.sh └── core_integrate.sh ├── README.md └── LICENSE /cores/.empty: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /integrated_cores/.empty: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/cover.cfg: -------------------------------------------------------------------------------- 1 | +tree tb_top.rvtop.swerv 2 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/directed_tests/c/cmark_dccm.c: -------------------------------------------------------------------------------- 1 | cmark.c -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/directed_tests/asm/hello_world_dccm.s: -------------------------------------------------------------------------------- 1 | hello_world.s -------------------------------------------------------------------------------- /docs/img/csv.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Lampro-Mellon/LM-RISCV-DV/HEAD/docs/img/csv.png -------------------------------------------------------------------------------- /docs/img/fcov.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Lampro-Mellon/LM-RISCV-DV/HEAD/docs/img/fcov.png -------------------------------------------------------------------------------- /docs/img/spike.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Lampro-Mellon/LM-RISCV-DV/HEAD/docs/img/spike.png -------------------------------------------------------------------------------- /Contributors: -------------------------------------------------------------------------------- 1 | Haroon Shafique 2 | Najeeb Afzal 3 | Behzad Mehmood 4 | Nadeem Yaseen 5 | Amna Fayyaz 6 | -------------------------------------------------------------------------------- /docs/img/post_sim.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Lampro-Mellon/LM-RISCV-DV/HEAD/docs/img/post_sim.png -------------------------------------------------------------------------------- /docs/img/thumbnail.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Lampro-Mellon/LM-RISCV-DV/HEAD/docs/img/thumbnail.png -------------------------------------------------------------------------------- /docs/img/trace_log.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Lampro-Mellon/LM-RISCV-DV/HEAD/docs/img/trace_log.png -------------------------------------------------------------------------------- /docs/img/Post_compare.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Lampro-Mellon/LM-RISCV-DV/HEAD/docs/img/Post_compare.jpg -------------------------------------------------------------------------------- /docs/img/Post_compare.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Lampro-Mellon/LM-RISCV-DV/HEAD/docs/img/Post_compare.png -------------------------------------------------------------------------------- /docs/img/google_rv_dv.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Lampro-Mellon/LM-RISCV-DV/HEAD/docs/img/google_rv_dv.png -------------------------------------------------------------------------------- /docs/img/youtube_thumb.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Lampro-Mellon/LM-RISCV-DV/HEAD/docs/img/youtube_thumb.png -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /cores/** 2 | /google_riscv_dv/** 3 | /riscv-compliance/** 4 | /integrated_cores/** 5 | **.vscode 6 | **.log 7 | **~ 8 | -------------------------------------------------------------------------------- /docs/img/Google_RISCV_DV_Flow_Random.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Lampro-Mellon/LM-RISCV-DV/HEAD/docs/img/Google_RISCV_DV_Flow_Random.png -------------------------------------------------------------------------------- /docs/img/Google_RISCV_DV_Flow_Directed.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Lampro-Mellon/LM-RISCV-DV/HEAD/docs/img/Google_RISCV_DV_Flow_Directed.png -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv_dv_extension/link.ld: -------------------------------------------------------------------------------- 1 | 2 | OUTPUT_ARCH( "riscv" ) 3 | ENTRY(_start) 4 | 5 | SECTIONS 6 | { 7 | . = 0x80000000; 8 | .text : { *(.text*) } 9 | _end = .; 10 | . = 0x80010000; 11 | .data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; } 12 | } 13 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/directed_tests/c/cmark_dccm.ld: -------------------------------------------------------------------------------- 1 | 2 | OUTPUT_ARCH( "riscv" ) 3 | ENTRY(_start) 4 | 5 | SECTIONS { 6 | .text : { *(.text*) } 7 | _end = .; 8 | . = 0xf0040000; 9 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 10 | .bss : { *(.bss) } 11 | . = 0xfffffff8; 12 | .data.ctl : { LONG(0xf0040000); LONG(STACK) } 13 | } 14 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/directed_tests/asm/hello_world_dccm.ld: -------------------------------------------------------------------------------- 1 | 2 | OUTPUT_ARCH( "riscv" ) 3 | ENTRY(_start) 4 | 5 | SECTIONS { 6 | .text : { *(.text*) } 7 | _end = .; 8 | . = 0xf0040000; 9 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 10 | .bss : { *(.bss) } 11 | . = 0xfffffff8; 12 | .data.ctl : { LONG(0xf0040000); LONG(STACK) } 13 | } 14 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv_dv_extension/linker_scripts/cmark.ld: -------------------------------------------------------------------------------- 1 | 2 | OUTPUT_ARCH( "riscv" ) 3 | ENTRY(_start) 4 | 5 | SECTIONS { 6 | .text : { *(.text*) } 7 | _end = .; 8 | . = 0xf0040000; 9 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 10 | .bss : { *(.bss) } 11 | . = 0xfffffff8; 12 | .data.ctl : { LONG(0xf0040000); LONG(STACK) } 13 | } 14 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv_dv_extension/linker_scripts/cmark_dccm.ld: -------------------------------------------------------------------------------- 1 | 2 | OUTPUT_ARCH( "riscv" ) 3 | ENTRY(_start) 4 | 5 | SECTIONS { 6 | .text : { *(.text*) } 7 | _end = .; 8 | . = 0xf0040000; 9 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 10 | .bss : { *(.bss) } 11 | . = 0xfffffff8; 12 | .data.ctl : { LONG(0xf0040000); LONG(STACK) } 13 | } 14 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv_dv_extension/linker_scripts/hello_world_dccm.ld: -------------------------------------------------------------------------------- 1 | 2 | OUTPUT_ARCH( "riscv" ) 3 | ENTRY(_start) 4 | 5 | SECTIONS { 6 | .text : { *(.text*) } 7 | _end = .; 8 | . = 0xf0040000; 9 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} 10 | .bss : { *(.bss) } 11 | . = 0xfffffff8; 12 | .data.ctl : { LONG(0xf0040000); LONG(STACK) } 13 | } 14 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/testbench_veri.f: -------------------------------------------------------------------------------- 1 | +incdir+${PRJ_DIR}/rtl/lib 2 | +incdir+${PRJ_DIR}/rtl/include 3 | +incdir+${PRJ_DIR}/snapshots/defaults 4 | 5 | // Including Testbench Files 6 | ${PRJ_DIR}/testbench/pkg.sv 7 | ${PRJ_DIR}/testbench/tracer_pkg.sv 8 | ${PRJ_DIR}/testbench/tracer.sv 9 | ${PRJ_DIR}/testbench/ahb_sif.sv 10 | ${PRJ_DIR}/testbench/tb_top.sv 11 | ${PRJ_DIR}/testbench/test_tb_top.cpp 12 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/snapshots/default/pd_defines.vh: -------------------------------------------------------------------------------- 1 | // NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 2 | // This is an automatically generated file by haroonshafique on Fri Sep 25 11:31:01 PKT 2020 3 | // 4 | // cmd: swerv -target=default 5 | // 6 | 7 | `include "common_defines.vh" 8 | `undef ASSERT_ON 9 | `undef TEC_RV_ICG 10 | `define TEC_RV_ICG CKLNQD12BWP35P140 11 | `define PHYSICAL 1 12 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv_dv_extension/linker_scripts/link_comp.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS 5 | { 6 | . = 0x80000000; 7 | .text.init : { *(.text.init) } 8 | . = ALIGN(0x1000); 9 | .tohost : { *(.tohost) } 10 | . = ALIGN(0x1000); 11 | .text : { *(.text) } 12 | . = ALIGN(0x1000); 13 | /* . = 0x80000;*/ 14 | . = 0x800e0000; 15 | .data : { *(.data) } 16 | .data.string : { *(.data.string)} 17 | .bss : { *(.bss) } 18 | _end = .; 19 | } 20 | 21 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/directed_tests/c/cmark_iccm.ld: -------------------------------------------------------------------------------- 1 | 2 | OUTPUT_ARCH( "riscv" ) 3 | ENTRY(_start) 4 | MEMORY { 5 | EXTCODE : ORIGIN = 0, LENGTH = 0x10000 6 | EXTDATA : ORIGIN = 0x10000, LENGTH = 0x10000 7 | ICCM : ORIGIN = 0xee000000, LENGTH = 0x80000 8 | DCCM : ORIGIN = 0xf0040000, LENGTH = 0x10000 9 | CTL : ORIGIN = 0xfffffff0, LENGTH = 16 10 | } 11 | SECTIONS { 12 | .text_init : {*(.text_init)} > EXTCODE 13 | init_end = .; 14 | .text : { *(.text) *(.text.startup)} > ICCM 15 | text_end = .; 16 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} > DCCM 17 | .bss : { *(.bss)} > DCCM 18 | .data.ctl : { LONG(ADDR(.text)); LONG(text_end); LONG(0xf0040000); LONG(STACK)}>CTL 19 | } 20 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv_dv_extension/linker_scripts/cmark_iccm.ld: -------------------------------------------------------------------------------- 1 | 2 | OUTPUT_ARCH( "riscv" ) 3 | ENTRY(_start) 4 | MEMORY { 5 | EXTCODE : ORIGIN = 0, LENGTH = 0x10000 6 | EXTDATA : ORIGIN = 0x10000, LENGTH = 0x10000 7 | ICCM : ORIGIN = 0xee000000, LENGTH = 0x80000 8 | DCCM : ORIGIN = 0xf0040000, LENGTH = 0x10000 9 | CTL : ORIGIN = 0xfffffff0, LENGTH = 16 10 | } 11 | SECTIONS { 12 | .text_init : {*(.text_init)} > EXTCODE 13 | init_end = .; 14 | .text : { *(.text) *(.text.startup)} > ICCM 15 | text_end = .; 16 | .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} > DCCM 17 | .bss : { *(.bss)} > DCCM 18 | .data.ctl : { LONG(ADDR(.text)); LONG(text_end); LONG(0xf0040000); LONG(STACK)}>CTL 19 | } 20 | -------------------------------------------------------------------------------- /docs/jumps_branches_loops.md: -------------------------------------------------------------------------------- 1 | # Jumps, Branches and Loop Tests 2 | RISC-V DV creates random test with jumps, branches and loop instructions with constrained randomization. Constrained randomization allows random test generation without falling in infinite loops scenarios. 3 | 4 | Follow the steps given below for jumps, branches and loop tests. 5 | ## Testlist Update 6 | Use base testlist in `google_riscv_dv` to populate the testlist in `riscv_dv_extension/testlist.yaml`. 7 | 8 | Include the following tests for jumps, branches and loop testing. 9 | 1. riscv_jump_stress_test 10 | 2. riscv_loop_test 11 | 3. riscv_rand_jump_test 12 | 13 | ## Setting up the Environment 14 | 15 | For `riscv_jump_stress_test` and `riscv_loop_test`, nothing needs to be changed to set up the environment, however, for `riscv_rand_jump_test`, follow the procedure mentioned in load_store_dccm section. To run the test follow the commands given in next section. 16 | 17 | ## Make Commands 18 | Use the following commands to run the desired test 19 | ``` 20 | #for random seed 21 | make TEST= 22 | #for fixed seed 23 | make TEST= SEED= 24 | ``` -------------------------------------------------------------------------------- /scripts/toolchain_paths.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # 3 | # ////////////////////////////////////////////////////////////////////// 4 | # Copyright [2020] [Lampro Mellon] 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # ////////////////////////////////////////////////////////////////////// 18 | 19 | export RISCV_TOOLCHAIN=$RISCV_PATH 20 | export RISCV_GCC="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-gcc" 21 | export RISCV_OBJCOPY="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-objcopy" 22 | export RISCV_LD="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-ld" 23 | export RISCV_OBJDUMP="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-objdump" 24 | 25 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/directed_tests/c/c_sample.c: -------------------------------------------------------------------------------- 1 | #include "defines.h" 2 | 3 | #define ITERATIONS 1 4 | extern int STACK; 5 | void main(); 6 | 7 | 8 | #define STDOUT 0xd0580000 9 | 10 | #define dccm_saddr 0xf004000 11 | #define dccm_eaddr 0xf0047ff0 12 | #define ones 0xffffffff 13 | #define zeros 0x00000000 14 | 15 | __asm (".section .text"); 16 | __asm (".global _start"); 17 | __asm ("_start:"); 18 | 19 | // Enable Caches in MRAC 20 | //__asm ("li t0, 0x5f555555"); 21 | //__asm ("csrw 0x7c0, t0"); 22 | 23 | // Set stack pointer. 24 | __asm ("la sp, STACK"); 25 | 26 | __asm ("jal main"); 27 | 28 | // Write 0xff to STDOUT for TB to termiate test. 29 | __asm (".global _finish"); 30 | __asm ("_finish:"); 31 | __asm ("li t0, 0xd0580000"); 32 | __asm ("addi t1, zero, 0xff"); 33 | __asm ("sb t1, 0(t0)"); 34 | __asm ("beq x0, x0, _finish"); 35 | __asm (".rept 10"); 36 | __asm ("nop"); 37 | __asm (".endr"); 38 | 39 | 40 | main() 41 | { 42 | volatile int *addr; 43 | /////ADD Code Here///// 44 | addr = (volatile int*)STDOUT; 45 | char arr[37]="Hello, is it me you are looking for!"; 46 | for(int i=0; i 20 | 21 |

Figure-1: CSV Standart Format
22 | 23 |

24 | 25 | ## Coverage Report 26 | Coverage report for the functional coverage of randomized test is generated through `urg` command in html format. Snippet of the example coverage report is given below: 27 |

28 | 29 |

Figure-2: Coverage Report
30 | 31 |

-------------------------------------------------------------------------------- /docs/spike.md: -------------------------------------------------------------------------------- 1 | # Spike Integration 2 | Spike is RISCV ISA Simulator, considered as golden reference for RISC-V. It implements the functional model of RISC-V for one or more harts. RISC-V DV environment also implements ISS flow for the generated test. Test is run both on core and ISS, in this case spike, and comparison is made afterwards for both log files. 3 | 4 |

5 | 6 |

Figure-1: Spike Flow in Simulation Environment
7 | 8 |

9 | 10 | ## Generation of Spike log 11 | Spike ISS follows the memory mapping such that after the bootloader, PC starts at `0x80000000` address. Hence, Link file for any test should be adjusted accordingly and `.text` section must start from this location. All other sections must be above this address. 12 | ### Test Compilation 13 | For the Spike simulation, .bin file for program is used for simulation. This binary version of the test program must be compiled and generated with linker flags. 14 | 15 | ## Generation of Core log 16 | To match the Spike log Program Counter mapping, SweRV-EH1 parameters needs to be set accordingly. Following changes are required. 17 | ### SweRV-EH1 Configuration 18 | #### Core Reset Vector 19 | To match the starting Program Counter (PC) to 32'h80000000 as is the contraint of Spike ISS. Change `Reset Vector` to match the `RV_RST_VEC` of `32'h80000000`. 20 | 21 | ## Unresolved Issue 22 | ### Spike simulation for .s asm tests 23 | Spike simulation for .s asm tests ends in assertion failure. This issue stems from the gcc-compilation issue without linker flag. -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/flist_verilator.f: -------------------------------------------------------------------------------- 1 | +incdir+${PRJ_DIR}/rtl/lib 2 | +incdir+${PRJ_DIR}/rtl/include 3 | +incdir+${PRJ_DIR}/snapshots/default 4 | 5 | //+libext+.v 6 | 7 | // Including Defines Files 8 | ${PRJ_DIR}/snapshots/default/common_defines_verilator.vh 9 | ${PRJ_DIR}/rtl/include/swerv_types.sv 10 | 11 | // Including Design Files 12 | ${PRJ_DIR}/rtl/swerv_wrapper.sv 13 | ${PRJ_DIR}/rtl/mem.sv 14 | ${PRJ_DIR}/rtl/pic_ctrl.sv 15 | ${PRJ_DIR}/rtl/swerv.sv 16 | ${PRJ_DIR}/rtl/dma_ctrl.sv 17 | ${PRJ_DIR}/rtl/ifu/ifu_aln_ctl.sv 18 | ${PRJ_DIR}/rtl/ifu/ifu_compress_ctl.sv 19 | ${PRJ_DIR}/rtl/ifu/ifu_ifc_ctl.sv 20 | ${PRJ_DIR}/rtl/ifu/ifu_bp_ctl.sv 21 | ${PRJ_DIR}/rtl/ifu/ifu_ic_mem.sv 22 | ${PRJ_DIR}/rtl/ifu/ifu_mem_ctl.sv 23 | ${PRJ_DIR}/rtl/ifu/ifu_iccm_mem.sv 24 | ${PRJ_DIR}/rtl/ifu/ifu.sv 25 | ${PRJ_DIR}/rtl/dec/dec_decode_ctl.sv 26 | ${PRJ_DIR}/rtl/dec/dec_gpr_ctl.sv 27 | ${PRJ_DIR}/rtl/dec/dec_ib_ctl.sv 28 | ${PRJ_DIR}/rtl/dec/dec_tlu_ctl.sv 29 | ${PRJ_DIR}/rtl/dec/dec_trigger.sv 30 | ${PRJ_DIR}/rtl/dec/dec.sv 31 | ${PRJ_DIR}/rtl/exu/exu_alu_ctl.sv 32 | ${PRJ_DIR}/rtl/exu/exu_mul_ctl.sv 33 | ${PRJ_DIR}/rtl/exu/exu_div_ctl.sv 34 | ${PRJ_DIR}/rtl/exu/exu.sv 35 | ${PRJ_DIR}/rtl/lsu/lsu.sv 36 | ${PRJ_DIR}/rtl/lsu/lsu_clkdomain.sv 37 | ${PRJ_DIR}/rtl/lsu/lsu_addrcheck.sv 38 | ${PRJ_DIR}/rtl/lsu/lsu_lsc_ctl.sv 39 | ${PRJ_DIR}/rtl/lsu/lsu_stbuf.sv 40 | ${PRJ_DIR}/rtl/lsu/lsu_bus_buffer.sv 41 | ${PRJ_DIR}/rtl/lsu/lsu_bus_intf.sv 42 | ${PRJ_DIR}/rtl/lsu/lsu_ecc.sv 43 | ${PRJ_DIR}/rtl/lsu/lsu_dccm_mem.sv 44 | ${PRJ_DIR}/rtl/lsu/lsu_dccm_ctl.sv 45 | ${PRJ_DIR}/rtl/lsu/lsu_trigger.sv 46 | ${PRJ_DIR}/rtl/dbg/dbg.sv 47 | ${PRJ_DIR}/rtl/dmi/dmi_wrapper.v 48 | ${PRJ_DIR}/rtl/dmi/dmi_jtag_to_core_sync.v 49 | ${PRJ_DIR}/rtl/dmi/rvjtag_tap.sv 50 | ${PRJ_DIR}/rtl/lib/beh_lib.sv 51 | ${PRJ_DIR}/rtl/lib/mem_lib.sv 52 | ${PRJ_DIR}/rtl/lib/ahb_to_axi4.sv 53 | ${PRJ_DIR}/rtl/lib/axi4_to_ahb.sv 54 | 55 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/directed_tests/asm/hello_world2.s: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | // 16 | 17 | // Assembly code for Hello World 18 | // Not using only ALU ops for creating the string 19 | 20 | 21 | #include "defines.h" 22 | 23 | #define STDOUT 0xd0580000 24 | 25 | 26 | // Code to execute 27 | .section .text 28 | .global _start 29 | _start: 30 | 31 | // Clear minstret 32 | csrw minstret, zero 33 | csrw minstreth, zero 34 | 35 | // Set up MTVEC - not expecting to use it though 36 | li x1, RV_ICCM_SADR 37 | csrw mtvec, x1 38 | 39 | 40 | // Enable Caches in MRAC 41 | li x1, 0x55555555 42 | csrw 0x7c0, x1 43 | 44 | // Load string from hw_data 45 | // and write to stdout address 46 | 47 | li x3, STDOUT 48 | la x4, hw_data 49 | 50 | loop: 51 | lb x5, 0(x4) 52 | sb x5, 0(x3) 53 | addi x4, x4, 1 54 | bnez x5, loop 55 | 56 | // Write 0xff to STDOUT for TB to termiate test. 57 | _finish: 58 | li x3, STDOUT 59 | addi x5, x0, 0xff 60 | sb x5, 0(x3) 61 | beq x0, x0, _finish 62 | .rept 100 63 | nop 64 | .endr 65 | 66 | .data 67 | hw_data: 68 | .ascii "------------------------------------\n" 69 | .ascii "Hello World from SweRV EH1.4 @WDC !!\n" 70 | .ascii "------------------------------------" 71 | .byte 0 72 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/directed_tests/asm/hello_world.s: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | // 16 | 17 | // Assembly code for Hello World 18 | // Not using only ALU ops for creating the string 19 | 20 | 21 | #include "defines.h" 22 | 23 | #define STDOUT 0xd0580000 24 | 25 | 26 | // Code to execute 27 | .section .text 28 | .global _start 29 | _start: 30 | 31 | // Clear minstret 32 | csrw minstret, zero 33 | csrw minstreth, zero 34 | 35 | // Set up MTVEC - not expecting to use it though 36 | li x1, RV_ICCM_SADR 37 | csrw mtvec, x1 38 | 39 | 40 | // Enable Caches in MRAC 41 | li x1, 0x5f555555 42 | csrw 0x7c0, x1 43 | 44 | // Load string from hw_data 45 | // and write to stdout address 46 | 47 | li x3, STDOUT 48 | la x4, hw_data 49 | 50 | loop: 51 | lb x5, 0(x4) 52 | sb x5, 0(x3) 53 | addi x4, x4, 1 54 | bnez x5, loop 55 | 56 | // Write 0xff to STDOUT for TB to terminate test. 57 | _finish: 58 | li x3, STDOUT 59 | addi x5, x0, 0xff 60 | sb x5, 0(x3) 61 | beq x0, x0, _finish 62 | .rept 100 63 | nop 64 | .endr 65 | 66 | .global hw_data 67 | .data 68 | hw_data: 69 | .ascii "----------------------------------\n" 70 | .ascii "Hello World from SweRV EH1 @WDC !!\n" 71 | .ascii "----------------------------------\n" 72 | .byte 0 73 | -------------------------------------------------------------------------------- /docs/exceptions_interrupts.md: -------------------------------------------------------------------------------- 1 | # [Exceptions](###Exceptions) and [interrupts](###Interrupts) 2 | ### Exceptions 3 | An exception is an unexpected event from within the processor and caused by some instruction written within a program. We have caused the following RISCV exceptions to trigger: 4 | 5 | 1. `Illegal instruction exception` is triggered when an unknown opcode is detected in any instruction. 6 | 2. `Load address misaligned exception` is triggered when data to be loaded is divided into two memory regions. 7 | 3. `Load access fault exception` is triggered when the address of data to be loaded is out of core internal memory. 8 | 4. `Store address misaligned exception` is triggered when data to be written is divided into two memory regions. 9 | 5. `Store access fault exception` is triggered when the address of data to be written is out of core internal memory. 10 | 6. `Ecall from M-mode exception` is simply triggered by `ecall` instruction. 11 | ### Interrupts 12 | An interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention. We have implemented [internal timer interrupt](###Internal timer interrupt) for `SweRV EH1`. 13 | ### Internal timer interrupt 14 | RISCV uses two CSRs `mtime` and `mtimecmp` for a timer interrupt. When value in `mtime` is greater than the value of `mtimecmp`. `SweRV EH1` uses four CSRs `mitcnt0/1` and `mitb0/1`, whenever the value of `mitcnt0/1` is greater than `mitb0/1`. 15 | # Changes 16 | We made changes in following files for this task: 17 | 1. [riscv_asm_program_gen.sv](###riscv_asm_program_gen.sv) 18 | 2. [riscv_instr_gen_config.sv](###riscv_instr_gen_config.sv) 19 | ### riscv_asm_program_gen.sv 20 | 1. Updated already written exception handlers to go to the next instruction. 21 | 2. Exception handlers were added for misaligned exceptions. 22 | 3. Added directed instructions to trigger these exceptions and interrupts. 23 | ### riscv_instr_gen_config.sv 24 | 1. Introduced an argument to `gen_opts` to enable stream which triggers instructions. -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv-target/testlists/testlist_Zifencei.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Google LLC 2 | # Copyright 2020 Lampro Mellon 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # ================================================================================ 17 | # Regression test list format 18 | # -------------------------------------------------------------------------------- 19 | # test : Assembly test name 20 | # description : Description of this test 21 | # gen_opts : Instruction generator options 22 | # iterations : Number of iterations of this test 23 | # no_iss : Enable/disable ISS simulator (Optional) 24 | # gen_test : Test name used by the instruction generator 25 | # asm_tests : Path to directed, hand-coded assembly test file or directory 26 | # c_tests : Path to directed, hand-coded C test file or directory 27 | # rtl_test : RTL simulation test name 28 | # cmp_opts : Compile options passed to the instruction generator 29 | # sim_opts : Simulation options passed to the instruction generator 30 | # no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) 31 | # compare_opts : Options for the RTL & ISS trace comparison 32 | # gcc_opts : gcc compile options 33 | # -------------------------------------------------------------------------------- 34 | 35 | - test: Fencei 36 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/Zifencei/src/Fencei.S 37 | iterations: 1 38 | rtl_test: core_compliance_test 39 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/SweRV_EH1_flist.f: -------------------------------------------------------------------------------- 1 | +incdir+${PRJ_DIR}/rtl/lib 2 | +incdir+${PRJ_DIR}/rtl/include 3 | +incdir+${PRJ_DIR}/snapshots/default 4 | 5 | +libext+.v 6 | 7 | // Including Defines Files 8 | ${PRJ_DIR}/snapshots/default/common_defines.vh 9 | ${PRJ_DIR}/rtl/include/swerv_types.sv 10 | 11 | // Including Design Files 12 | ${PRJ_DIR}/rtl/swerv_wrapper.sv 13 | ${PRJ_DIR}/rtl/mem.sv 14 | ${PRJ_DIR}/rtl/pic_ctrl.sv 15 | ${PRJ_DIR}/rtl/swerv.sv 16 | ${PRJ_DIR}/rtl/dma_ctrl.sv 17 | ${PRJ_DIR}/rtl/ifu/ifu_aln_ctl.sv 18 | ${PRJ_DIR}/rtl/ifu/ifu_compress_ctl.sv 19 | ${PRJ_DIR}/rtl/ifu/ifu_ifc_ctl.sv 20 | ${PRJ_DIR}/rtl/ifu/ifu_bp_ctl.sv 21 | ${PRJ_DIR}/rtl/ifu/ifu_ic_mem.sv 22 | ${PRJ_DIR}/rtl/ifu/ifu_mem_ctl.sv 23 | ${PRJ_DIR}/rtl/ifu/ifu_iccm_mem.sv 24 | ${PRJ_DIR}/rtl/ifu/ifu.sv 25 | ${PRJ_DIR}/rtl/dec/dec_decode_ctl.sv 26 | ${PRJ_DIR}/rtl/dec/dec_gpr_ctl.sv 27 | ${PRJ_DIR}/rtl/dec/dec_ib_ctl.sv 28 | ${PRJ_DIR}/rtl/dec/dec_tlu_ctl.sv 29 | ${PRJ_DIR}/rtl/dec/dec_trigger.sv 30 | ${PRJ_DIR}/rtl/dec/dec.sv 31 | ${PRJ_DIR}/rtl/exu/exu_alu_ctl.sv 32 | ${PRJ_DIR}/rtl/exu/exu_mul_ctl.sv 33 | ${PRJ_DIR}/rtl/exu/exu_div_ctl.sv 34 | ${PRJ_DIR}/rtl/exu/exu.sv 35 | ${PRJ_DIR}/rtl/lsu/lsu.sv 36 | ${PRJ_DIR}/rtl/lsu/lsu_clkdomain.sv 37 | ${PRJ_DIR}/rtl/lsu/lsu_addrcheck.sv 38 | ${PRJ_DIR}/rtl/lsu/lsu_lsc_ctl.sv 39 | ${PRJ_DIR}/rtl/lsu/lsu_stbuf.sv 40 | ${PRJ_DIR}/rtl/lsu/lsu_bus_buffer.sv 41 | ${PRJ_DIR}/rtl/lsu/lsu_bus_intf.sv 42 | ${PRJ_DIR}/rtl/lsu/lsu_ecc.sv 43 | ${PRJ_DIR}/rtl/lsu/lsu_dccm_mem.sv 44 | ${PRJ_DIR}/rtl/lsu/lsu_dccm_ctl.sv 45 | ${PRJ_DIR}/rtl/lsu/lsu_trigger.sv 46 | ${PRJ_DIR}/rtl/dbg/dbg.sv 47 | ${PRJ_DIR}/rtl/dmi/dmi_wrapper.v 48 | ${PRJ_DIR}/rtl/dmi/dmi_jtag_to_core_sync.v 49 | ${PRJ_DIR}/rtl/dmi/rvjtag_tap.sv 50 | -v ${PRJ_DIR}/rtl/lib/beh_lib.sv 51 | -v ${PRJ_DIR}/rtl/lib/mem_lib.sv 52 | -v ${PRJ_DIR}/rtl/lib/ahb_to_axi4.sv 53 | -v ${PRJ_DIR}/rtl/lib/axi4_to_ahb.sv 54 | 55 | // Including Testbench Files 56 | ${PRJ_DIR}/testbench/pkg.sv 57 | ${PRJ_DIR}/testbench/tracer_pkg.sv 58 | ${PRJ_DIR}/testbench/tracer.sv 59 | ${PRJ_DIR}/testbench/ahb_sif.sv 60 | ${PRJ_DIR}/testbench/tb_top.sv 61 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/waves.tcl: -------------------------------------------------------------------------------- 1 | # TCL file invoked from VCS's simv at run-time using this: -ucli -do 2 | 3 | # We have to tell VCS where to put the waves. We do this with a 4 | # SIM_DIR environment variable, which we prepend to the wave name. If 5 | # SIM_DIR is not set, we just dump to the current directory. 6 | if { [info exists ::env(SIM_DIR)] } { 7 | set sim_dir $::env(SIM_DIR) 8 | } else { 9 | set sim_dir "." 10 | } 11 | 12 | if { [info exists ::env(VERDI_HOME)] } { 13 | # Use FSDB for dumping data, but only if we have Verdi set up. 14 | 15 | # Syntax: fsdbDumpfile FSDB_Name [Limit_Size] 16 | fsdbDumpfile "${sim_dir}/waves.fsdb" 17 | 18 | # Syntax: fsdbDumpvars [depth] [instance] [option]* 19 | ############################################################################## 20 | # Option Description 21 | ############################################################################## 22 | # +mda Dumps memory and MDA signals in all scopes. 23 | # +packedmda Dumps packed signals 24 | # +struct Dumps structs 25 | # +skip_cell_instance=mode Enables or disables cell dumping 26 | # +strength Enables strength dumping 27 | # +parameter Dumps parameters 28 | # +power Dumps power-related signals 29 | # +trace_process Dumps VHDL processes 30 | # +no_functions Disables dumping of functions 31 | # +sva Dumps assertions 32 | # +Reg_Only Dumps only reg type signals 33 | # +IO_Only Dumps only IO port signals 34 | # +by_file= File to specify objects to add 35 | # +all Dumps memories, MDA signals, structs, unions,power, and packed structs 36 | fsdbDumpvars 0 tb_top +all 37 | fsdbDumpSVA 0 tb_top.rvtop 38 | } else { 39 | # We don't have VERDI set up, so use VCS's standard dumping format. 40 | dump -file "${sim_dir}/waves.vpd" 41 | dump -add { tb_top } -depth 0 -aggregates -scope "." 42 | } 43 | 44 | run 45 | quit 46 | -------------------------------------------------------------------------------- /docs/post_compare.md: -------------------------------------------------------------------------------- 1 | # Post-sim Comparison 2 | ------ 3 | 4 | ### Introduction 5 | 6 | Post-sim is used to compare the Spike ISS and RTL simulation results. 7 | Python scripts are used for this comparison. Comparing all the tests as specified by the iterations (no. of tests) the results are generated. 8 | For Post-sim the log files from Spike ISS and trace are taken and converted into CSV files using coresponding log to CSV python scripts. 9 | 10 | ### Working Flow 11 | 12 | Spike ISS log and core trace log are used to generate the respective CSV files. Using Spike ISS log ***spike_log_to_trace_CSV.py*** python script generates Spike ISS CSV and using core trace log ***core_log_to_trace_CSV.py*** python script generates trace CSV. Then the ***post_compare*** target in **Makefile** uses the ***compare*** function in sim.py which in turn uses ***compare_trace_CSV*** function from the **instr_trace_compare.py** python script for comparing the generated CSV files. This can be visualized from the following flow diagram. 13 | 14 | 15 |

16 | 17 |

Figure-1: Post-sim Flow
18 | 19 |

20 | 21 |

22 | 23 | **instr_trace_compare.py** script compares both the CSV files as: 24 | - It takes data from Spike CSV, stores in a list and then compares it with the core CSV. 25 | - Taking Spike CSV as a standard it compares its **rd** values with the corresponding core CSV **rd** values. 26 | - It checks the *GPR* (rd values) update between both the trace CSV files. 27 | - In case of mismatched GPR update, the test fails. 28 | 29 | #### Output File 30 | 31 | A regression log (**regr.log**) file is generated which shows the result of post-sim comparison. It shows the passed tests or in failed test cases it shows the instructions on which those tests failed. 32 | It can be seen in the following figure that ***riscv_rand_instr_test.1*** passed but ***riscv_rand_instr_test.0*** failed. So the **regr.log** shows the respective mismatch cases for **riscv_rand_instr_test.0.o**. 33 | 34 |

35 | 36 |

Figure-2: regr.log
37 | 38 | 39 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/yaml/rtl_simulation.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Google LLC 2 | # Copyright 2020 Lampro Mellon 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http:#www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | - tool: vcs 17 | compile: 18 | cmd: 19 | - "vcs -full64 -LDFLAGS '-Wl,--no-as-needed' 20 | -assert svaext -sverilog +error+500 21 | -timescale=1ns/10ps 22 | -f SweRV_EH1_flist.f 23 | -Mdir=/vcs_simv.csrc 24 | -o /vcs_simv 25 | -l /compile.log 26 | -lca -kdb " 27 | wave_opts: > 28 | -debug_access+all -ucli -do waves.tcl 29 | cov_opts: > 30 | -cm line+tgl+branch 31 | -cm_hier cover.cfg 32 | -cm_dir /test.vdb 33 | 34 | sim: 35 | cmd: > 36 | env SIM_DIR= 37 | /vcs_simv +vcs+lic+wait 38 | 39 | +tracer_file_base=/trace_core 40 | -l /sim.log 41 | wave_opts: > 42 | -ucli -do /waves.tcl 43 | cov_opts: > 44 | -cm line+tgl+branch 45 | -cm_name test__ 46 | -cm_dir /test.vdb 47 | 48 | - tool: verilator 49 | compile: 50 | cmd: 51 | - "verilator --cc -CFLAGS \"-std=c++11\" 52 | -Wno-UNOPTFLAT -I/testbench 53 | -f flist_verilator.f --top-module tb_top -exe test_tb_top.cpp --autoflush --trace 54 | -f testbench_veri.f" 55 | - "cp ./testbench/test_tb_top.cpp obj_dir" 56 | - "make -C obj_dir -f Vtb_top.mk OPT_FAST=\"-O2\"" 57 | sim: 58 | cmd: > 59 | ./obj_dir/Vtb_top +dumpon >>/sim.log 60 | env SIM_DIR= 61 | 62 | +tracer_file_base=/trace_core 63 | -l /sim.log 64 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/google_riscv_dv/riscv_instr_base_test.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2020 Google LLC 3 | Copyright 2020 PerfectVIPs Inc. 4 | Licensed under the Apache License, Version 2.0 (the "License"); 5 | you may not use this file except in compliance with the License. 6 | You may obtain a copy of the License at 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | Unless required by applicable law or agreed to in writing, software 9 | distributed under the License is distributed on an "AS IS" BASIS, 10 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 11 | """ 12 | 13 | import sys 14 | import logging 15 | import os 16 | import imp 17 | 18 | cwd = os.getcwd() 19 | c_p = os.path.realpath(__file__) 20 | sys.path.insert(0, "./../../google_riscv_dv/pygen/") 21 | from pygen_src.riscv_instr_pkg import * 22 | from pygen_src.riscv_instr_gen_config import cfg # NOQA 23 | for isa in rcs.supported_isa: 24 | import_module("pygen_src.isa." + isa.name.lower() + "_instr") 25 | from pygen_src.isa.riscv_instr import riscv_instr # NOQA 26 | from pygen_src.riscv_asm_program_gen import riscv_asm_program_gen # NOQA 27 | from pygen_src.riscv_utils import gen_config_table 28 | class riscv_instr_base_test: 29 | def __init__(self): 30 | self.start_idx = cfg.argv.start_idx 31 | self.asm_file_name = cfg.argv.asm_file_name 32 | self.asm = "" 33 | 34 | def run_phase(self): 35 | for _ in range(cfg.num_of_tests): 36 | self.randomize_cfg() 37 | self.asm = riscv_asm_program_gen() 38 | riscv_instr.create_instr_list(cfg) 39 | if cfg.asm_test_suffix != "": 40 | self.asm_file_name = "{}.{}".format(self.asm_file_name, 41 | cfg.asm_test_suffix) 42 | test_name = "{}_{}.S".format(self.asm_file_name, 43 | _ + self.start_idx) 44 | self.asm.get_directed_instr_stream() 45 | self.asm.gen_program() 46 | self.asm.gen_test_file(test_name) 47 | 48 | def randomize_cfg(self): 49 | cfg.randomize() 50 | logging.info("riscv_instr_gen_config is randomized") 51 | gen_config_table() 52 | 53 | 54 | riscv_base_test_ins = riscv_instr_base_test() 55 | riscv_base_test_ins.run_phase() 56 | 57 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/testbench/test_tb_top.cpp: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // 4 | // Licensed under the Apache License, Version 2.0 (the "License"); 5 | // you may not use this file except in compliance with the License. 6 | // You may obtain a copy of the License at 7 | // 8 | // http://www.apache.org/licenses/LICENSE-2.0 9 | // 10 | // Unless required by applicable law or agreed to in writing, software 11 | // distributed under the License is distributed on an "AS IS" BASIS, 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | // See the License for the specific language governing permissions and 14 | // limitations under the License. 15 | // 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include "Vtb_top.h" 22 | #include "verilated.h" 23 | #include "verilated_vcd_c.h" 24 | 25 | vluint64_t main_time = 0; 26 | 27 | double sc_time_stamp () { 28 | return main_time; 29 | } 30 | 31 | 32 | int main(int argc, char** argv) { 33 | std::cout << "\nVerilatorTB: Start of sim\n" << std::endl; 34 | 35 | Verilated::commandArgs(argc, argv); 36 | 37 | Vtb_top* tb = new Vtb_top; 38 | 39 | // init trace dump 40 | VerilatedVcdC* tfp = NULL; 41 | 42 | // initializing file path for sim.vcd 43 | std::stringstream file_path; 44 | std::string file; 45 | 46 | // appending sim_dir path with sim.vcd to copy it in the right folder 47 | file_path << argv[3] << "/sim.vcd"; 48 | file = file_path.str(); 49 | //std::cout << file_path << std::endl; 50 | 51 | std::string delimiter = "="; 52 | std::string f_token; 53 | f_token = file.substr(file.rfind(delimiter)+1); 54 | //std::cout << f_token << std::endl; 55 | 56 | #if VM_TRACE 57 | Verilated::traceEverOn(true); 58 | tfp = new VerilatedVcdC; 59 | tb->trace (tfp, 24); 60 | //Adding sim.vcd path 61 | tfp->open (f_token.c_str()); 62 | #endif 63 | // Simulate 64 | while(!Verilated::gotFinish()){ 65 | #if VM_TRACE 66 | tfp->dump (main_time); 67 | #endif 68 | main_time += 5; 69 | tb->core_clk = !tb->core_clk; 70 | tb->eval(); 71 | } 72 | 73 | #if VM_TRACE 74 | tfp->close(); 75 | #endif 76 | 77 | std::cout << "\nVerilatorTB: End of sim" << std::endl; 78 | exit(EXIT_SUCCESS); 79 | 80 | return 0; 81 | 82 | } 83 | -------------------------------------------------------------------------------- /docs/load_store_dccm.md: -------------------------------------------------------------------------------- 1 | # Load/Store from DCCM in SweRV-EH1 using RISC-V DV 2 | Loading and storing data from one of the internal memories like DCCM can be done via randomized tests. Follow the steps given in the following sections to run this test. 3 | ## Set up Memory Map 4 | Memory map needs to be configured from riscv_instr_gen_config.sv file. Change the following memory map regions according to the core's memory map. Random data will be generated and used in the randomized test according to this memory map. 5 | ``` 6 | mem_region_t mem_region[$] = '{ 7 |     '{name:"region_0", size_in_bytes: 1024*32, xwr: 3'b111}, 8 |     '{name:"region_1", size_in_bytes: 1024*16, xwr: 3'b111} 9 |   }; 10 | ``` 11 | ### Random Data Generation 12 | Random data generated can be all-zeroes, incremental or random data. Selection between these options happens randomly. Data size is governed by the memory map set up in riscv_instr_gen_config.sv. 13 | 14 | ## Preloading of DCCM for SweRV-EH1 Test bench 15 | Preloading task for `DCCM` in `Testbench Top` requires starting address and ending address placed in `data.hex` at certain location 0xfffffff8 and 0xffffffffc respectively for the current integration of SweRV-EH1 in LM-RISCV-DV. This information can be added via `.data.ctl` section in linker script. Linker script example given below demonstrates this requirement as well. 16 | 17 | ## Linking random data through Linker Script 18 | Include the memory map region in the .data section through Linker Scripts. As per the Makefile flow, name the linker script same as the test name with .ld extension and place the custom linker script in `riscv_dv_extension/linker_scripts` directory. 19 | Example linker script is given below. Note the addition of region_0 and region_1 (same names as set in memory map) in .data section. 20 | ``` 21 | OUTPUT_ARCH( "riscv" ) 22 | ENTRY(_start) 23 | 24 | SECTIONS { 25 |   . = 0x80000000; 26 |   .text   : { *(.text*) } 27 |   . = ALIGN(0x40); 28 |   .tohost : { *(.tohost) } 29 |   . = ALIGN(0x1000); 30 |   .page_table : { *(.page_table) } 31 |   .user_stack : { *(.user_stack) } 32 |   .kernel_data : { *(.kernel_data) } 33 |   .kernel_stack : { *(.kernel_stack) } 34 |   _end = .; 35 |   . = 0xfffffff8; 36 |   .data.ctl : { LONG(0xf0040000); LONG(STACK) } 37 | . = 0xf0040000; 38 |   .data  :  { *(.data) *(.region_0) *(.region_1) STACK = ALIGN(16) + 0x1000;} 39 | _data_end = .; 40 |   .bss : AT(_data_end) { *(.bss) } 41 | } 42 | ``` 43 | 44 | ## Make Command 45 | Use the following commands to run the load/store test 46 | ``` 47 | #for random seed 48 | make TEST=riscv_load_store_instr_dccm_test SEED= LINK=1 49 | 50 | ``` -------------------------------------------------------------------------------- /docs/SweRV_Tracer.md: -------------------------------------------------------------------------------- 1 | # SweRV EH1 Tracer Implementation 2 | --- 3 | 4 | ### Introduction 5 | 6 | Advanced debugging capability that allows capturing code execution and system events. A tracer is implemented to help designers to find what is going on when the instructions are being executed. It produces a text (log) file with a human-readable trace that enables the users to determine the exact set of instructions executed by the core. It is used for debugging and analyzing functional verification. 7 | 8 | 9 | Features two main categories: 10 | 11 | - **Core Trace:** inspects the code execution 12 | - **System Trace:** oversees the system behaviour 13 | 14 | Currently we are focussing on implementing core trace. 15 | 16 | ### The Trace file 17 | 18 | The tracer takes execution information from the RISC-V Verification Interface (RVFI) and produces a log file. Trace imports a file named **tracer_pkg** which in turn imports a **pkg** file. 19 | 20 | SweRV EH1 is a dual issue core and so the trace file is updated to implement dual issue. On a *valid* signal, the corresponding bits of the PC, instruction and the respective registers are used to generate a log file named **trace_core_xxx.log**. Tracer module is instantiated in **tb_top**. ***rtl_sim*** target is used for the generation of trace log files for corresponding number of tests. ***iss_sim*** target generates the trace log files of the Spike ISS simulation. Both of these trace log files are then utilized in *post-sim* comparison. 21 | 22 | ### Output file 23 | 24 | A log file named **trace_core_xxx.log** is generated as an output of the tracer implementation. It contains the time instants, cycle count, PC, decoded instruction, operands' registers and the memory contents. 25 | 26 | #### Tracer Output Format 27 | 28 | The output log is in the following format containing six columns, separated by tabs: 29 | 30 | - **Simulation Time:** The current simulation time. 31 | - **Clock Cycle Count:** The number of cycles since the last reset. 32 | - **Program Counter (PC):** The program counter. 33 | - **Instruction:** The executed instruction (hexadecimal). 32 bit wide instructions (8 hex digits) are uncompressed instructions, 16 bit wide instructions (4 hex digits) are compressed instructions. 34 | - **Decoded Instruction:** Decoded instruction string, together with the accessed registers and read/written memory values. Jumps and branches show the target address. 35 | - **Register and memory contents:** For all accessed registers, the value before and after the instruction execution is given. For memory accesses, the address and the loaded and stored data are given. 36 | 37 | *Figure-1* shows a trace log file generated for a **riscv_rand_instr_test.0** test. 38 | 39 |

40 | 41 |

42 | 43 |
Figure-1: Trace log file
-------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv-target/model_test.h: -------------------------------------------------------------------------------- 1 | // RISC-V Compliance Test Header File 2 | // Copyright (c) 2017, Codasip Ltd. All Rights Reserved. 3 | // See LICENSE for license details. 4 | // 5 | // Description: Common header file for RV32I tests 6 | 7 | #ifndef _COMPLIANCE_MODEL_H 8 | #define _COMPLIANCE_MODEL_H 9 | 10 | //----------------------------------------------------------------------- 11 | // RV Compliance Macros 12 | //----------------------------------------------------------------------- 13 | 14 | #define RVMODEL_HALT \ 15 | la a0, data_begin; \ 16 | la a1, data_end; \ 17 | li a2, 0x80005008; \ 18 | compliance_halt_loop: \ 19 | beq a0, a1, compliance_halt_break; \ 20 | addi a3, a0, 4; \ 21 | compliance_halt_loop2: \ 22 | addi a3, a3, -1; \ 23 | \ 24 | lb a4, 0 (a3); \ 25 | srai a5, a4, 4; \ 26 | andi a5, a5, 0xF; \ 27 | li a6, 10; \ 28 | blt a5, a6, notLetter; \ 29 | addi a5, a5, 39; \ 30 | notLetter: \ 31 | addi a5, a5, 0x30; \ 32 | sb a5, 0 (a2); \ 33 | \ 34 | srai a5, a4, 0; \ 35 | andi a5, a5, 0xF; \ 36 | li a6, 10; \ 37 | blt a5, a6, notLetter2; \ 38 | addi a5, a5, 39; \ 39 | notLetter2: \ 40 | addi a5, a5, 0x30; \ 41 | sb a5, 0 (a2); \ 42 | bne a0, a3,compliance_halt_loop2; \ 43 | addi a0, a0, 4; \ 44 | \ 45 | li a4, '\n'; \ 46 | sb a4, 0 (a2); \ 47 | j compliance_halt_loop; \ 48 | j compliance_halt_break; \ 49 | compliance_halt_break: \ 50 | li a0,0x80005009; \ 51 | sb a3,0(a0); \ 52 | test_done:\ 53 | li gp,1; \ 54 | ecall; 55 | 56 | #define RVMODEL_BOOT \ 57 | .section .text.init; \ 58 | .align 4; \ 59 | .globl _start; \ 60 | _start: \ 61 | 62 | #define RVMODEL_DATA_BEGIN .align 4; .global data_begin; data_begin: 63 | 64 | #define RVMODEL_DATA_END .align 4; .global data_end; data_end: 65 | // Env Variable to be set accordingly 66 | #define XLEN 32 67 | 68 | #define RVMODEL_IO_WRITE_STR(_SP, _STR) 69 | 70 | #define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I) 71 | 72 | //RVTEST_IO_ASSERT_SFPR_EQ 73 | #define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I) 74 | //RVTEST_IO_ASSERT_DFPR_EQ 75 | #define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) 76 | 77 | // TODO: specify the routine for setting machine software interrupt 78 | #define RVMODEL_SET_MSW_INT 79 | 80 | // TODO: specify the routine for clearing machine software interrupt 81 | #define RVMODEL_CLEAR_MSW_INT 82 | 83 | // TODO: specify the routine for clearing machine timer interrupt 84 | #define RVMODEL_CLEAR_MTIMER_INT 85 | 86 | // TODO: specify the routine for clearing machine external interrupt 87 | #define RVMODEL_CLEAR_MEXT_INT 88 | 89 | #endif // _COMPLIANCE_MODEL_H -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv-target/testlists/testlist_M.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Google LLC 2 | # Copyright 2020 Lampro Mellon 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # ================================================================================ 17 | # Regression test list format 18 | # -------------------------------------------------------------------------------- 19 | # test : Assembly test name 20 | # description : Description of this test 21 | # gen_opts : Instruction generator options 22 | # iterations : Number of iterations of this test 23 | # no_iss : Enable/disable ISS simulator (Optional) 24 | # gen_test : Test name used by the instruction generator 25 | # asm_tests : Path to directed, hand-coded assembly test file or directory 26 | # c_tests : Path to directed, hand-coded C test file or directory 27 | # rtl_test : RTL simulation test name 28 | # cmp_opts : Compile options passed to the instruction generator 29 | # sim_opts : Simulation options passed to the instruction generator 30 | # no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) 31 | # compare_opts : Options for the RTL & ISS trace comparison 32 | # gcc_opts : gcc compile options 33 | # -------------------------------------------------------------------------------- 34 | 35 | - test: div-01 36 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/M/src/div-01.S 37 | iterations: 1 38 | rtl_test: core_compliance_test 39 | 40 | - test: divu-01 41 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/M/src/divu-01.S 42 | iterations: 1 43 | rtl_test: core_compliance_test 44 | 45 | - test: mul-01 46 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/M/src/mul-01.S 47 | iterations: 1 48 | rtl_test: core_compliance_test 49 | 50 | - test: mulh-01 51 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/M/src/mulh-01.S 52 | iterations: 1 53 | rtl_test: core_compliance_test 54 | 55 | - test: mulhsu-01 56 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/M/src/mulhsu-01.S 57 | iterations: 1 58 | rtl_test: core_compliance_test 59 | 60 | - test: mulhu-01 61 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/M/src/mulhu-01.S 62 | iterations: 1 63 | rtl_test: core_compliance_test 64 | 65 | - test: rem-01 66 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/M/src/rem-01.S 67 | iterations: 1 68 | rtl_test: core_compliance_test 69 | 70 | - test: remu-01 71 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/M/src/remu-01.S 72 | iterations: 1 73 | rtl_test: core_compliance_test -------------------------------------------------------------------------------- /docs/document_csr_test.md: -------------------------------------------------------------------------------- 1 | # Control and Status registers (CSRs) 2 | CSRs contain the working state of a RISC-V machine. Some of the CSRs are used to store machine specifications like `VENDORID`, `ISA`, etc., while others are used for `interrupts`, `exceptions`, and `debugging`. CSRs are different from normal registers in a sense that a bit field in a CSR can be `only readable`, `readable and writeable`, `write any read legal` (anything can be written but only legal values are read) or `write legal read legal` while normal registers and memory locations are `readable and writeable`, details of RISCV implemented CSRs can be found [here](https://riscv.org//wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf). 3 | 4 | # RISCV-DV CSR test generation 5 | In this section, we'll discuss the files needed for the CSR test and [changes](###Changes) made for a successful run of the test. 6 | 7 | RISCV-DV uses following files for CSR test. 8 | 1. [csr_template.yaml](###csr_template.yaml) 9 | 2. [gen_csr_test.py](###gen_csr_test.py) 10 | ## csr_template.yaml 11 | CSRs under test are written in `csr_template.yaml`, following informations are provided for each each CSR. This file needs to be updated for each core according to CSRs implementation. 12 | 13 | 1. [Name](###Name) 14 | 2. [Description](###Description) 15 | 3. [Address](###Address) 16 | 4. [Previlege mode](###Previlege-mode) 17 | 5. [ISA](###ISA) 18 | ### Name 19 | The name of the CSR is given in the `csr` field. 20 | ### Description 21 | The `Description` field describes the purpose of CSR. 22 | ### Address 23 | The `Address` field gives the address of the CSR where data will be written to and read from. 24 | ### Previlige mode 25 | The `Previlege mode` field tells the mode in which the CSR test is being run. 26 | ### ISA 27 | This field tells whether the ISA is `rv32` or `rv64`. It is further divided into one or more bit fields, where each bit field is represented by `field name` which tells the name of that bit field, the `description` which describes the purpose of the bit field, the `type` which tells the permission of read/write for the bit field, `reset value`, `msb` which tells the bit number of the most significant bit of the bit field and `lsb` which tells the bit number of least significant bit. 28 | 29 | ## gen_csr_test.py 30 | It generates a self-checking test. The main blocks of the code serve the following purposes: 31 | 1. `rs1` value generation which is written to the CSR. 32 | 2. Reading the value in a general-purpose register. 33 | 3. Predicting the value which will be read from `core's CSR`. This value is predicted based on the `write` and `read` masks defined in `csr_template.yaml`. 34 | 4. Comparing the predicted value with the read value. 35 | 5. An instruction generator block which calls the above-mentioned functions in order. 36 | ## Changes 37 | Changes were made in both in-use files, `csr_template.yaml` was filled taking into account the CSR implementation of `SweRV EH1` while the following code blocks were changed in `gen_csr_test.py`: 38 | 1. [Prediction function](###Prediction-function) 39 | 2. [End of test behaviour](###End-of-test-behaviour) 40 | ### Prediction function 41 | Some bits in WARL permission in CSRs can be `one` when upper bits are `zero` but setting these bits is illegal when upper bits are high. Example CSRs for `SweRV EH1` are event selector CSRs `mhpmeventx` which can take a maximum value of `0x32` or `0'b110010`, thus when bit no. 4-5 are `one` bit no. 3,4 must be `zero`. The prediction function given in the original file checks the field type and writes the given value to the complete bit field if the field is not `read-only`, so we needed to update the prediction function for the above-mentioned CSRs. 42 | ### End of test behaviour 43 | The test was going to a timeout because both the pass and fail behaviours were stuck in an infinite loop, we updated end behaviour according to SweRV EH1 testbench. 44 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv_dv_extension/nb_postfix.py: -------------------------------------------------------------------------------- 1 | # ////////////////////////////////////////////////////////////////////// 2 | # Copyright [2020] [Lampro Mellon] 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | # ////////////////////////////////////////////////////////////////////// 16 | 17 | 18 | def nb_post_fix(rtl_log_f,rtl_log,nb_log): 19 | ''' Replaces non-blocking load results in rd of trace log. 20 | Sees time/CycleCnt at which non-block load is written back to gpr, 21 | checks from that time/CycleCnt backwards, where this gpr was written in trace log, 22 | replaces the result in rd (also load) at that instruction''' 23 | 24 | nb_file = open(nb_log,"r") 25 | load_lines = nb_file.readlines() 26 | #read whole file 27 | trace_file = open(rtl_log,"r") 28 | trace_lines = trace_file.readlines() 29 | list1 = [] 30 | list2 = [] 31 | list3 = ['lb', 'lh', 'lw', 'lbu', 'lhu', 'c.lw', 'c.lwsp', 'c.ld', 'c.ldsp', 'c.lq', 'c.lqsp'] 32 | x = 1 33 | i = 1 34 | 35 | for i in range(len(load_lines)): 36 | l= load_lines[i].split() 37 | list1.append(l) 38 | for i in range(len(trace_lines)): 39 | l2 = trace_lines[i].split() 40 | list2.append(l2) 41 | #flow with trace log read as whole 42 | # find and replace the non-block load instruction reg 43 | i = 1 44 | while (x < len(load_lines)): 45 | try: 46 | t = list1[x][0] 47 | except IndexError: 48 | break 49 | if(int(list1[x][0])<=int(list2[i][0])): 50 | for a in range(i,i-20,-1): 51 | try: 52 | t = list2[a][5].split(',') 53 | except IndexError: 54 | continue 55 | try: 56 | t = list2[a][10].split(':') 57 | except IndexError: 58 | continue 59 | if(list1[x][2]==list2[a][5].split(',')[0] and (list2[a][10].split(':')[0]=="load") and (list2[a][4] in list3)): 60 | list2[a][7]=("%s=0x%s" %(list1[x][2],list1[x][3])) 61 | list2[a][10]=("load:0x%s" %(list1[x][3])) 62 | i=a+1 63 | break 64 | x+=1 65 | i+=1 66 | 67 | #update trace lines 68 | for i in range(len(trace_lines)): 69 | list2[i]='\t'.join(list2[i]) 70 | trace_lines[i]=str(list2[i]+'\n') 71 | #writing back lines 72 | nb_file = open(rtl_log_f, "w") 73 | nb_file.writelines(trace_lines) 74 | 75 | def main(): 76 | parser = argparse.ArgumentParser() 77 | parser.add_argument("--rtl_log_f", 78 | help="Output core simulation log post-fixed (default: stdout)", 79 | type=argparse.FileType('w'), 80 | default=sys.stdout) 81 | parser.add_argument("--nb_log", 82 | help="Input core simulation log (default: stdin)", 83 | type=argparse.FileType('r'), 84 | default=sys.stdin) 85 | parser.add_argument("--rtl_log", 86 | help="Input core simulation log (default: stdin)", 87 | type=argparse.FileType('r'), 88 | default=sys.stdin) 89 | 90 | args = parser.parse_args() 91 | 92 | print("Post-fix log for nonblock load values\n") 93 | nb_post_fix(args.rtl_log_f, args.rtl_log, args.nb_log) 94 | 95 | 96 | 97 | if __name__ == "__main__": 98 | main() 99 | 100 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv-target/testlists/testlist_privilege.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Google LLC 2 | # Copyright 2020 Lampro Mellon 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # ================================================================================ 17 | # Regression test list format 18 | # -------------------------------------------------------------------------------- 19 | # test : Assembly test name 20 | # description : Description of this test 21 | # gen_opts : Instruction generator options 22 | # iterations : Number of iterations of this test 23 | # no_iss : Enable/disable ISS simulator (Optional) 24 | # gen_test : Test name used by the instruction generator 25 | # asm_tests : Path to directed, hand-coded assembly test file or directory 26 | # c_tests : Path to directed, hand-coded C test file or directory 27 | # rtl_test : RTL simulation test name 28 | # cmp_opts : Compile options passed to the instruction generator 29 | # sim_opts : Simulation options passed to the instruction generator 30 | # no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) 31 | # compare_opts : Options for the RTL & ISS trace comparison 32 | # gcc_opts : gcc compile options 33 | # -------------------------------------------------------------------------------- 34 | 35 | - test: ebreak 36 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/ebreak.S 37 | iterations: 1 38 | rtl_test: core_compliance_test 39 | 40 | - test: ecall 41 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/ecall.S 42 | iterations: 1 43 | rtl_test: core_compliance_test 44 | 45 | # - test: misalign-beq-01 46 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S 47 | # iterations: 1 48 | # rtl_test: core_compliance_test 49 | 50 | # - test: misalign-bge-01 51 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bge-01.S 52 | # iterations: 1 53 | # rtl_test: core_compliance_test 54 | 55 | # - test: misalign-bgeu-01 56 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bgeu-01.S 57 | # iterations: 1 58 | # rtl_test: core_compliance_test 59 | 60 | # - test: misalign-blt-01 61 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/misalign-blt-01.S 62 | # iterations: 1 63 | # rtl_test: core_compliance_test 64 | 65 | # - test: misalign-bltu-01 66 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bltu-01.S 67 | # iterations: 1 68 | # rtl_test: core_compliance_test 69 | 70 | # - test: misalign-bne-01 71 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bne-01.S 72 | # iterations: 1 73 | # rtl_test: core_compliance_test 74 | 75 | # - test: misalign-jal-01 76 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/misalign-jal-01.S 77 | # iterations: 1 78 | # rtl_test: core_compliance_test 79 | 80 | #tests are failing due to exception. TODO: explore more why spike is failing 81 | # - test: misalign-lh-01 82 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lh-01.S 83 | # iterations: 1 84 | # rtl_test: core_compliance_test 85 | 86 | # - test: misalign-lhu-01 87 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lhu-01.S 88 | # iterations: 1 89 | # rtl_test: core_compliance_test 90 | 91 | # - test: misalign-lw-01 92 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lw-01.S 93 | # iterations: 1 94 | # rtl_test: core_compliance_test 95 | 96 | # - test: misalign-sh-01 97 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sh-01.S 98 | # iterations: 1 99 | # rtl_test: core_compliance_test 100 | 101 | # - test: misalign-sw-01 102 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sw-01.S 103 | # iterations: 1 104 | # rtl_test: core_compliance_test 105 | 106 | # - test: misalign1-jalr-01 107 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/misalign1-jalr-01.S 108 | # iterations: 1 109 | # rtl_test: core_compliance_test 110 | 111 | # - test: misalign2-jalr-01 112 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/privilege/src/misalign2-jalr-01.S 113 | # iterations: 1 114 | # rtl_test: core_compliance_test 115 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/directed_tests/asm/defines.h: -------------------------------------------------------------------------------- 1 | // NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 2 | // This is an automatically generated file by haroonshafique on Mon Aug 3 11:11:35 PKT 2020 3 | // 4 | // cmd: swerv -target=default 5 | // 6 | #define RV_XLEN 32 7 | #define RV_SERIALIO 0xd0580000 8 | #define RV_EXTERNAL_PROG 0xb0000000 9 | #define RV_UNUSED_REGION5 0x50000000 10 | #define RV_EXTERNAL_DATA 0xc0580000 11 | #define RV_DEBUG_SB_MEM 0xb0580000 12 | #define RV_UNUSED_REGION3 0x30000000 13 | #define RV_UNUSED_REGION0 0x00000000 14 | #define RV_UNUSED_REGION4 0x40000000 15 | #define RV_UNUSED_REGION7 0x70000000 16 | #define RV_UNUSED_REGION1 0x10000000 17 | #define RV_UNUSED_REGION6 0x60000000 18 | #define RV_UNUSED_REGION2 0x20000000 19 | #define RV_UNUSED_REGION9 0x90000000 20 | #define RV_EXTERNAL_DATA_1 0x00000000 21 | #define RV_IFU_BUS_TAG 3 22 | #define RV_LSU_BUS_TAG 4 23 | #define RV_DMA_BUS_TAG 1 24 | #define RV_SB_BUS_TAG 1 25 | #ifndef RV_NMI_VEC 26 | #define RV_NMI_VEC 0x11110000 27 | #endif 28 | #define RV_ICCM_RESERVED 0x1000 29 | #define RV_ICCM_ROWS 16384 30 | #define RV_ICCM_OFFSET 0xe000000 31 | #define RV_ICCM_SIZE_512 32 | #define RV_ICCM_SADR 0xee000000 33 | #define RV_ICCM_BANK_BITS 3 34 | #define RV_ICCM_NUM_BANKS_8 35 | #define RV_ICCM_SIZE 512 36 | #define RV_ICCM_EADR 0xee07ffff 37 | #define RV_ICCM_INDEX_BITS 14 38 | #define RV_ICCM_REGION 0xe 39 | #define RV_ICCM_DATA_CELL ram_16384x39 40 | #define RV_ICCM_BITS 19 41 | #define RV_ICCM_NUM_BANKS 8 42 | #define RV_PIC_SIZE 32 43 | #define RV_PIC_MPICCFG_OFFSET 0x3000 44 | #define RV_PIC_MEIE_OFFSET 0x2000 45 | #define RV_PIC_MEIGWCTRL_OFFSET 0x4000 46 | #define RV_PIC_MEIGWCLR_OFFSET 0x5000 47 | #define RV_PIC_BASE_ADDR 0xf00c0000 48 | #define RV_PIC_TOTAL_INT 8 49 | #define RV_PIC_REGION 0xf 50 | #define RV_PIC_MEIP_OFFSET 0x1000 51 | #define RV_PIC_MEIPL_OFFSET 0x0000 52 | #define RV_PIC_MEIPT_OFFSET 0x3004 53 | #define RV_PIC_TOTAL_INT_PLUS1 9 54 | #define RV_PIC_BITS 15 55 | #define RV_PIC_INT_WORDS 1 56 | #define RV_PIC_OFFSET 0xc0000 57 | #define RV_TARGET default 58 | #define RV_INST_ACCESS_ENABLE6 0x0 59 | #define RV_INST_ACCESS_ENABLE3 0x0 60 | #define RV_INST_ACCESS_MASK5 0xffffffff 61 | #define RV_DATA_ACCESS_ADDR2 0x00000000 62 | #define RV_INST_ACCESS_MASK1 0xffffffff 63 | #define RV_INST_ACCESS_MASK6 0xffffffff 64 | #define RV_INST_ACCESS_ENABLE1 0x0 65 | #define RV_INST_ACCESS_ADDR3 0x00000000 66 | #define RV_DATA_ACCESS_MASK1 0xffffffff 67 | #define RV_DATA_ACCESS_ENABLE3 0x0 68 | #define RV_INST_ACCESS_ADDR4 0x00000000 69 | #define RV_DATA_ACCESS_ENABLE1 0x0 70 | #define RV_DATA_ACCESS_MASK3 0xffffffff 71 | #define RV_DATA_ACCESS_MASK7 0xffffffff 72 | #define RV_INST_ACCESS_ENABLE5 0x0 73 | #define RV_INST_ACCESS_ENABLE7 0x0 74 | #define RV_DATA_ACCESS_ADDR3 0x00000000 75 | #define RV_INST_ACCESS_ADDR7 0x00000000 76 | #define RV_DATA_ACCESS_MASK5 0xffffffff 77 | #define RV_DATA_ACCESS_ENABLE7 0x0 78 | #define RV_INST_ACCESS_ADDR2 0x00000000 79 | #define RV_INST_ACCESS_ADDR0 0x00000000 80 | #define RV_INST_ACCESS_ADDR5 0x00000000 81 | #define RV_DATA_ACCESS_ADDR0 0x00000000 82 | #define RV_DATA_ACCESS_ENABLE4 0x0 83 | #define RV_INST_ACCESS_MASK3 0xffffffff 84 | #define RV_DATA_ACCESS_ADDR4 0x00000000 85 | #define RV_INST_ACCESS_MASK7 0xffffffff 86 | #define RV_DATA_ACCESS_ENABLE5 0x0 87 | #define RV_DATA_ACCESS_ADDR7 0x00000000 88 | #define RV_INST_ACCESS_ADDR6 0x00000000 89 | #define RV_INST_ACCESS_ENABLE4 0x0 90 | #define RV_DATA_ACCESS_MASK4 0xffffffff 91 | #define RV_DATA_ACCESS_ADDR5 0x00000000 92 | #define RV_DATA_ACCESS_ENABLE2 0x0 93 | #define RV_DATA_ACCESS_MASK6 0xffffffff 94 | #define RV_DATA_ACCESS_MASK0 0xffffffff 95 | #define RV_DATA_ACCESS_ADDR1 0x00000000 96 | #define RV_INST_ACCESS_MASK4 0xffffffff 97 | #define RV_INST_ACCESS_ENABLE2 0x0 98 | #define RV_INST_ACCESS_ADDR1 0x00000000 99 | #define RV_INST_ACCESS_MASK2 0xffffffff 100 | #define RV_DATA_ACCESS_ADDR6 0x00000000 101 | #define RV_DATA_ACCESS_ENABLE6 0x0 102 | #define RV_INST_ACCESS_ENABLE0 0x0 103 | #define RV_DATA_ACCESS_MASK2 0xffffffff 104 | #define RV_DATA_ACCESS_ENABLE0 0x0 105 | #define RV_INST_ACCESS_MASK0 0xffffffff 106 | #define RV_DCCM_RESERVED 0x1000 107 | #define RV_DCCM_INDEX_BITS 11 108 | #define RV_DCCM_ROWS 2048 109 | #define RV_DCCM_ENABLE 1 110 | #define RV_DCCM_SADR 0xf0040000 111 | #define RV_DCCM_BYTE_WIDTH 4 112 | #define RV_DCCM_WIDTH_BITS 2 113 | #define RV_DCCM_ECC_WIDTH 7 114 | #define RV_DCCM_REGION 0xf 115 | #define RV_DCCM_SIZE_64 116 | #define RV_DCCM_DATA_CELL ram_2048x39 117 | #define RV_DCCM_OFFSET 0x40000 118 | #define RV_LSU_SB_BITS 16 119 | #define RV_DCCM_DATA_WIDTH 32 120 | #define RV_DCCM_BITS 16 121 | #define RV_DCCM_FDATA_WIDTH 39 122 | #define RV_DCCM_EADR 0xf004ffff 123 | #define RV_DCCM_BANK_BITS 3 124 | #define RV_DCCM_SIZE 64 125 | #define RV_DCCM_NUM_BANKS 8 126 | #define RV_DCCM_NUM_BANKS_8 127 | #ifndef RV_RESET_VEC 128 | #define RV_RESET_VEC 0x80000000 129 | #endif 130 | #define RV_TOP `TOP.rvtop 131 | #define ASSERT_ON 132 | #define RV_STERR_ROLLBACK 0 133 | #define RV_LDERR_ROLLBACK 1 134 | #define RV_EXT_ADDRWIDTH 32 135 | #define SDVT_AHB 1 136 | #define DATAWIDTH 64 137 | #define TOP tb_top 138 | #define RV_BUILD_AXI4 1 139 | #define CLOCK_PERIOD 100 140 | #define CPU_TOP `RV_TOP.swerv 141 | #define RV_EXT_DATAWIDTH 64 142 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/directed_tests/c/defines.h: -------------------------------------------------------------------------------- 1 | // NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 2 | // This is an automatically generated file by haroonshafique on Mon Aug 3 11:11:35 PKT 2020 3 | // 4 | // cmd: swerv -target=default 5 | // 6 | #define RV_XLEN 32 7 | #define RV_SERIALIO 0xd0580000 8 | #define RV_EXTERNAL_PROG 0xb0000000 9 | #define RV_UNUSED_REGION5 0x50000000 10 | #define RV_EXTERNAL_DATA 0xc0580000 11 | #define RV_DEBUG_SB_MEM 0xb0580000 12 | #define RV_UNUSED_REGION3 0x30000000 13 | #define RV_UNUSED_REGION0 0x00000000 14 | #define RV_UNUSED_REGION4 0x40000000 15 | #define RV_UNUSED_REGION7 0x70000000 16 | #define RV_UNUSED_REGION1 0x10000000 17 | #define RV_UNUSED_REGION6 0x60000000 18 | #define RV_UNUSED_REGION2 0x20000000 19 | #define RV_UNUSED_REGION9 0x90000000 20 | #define RV_EXTERNAL_DATA_1 0x00000000 21 | #define RV_IFU_BUS_TAG 3 22 | #define RV_LSU_BUS_TAG 4 23 | #define RV_DMA_BUS_TAG 1 24 | #define RV_SB_BUS_TAG 1 25 | #ifndef RV_NMI_VEC 26 | #define RV_NMI_VEC 0x11110000 27 | #endif 28 | #define RV_ICCM_RESERVED 0x1000 29 | #define RV_ICCM_ROWS 16384 30 | #define RV_ICCM_OFFSET 0xe000000 31 | #define RV_ICCM_SIZE_512 32 | #define RV_ICCM_SADR 0xee000000 33 | #define RV_ICCM_BANK_BITS 3 34 | #define RV_ICCM_NUM_BANKS_8 35 | #define RV_ICCM_SIZE 512 36 | #define RV_ICCM_EADR 0xee07ffff 37 | #define RV_ICCM_INDEX_BITS 14 38 | #define RV_ICCM_REGION 0xe 39 | #define RV_ICCM_DATA_CELL ram_16384x39 40 | #define RV_ICCM_BITS 19 41 | #define RV_ICCM_NUM_BANKS 8 42 | #define RV_PIC_SIZE 32 43 | #define RV_PIC_MPICCFG_OFFSET 0x3000 44 | #define RV_PIC_MEIE_OFFSET 0x2000 45 | #define RV_PIC_MEIGWCTRL_OFFSET 0x4000 46 | #define RV_PIC_MEIGWCLR_OFFSET 0x5000 47 | #define RV_PIC_BASE_ADDR 0xf00c0000 48 | #define RV_PIC_TOTAL_INT 8 49 | #define RV_PIC_REGION 0xf 50 | #define RV_PIC_MEIP_OFFSET 0x1000 51 | #define RV_PIC_MEIPL_OFFSET 0x0000 52 | #define RV_PIC_MEIPT_OFFSET 0x3004 53 | #define RV_PIC_TOTAL_INT_PLUS1 9 54 | #define RV_PIC_BITS 15 55 | #define RV_PIC_INT_WORDS 1 56 | #define RV_PIC_OFFSET 0xc0000 57 | #define RV_TARGET default 58 | #define RV_INST_ACCESS_ENABLE6 0x0 59 | #define RV_INST_ACCESS_ENABLE3 0x0 60 | #define RV_INST_ACCESS_MASK5 0xffffffff 61 | #define RV_DATA_ACCESS_ADDR2 0x00000000 62 | #define RV_INST_ACCESS_MASK1 0xffffffff 63 | #define RV_INST_ACCESS_MASK6 0xffffffff 64 | #define RV_INST_ACCESS_ENABLE1 0x0 65 | #define RV_INST_ACCESS_ADDR3 0x00000000 66 | #define RV_DATA_ACCESS_MASK1 0xffffffff 67 | #define RV_DATA_ACCESS_ENABLE3 0x0 68 | #define RV_INST_ACCESS_ADDR4 0x00000000 69 | #define RV_DATA_ACCESS_ENABLE1 0x0 70 | #define RV_DATA_ACCESS_MASK3 0xffffffff 71 | #define RV_DATA_ACCESS_MASK7 0xffffffff 72 | #define RV_INST_ACCESS_ENABLE5 0x0 73 | #define RV_INST_ACCESS_ENABLE7 0x0 74 | #define RV_DATA_ACCESS_ADDR3 0x00000000 75 | #define RV_INST_ACCESS_ADDR7 0x00000000 76 | #define RV_DATA_ACCESS_MASK5 0xffffffff 77 | #define RV_DATA_ACCESS_ENABLE7 0x0 78 | #define RV_INST_ACCESS_ADDR2 0x00000000 79 | #define RV_INST_ACCESS_ADDR0 0x00000000 80 | #define RV_INST_ACCESS_ADDR5 0x00000000 81 | #define RV_DATA_ACCESS_ADDR0 0x00000000 82 | #define RV_DATA_ACCESS_ENABLE4 0x0 83 | #define RV_INST_ACCESS_MASK3 0xffffffff 84 | #define RV_DATA_ACCESS_ADDR4 0x00000000 85 | #define RV_INST_ACCESS_MASK7 0xffffffff 86 | #define RV_DATA_ACCESS_ENABLE5 0x0 87 | #define RV_DATA_ACCESS_ADDR7 0x00000000 88 | #define RV_INST_ACCESS_ADDR6 0x00000000 89 | #define RV_INST_ACCESS_ENABLE4 0x0 90 | #define RV_DATA_ACCESS_MASK4 0xffffffff 91 | #define RV_DATA_ACCESS_ADDR5 0x00000000 92 | #define RV_DATA_ACCESS_ENABLE2 0x0 93 | #define RV_DATA_ACCESS_MASK6 0xffffffff 94 | #define RV_DATA_ACCESS_MASK0 0xffffffff 95 | #define RV_DATA_ACCESS_ADDR1 0x00000000 96 | #define RV_INST_ACCESS_MASK4 0xffffffff 97 | #define RV_INST_ACCESS_ENABLE2 0x0 98 | #define RV_INST_ACCESS_ADDR1 0x00000000 99 | #define RV_INST_ACCESS_MASK2 0xffffffff 100 | #define RV_DATA_ACCESS_ADDR6 0x00000000 101 | #define RV_DATA_ACCESS_ENABLE6 0x0 102 | #define RV_INST_ACCESS_ENABLE0 0x0 103 | #define RV_DATA_ACCESS_MASK2 0xffffffff 104 | #define RV_DATA_ACCESS_ENABLE0 0x0 105 | #define RV_INST_ACCESS_MASK0 0xffffffff 106 | #define RV_DCCM_RESERVED 0x1000 107 | #define RV_DCCM_INDEX_BITS 11 108 | #define RV_DCCM_ROWS 2048 109 | #define RV_DCCM_ENABLE 1 110 | #define RV_DCCM_SADR 0xf0040000 111 | #define RV_DCCM_BYTE_WIDTH 4 112 | #define RV_DCCM_WIDTH_BITS 2 113 | #define RV_DCCM_ECC_WIDTH 7 114 | #define RV_DCCM_REGION 0xf 115 | #define RV_DCCM_SIZE_64 116 | #define RV_DCCM_DATA_CELL ram_2048x39 117 | #define RV_DCCM_OFFSET 0x40000 118 | #define RV_LSU_SB_BITS 16 119 | #define RV_DCCM_DATA_WIDTH 32 120 | #define RV_DCCM_BITS 16 121 | #define RV_DCCM_FDATA_WIDTH 39 122 | #define RV_DCCM_EADR 0xf004ffff 123 | #define RV_DCCM_BANK_BITS 3 124 | #define RV_DCCM_SIZE 64 125 | #define RV_DCCM_NUM_BANKS 8 126 | #define RV_DCCM_NUM_BANKS_8 127 | #ifndef RV_RESET_VEC 128 | #define RV_RESET_VEC 0x80000000 129 | #endif 130 | #define RV_TOP `TOP.rvtop 131 | #define ASSERT_ON 132 | #define RV_STERR_ROLLBACK 0 133 | #define RV_LDERR_ROLLBACK 1 134 | #define RV_EXT_ADDRWIDTH 32 135 | #define SDVT_AHB 1 136 | #define DATAWIDTH 64 137 | #define TOP tb_top 138 | #define RV_BUILD_AXI4 1 139 | #define CLOCK_PERIOD 100 140 | #define CPU_TOP `RV_TOP.swerv 141 | #define RV_EXT_DATAWIDTH 64 142 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/snapshots/default/defines.h: -------------------------------------------------------------------------------- 1 | // NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 2 | // This is an automatically generated file by haroonshafique on Fri Sep 25 11:31:01 PKT 2020 3 | // 4 | // cmd: swerv -target=default 5 | // 6 | #define RV_DMA_BUS_TAG 1 7 | #define RV_IFU_BUS_TAG 3 8 | #define RV_LSU_BUS_TAG 4 9 | #define RV_SB_BUS_TAG 1 10 | #define RV_ICCM_OFFSET 0xe000000 11 | #define RV_ICCM_ROWS 16384 12 | #define RV_ICCM_SIZE_512 13 | #define RV_ICCM_INDEX_BITS 14 14 | #define RV_ICCM_BITS 19 15 | #define RV_ICCM_SIZE 512 16 | #define RV_ICCM_NUM_BANKS 8 17 | #define RV_ICCM_EADR 0xee07ffff 18 | #define RV_ICCM_RESERVED 0x1000 19 | #define RV_ICCM_REGION 0xe 20 | #define RV_ICCM_SADR 0xee000000 21 | #define RV_ICCM_DATA_CELL ram_16384x39 22 | #define RV_ICCM_NUM_BANKS_8 23 | #define RV_ICCM_BANK_BITS 3 24 | #define RV_UNUSED_REGION2 0x20000000 25 | #define RV_UNUSED_REGION4 0x40000000 26 | #define RV_EXTERNAL_PROG 0xb0000000 27 | #define RV_UNUSED_REGION3 0x30000000 28 | #define RV_UNUSED_REGION9 0x90000000 29 | #define RV_EXTERNAL_DATA_1 0x00000000 30 | #define RV_UNUSED_REGION7 0x70000000 31 | #define RV_SERIALIO 0xd0580000 32 | #define RV_UNUSED_REGION5 0x50000000 33 | #define RV_DEBUG_SB_MEM 0xb0580000 34 | #define RV_UNUSED_REGION0 0x00000000 35 | #define RV_UNUSED_REGION6 0x60000000 36 | #define RV_UNUSED_REGION1 0x10000000 37 | #define RV_EXTERNAL_DATA 0xc0580000 38 | #define RV_XLEN 32 39 | #define RV_BUILD_AXI4 1 40 | #define TOP tb_top 41 | #define CPU_TOP `RV_TOP.swerv 42 | #define DATAWIDTH 64 43 | #define ASSERT_ON 44 | #define RV_EXT_ADDRWIDTH 32 45 | #define CLOCK_PERIOD 100 46 | #define RV_TOP `TOP.rvtop 47 | #define SDVT_AHB 1 48 | #define RV_EXT_DATAWIDTH 64 49 | #define RV_LDERR_ROLLBACK 1 50 | #define RV_STERR_ROLLBACK 0 51 | #define RV_TARGET default 52 | #ifndef RV_NMI_VEC 53 | #define RV_NMI_VEC 0x11110000 54 | #endif 55 | #ifndef RV_RESET_VEC 56 | #define RV_RESET_VEC 0x80000000 57 | #endif 58 | #define RV_PIC_MEIPT_COUNT 8 59 | #define RV_PIC_INT_WORDS 1 60 | #define RV_PIC_MEIPL_COUNT 8 61 | #define RV_PIC_MEIE_MASK 0x1 62 | #define RV_PIC_TOTAL_INT_PLUS1 9 63 | #define RV_PIC_SIZE 32 64 | #define RV_PIC_MEIGWCTRL_OFFSET 0x4000 65 | #define RV_PIC_MPICCFG_MASK 0x1 66 | #define RV_PIC_MEIPL_MASK 0xf 67 | #define RV_PIC_OFFSET 0xc0000 68 | #define RV_PIC_MEIP_MASK 0x0 69 | #define RV_PIC_MEIGWCLR_MASK 0x0 70 | #define RV_PIC_MEIE_OFFSET 0x2000 71 | #define RV_PIC_MEIPL_OFFSET 0x0000 72 | #define RV_PIC_BITS 15 73 | #define RV_PIC_MEIP_OFFSET 0x1000 74 | #define RV_PIC_MEIGWCTRL_MASK 0x3 75 | #define RV_PIC_MEIPT_OFFSET 0x3004 76 | #define RV_PIC_MEIPT_MASK 0x0 77 | #define RV_PIC_BASE_ADDR 0xf00c0000 78 | #define RV_PIC_MPICCFG_OFFSET 0x3000 79 | #define RV_PIC_TOTAL_INT 8 80 | #define RV_PIC_MEIE_COUNT 8 81 | #define RV_PIC_REGION 0xf 82 | #define RV_PIC_MEIGWCTRL_COUNT 8 83 | #define RV_PIC_MEIGWCLR_COUNT 8 84 | #define RV_PIC_MEIP_COUNT 4 85 | #define RV_PIC_MEIGWCLR_OFFSET 0x5000 86 | #define RV_PIC_MPICCFG_COUNT 1 87 | #define RV_DCCM_ENABLE 1 88 | #define RV_DCCM_BANK_BITS 3 89 | #define RV_DCCM_BYTE_WIDTH 4 90 | #define RV_DCCM_SIZE_64 91 | #define RV_DCCM_RESERVED 0x1000 92 | #define RV_DCCM_DATA_WIDTH 32 93 | #define RV_DCCM_BITS 16 94 | #define RV_DCCM_ROWS 2048 95 | #define RV_DCCM_EADR 0xf004ffff 96 | #define RV_DCCM_ECC_WIDTH 7 97 | #define RV_DCCM_SADR 0xf0040000 98 | #define RV_LSU_SB_BITS 16 99 | #define RV_DCCM_NUM_BANKS 8 100 | #define RV_DCCM_OFFSET 0x40000 101 | #define RV_DCCM_FDATA_WIDTH 39 102 | #define RV_DCCM_WIDTH_BITS 2 103 | #define RV_DCCM_REGION 0xf 104 | #define RV_DCCM_DATA_CELL ram_2048x39 105 | #define RV_DCCM_NUM_BANKS_8 106 | #define RV_DCCM_INDEX_BITS 11 107 | #define RV_DCCM_SIZE 64 108 | #define RV_INST_ACCESS_ADDR4 0x00000000 109 | #define RV_DATA_ACCESS_ADDR5 0x00000000 110 | #define RV_DATA_ACCESS_ENABLE7 0x0 111 | #define RV_INST_ACCESS_MASK1 0xffffffff 112 | #define RV_DATA_ACCESS_MASK4 0xffffffff 113 | #define RV_DATA_ACCESS_ADDR7 0x00000000 114 | #define RV_INST_ACCESS_ENABLE7 0x0 115 | #define RV_INST_ACCESS_ENABLE4 0x0 116 | #define RV_DATA_ACCESS_ENABLE5 0x0 117 | #define RV_INST_ACCESS_ADDR3 0x00000000 118 | #define RV_DATA_ACCESS_ADDR0 0x00000000 119 | #define RV_DATA_ACCESS_MASK3 0xffffffff 120 | #define RV_INST_ACCESS_ADDR0 0x00000000 121 | #define RV_DATA_ACCESS_ADDR2 0x00000000 122 | #define RV_DATA_ACCESS_ENABLE2 0x0 123 | #define RV_INST_ACCESS_ENABLE5 0x0 124 | #define RV_INST_ACCESS_ENABLE2 0x0 125 | #define RV_DATA_ACCESS_MASK6 0xffffffff 126 | #define RV_DATA_ACCESS_ENABLE4 0x0 127 | #define RV_DATA_ACCESS_ENABLE0 0x0 128 | #define RV_DATA_ACCESS_ADDR4 0x00000000 129 | #define RV_INST_ACCESS_ENABLE6 0x0 130 | #define RV_DATA_ACCESS_ADDR1 0x00000000 131 | #define RV_INST_ACCESS_MASK4 0xffffffff 132 | #define RV_DATA_ACCESS_ENABLE3 0x0 133 | #define RV_DATA_ACCESS_MASK2 0xffffffff 134 | #define RV_INST_ACCESS_MASK0 0xffffffff 135 | #define RV_DATA_ACCESS_ENABLE1 0x0 136 | #define RV_DATA_ACCESS_ENABLE6 0x0 137 | #define RV_INST_ACCESS_ADDR6 0x00000000 138 | #define RV_DATA_ACCESS_MASK0 0xffffffff 139 | #define RV_INST_ACCESS_MASK5 0xffffffff 140 | #define RV_INST_ACCESS_MASK7 0xffffffff 141 | #define RV_DATA_ACCESS_MASK7 0xffffffff 142 | #define RV_INST_ACCESS_ENABLE1 0x0 143 | #define RV_INST_ACCESS_ADDR5 0x00000000 144 | #define RV_INST_ACCESS_MASK3 0xffffffff 145 | #define RV_INST_ACCESS_ADDR7 0x00000000 146 | #define RV_INST_ACCESS_MASK2 0xffffffff 147 | #define RV_DATA_ACCESS_ADDR6 0x00000000 148 | #define RV_INST_ACCESS_ENABLE0 0x0 149 | #define RV_INST_ACCESS_ADDR1 0x00000000 150 | #define RV_INST_ACCESS_MASK6 0xffffffff 151 | #define RV_DATA_ACCESS_MASK1 0xffffffff 152 | #define RV_INST_ACCESS_ADDR2 0x00000000 153 | #define RV_DATA_ACCESS_ADDR3 0x00000000 154 | #define RV_DATA_ACCESS_MASK5 0xffffffff 155 | #define RV_INST_ACCESS_ENABLE3 0x0 156 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv_dv_extension/testlist.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Google LLC 2 | # Copyright 2020 Lampro Mellon 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # ================================================================================ 17 | # Regression test list format 18 | # -------------------------------------------------------------------------------- 19 | # test : Assembly test name 20 | # description : Description of this test 21 | # gen_opts : Instruction generator options 22 | # iterations : Number of iterations of this test 23 | # no_iss : Enable/disable ISS simulator (Optional) 24 | # gen_test : Test name used by the instruction generator 25 | # asm_tests : Path to directed, hand-coded assembly test file or directory 26 | # c_tests : Path to directed, hand-coded C test file or directory 27 | # rtl_test : RTL simulation test name 28 | # cmp_opts : Compile options passed to the instruction generator 29 | # sim_opts : Simulation options passed to the instruction generator 30 | # no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) 31 | # compare_opts : Options for the RTL & ISS trace comparison 32 | # gcc_opts : gcc compile options 33 | # -------------------------------------------------------------------------------- 34 | 35 | - test: cmark 36 | c_tests: directed_tests/c/cmark.c 37 | gcc_opts: -g -O3 -funroll-all-loops 38 | iterations: 1 39 | rtl_test: core_base_test_benchmark 40 | no_iss: 1 41 | no_post_compare: 1 42 | 43 | - test: cmark_iccm 44 | c_tests: directed_tests/c/cmark_iccm.c 45 | gcc_opts: -g -O3 -funroll-all-loops 46 | iterations: 1 47 | rtl_test: core_base_test_benchmark 48 | no_iss: 1 49 | no_post_compare: 1 50 | 51 | - test: hello_world 52 | asm_tests: directed_tests/asm/hello_world.s 53 | iterations: 1 54 | rtl_test: core_base_test_benchmark 55 | no_iss: 1 56 | no_post_compare: 1 57 | 58 | - test: hello_world_dccm 59 | asm_tests: directed_tests/asm/hello_world_dccm.s 60 | iterations: 1 61 | rtl_test: core_base_test_benchmark 62 | no_iss: 1 63 | no_post_compare: 1 64 | 65 | - test: riscv_arithmetic_basic_test 66 | description: > 67 | Arithmetic instruction test, no load/store/branch instructions 68 | gen_opts: > 69 | +instr_cnt=2000 70 | +num_of_sub_program=0 71 | +directed_instr_0=riscv_int_numeric_corner_stream,4 72 | +no_fence=1 73 | +no_data_page=1 74 | +no_branch_jump=1 75 | +boot_mode=m 76 | +no_csr_instr=1 77 | iterations: 2 78 | gen_test: riscv_instr_base_test 79 | rtl_test: core_base_test 80 | 81 | - test: riscv_load_store_instr_dccm_test 82 | description: > 83 | Random instruction stress test 84 | iterations: 2 85 | gen_test: riscv_instr_base_test 86 | gen_opts: > 87 | +instr_cnt=1000 88 | +num_of_sub_program=0 89 | +directed_instr_0=riscv_load_store_rand_instr_stream,4 90 | rtl_test: core_base_test 91 | 92 | - test: riscv_rand_instr_test 93 | description: > 94 | Random instruction stress test 95 | iterations: 2 96 | gen_test: riscv_instr_base_test 97 | gen_opts: > 98 | +instr_cnt=5000 99 | +num_of_sub_program=5 100 | +directed_instr_0=riscv_load_store_rand_instr_stream,4 101 | +directed_instr_1=riscv_loop_instr,4 102 | +directed_instr_2=riscv_hazard_instr_stream,4 103 | +directed_instr_3=riscv_load_store_hazard_instr_stream,4 104 | +directed_instr_4=riscv_multi_page_load_store_instr_stream,4 105 | +directed_instr_5=riscv_mem_region_stress_test,4 106 | +directed_instr_6=riscv_jal_instr,4 107 | rtl_test: core_base_test 108 | 109 | - test: riscv_jump_stress_test 110 | description: > 111 | Stress back-to-back jump instruction test 112 | iterations: 2 113 | gen_test: riscv_instr_base_test 114 | gen_opts: > 115 | +instr_cnt=5000 116 | +num_of_sub_program=5 117 | +directed_instr_1=riscv_jal_instr,20 118 | rtl_test: core_base_test 119 | 120 | - test: riscv_loop_test 121 | description: > 122 | Random instruction stress test 123 | iterations: 2 124 | gen_test: riscv_instr_base_test 125 | gen_opts: > 126 | +instr_cnt=10000 127 | +num_of_sub_program=5 128 | +directed_instr_1=riscv_loop_instr,20 129 | rtl_test: core_base_test 130 | 131 | - test: riscv_rand_jump_test 132 | description: > 133 | Jump among large number of sub-programs, stress testing iTLB operations. 134 | iterations: 2 135 | gen_test: riscv_instr_base_test 136 | gen_opts: > 137 | +instr_cnt=10000 138 | +num_of_sub_program=10 139 | +directed_instr_0=riscv_load_store_rand_instr_stream,8 140 | rtl_test: core_base_test 141 | 142 | # Please enable this test for your RTL simulation 143 | - test: riscv_csr_test 144 | description: > 145 | Test all CSR instructions on all implemented CSR registers 146 | iterations: 1 147 | no_iss: 1 148 | rtl_test: core_csr_test 149 | no_post_compare: 1 150 | 151 | - test: riscv_exceptions_test 152 | description: > 153 | Random instruction test with complete interrupt handling 154 | iterations: 1 155 | gen_test: riscv_rand_instr_test 156 | gen_opts: > 157 | +gen_exceptions=1 158 | rtl_test: core_base_test 159 | sim_opts: > 160 | +enable_irq_seq=1 161 | no_post_compare: 1 162 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv-target/testlists/testlist_C.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Google LLC 2 | # Copyright 2020 Lampro Mellon 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # ================================================================================ 17 | # Regression test list format 18 | # -------------------------------------------------------------------------------- 19 | # test : Assembly test name 20 | # description : Description of this test 21 | # gen_opts : Instruction generator options 22 | # iterations : Number of iterations of this test 23 | # no_iss : Enable/disable ISS simulator (Optional) 24 | # gen_test : Test name used by the instruction generator 25 | # asm_tests : Path to directed, hand-coded assembly test file or directory 26 | # c_tests : Path to directed, hand-coded C test file or directory 27 | # rtl_test : RTL simulation test name 28 | # cmp_opts : Compile options passed to the instruction generator 29 | # sim_opts : Simulation options passed to the instruction generator 30 | # no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) 31 | # compare_opts : Options for the RTL & ISS trace comparison 32 | # gcc_opts : gcc compile options 33 | # -------------------------------------------------------------------------------- 34 | 35 | - test: cadd-01 36 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cadd-01.S 37 | iterations: 1 38 | rtl_test: core_compliance_test 39 | 40 | - test: caddi-01 41 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/caddi-01.S 42 | iterations: 1 43 | rtl_test: core_compliance_test 44 | 45 | - test: caddi4spn-01 46 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/caddi4spn-01.S 47 | iterations: 1 48 | rtl_test: core_compliance_test 49 | 50 | - test: caddi16sp-01 51 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/caddi16sp-01.S 52 | iterations: 1 53 | rtl_test: core_compliance_test 54 | 55 | - test: cand-01 56 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cand-01.S 57 | iterations: 1 58 | rtl_test: core_compliance_test 59 | 60 | - test: candi-01 61 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/candi-01.S 62 | iterations: 1 63 | rtl_test: core_compliance_test 64 | 65 | - test: cbeqz-01 66 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cbeqz-01.S 67 | iterations: 1 68 | rtl_test: core_compliance_test 69 | 70 | - test: cbnez-01 71 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cbnez-01.S 72 | iterations: 1 73 | rtl_test: core_compliance_test 74 | 75 | # - test: cebreak-01 76 | # asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cebreak-01.S 77 | # iterations: 1 78 | # rtl_test: core_compliance_test 79 | 80 | - test: cj-01 81 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cj-01.S 82 | iterations: 1 83 | rtl_test: core_compliance_test 84 | 85 | - test: cjal-01 86 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cjal-01.S 87 | iterations: 1 88 | rtl_test: core_compliance_test 89 | 90 | - test: cjalr-01 91 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cjalr-01.S 92 | iterations: 1 93 | rtl_test: core_compliance_test 94 | 95 | - test: cjr-01 96 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cjr-01.S 97 | iterations: 1 98 | rtl_test: core_compliance_test 99 | 100 | - test: cli-01 101 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cli-01.S 102 | iterations: 1 103 | rtl_test: core_compliance_test 104 | 105 | - test: clui-01 106 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/clui-01.S 107 | iterations: 1 108 | rtl_test: core_compliance_test 109 | 110 | - test: clw-01 111 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/clw-01.S 112 | iterations: 1 113 | rtl_test: core_compliance_test 114 | 115 | - test: clwsp-01 116 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/clwsp-01.S 117 | iterations: 1 118 | rtl_test: core_compliance_test 119 | 120 | - test: cmv-01 121 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cmv-01.S 122 | iterations: 1 123 | rtl_test: core_compliance_test 124 | 125 | - test: cnop-01 126 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cnop-01.S 127 | iterations: 1 128 | rtl_test: core_compliance_test 129 | 130 | - test: cor-01 131 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cor-01.S 132 | iterations: 1 133 | rtl_test: core_compliance_test 134 | 135 | - test: cslli-01 136 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cslli-01.S 137 | iterations: 1 138 | rtl_test: core_compliance_test 139 | 140 | - test: csrai-01 141 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/csrai-01.S 142 | iterations: 1 143 | rtl_test: core_compliance_test 144 | 145 | - test: csrli-01 146 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/csrli-01.S 147 | iterations: 1 148 | rtl_test: core_compliance_test 149 | 150 | - test: csub-01 151 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/csub-01.S 152 | iterations: 1 153 | rtl_test: core_compliance_test 154 | 155 | - test: csw-01 156 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/csw-01.S 157 | iterations: 1 158 | rtl_test: core_compliance_test 159 | 160 | - test: cswsp-01 161 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cswsp-01.S 162 | iterations: 1 163 | rtl_test: core_compliance_test 164 | 165 | - test: cxor-01 166 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/C/src/cxor-01.S 167 | iterations: 1 168 | rtl_test: core_compliance_test 169 | -------------------------------------------------------------------------------- /scripts/core_integrate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # 3 | # ////////////////////////////////////////////////////////////////////// 4 | # Copyright [2020] [Lampro Mellon] 5 | # 6 | # Licensed under the Apache License, Version 2.0 (the "License"); 7 | # you may not use this file except in compliance with the License. 8 | # You may obtain a copy of the License at 9 | # 10 | # http://www.apache.org/licenses/LICENSE-2.0 11 | # 12 | # Unless required by applicable law or agreed to in writing, software 13 | # distributed under the License is distributed on an "AS IS" BASIS, 14 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | # See the License for the specific language governing permissions and 16 | # limitations under the License. 17 | # ////////////////////////////////////////////////////////////////////// 18 | 19 | SCRIPT_PATH=$( dirname "${BASH_SOURCE[0]}") 20 | BASE_DIR=$(cd ${SCRIPT_PATH}; cd ..; pwd) 21 | echo "BASE_DIR = ${BASE_DIR}" 22 | 23 | RV_DV_REMOTE='https://github.com/google/riscv-dv.git' 24 | RV_DV_COMMIT_SHA='0b625258549e733082c12e5dc749f05aefb07d5a' 25 | 26 | SWERV_REMOTE='https://github.com/chipsalliance/Cores-SweRV.git' 27 | SWERV_COMMIT_SHA='7332edc0adaa7e9a0c842d169154429e8d987786' 28 | 29 | RC_REMOTE='https://github.com/riscv/riscv-compliance.git' 30 | RC_COMMIT_SHA='0e77784916ed9c07842883ba6c62db2555a8335f' 31 | 32 | CORES="${BASE_DIR}/cores" 33 | INTEGRATED_CORES="${BASE_DIR}/integrated_cores" 34 | INTEGRATION_FILES="${BASE_DIR}/integration_files" 35 | RV_DV="${BASE_DIR}/google_riscv_dv" 36 | 37 | SWERV_LOCAL="${CORES}/SweRV_EH1" 38 | RC_LOCAL="${BASE_DIR}/riscv-compliance" 39 | 40 | 41 | # Clone RISCV-DV if it does not exist 42 | printf "Checking for RISCV-DV with COMMIT ID: ${RV_DV_COMMIT_SHA} ...\n\n" 43 | if [ -d "${RV_DV}" ] && [ -d "${RV_DV}/.git" ] 44 | then 45 | printf "${RV_DV}/ is already a git repository \n" 46 | cd ${RV_DV} 47 | RV_DV_SHA_OUTPUT=$(git log -1 --pretty=format:"%H") 48 | else 49 | printf "${RV_DV}/ is not a git repository \n" 50 | RV_DV_SHA_OUTPUT="-1" 51 | fi 52 | 53 | if [ ${RV_DV_SHA_OUTPUT} != ${RV_DV_COMMIT_SHA} ] 54 | then 55 | git clone ${RV_DV_REMOTE} ${RV_DV} 56 | cd ${RV_DV} 57 | pip3 install -r requirements.txt 58 | git checkout ${RV_DV_COMMIT_SHA} 59 | else 60 | printf "HEAD of ${RV_DV} is already at ${RV_DV_COMMIT_SHA}! \n\n" 61 | fi 62 | 63 | 64 | # # Clone SweRV EH-1 if it does not exist 65 | printf "Checking for SweRV EH-1 with COMMIT ID: ${SWERV_COMMIT_SHA} ...\n\n" 66 | if [ -d "${SWERV_LOCAL}" ] && [ -d "${SWERV_LOCAL}/.git" ] 67 | then 68 | printf "${SWERV_LOCAL}/ is already a git repository \n" 69 | cd ${SWERV_LOCAL} 70 | SWERV_SHA_OUTPUT=$(git log -1 --pretty=format:"%H") 71 | else 72 | printf "${SWERV_LOCAL}/ is not a git repository \n" 73 | SWERV_SHA_OUTPUT="-1" 74 | fi 75 | 76 | if [ ${SWERV_SHA_OUTPUT} != ${SWERV_COMMIT_SHA} ] 77 | then 78 | git clone ${SWERV_REMOTE} ${SWERV_LOCAL}; 79 | cd ${SWERV_LOCAL}; 80 | git checkout ${SWERV_COMMIT_SHA}; 81 | else 82 | printf "HEAD of ${SWERV_LOCAL} is already at ${SWERV_COMMIT_SHA}! \n\n" 83 | fi 84 | 85 | # # Clone riscv-compliance if it does not exist 86 | printf "Checking for SweRV EH-1 with COMMIT ID: ${RC_COMMIT_SHA} ...\n\n" 87 | if [ -d "${RC_LOCAL}" ] && [ -d "${RC_LOCAL}/.git" ] 88 | then 89 | printf "${RC_LOCAL}/ is already a git repository \n" 90 | cd ${RC_LOCAL} 91 | RC_SHA_OUTPUT=$(git log -1 --pretty=format:"%H") 92 | else 93 | printf "${RC_LOCAL}/ is not a git repository \n" 94 | RC_SHA_OUTPUT="-1" 95 | fi 96 | 97 | if [ ${RC_SHA_OUTPUT} != ${RC_COMMIT_SHA} ] 98 | then 99 | git clone ${RC_REMOTE} ${RC_LOCAL}; 100 | cd ${RC_LOCAL}; 101 | git checkout ${RC_COMMIT_SHA}; 102 | else 103 | printf "HEAD of ${RC_LOCAL} is already at ${RC_COMMIT_SHA}! \n\n" 104 | fi 105 | 106 | # Environment Setup for SweRV EH-1 107 | printf "Setting up the Environment for SweRV EH-1 core in integrated_cores/SweRV_EH1 ...\n"; 108 | 109 | rm -rf "${INTEGRATED_CORES}/SweRV_EH1/" 110 | cp -r "${INTEGRATION_FILES}/SweRV_EH1" "${INTEGRATED_CORES}/SweRV_EH1"; 111 | rm -rf "${INTEGRATED_CORES}/SweRV_EH1/google_riscv_dv/" 112 | cp -r "${INTEGRATION_FILES}/SweRV_EH1/testbench" "${INTEGRATED_CORES}/SweRV_EH1/"; 113 | cp -r "${CORES}/SweRV_EH1/design" "${INTEGRATED_CORES}/SweRV_EH1/rtl/"; 114 | 115 | # TODO: Check for files before renaming 116 | mv "${RV_DV}/src/riscv_instr_gen_config.sv" "${RV_DV}/src/default_riscv_instr_gen_config.sv"; 117 | mv "${RV_DV}/src/riscv_asm_program_gen.sv" "${RV_DV}/src/default_riscv_asm_program_gen.sv"; 118 | mv "${RV_DV}/scripts/gen_csr_test.py" "${RV_DV}/scripts/default_gen_csr_test.py"; 119 | #mv "${RV_DV}/scripts/spike_log_to_trace_csv.py" "${RV_DV}/scripts/default_spike_log_to_trace_csv.py"; 120 | mv "${RV_DV}/scripts/instr_trace_compare.py" "${RV_DV}/scripts/default_instr_trace_compare.py"; 121 | 122 | cp "${INTEGRATION_FILES}/SweRV_EH1/google_riscv_dv/lm_run.py" "${RV_DV}/"; 123 | cp "${INTEGRATION_FILES}/SweRV_EH1/google_riscv_dv/lm_cov.py" "${RV_DV}/"; 124 | cp "${INTEGRATION_FILES}/SweRV_EH1/google_riscv_dv/src/riscv_instr_gen_config.sv" "${RV_DV}/src/"; 125 | cp "${INTEGRATION_FILES}/SweRV_EH1/google_riscv_dv/src/riscv_asm_program_gen.sv" "${RV_DV}/src/"; 126 | cp "${INTEGRATION_FILES}/SweRV_EH1/google_riscv_dv/scripts/gen_csr_test.py" "${RV_DV}/scripts/"; 127 | cp "${INTEGRATION_FILES}/SweRV_EH1/google_riscv_dv/riscv_instr_base_test.py" "${RV_DV}/pygen/pygen_src/test/"; 128 | #cp "${INTEGRATION_FILES}/SweRV_EH1/google_riscv_dv/scripts/spike_log_to_trace_csv.py" "${RV_DV}/scripts/"; 129 | cp "${INTEGRATION_FILES}/SweRV_EH1/google_riscv_dv/scripts/instr_trace_compare.py" "${RV_DV}/scripts/"; 130 | 131 | # Setup SweRV-EH1 with riscv-compliance files 132 | cp -r "${RC_LOCAL}/riscv-test-suite" "${INTEGRATED_CORES}/SweRV_EH1/directed_tests/"; 133 | cp -r "${RC_LOCAL}/riscv-test-env" "${INTEGRATED_CORES}/SweRV_EH1/snapshots/default/"; 134 | cp "${RC_LOCAL}/riscv-test-env/arch_test.h" "${INTEGRATED_CORES}/SweRV_EH1/snapshots/default/"; 135 | cp "${RC_LOCAL}/riscv-test-env/encoding.h" "${INTEGRATED_CORES}/SweRV_EH1/snapshots/default/"; 136 | cp -r "${INTEGRATION_FILES}/SweRV_EH1/riscv-target/model_test.h" "${INTEGRATED_CORES}/SweRV_EH1/snapshots/default/"; 137 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv_dv_extension/riscv_core_setting.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2019 Google LLC 3 | * Copyright 2020 Lampro Mellon 4 | * 5 | * Licensed under the Apache License, Version 2.0 (the "License"); 6 | * you may not use this file except in compliance with the License. 7 | * You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | */ 17 | 18 | //----------------------------------------------------------------------------- 19 | // Processor feature configuration 20 | //----------------------------------------------------------------------------- 21 | // XLEN 22 | parameter int XLEN = 32; 23 | 24 | // Parameter for SATP mode, set to BARE if address translation is not supported 25 | parameter satp_mode_t SATP_MODE = BARE; 26 | 27 | // Supported Privileged mode 28 | privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE}; 29 | 30 | // Unsupported instructions 31 | riscv_instr_name_t unsupported_instr[]; 32 | 33 | // ISA supported by the processor 34 | riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C}; //To do (Amna): Add RV32C after fixing post compare for RV32C 35 | 36 | // Interrupt mode support 37 | mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED}; 38 | 39 | // The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is 40 | // supported 41 | int max_interrupt_vector_num = 16; 42 | 43 | // Physical memory protection support 44 | bit support_pmp = 0; 45 | 46 | // Debug mode support 47 | bit support_debug_mode = 0; 48 | 49 | // Support delegate trap to user mode 50 | bit support_umode_trap = 0; 51 | 52 | // Support sfence.vma instruction 53 | bit support_sfence = 0; 54 | 55 | // Support unaligned load/store 56 | bit support_unaligned_load_store = 1'b1; 57 | 58 | // GPR setting 59 | parameter int NUM_FLOAT_GPR = 32; 60 | parameter int NUM_GPR = 32; 61 | parameter int NUM_VEC_GPR = 32; 62 | 63 | // ---------------------------------------------------------------------------- 64 | // Vector extension configuration | Not implemented in SweRV-EH1 65 | // ---------------------------------------------------------------------------- 66 | 67 | // Parameter for vector extension 68 | parameter int VECTOR_EXTENSION_ENABLE = 0; 69 | 70 | parameter int VLEN = 512; 71 | 72 | // Maximum size of a single vector element 73 | parameter int ELEN = 32; 74 | 75 | // Minimum size of a sub-element, which must be at most 8-bits. 76 | parameter int SELEN = 8; 77 | 78 | // Maximum size of a single vector element (encoded in vsew format) 79 | parameter int VELEN = int'($ln(ELEN)/$ln(2)) - 3; 80 | 81 | // Maxium LMUL supported by the core 82 | parameter int MAX_LMUL = 8; 83 | 84 | // ---------------------------------------------------------------------------- 85 | // Multi-harts configuration 86 | // ---------------------------------------------------------------------------- 87 | 88 | // Number of harts 89 | parameter int NUM_HARTS = 1; 90 | 91 | // ---------------------------------------------------------------------------- 92 | // Previleged CSR implementation 93 | // ---------------------------------------------------------------------------- 94 | 95 | // Implemented previlieged CSR list 96 | `ifdef DSIM 97 | privileged_reg_t implemented_csr[] = { 98 | `else 99 | const privileged_reg_t implemented_csr[] = { 100 | `endif 101 | // Machine mode mode CSR 102 | MVENDORID, // Vendor ID 103 | MARCHID, // Architecture ID 104 | MIMPID, // Implementation ID 105 | MHARTID, // Hardware thread ID 106 | MISA, // ISA and extensions 107 | 108 | MSTATUS, // Machine status 109 | MIE, // Machine interrupt-enable register 110 | MTVEC, // Machine trap-handler base address 111 | MSCRATCH, // Scratch register for machine trap handlers 112 | MEPC, // Machine exception program counter 113 | MCAUSE, // Machine trap cause 114 | MTVAL, // Machine bad address or instruction 115 | MIP, // Machine interrupt pending 116 | 117 | MCYCLE, // Machine cycle counter 118 | MCYCLEH, // Upper 32 bits of mcycle, RV32I only 119 | MINSTRET, // Machine instructions-retired counter 120 | MINSTRETH, // Upper 32 bits of minstret, RV32I only 121 | 122 | MHPMEVENT3, // Machine performance-monitoring event selector 3 123 | MHPMEVENT4, // Machine performance-monitoring event selector 4 124 | MHPMEVENT5, // Machine performance-monitoring event selector 5 125 | MHPMEVENT6, // Machine performance-monitoring event selector 6 126 | 127 | MHPMCOUNTER3, // Machine performance-monitoring counter 3 128 | MHPMCOUNTER4, // Machine performance-monitoring counter 4 129 | MHPMCOUNTER5, // Machine performance-monitoring counter 5 130 | MHPMCOUNTER6, // Machine performance-monitoring counter 6 131 | 132 | MHPMCOUNTER3H, // Upper 32 bits of mhpmcounter3, RV32I only 133 | MHPMCOUNTER4H, // Upper 32 bits of mhpmcounter4, RV32I only 134 | MHPMCOUNTER5H, // Upper 32 bits of mhpmcounter5, RV32I only 135 | MHPMCOUNTER6H // Upper 32 bits of mhpmcounter6, RV32I only 136 | }; 137 | 138 | // Implementation-specific custom CSRs 139 | `ifdef DSIM 140 | bit [11:0] custom_csr[] = { 141 | `else 142 | const bit [11:0] custom_csr[] = { 143 | `endif 144 | }; 145 | 146 | // ---------------------------------------------------------------------------- 147 | // Supported interrupt/exception setting, used for functional coverage 148 | // ---------------------------------------------------------------------------- 149 | 150 | `ifdef DSIM 151 | interrupt_cause_t implemented_interrupt[] = { 152 | `else 153 | const interrupt_cause_t implemented_interrupt[] = { 154 | `endif 155 | M_TIMER_INTR, 156 | M_EXTERNAL_INTR 157 | }; 158 | 159 | `ifdef DSIM 160 | exception_cause_t implemented_exception[] = { 161 | `else 162 | const exception_cause_t implemented_exception[] = { 163 | `endif 164 | INSTRUCTION_ACCESS_FAULT, 165 | ILLEGAL_INSTRUCTION, 166 | BREAKPOINT, 167 | LOAD_ADDRESS_MISALIGNED, 168 | LOAD_ACCESS_FAULT, 169 | STORE_AMO_ADDRESS_MISALIGNED, 170 | STORE_AMO_ACCESS_FAULT, 171 | ECALL_MMODE 172 | }; 173 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Overview 2 | 3 | LM RISC-V DV is a verification environment which integrates [SweRV EH-1 Core](https://github.com/chipsalliance/Cores-SweRV) from Western Digital and a random assembly test generator from [RISCV-DV](https://github.com/google/riscv-dv) which is a SV/UVM based instructions generator. This is a work in progress. At present it supports: 4 | 5 | - RTL Compilation 6 | - Random Assembly Test Generation 7 | - Test Compilation (Random, Directed) 8 | - RTL Simulation 9 | - Spike ISS Simulation 10 | - Post-simulation Comparison with ISS (Spike) 11 | - Code Coverage Report Generation 12 | - Extraction of Functional Coverage 13 | 14 | You can watch the [**Youtube playlist**](https://www.youtube.com/watch?v=I8ISkRhPA5M&list=PLLBoDLOd3AMSHjz4mMJsWfSNV-TZBWArQ) about an [**Introduction to LM RISC-V DV**](https://www.youtube.com/watch?v=I8ISkRhPA5M&t=1s) and its [**Detailed Environment Demo**](https://www.youtube.com/watch?v=Pu-si58uosA&t=3s). 15 | 16 | [LM RISC-V DV Thumbnail](https://www.youtube.com/watch?v=I8ISkRhPA5M&list=PLLBoDLOd3AMSHjz4mMJsWfSNV-TZBWArQ) 17 | 18 | 19 | ## Directory Structure 20 | 21 | ```bash 22 | ├── cores/ 23 | ├── docs/ 24 | ├── google_riscv_dv/ 25 | ├── integrated_cores/ 26 | ├── integration_files/ 27 | │   └── SweRV_EH1/ 28 | │   ├── directed_tests/ 29 | │   ├── google_riscv_dv/ 30 | │   ├── riscv_dv_extension/ 31 | │   ├── snapshots/ 32 | │   ├── testbench/ 33 | │   ├── yaml/ 34 | │   ├── cover.cfg 35 | │   ├── Makefile 36 | │   ├── sim.py 37 | │   ├── SweRV_EH1_flist.f 38 | │   └── waves.tcl 39 | └── scripts/ 40 | ├── core_integrate.sh 41 | └── toolchain_paths.sh 42 | ``` 43 | 44 | ### [cores](./cores)/ 45 | 46 | This directory is a place holder which will contain the cores in their original source forms cloned from their sites. Currently, LM RISC-V DV has been set up and tested for SweRV EH-1 core. When the cores are cloned, they will be checked out to the most recent versions which have been tested in this environment. 47 | 48 | ### [docs](./docs)/ 49 | 50 | This directory is dedicated to all the documentation related to directory structure and environment flow. It also contains documentation for tests which are generated for a specific core. 51 | 52 | ### [google_riscv_dv](./google_riscv_dv)/ 53 | 54 | RISCV-DV is cloned into this repository. It contains the source for random assembly test generator written in SystemVerilog/UVM. 55 | 56 | ### [integrated_cores](./integrated_cores)/ 57 | 58 | After the cores and RISCV-DV are cloned into their respective directories, the verification environment for the cores will be set up here with each core in its separate directory. 59 | 60 | ### [integration files](./integration_files)/ 61 | 62 | This directory contains files which will be used in setting up the verification environment. It contains: 63 | 64 | - Makefiles, python scripts, YAML files, linker files, and core configuration files 65 | - Modified RISCV-DV files specific for cores 66 | - Modified RTL and Testbench files related to cores 67 | 68 | ### [scripts](./scripts)/ 69 | 70 | All the scripts for setting up the repository and core integration will be placed in this directory. At present, it contains two scripts. 71 | 72 | - [core_integrate.sh](./scripts/core_integrate.sh) 73 | - [toolchain_paths.sh](./scripts/toolchain_paths.sh) 74 | 75 | ## Pre-Requisites 76 | 77 | Following are the requirements for running the test generator and environment. 78 | 79 | - RISC-V GNU Toolchain 80 | - Instruction Set Simulator ISS (Spike) 81 | - Python 3 82 | - SV and UVM 1.2 Simulator 83 | 84 | For manually building the `RISC-V GNU Toolchain`, visit the [riscv-gnu-toolchain](https://github.com/riscv/riscv-gnu-toolchain) repository on Github. Pre-built toolchains can be downloaded from [SiFive Software](https://www.sifive.com/software) Page. We are using `Spike ISS` for LM RISC-V DV. It can be manually built from the source which can be obtained from [riscv-isa-sim](https://github.com/riscv/riscv-isa-sim) repository. `Python 3.7` or above is recommended for the python scripts to work properly for test generation, compilation and simulation. According to RISCV-DV Documentation, a number of `simulators` has been verified with the test generator including Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO. 85 | 86 | ## Setup 87 | 88 | After the `RISC-V GNU toolchain` and `Spike` (or any other RISC-V ISS) are installed, their installation paths should be added to the `~/.bashrc` file in `RISCV_PATH` and `SPIKE_PATH` (or path variable corresponding to installed ISS) variables respectively. Following is the sample of paths to be added on a ubuntu OS. 89 | 90 | ```bash 91 | export RISCV_PATH = /riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14 92 | export SPIKE_PATH = 93 | ``` 94 | 95 | Their is a [toolchain_paths.sh](./scripts/toolchain_paths.sh) script in [scripts/](./scripts) directory. You need to `source` it after exporting the above paths in the `~/.bashrc` file as 96 | 97 | ```bash 98 | source 99 | ``` 100 | 101 | ## Integration of Core with RISCV-DV 102 | 103 | [core_integrate.sh](./scripts/core_integrate.sh) is a `bash` script placed in [scripts/](./scripts). You just simply need to run the script through terminal for setting up the environment for the core. 104 | 105 | ```bash 106 | ./core_integrate.sh 107 | ``` 108 | 109 | When the script is run, it: 110 | 111 | - clones the cores (SweRV EH-1 for now) and RISCV-DV into their respective folders 112 | - checkouts the sources to the lastest tested commit versions 113 | - takes the required RTL and Testbench sources from [cores](./cores) and integration files, and set up the environment in [integrated_cores](./integrated_cores) 114 | 115 | Currently, only SweRV EH-1 has been integrated. It will thus set up the environment for the SweRV EH-1 core only. 116 | 117 | ## Contribution 118 | 119 | This is a work in progress. We'd like to accept your contributions to this project. 120 | 121 | ## Acknowledgement 122 | 123 | - [RISCV-DV](https://github.com/google/riscv-dv) 124 | - [SweRV EH-1 Core (Western Digital)](https://github.com/chipsalliance/Cores-SweRV) 125 | - [Ibex core (lowRISC)](https://github.com/lowRISC/ibex) 126 | 127 | ## Contact 128 | 129 | If you have any queries, feel free to contact us at hardware@lampromellon.com or contact page on our site [Lampro Mellon](http://www.lampromellon.com). 130 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/snapshots/default/common_defines.vh: -------------------------------------------------------------------------------- 1 | // NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 2 | // This is an automatically generated file by haroonshafique on Fri Sep 25 11:31:01 PKT 2020 3 | // 4 | // cmd: swerv -target=default 5 | // 6 | `define RV_DMA_BUS_TAG 1 7 | `define RV_IFU_BUS_TAG 3 8 | `define RV_LSU_BUS_TAG 4 9 | `define RV_SB_BUS_TAG 1 10 | `define RV_ICCM_OFFSET 10'he000000 11 | `define RV_ICCM_ROWS 16384 12 | `define RV_ICCM_SIZE_512 13 | `define RV_ICCM_INDEX_BITS 14 14 | `define RV_ICCM_BITS 19 15 | `define RV_ICCM_SIZE 512 16 | `define RV_ICCM_NUM_BANKS 8 17 | `define RV_ICCM_EADR 32'hee07ffff 18 | `define RV_ICCM_RESERVED 'h1000 19 | `define RV_ICCM_REGION 4'he 20 | `define RV_ICCM_SADR 32'hee000000 21 | `define RV_ICCM_DATA_CELL ram_16384x39 22 | `define RV_ICCM_NUM_BANKS_8 23 | `define RV_ICCM_BANK_BITS 3 24 | `define RV_BHT_ADDR_LO 4 25 | `define RV_BHT_GHR_RANGE 4:0 26 | `define RV_BHT_SIZE 128 27 | `define RV_BHT_ADDR_HI 7 28 | `define RV_BHT_HASH_STRING {ghr[3:2] ^ {ghr[3+1], {4-1-2{1'b0} } },hashin[5:4]^ghr[2-1:0]} 29 | `define RV_BHT_ARRAY_DEPTH 16 30 | `define RV_BHT_GHR_PAD2 fghr[4:3],2'b0 31 | `define RV_BHT_GHR_SIZE 5 32 | `define RV_BHT_GHR_PAD fghr[4],3'b0 33 | `define RV_UNUSED_REGION2 'h20000000 34 | `define RV_UNUSED_REGION4 'h40000000 35 | `define RV_EXTERNAL_PROG 'hb0000000 36 | `define RV_UNUSED_REGION3 'h30000000 37 | `define RV_UNUSED_REGION9 'h90000000 38 | `define RV_EXTERNAL_DATA_1 'h00000000 39 | `define RV_UNUSED_REGION7 'h70000000 40 | `define RV_SERIALIO 'hd0580000 41 | `define RV_UNUSED_REGION5 'h50000000 42 | `define RV_DEBUG_SB_MEM 'hb0580000 43 | `define RV_UNUSED_REGION0 'h00000000 44 | `define RV_UNUSED_REGION6 'h60000000 45 | `define RV_UNUSED_REGION1 'h10000000 46 | `define RV_EXTERNAL_DATA 'hc0580000 47 | `define RV_XLEN 32 48 | `define RV_RET_STACK_SIZE 4 49 | `define TEC_RV_ICG clockhdr 50 | `define RV_BTB_ADDR_LO 4 51 | `define RV_BTB_INDEX1_LO 4 52 | `define RV_BTB_INDEX3_HI 9 53 | `define RV_BTB_SIZE 32 54 | `define RV_BTB_BTAG_FOLD 1 55 | `define RV_BTB_INDEX2_LO 6 56 | `define RV_BTB_ARRAY_DEPTH 4 57 | `define RV_BTB_INDEX2_HI 7 58 | `define RV_BTB_ADDR_HI 5 59 | `define RV_BTB_BTAG_SIZE 9 60 | `define RV_BTB_INDEX1_HI 5 61 | `define RV_BTB_INDEX3_LO 8 62 | `define RV_NUMIREGS 32 63 | `define RV_ICACHE_TAG_DEPTH 64 64 | `define RV_ICACHE_TAG_CELL ram_64x21 65 | `define RV_ICACHE_IC_DEPTH 8 66 | `define RV_ICACHE_DATA_CELL ram_256x34 67 | `define RV_ICACHE_SIZE 16 68 | `define RV_ICACHE_TAG_HIGH 12 69 | `define RV_ICACHE_IC_INDEX 8 70 | `define RV_ICACHE_TAG_LOW 6 71 | `define RV_ICACHE_ENABLE 1 72 | `define RV_ICACHE_TADDR_HIGH 5 73 | `define RV_ICACHE_IC_ROWS 256 74 | `define RV_BUILD_AXI4 1 75 | `define TOP tb_top 76 | `define CPU_TOP `RV_TOP.swerv 77 | `define DATAWIDTH 64 78 | `define ASSERT_ON 79 | `define RV_EXT_ADDRWIDTH 32 80 | `define CLOCK_PERIOD 100 81 | `define RV_TOP `TOP.rvtop 82 | `define SDVT_AHB 1 83 | `define RV_EXT_DATAWIDTH 64 84 | `define RV_LDERR_ROLLBACK 1 85 | `define RV_STERR_ROLLBACK 0 86 | `define RV_TARGET default 87 | `define RV_NMI_VEC 'h11110000 88 | `define REGWIDTH 32 89 | `define RV_RESET_VEC 'h80000000 90 | `define RV_DMA_BUF_DEPTH 4 91 | `define RV_FPGA_OPTIMIZE 1 92 | `define RV_LSU_NUM_NBLOAD 8 93 | `define RV_LSU_NUM_NBLOAD_WIDTH 3 94 | `define RV_LSU_STBUF_DEPTH 8 95 | `define RV_DEC_INSTBUF_DEPTH 4 96 | `define RV_PIC_MEIPT_COUNT 8 97 | `define RV_PIC_INT_WORDS 1 98 | `define RV_PIC_MEIPL_COUNT 8 99 | `define RV_PIC_MEIE_MASK 'h1 100 | `define RV_PIC_TOTAL_INT_PLUS1 9 101 | `define RV_PIC_SIZE 32 102 | `define RV_PIC_MEIGWCTRL_OFFSET 'h4000 103 | `define RV_PIC_MPICCFG_MASK 'h1 104 | `define RV_PIC_MEIPL_MASK 'hf 105 | `define RV_PIC_OFFSET 10'hc0000 106 | `define RV_PIC_MEIP_MASK 'h0 107 | `define RV_PIC_MEIGWCLR_MASK 'h0 108 | `define RV_PIC_MEIE_OFFSET 'h2000 109 | `define RV_PIC_MEIPL_OFFSET 'h0000 110 | `define RV_PIC_BITS 15 111 | `define RV_PIC_MEIP_OFFSET 'h1000 112 | `define RV_PIC_MEIGWCTRL_MASK 'h3 113 | `define RV_PIC_MEIPT_OFFSET 'h3004 114 | `define RV_PIC_MEIPT_MASK 'h0 115 | `define RV_PIC_BASE_ADDR 32'hf00c0000 116 | `define RV_PIC_MPICCFG_OFFSET 'h3000 117 | `define RV_PIC_TOTAL_INT 8 118 | `define RV_PIC_MEIE_COUNT 8 119 | `define RV_PIC_REGION 4'hf 120 | `define RV_PIC_MEIGWCTRL_COUNT 8 121 | `define RV_PIC_MEIGWCLR_COUNT 8 122 | `define RV_PIC_MEIP_COUNT 4 123 | `define RV_PIC_MEIGWCLR_OFFSET 'h5000 124 | `define RV_PIC_MPICCFG_COUNT 1 125 | `define RV_DCCM_ENABLE 1 126 | `define RV_DCCM_BANK_BITS 3 127 | `define RV_DCCM_BYTE_WIDTH 4 128 | `define RV_DCCM_SIZE_64 129 | `define RV_DCCM_RESERVED 'h1000 130 | `define RV_DCCM_DATA_WIDTH 32 131 | `define RV_DCCM_BITS 16 132 | `define RV_DCCM_ROWS 2048 133 | `define RV_DCCM_EADR 32'hf004ffff 134 | `define RV_DCCM_ECC_WIDTH 7 135 | `define RV_DCCM_SADR 32'hf0040000 136 | `define RV_LSU_SB_BITS 16 137 | `define RV_DCCM_NUM_BANKS 8 138 | `define RV_DCCM_OFFSET 28'h40000 139 | `define RV_DCCM_FDATA_WIDTH 39 140 | `define RV_DCCM_WIDTH_BITS 2 141 | `define RV_DCCM_REGION 4'hf 142 | `define RV_DCCM_DATA_CELL ram_2048x39 143 | `define RV_DCCM_NUM_BANKS_8 144 | `define RV_DCCM_INDEX_BITS 11 145 | `define RV_DCCM_SIZE 64 146 | `define RV_INST_ACCESS_ADDR4 'h00000000 147 | `define RV_DATA_ACCESS_ADDR5 'h00000000 148 | `define RV_DATA_ACCESS_ENABLE7 1'h0 149 | `define RV_INST_ACCESS_MASK1 'hffffffff 150 | `define RV_DATA_ACCESS_MASK4 'hffffffff 151 | `define RV_DATA_ACCESS_ADDR7 'h00000000 152 | `define RV_INST_ACCESS_ENABLE7 1'h0 153 | `define RV_INST_ACCESS_ENABLE4 1'h0 154 | `define RV_DATA_ACCESS_ENABLE5 1'h0 155 | `define RV_INST_ACCESS_ADDR3 'h00000000 156 | `define RV_DATA_ACCESS_ADDR0 'h00000000 157 | `define RV_DATA_ACCESS_MASK3 'hffffffff 158 | `define RV_INST_ACCESS_ADDR0 'h00000000 159 | `define RV_DATA_ACCESS_ADDR2 'h00000000 160 | `define RV_DATA_ACCESS_ENABLE2 1'h0 161 | `define RV_INST_ACCESS_ENABLE5 1'h0 162 | `define RV_INST_ACCESS_ENABLE2 1'h0 163 | `define RV_DATA_ACCESS_MASK6 'hffffffff 164 | `define RV_DATA_ACCESS_ENABLE4 1'h0 165 | `define RV_DATA_ACCESS_ENABLE0 1'h0 166 | `define RV_DATA_ACCESS_ADDR4 'h00000000 167 | `define RV_INST_ACCESS_ENABLE6 1'h0 168 | `define RV_DATA_ACCESS_ADDR1 'h00000000 169 | `define RV_INST_ACCESS_MASK4 'hffffffff 170 | `define RV_DATA_ACCESS_ENABLE3 1'h0 171 | `define RV_DATA_ACCESS_MASK2 'hffffffff 172 | `define RV_INST_ACCESS_MASK0 'hffffffff 173 | `define RV_DATA_ACCESS_ENABLE1 1'h0 174 | `define RV_DATA_ACCESS_ENABLE6 1'h0 175 | `define RV_INST_ACCESS_ADDR6 'h00000000 176 | `define RV_DATA_ACCESS_MASK0 'hffffffff 177 | `define RV_INST_ACCESS_MASK5 'hffffffff 178 | `define RV_INST_ACCESS_MASK7 'hffffffff 179 | `define RV_DATA_ACCESS_MASK7 'hffffffff 180 | `define RV_INST_ACCESS_ENABLE1 1'h0 181 | `define RV_INST_ACCESS_ADDR5 'h00000000 182 | `define RV_INST_ACCESS_MASK3 'hffffffff 183 | `define RV_INST_ACCESS_ADDR7 'h00000000 184 | `define RV_INST_ACCESS_MASK2 'hffffffff 185 | `define RV_DATA_ACCESS_ADDR6 'h00000000 186 | `define RV_INST_ACCESS_ENABLE0 1'h0 187 | `define RV_INST_ACCESS_ADDR1 'h00000000 188 | `define RV_INST_ACCESS_MASK6 'hffffffff 189 | `define RV_DATA_ACCESS_MASK1 'hffffffff 190 | `define RV_INST_ACCESS_ADDR2 'h00000000 191 | `define RV_DATA_ACCESS_ADDR3 'h00000000 192 | `define RV_DATA_ACCESS_MASK5 'hffffffff 193 | `define RV_INST_ACCESS_ENABLE3 1'h0 194 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/snapshots/default/common_defines_verilator.vh: -------------------------------------------------------------------------------- 1 | // NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 2 | // This is an automatically generated file by amnafayyaz on Wed Jan 13 18:05:15 PKT 2021 3 | // 4 | // cmd: swerv -target=default 5 | // 6 | `define RV_LSU_BUS_TAG 4 7 | `define RV_SB_BUS_TAG 1 8 | `define RV_IFU_BUS_TAG 3 9 | `define RV_DMA_BUS_TAG 1 10 | `define REGWIDTH 32 11 | `define RV_INST_ACCESS_ENABLE6 1'h0 12 | `define RV_DATA_ACCESS_ENABLE6 1'h0 13 | `define RV_DATA_ACCESS_ENABLE3 1'h0 14 | `define RV_DATA_ACCESS_ENABLE0 1'h0 15 | `define RV_INST_ACCESS_ADDR4 'h00000000 16 | `define RV_DATA_ACCESS_ADDR6 'h00000000 17 | `define RV_INST_ACCESS_ADDR6 'h00000000 18 | `define RV_DATA_ACCESS_ENABLE4 1'h0 19 | `define RV_DATA_ACCESS_ADDR3 'h00000000 20 | `define RV_INST_ACCESS_MASK7 'hffffffff 21 | `define RV_DATA_ACCESS_ADDR4 'h00000000 22 | `define RV_DATA_ACCESS_ENABLE7 1'h0 23 | `define RV_DATA_ACCESS_ADDR1 'h00000000 24 | `define RV_INST_ACCESS_ENABLE1 1'h0 25 | `define RV_DATA_ACCESS_MASK0 'hffffffff 26 | `define RV_DATA_ACCESS_ADDR5 'h00000000 27 | `define RV_INST_ACCESS_MASK3 'hffffffff 28 | `define RV_INST_ACCESS_ADDR0 'h00000000 29 | `define RV_INST_ACCESS_MASK5 'hffffffff 30 | `define RV_DATA_ACCESS_MASK2 'hffffffff 31 | `define RV_INST_ACCESS_MASK0 'hffffffff 32 | `define RV_DATA_ACCESS_ENABLE5 1'h0 33 | `define RV_INST_ACCESS_MASK2 'hffffffff 34 | `define RV_INST_ACCESS_MASK6 'hffffffff 35 | `define RV_INST_ACCESS_ADDR1 'h00000000 36 | `define RV_DATA_ACCESS_MASK3 'hffffffff 37 | `define RV_INST_ACCESS_ENABLE3 1'h0 38 | `define RV_DATA_ACCESS_ENABLE1 1'h0 39 | `define RV_INST_ACCESS_ADDR2 'h00000000 40 | `define RV_INST_ACCESS_ENABLE0 1'h0 41 | `define RV_DATA_ACCESS_MASK7 'hffffffff 42 | `define RV_DATA_ACCESS_MASK4 'hffffffff 43 | `define RV_DATA_ACCESS_MASK6 'hffffffff 44 | `define RV_DATA_ACCESS_ADDR7 'h00000000 45 | `define RV_DATA_ACCESS_ADDR0 'h00000000 46 | `define RV_INST_ACCESS_ADDR3 'h00000000 47 | `define RV_INST_ACCESS_ENABLE4 1'h0 48 | `define RV_INST_ACCESS_ADDR5 'h00000000 49 | `define RV_INST_ACCESS_ENABLE2 1'h0 50 | `define RV_INST_ACCESS_ENABLE5 1'h0 51 | `define RV_INST_ACCESS_MASK4 'hffffffff 52 | `define RV_INST_ACCESS_ADDR7 'h00000000 53 | `define RV_DATA_ACCESS_MASK1 'hffffffff 54 | `define RV_INST_ACCESS_MASK1 'hffffffff 55 | `define RV_INST_ACCESS_ENABLE7 1'h0 56 | `define RV_DATA_ACCESS_ADDR2 'h00000000 57 | `define RV_DATA_ACCESS_ENABLE2 1'h0 58 | `define RV_DATA_ACCESS_MASK5 'hffffffff 59 | `define RV_FPGA_OPTIMIZE 1 60 | `define RV_DEC_INSTBUF_DEPTH 4 61 | `define RV_LSU_STBUF_DEPTH 8 62 | `define RV_DMA_BUF_DEPTH 4 63 | `define RV_LSU_NUM_NBLOAD 8 64 | `define RV_LSU_NUM_NBLOAD_WIDTH 3 65 | `define RV_TARGET default 66 | `define RV_RESET_VEC 'h80000000 67 | `define RV_XLEN 32 68 | `define RV_UNUSED_REGION6 'h60000000 69 | `define RV_EXTERNAL_PROG 'hb0000000 70 | `define RV_UNUSED_REGION0 'h00000000 71 | `define RV_UNUSED_REGION4 'h40000000 72 | `define RV_UNUSED_REGION9 'h90000000 73 | `define RV_UNUSED_REGION5 'h50000000 74 | `define RV_EXTERNAL_DATA 'hc0580000 75 | `define RV_SERIALIO 'hd0580000 76 | `define RV_DEBUG_SB_MEM 'hb0580000 77 | `define RV_UNUSED_REGION3 'h30000000 78 | `define RV_UNUSED_REGION7 'h70000000 79 | `define RV_UNUSED_REGION1 'h10000000 80 | `define RV_UNUSED_REGION2 'h20000000 81 | `define RV_EXTERNAL_DATA_1 'h00000000 82 | `define RV_ICCM_NUM_BANKS_8 83 | `define RV_ICCM_BITS 19 84 | `define RV_ICCM_SADR 32'hee000000 85 | `define RV_ICCM_DATA_CELL ram_16384x39 86 | `define RV_ICCM_INDEX_BITS 14 87 | `define RV_ICCM_BANK_BITS 3 88 | `define RV_ICCM_RESERVED 'h1000 89 | `define RV_ICCM_ROWS 16384 90 | `define RV_ICCM_REGION 4'he 91 | `define RV_ICCM_SIZE_512 92 | `define RV_ICCM_EADR 32'hee07ffff 93 | `define RV_ICCM_OFFSET 10'he000000 94 | `define RV_ICCM_SIZE 512 95 | `define RV_ICCM_NUM_BANKS 8 96 | `define RV_NUMIREGS 32 97 | `define TEC_RV_ICG clockhdr 98 | `define RV_BHT_GHR_SIZE 5 99 | `define RV_BHT_ARRAY_DEPTH 16 100 | `define RV_BHT_GHR_RANGE 4:0 101 | `define RV_BHT_GHR_PAD fghr[4],3'b0 102 | `define RV_BHT_ADDR_LO 4 103 | `define RV_BHT_HASH_STRING {ghr[3:2] ^ {ghr[3+1], {4-1-2{1'b0} } },hashin[5:4]^ghr[2-1:0]} 104 | `define RV_BHT_SIZE 128 105 | `define RV_BHT_GHR_PAD2 fghr[4:3],2'b0 106 | `define RV_BHT_ADDR_HI 7 107 | `define TOP tb_top 108 | `define RV_STERR_ROLLBACK 0 109 | `define RV_TOP `TOP.rvtop 110 | `define ASSERT_ON 111 | `define RV_LDERR_ROLLBACK 1 112 | `define CLOCK_PERIOD 100 113 | `define RV_EXT_DATAWIDTH 64 114 | `define RV_EXT_ADDRWIDTH 32 115 | `define SDVT_AHB 1 116 | `define CPU_TOP `RV_TOP.swerv 117 | `define RV_BUILD_AXI4 1 118 | `define DATAWIDTH 64 119 | `define RV_ICACHE_ENABLE 1 120 | `define RV_ICACHE_SIZE 16 121 | `define RV_ICACHE_IC_DEPTH 8 122 | `define RV_ICACHE_DATA_CELL ram_256x34 123 | `define RV_ICACHE_IC_ROWS 256 124 | `define RV_ICACHE_IC_INDEX 8 125 | `define RV_ICACHE_TAG_HIGH 12 126 | `define RV_ICACHE_TAG_LOW 6 127 | `define RV_ICACHE_TAG_CELL ram_64x21 128 | `define RV_ICACHE_TAG_DEPTH 64 129 | `define RV_ICACHE_TADDR_HIGH 5 130 | `define RV_DCCM_EADR 32'hf004ffff 131 | `define RV_DCCM_SIZE_64 132 | `define RV_DCCM_ENABLE 1 133 | `define RV_DCCM_BANK_BITS 3 134 | `define RV_DCCM_NUM_BANKS 8 135 | `define RV_DCCM_ROWS 2048 136 | `define RV_DCCM_DATA_CELL ram_2048x39 137 | `define RV_DCCM_BITS 16 138 | `define RV_DCCM_SADR 32'hf0040000 139 | `define RV_DCCM_FDATA_WIDTH 39 140 | `define RV_DCCM_RESERVED 'h1000 141 | `define RV_DCCM_NUM_BANKS_8 142 | `define RV_DCCM_DATA_WIDTH 32 143 | `define RV_DCCM_WIDTH_BITS 2 144 | `define RV_DCCM_REGION 4'hf 145 | `define RV_DCCM_BYTE_WIDTH 4 146 | `define RV_DCCM_OFFSET 28'h40000 147 | `define RV_DCCM_ECC_WIDTH 7 148 | `define RV_DCCM_INDEX_BITS 11 149 | `define RV_DCCM_SIZE 64 150 | `define RV_LSU_SB_BITS 16 151 | `define RV_NMI_VEC 'h11110000 152 | `define RV_BTB_INDEX2_LO 6 153 | `define RV_BTB_ARRAY_DEPTH 4 154 | `define RV_BTB_BTAG_SIZE 9 155 | `define RV_BTB_SIZE 32 156 | `define RV_BTB_INDEX2_HI 7 157 | `define RV_BTB_INDEX1_HI 5 158 | `define RV_BTB_ADDR_LO 4 159 | `define RV_BTB_INDEX3_HI 9 160 | `define RV_BTB_BTAG_FOLD 1 161 | `define RV_BTB_INDEX3_LO 8 162 | `define RV_BTB_INDEX1_LO 4 163 | `define RV_BTB_ADDR_HI 5 164 | `define RV_PIC_MEIP_MASK 'h0 165 | `define RV_PIC_MPICCFG_OFFSET 'h3000 166 | `define RV_PIC_INT_WORDS 1 167 | `define RV_PIC_BASE_ADDR 32'hf00c0000 168 | `define RV_PIC_MEIE_MASK 'h1 169 | `define RV_PIC_MEIP_COUNT 4 170 | `define RV_PIC_MEIGWCTRL_MASK 'h3 171 | `define RV_PIC_MEIGWCLR_COUNT 8 172 | `define RV_PIC_MEIE_OFFSET 'h2000 173 | `define RV_PIC_MPICCFG_COUNT 1 174 | `define RV_PIC_TOTAL_INT 8 175 | `define RV_PIC_REGION 4'hf 176 | `define RV_PIC_MEIGWCTRL_COUNT 8 177 | `define RV_PIC_MEIPL_MASK 'hf 178 | `define RV_PIC_MEIPT_OFFSET 'h3004 179 | `define RV_PIC_MEIGWCTRL_OFFSET 'h4000 180 | `define RV_PIC_SIZE 32 181 | `define RV_PIC_MPICCFG_MASK 'h1 182 | `define RV_PIC_MEIE_COUNT 8 183 | `define RV_PIC_MEIPT_MASK 'h0 184 | `define RV_PIC_BITS 15 185 | `define RV_PIC_MEIGWCLR_OFFSET 'h5000 186 | `define RV_PIC_MEIPL_OFFSET 'h0000 187 | `define RV_PIC_MEIGWCLR_MASK 'h0 188 | `define RV_PIC_OFFSET 10'hc0000 189 | `define RV_PIC_MEIPT_COUNT 8 190 | `define RV_PIC_MEIPL_COUNT 8 191 | `define RV_PIC_MEIP_OFFSET 'h1000 192 | `define RV_PIC_TOTAL_INT_PLUS1 9 193 | `define RV_RET_STACK_SIZE 4 194 | `undef ASSERT_ON 195 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/testbench/ahb_sif.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: Apache-2.0 2 | // Copyright 2019 Western Digital Corporation or its affiliates. 3 | // Copyright 2020 Lampro Mellon 4 | // 5 | // Licensed under the Apache License, Version 2.0 (the "License"); 6 | // you may not use this file except in compliance with the License. 7 | // You may obtain a copy of the License at 8 | // 9 | // http://www.apache.org/licenses/LICENSE-2.0 10 | // 11 | // Unless required by applicable law or agreed to in writing, software 12 | // distributed under the License is distributed on an "AS IS" BASIS, 13 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | // See the License for the specific language governing permissions and 15 | // limitations under the License. 16 | // 17 | `ifdef RV_BUILD_AHB_LITE 18 | 19 | module ahb_sif ( 20 | input logic [63:0] HWDATA, 21 | input logic HCLK, 22 | input logic HSEL, 23 | input logic [3:0] HPROT, 24 | input logic HWRITE, 25 | input logic [1:0] HTRANS, 26 | input logic [2:0] HSIZE, 27 | input logic HREADY, 28 | input logic HRESETn, 29 | input logic [31:0] HADDR, 30 | input logic [2:0] HBURST, 31 | 32 | output logic HREADYOUT, 33 | output logic HRESP, 34 | output logic [63:0] HRDATA 35 | ); 36 | 37 | parameter MAILBOX_ADDR = 32'hD0580000; 38 | 39 | logic write; 40 | logic [31:0] laddr, addr; 41 | logic [7:0] strb_lat; 42 | logic [63:0] rdata; 43 | 44 | bit [7:0] mem [bit[31:0]]; 45 | bit [7:0] wscnt; 46 | int dws = 0; 47 | int iws = 0; 48 | bit dws_rand; 49 | bit iws_rand; 50 | bit ok; 51 | 52 | // Wires 53 | wire [63:0] WriteData = HWDATA; 54 | wire [7:0] strb = HSIZE == 3'b000 ? 8'h1 << HADDR[2:0] : 55 | HSIZE == 3'b001 ? 8'h3 << {HADDR[2:1],1'b0} : 56 | HSIZE == 3'b010 ? 8'hf << {HADDR[2],2'b0} : 8'hff; 57 | 58 | 59 | wire mailbox_write = write && laddr==MAILBOX_ADDR; 60 | 61 | 62 | initial begin 63 | if ($value$plusargs("iws=%d", iws)); 64 | if ($value$plusargs("dws=%d", dws)); 65 | dws_rand = dws < 0; 66 | iws_rand = iws < 0; 67 | end 68 | 69 | 70 | 71 | always @ (negedge HCLK ) begin 72 | if(HREADY) 73 | addr = HADDR; 74 | if (write & HREADY) begin 75 | if(strb_lat[7]) mem[{laddr[31:3],3'd7}] = HWDATA[63:56]; 76 | if(strb_lat[6]) mem[{laddr[31:3],3'd6}] = HWDATA[55:48]; 77 | if(strb_lat[5]) mem[{laddr[31:3],3'd5}] = HWDATA[47:40]; 78 | if(strb_lat[4]) mem[{laddr[31:3],3'd4}] = HWDATA[39:32]; 79 | if(strb_lat[3]) mem[{laddr[31:3],3'd3}] = HWDATA[31:24]; 80 | if(strb_lat[2]) mem[{laddr[31:3],3'd2}] = HWDATA[23:16]; 81 | if(strb_lat[1]) mem[{laddr[31:3],3'd1}] = HWDATA[15:08]; 82 | if(strb_lat[0]) mem[{laddr[31:3],3'd0}] = HWDATA[07:00]; 83 | end 84 | if(HREADY & HSEL & |HTRANS) begin 85 | `ifdef VERILATOR 86 | if(iws_rand & ~HPROT[0]) 87 | iws = $random & 15; 88 | if(dws_rand & HPROT[0]) 89 | dws = $random & 15; 90 | `else 91 | if(iws_rand & ~HPROT[0]) 92 | ok = std::randomize(iws) with {iws dist {0:=10, [1:3]:/2, [4:15]:/1};}; 93 | if(dws_rand & HPROT[0]) 94 | ok = std::randomize(dws) with {dws dist {0:=10, [1:3]:/2, [4:15]:/1};}; 95 | `endif 96 | end 97 | end 98 | 99 | 100 | assign HRDATA = HREADY ? rdata : ~rdata; 101 | assign HREADYOUT = wscnt == 0; 102 | assign HRESP = 0; 103 | 104 | always @(posedge HCLK or negedge HRESETn) begin 105 | if(~HRESETn) begin 106 | laddr <= 32'b0; 107 | write <= 1'b0; 108 | rdata <= '0; 109 | wscnt <= 0; 110 | end 111 | else begin 112 | if(HREADY & HSEL) begin 113 | laddr <= HADDR; 114 | write <= HWRITE & |HTRANS; 115 | if(|HTRANS & ~HWRITE) 116 | rdata <= {mem[{addr[31:3],3'd7}], 117 | mem[{addr[31:3],3'd6}], 118 | mem[{addr[31:3],3'd5}], 119 | mem[{addr[31:3],3'd4}], 120 | mem[{addr[31:3],3'd3}], 121 | mem[{addr[31:3],3'd2}], 122 | mem[{addr[31:3],3'd1}], 123 | mem[{addr[31:3],3'd0}]}; 124 | strb_lat <= strb; 125 | end 126 | end 127 | if(HREADY & HSEL & |HTRANS) 128 | wscnt <= HPROT[0] ? dws[7:0] : iws[7:0]; 129 | else if(wscnt != 0) 130 | wscnt <= wscnt-1; 131 | end 132 | 133 | 134 | endmodule 135 | `endif 136 | 137 | `ifdef RV_BUILD_AXI4 138 | module axi_slv #(TAGW=1) ( 139 | input aclk, 140 | input rst_l, 141 | input arvalid, 142 | output reg arready, 143 | input [31:0] araddr, 144 | input [TAGW-1:0] arid, 145 | input [7:0] arlen, 146 | input [1:0] arburst, 147 | input [2:0] arsize, 148 | 149 | output reg rvalid, 150 | input rready, 151 | output reg [63:0] rdata, 152 | output reg [1:0] rresp, 153 | output reg [TAGW-1:0] rid, 154 | output rlast, 155 | 156 | input awvalid, 157 | output awready, 158 | input [31:0] awaddr, 159 | input [TAGW-1:0] awid, 160 | input [7:0] awlen, 161 | input [1:0] awburst, 162 | input [2:0] awsize, 163 | 164 | input [63:0] wdata, 165 | input [7:0] wstrb, 166 | input wvalid, 167 | output wready, 168 | 169 | output reg bvalid, 170 | input bready, 171 | output reg [1:0] bresp, 172 | output reg [TAGW-1:0] bid 173 | ); 174 | 175 | parameter MAILBOX_ADDR = 32'hD0580000; 176 | parameter MEM_SIZE_DW = 8192; 177 | 178 | bit [7:0] mem [bit[31:0]]; 179 | bit [63:0] memdata; 180 | wire [63:0] WriteData; 181 | wire mailbox_write; 182 | 183 | 184 | assign mailbox_write = awvalid && awaddr==MAILBOX_ADDR && rst_l; 185 | assign WriteData = wdata; 186 | 187 | always @ ( posedge aclk or negedge rst_l) begin 188 | if(!rst_l) begin 189 | rvalid <= 0; 190 | bvalid <= 0; 191 | end 192 | else begin 193 | bid <= awid; 194 | rid <= arid; 195 | rvalid <= arvalid; 196 | bvalid <= awvalid; 197 | rdata <= memdata; 198 | end 199 | end 200 | 201 | always @ ( negedge aclk) begin 202 | if(arvalid) memdata <= {mem[araddr+7], mem[araddr+6], mem[araddr+5], mem[araddr+4], 203 | mem[araddr+3], mem[araddr+2], mem[araddr+1], mem[araddr]}; 204 | if(awvalid) begin 205 | if(wstrb[7]) mem[awaddr+7] = wdata[63:56]; 206 | if(wstrb[6]) mem[awaddr+6] = wdata[55:48]; 207 | if(wstrb[5]) mem[awaddr+5] = wdata[47:40]; 208 | if(wstrb[4]) mem[awaddr+4] = wdata[39:32]; 209 | if(wstrb[3]) mem[awaddr+3] = wdata[31:24]; 210 | if(wstrb[2]) mem[awaddr+2] = wdata[23:16]; 211 | if(wstrb[1]) mem[awaddr+1] = wdata[15:08]; 212 | if(wstrb[0]) mem[awaddr+0] = wdata[07:00]; 213 | end 214 | end 215 | 216 | 217 | assign arready = 1'b1; 218 | assign awready = 1'b1; 219 | assign wready = 1'b1; 220 | assign rresp = 2'b0; 221 | assign bresp = 2'b0; 222 | assign rlast = 1'b1; 223 | 224 | endmodule 225 | `endif 226 | 227 | -------------------------------------------------------------------------------- /docs/SweRV_setup_with_RVDV.md: -------------------------------------------------------------------------------- 1 | # SweRV Environment Setup with Google's RISCV-DV 2 | 3 | This document briefly highlights the directory structure and files used in integration of SweRV EH1 with Google RISC-V DV. 4 | 5 | ## Directory Structure 6 | 7 | Following is the directory structure of integrated SweRV EH1 core with Google RISC-V DV. 8 | 9 | ``` 10 | SweRV_EH1 11 | ├── directed_tests/ 12 | ├── riscv_dv_extension/ 13 | │   ├── riscv_core_setting.sv 14 | │   └── testlist.yaml 15 | ├── rtl/ 16 | ├── snapshots/ 17 | ├── testbench/ 18 | ├── yaml/ 19 | │   └── rtl_simulation.yaml 20 | ├── cover.cfg 21 | ├── Makefile 22 | ├── sim.py 23 | ├── SweRV_EH1_flist.f 24 | └── waves.tcl 25 | ``` 26 | 27 | ### directed_tests/ 28 | 29 | This directory will contain directed tests to be run on the core. Assembly tests are placed in `asm/` sub-directory whereas C tests are placed in `c/`. The purpose of these two subdirectories is to just keep the directory structure clean and consistent. 30 | 31 | ### riscv_dv_extension/ 32 | 33 | This directory contains atleast two files which are used by RISCV-DV. These files provide customization according to the core we are integrating with RISCV-DV. 34 | 35 | `riscv_core_setting.sv` contains all of the necessary configurations related to core. For example register lengths, supported instruction extensions, unsupported instructions, supported CSRs, types of exceptions and interrupts etc. Update this file according to core features. 36 | 37 | `testlist.yaml` contains list of all the tests needed to be run on SweRV core using RISCV-DV. Following are the options that can be set depending on the test. 38 | 39 | ```yaml 40 | # -------------------------------------------------------------------------------- 41 | # test : Assembly test name 42 | # description : Description of this test 43 | # gen_opts : Instruction generator options 44 | # iterations : Number of iterations of this test 45 | # no_iss : Enable/disable ISS simulator (Optional) 46 | # gen_test : Test name used by the instruction generator 47 | # asm_tests : Path to directed, hand-coded assembly test file or directory 48 | # c_tests : Path to directed, hand-coded C test file or directory 49 | # rtl_test : RTL simulation test name 50 | # cmp_opts : Compile options passed to the instruction generator 51 | # sim_opts : Simulation options passed to the instruction generator 52 | # no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) 53 | # compare_opts : Options for the RTL & ISS trace comparison 54 | # gcc_opts : gcc compile options 55 | # -------------------------------------------------------------------------------- 56 | ``` 57 | 58 | For using a random assembly test e.g `riscv_basic_arithmetic_test`, test is added into the yaml file as follows: 59 | 60 | ```yaml 61 | - test: riscv_arithmetic_basic_test 62 | description: > 63 | Arithmetic instruction test, no load/store/branch instructions 64 | gen_opts: > 65 | +instr_cnt=320 66 | +num_of_sub_program=0 67 | +no_fence=1 68 | +no_data_page=1 69 | +no_branch_jump=1 70 | +boot_mode=m 71 | iterations: 1 72 | gen_test: riscv_instr_base_test 73 | rtl_test: core_base_test 74 | ``` 75 | 76 | In order to use a Directed C or Assembly test, test is added into the yaml file as follows: 77 | 78 | ```yaml 79 | - test: hello_world 80 | asm_tests: /home/users//Desktop/dv_env/cores/SweRV_EH1/directed_tests/asm/hello_world.s 81 | iterations: 1 82 | rtl_test: core_base_test_benchmark 83 | ``` 84 | 85 | If there is a customized and dedicated linker file which is to be used for test compilation, it should be placed here. When integrating an ISS in this environment, scripts for generating trace logs and csv files in a format similar to ISS (Instruction Set Simulator) for comparison are also placed here. 86 | 87 | ### rtl/ 88 | 89 | This directory contains all the source files related to design of the core. It may contain subdirectories depending upon pipeline stages etc. 90 | 91 | ### snapshots/ 92 | 93 | It contains `configuration` files and `defines` files for the all the source files related to design of the core. If there are multiple possible configurations for a core then each configuration should be placed in a seperate subdirectory. For SweRV, if you are using `default` configuration then all the related files should be placed in `snapshots/default/` directory. 94 | 95 | ### testbench/ 96 | 97 | This directory contains all the files related to testbench for the core. 98 | 99 | ### yaml/rtl_simulation.yaml 100 | 101 | This yaml file is used while compiling and simulating the RTL. It is called from `sim.py` script. Compilation `compile` and simulation `sim` commands are used from this yaml. The options enclosed within arrows symbols e.g. ``, `` etc gets substituted automatically from the `sim.py` script with appropriate values. Flags and options should be added or modified in this yaml based on the requirements. 102 | 103 | ```yaml 104 | - tool: vcs 105 | compile: 106 | cmd: 107 | - "vcs -full64 -LDFLAGS '-Wl,--no-as-needed' 108 | -assert svaext -sverilog +error+500 109 | -timescale=1ns/10ps 110 | -Mdir=/vcs_simv.csrc 111 | -o /vcs_simv 112 | -l /compile.log 113 | -lca -kdb " 114 | wave_opts: > 115 | -debug_access+all -ucli -do waves.tcl 116 | cov_opts: > 117 | -cm_dir /test.vdb 118 | 119 | sim: 120 | cmd: > 121 | env SIM_DIR= 122 | /vcs_simv +vcs+lic+wait 123 | 124 | -l /sim.log 125 | wave_opts: > 126 | -ucli -do /waves.tcl 127 | cov_opts: > 128 | -cm_name test__ 129 | -cm_dir /test.vdb 130 | ``` 131 | 132 | ### Makefile 133 | 134 | All of the DV flow is controlled and run using this makefile. It contains variables which need to be set according to the core and its directory structure. Following is the list of targets which will be used. 135 | 136 | - clean 137 | - compile 138 | - gen 139 | - gcc_compile 140 | - rtl_sim 141 | - iss_sim 142 | - cov_urg 143 | 144 | You need to complete this makefile for running the DV Flow. 145 | 146 | ### sim.py 147 | 148 | This python script is used by makefile for compiling and simulating the design. When `compile` or `rtl_sim` targets are used, `compilation` and `simulation` commands are generated and run from this script. 149 | 150 | ### SweRV_EH1_flist.f 151 | 152 | It lists all the files and directories which are to be compiled. This file is given to RTL Compilation command using flag in `yaml/rtl_simualtion.yaml`. 153 | 154 | ### waves.tcl 155 | 156 | This TCL script contains code for dumping waves on core simulation. 157 | 158 | ### RISC-V DV Flow for Random ASM Tests 159 | 160 | ![Google_RISCV_DV_Flow_Random_Tests](img/Google_RISCV_DV_Flow_Random.png) 161 | 162 | ### RISC-V DV Flow for Directed Tests 163 | 164 | ![Google_RISCV_DV_Flow_Directed_Tests](img/Google_RISCV_DV_Flow_Directed.png) 165 | 166 | **Note**: Above shown files and scripts are just examples for reference. These files are not complete and need to get modified. 167 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv-target/testlists/testlist_I.yaml: -------------------------------------------------------------------------------- 1 | # Copyright Google LLC 2 | # Copyright 2020 Lampro Mellon 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # ================================================================================ 17 | # Regression test list format 18 | # -------------------------------------------------------------------------------- 19 | # test : Assembly test name 20 | # description : Description of this test 21 | # gen_opts : Instruction generator options 22 | # iterations : Number of iterations of this test 23 | # no_iss : Enable/disable ISS simulator (Optional) 24 | # gen_test : Test name used by the instruction generator 25 | # asm_tests : Path to directed, hand-coded assembly test file or directory 26 | # c_tests : Path to directed, hand-coded C test file or directory 27 | # rtl_test : RTL simulation test name 28 | # cmp_opts : Compile options passed to the instruction generator 29 | # sim_opts : Simulation options passed to the instruction generator 30 | # no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) 31 | # compare_opts : Options for the RTL & ISS trace comparison 32 | # gcc_opts : gcc compile options 33 | # -------------------------------------------------------------------------------- 34 | 35 | - test: add-01 36 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/add-01.S 37 | iterations: 1 38 | rtl_test: core_compliance_test 39 | 40 | - test: addi-01 41 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/addi-01.S 42 | iterations: 1 43 | rtl_test: core_compliance_test 44 | 45 | - test: and-01 46 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/and-01.S 47 | iterations: 1 48 | rtl_test: core_compliance_test 49 | 50 | - test: andi-01 51 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/andi-01.S 52 | iterations: 1 53 | rtl_test: core_compliance_test 54 | 55 | - test: auipc-01 56 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/auipc-01.S 57 | iterations: 1 58 | rtl_test: core_compliance_test 59 | 60 | - test: beq-01 61 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/beq-01.S 62 | iterations: 1 63 | rtl_test: core_compliance_test 64 | 65 | - test: bge-01 66 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/bge-01.S 67 | iterations: 1 68 | rtl_test: core_compliance_test 69 | 70 | - test: bgeu-01 71 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/bgeu-01.S 72 | iterations: 1 73 | rtl_test: core_compliance_test 74 | 75 | - test: blt-01 76 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/blt-01.S 77 | iterations: 1 78 | rtl_test: core_compliance_test 79 | 80 | - test: bltu-01 81 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/bltu-01.S 82 | iterations: 1 83 | rtl_test: core_compliance_test 84 | 85 | - test: bne-01 86 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/bne-01.S 87 | iterations: 1 88 | rtl_test: core_compliance_test 89 | 90 | - test: fence-01 91 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/fence-01.S 92 | iterations: 1 93 | rtl_test: core_compliance_test 94 | 95 | - test: jal-01 96 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/jal-01.S 97 | iterations: 1 98 | rtl_test: core_compliance_test 99 | 100 | - test: jalr-01 101 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/jalr-01.S 102 | iterations: 1 103 | rtl_test: core_compliance_test 104 | 105 | - test: lb-align-01 106 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/lb-align-01.S 107 | iterations: 1 108 | rtl_test: core_compliance_test 109 | 110 | - test: lbu-align-01 111 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/lbu-align-01.S 112 | iterations: 1 113 | rtl_test: core_compliance_test 114 | 115 | - test: lh-align-01 116 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/lh-align-01.S 117 | iterations: 1 118 | rtl_test: core_compliance_test 119 | 120 | - test: lhu-align-01 121 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/lhu-align-01.S 122 | iterations: 1 123 | rtl_test: core_compliance_test 124 | 125 | - test: lui-01 126 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/lui-01.S 127 | iterations: 1 128 | rtl_test: core_compliance_test 129 | 130 | - test: lw-align-01 131 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/lw-align-01.S 132 | iterations: 1 133 | rtl_test: core_compliance_test 134 | 135 | - test: or-01 136 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/or-01.S 137 | iterations: 1 138 | rtl_test: core_compliance_test 139 | 140 | - test: ori-01 141 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/ori-01.S 142 | iterations: 1 143 | rtl_test: core_compliance_test 144 | 145 | - test: sb-align-01 146 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/sb-align-01.S 147 | iterations: 1 148 | rtl_test: core_compliance_test 149 | 150 | - test: sh-align-01 151 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/sh-align-01.S 152 | iterations: 1 153 | rtl_test: core_compliance_test 154 | 155 | - test: sll-01 156 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/sll-01.S 157 | iterations: 1 158 | rtl_test: core_compliance_test 159 | 160 | - test: slli-01 161 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/slli-01.S 162 | iterations: 1 163 | rtl_test: core_compliance_test 164 | 165 | - test: slt-01 166 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/slt-01.S 167 | iterations: 1 168 | rtl_test: core_compliance_test 169 | 170 | - test: slti-01 171 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/slti-01.S 172 | iterations: 1 173 | rtl_test: core_compliance_test 174 | 175 | - test: sltiu-01 176 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/sltiu-01.S 177 | iterations: 1 178 | rtl_test: core_compliance_test 179 | 180 | - test: sltu-01 181 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/sltu-01.S 182 | iterations: 1 183 | rtl_test: core_compliance_test 184 | 185 | - test: sra-01 186 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/sra-01.S 187 | iterations: 1 188 | rtl_test: core_compliance_test 189 | 190 | - test: srai-01 191 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/srai-01.S 192 | iterations: 1 193 | rtl_test: core_compliance_test 194 | 195 | - test: srl-01 196 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/srl-01.S 197 | iterations: 1 198 | rtl_test: core_compliance_test 199 | 200 | - test: srli-01 201 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/srli-01.S 202 | iterations: 1 203 | rtl_test: core_compliance_test 204 | 205 | - test: sub-01 206 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/sub-01.S 207 | iterations: 1 208 | rtl_test: core_compliance_test 209 | 210 | - test: sw-align-01 211 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/sw-align-01.S 212 | iterations: 1 213 | rtl_test: core_compliance_test 214 | 215 | - test: xor-01 216 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/xor-01.S 217 | iterations: 1 218 | rtl_test: core_compliance_test 219 | 220 | - test: xori-01 221 | asm_tests: directed_tests/riscv-test-suite/rv32i_m/I/src/xori-01.S 222 | iterations: 1 223 | rtl_test: core_compliance_test 224 | 225 | 226 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/snapshots/default/pic_ctrl_verilator_unroll.sv: -------------------------------------------------------------------------------- 1 | // argv=9 2 | // TOTAL_INT=9 NUM_LEVELS=4 3 | `ifdef RV_PIC_2CYCLE 4 | // LEVEL0 5 | logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en_1; 6 | logic [TOTAL_INT+2:0] [ID_BITS-1:0] level_intpend_id_1; 7 | for (m=0; m<=(TOTAL_INT)/(2**(1)) ; m++) begin : COMPARE0 8 | if ( m == (TOTAL_INT)/(2**(1))) begin 9 | assign level_intpend_w_prior_en_1[m+1] = '0 ; 10 | assign level_intpend_id_1[m+1] = '0 ; 11 | end 12 | cmp_and_mux #( 13 | .ID_BITS(ID_BITS), 14 | .INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l1 ( 15 | .a_id(level_intpend_id[0][2*m]), 16 | .a_priority(level_intpend_w_prior_en[0][2*m]), 17 | .b_id(level_intpend_id[0][2*m+1]), 18 | .b_priority(level_intpend_w_prior_en[0][2*m+1]), 19 | .out_id(level_intpend_id_1[m]), 20 | .out_priority(level_intpend_w_prior_en_1[m])) ; 21 | 22 | end 23 | 24 | // LEVEL1 25 | logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en_2; 26 | logic [TOTAL_INT+2:0] [ID_BITS-1:0] level_intpend_id_2; 27 | for (m=0; m<=(TOTAL_INT)/(2**(2)) ; m++) begin : COMPARE1 28 | if ( m == (TOTAL_INT)/(2**(2))) begin 29 | assign level_intpend_w_prior_en_2[m+1] = '0 ; 30 | assign level_intpend_id_2[m+1] = '0 ; 31 | end 32 | cmp_and_mux #( 33 | .ID_BITS(ID_BITS), 34 | .INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l2 ( 35 | .a_id(level_intpend_id_1[2*m]), 36 | .a_priority(level_intpend_w_prior_en_1[2*m]), 37 | .b_id(level_intpend_id_1[2*m+1]), 38 | .b_priority(level_intpend_w_prior_en_1[2*m+1]), 39 | .out_id(level_intpend_id_2[m]), 40 | .out_priority(level_intpend_w_prior_en_2[m])) ; 41 | 42 | end 43 | 44 | for (i=0; i<=TOTAL_INT/2**(NUM_LEVELS/2) ; i++) begin : MIDDLE_FLOPS 45 | rvdff #(INTPRIORITY_BITS) level2_intpend_prior_reg (.*, .din (level_intpend_w_prior_en_2[i]), .dout(l2_intpend_w_prior_en_ff[i]), .clk(active_clk)); 46 | rvdff #(ID_BITS) level2_intpend_id_reg (.*, .din (level_intpend_id_2[i]), .dout(l2_intpend_id_ff[i]), .clk(active_clk)); 47 | end 48 | // LEVEL2 49 | logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] levelx_intpend_w_prior_en_3; 50 | logic [TOTAL_INT+2:0] [ID_BITS-1:0] levelx_intpend_id_3; 51 | for (m=0; m<=(TOTAL_INT)/(2**(3)) ; m++) begin : COMPARE2 52 | if ( m == (TOTAL_INT)/(2**(3))) begin 53 | assign levelx_intpend_w_prior_en_3[m+1] = '0 ; 54 | assign levelx_intpend_id_3[m+1] = '0 ; 55 | end 56 | cmp_and_mux #( 57 | .ID_BITS(ID_BITS), 58 | .INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l3 ( 59 | .a_id(levelx_intpend_id[2][2*m]), 60 | .a_priority(levelx_intpend_w_prior_en[2][2*m]), 61 | .b_id(levelx_intpend_id[2][2*m+1]), 62 | .b_priority(levelx_intpend_w_prior_en[2][2*m+1]), 63 | .out_id(levelx_intpend_id_3[m]), 64 | .out_priority(levelx_intpend_w_prior_en_3[m])) ; 65 | 66 | end 67 | 68 | // LEVEL3 69 | logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] levelx_intpend_w_prior_en_4; 70 | logic [TOTAL_INT+2:0] [ID_BITS-1:0] levelx_intpend_id_4; 71 | for (m=0; m<=(TOTAL_INT)/(2**(4)) ; m++) begin : COMPARE3 72 | if ( m == (TOTAL_INT)/(2**(4))) begin 73 | assign levelx_intpend_w_prior_en_4[m+1] = '0 ; 74 | assign levelx_intpend_id_4[m+1] = '0 ; 75 | end 76 | cmp_and_mux #( 77 | .ID_BITS(ID_BITS), 78 | .INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l4 ( 79 | .a_id(levelx_intpend_id_3[2*m]), 80 | .a_priority(levelx_intpend_w_prior_en_3[2*m]), 81 | .b_id(levelx_intpend_id_3[2*m+1]), 82 | .b_priority(levelx_intpend_w_prior_en_3[2*m+1]), 83 | .out_id(levelx_intpend_id_4[m]), 84 | .out_priority(levelx_intpend_w_prior_en_4[m])) ; 85 | 86 | end 87 | 88 | assign claimid_in[ID_BITS-1:0] = levelx_intpend_id_4[0] ; // This is the last level output 89 | assign selected_int_priority[INTPRIORITY_BITS-1:0] = levelx_intpend_w_prior_en_4[0] ; 90 | `else 91 | // LEVEL0 92 | logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en_1; 93 | logic [TOTAL_INT+2:0] [ID_BITS-1:0] level_intpend_id_1; 94 | for (m=0; m<=(TOTAL_INT)/(2**(1)) ; m++) begin : COMPARE0 95 | if ( m == (TOTAL_INT)/(2**(1))) begin 96 | assign level_intpend_w_prior_en_1[m+1] = '0 ; 97 | assign level_intpend_id_1[m+1] = '0 ; 98 | end 99 | cmp_and_mux #( 100 | .ID_BITS(ID_BITS), 101 | .INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l1 ( 102 | .a_id(level_intpend_id[0][2*m]), 103 | .a_priority(level_intpend_w_prior_en[0][2*m]), 104 | .b_id(level_intpend_id[0][2*m+1]), 105 | .b_priority(level_intpend_w_prior_en[0][2*m+1]), 106 | .out_id(level_intpend_id_1[m]), 107 | .out_priority(level_intpend_w_prior_en_1[m])) ; 108 | 109 | end 110 | 111 | // LEVEL1 112 | logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en_2; 113 | logic [TOTAL_INT+2:0] [ID_BITS-1:0] level_intpend_id_2; 114 | for (m=0; m<=(TOTAL_INT)/(2**(2)) ; m++) begin : COMPARE1 115 | if ( m == (TOTAL_INT)/(2**(2))) begin 116 | assign level_intpend_w_prior_en_2[m+1] = '0 ; 117 | assign level_intpend_id_2[m+1] = '0 ; 118 | end 119 | cmp_and_mux #( 120 | .ID_BITS(ID_BITS), 121 | .INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l2 ( 122 | .a_id(level_intpend_id_1[2*m]), 123 | .a_priority(level_intpend_w_prior_en_1[2*m]), 124 | .b_id(level_intpend_id_1[2*m+1]), 125 | .b_priority(level_intpend_w_prior_en_1[2*m+1]), 126 | .out_id(level_intpend_id_2[m]), 127 | .out_priority(level_intpend_w_prior_en_2[m])) ; 128 | 129 | end 130 | 131 | // LEVEL2 132 | logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en_3; 133 | logic [TOTAL_INT+2:0] [ID_BITS-1:0] level_intpend_id_3; 134 | for (m=0; m<=(TOTAL_INT)/(2**(3)) ; m++) begin : COMPARE2 135 | if ( m == (TOTAL_INT)/(2**(3))) begin 136 | assign level_intpend_w_prior_en_3[m+1] = '0 ; 137 | assign level_intpend_id_3[m+1] = '0 ; 138 | end 139 | cmp_and_mux #( 140 | .ID_BITS(ID_BITS), 141 | .INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l3 ( 142 | .a_id(level_intpend_id_2[2*m]), 143 | .a_priority(level_intpend_w_prior_en_2[2*m]), 144 | .b_id(level_intpend_id_2[2*m+1]), 145 | .b_priority(level_intpend_w_prior_en_2[2*m+1]), 146 | .out_id(level_intpend_id_3[m]), 147 | .out_priority(level_intpend_w_prior_en_3[m])) ; 148 | 149 | end 150 | 151 | // LEVEL3 152 | logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en_4; 153 | logic [TOTAL_INT+2:0] [ID_BITS-1:0] level_intpend_id_4; 154 | for (m=0; m<=(TOTAL_INT)/(2**(4)) ; m++) begin : COMPARE3 155 | if ( m == (TOTAL_INT)/(2**(4))) begin 156 | assign level_intpend_w_prior_en_4[m+1] = '0 ; 157 | assign level_intpend_id_4[m+1] = '0 ; 158 | end 159 | cmp_and_mux #( 160 | .ID_BITS(ID_BITS), 161 | .INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l4 ( 162 | .a_id(level_intpend_id_3[2*m]), 163 | .a_priority(level_intpend_w_prior_en_3[2*m]), 164 | .b_id(level_intpend_id_3[2*m+1]), 165 | .b_priority(level_intpend_w_prior_en_3[2*m+1]), 166 | .out_id(level_intpend_id_4[m]), 167 | .out_priority(level_intpend_w_prior_en_4[m])) ; 168 | 169 | end 170 | 171 | assign claimid_in[ID_BITS-1:0] = level_intpend_id_4[0] ; // This is the last level output 172 | assign selected_int_priority[INTPRIORITY_BITS-1:0] = level_intpend_w_prior_en_4[0] ; 173 | `endif 174 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/google_riscv_dv/scripts/spike_log_to_trace_csv.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2019 Google LLC 3 | Copyright 2020 Lampro Mellon 4 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); 6 | you may not use this file except in compliance with the License. 7 | You may obtain a copy of the License at 8 | 9 | http://www.apache.org/licenses/LICENSE-2.0 10 | 11 | Unless required by applicable law or agreed to in writing, software 12 | distributed under the License is distributed on an "AS IS" BASIS, 13 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | See the License for the specific language governing permissions and 15 | limitations under the License. 16 | 17 | Convert spike sim log to standard riscv instruction trace format 18 | """ 19 | 20 | import argparse 21 | import os 22 | import re 23 | import sys 24 | import logging 25 | 26 | sys.path.insert(0, os.path.dirname(os.path.realpath(__file__))) 27 | 28 | from riscv_trace_csv import * 29 | from lib import * 30 | 31 | RD_RE = re.compile(r"(?P\d) 0x(?P[a-f0-9]+?) " \ 32 | "\((?P.*?)\) (?P[xf]\s*\d*?) 0x(?P[a-f0-9]+)") 33 | CORE_RE = re.compile(r"core.*0x(?P[a-f0-9]+?) \(0x(?P.*?)\) (?P.*?)$") 34 | ILLE_RE = re.compile(r"trap_illegal_instruction") 35 | 36 | LOGGER = logging.getLogger() 37 | 38 | 39 | def process_instr(trace): 40 | if trace.instr == "jal": 41 | # Spike jal format jal rd, -0xf -> jal rd, -15 42 | idx = trace.operand.rfind(",") 43 | imm = trace.operand[idx+1:] 44 | if imm[0] == "-": 45 | imm = "-" + str(int(imm[1:], 16)) 46 | else: 47 | imm = str(int(imm, 16)) 48 | trace.operand = trace.operand[0:idx+1] + imm 49 | trace.operand = trace.operand.replace("(", ",") 50 | trace.operand = trace.operand.replace(")", "") 51 | 52 | 53 | def read_spike_instr(match, full_trace): 54 | '''Unpack a regex match for CORE_RE to a RiscvInstructionTraceEntry 55 | 56 | If full_trace is true, extract operand data from the disassembled 57 | instruction. 58 | 59 | ''' 60 | 61 | # Extract the disassembled instruction. 62 | disasm = match.group('instr') 63 | 64 | # Spike's disassembler shows a relative jump as something like "j pc + 65 | # 0x123" or "j pc - 0x123". We just want the relative offset. 66 | disasm = disasm.replace('pc + ', '').replace('pc - ', '-') 67 | 68 | instr = RiscvInstructionTraceEntry() 69 | instr.pc = match.group('addr') 70 | instr.instr_str = disasm 71 | instr.binary = match.group('bin') 72 | 73 | #if full_trace: 74 | opcode = disasm.split(' ')[0] 75 | operand = disasm[len(opcode):].replace(' ', '') 76 | instr.instr, instr.operand = \ 77 | convert_pseudo_instr(opcode, operand, instr.binary) 78 | 79 | process_instr(instr) 80 | 81 | return instr 82 | 83 | 84 | def read_spike_trace(path, full_trace): 85 | '''Read a Spike simulation log at , yielding executed instructions. 86 | 87 | This assumes that the log was generated with the -l and --log-commits options 88 | to Spike. 89 | 90 | If full_trace is true, extract operands from the disassembled instructions. 91 | 92 | Since Spike has a strange trampoline that always runs at the start, we skip 93 | instructions up to and including the one at PC 0x1010 (the end of the 94 | trampoline). At the end of a DV program, there's an ECALL instruction, which 95 | we take as a signal to stop checking, so we ditch everything that follows 96 | that instruction. 97 | 98 | This function yields instructions as it parses them as tuples of the form 99 | (entry, illegal). entry is a RiscvInstructionTraceEntry. illegal is a 100 | boolean, which is true if the instruction caused an illegal instruction trap. 101 | 102 | ''' 103 | 104 | # This loop is a simple FSM with states TRAMPOLINE, INSTR, EFFECT. The idea 105 | # is that we're in state TRAMPOLINE until we get to the end of Spike's 106 | # trampoline, then we switch between INSTR (where we expect to read an 107 | # instruction) and EFFECT (where we expect to read commit information). 108 | # 109 | # We yield a RiscvInstructionTraceEntry object each time we leave EFFECT 110 | # (going back to INSTR), we loop back from INSTR to itself, or we get to the 111 | # end of the file and have an instruction in hand. 112 | # 113 | # On entry to the loop body, we are in state TRAMPOLINE if in_trampoline is 114 | # true. Otherwise, we are in state EFFECT if instr is not None, otherwise we 115 | # are in state INSTR. 116 | 117 | end_trampoline_re = re.compile(r'core.*: 0x0*1010 ') 118 | 119 | in_trampoline = True 120 | instr = None 121 | 122 | with open(path, 'r') as handle: 123 | for line in handle: 124 | if in_trampoline: 125 | # The TRAMPOLINE state 126 | if end_trampoline_re.match(line): 127 | in_trampoline = False 128 | continue 129 | 130 | if instr is None: 131 | # The INSTR state. We expect to see a line matching CORE_RE. We'll 132 | # discard any other lines. 133 | instr_match = CORE_RE.match(line) 134 | if not instr_match: 135 | continue 136 | 137 | instr = read_spike_instr(instr_match, full_trace) 138 | 139 | # If instr.instr_str is 'ecall', we should stop. 140 | if instr.instr_str == 'ecall': 141 | break 142 | 143 | continue 144 | 145 | # The EFFECT state. If the line matches CORE_RE, we should have been in 146 | # state INSTR, so we yield the instruction we had, read the new 147 | # instruction and continue. As above, if the new instruction is 'ecall', 148 | # we need to stop immediately. 149 | instr_match = CORE_RE.match(line) 150 | if instr_match: 151 | yield (instr, False) 152 | instr = read_spike_instr(instr_match, full_trace) 153 | if instr.instr_str == 'ecall': 154 | break 155 | continue 156 | 157 | # The line doesn't match CORE_RE, so we are definitely on a follow-on 158 | # line in the log. First, check for illegal instructions 159 | if 'trap_illegal_instruction' in line: 160 | yield (instr, True) 161 | instr = None 162 | continue 163 | 164 | # The instruction seems to have been fine. Do we have commit data (from 165 | # the --log-commits Spike option)? 166 | commit_match = RD_RE.match(line) 167 | if commit_match: 168 | instr.gpr.append(gpr_to_abi(commit_match.group('reg') 169 | .replace(' ', '')) + 170 | ':' + commit_match.group('val')) 171 | instr.mode = commit_match.group('pri') 172 | 173 | # At EOF, we might have an instruction in hand. Yield it if so. 174 | if instr is not None: 175 | yield (instr, False) 176 | 177 | 178 | def process_spike_sim_log(spike_log, csv, full_trace = 0): 179 | """Process SPIKE simulation log. 180 | 181 | Extract instruction and affected register information from spike simulation 182 | log and write the results to a CSV file at csv. Returns the number of 183 | instructions written. 184 | 185 | """ 186 | logging.info("Processing spike log : %s" % spike_log) 187 | instrs_in = 0 188 | instrs_out = 0 189 | 190 | with open(csv, "w") as csv_fd: 191 | trace_csv = RiscvInstructionTraceCsv(csv_fd) 192 | trace_csv.start_new_trace() 193 | 194 | for (entry, illegal) in read_spike_trace(spike_log, full_trace): 195 | instrs_in += 1 196 | 197 | if illegal and full_trace: 198 | logging.debug("Illegal instruction: {}, opcode:{}" 199 | .format(entry.instr_str, entry.binary)) 200 | 201 | # Instructions that cause no architectural update (which includes illegal 202 | # instructions) are ignored if full_trace is false. 203 | # 204 | # We say that an instruction caused an architectural update if either we 205 | # saw a commit line (in which case, entry.gpr will contain a single 206 | # entry) or the instruction was 'wfi' or 'ecall'. 207 | if not (full_trace or entry.gpr or entry.instr_str in ['wfi', 'ecall']): 208 | continue 209 | 210 | trace_csv.write_trace_entry(entry) 211 | instrs_out += 1 212 | 213 | logging.info("Processed instruction count : %d" % instrs_in) 214 | logging.info("CSV saved to : %s" % csv) 215 | return instrs_out 216 | 217 | 218 | def main(): 219 | # Parse input arguments 220 | parser = argparse.ArgumentParser() 221 | parser.add_argument("--log", type=str, help="Input spike simulation log") 222 | parser.add_argument("--csv", type=str, help="Output trace csv_buf file") 223 | parser.add_argument("-f", "--full_trace", dest="full_trace", action="store_true", 224 | help="Generate the full trace") 225 | parser.add_argument("-v", "--verbose", dest="verbose", action="store_true", 226 | help="Verbose logging") 227 | parser.set_defaults(full_trace=False) 228 | parser.set_defaults(verbose=False) 229 | args = parser.parse_args() 230 | setup_logging(args.verbose) 231 | # Process spike log 232 | process_spike_sim_log(args.log, args.csv, args.full_trace) 233 | 234 | 235 | if __name__ == "__main__": 236 | main() 237 | -------------------------------------------------------------------------------- /integration_files/SweRV_EH1/riscv_dv_extension/core_log_to_trace_csv.py: -------------------------------------------------------------------------------- 1 | # Copyright lowRISC contributors. 2 | # Copyright 2020 Lampro Mellon 3 | # 4 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. 5 | # SPDX-License-Identifier: Apache-2.0 6 | # 7 | # Convert Core log to the standard trace CSV format 8 | 9 | import argparse 10 | import os 11 | import re 12 | import sys 13 | 14 | _CORE_ROOT = os.path.normpath(os.path.join(os.path.dirname(__file__), 15 | '../')) 16 | _DV_SCRIPTS = os.path.join(_CORE_ROOT, '../../../google_riscv_dv/scripts') 17 | _OLD_SYS_PATH = sys.path 18 | 19 | # Import riscv_trace_csv and lib from _DV_SCRIPTS before putting sys.path back 20 | # as it started. 21 | try: 22 | sys.path.insert(0, _DV_SCRIPTS) 23 | 24 | from riscv_trace_csv import (RiscvInstructionTraceCsv, 25 | RiscvInstructionTraceEntry, 26 | get_imm_hex_val) 27 | from lib import RET_FATAL, gpr_to_abi, sint_to_hex 28 | import logging 29 | 30 | finally: 31 | sys.path = _OLD_SYS_PATH 32 | 33 | 34 | INSTR_RE = \ 35 | re.compile(r"^\s*(?P