├── .vscode ├── .cortex-debug.peripherals.state.json ├── .cortex-debug.registers.state.json └── launch.json ├── EspZephyr.code-workspace ├── README.md └── esp_svd ├── esp32.svd ├── esp32c2.svd ├── esp32c3.svd ├── esp32c6-lp.svd ├── esp32c6.svd ├── esp32h2.svd ├── esp32p4.svd ├── esp32s2-ulp.svd ├── esp32s2.svd ├── esp32s3-ulp.svd └── esp32s3.svd /.vscode/.cortex-debug.peripherals.state.json: -------------------------------------------------------------------------------- 1 | [] -------------------------------------------------------------------------------- /.vscode/.cortex-debug.registers.state.json: -------------------------------------------------------------------------------- 1 | [] -------------------------------------------------------------------------------- /.vscode/launch.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": "0.1.0", 3 | "configurations": [ 4 | { 5 | "name": "ESP32", 6 | "cwd": "${workspaceFolder:zephyr}", 7 | "executable": "${workspaceFolder:zephyr}/build/zephyr/zephyr.elf", 8 | "request": "attach", 9 | "type": "cortex-debug", 10 | "servertype": "openocd", 11 | "interface": "jtag", 12 | "svdFile": "${config:bsp.svd_path}/esp32.svd", 13 | "serverpath": "${config:bsp.openocd_root}/bin/openocd", 14 | "toolchainPath": "${userHome}/zephyr-sdk-${config:bsp.zephyr_sdk_version}/xtensa-espressif_esp32_zephyr-elf/bin", 15 | "toolchainPrefix": "xtensa-espressif_esp32_zephyr-elf", 16 | "openOCDPreConfigLaunchCommands":[ 17 | "set ESP_RTOS Zephyr", 18 | ], 19 | "openOCDLaunchCommands": [ 20 | "init", 21 | "reset halt", 22 | "esp appimage_offset 0x0" 23 | ], 24 | "configFiles": [ 25 | "board/esp32_devkitj_v1.cfg" 26 | ], 27 | "overrideAttachCommands": [ 28 | "mon reset halt", 29 | "maintenance flush register-cache" 30 | ], 31 | "overrideRestartCommands": [ 32 | "mon reset halt", 33 | "maintenance flush register-cache", 34 | ], 35 | "runToEntryPoint": "main", 36 | }, 37 | { 38 | "name": "ESP-WROVER-KIT", 39 | "cwd": "${workspaceFolder:zephyr}", 40 | "executable": "${workspaceFolder:zephyr}/build/zephyr/zephyr.elf", 41 | "request": "attach", 42 | "type": "cortex-debug", 43 | "servertype": "openocd", 44 | "interface": "jtag", 45 | "svdFile": "${config:bsp.svd_path}/esp32.svd", 46 | "serverpath": "${config:bsp.openocd_root}/bin/openocd", 47 | "toolchainPath": "${userHome}/zephyr-sdk-${config:bsp.zephyr_sdk_version}/xtensa-espressif_esp32_zephyr-elf/bin", 48 | "toolchainPrefix": "xtensa-espressif_esp32_zephyr-elf", 49 | "openOCDPreConfigLaunchCommands":[ 50 | "set ESP_RTOS Zephyr", 51 | ], 52 | "openOCDLaunchCommands": [ 53 | "init", 54 | "reset halt", 55 | "esp appimage_offset 0x0" 56 | ], 57 | "configFiles": [ 58 | "board/esp32-wrover-kit-3.3v.cfg" 59 | ], 60 | "overrideAttachCommands": [ 61 | "mon reset halt", 62 | "maintenance flush register-cache" 63 | ], 64 | "overrideRestartCommands": [ 65 | "mon reset halt", 66 | "maintenance flush register-cache", 67 | ], 68 | "runToEntryPoint": "main", 69 | }, 70 | { 71 | "name": "ESP32S2", 72 | "cwd": "${workspaceFolder:zephyr}", 73 | "executable": "${workspaceFolder:zephyr}/build/zephyr/zephyr.elf", 74 | "request": "attach", 75 | "type": "cortex-debug", 76 | "servertype": "openocd", 77 | "interface": "jtag", 78 | "svdFile": "${config:bsp.svd_path}/esp32s2.svd", 79 | "serverpath": "${config:bsp.openocd_root}/bin/openocd", 80 | "toolchainPath": "${userHome}/zephyr-sdk-${config:bsp.zephyr_sdk_version}/xtensa-espressif_esp32s2_zephyr-elf/bin", 81 | "toolchainPrefix": "xtensa-espressif_esp32s2_zephyr-elf", 82 | "openOCDPreConfigLaunchCommands":[ 83 | "set ESP_RTOS Zephyr", 84 | ], 85 | "openOCDLaunchCommands": [ 86 | "init", 87 | "reset halt", 88 | "esp appimage_offset 0x0" 89 | ], 90 | "configFiles": [ 91 | "board/esp32s2-kaluga-1.cfg" 92 | ], 93 | "overrideAttachCommands": [ 94 | "mon reset halt", 95 | "maintenance flush register-cache" 96 | ], 97 | "overrideRestartCommands": [ 98 | "mon reset halt", 99 | "maintenance flush register-cache", 100 | ], 101 | "runToEntryPoint": "main", 102 | }, 103 | { 104 | "name": "ESP32C2", 105 | "cwd": "${workspaceRoot}", 106 | "executable": "${workspaceFolder:zephyr}/build/zephyr/zephyr.elf", 107 | "request": "attach", 108 | "type": "cortex-debug", 109 | "servertype": "openocd", 110 | "interface": "jtag", 111 | "svdFile": "${config:bsp.svd_path}/esp32c2.svd", 112 | "serverpath": "${config:bsp.openocd_root}/bin/openocd", 113 | "toolchainPath": "${userHome}/zephyr-sdk-${config:bsp.zephyr_sdk_version}/riscv64-zephyr-elf/bin/", 114 | "toolchainPrefix": "riscv64-zephyr-elf", 115 | "openOCDPreConfigLaunchCommands":[ 116 | "set ESP_RTOS Zephyr", 117 | ], 118 | "openOCDLaunchCommands": [ 119 | "init", 120 | "reset halt", 121 | "esp appimage_offset 0x0" 122 | ], 123 | "configFiles": [ 124 | "board/esp32c2-bridge.cfg" 125 | ], 126 | "overrideAttachCommands": [ 127 | "mon reset halt", 128 | "maintenance flush register-cache" 129 | ], 130 | "overrideRestartCommands": [ 131 | "mon reset halt", 132 | "maintenance flush register-cache", 133 | ], 134 | "runToEntryPoint": "main", 135 | }, 136 | { 137 | "name": "ESP32C3", 138 | "cwd": "${workspaceRoot}", 139 | "executable": "${workspaceFolder:zephyr}/build/zephyr/zephyr.elf", 140 | "request": "attach", 141 | "type": "cortex-debug", 142 | "servertype": "openocd", 143 | "interface": "jtag", 144 | "svdFile": "${config:bsp.svd_path}/esp32c3.svd", 145 | "serverpath": "${config:bsp.openocd_root}/bin/openocd", 146 | "toolchainPath": "${userHome}/zephyr-sdk-${config:bsp.zephyr_sdk_version}/riscv64-zephyr-elf/bin/", 147 | "toolchainPrefix": "riscv64-zephyr-elf", 148 | "openOCDPreConfigLaunchCommands":[ 149 | "set ESP_RTOS Zephyr", 150 | ], 151 | "openOCDLaunchCommands": [ 152 | "init", 153 | "reset halt", 154 | "esp appimage_offset 0x0" 155 | ], 156 | "configFiles": [ 157 | "board/esp32c3-builtin.cfg" 158 | ], 159 | "overrideAttachCommands": [ 160 | "mon reset halt", 161 | "maintenance flush register-cache" 162 | ], 163 | "overrideRestartCommands": [ 164 | "mon reset halt", 165 | "maintenance flush register-cache", 166 | ], 167 | "runToEntryPoint": "main", 168 | }, 169 | { 170 | "name": "ESP32C6", 171 | "cwd": "${workspaceRoot}", 172 | "executable": "${workspaceFolder:zephyr}/build/zephyr/zephyr.elf", 173 | "request": "attach", 174 | "type": "cortex-debug", 175 | "servertype": "openocd", 176 | "interface": "jtag", 177 | "svdFile": "${config:bsp.svd_path}/esp32c6.svd", 178 | "serverpath": "${config:bsp.openocd_root}/bin/openocd", 179 | "toolchainPath": "${userHome}/zephyr-sdk-${config:bsp.zephyr_sdk_version}/riscv64-zephyr-elf/bin/", 180 | "toolchainPrefix": "riscv64-zephyr-elf", 181 | "openOCDPreConfigLaunchCommands":[ 182 | "set ESP_RTOS Zephyr", 183 | ], 184 | "openOCDLaunchCommands": [ 185 | "init", 186 | "reset halt", 187 | "esp appimage_offset 0x0" 188 | ], 189 | "configFiles": [ 190 | "board/esp32c6-builtin.cfg", 191 | ], 192 | "overrideAttachCommands": [ 193 | "mon reset halt", 194 | "maintenance flush register-cache" 195 | ], 196 | "overrideRestartCommands": [ 197 | "mon reset halt", 198 | "maintenance flush register-cache", 199 | ], 200 | "runToEntryPoint": "main", 201 | }, 202 | { 203 | "name": "ESP32S3", 204 | "cwd": "${workspaceRoot}", 205 | "executable": "${workspaceFolder:zephyr}/build/zephyr/zephyr.elf", 206 | "request": "attach", 207 | "type": "cortex-debug", 208 | "servertype": "openocd", 209 | "interface": "jtag", 210 | "svdFile": "${config:bsp.svd_path}/esp32s3.svd", 211 | "serverpath": "${config:bsp.openocd_root}/bin/openocd", 212 | "toolchainPath": "${userHome}/zephyr-sdk-${config:bsp.zephyr_sdk_version}/xtensa-espressif_esp32s3_zephyr-elf/bin/", 213 | "toolchainPrefix": "xtensa-espressif_esp32s3_zephyr-elf", 214 | "openOCDPreConfigLaunchCommands":[ 215 | "set ESP_RTOS Zephyr", 216 | ], 217 | "openOCDLaunchCommands": [ 218 | "init", 219 | "reset halt", 220 | "esp appimage_offset 0x0" 221 | ], 222 | "configFiles": [ 223 | "board/esp32s3-builtin.cfg" 224 | ], 225 | "overrideAttachCommands": [ 226 | "mon reset halt", 227 | "maintenance flush register-cache", 228 | ], 229 | "overrideRestartCommands": [ 230 | "mon reset halt", 231 | "maintenance flush register-cache", 232 | ], 233 | } 234 | 235 | ] 236 | } 237 | -------------------------------------------------------------------------------- /EspZephyr.code-workspace: -------------------------------------------------------------------------------- 1 | { 2 | "folders": [ 3 | { 4 | "name": "workspace", 5 | "path": "." 6 | }, 7 | { 8 | "name": "hal_espressif", 9 | "path": "../modules/hal/espressif", 10 | }, 11 | { 12 | "name": "zephyr", 13 | "path": "../zephyr", 14 | }, 15 | ], 16 | 17 | "settings": { 18 | // Board support package settings: 19 | "bsp": { 20 | "cpu": "", 21 | "soc": "", 22 | "board": "", 23 | "board_root": "", 24 | "board_path": "", 25 | "svd_path": "${workspaceFolder}/esp_svd", 26 | "rom_elf_path": "${workspaceFolder}/rom_elf", 27 | "openocd_root": "/usr/local", 28 | "debug_config": "", 29 | "zephyr_sdk_version": "0.17.0", 30 | }, 31 | 32 | "C_Cpp.default.compileCommands": "${workspaceFolder:zephyr}/build/compile_commands.json", 33 | "C_Cpp.default.includePath": [ 34 | "${workspaceFolder:zephyr}", 35 | "${workspaceFolder:hal_espressif}", 36 | ], 37 | 38 | "cmake.configureOnOpen": false, 39 | 40 | // The number of spaces a tab is equal to. This setting is overridden 41 | // based on the file contents when `editor.detectIndentation` is true. 42 | "editor.tabSize": 8, 43 | 44 | // Insert spaces when pressing Tab. This setting is overriden 45 | // based on the file contents when `editor.detectIndentation` is true. 46 | "editor.insertSpaces": false, 47 | 48 | // When opening a file, `editor.tabSize` and `editor.insertSpaces` 49 | // will be detected based on the file contents. Set to false to keep 50 | // the values you've explicitly set, above. 51 | "editor.detectIndentation": false, 52 | "editor.rulers": [100], 53 | 54 | "editor.cursorBlinking": "smooth", 55 | 56 | "files.trimFinalNewlines": true, 57 | "editor.formatOnSave": false, 58 | "editor.codeActionsOnSave": [], 59 | 60 | "editor.renderWhitespace": "all", 61 | 62 | "files.watcherExclude": { 63 | "**/.git/objects/**": true, 64 | "**/.git/subtree-cache/**": true, 65 | "**/node_modules/**": true, 66 | "**/tmp/**": true, 67 | "**/.git": true, 68 | "**/.svn": true, 69 | "**/.hg": true, 70 | "**/CVS": true, 71 | "**/.DS_Store": true, 72 | "**/node_modules": true, 73 | "**/bower_components": true, 74 | "**/dist/**": true, 75 | "**/log/**": true, 76 | "**/logs/**": true, 77 | "**/.fdk/**": true, 78 | "**/.west/**": true, 79 | "**/.vscode/**": true, 80 | "${workspaceRoot}/../zephyr/**": true 81 | }, 82 | "files.exclude": { 83 | "**/.git/objects/**": true, 84 | "**/.git/subtree-cache/**": true, 85 | "**/node_modules/**": true, 86 | "**/tmp/**": true, 87 | "**/.git": true, 88 | "**/.svn": true, 89 | "**/.hg": true, 90 | "**/CVS": true, 91 | "**/.DS_Store": true, 92 | "**/node_modules": true, 93 | "**/bower_components": true, 94 | "**/dist/**": true, 95 | "**/log/**": true, 96 | "**/.fdk/**": true, 97 | "**/.west/**": true 98 | }, 99 | "search.exclude": { 100 | "**/.git/objects/**": true, 101 | "**/.git/subtree-cache/**": true, 102 | "**/node_modules/**": true, 103 | "**/tmp/**": true, 104 | "**/.git": true, 105 | "**/.svn": true, 106 | "**/.hg": true, 107 | "**/CVS": true, 108 | "**/.DS_Store": true, 109 | "**/node_modules": true, 110 | "**/bower_components": true, 111 | "**/dist/**": true, 112 | "**/log/**": true, 113 | "**/.west/**": true 114 | }, 115 | "editor.renderControlCharacters": false, 116 | "cortex-debug.variableUseNaturalFormat": false, 117 | } 118 | } 119 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Workspace for Espressif's SoC development on Zephyr 2 | 3 | This simple repository provides Visual Studio Code (aka VSCode) necessary 4 | configurations for [Espressif](https://www.espressif.com/) SoC development on [Zephyr](https://github.com/zephyrproject-rtos/zephyr) 5 | 6 | * Configuration of VSCode workspace 7 | * Debug Launch for ESP32, ESP32S2/S3 and ESP32C3/C6 8 | * OpenOCD ESP config files 9 | * ESP32/S2/S3/C3/C6 SVD files needed for debugger 10 | 11 | ## Getting started 12 | Follow this simple steps to simplify your Zephyr development in VSCode: 13 | 14 | 1. Follow Zephyr's latest [Getting Started Guide](https://docs.zephyrproject.org/latest/getting_started/index.html) 15 | 2. Switch to yout `zephyrproject` path from terminal: 16 | > cd /zephyrproject 17 | 3. Clone this repository in your `zephyrproject`: 18 | > git clone https://github.com/LucasTambor/EspZephyrWS.git 19 | 4. Open [EspZephyr.code-workspace](https://github.com/LucasTambor/EspZephyrWS/blob/main/Espressif_Zephyr.code-workspace) as a workspace in VSCode: 20 | > File -> Open Workspace... 21 | (be careful: last opened active workspace must be closed) 22 | 23 | **Note:** This repository must be placed in your `zephyrproject` folder! 24 | 25 | ## Workspace Configuration 26 | The [EspZephyr.code-workspace](https://github.com/LucasTambor/EspZephyrWS/blob/main/Espressif_Zephyr.code-workspace) 27 | contains all neccessary workspace configuration accepted by Zephyr project like: 28 | * Folders to open (like `zephyrproject`) 29 | * Minimal code styling settings (TABs/SPACES) 30 | * Exclude paths (needed to reduce CPU usage while workspace is opened) 31 | 32 | ## OpenOCD for ESP32 33 | 34 | The Open On-Chip Debugger (OpenOCD) is an open source application that implements a remote GDB server for a wide variety of embedded devices. 35 | The ESP32 modules need some patches that are not available in the upstream project. 36 | For this reason Espressif maintains its own version of the repository. 37 | 38 | The custom OpenOCD can be obtained at [OpenOCD ESP32](https://github.com/espressif/openocd-esp32/releases). 39 | 40 | Download the latest version and extract it at your preferred location. 41 | Overwrite the `openocd_root` configuration at [EspZephyr.code-workspace](https://github.com/LucasTambor/EspZephyrWS/blob/main/Espressif_Zephyr.code-workspace) with the path where you extract it. 42 | 43 | ## Debug 44 | 45 | To launch the project you need [Cortex-Debug](https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug) 46 | extension for Visual Studio Code. Please install it and follow it's installation guide. 47 | 48 | After installing `Cortex-Debug` and `OpenOCD` on your system, the debug button 49 | should appear in your VSCode GUI. 50 | 51 | The [.vscode/launch.json](https://github.com/Nukersson/zephyr_vscode_workspace/blob/master/.vscode/launch.json) 52 | describes launch configuration for `Cortex-Debug`. 53 | 54 | # Acknowledges 55 | 56 | Inspired by https://github.com/Nukersson/zephyr_vscode_workspace 57 | -------------------------------------------------------------------------------- /esp_svd/esp32s2-ulp.svd: -------------------------------------------------------------------------------- 1 | 2 | 3 | ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. 4 | ESPRESSIF 5 | ESP32-S2-ULP 6 | RISC-V ULP 7 | 1 8 | 32-bit RISC-V MCU 9 | 10 | Copyright 2023 Espressif Systems (Shanghai) PTE LTD 11 | 12 | Licensed under the Apache License, Version 2.0 (the "License"); 13 | you may not use this file except in compliance with the License. 14 | You may obtain a copy of the License at 15 | 16 | http://www.apache.org/licenses/LICENSE-2.0 17 | 18 | Unless required by applicable law or agreed to in writing, software 19 | distributed under the License is distributed on an "AS IS" BASIS, 20 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | See the License for the specific language governing permissions and 22 | limitations under the License. 23 | 24 | 25 | RV32IMC 26 | r0p0 27 | little 28 | false 29 | false 30 | 4 31 | false 32 | 33 | 32 34 | 32 35 | 0x00000000 36 | 0xFFFFFFFF 37 | 38 | 39 | RTC_IO 40 | Low-power Input/Output 41 | RTCIO 42 | 0x0000A400 43 | 44 | 0x0 45 | 0xF0 46 | registers 47 | 48 | 49 | 50 | RTC_GPIO_OUT 51 | RTC GPIO output register 52 | 0x0 53 | 0x20 54 | 55 | 56 | GPIO_OUT_DATA 57 | GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. 58 | 10 59 | 22 60 | read-write 61 | 62 | 63 | 64 | 65 | RTC_GPIO_OUT_W1TS 66 | RTC GPIO output bit set register 67 | 0x4 68 | 0x20 69 | 70 | 71 | GPIO_OUT_DATA_W1TS 72 | GPIO0 ~ 21 output set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_OUT_REG. 73 | 10 74 | 22 75 | write-only 76 | 77 | 78 | 79 | 80 | RTC_GPIO_OUT_W1TC 81 | RTC GPIO output bit clear register 82 | 0x8 83 | 0x20 84 | 85 | 86 | GPIO_OUT_DATA_W1TC 87 | GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG. 88 | 10 89 | 22 90 | write-only 91 | 92 | 93 | 94 | 95 | RTC_GPIO_ENABLE 96 | RTC GPIO output enable register 97 | 0xC 98 | 0x20 99 | 100 | 101 | REG_RTCIO_REG_GPIO_ENABLE 102 | GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output. 103 | 10 104 | 22 105 | read-write 106 | 107 | 108 | 109 | 110 | RTC_GPIO_ENABLE_W1TS 111 | RTC GPIO output enable bit set register 112 | 0x10 113 | 0x20 114 | 115 | 116 | REG_RTCIO_REG_GPIO_ENABLE_W1TS 117 | GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_ENABLE_REG. 118 | 10 119 | 22 120 | write-only 121 | 122 | 123 | 124 | 125 | RTC_GPIO_ENABLE_W1TC 126 | RTC GPIO output enable bit clear register 127 | 0x14 128 | 0x20 129 | 130 | 131 | REG_RTCIO_REG_GPIO_ENABLE_W1TC 132 | GPIO0 ~ 21 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_ENABLE_REG. 133 | 10 134 | 22 135 | write-only 136 | 137 | 138 | 139 | 140 | RTC_GPIO_STATUS 141 | RTC GPIO interrupt status register 142 | 0x18 143 | 0x20 144 | 145 | 146 | GPIO_STATUS_INT 147 | GPIO0 ~ 21 interrupt status register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RTCIO_RTC_GPIO_PINn_REG. 0: no interrupt; 1: corresponding interrupt. 148 | 10 149 | 22 150 | read-write 151 | 152 | 153 | 154 | 155 | RTC_GPIO_STATUS_W1TS 156 | RTC GPIO interrupt status bit set register 157 | 0x1C 158 | 0x20 159 | 160 | 161 | GPIO_STATUS_INT_W1TS 162 | GPIO0 ~ 21 interrupt set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be set to 1. Recommended operation: use this register to set RTCIO_GPIO_STATUS_INT. 163 | 10 164 | 22 165 | write-only 166 | 167 | 168 | 169 | 170 | RTC_GPIO_STATUS_W1TC 171 | RTC GPIO interrupt status bit clear register 172 | 0x20 173 | 0x20 174 | 175 | 176 | GPIO_STATUS_INT_W1TC 177 | GPIO0 ~ 21 interrupt clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be cleared. Recommended operation: use this register to clear RTCIO_GPIO_STATUS_INT. 178 | 10 179 | 22 180 | write-only 181 | 182 | 183 | 184 | 185 | RTC_GPIO_IN 186 | RTC GPIO input register 187 | 0x24 188 | 0x20 189 | 190 | 191 | GPIO_IN_NEXT 192 | GPIO0 ~ 21 input value. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. Each bit represents a pad input value, 1 for high level, and 0 for low level. 193 | 10 194 | 22 195 | read-only 196 | 197 | 198 | 199 | 200 | 22 201 | 0x4 202 | RTC_GPIO_PIN%s 203 | RTC configuration for pin %s 204 | 0x28 205 | 0x20 206 | 207 | 208 | GPIO_PIN_PAD_DRIVER 209 | Pad driver selection. 0: normal output. 1: open drain. 210 | 2 211 | 1 212 | read-write 213 | 214 | 215 | GPIO_PIN_INT_TYPE 216 | GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger. 217 | 7 218 | 3 219 | read-write 220 | 221 | 222 | GPIO_PIN_WAKEUP_ENABLE 223 | GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. 224 | 10 225 | 1 226 | read-write 227 | 228 | 229 | 230 | 231 | RTC_DEBUG_SEL 232 | RTC debug select register 233 | 0x80 234 | 0x20 235 | 236 | 237 | RTC_DEBUG_SEL0 238 | 0 239 | 5 240 | read-write 241 | 242 | 243 | RTC_DEBUG_SEL1 244 | 5 245 | 5 246 | read-write 247 | 248 | 249 | RTC_DEBUG_SEL2 250 | 10 251 | 5 252 | read-write 253 | 254 | 255 | RTC_DEBUG_SEL3 256 | 15 257 | 5 258 | read-write 259 | 260 | 261 | RTC_DEBUG_SEL4 262 | 20 263 | 5 264 | read-write 265 | 266 | 267 | RTC_DEBUG_12M_NO_GATING 268 | 25 269 | 1 270 | read-write 271 | 272 | 273 | 274 | 275 | 15 276 | 0x4 277 | TOUCH_PAD%s 278 | Touch pad %s configuration register 279 | 0x84 280 | 0x20 281 | 0x52000000 282 | 283 | 284 | FUN_IE 285 | Input enable in normal execution. 286 | 13 287 | 1 288 | read-write 289 | 290 | 291 | SLP_OE 292 | Output enable in sleep mode. 293 | 14 294 | 1 295 | read-write 296 | 297 | 298 | SLP_IE 299 | Input enable in sleep mode. 300 | 15 301 | 1 302 | read-write 303 | 304 | 305 | SLP_SEL 306 | 0: no sleep mode. 1: enable sleep mode. 307 | 16 308 | 1 309 | read-write 310 | 311 | 312 | FUN_SEL 313 | Function selection. 314 | 17 315 | 2 316 | read-write 317 | 318 | 319 | MUX_SEL 320 | Connect the RTC pad input to digital pad input. 0 is available. 321 | 19 322 | 1 323 | read-write 324 | 325 | 326 | XPD 327 | Touch sensor power on. 328 | 20 329 | 1 330 | read-write 331 | 332 | 333 | TIE_OPT 334 | The tie option of touch sensor. 0: tie low. 1: tie high. 335 | 21 336 | 1 337 | read-write 338 | 339 | 340 | START 341 | Start touch sensor. 342 | 22 343 | 1 344 | read-write 345 | 346 | 347 | DAC 348 | Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. 349 | 23 350 | 3 351 | read-write 352 | 353 | 354 | RUE 355 | Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 356 | 27 357 | 1 358 | read-write 359 | 360 | 361 | RDE 362 | Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 363 | 28 364 | 1 365 | read-write 366 | 367 | 368 | DRV 369 | Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 370 | 29 371 | 2 372 | read-write 373 | 374 | 375 | 376 | 377 | XTAL_32P_PAD 378 | 32KHz crystal P-pad configuration register 379 | 0xC0 380 | 0x20 381 | 0x40000000 382 | 383 | 384 | X32P_FUN_IE 385 | Input enable in normal execution. 386 | 13 387 | 1 388 | read-write 389 | 390 | 391 | X32P_SLP_OE 392 | output enable in sleep mode. 393 | 14 394 | 1 395 | read-write 396 | 397 | 398 | X32P_SLP_IE 399 | input enable in sleep mode. 400 | 15 401 | 1 402 | read-write 403 | 404 | 405 | X32P_SLP_SEL 406 | 1: enable sleep mode. 0: no sleep mode. 407 | 16 408 | 1 409 | read-write 410 | 411 | 412 | X32P_FUN_SEL 413 | Function selection. 414 | 17 415 | 2 416 | read-write 417 | 418 | 419 | X32P_MUX_SEL 420 | 1: use RTC GPIO. 0: use digital GPIO. 421 | 19 422 | 1 423 | read-write 424 | 425 | 426 | X32P_RUE 427 | Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 428 | 27 429 | 1 430 | read-write 431 | 432 | 433 | X32P_RDE 434 | Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 435 | 28 436 | 1 437 | read-write 438 | 439 | 440 | X32P_DRV 441 | Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 442 | 29 443 | 2 444 | read-write 445 | 446 | 447 | 448 | 449 | XTAL_32N_PAD 450 | 32KHz crystal N-pad configuration register 451 | 0xC4 452 | 0x20 453 | 0x40000000 454 | 455 | 456 | X32N_FUN_IE 457 | Input enable in normal execution. 458 | 13 459 | 1 460 | read-write 461 | 462 | 463 | X32N_SLP_OE 464 | Output enable in sleep mode. 465 | 14 466 | 1 467 | read-write 468 | 469 | 470 | X32N_SLP_IE 471 | Input enable in sleep mode. 472 | 15 473 | 1 474 | read-write 475 | 476 | 477 | X32N_SLP_SEL 478 | 1: enable sleep mode. 0: no sleep mode. 479 | 16 480 | 1 481 | read-write 482 | 483 | 484 | X32N_FUN_SEL 485 | Function selection. 486 | 17 487 | 2 488 | read-write 489 | 490 | 491 | X32N_MUX_SEL 492 | 1: use RTC GPIO. 0: use digital GPIO. 493 | 19 494 | 1 495 | read-write 496 | 497 | 498 | X32N_RUE 499 | Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 500 | 27 501 | 1 502 | read-write 503 | 504 | 505 | X32N_RDE 506 | Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 507 | 28 508 | 1 509 | read-write 510 | 511 | 512 | X32N_DRV 513 | Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 514 | 29 515 | 2 516 | read-write 517 | 518 | 519 | 520 | 521 | PAD_DAC1 522 | DAC1 configuration register 523 | 0xC8 524 | 0x20 525 | 0x40000000 526 | 527 | 528 | PDAC1_DAC 529 | Configure DAC_1 output when RTCIO_PDAC1_DAC_XPD_FORCE is set to 1. 530 | 3 531 | 8 532 | read-write 533 | 534 | 535 | PDAC1_XPD_DAC 536 | When RTCIO_PDAC1_DAC_XPD_FORCE is set to 1, 1: enable DAC_1 output. 0: disable DAC_1 output. 537 | 11 538 | 1 539 | read-write 540 | 541 | 542 | PDAC1_DAC_XPD_FORCE 543 | 1: use RTCIO_PDAC1_XPD_DAC to control DAC_1 output. 0: use SAR ADC FSM to control DAC_1 output. 544 | 12 545 | 1 546 | read-write 547 | 548 | 549 | PDAC1_FUN_IE 550 | Input enable in normal execution. 551 | 13 552 | 1 553 | read-write 554 | 555 | 556 | PDAC1_SLP_OE 557 | Output enable in sleep mode 558 | 14 559 | 1 560 | read-write 561 | 562 | 563 | PDAC1_SLP_IE 564 | Input enable in sleep mode 565 | 15 566 | 1 567 | read-write 568 | 569 | 570 | PDAC1_SLP_SEL 571 | 1: enable sleep mode. 0: no sleep mode 572 | 16 573 | 1 574 | read-write 575 | 576 | 577 | PDAC1_FUN_SEL 578 | DAC_1 function selection. 579 | 17 580 | 2 581 | read-write 582 | 583 | 584 | PDAC1_MUX_SEL 585 | 1: use RTC GPIO. 0: use digital GPIO 586 | 19 587 | 1 588 | read-write 589 | 590 | 591 | PDAC1_RUE 592 | Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 593 | 27 594 | 1 595 | read-write 596 | 597 | 598 | PDAC1_RDE 599 | Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 600 | 28 601 | 1 602 | read-write 603 | 604 | 605 | PDAC1_DRV 606 | Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 607 | 29 608 | 2 609 | read-write 610 | 611 | 612 | 613 | 614 | PAD_DAC2 615 | DAC2 configuration register 616 | 0xCC 617 | 0x20 618 | 0x40000000 619 | 620 | 621 | PDAC2_DAC 622 | Configure DAC_2 output when RTCIO_PDAC2_DAC_XPD_FORCE is set to 1. 623 | 3 624 | 8 625 | read-write 626 | 627 | 628 | PDAC2_XPD_DAC 629 | When RTCIO_PDAC2_DAC_XPD_FORCE is set to 1, 1: enable DAC_2 output. 0: disable DAC_2 output. 630 | 11 631 | 1 632 | read-write 633 | 634 | 635 | PDAC2_DAC_XPD_FORCE 636 | 1: use RTCIO_PDAC2_XPD_DAC to control DAC_2 output. 0: use SAR ADC FSM to control DAC_2 output. 637 | 12 638 | 1 639 | read-write 640 | 641 | 642 | PDAC2_FUN_IE 643 | Input enable in normal execution. 644 | 13 645 | 1 646 | read-write 647 | 648 | 649 | PDAC2_SLP_OE 650 | Output enable in sleep mode. 651 | 14 652 | 1 653 | read-write 654 | 655 | 656 | PDAC2_SLP_IE 657 | Input enable in sleep mode. 658 | 15 659 | 1 660 | read-write 661 | 662 | 663 | PDAC2_SLP_SEL 664 | 1: enable sleep mode. 0: no sleep mode. 665 | 16 666 | 1 667 | read-write 668 | 669 | 670 | PDAC2_FUN_SEL 671 | DAC_2 function selection. 672 | 17 673 | 2 674 | read-write 675 | 676 | 677 | PDAC2_MUX_SEL 678 | 1: use RTC GPIO. 0: use digital GPIO. 679 | 19 680 | 1 681 | read-write 682 | 683 | 684 | PDAC2_RUE 685 | Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 686 | 27 687 | 1 688 | read-write 689 | 690 | 691 | PDAC2_RDE 692 | Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 693 | 28 694 | 1 695 | read-write 696 | 697 | 698 | PDAC2_DRV 699 | Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 700 | 29 701 | 2 702 | read-write 703 | 704 | 705 | 706 | 707 | RTC_PAD19 708 | Touch pad 19 configuration register 709 | 0xD0 710 | 0x20 711 | 0x50000000 712 | 713 | 714 | FUN_IE 715 | Input enable in normal execution. 716 | 13 717 | 1 718 | read-write 719 | 720 | 721 | SLP_OE 722 | Output enable in sleep mode. 723 | 14 724 | 1 725 | read-write 726 | 727 | 728 | SLP_IE 729 | Input enable in sleep mode. 730 | 15 731 | 1 732 | read-write 733 | 734 | 735 | SLP_SEL 736 | 1: enable sleep mode. 0: no sleep mode 737 | 16 738 | 1 739 | read-write 740 | 741 | 742 | FUN_SEL 743 | Function selection. 744 | 17 745 | 2 746 | read-write 747 | 748 | 749 | MUX_SEL 750 | 1: use RTC GPIO. 0: use digital GPIO. 751 | 19 752 | 1 753 | read-write 754 | 755 | 756 | RUE 757 | Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 758 | 27 759 | 1 760 | read-write 761 | 762 | 763 | RDE 764 | Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 765 | 28 766 | 1 767 | read-write 768 | 769 | 770 | DRV 771 | Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 772 | 29 773 | 2 774 | read-write 775 | 776 | 777 | 778 | 779 | RTC_PAD20 780 | Touch pad 20 configuration register 781 | 0xD4 782 | 0x20 783 | 0x50000000 784 | 785 | 786 | FUN_IE 787 | Input enable in normal execution. 788 | 13 789 | 1 790 | read-write 791 | 792 | 793 | SLP_OE 794 | Output enable in sleep mode. 795 | 14 796 | 1 797 | read-write 798 | 799 | 800 | SLP_IE 801 | Input enable in sleep mode. 802 | 15 803 | 1 804 | read-write 805 | 806 | 807 | SLP_SEL 808 | 1: enable sleep mode. 0: no sleep mode. 809 | 16 810 | 1 811 | read-write 812 | 813 | 814 | FUN_SEL 815 | Function selection. 816 | 17 817 | 2 818 | read-write 819 | 820 | 821 | MUX_SEL 822 | 1: use RTC GPIO. 0: use digital GPIO. 823 | 19 824 | 1 825 | read-write 826 | 827 | 828 | RUE 829 | Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 830 | 27 831 | 1 832 | read-write 833 | 834 | 835 | RDE 836 | Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 837 | 28 838 | 1 839 | read-write 840 | 841 | 842 | DRV 843 | Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 844 | 29 845 | 2 846 | read-write 847 | 848 | 849 | 850 | 851 | RTC_PAD21 852 | Touch pad 21 configuration register 853 | 0xD8 854 | 0x20 855 | 0x50000000 856 | 857 | 858 | FUN_IE 859 | Input enable in normal execution. 860 | 13 861 | 1 862 | read-write 863 | 864 | 865 | SLP_OE 866 | Output enable in sleep mode. 867 | 14 868 | 1 869 | read-write 870 | 871 | 872 | SLP_IE 873 | Input enable in sleep mode. 874 | 15 875 | 1 876 | read-write 877 | 878 | 879 | SLP_SEL 880 | 1: enable sleep mode. 0: no sleep mode. 881 | 16 882 | 1 883 | read-write 884 | 885 | 886 | FUN_SEL 887 | Function selection. 888 | 17 889 | 2 890 | read-write 891 | 892 | 893 | MUX_SEL 894 | 1: use RTC GPIO. 0: use digital GPIO. 895 | 19 896 | 1 897 | read-write 898 | 899 | 900 | RUE 901 | Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 902 | 27 903 | 1 904 | read-write 905 | 906 | 907 | RDE 908 | Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 909 | 28 910 | 1 911 | read-write 912 | 913 | 914 | DRV 915 | Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. 916 | 29 917 | 2 918 | read-write 919 | 920 | 921 | 922 | 923 | EXT_WAKEUP0 924 | External wake up configuration register 925 | 0xDC 926 | 0x20 927 | 928 | 929 | SEL 930 | GPIO[0-17] can be used to wake up the chip when the chip is in the sleep mode. This register prompts the pad source to wake up the chip when the latter is indeep/light sleep mode. 931 | 0: select GPIO0; 1: select GPIO2, etc 932 | 27 933 | 5 934 | read-write 935 | 936 | 937 | 938 | 939 | XTL_EXT_CTR 940 | Crystal power down enable GPIO source 941 | 0xE0 942 | 0x20 943 | 944 | 945 | SEL 946 | Select the external crystal power down enable source to get into sleep mode. 0: select GPIO0. 1: select GPIO1, etc. The input value on this pin XOR RTC_CNTL_EXT_XTL_CONF_REG[30] is the crystal power down enable signal. 947 | 27 948 | 5 949 | read-write 950 | 951 | 952 | 953 | 954 | SAR_I2C_IO 955 | RTC I2C pad selection 956 | 0xE4 957 | 0x20 958 | 959 | 960 | SAR_DEBUG_BIT_SEL 961 | 23 962 | 5 963 | read-write 964 | 965 | 966 | SAR_I2C_SCL_SEL 967 | Selects a pad the RTC I2C SCL signal connects to. 0: use TOUCH PAD0. 1: use TOUCH PAD2. 968 | 28 969 | 2 970 | read-write 971 | 972 | 973 | SAR_I2C_SDA_SEL 974 | Selects a pad the RTC I2C SDA signal connects to. 0: use TOUCH PAD1. 1: use TOUCH PAD3. 975 | 30 976 | 2 977 | read-write 978 | 979 | 980 | 981 | 982 | RTC_IO_TOUCH_CTRL 983 | Touch control register 984 | 0xE8 985 | 0x20 986 | 987 | 988 | IO_TOUCH_BUFSEL 989 | 0 990 | 4 991 | read-write 992 | 993 | 994 | IO_TOUCH_BUFMODE 995 | 4 996 | 1 997 | read-write 998 | 999 | 1000 | 1001 | 1002 | RTC_IO_DATE 1003 | Version control register 1004 | 0x1FC 1005 | 0x20 1006 | 0x01903170 1007 | 1008 | 1009 | IO_DATE 1010 | Version control register 1011 | 0 1012 | 28 1013 | read-write 1014 | 1015 | 1016 | 1017 | 1018 | 1019 | 1020 | RTC_CNTL 1021 | Real-Time Clock Control 1022 | RTC_CNTL 1023 | 0x00008000 1024 | 1025 | 0x0 1026 | 0x138 1027 | registers 1028 | 1029 | 1030 | RISCV_START_INT 1031 | 6 1032 | 1033 | 1034 | SW_INT 1035 | 7 1036 | 1037 | 1038 | SWD_INT 1039 | 8 1040 | 1041 | 1042 | 1043 | ULP_CP_TIMER 1044 | Configure coprocessor timer 1045 | 0xF8 1046 | 0x20 1047 | 1048 | 1049 | ULP_CP_PC_INIT 1050 | ULP coprocessor PC initial address 1051 | 0 1052 | 11 1053 | read-write 1054 | 1055 | 1056 | ULP_CP_GPIO_WAKEUP_ENA 1057 | Enable the option of ULP coprocessor woken up by 1058 | RTC GPIO 1059 | 29 1060 | 1 1061 | read-write 1062 | 1063 | 1064 | ULP_CP_GPIO_WAKEUP_CLR 1065 | Disable the option of ULP coprocessor woken up by 1066 | RTC GPIO 1067 | 30 1068 | 1 1069 | write-only 1070 | 1071 | 1072 | ULP_CP_SLP_TIMER_EN 1073 | ULP coprocessor timer enable bit. 0: Disable hardware 1074 | Timer. 1: Enable hardware timer 1075 | 31 1076 | 1 1077 | read-write 1078 | 1079 | 1080 | 1081 | 1082 | ULP_CP_CTRL 1083 | ULP-FSM configuration register 1084 | 0xFC 1085 | 0x20 1086 | 0x00100200 1087 | 1088 | 1089 | ULP_CP_MEM_ADDR_INIT 1090 | 0 1091 | 11 1092 | read-write 1093 | 1094 | 1095 | ULP_CP_MEM_ADDR_SIZE 1096 | 11 1097 | 11 1098 | read-write 1099 | 1100 | 1101 | ULP_CP_MEM_OFFSET_CLR 1102 | 22 1103 | 1 1104 | write-only 1105 | 1106 | 1107 | ULP_CP_CLK_FO 1108 | ULP-FSM clock force on 1109 | 28 1110 | 1 1111 | read-write 1112 | 1113 | 1114 | ULP_CP_RESET 1115 | ULP-FSM clock software reset 1116 | 29 1117 | 1 1118 | read-write 1119 | 1120 | 1121 | ULP_CP_FORCE_START_TOP 1122 | Write 1 to start ULP-FSM by software 1123 | 30 1124 | 1 1125 | read-write 1126 | 1127 | 1128 | ULP_CP_START_TOP 1129 | Write 1 to start ULP-FSM 1130 | 31 1131 | 1 1132 | read-write 1133 | 1134 | 1135 | 1136 | 1137 | COCPU_CTRL 1138 | ULP-RISCV configuration register 1139 | 0x100 1140 | 0x20 1141 | 0x008A0810 1142 | 1143 | 1144 | COCPU_CLK_FO 1145 | ULP-RISCV clock force on 1146 | 0 1147 | 1 1148 | read-write 1149 | 1150 | 1151 | COCPU_START_2_RESET_DIS 1152 | Time from ULP-RISCV startup to pull down reset 1153 | 1 1154 | 6 1155 | read-write 1156 | 1157 | 1158 | COCPU_START_2_INTR_EN 1159 | Time from ULP-RISCV startup to send out 1160 | RISCV_START_INT interrupt 1161 | 7 1162 | 6 1163 | read-write 1164 | 1165 | 1166 | COCPU_SHUT 1167 | Shut down ULP-RISCV 1168 | 13 1169 | 1 1170 | read-write 1171 | 1172 | 1173 | COCPU_SHUT_2_CLK_DIS 1174 | Time from shut down ULP-RISCV to disable clock 1175 | 14 1176 | 8 1177 | read-write 1178 | 1179 | 1180 | COCPU_SHUT_RESET_EN 1181 | This bit is used to reset ULP-RISCV 1182 | 22 1183 | 1 1184 | read-write 1185 | 1186 | 1187 | COCPU_SEL 1188 | 0: select ULP-RISCV. 1: select ULP-FSM 1189 | 23 1190 | 1 1191 | read-write 1192 | 1193 | 1194 | COCPU_DONE_FORCE 1195 | 0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE 1196 | signal 1197 | 24 1198 | 1 1199 | read-write 1200 | 1201 | 1202 | COCPU_DONE 1203 | DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the 1204 | timer starts counting 1205 | 25 1206 | 1 1207 | read-write 1208 | 1209 | 1210 | COCPU_SW_INT_TRIGGER 1211 | Trigger ULP-RISCV register interrupt 1212 | 26 1213 | 1 1214 | write-only 1215 | 1216 | 1217 | 1218 | 1219 | ULP_CP_TIMER_1 1220 | Configure sleep cycle of the timer 1221 | 0x130 1222 | 0x20 1223 | 0x0000C800 1224 | 1225 | 1226 | ULP_CP_TIMER_SLP_CYCLE 1227 | Set sleep cycles for ULP coprocessor timer 1228 | 8 1229 | 24 1230 | read-write 1231 | 1232 | 1233 | 1234 | 1235 | 1236 | 1237 | RTC_I2C 1238 | Low-power I2C (Inter-Integrated Circuit) Controller 1239 | RTC_I2C 1240 | 0x0000EC00 1241 | 1242 | 0x0 1243 | 0x7C 1244 | registers 1245 | 1246 | 1247 | 1248 | SCL_LOW 1249 | Configure the low level width of SCL 1250 | 0x0 1251 | 0x20 1252 | 0x00000100 1253 | 1254 | 1255 | PERIOD 1256 | This register is used to configure how many clock cycles SCL 1257 | remains low. 1258 | 0 1259 | 20 1260 | read-write 1261 | 1262 | 1263 | 1264 | 1265 | CTRL 1266 | Transmission setting 1267 | 0x4 1268 | 0x20 1269 | 1270 | 1271 | SDA_FORCE_OUT 1272 | SDA output mode. 0: open drain. 1: push pull. 1273 | 0 1274 | 1 1275 | read-write 1276 | 1277 | 1278 | SCL_FORCE_OUT 1279 | SCL output mode. 0: open drain. 1: push pull. 1280 | 1 1281 | 1 1282 | read-write 1283 | 1284 | 1285 | MS_MODE 1286 | Set this bit to configure RTC I²C as a master. 1287 | 2 1288 | 1 1289 | read-write 1290 | 1291 | 1292 | TRANS_START 1293 | Set this bit to 1, RTC I2C starts sending data. 1294 | 3 1295 | 1 1296 | read-write 1297 | 1298 | 1299 | TX_LSB_FIRST 1300 | This bit is used to control the sending mode. 0: send data from the most 1301 | significant bit. 1: send data from the least significant bit. 1302 | 4 1303 | 1 1304 | read-write 1305 | 1306 | 1307 | RX_LSB_FIRST 1308 | This bit is used to control the storage mode for received data. 0: receive 1309 | data from the most significant bit. 1: receive data from the least significant bit. 1310 | 5 1311 | 1 1312 | read-write 1313 | 1314 | 1315 | CLK_GATE_EN 1316 | RTC I²C controller clock gate. 1317 | 29 1318 | 1 1319 | read-write 1320 | 1321 | 1322 | RESET 1323 | RTC I²C software reset. 1324 | 30 1325 | 1 1326 | read-write 1327 | 1328 | 1329 | CLK_EN 1330 | rtc i2c reg clk gating 1331 | 31 1332 | 1 1333 | read-write 1334 | 1335 | 1336 | 1337 | 1338 | STATUS 1339 | RTC I2C status 1340 | 0x8 1341 | 0x20 1342 | 1343 | 1344 | ACK_REC 1345 | The received ACK value. 0: ACK. 1: NACK. 1346 | 0 1347 | 1 1348 | read-only 1349 | 1350 | 1351 | SLAVE_RW 1352 | 0: master writes to slave. 1: master reads from slave. 1353 | 1 1354 | 1 1355 | read-only 1356 | 1357 | 1358 | ARB_LOST 1359 | When the RTC I2C loses control of SCL line, the register changes to 1. 1360 | 2 1361 | 1 1362 | read-only 1363 | 1364 | 1365 | BUS_BUSY 1366 | 0: RTC I2C bus is in idle state. 1: RTC I2C bus is busy transferring data. 1367 | 3 1368 | 1 1369 | read-only 1370 | 1371 | 1372 | SLAVE_ADDRESSED 1373 | When the address sent by the master matches the address of the 1374 | slave, then this bit will be set. 1375 | 4 1376 | 1 1377 | read-only 1378 | 1379 | 1380 | BYTE_TRANS 1381 | This field changes to 1 when one byte is transferred. 1382 | 5 1383 | 1 1384 | read-only 1385 | 1386 | 1387 | OP_CNT 1388 | Indicate which operation is working. 1389 | 6 1390 | 2 1391 | read-only 1392 | 1393 | 1394 | SHIFT 1395 | shifter content 1396 | 16 1397 | 8 1398 | read-only 1399 | 1400 | 1401 | SCL_MAIN_STATE_LAST 1402 | i2c last main status 1403 | 24 1404 | 3 1405 | read-only 1406 | 1407 | 1408 | SCL_STATE_LAST 1409 | scl last status 1410 | 28 1411 | 3 1412 | read-only 1413 | 1414 | 1415 | 1416 | 1417 | TO 1418 | Configure RTC I2C timeout 1419 | 0xC 1420 | 0x20 1421 | 0x00010000 1422 | 1423 | 1424 | TIME_OUT 1425 | Timeout threshold 1426 | 0 1427 | 20 1428 | read-write 1429 | 1430 | 1431 | 1432 | 1433 | SLAVE_ADDR 1434 | Configure slave address 1435 | 0x10 1436 | 0x20 1437 | 1438 | 1439 | SLAVE_ADDR 1440 | slave address 1441 | 0 1442 | 15 1443 | read-write 1444 | 1445 | 1446 | ADDR_10BIT_EN 1447 | This field is used to enable the slave 10-bit addressing mode. 1448 | 31 1449 | 1 1450 | read-write 1451 | 1452 | 1453 | 1454 | 1455 | SCL_HIGH 1456 | Configure the high level width of SCL 1457 | 0x14 1458 | 0x20 1459 | 0x00000100 1460 | 1461 | 1462 | PERIOD 1463 | This register is used to configure how many cycles SCL remains high. 1464 | 0 1465 | 20 1466 | read-write 1467 | 1468 | 1469 | 1470 | 1471 | SDA_DUTY 1472 | Configure the SDA hold time after a negative 1473 | SCL edge 1474 | 0x18 1475 | 0x20 1476 | 0x00000010 1477 | 1478 | 1479 | NUM 1480 | The number of clock cycles between the SDA switch and the falling 1481 | edge of SCL. 1482 | 0 1483 | 20 1484 | read-write 1485 | 1486 | 1487 | 1488 | 1489 | SCL_START_PERIOD 1490 | Configure the delay between the SDA and SCL 1491 | negative edge for a start condition 1492 | 0x1C 1493 | 0x20 1494 | 0x00000008 1495 | 1496 | 1497 | SCL_START_PERIOD 1498 | Number of clock cycles to wait after generating a start condition. 1499 | 0 1500 | 20 1501 | read-write 1502 | 1503 | 1504 | 1505 | 1506 | SCL_STOP_PERIOD 1507 | Configure the delay between SDA and SCL positive edge for a stop condition 1508 | 0x20 1509 | 0x20 1510 | 0x00000008 1511 | 1512 | 1513 | SCL_STOP_PERIOD 1514 | Number of clock cycles to wait before generating a stop condition. 1515 | 0 1516 | 20 1517 | read-write 1518 | 1519 | 1520 | 1521 | 1522 | INT_CLR 1523 | Clear RTC I2C interrupt 1524 | 0x24 1525 | 0x20 1526 | 1527 | 1528 | SLAVE_TRAN_COMP_INT_CLR 1529 | RTC_I2C_SLAVE_TRAN_COMP_INT interrupt clear bit 1530 | 0 1531 | 1 1532 | write-only 1533 | 1534 | 1535 | ARBITRATION_LOST_INT_CLR 1536 | RTC_I2C_ARBITRATION_LOST_INT interrupt clear bit 1537 | 1 1538 | 1 1539 | write-only 1540 | 1541 | 1542 | MASTER_TRAN_COMP_INT_CLR 1543 | RTC_I2C_MASTER_TRAN_COMP_INT interrupt 1544 | clear bit 1545 | 2 1546 | 1 1547 | write-only 1548 | 1549 | 1550 | TRANS_COMPLETE_INT_CLR 1551 | RTC_I2C_TRANS_COMPLETE_INT interrupt clear bit 1552 | 3 1553 | 1 1554 | write-only 1555 | 1556 | 1557 | TIME_OUT_INT_CLR 1558 | RTC_I2C_TIME_OUT_INT interrupt clear bit 1559 | 4 1560 | 1 1561 | write-only 1562 | 1563 | 1564 | ACK_ERR_INT_CLR 1565 | RTC_I2C_ACK_ERR_INT interrupt clear bit 1566 | 5 1567 | 1 1568 | write-only 1569 | 1570 | 1571 | RX_DATA_INT_CLR 1572 | RTC_I2C_RX_DATA_INT interrupt clear bit 1573 | 6 1574 | 1 1575 | write-only 1576 | 1577 | 1578 | TX_DATA_INT_CLR 1579 | RTC_I2C_TX_DATA_INT interrupt clear bit 1580 | 7 1581 | 1 1582 | write-only 1583 | 1584 | 1585 | DETECT_START_INT_CLR 1586 | RTC_I2C_DETECT_START_INT interrupt clear bit 1587 | 8 1588 | 1 1589 | write-only 1590 | 1591 | 1592 | 1593 | 1594 | INT_RAW 1595 | RTC I2C raw interrupt 1596 | 0x28 1597 | 0x20 1598 | 1599 | 1600 | SLAVE_TRAN_COMP_INT_RAW 1601 | RTC_I2C_SLAVE_TRAN_COMP_INT interrupt raw bit 1602 | 0 1603 | 1 1604 | read-only 1605 | 1606 | 1607 | ARBITRATION_LOST_INT_RAW 1608 | RTC_I2C_ARBITRATION_LOST_INT interrupt raw bit 1609 | 1 1610 | 1 1611 | read-only 1612 | 1613 | 1614 | MASTER_TRAN_COMP_INT_RAW 1615 | RTC_I2C_MASTER_TRAN_COMP_INT interrupt raw bit 1616 | 2 1617 | 1 1618 | read-only 1619 | 1620 | 1621 | TRANS_COMPLETE_INT_RAW 1622 | RTC_I2C_TRANS_COMPLETE_INT interrupt raw bit 1623 | 3 1624 | 1 1625 | read-only 1626 | 1627 | 1628 | TIME_OUT_INT_RAW 1629 | RTC_I2C_TIME_OUT_INT interrupt raw bit 1630 | 4 1631 | 1 1632 | read-only 1633 | 1634 | 1635 | ACK_ERR_INT_RAW 1636 | RTC_I2C_ACK_ERR_INT interrupt raw bit 1637 | 5 1638 | 1 1639 | read-only 1640 | 1641 | 1642 | RX_DATA_INT_RAW 1643 | RTC_I2C_RX_DATA_INT interrupt raw bit 1644 | 6 1645 | 1 1646 | read-only 1647 | 1648 | 1649 | TX_DATA_INT_RAW 1650 | RTC_I2C_TX_DATA_INT interrupt raw bit 1651 | 7 1652 | 1 1653 | read-only 1654 | 1655 | 1656 | DETECT_START_INT_RAW 1657 | RTC_I2C_DETECT_START_INT interrupt raw bit 1658 | 8 1659 | 1 1660 | read-only 1661 | 1662 | 1663 | 1664 | 1665 | INT_ST 1666 | RTC I2C interrupt status 1667 | 0x2C 1668 | 0x20 1669 | 1670 | 1671 | SLAVE_TRAN_COMP_INT_ST 1672 | RTC_I2C_SLAVE_TRAN_COMP_INT interrupt status bit 1673 | 0 1674 | 1 1675 | read-only 1676 | 1677 | 1678 | ARBITRATION_LOST_INT_ST 1679 | RTC_I2C_ARBITRATION_LOST_INT interrupt status bit 1680 | 1 1681 | 1 1682 | read-only 1683 | 1684 | 1685 | MASTER_TRAN_COMP_INT_ST 1686 | RTC_I2C_MASTER_TRAN_COMP_INT interrupt status bit 1687 | 2 1688 | 1 1689 | read-only 1690 | 1691 | 1692 | TRANS_COMPLETE_INT_ST 1693 | RTC_I2C_TRANS_COMPLETE_INT interrupt status bit 1694 | 3 1695 | 1 1696 | read-only 1697 | 1698 | 1699 | TIME_OUT_INT_ST 1700 | RTC_I2C_TIME_OUT_INT interrupt status bit 1701 | 4 1702 | 1 1703 | read-only 1704 | 1705 | 1706 | ACK_ERR_INT_ST 1707 | RTC_I2C_ACK_ERR_INT interrupt status bit 1708 | 5 1709 | 1 1710 | read-only 1711 | 1712 | 1713 | RX_DATA_INT_ST 1714 | RTC_I2C_RX_DATA_INT interrupt status bit 1715 | 6 1716 | 1 1717 | read-only 1718 | 1719 | 1720 | TX_DATA_INT_ST 1721 | RTC_I2C_TX_DATA_INT interrupt status bit 1722 | 7 1723 | 1 1724 | read-only 1725 | 1726 | 1727 | DETECT_START_INT_ST 1728 | RTC_I2C_DETECT_START_INT interrupt status bit 1729 | 8 1730 | 1 1731 | read-only 1732 | 1733 | 1734 | 1735 | 1736 | INT_ENA 1737 | Enable RTC I2C interrupt 1738 | 0x30 1739 | 0x20 1740 | 1741 | 1742 | SLAVE_TRAN_COMP_INT_ENA 1743 | RTC_I2C_SLAVE_TRAN_COMP_INT interrupt enable bit 1744 | 0 1745 | 1 1746 | read-write 1747 | 1748 | 1749 | ARBITRATION_LOST_INT_ENA 1750 | RTC_I2C_ARBITRATION_LOST_INT interrupt enable bit 1751 | 1 1752 | 1 1753 | read-write 1754 | 1755 | 1756 | MASTER_TRAN_COMP_INT_ENA 1757 | RTC_I2C_MASTER_TRAN_COMP_INT interrupt enable bit 1758 | 2 1759 | 1 1760 | read-write 1761 | 1762 | 1763 | TRANS_COMPLETE_INT_ENA 1764 | RTC_I2C_TRANS_COMPLETE_INT interrupt enable bit 1765 | 3 1766 | 1 1767 | read-write 1768 | 1769 | 1770 | TIME_OUT_INT_ENA 1771 | RTC_I2C_TIME_OUT_INT interrupt enable bit 1772 | 4 1773 | 1 1774 | read-write 1775 | 1776 | 1777 | ACK_ERR_INT_ENA 1778 | RTC_I2C_ACK_ERR_INT interrupt enable bit 1779 | 5 1780 | 1 1781 | read-write 1782 | 1783 | 1784 | RX_DATA_INT_ENA 1785 | RTC_I2C_RX_DATA_INT interrupt enable bit 1786 | 6 1787 | 1 1788 | read-write 1789 | 1790 | 1791 | TX_DATA_INT_ENA 1792 | RTC_I2C_TX_DATA_INT interrupt enable bit 1793 | 7 1794 | 1 1795 | read-write 1796 | 1797 | 1798 | DETECT_START_INT_ENA 1799 | RTC_I2C_DETECT_START_INT interrupt enable bit 1800 | 8 1801 | 1 1802 | read-write 1803 | 1804 | 1805 | 1806 | 1807 | DATA 1808 | RTC I2C read data 1809 | 0x34 1810 | 0x20 1811 | 1812 | 1813 | RDATA 1814 | Data received 1815 | 0 1816 | 8 1817 | read-only 1818 | 1819 | 1820 | SLAVE_TX_DATA 1821 | The data sent by slave 1822 | 8 1823 | 8 1824 | read-write 1825 | 1826 | 1827 | DONE 1828 | RTC I2C transmission is done. 1829 | 31 1830 | 1 1831 | read-only 1832 | 1833 | 1834 | 1835 | 1836 | CMD0 1837 | RTC I2C Command 0 1838 | 0x38 1839 | 0x20 1840 | 0x00000903 1841 | 1842 | 1843 | COMMAND0 1844 | Content of command 0. For more information, please refer to the register 1845 | I2C_COMD0_REG in Chapter I²C Controller 1846 | 0 1847 | 14 1848 | read-write 1849 | 1850 | 1851 | COMMAND0_DONE 1852 | When command 0 is done, this bit changes to 1. 1853 | 31 1854 | 1 1855 | read-only 1856 | 1857 | 1858 | 1859 | 1860 | CMD1 1861 | RTC I2C Command 1 1862 | 0x3C 1863 | 0x20 1864 | 0x00001901 1865 | 1866 | 1867 | COMMAND1 1868 | Content of command 1. For more information, please refer to the register 1869 | I2C_COMD1_REG in Chapter I²C Controller. 1870 | 0 1871 | 14 1872 | read-write 1873 | 1874 | 1875 | COMMAND1_DONE 1876 | When command 1 is done, this bit changes to 1. 1877 | 31 1878 | 1 1879 | read-only 1880 | 1881 | 1882 | 1883 | 1884 | CMD2 1885 | RTC I2C Command 2 1886 | 0x40 1887 | 0x20 1888 | 0x00000902 1889 | 1890 | 1891 | COMMAND2 1892 | Content of command 2. For more information, please refer to the register 1893 | I2C_COMD2_REG in Chapter I²C Controller. 1894 | 0 1895 | 14 1896 | read-write 1897 | 1898 | 1899 | COMMAND2_DONE 1900 | When command 2 is done, this bit changes to 1. 1901 | 31 1902 | 1 1903 | read-only 1904 | 1905 | 1906 | 1907 | 1908 | CMD3 1909 | RTC I2C Command 3 1910 | 0x44 1911 | 0x20 1912 | 0x00000101 1913 | 1914 | 1915 | COMMAND3 1916 | Content of command 3. For more information, please refer to the register 1917 | I2C_COMD3_REG in Chapter I²C Controller. 1918 | 0 1919 | 14 1920 | read-write 1921 | 1922 | 1923 | COMMAND3_DONE 1924 | When command 3 is done, this bit changes to 1. 1925 | 31 1926 | 1 1927 | read-only 1928 | 1929 | 1930 | 1931 | 1932 | CMD4 1933 | RTC I2C Command 4 1934 | 0x48 1935 | 0x20 1936 | 0x00000901 1937 | 1938 | 1939 | COMMAND4 1940 | Content of command 4. For more information, please refer to the register 1941 | I2C_COMD4_REG in Chapter I²C Controller. 1942 | 0 1943 | 14 1944 | read-write 1945 | 1946 | 1947 | COMMAND4_DONE 1948 | When command 4 is done, this bit changes to 1. 1949 | 31 1950 | 1 1951 | read-only 1952 | 1953 | 1954 | 1955 | 1956 | CMD5 1957 | RTC I2C Command 5 1958 | 0x4C 1959 | 0x20 1960 | 0x00001701 1961 | 1962 | 1963 | COMMAND5 1964 | Content of command 5. For more information, please refer to the register 1965 | I2C_COMD5_REG in Chapter I²C Controller. 1966 | 0 1967 | 14 1968 | read-write 1969 | 1970 | 1971 | COMMAND5_DONE 1972 | When command 5 is done, this bit changes to 1. 1973 | 31 1974 | 1 1975 | read-only 1976 | 1977 | 1978 | 1979 | 1980 | CMD6 1981 | RTC I2C Command 6 1982 | 0x50 1983 | 0x20 1984 | 0x00001901 1985 | 1986 | 1987 | COMMAND6 1988 | Content of command 6. For more information, please refer to the register 1989 | I2C_COMD6_REG in Chapter I²C Controller. 1990 | 0 1991 | 14 1992 | read-write 1993 | 1994 | 1995 | COMMAND6_DONE 1996 | When command 6 is done, this bit changes to 1. 1997 | 31 1998 | 1 1999 | read-only 2000 | 2001 | 2002 | 2003 | 2004 | CMD7 2005 | RTC I2C Command 7 2006 | 0x54 2007 | 0x20 2008 | 0x00000904 2009 | 2010 | 2011 | COMMAND7 2012 | Content of command 7. For more information, please refer to the register 2013 | I2C_COMD7_REG in Chapter I²C Controller. 2014 | 0 2015 | 14 2016 | read-write 2017 | 2018 | 2019 | COMMAND7_DONE 2020 | When command 7 is done, this bit changes to 1. 2021 | 31 2022 | 1 2023 | read-only 2024 | 2025 | 2026 | 2027 | 2028 | CMD8 2029 | RTC I2C Command 8 2030 | 0x58 2031 | 0x20 2032 | 0x00001901 2033 | 2034 | 2035 | COMMAND8 2036 | Content of command 8. For more information, please refer to the register 2037 | I2C_COMD8_REG in Chapter I²C Controller. 2038 | 0 2039 | 14 2040 | read-write 2041 | 2042 | 2043 | COMMAND8_DONE 2044 | When command 8 is done, this bit changes to 1. 2045 | 31 2046 | 1 2047 | read-only 2048 | 2049 | 2050 | 2051 | 2052 | CMD9 2053 | RTC I2C Command 9 2054 | 0x5C 2055 | 0x20 2056 | 0x00000903 2057 | 2058 | 2059 | COMMAND9 2060 | Content of command 9. For more information, please refer to the register 2061 | I2C_COMD9_REG in Chapter I²C Controller 2062 | 0 2063 | 14 2064 | read-write 2065 | 2066 | 2067 | COMMAND9_DONE 2068 | When command 9 is done, this bit changes to 1. 2069 | 31 2070 | 1 2071 | read-only 2072 | 2073 | 2074 | 2075 | 2076 | CMD10 2077 | RTC I2C Command 10 2078 | 0x60 2079 | 0x20 2080 | 0x00000101 2081 | 2082 | 2083 | COMMAND10 2084 | Content of command 10. For more information, please refer to the register 2085 | I2C_COMD10_REG in Chapter I²C Controller. 2086 | 0 2087 | 14 2088 | read-write 2089 | 2090 | 2091 | COMMAND10_DONE 2092 | When command 10 is done, this bit changes to 1. 2093 | 31 2094 | 1 2095 | read-only 2096 | 2097 | 2098 | 2099 | 2100 | CMD11 2101 | RTC I2C Command 11 2102 | 0x64 2103 | 0x20 2104 | 0x00000901 2105 | 2106 | 2107 | COMMAND11 2108 | Content of command 11. For more information, please refer to the register 2109 | I2C_COMD11_REG in Chapter I²C Controller. 2110 | 0 2111 | 14 2112 | read-write 2113 | 2114 | 2115 | COMMAND11_DONE 2116 | When command 11 is done, this bit changes to 1. 2117 | 31 2118 | 1 2119 | read-only 2120 | 2121 | 2122 | 2123 | 2124 | CMD12 2125 | RTC I2C Command 12 2126 | 0x68 2127 | 0x20 2128 | 0x00001701 2129 | 2130 | 2131 | COMMAND12 2132 | Content of command 12. For more information, please refer to the register 2133 | I2C_COMD12_REG in Chapter I²C Controller. 2134 | 0 2135 | 14 2136 | read-write 2137 | 2138 | 2139 | COMMAND12_DONE 2140 | When command 12 is done, this bit changes to 1. 2141 | 31 2142 | 1 2143 | read-only 2144 | 2145 | 2146 | 2147 | 2148 | CMD13 2149 | RTC I2C Command 13 2150 | 0x6C 2151 | 0x20 2152 | 0x00001901 2153 | 2154 | 2155 | COMMAND13 2156 | Content of command 13. For more information, please refer to the register 2157 | I2C_COMD13_REG in Chapter I²C Controller. 2158 | 0 2159 | 14 2160 | read-write 2161 | 2162 | 2163 | COMMAND13_DONE 2164 | When command 13 is done, this bit changes to 1. 2165 | 31 2166 | 1 2167 | read-only 2168 | 2169 | 2170 | 2171 | 2172 | CMD14 2173 | RTC I2C Command 14 2174 | 0x70 2175 | 0x20 2176 | 2177 | 2178 | COMMAND14 2179 | Content of command 14. For more information, please refer to the register 2180 | I2C_COMD14_REG in Chapter I²C Controller. 2181 | 0 2182 | 14 2183 | read-write 2184 | 2185 | 2186 | COMMAND14_DONE 2187 | When command 14 is done, this bit changes to 1. 2188 | 31 2189 | 1 2190 | read-only 2191 | 2192 | 2193 | 2194 | 2195 | CMD15 2196 | RTC I2C Command 15 2197 | 0x74 2198 | 0x20 2199 | 2200 | 2201 | COMMAND15 2202 | Content of command 15. For more information, please refer to the register 2203 | I2C_COMD15_REG in Chapter I²C Controller. 2204 | 0 2205 | 14 2206 | read-write 2207 | 2208 | 2209 | COMMAND15_DONE 2210 | When command 15 is done, this bit changes to 1. 2211 | 31 2212 | 1 2213 | read-only 2214 | 2215 | 2216 | 2217 | 2218 | DATE 2219 | Version control register 2220 | 0xFC 2221 | 0x20 2222 | 0x01905310 2223 | 2224 | 2225 | DATE 2226 | Version control register 2227 | 0 2228 | 28 2229 | read-write 2230 | 2231 | 2232 | 2233 | 2234 | 2235 | 2236 | SENS 2237 | SENS Peripheral 2238 | SENS 2239 | 0x0000C800 2240 | 2241 | 0x0 2242 | 0x110 2243 | registers 2244 | 2245 | 2246 | TOUCH_DONE_INT 2247 | 0 2248 | 2249 | 2250 | TOUCH_INACTIVE_INT 2251 | 1 2252 | 2253 | 2254 | TOUCH_ACTIVE_INT 2255 | 2 2256 | 2257 | 2258 | SARADC1_DONE_INT 2259 | 3 2260 | 2261 | 2262 | SARADC2_DONE_INT 2263 | 4 2264 | 2265 | 2266 | TSENS_DONE_INT 2267 | 5 2268 | 2269 | 2270 | 2271 | SAR_SLAVE_ADDR1 2272 | Configure slave addresses 0-1 of RTC I2C 2273 | 0x40 2274 | 0x20 2275 | 2276 | 2277 | I2C_SLAVE_ADDR1 2278 | RTC I2C slave address 1 2279 | 0 2280 | 11 2281 | read-write 2282 | 2283 | 2284 | I2C_SLAVE_ADDR0 2285 | RTC I2C slave address 0 2286 | 11 2287 | 11 2288 | read-write 2289 | 2290 | 2291 | MEAS_STATUS 2292 | 22 2293 | 8 2294 | read-only 2295 | 2296 | 2297 | 2298 | 2299 | SAR_SLAVE_ADDR2 2300 | Configure slave addresses 2-3 of RTC I2C 2301 | 0x44 2302 | 0x20 2303 | 2304 | 2305 | I2C_SLAVE_ADDR3 2306 | RTC I2C slave address 3 2307 | 0 2308 | 11 2309 | read-write 2310 | 2311 | 2312 | I2C_SLAVE_ADDR2 2313 | RTC I2C slave address 2 2314 | 11 2315 | 11 2316 | read-write 2317 | 2318 | 2319 | 2320 | 2321 | SAR_SLAVE_ADDR3 2322 | Configure slave addresses 4-5 of RTC I2C 2323 | 0x48 2324 | 0x20 2325 | 2326 | 2327 | I2C_SLAVE_ADDR5 2328 | RTC I2C slave address 5 2329 | 0 2330 | 11 2331 | read-write 2332 | 2333 | 2334 | I2C_SLAVE_ADDR4 2335 | RTC I2C slave address 4 2336 | 11 2337 | 11 2338 | read-write 2339 | 2340 | 2341 | 2342 | 2343 | SAR_SLAVE_ADDR4 2344 | Configure slave addresses 6-7 of RTC I2C 2345 | 0x4C 2346 | 0x20 2347 | 2348 | 2349 | I2C_SLAVE_ADDR7 2350 | RTC I2C slave address 7 2351 | 0 2352 | 11 2353 | read-write 2354 | 2355 | 2356 | I2C_SLAVE_ADDR6 2357 | RTC I2C slave address 6 2358 | 11 2359 | 11 2360 | read-write 2361 | 2362 | 2363 | 2364 | 2365 | SAR_I2C_CTRL 2366 | Configure RTC I2C transmission 2367 | 0x58 2368 | 0x20 2369 | 2370 | 2371 | SAR_I2C_CTRL 2372 | RTC I2C control data. Active only when SENS_SAR_I2C_START_FORCE = 2373 | 1. 2374 | 0 2375 | 28 2376 | read-write 2377 | 2378 | 2379 | SAR_I2C_START 2380 | Start RTC I2C. Active only when SENS_SAR_I2C_START_FORCE = 1 2381 | 28 2382 | 1 2383 | read-write 2384 | 2385 | 2386 | SAR_I2C_START_FORCE 2387 | 0: RTC I2C started by FSM. 1: RTC I2C started by software. 2388 | 29 2389 | 1 2390 | read-write 2391 | 2392 | 2393 | 2394 | 2395 | SAR_COCPU_INT_RAW 2396 | Interrupt raw bit of ULP-RISCV 2397 | 0x128 2398 | 0x20 2399 | 2400 | 2401 | COCPU_TOUCH_DONE_INT_RAW 2402 | TOUCH_DONE_INT interrupt raw bit 2403 | 0 2404 | 1 2405 | read-only 2406 | 2407 | 2408 | COCPU_TOUCH_INACTIVE_INT_RAW 2409 | TOUCH_INACTIVE_INT interrupt raw bit 2410 | 1 2411 | 1 2412 | read-only 2413 | 2414 | 2415 | COCPU_TOUCH_ACTIVE_INT_RAW 2416 | TOUCH_ACTIVE_INT interrupt raw bit 2417 | 2 2418 | 1 2419 | read-only 2420 | 2421 | 2422 | COCPU_SARADC1_INT_RAW 2423 | SARADC1_DONE_INT interrupt raw bit 2424 | 3 2425 | 1 2426 | read-only 2427 | 2428 | 2429 | COCPU_SARADC2_INT_RAW 2430 | SARADC2_DONE_INT interrupt raw bit 2431 | 4 2432 | 1 2433 | read-only 2434 | 2435 | 2436 | COCPU_TSENS_INT_RAW 2437 | TSENS_DONE_INT interrupt raw bit 2438 | 5 2439 | 1 2440 | read-only 2441 | 2442 | 2443 | COCPU_START_INT_RAW 2444 | RISCV_START_INT interrupt raw bit 2445 | 6 2446 | 1 2447 | read-only 2448 | 2449 | 2450 | COCPU_SW_INT_RAW 2451 | SW_INT interrupt raw bit 2452 | 7 2453 | 1 2454 | read-only 2455 | 2456 | 2457 | COCPU_SWD_INT_RAW 2458 | SWD_INT interrupt raw bit 2459 | 8 2460 | 1 2461 | read-only 2462 | 2463 | 2464 | 2465 | 2466 | SAR_COCPU_INT_ENA 2467 | Interrupt enable bit of ULP-RISCV 2468 | 0x12C 2469 | 0x20 2470 | 2471 | 2472 | COCPU_TOUCH_DONE_INT_ENA 2473 | TOUCH_DONE_INT interrupt enable bit 2474 | 0 2475 | 1 2476 | read-write 2477 | 2478 | 2479 | COCPU_TOUCH_INACTIVE_INT_ENA 2480 | TOUCH_INACTIVE_INT interrupt enable bit 2481 | 1 2482 | 1 2483 | read-write 2484 | 2485 | 2486 | COCPU_TOUCH_ACTIVE_INT_ENA 2487 | TOUCH_ACTIVE_INT interrupt enable bit 2488 | 2 2489 | 1 2490 | read-write 2491 | 2492 | 2493 | COCPU_SARADC1_INT_ENA 2494 | SARADC1_DONE_INT interrupt enable bit 2495 | 3 2496 | 1 2497 | read-write 2498 | 2499 | 2500 | COCPU_SARADC2_INT_ENA 2501 | SARADC2_DONE_INT interrupt enable bit 2502 | 4 2503 | 1 2504 | read-write 2505 | 2506 | 2507 | COCPU_TSENS_INT_ENA 2508 | TSENS_DONE_INT interrupt enable bit 2509 | 5 2510 | 1 2511 | read-write 2512 | 2513 | 2514 | COCPU_START_INT_ENA 2515 | RISCV_START_INT interrupt enable bit 2516 | 6 2517 | 1 2518 | read-write 2519 | 2520 | 2521 | COCPU_SW_INT_ENA 2522 | SW_INT interrupt enable bit 2523 | 7 2524 | 1 2525 | read-write 2526 | 2527 | 2528 | COCPU_SWD_INT_ENA 2529 | SWD_INT interrupt enable bit 2530 | 8 2531 | 1 2532 | read-write 2533 | 2534 | 2535 | 2536 | 2537 | SAR_COCPU_INT_ST 2538 | Interrupt status bit of ULP-RISCV 2539 | 0x130 2540 | 0x20 2541 | 2542 | 2543 | COCPU_TOUCH_DONE_INT_ST 2544 | TOUCH_DONE_INT interrupt status bit 2545 | 0 2546 | 1 2547 | read-only 2548 | 2549 | 2550 | COCPU_TOUCH_INACTIVE_INT_ST 2551 | TOUCH_INACTIVE_INT interrupt status bit 2552 | 1 2553 | 1 2554 | read-only 2555 | 2556 | 2557 | COCPU_TOUCH_ACTIVE_INT_ST 2558 | TOUCH_ACTIVE_INT interrupt status bit 2559 | 2 2560 | 1 2561 | read-only 2562 | 2563 | 2564 | COCPU_SARADC1_INT_ST 2565 | SARADC1_DONE_INT interrupt status bit 2566 | 3 2567 | 1 2568 | read-only 2569 | 2570 | 2571 | COCPU_SARADC2_INT_ST 2572 | SARADC2_DONE_INT interrupt status bit 2573 | 4 2574 | 1 2575 | read-only 2576 | 2577 | 2578 | COCPU_TSENS_INT_ST 2579 | TSENS_DONE_INT interrupt status bit 2580 | 5 2581 | 1 2582 | read-only 2583 | 2584 | 2585 | COCPU_START_INT_ST 2586 | RISCV_START_INT interrupt status bit 2587 | 6 2588 | 1 2589 | read-only 2590 | 2591 | 2592 | COCPU_SW_INT_ST 2593 | SW_INT interrupt status bit 2594 | 7 2595 | 1 2596 | read-only 2597 | 2598 | 2599 | COCPU_SWD_INT_ST 2600 | SWD_INT interrupt status bit 2601 | 8 2602 | 1 2603 | read-only 2604 | 2605 | 2606 | 2607 | 2608 | SAR_COCPU_INT_CLR 2609 | Interrupt clear bit of ULP-RISCV 2610 | 0x134 2611 | 0x20 2612 | 2613 | 2614 | COCPU_TOUCH_DONE_INT_CLR 2615 | TOUCH_DONE_INT interrupt clear bit 2616 | 0 2617 | 1 2618 | write-only 2619 | 2620 | 2621 | COCPU_TOUCH_INACTIVE_INT_CLR 2622 | TOUCH_INACTIVE_INT interrupt clear bit 2623 | 1 2624 | 1 2625 | write-only 2626 | 2627 | 2628 | COCPU_TOUCH_ACTIVE_INT_CLR 2629 | TOUCH_ACTIVE_INT interrupt clear bit 2630 | 2 2631 | 1 2632 | write-only 2633 | 2634 | 2635 | COCPU_SARADC1_INT_CLR 2636 | SARADC1_DONE_INT interrupt clear bit 2637 | 3 2638 | 1 2639 | write-only 2640 | 2641 | 2642 | COCPU_SARADC2_INT_CLR 2643 | SARADC2_DONE_INT interrupt clear bit 2644 | 4 2645 | 1 2646 | write-only 2647 | 2648 | 2649 | COCPU_TSENS_INT_CLR 2650 | TSENS_DONE_INT interrupt clear bit 2651 | 5 2652 | 1 2653 | write-only 2654 | 2655 | 2656 | COCPU_START_INT_CLR 2657 | RISCV_START_INT interrupt clear bit 2658 | 6 2659 | 1 2660 | write-only 2661 | 2662 | 2663 | COCPU_SW_INT_CLR 2664 | SW_INT interrupt clear bit 2665 | 7 2666 | 1 2667 | write-only 2668 | 2669 | 2670 | COCPU_SWD_INT_CLR 2671 | SWD_INT interrupt clear bit 2672 | 8 2673 | 1 2674 | write-only 2675 | 2676 | 2677 | 2678 | 2679 | 2680 | 2681 | --------------------------------------------------------------------------------