├── .github ├── ISSUE_TEMPLATE.md └── PULL_REQUEST_TEMPLATE.md ├── .gitignore ├── .gitmodules ├── .travis.yml ├── LICENSE.Berkeley ├── LICENSE.SiFive ├── LICENSE.jtag ├── Makefrag ├── README-rocketchip.md ├── README.md ├── README_LvNA.md ├── README_TRAVIS.md ├── bootrom ├── .gitignore ├── Makefile ├── bootrom.S └── linker.ld ├── csrc ├── client.c └── dmi.h ├── emulator ├── .gitignore ├── Makefile └── Makefrag-verilator ├── fpga ├── .gitignore ├── Makefile ├── Makefile.check ├── Makefile.sw ├── README.md ├── board │ ├── common.tcl │ ├── sidewinder │ │ ├── bd │ │ │ └── prm.tcl │ │ ├── constr │ │ │ └── constr.xdc │ │ ├── mk.tcl │ │ ├── rtl │ │ │ ├── addr_mapper.v │ │ │ └── system_top.v │ │ └── vivado │ │ │ ├── README.md │ │ │ └── sidewinder │ │ │ └── Fidus │ │ │ └── 2.0 │ │ │ ├── Fidus.jpeg │ │ │ ├── board.xml │ │ │ └── preset.xml │ ├── ultraZ │ │ ├── bd │ │ │ └── prm.tcl │ │ ├── constr │ │ │ └── constr.xdc │ │ ├── mk.tcl │ │ └── rtl │ │ │ ├── addr_mapper.v │ │ │ └── system_top.v │ ├── zcu102 │ │ ├── bd │ │ │ └── prm.tcl │ │ ├── constr │ │ │ └── constr.xdc │ │ ├── mk.tcl │ │ ├── patch │ │ │ └── 0001-patch-for-new-version-of-zcu102.patch │ │ └── rtl │ │ │ ├── addr_mapper.v │ │ │ └── system_top.v │ └── zedboard │ │ ├── bd │ │ └── prm.tcl │ │ ├── constr │ │ └── constr.xdc │ │ ├── mk.tcl │ │ └── rtl │ │ ├── addr_mapper.v │ │ └── system_top.v ├── boot │ ├── .gitignore │ ├── README.md │ ├── bootgen-zynq.bif │ ├── bootgen-zynqmp.bif │ ├── bug-list.md │ └── mk.tcl ├── doc │ ├── lazy_module.md │ ├── openocd-rpc-on-smp.md │ ├── riscv-pard-fpga-how-to.md │ ├── riscv-pard-fpga-old.md │ ├── rocketchip-bus.md │ ├── rocketchip-pcie-ssd-debian.md │ ├── rocketchip_config_detail.md │ ├── rocketchip_linux_kernel_clock.md │ ├── rocketchip_on_pard_details.md │ ├── rocketchip_on_pard_journal_tailored.md │ └── rocketchip_on_pard_simulation.md ├── emu │ ├── Makefile │ ├── gen_bin.sh │ ├── gen_dtb_bin.sh │ ├── gen_nohype_dtb │ ├── mem_init │ ├── py-check.sh │ └── python │ │ ├── .gitignore │ │ ├── common.py │ │ └── emu_wrapper.py ├── lib │ ├── dmi │ │ ├── dmi.xml │ │ └── dmi_rtl.xml │ ├── include │ │ ├── axi.vh │ │ └── dmi.vh │ ├── jtag │ │ ├── axi4_lite_if.v │ │ ├── axi_jtag_v1_0.v │ │ └── jtag_proc.v │ └── util │ │ ├── axi_reg.v │ │ ├── cdma_addr.v │ │ ├── cross_domain.v │ │ ├── leds_mux_controller.v │ │ └── uart_inverter.v ├── openocd_rpc │ ├── .gitignore │ ├── dm_reg.py │ ├── dm_utils.py │ ├── dmcontrol │ ├── dmstatus │ ├── dpc │ ├── get_cp │ ├── get_mem │ ├── halt │ ├── haltsum0 │ ├── log │ ├── openocd.py │ ├── put_mem │ ├── restart │ ├── resume │ ├── scause │ ├── sepc │ ├── set_cp │ ├── show_cache_capacity │ ├── show_traffic │ └── stval ├── pardcore │ ├── Makefile │ ├── bd │ │ └── pardcore.tcl │ └── rtl │ │ └── rocket │ │ └── .gitignore └── scripts │ ├── account.py │ ├── gen.sh │ └── range.py ├── macros └── src │ └── main │ └── scala │ └── ValName.scala ├── origin_rocket_README.md ├── project ├── .gitignore ├── build.properties └── plugins.sbt ├── regression ├── .gitignore └── Makefile ├── riscv-tools.hash ├── sbt-launch.jar ├── scripts ├── .gitignore ├── Makefile ├── RocketSim.cfg ├── RocketSim.py ├── RocketSim32.py ├── RocketSim64.py ├── authors ├── check_cache_trace.py ├── check_comparator_trace.py ├── copyright-file ├── debug_rom │ ├── .gitignore │ ├── Makefile │ ├── debug_rom.S │ └── link.ld ├── modify-copyright ├── toaxe.py ├── tracegen+check.sh ├── tracegen.py ├── tracestats.py ├── vlsi_mem_gen └── vlsi_rom_gen ├── src └── main │ ├── resources │ ├── csrc │ │ ├── SimDTM.cc │ │ ├── SimJTAG.cc │ │ ├── comlog.cc │ │ ├── emulator.cc │ │ ├── float_fix.cc │ │ ├── remote_bitbang.cc │ │ ├── remote_bitbang.h │ │ └── verilator.h │ └── vsrc │ │ ├── AsyncResetReg.v │ │ ├── ClockDivider2.v │ │ ├── ClockDivider3.v │ │ ├── EICG_wrapper.v │ │ ├── SimDTM.v │ │ ├── SimJTAG.v │ │ ├── TestDriver.v │ │ ├── UARTPrinter.v │ │ └── plusarg_reader.v │ └── scala │ ├── amba │ ├── ahb │ │ ├── Bundles.scala │ │ ├── Nodes.scala │ │ ├── Parameters.scala │ │ ├── Protocol.scala │ │ ├── RegisterRouter.scala │ │ ├── SRAM.scala │ │ ├── Test.scala │ │ ├── ToTL.scala │ │ ├── Xbar.scala │ │ └── package.scala │ ├── apb │ │ ├── Bundles.scala │ │ ├── Nodes.scala │ │ ├── Parameters.scala │ │ ├── Protocol.scala │ │ ├── RegisterRouter.scala │ │ ├── SRAM.scala │ │ ├── Test.scala │ │ ├── Xbar.scala │ │ └── package.scala │ └── axi4 │ │ ├── AsyncCrossing.scala │ │ ├── Buffer.scala │ │ ├── Bundles.scala │ │ ├── CrossingHelper.scala │ │ ├── Deinterleaver.scala │ │ ├── Delayer.scala │ │ ├── Dumper.scala │ │ ├── Filter.scala │ │ ├── Fragmenter.scala │ │ ├── IdIndexer.scala │ │ ├── Nodes.scala │ │ ├── Parameters.scala │ │ ├── Protocol.scala │ │ ├── RegisterRouter.scala │ │ ├── SRAM.scala │ │ ├── Test.scala │ │ ├── ToTL.scala │ │ ├── UserYanker.scala │ │ ├── Xbar.scala │ │ └── package.scala │ ├── config │ └── Config.scala │ ├── debug │ ├── DebugBundles.scala │ └── Stats.scala │ ├── devices │ ├── debug │ │ ├── Custom.scala │ │ ├── DMI.scala │ │ ├── Debug.scala │ │ ├── DebugRomContents.scala │ │ ├── DebugTransport.scala │ │ ├── Periphery.scala │ │ ├── SBA.scala │ │ ├── abstract_commands.scala │ │ └── dm_registers.scala │ └── tilelink │ │ ├── BootROM.scala │ │ ├── BusBlocker.scala │ │ ├── BusBypass.scala │ │ ├── CLINT.scala │ │ ├── CanHaveBuiltInDevices.scala │ │ ├── Deadlock.scala │ │ ├── DevNull.scala │ │ ├── Error.scala │ │ ├── MaskROM.scala │ │ ├── MasterMux.scala │ │ ├── PhysicalFilter.scala │ │ ├── Plic.scala │ │ ├── TestRAM.scala │ │ └── Zero.scala │ ├── diplomacy │ ├── AddressDecoder.scala │ ├── AddressRange.scala │ ├── BundleBridge.scala │ ├── ClockDomain.scala │ ├── Clone.scala │ ├── CloneModule.scala │ ├── DeviceTree.scala │ ├── FixedClockResource.scala │ ├── JSON.scala │ ├── LazyModule.scala │ ├── Nodes.scala │ ├── Parameters.scala │ ├── Resources.scala │ ├── SRAM.scala │ ├── ValName.scala │ └── package.scala │ ├── diplomaticobjectmodel │ ├── DiplomaticObjectModel.scala │ ├── DiplomaticObjectModelUtils.scala │ └── model │ │ ├── ISASpecifications.scala │ │ ├── OMAddressing.scala │ │ ├── OMBase.scala │ │ ├── OMBranchPredictor.scala │ │ ├── OMCLINT.scala │ │ ├── OMCaches.scala │ │ ├── OMCore.scala │ │ ├── OMDebug.scala │ │ ├── OMDevice.scala │ │ ├── OMFPU.scala │ │ ├── OMISA.scala │ │ ├── OMInterrupts.scala │ │ ├── OMMemory.scala │ │ ├── OMMulDiv.scala │ │ ├── OMPLIC.scala │ │ ├── OMPMP.scala │ │ ├── OMPerformanceMonitor.scala │ │ ├── OMRTLModule.scala │ │ ├── OMRegFieldAccessType.scala │ │ ├── OMRegFieldRdAction.scala │ │ ├── OMRegFieldWrType.scala │ │ ├── OMRocketCore.scala │ │ └── OMSpecification.scala │ ├── groundtest │ ├── Configs.scala │ ├── DummyPTW.scala │ ├── Generator.scala │ ├── GroundTestSubsystem.scala │ ├── Package.scala │ ├── Status.scala │ ├── TestHarness.scala │ ├── Tile.scala │ └── TraceGen.scala │ ├── interrupts │ ├── Bundles.scala │ ├── Crossing.scala │ ├── CrossingHelper.scala │ ├── Nodes.scala │ ├── NullIntSource.scala │ ├── Parameters.scala │ ├── RegisterRouter.scala │ ├── Xbar.scala │ └── package.scala │ ├── jtag │ ├── JtagShifter.scala │ ├── JtagStateMachine.scala │ ├── JtagTap.scala │ ├── JtagUtils.scala │ ├── Utils.scala │ └── package.scala │ ├── l2cache │ ├── SimpleL2.scala │ └── TLSimpleL2.scala │ ├── lvna │ ├── Dirty.scala │ ├── ILA.scala │ ├── LvNAConfigs.scala │ ├── LvNATop.scala │ └── controlplane │ │ ├── ControlPlane.scala │ │ ├── TokenBucket.scala │ │ └── TokenBucketNode.scala │ ├── regmapper │ ├── Annotation.scala │ ├── DescribedReg.scala │ ├── RegField.scala │ ├── RegMapper.scala │ ├── RegisterCrossing.scala │ └── RegisterRouter.scala │ ├── rocket │ ├── ALU.scala │ ├── AMOALU.scala │ ├── BTB.scala │ ├── Breakpoint.scala │ ├── CSR.scala │ ├── Consts.scala │ ├── DCache.scala │ ├── Decode.scala │ ├── Events.scala │ ├── Frontend.scala │ ├── HellaCache.scala │ ├── HellaCacheArbiter.scala │ ├── IBuf.scala │ ├── ICache.scala │ ├── IDecode.scala │ ├── Instructions.scala │ ├── Multiplier.scala │ ├── NBDcache.scala │ ├── PMP.scala │ ├── PTW.scala │ ├── Prefetch.scala │ ├── RVC.scala │ ├── RocketCore.scala │ ├── ScratchpadSlavePort.scala │ ├── SimpleHellaCacheIF.scala │ ├── TLB.scala │ ├── TLBPermissions.scala │ └── package.scala │ ├── scie │ └── SCIE.scala │ ├── sifive-blocks │ ├── LICENSE │ ├── devices │ │ └── uart │ │ │ ├── UART.scala │ │ │ ├── UARTCtrlRegs.scala │ │ │ ├── UARTPeriphery.scala │ │ │ └── UARTPrinter.scala │ ├── util │ │ ├── DeglitchShiftRegister.scala │ │ ├── RegMapFIFO.scala │ │ ├── ResetCatchAndSync.scala │ │ ├── SRLatch.scala │ │ ├── ShiftReg.scala │ │ └── Timer.scala │ └── vsrc │ │ ├── SRLatch.v │ │ └── vc707reset.v │ ├── subsystem │ ├── BaseSubsystem.scala │ ├── Configs.scala │ ├── CrossingWrapper.scala │ ├── FrontBus.scala │ ├── HasTiles.scala │ ├── InterruptBus.scala │ ├── MemoryBus.scala │ ├── PeripheryBus.scala │ ├── Ports.scala │ ├── RTC.scala │ ├── ResetVector.scala │ ├── RocketSubsystem.scala │ └── SystemBus.scala │ ├── system │ ├── Configs.scala │ ├── ExampleRocketSystem.scala │ ├── Generator.scala │ ├── RocketTestSuite.scala │ └── TestHarness.scala │ ├── tile │ ├── BaseTile.scala │ ├── BusErrorUnit.scala │ ├── Core.scala │ ├── CustomCSRs.scala │ ├── FPU.scala │ ├── Interrupts.scala │ ├── L1Cache.scala │ ├── LazyRoCC.scala │ └── RocketTile.scala │ ├── tilelink │ ├── AddressAdjuster.scala │ ├── Arbiter.scala │ ├── AsyncCrossing.scala │ ├── AtomicAutomata.scala │ ├── Atomics.scala │ ├── BankBinder.scala │ ├── Broadcast.scala │ ├── Buffer.scala │ ├── Bundles.scala │ ├── BusWrapper.scala │ ├── CacheCork.scala │ ├── CrossingHelper.scala │ ├── Delayer.scala │ ├── Dumper.scala │ ├── Edges.scala │ ├── ErrorEvaluator.scala │ ├── Example.scala │ ├── FIFOFixer.scala │ ├── Filter.scala │ ├── Fragmenter.scala │ ├── Fuzzer.scala │ ├── HintHandler.scala │ ├── Isolation.scala │ ├── Map.scala │ ├── Metadata.scala │ ├── Monitor.scala │ ├── Nodes.scala │ ├── Parameters.scala │ ├── PatternPusher.scala │ ├── ProbePicker.scala │ ├── RAMModel.scala │ ├── RationalCrossing.scala │ ├── RegionReplication.scala │ ├── RegisterRouter.scala │ ├── RegisterRouterTest.scala │ ├── SRAM.scala │ ├── SourceShrinker.scala │ ├── ToAHB.scala │ ├── ToAPB.scala │ ├── ToAXI4.scala │ ├── WidthWidget.scala │ ├── Xbar.scala │ └── package.scala │ ├── unittest │ ├── Configs.scala │ ├── Generator.scala │ ├── TestGenerator.scala │ ├── TestHarness.scala │ ├── UnitTest.scala │ └── package.scala │ └── util │ ├── Annotations.scala │ ├── Arbiters.scala │ ├── AsyncQueue.scala │ ├── AsyncResetReg.scala │ ├── Broadcaster.scala │ ├── CRC.scala │ ├── CheckOneHot.scala │ ├── ClockDivider.scala │ ├── ClockGate.scala │ ├── CoreMonitor.scala │ ├── Counters.scala │ ├── Crossing.scala │ ├── DescribedSRAM.scala │ ├── ECC.scala │ ├── Frequency.scala │ ├── GeneratorUtils.scala │ ├── GenericParameterizedBundle.scala │ ├── GlobalTimer.scala │ ├── HellaQueue.scala │ ├── HeterogeneousBag.scala │ ├── IDPool.scala │ ├── IdentityModule.scala │ ├── LCG.scala │ ├── LanePositionedQueue.scala │ ├── LatencyPipe.scala │ ├── Misc.scala │ ├── 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