├── .gitignore ├── Dockerfile ├── LICENSE ├── README.md ├── doc └── cpu-base.png ├── docker-compose.yml ├── result ├── DoM.log ├── Figure10 │ ├── performance.pdf │ ├── plot.py │ ├── print.py │ ├── run_local.py │ ├── summary.json │ └── summary.py └── GhostMinion.log ├── script ├── archive.py ├── plot_helper.py ├── run.py ├── run_helper_local.py └── summary_helper.py └── src ├── CPU ├── CPU.rkt ├── ROB.rkt ├── alu.rkt ├── cache.rkt ├── decode.rkt ├── inFetchScoreBoard.rkt ├── issue.rkt └── renameTB.rkt ├── ISASimulator.rkt ├── abs-module ├── absArbiter.rkt ├── absBufferGM.rkt ├── absDelay.rkt ├── absFifo.rkt ├── absFifo2.rkt └── brPred.rkt ├── decode.rkt ├── inst.rkt ├── lib ├── array.rkt ├── bv.rkt ├── debug │ ├── assert-debug-commitLog.rkt │ ├── buginfo.rkt │ ├── debug.rkt │ └── unittest.rkt ├── lib.rkt └── param.rkt ├── main_veriCorr.rkt ├── main_veriSpec.rkt └── sym-state ├── mem.rkt ├── memd.rkt ├── memi.rkt └── rf.rkt /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | .DS_Store 3 | __pycache__ 4 | 5 | /result 6 | 7 | -------------------------------------------------------------------------------- /Dockerfile: -------------------------------------------------------------------------------- 1 | FROM ubuntu:focal-20230308 2 | 3 | # STEP1 tools 4 | RUN apt update && \ 5 | DEBIAN_FRONTEND=noninteractive apt install -y --no-install-recommends \ 6 | git \ 7 | wget \ 8 | curl \ 9 | ca-certificates \ 10 | vim \ 11 | graphviz \ 12 | firefox 13 | 14 | 15 | # STEP2 python3 16 | RUN DEBIAN_FRONTEND=noninteractive apt install -y --no-install-recommends \ 17 | python3 \ 18 | python3-pip && \ 19 | python3 -m pip install numpy==1.24.2 matplotlib==3.7.1 20 | 21 | 22 | # STEP3 racket8.3 23 | RUN wget https://download.racket-lang.org/installers/8.3/racket-8.3-x86_64-linux-cs.sh && \ 24 | bash racket-8.3-x86_64-linux-cs.sh --in-place --dest /usr/racket && \ 25 | rm racket-8.3-x86_64-linux-cs.sh && \ 26 | echo "export PATH=/usr/racket/bin:\$PATH" >> /root/.bashrc 27 | 28 | 29 | # STEP4 rosette newest version at the time 30 | RUN git clone https://github.com/emina/rosette.git && \ 31 | cd rosette && git checkout 15647f24b4b942e5eaae19a8ec0fcd272ce7504f && cd .. && \ 32 | /usr/racket/bin/raco pkg install --no-docs --copy --auto -i -t dir rosette && \ 33 | rm -rf rosette 34 | 35 | 36 | # STEP5 boolector 3.2.2 37 | RUN DEBIAN_FRONTEND=noninteractive apt install -y --no-install-recommends \ 38 | make \ 39 | cmake \ 40 | gcc \ 41 | g++ 42 | RUN wget https://github.com/Boolector/boolector/archive/refs/tags/3.2.2.tar.gz && \ 43 | tar -zxvf 3.2.2.tar.gz && \ 44 | cd boolector-3.2.2 && \ 45 | ./contrib/setup-lingeling.sh && \ 46 | ./contrib/setup-btor2tools.sh && \ 47 | ./configure.sh --prefix /usr/boolector && cd build && make -j8 && make install && \ 48 | cd ../.. && rm -rf 3.2.2.tar.gz boolector-3.2.2 && \ 49 | echo "export PATH=/usr/boolector/bin:\$PATH" >> /root/.bashrc 50 | 51 | 52 | # STEP6 DASK 53 | RUN python3 -m pip install "dask[complete]"==2023.3.1 54 | 55 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2023 Arch-Sec Group at CSAIL, MIT 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | # Pensieve 3 | 4 | This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks. 5 | 6 | 7 | ### Demo Video of Finding Attacks on Delay-on-Miss 8 | 9 | https://github.com/CSAIL-Arch-Sec/Pensieve/assets/40620196/af6fbc09-727b-4714-be4c-4dcb095f6e44 10 | 11 | 12 | ### More in Our Paper 13 | 14 | Please check our ISCA 2023 paper, [Pensieve: Microarchitectural Modeling for Security Evaluation](https://people.csail.mit.edu/mengjia/data/Pensieve_ISCA_23.pdf) for a comprehensive understanding of the framework. 15 | Alternatively, its abstract can also provide you with a quick overview: 16 | 17 | > Traditional modeling approaches in computer architecture aim to obtain an accurate estimation of performance, area, and energy of a processor design. 18 | > With the advent of speculative execution attacks and their security concerns, these traditional modeling techniques fall short when used for security evaluation of defenses against these attacks. 19 | > 20 | > This paper presents Pensieve, a security evaluation framework targeting early-stage microarchitectural defenses against speculative execution attacks. 21 | > At the core, it introduces a modeling discipline for systematically studying early-stage defenses. 22 | > This discipline allows us to cover a space of designs that are functionally equivalent while precisely capturing timing variations due to resource contention and microarchitectural optimizations. 23 | > We implement a model checking framework to automatically find vulnerabilities in designs. 24 | > We use Pensieve to evaluate a series of state-of-the-art invisible speculation defense schemes, including Delay-on-Miss, InvisiSpec, and GhostMinion, against a formally defined security property, speculative non-interference. 25 | > Pensieve finds Spectre-like attacks in all those defenses, including a new speculative interference attack variant that breaks GhostMinion, one of the latest defenses. 26 | 27 | 28 | 29 | 30 | 31 | 32 | ## Readme Overview 33 | 34 | This readme document provides you with the basic usage of this repository. 35 | We will first guide you to [set up the environment](#Environment-Setup) in docker and [run the framework](#Run-Examples) to evaluate a few example designs. 36 | 37 | To help you understand the framework, we then [explain the terminal outputs](#Understand-the-Terminal-Output) when evaluating the example designs. 38 | This can guide you through the code that utilizes Rosette for symbolic execution, invokes SMT solver for automatic evaluation, and finally generates attacks on example designs. 39 | 40 | Finally, we provide [documents](#Understand-the-Code-and-Verify-Your-Own-Design) on the implementation of our example designs to warm you up for using Pensieve to evaluate your own designs. 41 | 42 | 43 | 44 | 45 | 46 | 47 | ## Environment Setup 48 | 49 | ### Docker 50 | 51 | You can create a docker container (and delete it afterwards) with the following commands: 52 | 53 | 1. Run `docker-compose up -d` to build up the container. 54 | 2. Run `docker-compose exec env bash` to log in to the container. 55 | 3. Run `docker-compose stop` to pause and `docker-compose up -d` to relaunch the container. 56 | 4. Run `docker-compose down --rmi all` to clean up. (`docker system prune` can further clean up the cache, including your cache for other projects.) 57 | 58 | 59 | 60 | 61 | 62 | 63 | ### Physical Machine 64 | 65 | To set up a physical machine environment, please refer to [Dockerfile](Dockerfile) to install racket, rosette, boolector, and dask (or HTcondor). 66 | 67 | 68 | 69 | 70 | 71 | 72 | ## Run Examples 73 | 74 | You can test the framework on a few example designs with the following commands: 75 | 76 | 1. Enter the repository folder. (Mounted at `/vagrant` in the container or virtual machine) 77 | 2. Always run commands in this folder. 78 | 3. We have a few pre-set parameters to evaluate example defense designs and find attacks: 79 | - Spectre attack on Baseline design: `raco test ++arg --param-saved-params ++arg spectre ++arg --param-saved-sizes ++arg spectre src/main_veriSpec.rkt` 80 | - Interference attack on DoM defense: `raco test ++arg --param-saved-params ++arg DoM ++arg --param-saved-sizes ++arg DoM src/main_veriSpec.rkt` 81 | - New interference attack variant on GhostMinion defense: `raco test ++arg --param-saved-params ++arg GhostMinion ++arg --param-saved-sizes ++arg GhostMinion src/main_veriSpec.rkt` 82 | 4. You can further customize the parameters in `lib/param.rkt`. 83 | 84 | You can also evaluate a bash of designs with different parameters. 85 | Please refer to the Artifact Appendix of the Pensieve paper for more details. 86 | 87 | 88 | 89 | 90 | 91 | 92 | ## Understand the Terminal Output 93 | 94 | ### Workflow 95 | 96 | File `src/main_veriSpec.rkt` is the high-level workflow of the code. It will evaluate the design by following steps: 97 | 98 | 1. Simulate the design using a symbolic initial state with Rosette framework. It prints "Finish Symbolic Execution" to the terminal after this step. 99 | 2. Query the SMT solver with security property, which is encoded as a symbolic formula. It prints `Finish STM Solver` after SMT solver finishes. 100 | 3. If no counterexample is found, it will print "No Counterexample". 101 | 4. If a counterexample is found, it will print "Find Counterexample" and continue to provide the content of the counterexample by following steps: 102 | 1. Query the SMT solver for concrete initial state instances that trigger the counterexample. It includes a pair of initial states with different secret value. 103 | 2. Simulate the design twice under different secrets. During the simulations, it prints out the execution traces specified by `param-debug-print-on` in the code base. It prints out `Finish SMT Result Evaluation` after this step. 104 | 3. Print a summary of the instruction sequence of the counterexample, the initial architecture state, and the final states of the simulation of the ISA model and uarch model. 105 | 106 | You can check these steps with `src/main_veriSpec.rkt` and search for `param-debug-print-on` in the code base if you want to customize the printouts. 107 | 108 | 109 | 110 | 111 | 112 | 113 | ## Understand the Code and Verify Your Own Design 114 | 115 | The code implements a baseline microarchitecture with a few defense augmentations. 116 | We will first give you an [overview of the baseline microarchitecture](#Baseline-Microarchitecture) as well as [how the files are organized](#File-Organization) to implement it. 117 | Then we point you to the source code related to the key technique described in the paper, which [uses uninterpreted functions](#Usage-of-Uninterpreted-Functions) to represent a space of designs. 118 | Finally, we point you to how we augment the baseline microarchitecture to implement our [example defenses](#Defense-Augmentations). 119 | You can further follow the pattern to implement your own defenses and evaluate them. 120 | 121 | 122 | 123 | 124 | 125 | 126 | ### Baseline Microarchitecture 127 | 128 | We quote part of section 5.1 of the Pensieve paper to give an overview of the baseline microarchitecture. 129 | 130 | > 131 | > 132 | > **Figure 6: The baseline uarch model with the submodules using uninterpreted functions highlighted.** 133 | > 134 | > Our baseline uarch model, though simple, covers a large design space and potentially complex pipeline scheduling policies. 135 | > In Figure 6, we highlight the submodules that use uninterpreted functions. 136 | > The fetch module models an arbitrary branch predictor having an arbitrary fetch latency. 137 | > This accounts for different latencies introduced by varied complexity of the branch predictor and varied instruction memory access latency. 138 | > The dispatch module uses an uninterpreted function to select which instruction to send to the corresponding execution unit among the instructions whose operands are ready. 139 | > We use the toy examples from Section 4.1 as the ALU and memory modules, which have been shown to cover a large space. 140 | > 141 | > We note that our baseline uarch model has concrete decode&rename and commit stages. 142 | > We show our baseline uarch model was sufficient to find vulnerabilities in existing defenses in our case studies and discuss its limitations in Section 8. 143 | 144 | 145 | Here is a summary of the ISA used: 146 | 147 | | | op | rs1 | rs2 | rd | | 148 | | ---- | ---- | ---- | ---- | ---- | ------------------------------- | 149 | | Li | 0 | | X | | Reg[rd] <- rs1 | 150 | | Add | 1 | | | | Reg[rd] <- Reg[rs1] + Reg[rs2] | 151 | | Mul | 2 | | | | Reg[rd] <- Reg[rs1] * Reg[rs2] | 152 | | Ld | 3 | | X | | Reg[rd] <- Mem[Reg[rs1]] | 153 | | St | 4 | | | X | Mem[Reg[rs1]] <- Reg[rs2] | 154 | | Br | 5 | | | X | If (Reg[rs2]==0) PC <- PC + rs1 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | ### File Organization 162 | 163 | We implement the baseline microarchitecture with `src/CPU/CPU.rkt`. 164 | 165 | ``` 166 | main_veriSpec.rkt 167 | | 168 | |-- ISASimulator.rkt 169 | | |-- sym-state/* 170 | | |-- inst.rkt 171 | | |-- decode.rkt 172 | | 173 | |-- CPU/CPU.rkt 174 | |-- sym-state/* 175 | |-- CPU/rename.rkt 176 | |-- CPU/ROB.rkt 177 | |-- evalF 178 | | |-- CPU/inFetchScoreBoard.rkt 179 | | |-- abs-module/brPred.rkt 180 | | |-- abs-module/absFifo2.rkt 181 | | |-- CPU/decode.rkt 182 | |-- evalE 183 | | |-- CPU/issue.rkt 184 | | |-- CPU/alu.rkt 185 | | | |-- abs-module/absArbiter.rkt 186 | | | |-- abs-module/absFifo.rkt 187 | | | |-- abs-module/absBufferGM.rkt 188 | | |-- CPU/cache.rkt 189 | | |-- abs-module/absArbiter.rkt 190 | | |-- abs-module/absFifo.rkt 191 | | |-- abs-module/absBufferGM.rkt 192 | |-- evalE 193 | ``` 194 | 195 | 196 | Here are a few abbreviations used in the code: 197 | 198 | - brPred: branch predictor 199 | - FDelay: Fetch Delay 200 | - rf: register file 201 | - timFct: timing factors 202 | - obsv: observation 203 | 204 | 205 | 206 | 207 | 208 | 209 | ### Usage of Uninterpreted Functions 210 | 211 | We extensively use uninterpreted functions (UFs) to represent a space of functionality and timing. 212 | `CPU/abs-module/` include all modules using the UFs. 213 | 214 | - `CPU/abs-module/brPred.rkt` implements a branch predictor. It uses UFs to represent the direction of branch prediction. 215 | - `CPU/abs-module/absFifo2.rkt` implements a FIFO with two input and output channels and is used to represent the Fetch latency. It uses UFs to represent arbitrary latencies. 216 | - `CPU/abs-module/absArbiter.rkt` implements an N-to-1 arbiter and is used to represent the issuing policy. It uses UFs to choose an arbitrary ready instruction to issue. 217 | - `CPU/abs-module/absFifo.rkt` implements a FIFO and is used to represent the ALU and memory latency. It uses UFs to represent arbitrary latencies. 218 | - `CPU/abs-module/absBufferGM.rkt` implements a delay buffer with non-FIFO order to model GhostMinion defense. It uses UFs to represent arbitrary latencies. 219 | 220 | 221 | 222 | 223 | 224 | 225 | ### Defense Augmentations 226 | 227 | We use a few parameters in `lib/param.rkt` to enable defenses on baseline microarchitecture. 228 | They are `param-enable-DoM`, `param-enable-invisiSpec`, and`param-enable-GhostMinion`. 229 | Please search them in the `src` folder to see how these defenses are implemented. 230 | 231 | -------------------------------------------------------------------------------- /doc/cpu-base.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MATCHA-MIT/Pensieve/89ee3067103ec45306b7f0e6d0a1886841312f28/doc/cpu-base.png -------------------------------------------------------------------------------- /docker-compose.yml: -------------------------------------------------------------------------------- 1 | version: "3.9" 2 | services: 3 | env: 4 | build: . 5 | platform: linux/amd64 6 | volumes: 7 | - .:/vagrant 8 | environment: 9 | - DISPLAY=host.docker.internal:0 10 | stdin_open: true # docker run -i 11 | tty: true # docker run -t 12 | 13 | -------------------------------------------------------------------------------- /result/DoM.log: -------------------------------------------------------------------------------- 1 | root@0691dfed0aa1:/vagrant# raco test \ 2 | > ++arg --param-saved-params ++arg DoM \ 3 | > ++arg --param-saved-sizes ++arg DoM \ 4 | > src/main_veriSpec.rkt 5 | raco test: "src/main_veriSpec.rkt" "--param-saved-params" "DoM" "--param-saved-sizes" "DoM" 6 | Tests for veriSpec 7 | [ RUN ] "get-bug-info" 8 | Finish Symbolic Execution. 9 | Finish STM Solver. 10 | Find Counterexample. 11 | CPU: 12 | debug-commitLog: () underSpec: #f specBr-ROBlink(bv #x0 4) 13 | memi: history: () 14 | Dcache: 15 | history: (0 0 0 0 )(0 0 0 0 ), invisi: (0 0 0 0 )(0 0 0 0 ) 16 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 17 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 18 | adder: 19 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 20 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 21 | ROB: 22 | head: 0, tail: 0 23 | idle: (#t #t #t #t #t #t #t #t #t #t #t #t #t #t #t #t ), waiting: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 24 | executing: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), finished: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 25 | pc: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ), op: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ), brID: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 26 | underSpec: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), specBr-ROBlink: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 27 | 28 | 29 | 30 | datainReady: #f ROBlink: (bv #x1 4) 31 | datainReady: #f ROBlink: (bv #x3 4) 32 | datainReady: #f ROBlink: (bv #x0 4) 33 | squash-E: #f misPredBr-ROBlink-E: (bv #x0 4) misPredBr-brID-E: (bv #b11 2) nextPC-E: (bv #x0 4) 34 | CPU: 35 | debug-commitLog: () underSpec: #f specBr-ROBlink(bv #x0 4) 36 | memi: history: (0 1 ) 37 | Dcache: 38 | history: (0 0 0 0 )(0 0 0 0 ), invisi: (0 0 0 0 )(0 0 0 0 ) 39 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 40 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 41 | adder: 42 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 43 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 44 | ROB: 45 | head: 0, tail: 0 46 | idle: (#t #t #t #t #t #t #t #t #t #t #t #t #t #t #t #t ), waiting: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 47 | executing: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), finished: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 48 | pc: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ), op: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ), brID: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 49 | underSpec: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), specBr-ROBlink: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 50 | 51 | 52 | 53 | datainReady: #f ROBlink: (bv #x1 4) 54 | datainReady: #f ROBlink: (bv #x3 4) 55 | datainReady: #f ROBlink: (bv #x0 4) 56 | squash-E: #f misPredBr-ROBlink-E: (bv #x0 4) misPredBr-brID-E: (bv #b11 2) nextPC-E: (bv #x0 4) 57 | ---->pc: (bv #x0 4) underSpec: #f specBr-ROBlink: (bv #x0 4) 58 | ---->pc: (bv #x1 4) underSpec: #f specBr-ROBlink: (bv #x1 4) 59 | ---->pc: (bv #x2 4) underSpec: #t 60 | CPU: 61 | debug-commitLog: () underSpec: #f specBr-ROBlink(bv #x0 4) 62 | memi: history: (0 1 2 11 ) 63 | Dcache: 64 | history: (0 0 0 0 )(0 0 0 0 ), invisi: (0 0 0 0 )(0 0 0 0 ) 65 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 66 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 67 | adder: 68 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 69 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 70 | ROB: 71 | head: 0, tail: 2 72 | idle: (#f #f #t #t #t #t #t #t #t #t #t #t #t #t #t #t ), waiting: (#t #t #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 73 | executing: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), finished: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 74 | pc: (0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ), op: (3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ), brID: (0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 75 | underSpec: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), specBr-ROBlink: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 76 | 77 | 78 | 79 | datainReady: #f ROBlink: (bv #x1 4) 80 | datainReady: #f ROBlink: (bv #x3 4) 81 | datainReady: #t ROBlink: (bv #x1 4) 82 | squash-E: #f misPredBr-ROBlink-E: (bv #x0 4) misPredBr-brID-E: (bv #b11 2) nextPC-E: (bv #x0 4) 83 | ---->pc: (bv #x2 4) underSpec: #t specBr-ROBlink: (bv #x2 4) 84 | ---->pc: (bv #xb 4) underSpec: #f specBr-ROBlink: (bv #x3 4) 85 | ---->pc: (bv #xc 4) underSpec: #t 86 | ---->pc: (bv #xc 4) underSpec: #t 87 | return ROBlink: (bv #x1 4) 88 | CPU: 89 | debug-commitLog: () underSpec: #t specBr-ROBlink(bv #x2 4) 90 | memi: history: (0 1 2 11 12 12 ) 91 | Dcache: 92 | history: (0 0 1 0 )(0 0 0 0 ), invisi: (0 0 0 0 )(0 0 0 0 ) 93 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 94 | absDelay: Valid: (0 0 1 0 )timFct: (0 0 0 0 )buffer-brID: (1 0 0 0 ) 95 | adder: 96 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 97 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 98 | ROB: 99 | head: 0, tail: 4 100 | idle: (#f #f #f #f #t #t #t #t #t #t #t #t #t #t #t #t ), waiting: (#t #f #t #t #f #f #f #f #f #f #f #f #f #f #f #f ) 101 | executing: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), finished: (#f #t #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 102 | pc: (0 1 2 11 0 0 0 0 0 0 0 0 0 0 0 0 ), op: (3 3 5 3 0 0 0 0 0 0 0 0 0 0 0 0 ), brID: (0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 ) 103 | underSpec: (#f #f #f #t #f #f #f #f #f #f #f #f #f #f #f #f ), specBr-ROBlink: (0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 ) 104 | 105 | 106 | 107 | datainReady: #f ROBlink: (bv #x1 4) 108 | datainReady: #f ROBlink: (bv #x3 4) 109 | datainReady: #t ROBlink: (bv #x0 4) 110 | squash-E: #f misPredBr-ROBlink-E: (bv #x0 4) misPredBr-brID-E: (bv #b11 2) nextPC-E: (bv #x0 4) 111 | ---->pc: (bv #xe 4) underSpec: #t 112 | return ROBlink: (bv #x0 4) 113 | CPU: 114 | debug-commitLog: () underSpec: #f specBr-ROBlink(bv #x0 4) 115 | memi: history: () 116 | Dcache: 117 | history: (0 0 0 0 )(0 0 0 0 ), invisi: (0 0 0 0 )(0 0 0 0 ) 118 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 119 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 120 | adder: 121 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 122 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 123 | ROB: 124 | head: 0, tail: 0 125 | idle: (#t #t #t #t #t #t #t #t #t #t #t #t #t #t #t #t ), waiting: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 126 | executing: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), finished: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 127 | pc: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ), op: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ), brID: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 128 | underSpec: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), specBr-ROBlink: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 129 | 130 | 131 | 132 | datainReady: #f ROBlink: (bv #x1 4) 133 | datainReady: #f ROBlink: (bv #x3 4) 134 | datainReady: #f ROBlink: (bv #x0 4) 135 | squash-E: #f misPredBr-ROBlink-E: (bv #x0 4) misPredBr-brID-E: (bv #b11 2) nextPC-E: (bv #x0 4) 136 | CPU: 137 | debug-commitLog: () underSpec: #f specBr-ROBlink(bv #x0 4) 138 | memi: history: (0 1 ) 139 | Dcache: 140 | history: (0 0 0 0 )(0 0 0 0 ), invisi: (0 0 0 0 )(0 0 0 0 ) 141 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 142 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 143 | adder: 144 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 145 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 146 | ROB: 147 | head: 0, tail: 0 148 | idle: (#t #t #t #t #t #t #t #t #t #t #t #t #t #t #t #t ), waiting: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 149 | executing: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), finished: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 150 | pc: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ), op: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ), brID: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 151 | underSpec: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), specBr-ROBlink: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 152 | 153 | 154 | 155 | datainReady: #f ROBlink: (bv #x1 4) 156 | datainReady: #f ROBlink: (bv #x3 4) 157 | datainReady: #f ROBlink: (bv #x0 4) 158 | squash-E: #f misPredBr-ROBlink-E: (bv #x0 4) misPredBr-brID-E: (bv #b11 2) nextPC-E: (bv #x0 4) 159 | ---->pc: (bv #x0 4) underSpec: #f specBr-ROBlink: (bv #x0 4) 160 | ---->pc: (bv #x1 4) underSpec: #f specBr-ROBlink: (bv #x1 4) 161 | ---->pc: (bv #x2 4) underSpec: #t 162 | CPU: 163 | debug-commitLog: () underSpec: #f specBr-ROBlink(bv #x0 4) 164 | memi: history: (0 1 2 11 ) 165 | Dcache: 166 | history: (0 0 0 0 )(0 0 0 0 ), invisi: (0 0 0 0 )(0 0 0 0 ) 167 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 168 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 169 | adder: 170 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 171 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 172 | ROB: 173 | head: 0, tail: 2 174 | idle: (#f #f #t #t #t #t #t #t #t #t #t #t #t #t #t #t ), waiting: (#t #t #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 175 | executing: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), finished: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 176 | pc: (0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ), op: (3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ), brID: (0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 177 | underSpec: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), specBr-ROBlink: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 178 | 179 | 180 | 181 | datainReady: #f ROBlink: (bv #x1 4) 182 | datainReady: #f ROBlink: (bv #x3 4) 183 | datainReady: #t ROBlink: (bv #x1 4) 184 | squash-E: #f misPredBr-ROBlink-E: (bv #x0 4) misPredBr-brID-E: (bv #b11 2) nextPC-E: (bv #x0 4) 185 | ---->pc: (bv #x2 4) underSpec: #t specBr-ROBlink: (bv #x2 4) 186 | ---->pc: (bv #xb 4) underSpec: #f specBr-ROBlink: (bv #x3 4) 187 | ---->pc: (bv #xc 4) underSpec: #t 188 | ---->pc: (bv #xc 4) underSpec: #t 189 | return ROBlink: (bv #x1 4) 190 | CPU: 191 | debug-commitLog: () underSpec: #t specBr-ROBlink(bv #x2 4) 192 | memi: history: (0 1 2 11 12 12 ) 193 | Dcache: 194 | history: (0 0 1 0 )(0 0 0 0 ), invisi: (0 0 0 0 )(0 0 0 0 ) 195 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 196 | absDelay: Valid: (0 0 1 0 )timFct: (0 0 0 0 )buffer-brID: (1 0 0 0 ) 197 | adder: 198 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 199 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 200 | ROB: 201 | head: 0, tail: 4 202 | idle: (#f #f #f #f #t #t #t #t #t #t #t #t #t #t #t #t ), waiting: (#t #f #t #t #f #f #f #f #f #f #f #f #f #f #f #f ) 203 | executing: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), finished: (#f #t #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 204 | pc: (0 1 2 11 0 0 0 0 0 0 0 0 0 0 0 0 ), op: (3 3 5 3 0 0 0 0 0 0 0 0 0 0 0 0 ), brID: (0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 ) 205 | underSpec: (#f #f #f #t #f #f #f #f #f #f #f #f #f #f #f #f ), specBr-ROBlink: (0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 ) 206 | 207 | 208 | 209 | datainReady: #f ROBlink: (bv #x1 4) 210 | datainReady: #f ROBlink: (bv #x3 4) 211 | datainReady: #f ROBlink: (bv #xa 4) 212 | squash-E: #f misPredBr-ROBlink-E: (bv #x0 4) misPredBr-brID-E: (bv #b11 2) nextPC-E: (bv #x0 4) 213 | ---->pc: (bv #xe 4) underSpec: #t 214 | Finish SMT Result Evaluation. 215 | cfg: memi: 216 | (0-th INST Ld 12 2 2 : Reg[2] <- Mem[Reg[0]] 217 | 1-th INST Ld 13 1 0 : Reg[0] <- Mem[Reg[1]] 218 | 2-th INST Br 9 2 2 : If (Reg[2]==0) PC <- PC + 9 219 | 3-th INST Ld 7 0 0 : Reg[0] <- Mem[Reg[3]] 220 | 4-th INST Ld 0 0 0 : Reg[0] <- Mem[Reg[0]] 221 | 5-th INST Ld 0 0 0 : Reg[0] <- Mem[Reg[0]] 222 | 6-th INST Br 0 0 0 : If (Reg[0]==0) PC <- PC + 0 223 | 7-th INST Ld 0 0 0 : Reg[0] <- Mem[Reg[0]] 224 | 8-th INST Li 0 0 0 : Reg[0] <- 0 225 | 9-th INST Ld 0 0 0 : Reg[0] <- Mem[Reg[0]] 226 | 10-th INST Ld 0 0 0 : Reg[0] <- Mem[Reg[0]] 227 | 11-th INST Ld 12 3 1 : Reg[1] <- Mem[Reg[0]] 228 | 12-th INST Br 0 0 0 : If (Reg[0]==0) PC <- PC + 0 229 | 13-th INST Ld 0 0 0 : Reg[0] <- Mem[Reg[0]] 230 | 14-th INST Br 0 0 0 : If (Reg[0]==0) PC <- PC + 0 231 | 15-th INST Ld 0 0 0 : Reg[0] <- Mem[Reg[0]] 232 | )rf: (8 0 4 8 ) 233 | memd-0: (9 8 0 0 ) memd-1: (8 8 0 0 ) 234 | 235 | ISASimulator-0: memi: history: (0 1 2 3 ) 236 | memd: history: (0: 0, 1: 0, 3: 0, ) array: (9 8 0 0 ) 237 | 238 | ISASimulator-1: memi: history: (0 1 2 3 ) 239 | memd: history: (0: 0, 1: 0, 3: 0, ) array: (8 8 0 0 ) 240 | 241 | CPU-0: debug-commitLog: () underSpec: #t specBr-ROBlink(bv #x2 4) 242 | memi: history: (0 1 2 11 12 12 13 14 ) 243 | Dcache: 244 | history: (0 0 1 1 )(0 0 0 0 ), invisi: (0 0 0 0 )(0 0 0 0 ) 245 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 246 | absDelay: Valid: (0 0 1 1 )timFct: (0 0 0 0 )buffer-brID: (1 0 0 0 ) 247 | adder: 248 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 249 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 250 | ROB: 251 | head: 0, tail: 4 252 | idle: (#f #f #f #f #t #t #t #t #t #t #t #t #t #t #t #t ), waiting: (#f #f #t #t #f #f #f #f #f #f #f #f #f #f #f #f ) 253 | executing: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), finished: (#t #t #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 254 | pc: (0 1 2 11 0 0 0 0 0 0 0 0 0 0 0 0 ), op: (3 3 5 3 0 0 0 0 0 0 0 0 0 0 0 0 ), brID: (0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 ) 255 | underSpec: (#f #f #f #t #f #f #f #f #f #f #f #f #f #f #f #f ), specBr-ROBlink: (0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 ) 256 | 257 | 258 | CPU-1: debug-commitLog: () underSpec: #t specBr-ROBlink(bv #x2 4) 259 | memi: history: (0 1 2 11 12 12 13 14 ) 260 | Dcache: 261 | history: (0 0 1 0 )(0 0 0 0 ), invisi: (0 0 0 0 )(0 0 0 0 ) 262 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 263 | absDelay: Valid: (0 0 1 0 )timFct: (0 0 0 0 )buffer-brID: (1 0 0 0 ) 264 | adder: 265 | absArbiter: timFct: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )valid: (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) 266 | absDelay: Valid: (0 0 0 0 )timFct: (0 0 0 0 )buffer-brID: (0 0 0 0 ) 267 | ROB: 268 | head: 0, tail: 4 269 | idle: (#f #f #f #f #t #t #t #t #t #t #t #t #t #t #t #t ), waiting: (#t #f #t #t #f #f #f #f #f #f #f #f #f #f #f #f ) 270 | executing: (#f #f #f #f #f #f #f #f #f #f #f #f #f #f #f #f ), finished: (#f #t #f #f #f #f #f #f #f #f #f #f #f #f #f #f ) 271 | pc: (0 1 2 11 0 0 0 0 0 0 0 0 0 0 0 0 ), op: (3 3 5 3 0 0 0 0 0 0 0 0 0 0 0 0 ), brID: (0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 ) 272 | underSpec: (#f #f #f #t #f #f #f #f #f #f #f #f #f #f #f #f ), specBr-ROBlink: (0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 ) 273 | 274 | 275 | [ OK ] "get-bug-info" (6384ms cpu) (9180ms real) (239735 terms) 276 | 1 success(es) 0 failure(s) 0 error(s) 1 test(s) run 277 | cpu time: 6384 real time: 9181 gc time: 817 278 | 0 279 | 1 test passed 280 | root@0691dfed0aa1:/vagrant# 281 | 282 | -------------------------------------------------------------------------------- /result/Figure10/performance.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MATCHA-MIT/Pensieve/89ee3067103ec45306b7f0e6d0a1886841312f28/result/Figure10/performance.pdf -------------------------------------------------------------------------------- /result/Figure10/plot.py: -------------------------------------------------------------------------------- 1 | 2 | import sys, os 3 | sys.path.append(os.getcwd()) 4 | from script.plot_helper import getResult 5 | import numpy as np 6 | 7 | 8 | resultDir = os.path.dirname(os.path.abspath(__file__)) 9 | shape = [4, 4, 8] 10 | param = ["saved_params", "CPU_OOO_ROB_size", "CPU-simuCycle"] 11 | num_test = 128 12 | 13 | 14 | result = getResult(resultDir) 15 | time = np.array(result["time"]) 16 | index = np.array(result["index"]) 17 | model = np.array(result["model"]) 18 | 19 | connect_last_with_dashed = [ \ 20 | [False, False, False, False], \ 21 | [False, False, False, False], \ 22 | [False, False, False, False], \ 23 | [False, False, False, True], \ 24 | ] 25 | 26 | 27 | 28 | 29 | def plot_arch(ax, yy, mm, connect_last_with_dashed): 30 | x_base = 4 31 | x_end = 10 32 | x = range(x_base, x_end) 33 | yy = yy[::-1] 34 | yy = [[1 if data==0 else data for data in y] for y in yy] 35 | yy = [[data / 60.0 for data in y] for y in yy] 36 | mm = mm[::-1] 37 | connect_last_with_dashed = connect_last_with_dashed[::-1] 38 | linecolors = ["lightpink", "dodgerblue", "green", "black"][::-1] 39 | labels = ["ROB Size = 2", "ROB Size = 4", "ROB Size = 8", "ROB Size = 16"][::-1] 40 | 41 | 42 | unfinisheds = [[] for _ in yy] 43 | for (y, m, color, unfinished) in zip(yy, mm, linecolors, unfinisheds): 44 | secure_x = [] 45 | secure_y = [] 46 | attack_x = [] 47 | attack_y = [] 48 | for (data, data_model, data_x) in zip(y, m, x): 49 | if data_model==0: 50 | secure_x.append(data_x) 51 | secure_y.append(data) 52 | elif data_model==1: 53 | attack_x.append(data_x) 54 | attack_y.append(data) 55 | else: 56 | unfinished.append(data_x - x_base) 57 | 58 | ax.scatter(secure_x, secure_y, marker="o", s=320, alpha=0.7, color=color,edgecolor='None') 59 | ax.scatter(attack_x, attack_y, marker="x", s=280, lw=3, alpha=0.7, color=color,edgecolor='None') 60 | 61 | 62 | for (y, linecolor, label, unfinished, dashed) in \ 63 | zip(yy, linecolors, labels, unfinisheds, connect_last_with_dashed): 64 | x_temp = list(x).copy() 65 | y_temp = y.copy() 66 | for i in unfinished[::-1]: 67 | del x_temp[i] 68 | del y_temp[i] 69 | 70 | if dashed: 71 | ax.plot(x_temp[:3], y_temp[:3], color=linecolor, linewidth=3, label=label) 72 | ax.plot(x_temp[2:4], y_temp[2:4], color=linecolor, linewidth=3, linestyle="dashed") 73 | ax.plot(x_temp[3:], y_temp[3:], color=linecolor, linewidth=3, label=label) 74 | else: 75 | ax.plot(x_temp, y_temp, color=linecolor, linewidth=3, label=label) 76 | 77 | 78 | ax.set_ylim([0.01, 20000]) 79 | ax.set_yscale("log") 80 | ax.set_yticks([0.1, 1, 10, 100, 1000, 10000], ["0.1", "1", "10", "100", r"$10^3$", r"$10^4$"]) 81 | ax.grid(axis='y', linestyle='--', alpha=0.6) 82 | ax.set_xlabel("Simulated Cycle", fontsize=22) 83 | ax.tick_params(axis='x', labelsize=18) 84 | ax.tick_params(axis='y', labelsize=16) 85 | 86 | 87 | import matplotlib 88 | import matplotlib.pyplot as plt 89 | import matplotlib.gridspec as gridspec 90 | matplotlib.rcParams['pdf.fonttype'] = 42 91 | matplotlib.rcParams['ps.fonttype'] = 42 92 | gs = gridspec.GridSpec(3, 4, width_ratios=[1, 1, 1, 1], height_ratios=[1, 8, 1]) 93 | fig = plt.figure(figsize=(28,5)) 94 | ax0 = fig.add_subplot(gs[1, 0]) 95 | ax1 = fig.add_subplot(gs[1, 1]) 96 | ax2 = fig.add_subplot(gs[1, 2]) 97 | ax3 = fig.add_subplot(gs[1, 3]) 98 | 99 | time_to_plot = [[y[1:-1] for y in yy] for yy in result["time"]] 100 | model_to_plot = [[y[1:-1] for y in yy] for yy in result["model"]] 101 | plot_arch(ax0, time_to_plot[0], model_to_plot[0], connect_last_with_dashed[0]) 102 | plot_arch(ax1, time_to_plot[1], model_to_plot[1], connect_last_with_dashed[1]) 103 | plot_arch(ax2, time_to_plot[2], model_to_plot[2], connect_last_with_dashed[2]) 104 | plot_arch(ax3, time_to_plot[3], model_to_plot[3], connect_last_with_dashed[3]) 105 | 106 | 107 | ax0.set_ylabel("Checking Time (min)", fontsize=22) 108 | ax0.yaxis.set_label_coords(-0.15, 0.47) 109 | legend = ax0.legend(loc="lower left", bbox_to_anchor=(-0.018, 1.01), ncol=4, fontsize=20) 110 | #legend = ax0.legend(loc="lower left", bbox_to_anchor=(4.62, 0.0), ncol=1, fontsize=20) 111 | ax0.add_artist(legend) 112 | label1 = plt.scatter([], [], marker="o", s=320, alpha=0.7, color="black",edgecolor='None', label="no counterexample") 113 | label2 = plt.scatter([], [], marker="x", s=280, lw=3, alpha=0.7, color="black",edgecolor='None', label="counterexample") 114 | ax0.legend(handles=(label1, label2), loc="lower left", bbox_to_anchor=(2.73, 1.01), ncol=2, fontsize=20) 115 | #ax0.legend(handles=(label1, label2), loc="lower left", bbox_to_anchor=(4.62, 0.65), ncol=1, fontsize=20) 116 | 117 | 118 | ax0.text(0.02, -0.36, "(a) Baseline O3 Processor", fontsize=22, fontweight="bold", transform=ax0.transAxes) 119 | ax1.text(0.16, -0.36, "(b) Delay-on-miss", fontsize=22, fontweight="bold", transform=ax1.transAxes) 120 | ax2.text(0.04, -0.36, "(c) Invisible Speculation", fontsize=22, fontweight="bold", transform=ax2.transAxes) 121 | ax3.text(0.20, -0.36, "(d) GhostMinion", fontsize=22, fontweight="bold", transform=ax3.transAxes) 122 | 123 | 124 | 125 | plt.savefig(resultDir + "/performance.pdf", bbox_inches="tight") 126 | 127 | 128 | print(index[:]) 129 | print("\n\n") 130 | print(model[:]) 131 | print("\n\n") 132 | print(time[:]) 133 | 134 | -------------------------------------------------------------------------------- /result/Figure10/print.py: -------------------------------------------------------------------------------- 1 | 2 | import sys, os 3 | sys.path.append(os.getcwd()) 4 | from script.plot_helper import getResult 5 | import numpy as np 6 | 7 | 8 | resultDir = os.path.dirname(os.path.abspath(__file__)) 9 | shape = [4, 4, 8] 10 | param = ["CPU_OOO_ROB_size", "CPU-simuCycle"] 11 | num_test = 128 12 | 13 | 14 | result = getResult(resultDir) 15 | time = np.array(result["time"]) 16 | index = np.array(result["index"]) 17 | model = np.array(result["model"]) 18 | 19 | 20 | print(index[:]) 21 | print("\n\n") 22 | print(model[:]) 23 | print("\n\n") 24 | print(time) 25 | print("\n\n") 26 | 27 | -------------------------------------------------------------------------------- /result/Figure10/run_local.py: -------------------------------------------------------------------------------- 1 | 2 | import sys, os 3 | sys.path.append(os.getcwd()) 4 | 5 | 6 | def get_experiment_list(): 7 | param_saved_params_list = ["spectre", "DoM", "invisiSpec", "GhostMinion"] 8 | param_ROB_size_list = [2, 4, 8, 16] 9 | param_CPU_simuCycle_list = [3, 4, 5, 6, 7, 8, 9, 10] 10 | 11 | experiment_list = [] 12 | inputId = 0 13 | for param_saved_params in param_saved_params_list: 14 | for param_ROB_size in param_ROB_size_list: 15 | for param_CPU_simuCycle in param_CPU_simuCycle_list: 16 | inputParam = "++arg --param-debug-assert ++arg 0 " \ 17 | + "++arg --param-saved-params ++arg %s " % param_saved_params \ 18 | + "++arg --param-ROB-size ++arg %d " % param_ROB_size \ 19 | + "++arg --param-CPU-simuCycle ++arg %d " % param_CPU_simuCycle 20 | 21 | experiment_list.append({"inputParam": inputParam, "inputId": str(inputId)}) 22 | inputId += 1 23 | print("[experiment_list]:", experiment_list) 24 | return experiment_list 25 | 26 | 27 | if __name__ == "__main__": 28 | from script.run_helper_local import runBatch 29 | runBatch(os.path.dirname(os.path.abspath(__file__)), get_experiment_list()) 30 | 31 | -------------------------------------------------------------------------------- /result/Figure10/summary.json: -------------------------------------------------------------------------------- 1 | {"time": [[[0, 0, 5, 27, 84, 183, 388, 749], [0, 1, 6, 26, 89, 188, 492, 1068], [0, 2, 14, 53, 207, 527, 1110, 2033], [0, 9, 42, 147, 461, 1577, 4152, 7811]], [[0, 0, 5, 94, 530, 10976, -1, -1], [0, 1, 5, 24, 66, 212, 450, 994], [0, 1, 10, 48, 118, 458, 1069, 1970], [0, 4, 22, 110, 569, 1362, 3881, 9721]], [[0, 1, 9, 105, 852, 420, 1854, 1388], [0, 2, 9, 45, 92, 257, 778, 1808], [0, 3, 14, 89, 319, 667, 1311, 3326], [0, 9, 51, 194, 878, 2094, 4353, 10591]], [[0, 1, 8, 114, 916, 271, 30414, 3689], [0, 2, 83, 409, 249358, 394, 733, 1427], [0, 3, 85, 1219, 387794, 742, 1860, 3059], [0, 9, 128, 1938, -1, 2254, 5144, 8898]]], "model": [[[0, 0, 1, 1, 1, 1, 1, 1], [0, 1, 1, 1, 1, 1, 1, 1], [0, 1, 1, 1, 1, 1, 1, 1], [0, 1, 1, 1, 1, 1, 1, 1]], [[0, 0, 0, 0, 0, 0, -1, -1], [0, 1, 1, 1, 1, 1, 1, 1], [0, 1, 1, 1, 1, 1, 1, 1], [0, 1, 1, 1, 1, 1, 1, 1]], [[0, 0, 0, 0, 0, 1, 1, 1], [0, 1, 1, 1, 1, 1, 1, 1], [0, 1, 1, 1, 1, 1, 1, 1], [0, 1, 1, 1, 1, 1, 1, 1]], [[0, 0, 0, 0, 0, 1, 1, 1], [0, 0, 0, 0, 0, 1, 1, 1], [0, 0, 0, 0, 0, 1, 1, 1], [0, 0, 0, 0, -1, 1, 1, 1]]], "index": [[[0, 1, 2, 3, 4, 5, 6, 7], [8, 9, 10, 11, 12, 13, 14, 15], [16, 17, 18, 19, 20, 21, 22, 23], [24, 25, 26, 27, 28, 29, 30, 31]], [[32, 33, 34, 35, 36, 37, 38, 39], [40, 41, 42, 43, 44, 45, 46, 47], [48, 49, 50, 51, 52, 53, 54, 55], [56, 57, 58, 59, 60, 61, 62, 63]], [[64, 65, 66, 67, 68, 69, 70, 71], [72, 73, 74, 75, 76, 77, 78, 79], [80, 81, 82, 83, 84, 85, 86, 87], [88, 89, 90, 91, 92, 93, 94, 95]], [[96, 97, 98, 99, 100, 101, 102, 103], [104, 105, 106, 107, 108, 109, 110, 111], [112, 113, 114, 115, 116, 117, 118, 119], [120, 121, 122, 123, 124, 125, 126, 127]]]} -------------------------------------------------------------------------------- /result/Figure10/summary.py: -------------------------------------------------------------------------------- 1 | 2 | import sys, os 3 | sys.path.append(os.getcwd()) 4 | from script.summary_helper import summary 5 | import numpy as np 6 | 7 | 8 | resultDir = os.path.dirname(os.path.abspath(__file__)) 9 | num_test = 128 10 | shape = [4, 4, 8] 11 | 12 | summary(resultDir, num_test, shape) 13 | 14 | -------------------------------------------------------------------------------- /result/GhostMinion.log: -------------------------------------------------------------------------------- 1 | root@0691dfed0aa1:/vagrant# raco test \ 2 | > ++arg --param-saved-params ++arg GhostMinion \ 3 | > ++arg --param-saved-sizes ++arg GhostMinion \ 4 | > src/main_veriSpec.rkt 5 | raco test: "src/main_veriSpec.rkt" "--param-saved-params" "GhostMinion" "--param-saved-sizes" "GhostMinion" 6 | Tests for veriSpec 7 | [ RUN ] "get-bug-info" 8 | Finish Symbolic Execution. 9 | Finish STM Solver. 10 | Find Counterexample. 11 | CPU: 12 | debug-commitLog: () underSpec: #f specBr-ROBlink(bv #b00 2) 13 | memi: history: () 14 | Dcache: 15 | history: (0 0 0 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ) 16 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 17 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 18 | adder: 19 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 20 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 21 | ROB: 22 | head: 0, tail: 0 23 | idle: (#t #t #t #t ), waiting: (#f #f #f #f ) 24 | executing: (#f #f #f #f ), finished: (#f #f #f #f ) 25 | pc: (0 0 0 0 ), op: (0 0 0 0 ), brID: (0 0 0 0 ) 26 | underSpec: (#f #f #f #f ), specBr-ROBlink: (0 0 0 0 ) 27 | 28 | 29 | 30 | datainReady: #f ROBlink: (bv #b00 2) 31 | datainReady: #f ROBlink: (bv #b00 2) 32 | datainReady: #f ROBlink: (bv #b00 2) 33 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 34 | CPU: 35 | debug-commitLog: () underSpec: #f specBr-ROBlink(bv #b00 2) 36 | memi: history: (0 1 ) 37 | Dcache: 38 | history: (0 0 0 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ) 39 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 40 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 41 | adder: 42 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 43 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 44 | ROB: 45 | head: 0, tail: 0 46 | idle: (#t #t #t #t ), waiting: (#f #f #f #f ) 47 | executing: (#f #f #f #f ), finished: (#f #f #f #f ) 48 | pc: (0 0 0 0 ), op: (0 0 0 0 ), brID: (0 0 0 0 ) 49 | underSpec: (#f #f #f #f ), specBr-ROBlink: (0 0 0 0 ) 50 | 51 | 52 | 53 | datainReady: #f ROBlink: (bv #b00 2) 54 | datainReady: #f ROBlink: (bv #b00 2) 55 | datainReady: #f ROBlink: (bv #b00 2) 56 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 57 | ---->pc: (bv #x0 4) underSpec: #f specBr-ROBlink: (bv #b00 2) 58 | ---->pc: (bv #x1 4) underSpec: #f specBr-ROBlink: (bv #b01 2) 59 | ---->pc: (bv #x2 4) underSpec: #t 60 | CPU: 61 | debug-commitLog: () underSpec: #f specBr-ROBlink(bv #b00 2) 62 | memi: history: (0 1 2 11 ) 63 | Dcache: 64 | history: (0 0 0 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ) 65 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 66 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 67 | adder: 68 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 69 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 70 | ROB: 71 | head: 0, tail: 2 72 | idle: (#f #f #t #t ), waiting: (#t #t #f #f ) 73 | executing: (#f #f #f #f ), finished: (#f #f #f #f ) 74 | pc: (0 1 0 0 ), op: (3 1 0 0 ), brID: (0 1 0 0 ) 75 | underSpec: (#f #f #f #f ), specBr-ROBlink: (0 0 0 0 ) 76 | 77 | 78 | 79 | datainReady: #t ROBlink: (bv #b01 2) 80 | datainReady: #f ROBlink: (bv #b00 2) 81 | datainReady: #t ROBlink: (bv #b00 2) 82 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 83 | ---->pc: (bv #x2 4) underSpec: #t specBr-ROBlink: (bv #b10 2) 84 | ---->pc: (bv #xb 4) underSpec: #f specBr-ROBlink: (bv #b11 2) 85 | ---->pc: (bv #xd 4) underSpec: #t 86 | return ROBlink: (bv #b01 2) 87 | CPU: 88 | debug-commitLog: () underSpec: #t specBr-ROBlink(bv #b10 2) 89 | memi: history: (0 1 2 11 12 13 ) 90 | Dcache: 91 | history: (0 0 1 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ) 92 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 93 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 94 | adder: 95 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 96 | absDelay: history-valid: (0 0 1 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 1 0 0 0 0 0 ) 97 | ROB: 98 | head: 0, tail: 0 99 | idle: (#f #f #f #f ), waiting: (#f #f #t #t ) 100 | executing: (#f #f #f #f ), finished: (#t #t #f #f ) 101 | pc: (0 1 2 11 ), op: (3 1 5 3 ), brID: (0 1 2 3 ) 102 | underSpec: (#f #f #f #t ), specBr-ROBlink: (0 0 0 2 ) 103 | 104 | 105 | 106 | datainReady: #f ROBlink: (bv #b00 2) 107 | datainReady: #f ROBlink: (bv #b00 2) 108 | datainReady: #t ROBlink: (bv #b11 2) 109 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 110 | ---->pc: (bv #xc 4) underSpec: #f specBr-ROBlink: (bv #b00 2) 111 | ---->pc: (bv #x9 4) underSpec: #t 112 | ---->pc: (bv #x2 4) underSpec: #t 113 | return ROBlink: (bv #b11 2) 114 | CPU: 115 | debug-commitLog: ((0 1 2)) underSpec: #t specBr-ROBlink(bv #b10 2) 116 | memi: history: (0 1 2 11 12 13 9 2 ) 117 | Dcache: 118 | history: (0 0 1 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 1 0 0 0 0 )(0 0 0 2 0 0 0 0 ) 119 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 120 | absDelay: history-valid: (0 0 0 1 0 0 0 0 )history-timFct: (0 0 0 2 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 3 0 0 0 0 ) 121 | adder: 122 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 123 | absDelay: history-valid: (0 0 1 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 1 0 0 0 0 0 ) 124 | ROB: 125 | head: 1, tail: 1 126 | idle: (#f #f #f #f ), waiting: (#t #f #f #f ) 127 | executing: (#f #f #f #f ), finished: (#f #t #t #t ) 128 | pc: (12 1 2 11 ), op: (3 1 5 3 ), brID: (4 1 2 3 ) 129 | underSpec: (#t #f #f #t ), specBr-ROBlink: (2 0 0 2 ) 130 | 131 | 132 | 133 | datainReady: #f ROBlink: (bv #b00 2) 134 | datainReady: #f ROBlink: (bv #b00 2) 135 | datainReady: #t ROBlink: (bv #b00 2) 136 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 137 | ---->pc: (bv #xd 4) underSpec: #t specBr-ROBlink: (bv #b01 2) 138 | CPU: 139 | debug-commitLog: ((0 1 2) (1 0 1)) underSpec: #t specBr-ROBlink(bv #b01 2) 140 | memi: history: (0 1 2 11 12 13 9 2 11 12 ) 141 | Dcache: 142 | history: (0 0 1 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 1 1 0 0 0 )(0 0 0 2 3 0 0 0 ) 143 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 144 | absDelay: history-valid: (0 0 0 1 0 0 0 0 )history-timFct: (0 0 0 2 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 3 0 0 0 0 ) 145 | adder: 146 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 147 | absDelay: history-valid: (0 0 1 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 1 0 0 0 0 0 ) 148 | ROB: 149 | head: 2, tail: 2 150 | idle: (#f #f #f #f ), waiting: (#f #t #f #f ) 151 | executing: (#f #f #f #f ), finished: (#t #f #t #t ) 152 | pc: (12 13 2 11 ), op: (3 5 5 3 ), brID: (4 5 2 3 ) 153 | underSpec: (#t #t #f #t ), specBr-ROBlink: (2 2 0 2 ) 154 | 155 | 156 | 157 | datainReady: #f ROBlink: (bv #b00 2) 158 | datainReady: #f ROBlink: (bv #b00 2) 159 | datainReady: #f ROBlink: (bv #b00 2) 160 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 161 | CPU: 162 | debug-commitLog: ((0 1 2) (1 0 1) (2)) underSpec: #f specBr-ROBlink(bv #b01 2) 163 | memi: history: (0 1 2 11 12 13 9 2 11 12 3 4 ) 164 | Dcache: 165 | history: (0 0 1 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 1 1 0 0 0 )(0 0 0 2 3 0 0 0 ) 166 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 167 | absDelay: history-valid: (0 0 0 1 0 0 0 0 )history-timFct: (0 0 0 2 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 168 | adder: 169 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 170 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 171 | ROB: 172 | head: 0, tail: 0 173 | idle: (#t #t #t #t ), waiting: (#f #f #f #f ) 174 | executing: (#f #f #f #f ), finished: (#f #f #f #f ) 175 | pc: (0 0 0 0 ), op: (0 0 0 0 ), brID: (0 0 0 0 ) 176 | underSpec: (#f #f #f #f ), specBr-ROBlink: (0 0 0 0 ) 177 | 178 | 179 | 180 | datainReady: #f ROBlink: (bv #b00 2) 181 | datainReady: #f ROBlink: (bv #b00 2) 182 | datainReady: #f ROBlink: (bv #b00 2) 183 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 184 | ---->pc: (bv #x3 4) underSpec: #f specBr-ROBlink: (bv #b00 2) 185 | ---->pc: (bv #x4 4) underSpec: #f specBr-ROBlink: (bv #b01 2) 186 | CPU: 187 | debug-commitLog: ((0 1 2) (1 0 1) (2)) underSpec: #f specBr-ROBlink(bv #b01 2) 188 | memi: history: (0 1 2 11 12 13 9 2 11 12 3 4 5 6 ) 189 | Dcache: 190 | history: (0 0 1 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 1 1 0 0 0 )(0 0 0 2 3 0 0 0 ) 191 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 192 | absDelay: history-valid: (0 0 0 1 0 0 0 0 )history-timFct: (0 0 0 2 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 193 | adder: 194 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 195 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 196 | ROB: 197 | head: 0, tail: 2 198 | idle: (#f #f #t #t ), waiting: (#t #t #f #f ) 199 | executing: (#f #f #f #f ), finished: (#f #f #f #f ) 200 | pc: (3 4 0 0 ), op: (2 3 0 0 ), brID: (6 7 0 0 ) 201 | underSpec: (#f #f #f #f ), specBr-ROBlink: (1 1 0 0 ) 202 | 203 | 204 | 205 | datainReady: #f ROBlink: (bv #b00 2) 206 | datainReady: #t ROBlink: (bv #b00 2) 207 | datainReady: #t ROBlink: (bv #b01 2) 208 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 209 | return ROBlink: (bv #b00 2) 210 | return ROBlink: (bv #b01 2) 211 | CPU: 212 | debug-commitLog: () underSpec: #f specBr-ROBlink(bv #b00 2) 213 | memi: history: () 214 | Dcache: 215 | history: (0 0 0 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ) 216 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 217 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 218 | adder: 219 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 220 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 221 | ROB: 222 | head: 0, tail: 0 223 | idle: (#t #t #t #t ), waiting: (#f #f #f #f ) 224 | executing: (#f #f #f #f ), finished: (#f #f #f #f ) 225 | pc: (0 0 0 0 ), op: (0 0 0 0 ), brID: (0 0 0 0 ) 226 | underSpec: (#f #f #f #f ), specBr-ROBlink: (0 0 0 0 ) 227 | 228 | 229 | 230 | datainReady: #f ROBlink: (bv #b00 2) 231 | datainReady: #f ROBlink: (bv #b00 2) 232 | datainReady: #f ROBlink: (bv #b00 2) 233 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 234 | CPU: 235 | debug-commitLog: () underSpec: #f specBr-ROBlink(bv #b00 2) 236 | memi: history: (0 1 ) 237 | Dcache: 238 | history: (0 0 0 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ) 239 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 240 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 241 | adder: 242 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 243 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 244 | ROB: 245 | head: 0, tail: 0 246 | idle: (#t #t #t #t ), waiting: (#f #f #f #f ) 247 | executing: (#f #f #f #f ), finished: (#f #f #f #f ) 248 | pc: (0 0 0 0 ), op: (0 0 0 0 ), brID: (0 0 0 0 ) 249 | underSpec: (#f #f #f #f ), specBr-ROBlink: (0 0 0 0 ) 250 | 251 | 252 | 253 | datainReady: #f ROBlink: (bv #b00 2) 254 | datainReady: #f ROBlink: (bv #b00 2) 255 | datainReady: #f ROBlink: (bv #b00 2) 256 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 257 | ---->pc: (bv #x0 4) underSpec: #f specBr-ROBlink: (bv #b00 2) 258 | ---->pc: (bv #x1 4) underSpec: #f specBr-ROBlink: (bv #b01 2) 259 | ---->pc: (bv #x2 4) underSpec: #t 260 | CPU: 261 | debug-commitLog: () underSpec: #f specBr-ROBlink(bv #b00 2) 262 | memi: history: (0 1 2 11 ) 263 | Dcache: 264 | history: (0 0 0 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ) 265 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 266 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 267 | adder: 268 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 269 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 270 | ROB: 271 | head: 0, tail: 2 272 | idle: (#f #f #t #t ), waiting: (#t #t #f #f ) 273 | executing: (#f #f #f #f ), finished: (#f #f #f #f ) 274 | pc: (0 1 0 0 ), op: (3 1 0 0 ), brID: (0 1 0 0 ) 275 | underSpec: (#f #f #f #f ), specBr-ROBlink: (0 0 0 0 ) 276 | 277 | 278 | 279 | datainReady: #t ROBlink: (bv #b01 2) 280 | datainReady: #f ROBlink: (bv #b00 2) 281 | datainReady: #t ROBlink: (bv #b00 2) 282 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 283 | ---->pc: (bv #x2 4) underSpec: #t specBr-ROBlink: (bv #b10 2) 284 | ---->pc: (bv #xb 4) underSpec: #f specBr-ROBlink: (bv #b11 2) 285 | ---->pc: (bv #xd 4) underSpec: #t 286 | return ROBlink: (bv #b01 2) 287 | CPU: 288 | debug-commitLog: () underSpec: #t specBr-ROBlink(bv #b10 2) 289 | memi: history: (0 1 2 11 12 13 ) 290 | Dcache: 291 | history: (0 0 1 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ) 292 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 293 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 294 | adder: 295 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 296 | absDelay: history-valid: (0 0 1 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 1 0 0 0 0 0 ) 297 | ROB: 298 | head: 0, tail: 0 299 | idle: (#f #f #f #f ), waiting: (#f #f #t #t ) 300 | executing: (#f #f #f #f ), finished: (#t #t #f #f ) 301 | pc: (0 1 2 11 ), op: (3 1 5 3 ), brID: (0 1 2 3 ) 302 | underSpec: (#f #f #f #t ), specBr-ROBlink: (0 0 0 2 ) 303 | 304 | 305 | 306 | datainReady: #f ROBlink: (bv #b00 2) 307 | datainReady: #f ROBlink: (bv #b00 2) 308 | datainReady: #t ROBlink: (bv #b11 2) 309 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 310 | ---->pc: (bv #xc 4) underSpec: #f specBr-ROBlink: (bv #b00 2) 311 | ---->pc: (bv #x9 4) underSpec: #t 312 | ---->pc: (bv #x2 4) underSpec: #t 313 | return ROBlink: (bv #b11 2) 314 | CPU: 315 | debug-commitLog: ((0 1 3)) underSpec: #t specBr-ROBlink(bv #b10 2) 316 | memi: history: (0 1 2 11 12 13 9 2 ) 317 | Dcache: 318 | history: (0 0 1 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 1 0 0 0 0 )(0 0 0 3 0 0 0 0 ) 319 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 320 | absDelay: history-valid: (0 0 0 1 0 0 0 0 )history-timFct: (0 0 0 3 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 3 0 0 0 0 ) 321 | adder: 322 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 323 | absDelay: history-valid: (0 0 1 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 1 0 0 0 0 0 ) 324 | ROB: 325 | head: 1, tail: 1 326 | idle: (#f #f #f #f ), waiting: (#t #f #f #f ) 327 | executing: (#f #f #f #f ), finished: (#f #t #t #t ) 328 | pc: (12 1 2 11 ), op: (3 1 5 3 ), brID: (4 1 2 3 ) 329 | underSpec: (#t #f #f #t ), specBr-ROBlink: (2 0 0 2 ) 330 | 331 | 332 | 333 | datainReady: #f ROBlink: (bv #b00 2) 334 | datainReady: #f ROBlink: (bv #b00 2) 335 | datainReady: #t ROBlink: (bv #b00 2) 336 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 337 | ---->pc: (bv #xd 4) underSpec: #t specBr-ROBlink: (bv #b01 2) 338 | CPU: 339 | debug-commitLog: ((0 1 3) (1 0 1)) underSpec: #t specBr-ROBlink(bv #b01 2) 340 | memi: history: (0 1 2 11 12 13 9 2 11 12 ) 341 | Dcache: 342 | history: (0 0 1 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 1 1 0 0 0 )(0 0 0 3 3 0 0 0 ) 343 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 344 | absDelay: history-valid: (0 0 0 1 0 0 0 0 )history-timFct: (0 0 0 3 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 3 0 0 0 0 ) 345 | adder: 346 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 347 | absDelay: history-valid: (0 0 1 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 1 0 0 0 0 0 ) 348 | ROB: 349 | head: 2, tail: 2 350 | idle: (#f #f #f #f ), waiting: (#f #t #f #f ) 351 | executing: (#f #f #f #f ), finished: (#t #f #t #t ) 352 | pc: (12 13 2 11 ), op: (3 5 5 3 ), brID: (4 5 2 3 ) 353 | underSpec: (#t #t #f #t ), specBr-ROBlink: (2 2 0 2 ) 354 | 355 | 356 | 357 | datainReady: #f ROBlink: (bv #b00 2) 358 | datainReady: #f ROBlink: (bv #b00 2) 359 | datainReady: #f ROBlink: (bv #b00 2) 360 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 361 | CPU: 362 | debug-commitLog: ((0 1 3) (1 0 1) (2)) underSpec: #f specBr-ROBlink(bv #b01 2) 363 | memi: history: (0 1 2 11 12 13 9 2 11 12 3 4 ) 364 | Dcache: 365 | history: (0 0 1 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 1 1 0 0 0 )(0 0 0 3 3 0 0 0 ) 366 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 367 | absDelay: history-valid: (0 0 0 1 0 0 0 0 )history-timFct: (0 0 0 3 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 368 | adder: 369 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 370 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 371 | ROB: 372 | head: 0, tail: 0 373 | idle: (#t #t #t #t ), waiting: (#f #f #f #f ) 374 | executing: (#f #f #f #f ), finished: (#f #f #f #f ) 375 | pc: (0 0 0 0 ), op: (0 0 0 0 ), brID: (0 0 0 0 ) 376 | underSpec: (#f #f #f #f ), specBr-ROBlink: (0 0 0 0 ) 377 | 378 | 379 | 380 | datainReady: #f ROBlink: (bv #b00 2) 381 | datainReady: #f ROBlink: (bv #b00 2) 382 | datainReady: #f ROBlink: (bv #b00 2) 383 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 384 | ---->pc: (bv #x3 4) underSpec: #f specBr-ROBlink: (bv #b00 2) 385 | ---->pc: (bv #x4 4) underSpec: #f specBr-ROBlink: (bv #b01 2) 386 | CPU: 387 | debug-commitLog: ((0 1 3) (1 0 1) (2)) underSpec: #f specBr-ROBlink(bv #b01 2) 388 | memi: history: (0 1 2 11 12 13 9 2 11 12 3 4 5 6 ) 389 | Dcache: 390 | history: (0 0 1 0 0 0 0 0 )(0 0 0 0 0 0 0 0 ), invisi: (0 0 0 1 1 0 0 0 )(0 0 0 3 3 0 0 0 ) 391 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 392 | absDelay: history-valid: (0 0 0 1 0 0 0 0 )history-timFct: (0 0 0 3 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 393 | adder: 394 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 395 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 396 | ROB: 397 | head: 0, tail: 2 398 | idle: (#f #f #t #t ), waiting: (#t #t #f #f ) 399 | executing: (#f #f #f #f ), finished: (#f #f #f #f ) 400 | pc: (3 4 0 0 ), op: (2 3 0 0 ), brID: (6 7 0 0 ) 401 | underSpec: (#f #f #f #f ), specBr-ROBlink: (1 1 0 0 ) 402 | 403 | 404 | 405 | datainReady: #f ROBlink: (bv #b00 2) 406 | datainReady: #t ROBlink: (bv #b00 2) 407 | datainReady: #t ROBlink: (bv #b01 2) 408 | squash-E: #f misPredBr-ROBlink-E: (bv #b00 2) misPredBr-brID-E: (bv #xf 4) nextPC-E: (bv #x0 4) 409 | return ROBlink: (bv #b00 2) 410 | Finish SMT Result Evaluation. 411 | cfg: memi: 412 | (0-th INST Ld 14 2 1 : Reg[1] <- Mem[Reg[2]] 413 | 1-th INST Add 15 0 0 : Reg[0] <- Reg[3] + Reg[0] 414 | 2-th INST Br 9 0 2 : If (Reg[0]==0) PC <- PC + 9 415 | 3-th INST Mul 13 1 1 : Reg[1] <- Reg[1] * Reg[1] 416 | 4-th INST Ld 15 3 0 : Reg[0] <- Mem[Reg[3]] 417 | 5-th INST Add 12 0 3 : Reg[3] <- Reg[0] + Reg[0] 418 | 6-th INST Mul 5 1 1 : Reg[1] <- Reg[1] * Reg[1] 419 | 7-th INST Li 1 2 2 : Reg[2] <- 1 420 | 8-th INST Mul 14 2 1 : Reg[1] <- Reg[2] * Reg[2] 421 | 9-th INST Br 9 1 2 : If (Reg[1]==0) PC <- PC + 9 422 | 10-th INST Mul 11 2 1 : Reg[1] <- Reg[3] * Reg[2] 423 | 11-th INST Ld 13 1 2 : Reg[2] <- Mem[Reg[1]] 424 | 12-th INST Ld 7 3 1 : Reg[1] <- Mem[Reg[3]] 425 | 13-th INST Br 12 2 2 : If (Reg[2]==0) PC <- PC + 12 426 | 14-th INST Br 0 0 0 : If (Reg[0]==0) PC <- PC + 0 427 | 15-th INST Ld 0 0 0 : Reg[0] <- Mem[Reg[0]] 428 | )rf: (14 3 0 3 ) 429 | memd-0: (2 0 0 0 ) memd-1: (3 0 0 0 ) 430 | 431 | ISASimulator-0: memi: history: (0 1 2 3 4 5 6 7 8 9 10 11 ) 432 | memd: history: (0: 0, 4: 3, 11: 0, ) array: (2 0 0 0 ) 433 | 434 | ISASimulator-1: memi: history: (0 1 2 3 4 5 6 7 8 9 10 11 ) 435 | memd: history: (0: 0, 4: 3, 11: 0, ) array: (3 0 0 0 ) 436 | 437 | CPU-0: debug-commitLog: ((0 1 2) (1 0 1) (2)) underSpec: #f specBr-ROBlink(bv #b01 2) 438 | memi: history: (0 1 2 11 12 13 9 2 11 12 3 4 5 6 7 8 ) 439 | Dcache: 440 | history: (0 0 1 0 0 0 0 1 )(0 0 0 0 0 0 0 3 ), invisi: (0 0 0 1 1 0 0 0 )(0 0 0 2 3 0 0 0 ) 441 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 442 | absDelay: history-valid: (0 0 0 1 0 0 0 1 )history-timFct: (0 0 0 2 0 0 0 3 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 7 ) 443 | adder: 444 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 445 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 446 | ROB: 447 | head: 0, tail: 2 448 | idle: (#f #f #t #t ), waiting: (#f #f #f #f ) 449 | executing: (#f #f #f #f ), finished: (#t #t #f #f ) 450 | pc: (3 4 0 0 ), op: (2 3 0 0 ), brID: (6 7 0 0 ) 451 | underSpec: (#f #f #f #f ), specBr-ROBlink: (1 1 0 0 ) 452 | 453 | 454 | CPU-1: debug-commitLog: ((0 1 3) (1 0 1) (2)) underSpec: #f specBr-ROBlink(bv #b01 2) 455 | memi: history: (0 1 2 11 12 13 9 2 11 12 3 4 5 6 7 8 ) 456 | Dcache: 457 | history: (0 0 1 0 0 0 0 1 )(0 0 0 0 0 0 0 3 ), invisi: (0 0 0 1 1 0 0 0 )(0 0 0 3 3 0 0 0 ) 458 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 459 | absDelay: history-valid: (0 0 0 1 0 0 0 1 )history-timFct: (0 0 0 3 0 0 0 3 )buffer-valid: (0 0 0 0 0 0 0 1 )buffer-brID: (0 0 0 0 0 0 0 7 ) 460 | adder: 461 | absArbiter: timFct: (0 0 0 0 )valid: (0 0 0 0 ) 462 | absDelay: history-valid: (0 0 0 0 0 0 0 0 )history-timFct: (0 0 0 0 0 0 0 0 )buffer-valid: (0 0 0 0 0 0 0 0 )buffer-brID: (0 0 0 0 0 0 0 0 ) 463 | ROB: 464 | head: 0, tail: 2 465 | idle: (#f #f #t #t ), waiting: (#f #f #f #f ) 466 | executing: (#f #t #f #f ), finished: (#t #f #f #f ) 467 | pc: (3 4 0 0 ), op: (2 3 0 0 ), brID: (6 7 0 0 ) 468 | underSpec: (#f #f #f #f ), specBr-ROBlink: (1 1 0 0 ) 469 | 470 | 471 | [ OK ] "get-bug-info" (22561ms cpu) (650714ms real) (337181 terms) 472 | 1 success(es) 0 failure(s) 0 error(s) 1 test(s) run 473 | cpu time: 22562 real time: 650714 gc time: 2541 474 | 0 475 | 1 test passed 476 | root@0691dfed0aa1:/vagrant# 477 | 478 | -------------------------------------------------------------------------------- /script/archive.py: -------------------------------------------------------------------------------- 1 | 2 | import os 3 | 4 | 5 | if __name__ == "__main__": 6 | 7 | command = "cp -r . Pensieve" 8 | print("[command to run]: ", command) 9 | os.system(command) 10 | 11 | command = "rm -rf Pensieve/.git" 12 | print("[command to run]: ", command) 13 | os.system(command) 14 | 15 | command = "find Pensieve -name \".DS_Store\" -print -delete" 16 | print("[command to run]: ", command) 17 | os.system(command) 18 | 19 | command = "zip -r Pensieve.zip Pensieve" 20 | print("[command to run]: ", command) 21 | os.system(command) 22 | 23 | command = "rm -rf Pensieve" 24 | print("[command to run]: ", command) 25 | os.system(command) 26 | 27 | -------------------------------------------------------------------------------- /script/plot_helper.py: -------------------------------------------------------------------------------- 1 | 2 | import json 3 | import numpy as np 4 | 5 | 6 | def getResult(resultDir): 7 | with open(resultDir + "/summary.json",'r') as f: 8 | result = json.load(f, object_hook=lambda d: {int(k) if k.lstrip('-').isdigit() else k: v for k, v in d.items()}) 9 | return result 10 | 11 | -------------------------------------------------------------------------------- /script/run.py: -------------------------------------------------------------------------------- 1 | 2 | if __name__ == "__main__": 3 | 4 | #sudo renice -n -20 -u yuhengy 5 | command = "raco test src/main_veriSpec.rkt" 6 | #command = "raco symtrace src/main_veriSpec.rkt" 7 | #command = "raco symprofile src/main_veriSpec.rkt" 8 | print("[command to run]: ", command) 9 | 10 | import os 11 | os.system(command) 12 | 13 | -------------------------------------------------------------------------------- /script/run_helper_local.py: -------------------------------------------------------------------------------- 1 | 2 | 3 | def initClient(): 4 | from dask.distributed import Client, LocalCluster 5 | import time 6 | 7 | # STEP1 choose a cluster 8 | cluster = LocalCluster(threads_per_worker=1) 9 | # cluster = LocalCluster(threads_per_worker=1, n_workers=16) 10 | 11 | time.sleep(1) 12 | print(cluster) 13 | 14 | 15 | # STEP2 setup a client 16 | client = Client(cluster) 17 | 18 | return client 19 | 20 | 21 | def runBatch(resultDir, experiment_list): 22 | import os, time 23 | # STEP1 init the cluster or multiProcess 24 | client = initClient() 25 | 26 | 27 | # STEP2 mark start time 28 | startTime = time.time() 29 | 30 | 31 | # STEP3 run them 32 | futureList = [] 33 | for experiment in experiment_list: 34 | inputParam = experiment["inputParam"] 35 | inputId = experiment["inputId"] 36 | cmd = "raco test --timeout 604800 %s %s/src/main_veriSpec.rkt >> %s/runbatch-%s.out" % \ 37 | (inputParam, os.getcwd(), resultDir, inputId) 38 | futureList.append(client.submit(os.system, cmd)) 39 | 40 | for i, future in enumerate(futureList): 41 | future.result() 42 | print("----------> Finish %d/%d Simu, After %f minutes" % \ 43 | (i+1, len(experiment_list), (time.time() - startTime)/60)) 44 | 45 | -------------------------------------------------------------------------------- /script/summary_helper.py: -------------------------------------------------------------------------------- 1 | 2 | import json 3 | import numpy as np 4 | 5 | PRINT_FAIL = False 6 | 7 | 8 | def summary(resultDir, num_test, shape): 9 | 10 | def getTime(fileName): 11 | try: 12 | with open(fileName) as f: 13 | for line in f.readlines(): 14 | words = line.split() 15 | if len(words) > 0 and words[0] == "cpu": 16 | return int(int(words[5]) / 1000) 17 | except: 18 | return -1 19 | if PRINT_FAIL: 20 | print(fileName + " FAIL!!!") 21 | return -1 22 | 23 | def getModel(fileName): 24 | finished = False 25 | try: 26 | with open(fileName) as f: 27 | for line in f.readlines(): 28 | words = line.split() 29 | if len(words) > 0 and words[0] == "cpu": 30 | finished = True 31 | if len(words) > 0 and words[0] == "Find": 32 | return 1 # find attack program 33 | 34 | except: 35 | return -1 # smt have not finished 36 | 37 | if not finished: 38 | return -1 # smt have not finished 39 | 40 | return 0 # is secure 41 | 42 | 43 | # STEP1: Collect 44 | result = {} 45 | time = [] 46 | model = [] 47 | for i in range(num_test): 48 | time.append(getTime(resultDir + "/runbatch-%d.out" % i)) 49 | model.append(getModel(resultDir + "/runbatch-%d.out" % i)) 50 | result["time"] = np.reshape(time, shape).tolist() 51 | result["model"] = np.reshape(model, shape).tolist() 52 | result["index"] = np.reshape(range(num_test), shape).tolist() 53 | 54 | 55 | # STEP2: Write to Buffer 56 | with open(resultDir + "/summary.json", "w") as f: 57 | json.dump(result, f) 58 | return result 59 | 60 | -------------------------------------------------------------------------------- /src/CPU/ROB.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "../lib/lib.rkt" "../inst.rkt") 5 | (provide 6 | (struct-out ROB) init-ROB forward-ROB! ROB->brInfo clear-ROB-entry! 7 | squashPartial-ROB! resetsym-ROB! ROB-full ROB-empty 8 | ) 9 | 10 | 11 | (struct ROB ( 12 | idle waiting executing finished 13 | pc op 14 | rs1-imm rs1-brOffset rs1-stall rs1-data rs1-ROBlink 15 | rs2-stall rs2-data rs2-ROBlink 16 | wen rd rd-data 17 | mem-valid mem-rdwt mem-addr mem-data 18 | isBr brID taken pred-taken nextPC 19 | delayed-until-nonSpec underSpec specBr-ROBlink 20 | head tail) 21 | #:mutable #:transparent 22 | #:methods gen:custom-write 23 | [(define (write-proc this port mode) 24 | (write-string (ROB->string this) port))] 25 | ) 26 | 27 | 28 | (define (init-ROB) 29 | (ROB 30 | (init-array (make-vector param-ROB-size #t) param-ROB-size 1) 31 | (initFalseVec-array param-ROB-size) 32 | (initFalseVec-array param-ROB-size) 33 | (initFalseVec-array param-ROB-size) 34 | 35 | (initZeroVec-array param-ROB-size param-memi-size-log) 36 | (initZeroVec-array param-ROB-size inst-size-log) 37 | 38 | (initZeroVec-array param-ROB-size param-reg-len) 39 | (initZeroVec-array param-ROB-size param-memi-size-log) 40 | (initFalseVec-array param-ROB-size) 41 | (initZeroVec-array param-ROB-size param-reg-len) 42 | (initZeroVec-array param-ROB-size param-ROB-size-log) 43 | (initFalseVec-array param-ROB-size) 44 | (initZeroVec-array param-ROB-size param-reg-len) 45 | (initZeroVec-array param-ROB-size param-ROB-size-log) 46 | 47 | (initFalseVec-array param-ROB-size) 48 | (initZeroVec-array param-ROB-size param-rf-size-log) 49 | (initZeroVec-array param-ROB-size param-reg-len) 50 | 51 | (initFalseVec-array param-ROB-size) 52 | (initFalseVec-array param-ROB-size) 53 | (initZeroVec-array param-ROB-size param-memd-size-log) 54 | (initZeroVec-array param-ROB-size param-reg-len) 55 | 56 | (initFalseVec-array param-ROB-size) 57 | (initZeroVec-array param-ROB-size param-brID-len) 58 | (initFalseVec-array param-ROB-size) 59 | (initFalseVec-array param-ROB-size) 60 | (initZeroVec-array param-ROB-size param-memi-size-log) 61 | 62 | (initFalseVec-array param-ROB-size) 63 | (initFalseVec-array param-ROB-size) 64 | (initZeroVec-array param-ROB-size param-ROB-size-log) 65 | 66 | (bv 0 param-ROB-size-log) 67 | (bv 0 param-ROB-size-log)) 68 | ) 69 | 70 | 71 | ; NOTE: Putting the rd-data as argument instead of reading it from ROB 72 | ; is an optimization for symbolic execution 73 | (define (forward-ROB! ROB pos rd-data) 74 | (for ([i (in-range param-ROB-size)]) 75 | (define i-bv (integer->bitvector i (bitvector param-ROB-size-log))) 76 | (when (not (array-ref (ROB-idle ROB) i-bv)) 77 | (when (and (array-ref (ROB-rs1-stall ROB) i-bv) 78 | (bveq pos (array-ref (ROB-rs1-ROBlink ROB) i-bv))) 79 | (set-array! (ROB-rs1-stall ROB) i-bv #f) 80 | (set-array! (ROB-rs1-data ROB) i-bv rd-data)) 81 | (when (and (array-ref (ROB-rs2-stall ROB) i-bv) 82 | (bveq pos (array-ref (ROB-rs2-ROBlink ROB) i-bv))) 83 | (set-array! (ROB-rs2-stall ROB) i-bv #f) 84 | (set-array! (ROB-rs2-data ROB) i-bv rd-data)))) 85 | ) 86 | 87 | 88 | ; TODO: we need to consider more info later 89 | (define (ROB->brInfo ROB pos) 90 | (bool->bitvector (and (array-ref (ROB-isBr ROB) pos) 91 | (array-ref (ROB-taken ROB) pos))) 92 | ) 93 | 94 | 95 | (define (clear-ROB-entry! ROB pos) 96 | (set-array! (ROB-idle ROB) pos #t) 97 | (set-array! (ROB-finished ROB) pos #f) 98 | (set-array! (ROB-waiting ROB) pos #f) 99 | (set-array! (ROB-executing ROB) pos #f) 100 | 101 | (set-array! (ROB-pc ROB) pos (bv 0 param-memi-size-log)) 102 | (set-array! (ROB-op ROB) pos (bv 0 inst-size-log)) 103 | 104 | (set-array! (ROB-rs1-imm ROB) pos (bv 0 param-reg-len)) 105 | (set-array! (ROB-rs1-brOffset ROB) pos (bv 0 param-memi-size-log)) 106 | (set-array! (ROB-rs1-stall ROB) pos #f) 107 | (set-array! (ROB-rs1-data ROB) pos (bv 0 param-reg-len)) 108 | (set-array! (ROB-rs1-ROBlink ROB) pos (bv 0 param-ROB-size-log)) 109 | (set-array! (ROB-rs2-stall ROB) pos #f) 110 | (set-array! (ROB-rs2-data ROB) pos (bv 0 param-reg-len)) 111 | (set-array! (ROB-rs2-ROBlink ROB) pos (bv 0 param-ROB-size-log)) 112 | 113 | (set-array! (ROB-wen ROB) pos #f) 114 | (set-array! (ROB-rd ROB) pos (bv 0 param-rf-size-log)) 115 | (set-array! (ROB-rd-data ROB) pos (bv 0 param-reg-len)) 116 | 117 | (set-array! (ROB-mem-valid ROB) pos #f) 118 | (set-array! (ROB-mem-rdwt ROB) pos #f) 119 | (set-array! (ROB-mem-addr ROB) pos (bv 0 param-memd-size-log)) 120 | (set-array! (ROB-mem-data ROB) pos (bv 0 param-reg-len)) 121 | 122 | (set-array! (ROB-isBr ROB) pos #f) 123 | (set-array! (ROB-brID ROB) pos (bv 0 param-brID-len)) 124 | (set-array! (ROB-taken ROB) pos #f) 125 | (set-array! (ROB-pred-taken ROB) pos #f) 126 | (set-array! (ROB-nextPC ROB) pos (bv 0 param-memi-size-log)) 127 | 128 | (set-array! (ROB-delayed-until-nonSpec ROB) pos #f) 129 | (set-array! (ROB-underSpec ROB) pos #f) 130 | (set-array! (ROB-specBr-ROBlink ROB) pos (bv 0 param-ROB-size-log)) 131 | ) 132 | 133 | 134 | (define (squashPartial-ROB! ROB misPredBr-ROBlink misPredBr-brID) 135 | 136 | (for ([i (in-range param-ROB-size)]) 137 | (define i-bv (integer->bitvector i (bitvector param-ROB-size-log))) 138 | 139 | (define idle (array-ref (ROB-idle ROB) i-bv)) 140 | (define brID (array-ref (ROB-brID ROB) i-bv)) 141 | 142 | (when (bvugt brID misPredBr-brID) 143 | (clear-ROB-entry! ROB i-bv))) 144 | 145 | (set-ROB-tail! ROB (bvadd1 misPredBr-ROBlink)) 146 | ) 147 | 148 | 149 | (define (resetsym-ROB! ROB) 150 | (resetsym-boolVec-array! (ROB-idle ROB)) 151 | (resetsym-boolVec-array! (ROB-finished ROB)) 152 | (resetsym-boolVec-array! (ROB-waiting ROB)) 153 | (resetsym-boolVec-array! (ROB-executing ROB)) 154 | 155 | (resetsym-bvVec-array! (ROB-pc ROB)) 156 | (resetsym-bvVec-array! (ROB-op ROB)) 157 | 158 | (resetsym-bvVec-array! (ROB-rs1-imm ROB)) 159 | (resetsym-bvVec-array! (ROB-rs1-brOffset ROB)) 160 | (resetsym-boolVec-array! (ROB-rs1-stall ROB)) 161 | (resetsym-bvVec-array! (ROB-rs1-data ROB)) 162 | (resetsym-bvVec-array! (ROB-rs1-ROBlink ROB)) 163 | (resetsym-boolVec-array! (ROB-rs2-stall ROB)) 164 | (resetsym-bvVec-array! (ROB-rs2-data ROB)) 165 | (resetsym-bvVec-array! (ROB-rs2-ROBlink ROB)) 166 | 167 | (resetsym-boolVec-array! (ROB-wen ROB)) 168 | (resetsym-bvVec-array! (ROB-rd ROB)) 169 | (resetsym-bvVec-array! (ROB-rd-data ROB)) 170 | 171 | (resetsym-boolVec-array! (ROB-mem-valid ROB)) 172 | (resetsym-boolVec-array! (ROB-mem-rdwt ROB)) 173 | (resetsym-bvVec-array! (ROB-mem-addr ROB)) 174 | (resetsym-bvVec-array! (ROB-mem-data ROB)) 175 | 176 | (resetsym-boolVec-array! (ROB-isBr ROB)) 177 | (resetsym-bvVec-array! (ROB-brID ROB)) 178 | (resetsym-boolVec-array! (ROB-taken ROB)) 179 | (resetsym-boolVec-array! (ROB-pred-taken ROB)) 180 | (resetsym-bvVec-array! (ROB-nextPC ROB)) 181 | 182 | (resetsym-boolVec-array! (ROB-delayed-until-nonSpec ROB)) 183 | (resetsym-boolVec-array! (ROB-underSpec ROB)) 184 | (resetsym-bvVec-array! (ROB-specBr-ROBlink ROB)) 185 | ) 186 | 187 | 188 | (define (ROB-full ROB) 189 | (not (array-ref (ROB-idle ROB) (ROB-tail ROB))) 190 | ) 191 | 192 | 193 | (define (ROB-empty ROB) 194 | (array-ref (ROB-idle ROB) (ROB-head ROB)) 195 | ) 196 | 197 | 198 | (define (ROB->string ROB) 199 | (~a "\n" 200 | " head: " (bitvector->natural (ROB-head ROB)) ", " 201 | "tail: " (bitvector->natural (ROB-tail ROB)) "\n" 202 | 203 | " idle: " (ROB-idle ROB) ", " 204 | "waiting: " (ROB-waiting ROB) "\n" 205 | 206 | " executing: " (ROB-executing ROB) ", " 207 | "finished: " (ROB-finished ROB) "\n" 208 | 209 | " pc: " (ROB-pc ROB) ", " 210 | "op: " (ROB-op ROB) ", " 211 | "brID: " (ROB-brID ROB) "\n" 212 | 213 | " underSpec: " (ROB-underSpec ROB) ", " 214 | "specBr-ROBlink: " (ROB-specBr-ROBlink ROB) "\n" 215 | ) 216 | ) 217 | 218 | -------------------------------------------------------------------------------- /src/CPU/alu.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "../lib/lib.rkt" 5 | "../abs-module/absArbiter.rkt" "../abs-module/absFifo.rkt" 6 | "../abs-module/absBufferGM.rkt" "../abs-module/absDelay.rkt" 7 | ) 8 | (provide 9 | init-alu-cfg alu-cfg-evaluate 10 | init-alu alu-dataoutValid dataout-alu! datain-alu! alu-datainReady squash-alu! 11 | squashPartial-alu! tick-alu! alu-cfg? alu? 12 | ) 13 | 14 | 15 | ; PART alu-cfg 16 | (struct alu-cfg (absArbiter-cfg absDelay-cfg) 17 | #:mutable #:transparent 18 | #:methods gen:custom-write 19 | [(define (write-proc this port mode) 20 | (write-string (alu-cfg->string this) port))] 21 | ) 22 | 23 | 24 | (define (init-alu-cfg param-timFct-len param-fanin param-simuCycle 25 | param-symType) 26 | (alu-cfg 27 | (init-absArbiter-cfg param-timFct-len param-fanin param-symType) 28 | (cond 29 | [param-enable-GhostMinion 30 | (init-absBufferGM-cfg param-timFct-len param-simuCycle param-symType)] 31 | [else 32 | (init-absFifo-cfg param-timFct-len param-simuCycle param-symType)])) 33 | ) 34 | 35 | 36 | (define (alu-cfg-evaluate alu-cfg-sym sol) 37 | (define absArbiter-cfg (alu-cfg-absArbiter-cfg alu-cfg-sym)) 38 | (define absDelay-cfg (alu-cfg-absDelay-cfg alu-cfg-sym)) 39 | 40 | (alu-cfg (absArbiter-cfg-evaluate absArbiter-cfg sol) 41 | (absDelay-cfg-evaluate absDelay-cfg sol)) 42 | ) 43 | 44 | 45 | (define (alu-cfg->string alu-cfg) 46 | "alu-cfg" 47 | ) 48 | 49 | 50 | ; PART alu 51 | (struct alu (absArbiter absDelay encoder decoder) 52 | #:mutable #:transparent 53 | #:methods gen:custom-write 54 | [(define (write-proc this port mode) 55 | (write-string (alu->string this) port))] 56 | ) 57 | 58 | 59 | (define (init-alu alu-cfg f param-operand-len param-reqId-len) 60 | (define absArbiter-cfg (alu-cfg-absArbiter-cfg alu-cfg)) 61 | (define absDelay-cfg (alu-cfg-absDelay-cfg alu-cfg)) 62 | 63 | (define param-entry-len (+ param-reqId-len param-operand-len)) 64 | (define absDelay (init-absDelay absDelay-cfg param-entry-len)) 65 | (define absArbiter (init-absArbiter absArbiter-cfg absDelay param-entry-len)) 66 | 67 | (define (encoder reqId operand-a operand-b) 68 | (concat reqId (f operand-a operand-b))) 69 | (define (decoder entry) 70 | (define reqId (extract (sub1 param-entry-len) param-operand-len entry)) 71 | (define result (extract (sub1 param-operand-len) 0 entry)) 72 | (list reqId result) 73 | ) 74 | 75 | (alu absArbiter absDelay encoder decoder) 76 | ) 77 | 78 | 79 | (define (alu-dataoutValid alu) 80 | (define absDelay (alu-absDelay alu)) 81 | 82 | (absDelay-dataoutValid absDelay) 83 | ) 84 | 85 | 86 | (define (dataout-alu! alu) 87 | (define absDelay (alu-absDelay alu)) 88 | (define decoder (alu-decoder alu)) 89 | 90 | (decoder (dataout-absDelay! absDelay)) 91 | ) 92 | 93 | 94 | (define (datain-alu! alu brID reqId operand-a operand-b fanId timFct) 95 | (define absArbiter (alu-absArbiter alu)) 96 | (define encoder (alu-encoder alu)) 97 | 98 | (datain-absArbiter! absArbiter (encoder reqId operand-a operand-b) 99 | brID fanId timFct) 100 | ) 101 | 102 | 103 | (define (alu-datainReady alu) 104 | (define absArbiter (alu-absArbiter alu)) 105 | 106 | (absArbiter-datainReady absArbiter) 107 | ) 108 | 109 | 110 | (define (squash-alu! alu) 111 | (define absArbiter (alu-absArbiter alu)) 112 | (define absDelay (alu-absDelay alu)) 113 | 114 | (squash-absArbiter! absArbiter) 115 | (1cycleSquash-absDelay! absDelay) 116 | ) 117 | 118 | 119 | (define (squashPartial-alu! alu misPredBr-brID) 120 | (define absArbiter (alu-absArbiter alu)) 121 | (define absDelay (alu-absDelay alu)) 122 | 123 | (squashPartial-absArbiter! absArbiter misPredBr-brID) 124 | (drainSquashPartial-absDelay! absDelay misPredBr-brID) 125 | ) 126 | 127 | 128 | (define (tick-alu! alu) 129 | (define absArbiter (alu-absArbiter alu)) 130 | (define absDelay (alu-absDelay alu)) 131 | 132 | (when (absArbiter-dataoutValid absArbiter) 133 | (when param-debug-assert (bug-assert 134 | (absDelay-datainReady absDelay) 135 | #:msg "tick-alu!: absDelay-datainReady is False")) 136 | (match-define (list entry brID timFct) (dataout-absArbiter! absArbiter)) 137 | (datain-absDelay! absDelay entry brID timFct)) 138 | 139 | (tick-absArbiter! absArbiter) 140 | (tick-absDelay! absDelay) 141 | ) 142 | 143 | 144 | (define (alu->string alu) 145 | (define absArbiter (alu-absArbiter alu)) 146 | (define absDelay (alu-absDelay alu)) 147 | 148 | (~a "\n" 149 | " absArbiter: " absArbiter "\n" 150 | " absDelay: " absDelay 151 | ) 152 | ) 153 | 154 | 155 | (define (testMe) 156 | 157 | 158 | (define alu-cfg (init-alu-cfg 2 8 10 "func_concrete")) 159 | (define alu (init-alu alu-cfg bvadd 4 3)) 160 | (printf (~a alu "\n")) 161 | 162 | (printf (~a (alu-dataoutValid alu) "\n")) 163 | ;(printf (~a (dataout-alu! alu) "\n")) 164 | (printf (~a (datain-alu! alu (bv 1 param-brID-len) (bv 2 3) (bv 3 4) (bv 5 4) 165 | (bv 0 3) (bv 2 2)) 166 | "\n")) 167 | (printf (~a (alu-datainReady alu) "\n")) 168 | (printf (~a alu "\n")) 169 | 170 | (tick-alu! alu) 171 | (printf (~a "-----------------\n")) 172 | 173 | (printf (~a (alu-dataoutValid alu) "\n")) 174 | (printf (~a (dataout-alu! alu) "\n")) 175 | (printf (~a (datain-alu! alu (bv 3 param-brID-len) (bv 1 3) (bv 1 4) (bv 1 4) 176 | (bv 1 3) (bv 1 2)) 177 | "\n")) 178 | (printf (~a (alu-datainReady alu) "\n")) 179 | (printf (~a alu "\n")) 180 | ) 181 | ;(testMe) 182 | 183 | -------------------------------------------------------------------------------- /src/CPU/cache.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "../lib/lib.rkt" "../sym-state/mem.rkt" 5 | "../abs-module/absArbiter.rkt" "../abs-module/absFifo.rkt" 6 | "../abs-module/absBufferGM.rkt" "../abs-module/absDelay.rkt" 7 | ) 8 | (require "../sym-state/memd.rkt") ; for debug 9 | 10 | (provide 11 | init-cache-cfg cache-cfg-evaluate 12 | init-cache cache-dataoutValid dataout-cache! checkHitReq-cache! 13 | checkDelayedReq-cache! datain-cache! cache-datainReady squash-cache! 14 | squashPartial-cache! cache-obsv tick-cache! cache-cfg? cache? 15 | ) 16 | 17 | 18 | ; PART cache-cfg 19 | (struct cache-cfg (absArbiter-cfg isHit invisi-isHit absDelay-cfg 20 | param-timFct-len param-simuCycle) 21 | #:mutable #:transparent 22 | #:methods gen:custom-write 23 | [(define (write-proc this port mode) 24 | (write-string (cache-cfg->string this) port))] 25 | ) 26 | 27 | 28 | (define (init-cache-cfg param-timFct-len param-fanin param-simuCycle 29 | param-symType) 30 | (cache-cfg 31 | (init-absArbiter-cfg param-timFct-len param-fanin param-symType) 32 | 33 | ; TODO: move these two uninterpreted function to abs-module folder 34 | (cond 35 | [(equal? param-symType "func_concrete") 36 | (lambda (ignore) (bv 1 1))] 37 | [(equal? param-symType "func_sym") 38 | (build-unfuncbv (* param-simuCycle (add1 param-timFct-len)) 1)]) 39 | (cond 40 | [(equal? param-symType "func_concrete") 41 | (lambda (ignore) (bv 1 1))] 42 | [(equal? param-symType "func_sym") 43 | (build-unfuncbv (* 2 param-simuCycle (add1 param-timFct-len)) 1)]) 44 | (cond 45 | [param-enable-GhostMinion 46 | (init-absBufferGM-cfg param-timFct-len param-simuCycle param-symType)] 47 | [else 48 | (init-absFifo-cfg param-timFct-len param-simuCycle param-symType)]) 49 | param-timFct-len 50 | param-simuCycle) 51 | ) 52 | 53 | 54 | (define (cache-cfg-evaluate cache-cfg-sym sol) 55 | (define absArbiter-cfg (cache-cfg-absArbiter-cfg cache-cfg-sym)) 56 | (define isHit (cache-cfg-isHit cache-cfg-sym)) 57 | (define invisi-isHit (cache-cfg-invisi-isHit cache-cfg-sym)) 58 | (define absDelay-cfg (cache-cfg-absDelay-cfg cache-cfg-sym)) 59 | (define param-timFct-len (cache-cfg-param-timFct-len cache-cfg-sym)) 60 | (define param-simuCycle (cache-cfg-param-simuCycle cache-cfg-sym)) 61 | 62 | (cache-cfg 63 | (absArbiter-cfg-evaluate absArbiter-cfg sol) 64 | (evaluate isHit sol) 65 | (evaluate invisi-isHit sol) 66 | (absDelay-cfg-evaluate absDelay-cfg sol) 67 | param-timFct-len 68 | param-simuCycle 69 | ) 70 | ) 71 | 72 | 73 | (define (cache-cfg->string cache-cfg) 74 | "cache-cfg" 75 | ) 76 | 77 | 78 | ; PART cache 79 | (struct cache (absArbiter history-timFct history-valid history-return isHit 80 | invisi-timFct invisi-brID invisi-valid invisi-return invisi-isHit 81 | hitValid hitEntry delayValid delayReqId absDelay mem encoder1 82 | decoder1 encoder2 decoder2 clk) 83 | #:mutable #:transparent 84 | #:methods gen:custom-write 85 | [(define (write-proc this port mode) 86 | (write-string (cache->string this) port))] 87 | ) 88 | 89 | 90 | ; TODO: param-addr-len can be removed from the arguments 91 | (define (init-cache cache-cfg mem param-addr-len param-data-len param-reqId-len) 92 | (define absArbiter-cfg (cache-cfg-absArbiter-cfg cache-cfg)) 93 | (define isHit (cache-cfg-isHit cache-cfg)) 94 | (define invisi-isHit (cache-cfg-invisi-isHit cache-cfg)) 95 | (define absDelay-cfg (cache-cfg-absDelay-cfg cache-cfg)) 96 | (define param-timFct-len (cache-cfg-param-timFct-len cache-cfg)) 97 | (define param-simuCycle (cache-cfg-param-simuCycle cache-cfg)) 98 | (define param-simuCycle-log 99 | (inexact->exact (ceiling (log param-simuCycle 2)))) 100 | 101 | (define param-entry1-len (+ 1 param-reqId-len param-data-len)) 102 | (define param-entry2-len (+ 1 param-reqId-len param-data-len)) 103 | (define absDelay (init-absDelay absDelay-cfg param-entry2-len)) 104 | (define absArbiter (init-absArbiter absArbiter-cfg absDelay param-entry1-len)) 105 | 106 | (define (encoder1 underSpec reqId addr data rdwt mem) 107 | (when param-debug-assert (bug-assert 108 | rdwt 109 | #:msg "cache does not support write for now")) 110 | (concat (bool->bitvector underSpec) reqId (mem-ref mem addr)) 111 | ) 112 | (define (decoder1 entry) 113 | (define underSpec (extract (- param-entry1-len 1) (- param-entry1-len 1) 114 | entry)) 115 | (define reqId (extract (- param-entry1-len 2) param-data-len entry)) 116 | (define data (extract (- param-data-len 1) 0 entry)) 117 | (list (bitvector->bool underSpec) reqId data) 118 | ) 119 | 120 | (define (encoder2 underSpec reqId data) 121 | (concat (bool->bitvector underSpec) reqId data) 122 | ) 123 | (define (decoder2 entry) 124 | (define underSpec (extract (- param-entry2-len 1) (- param-entry2-len 1) 125 | entry)) 126 | (define reqId (extract (- param-entry2-len 2) param-data-len entry)) 127 | (define data (extract (- param-data-len 1) 0 entry)) 128 | (list (bitvector->bool underSpec) reqId data) 129 | ) 130 | 131 | (cache 132 | absArbiter 133 | 134 | (initZeroVec-array param-simuCycle param-timFct-len) 135 | (initZeroVec-array param-simuCycle 1) 136 | (initZeroVec-array param-simuCycle 1) 137 | isHit 138 | (initZeroVec-array param-simuCycle param-timFct-len) 139 | (initZeroVec-array param-simuCycle param-brID-len) 140 | (initZeroVec-array param-simuCycle 1) 141 | (initZeroVec-array param-simuCycle 1) 142 | invisi-isHit 143 | #f 144 | (bv 0 param-entry2-len) 145 | 146 | #f 147 | (bv 0 param-reqId-len) 148 | 149 | absDelay 150 | 151 | mem 152 | encoder1 decoder1 encoder2 decoder2 153 | (bv 0 param-simuCycle-log)) 154 | ) 155 | 156 | 157 | (define (cache-dataoutValid cache) 158 | (define delayValid (cache-delayValid cache)) 159 | (define hitValid (cache-hitValid cache)) 160 | (define absDelay (cache-absDelay cache)) 161 | 162 | (absDelay-dataoutValid absDelay) 163 | ) 164 | 165 | 166 | (define (dataout-cache! cache) 167 | (define history-return (cache-history-return cache)) 168 | (define invisi-return (cache-invisi-return cache)) 169 | (define absDelay (cache-absDelay cache)) 170 | (define decoder2 (cache-decoder2 cache)) 171 | (define clk (cache-clk cache)) 172 | 173 | (match-define (list underSpec reqId data) 174 | (decoder2 (dataout-absDelay! absDelay))) 175 | 176 | ; TODO: not only put return into observation, 177 | ; but also put into input to hit uninterFunc 178 | (when (and param-cache-useHit (not param-enable-invisiSpec)) 179 | (set-array! history-return clk (bv 1 1))) 180 | (when (and param-cache-useHit param-enable-invisiSpec) 181 | (if underSpec 182 | (set-array! invisi-return clk (bv 1 1)) 183 | (set-array! history-return clk (bv 1 1)))) 184 | 185 | (list reqId data) 186 | ) 187 | 188 | 189 | ; NOTE: we assume the hit return and delay return 190 | ; do not contend with miss return 191 | (define (checkHitReq-cache! cache) 192 | (define hitValid (cache-hitValid cache)) 193 | (define hitEntry (cache-hitEntry cache)) 194 | (define decoder2 (cache-decoder2 cache)) 195 | 196 | (set-cache-hitValid! cache #f) 197 | (match-define (list underSpec reqId data) (decoder2 hitEntry)) 198 | (list (and param-cache-useHit hitValid) reqId data) 199 | ) 200 | 201 | 202 | (define (checkDelayedReq-cache! cache) 203 | (define delayValid (cache-delayValid cache)) 204 | (define delayReqId (cache-delayReqId cache)) 205 | 206 | (set-cache-delayValid! cache #f) 207 | (list delayValid delayReqId) 208 | ) 209 | 210 | 211 | (define (datain-cache! cache underSpec brID reqId addr data rdwt fanId timFct) 212 | (define absArbiter (cache-absArbiter cache)) 213 | (define mem (cache-mem cache)) 214 | (define encoder1 (cache-encoder1 cache)) 215 | 216 | (when param-cache-useHit 217 | (when param-debug-assert (bug-assert 218 | (not (cache-hitValid cache)) 219 | #:msg "datain-cache!: cache hit should be returned no matter what"))) 220 | 221 | (datain-absArbiter! absArbiter (encoder1 underSpec reqId addr data rdwt mem) 222 | brID fanId timFct) 223 | ) 224 | 225 | 226 | (define (cache-datainReady cache) 227 | (define absArbiter (cache-absArbiter cache)) 228 | 229 | (absArbiter-datainReady absArbiter) 230 | ) 231 | 232 | 233 | ; TODO: merge invisi-timFct to history-timFct 234 | 235 | 236 | (define (squash-cache! cache) 237 | (define absArbiter (cache-absArbiter cache)) 238 | (define absDelay (cache-absDelay cache)) 239 | 240 | (squash-absArbiter! absArbiter) 241 | (drainSquash-absDelay! absDelay) 242 | ) 243 | 244 | 245 | (define (squashPartial-cache! cache misPredBr-brID) 246 | (define absArbiter (cache-absArbiter cache)) 247 | (define absDelay (cache-absDelay cache)) 248 | 249 | (squashPartial-absArbiter! absArbiter misPredBr-brID) 250 | (drainSquashPartial-absDelay! absDelay misPredBr-brID) 251 | ) 252 | 253 | 254 | (define (cache-obsv cache) 255 | (cond 256 | [(equal? param-obsvType "memTrace") 257 | (define absDelay (cache-absDelay cache)) 258 | (absDelay-obsv absDelay)] 259 | 260 | [(equal? param-obsvType "cacheState") 261 | (define history-timFct (cache-history-timFct cache)) 262 | (define history-valid (cache-history-valid cache)) 263 | (define history-return (cache-history-return cache)) 264 | (concat (array->bv history-timFct) (array->bv history-valid) 265 | (array->bv history-return))] 266 | 267 | [(equal? param-obsvType "commitPC") 268 | (when param-debug-assert 269 | (bug-assert #f #:msg "cache-obsv: param-obsvType"))] 270 | ) 271 | ) 272 | 273 | 274 | (define (cache->string cache) 275 | (define history-timFct (cache-history-timFct cache)) 276 | (define history-valid (cache-history-valid cache)) 277 | (define invisi-timFct (cache-invisi-timFct cache)) 278 | (define invisi-valid (cache-invisi-valid cache)) 279 | (define absArbiter (cache-absArbiter cache)) 280 | (define absDelay (cache-absDelay cache)) 281 | 282 | ; (~a absArbiter "\n" absDelay) 283 | (~a "\n" 284 | " history: " history-valid history-timFct 285 | ", invisi: " invisi-valid invisi-timFct "\n" 286 | " absArbiter: " absArbiter "\n" 287 | " absDelay: " absDelay 288 | ) 289 | ) 290 | 291 | 292 | (define (tick-cache! cache) 293 | (define absArbiter (cache-absArbiter cache)) 294 | (define history-timFct (cache-history-timFct cache)) 295 | (define history-valid (cache-history-valid cache)) 296 | (define isHit (cache-isHit cache)) 297 | (define invisi-timFct (cache-invisi-timFct cache)) 298 | (define invisi-brID (cache-invisi-brID cache)) 299 | (define invisi-valid (cache-invisi-valid cache)) 300 | (define invisi-isHit (cache-invisi-isHit cache)) 301 | (define absDelay (cache-absDelay cache)) 302 | (define mem (cache-mem cache)) 303 | (define decoder1 (cache-decoder1 cache)) 304 | (define encoder2 (cache-encoder2 cache)) 305 | (define clk (cache-clk cache)) 306 | 307 | (when (and param-debug-assert param-enable-DoM) (bug-assert 308 | (not (cache-delayValid cache)) 309 | #:msg "tick-cache!: cache delay should be returned no matter what")) 310 | (when (and param-debug-assert param-cache-useHit) (bug-assert 311 | (not (cache-hitValid cache)) 312 | #:msg "tick-cache!: cache hit should be returned no matter what")) 313 | 314 | (when (absArbiter-dataoutValid absArbiter) 315 | (when param-debug-assert (bug-assert 316 | (absDelay-datainReady absDelay) 317 | #:msg "tick-cache!: absDelay-datainReady is False")) 318 | 319 | ; PART: get one request from the arbiter 320 | (match-define (list entry1 brID timFct) (dataout-absArbiter! absArbiter)) 321 | (match-define (list underSpec reqId data) (decoder1 entry1)) 322 | (define entry2 (encoder2 underSpec reqId data)) 323 | 324 | (cond 325 | [(and param-cache-useHit (not param-enable-invisiSpec)) 326 | ; PART: update the cache hit history 327 | (set-array! history-timFct clk timFct) 328 | (set-array! history-valid clk (bv 1 1)) 329 | (define hit (bitvector->bool (isHit 330 | (concat (array->bv history-timFct) (array->bv history-valid))))) 331 | 332 | ; PART: DoM 333 | ; TODO: maybe remove the set-then-unset can improve the performance 334 | (when (and param-enable-DoM underSpec) 335 | (resetToZero-array! history-timFct clk) 336 | (resetToZero-array! history-valid clk)) 337 | 338 | ; PART: cache hit 339 | (when hit 340 | (set-cache-hitValid! cache #t) 341 | (set-cache-hitEntry! cache entry2)) 342 | 343 | ; PART: cache miss 344 | (when (not hit) 345 | ; PART: DoM 346 | (when (and param-enable-DoM underSpec) 347 | (set-cache-delayValid! cache #t) 348 | (set-cache-delayReqId! cache reqId)) 349 | (when (not (and param-enable-DoM underSpec)) 350 | (datain-absDelay! absDelay entry2 brID timFct))) 351 | ] 352 | 353 | [(and param-cache-useHit param-enable-invisiSpec) 354 | ; PART: update the cache hit history 355 | (define hit #t) 356 | (if underSpec 357 | (begin 358 | (set-array! invisi-timFct clk timFct) 359 | (when param-enable-GhostMinion (set-array! invisi-brID clk brID)) 360 | (set-array! invisi-valid clk (bv 1 1)) 361 | 362 | (define (maskThisEntry i-bv) 363 | (define i-brID (array-ref invisi-brID i-bv)) 364 | (bvugt i-brID brID)) 365 | (define invisi-timFct-masked (if param-enable-GhostMinion 366 | (array->masked invisi-timFct maskThisEntry) 367 | invisi-timFct)) 368 | (define invisi-valid-masked (if param-enable-GhostMinion 369 | (array->masked invisi-valid maskThisEntry) 370 | invisi-valid)) 371 | (set! hit (bitvector->bool (invisi-isHit 372 | (concat (array->bv history-timFct) (array->bv history-valid) 373 | (array->bv invisi-timFct-masked) 374 | (array->bv invisi-valid-masked)))))) 375 | (begin 376 | (set-array! history-timFct clk timFct) 377 | (set-array! history-valid clk (bv 1 1)) 378 | (set! hit (bitvector->bool (isHit 379 | (concat (array->bv history-timFct) (array->bv history-valid))))))) 380 | 381 | ; PART: cache hit 382 | (when hit 383 | (set-cache-hitValid! cache #t) 384 | (set-cache-hitEntry! cache entry2)) 385 | 386 | ; PART: cache miss 387 | (when (not hit) 388 | (datain-absDelay! absDelay entry2 brID timFct)) 389 | ] 390 | 391 | [else 392 | (datain-absDelay! absDelay entry2 brID timFct) 393 | ] 394 | ) 395 | ) 396 | 397 | (tick-absArbiter! absArbiter) 398 | (tick-absDelay! absDelay) 399 | (tick-mem! mem) 400 | (set-cache-clk! cache (bvadd1 clk)) 401 | ) 402 | 403 | 404 | (define (testMe) 405 | 406 | (match-define (list memd-cfg-1 memd-cfg-2) 407 | (init-memd-cfg-pair param-memd-size param-reg-len 408 | "vec_concrete")) 409 | (define memd (init-memd memd-cfg-2 10)) 410 | (define cache-cfg (init-cache-cfg 2 8 10 "func_concrete")) 411 | (define cache (init-cache cache-cfg memd 2 4 3)) 412 | (printf (~a cache "\n")) 413 | 414 | (printf (~a (cache-dataoutValid cache) "\n")) 415 | ;(printf (~a (dataout-cache! cache) "\n")) 416 | (printf (~a (datain-cache! cache #f (bv 1 param-brID-len) (bv 2 3) (bv 0 2) 417 | (bv 15 4) #t (bv 0 3) (bv 2 2)) 418 | "\n")) 419 | (printf (~a (cache-datainReady cache) "\n")) 420 | (printf (~a cache "\n")) 421 | 422 | (tick-cache! cache) 423 | (printf (~a "-----------------\n")) 424 | 425 | (printf (~a (cache-dataoutValid cache) "\n")) 426 | (printf (~a (dataout-cache! cache) "\n")) 427 | (printf (~a (datain-cache! cache #f (bv 3 param-brID-len) (bv 2 3) (bv 3 2) 428 | (bv 15 4) #t (bv 1 3) (bv 2 2)) 429 | "\n")) 430 | (printf (~a (cache-datainReady cache) "\n")) 431 | (printf (~a cache "\n")) 432 | ) 433 | ;(testMe) 434 | 435 | -------------------------------------------------------------------------------- /src/CPU/decode.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "renameTB.rkt" "ROB.rkt" 5 | "../sym-state/rf.rkt" "../inst.rkt" "../lib/lib.rkt") 6 | (provide rename decode) 7 | 8 | 9 | ; Given a regindex, this function return 10 | ; - whether the youngest producer of this register has computed the result 11 | ; - the result 12 | (define (rename rs renameTB ROB rf) 13 | 14 | (define rs-ROBlink (array-ref (renameTB-ROBlink renameTB) rs)) 15 | (define rs-in-ROB (array-ref (renameTB-valid renameTB) rs)) 16 | (define finish (array-ref (ROB-finished ROB) rs-ROBlink)) 17 | 18 | (define stall #f) (define data (rf-ref rf rs)) 19 | (when rs-in-ROB 20 | (if (array-ref (ROB-finished ROB) rs-ROBlink) 21 | (set! data (array-ref (ROB-rd-data ROB) rs-ROBlink)) 22 | (set! stall #t) 23 | ) 24 | ) 25 | 26 | (list stall data) 27 | ) 28 | 29 | 30 | (define (decode inst renameTB ROB rf) 31 | (define op (inst-op inst)) 32 | (define rs1 (inst-rs1 inst)) 33 | (define rs1-rfIndex (extract (sub1 param-rf-size-log) 0 rs1)) 34 | (define rs2 (inst-rs2 inst)) 35 | (define rd (inst-rd inst)) 36 | 37 | (define rs1-imm rs1) 38 | (define rs1-brOffset (extract (sub1 param-memi-size-log) 0 rs1)) 39 | (define rs1-ROBlink (array-ref (renameTB-ROBlink renameTB) rs1-rfIndex)) 40 | (define rs2-ROBlink (array-ref (renameTB-ROBlink renameTB) rs2)) 41 | 42 | (define rs1-stall #f) 43 | (define rs1-data rs1) 44 | (define rs2-stall #f) 45 | (define rs2-data (bv 0 param-reg-len)) 46 | (define wen #f) 47 | (define mem-valid #f) 48 | (define mem-rdwt #f) 49 | (define isBr #f) 50 | 51 | (cond 52 | 53 | [(bveq inst-op-Li op) 54 | ;(set! rs1-stall #f) 55 | ;(set! rs1-data rs1) 56 | ;(set! rs2-stall #f) 57 | 58 | (set! wen #t) 59 | ;(set! mem-valid #f) 60 | ;(set! isBr #f) 61 | ] 62 | 63 | [(or (bveq inst-op-Add op) (bveq inst-op-Mul op)) 64 | (match-define (list stall_1 data_1) (rename rs1-rfIndex renameTB ROB rf)) 65 | (set! rs1-stall stall_1) 66 | (set! rs1-data data_1) 67 | 68 | (match-define (list stall_2 data_2) (rename rs2 renameTB ROB rf)) 69 | (set! rs2-stall stall_2) 70 | (set! rs2-data data_2) 71 | 72 | (set! wen #t) 73 | ;(set! mem-valid #f) 74 | ;(set! isBr #f) 75 | ] 76 | 77 | [(bveq inst-op-Ld op) 78 | (match-define (list stall_1 data_1) (rename rs1-rfIndex renameTB ROB rf)) 79 | (set! rs1-stall stall_1) 80 | (set! rs1-data data_1) 81 | ;(set! rs2-stall #f) 82 | 83 | (set! wen #t) 84 | (set! mem-valid #t) 85 | (set! mem-rdwt #t) 86 | ;(set! isBr #f) 87 | ] 88 | 89 | [(bveq inst-op-St op) 90 | (match-define (list stall_1 data_1) (rename rs1-rfIndex renameTB ROB rf)) 91 | (set! rs1-stall stall_1) 92 | (set! rs1-data data_1) 93 | 94 | (match-define (list stall_2 data_2) (rename rs2 renameTB ROB rf)) 95 | (set! rs2-stall stall_2) 96 | (set! rs2-data data_2) 97 | 98 | ;(set! wen #f) 99 | (set! mem-valid #t) 100 | ;(set! mem-rdwt #f) 101 | ;(set! isBr #f) 102 | ] 103 | 104 | [(bveq inst-op-Br op) 105 | ;(set! rs1-stall #f) 106 | (match-define (list stall_2 data_2) (rename rs2 renameTB ROB rf)) 107 | (set! rs2-stall stall_2) 108 | (set! rs2-data data_2) 109 | 110 | ;(set! wen #f) 111 | ;(set! mem-valid #f) 112 | (set! isBr #t) 113 | ] 114 | ) 115 | 116 | 117 | (list rs1-imm rs1-brOffset rs1-stall rs1-data rs1-ROBlink 118 | rs2-stall rs2-data rs2-ROBlink 119 | wen rd 120 | mem-valid mem-rdwt 121 | isBr) 122 | ) 123 | 124 | -------------------------------------------------------------------------------- /src/CPU/inFetchScoreBoard.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "../lib/lib.rkt") 4 | (provide (struct-out inFetchScoreBoard) init-inFetchScoreBoard) 5 | 6 | 7 | (struct inFetchScoreBoard (numProducer) #:mutable #:transparent) 8 | 9 | 10 | (define (init-inFetchScoreBoard param-simuCycle param-arch-size) 11 | (define param-simuCycle2 (* 2 param-simuCycle)) 12 | (define param-simuCycle2-log 13 | (inexact->exact (ceiling (log param-simuCycle2 2)))) 14 | 15 | (inFetchScoreBoard 16 | (initZeroVec-array param-arch-size param-simuCycle2-log) 17 | ) 18 | ) 19 | -------------------------------------------------------------------------------- /src/CPU/issue.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "ROB.rkt" "alu.rkt" "cache.rkt" "../sym-state/memd.rkt" "../inst.rkt" 5 | "../lib/lib.rkt" 6 | ) 7 | (provide issue!) 8 | 9 | 10 | (define (issue! memd adder muler Dcache ROB param-debug-print-on) 11 | ; TODO: check memory st->ld forward before issuing with stld alias table 12 | 13 | ; STEP: we remember a forwardlist to deal with after issuing everything 14 | ; to avoid the forward data being used in the same cycle 15 | (define forwardlist (list)) 16 | 17 | (define squash-E #f) 18 | (define misPredBr-ROBlink-E (bv 0 param-ROB-size-log)) 19 | (define misPredBr-brID-E (bv -1 param-brID-len)) 20 | (define nextPC-E (bv 0 param-memi-size-log)) 21 | 22 | (for ([i (in-range param-ROB-size)]) 23 | (define i-bv (integer->bitvector i (bitvector param-ROB-size-log))) 24 | 25 | (define waiting (array-ref (ROB-waiting ROB) i-bv)) 26 | (define waiting-array (ROB-waiting ROB)) 27 | (define executing-array (ROB-executing ROB)) 28 | (define finished-array (ROB-finished ROB)) 29 | 30 | (define pc (array-ref (ROB-pc ROB) i-bv)) 31 | (define op (array-ref (ROB-op ROB) i-bv)) 32 | 33 | (define rs1-imm (array-ref (ROB-rs1-imm ROB) i-bv)) 34 | (define rs1-brOffset (array-ref (ROB-rs1-brOffset ROB) i-bv)) 35 | (define rs1-stall (array-ref (ROB-rs1-stall ROB) i-bv)) 36 | (define rs1-data (array-ref (ROB-rs1-data ROB) i-bv)) 37 | (define rs2-stall (array-ref (ROB-rs2-stall ROB) i-bv)) 38 | (define rs2-data (array-ref (ROB-rs2-data ROB) i-bv)) 39 | 40 | (define rd (array-ref (ROB-rd ROB) i-bv)) 41 | (define rd-data-array (ROB-rd-data ROB)) 42 | 43 | (define mem-rdwt (array-ref (ROB-mem-rdwt ROB) i-bv)) 44 | (define mem-addr-array (ROB-mem-addr ROB)) 45 | (define mem-data-array (ROB-mem-data ROB)) 46 | 47 | (define brID (array-ref (ROB-brID ROB) i-bv)) 48 | (define taken-array (ROB-taken ROB)) 49 | (define pred-taken-array (ROB-pred-taken ROB)) 50 | (define pred-taken (array-ref (ROB-pred-taken ROB) i-bv)) 51 | (define nextPC-array (ROB-nextPC ROB)) 52 | 53 | (define delayed-until-nonSpec 54 | (array-ref (ROB-delayed-until-nonSpec ROB) i-bv)) 55 | (define underSpec (array-ref (ROB-underSpec ROB) i-bv)) 56 | 57 | 58 | ; STEP: the condition to issue 59 | (when (and waiting (not rs1-stall) (not rs2-stall)) 60 | 61 | ; STEP: execute the instruction 62 | (cond 63 | [(bveq inst-op-Li op) 64 | (set-array! rd-data-array i-bv rs1-imm) 65 | (set-array! waiting-array i-bv #f) 66 | (set-array! finished-array i-bv #t) 67 | (set-array! nextPC-array i-bv (bvadd1 pc)) 68 | (set! forwardlist (append forwardlist (list (list i-bv rs1-imm))))] 69 | 70 | [(bveq inst-op-Add op) 71 | (datain-alu! adder brID i-bv rs1-data rs2-data i-bv (bv 0 1)) 72 | (set-array! nextPC-array i-bv (bvadd1 pc)) 73 | ] 74 | 75 | [(bveq inst-op-Mul op) 76 | (datain-alu! muler brID i-bv rs1-data rs2-data i-bv (bv 0 1)) 77 | (set-array! nextPC-array i-bv (bvadd1 pc)) 78 | ] 79 | 80 | [(and (bveq inst-op-Ld op) (not (and delayed-until-nonSpec underSpec))) 81 | (define mem-addr (extract (sub1 param-memd-size-log) 0 rs1-data)) 82 | (define mem-data rs2-data) 83 | (set-array! mem-addr-array i-bv mem-addr) 84 | (datain-cache! Dcache underSpec brID i-bv mem-addr mem-data mem-rdwt 85 | i-bv mem-addr) 86 | (set-array! nextPC-array i-bv (bvadd1 pc)) 87 | ] 88 | 89 | [(bveq inst-op-St op) 90 | (define mem-addr (extract (sub1 param-memd-size-log) 0 rs1-data)) 91 | (define mem-data rs2-data) 92 | (set-array! mem-addr-array i-bv mem-addr) 93 | (set-array! mem-data-array i-bv mem-data) 94 | (set-array! waiting-array i-bv #f) 95 | (set-array! finished-array i-bv #t) 96 | (set-array! nextPC-array i-bv (bvadd1 pc))] 97 | 98 | [(bveq inst-op-Br op) 99 | (define taken (bvzero? rs2-data)) 100 | (define nextPC (if (bvzero? rs2-data) (bvadd rs1-brOffset pc) (bvadd1 pc))) 101 | (set-array! taken-array i-bv taken) 102 | (set-array! nextPC-array i-bv nextPC) 103 | 104 | (when param-enable-execute-squash 105 | (when (not (equal? pred-taken taken)) 106 | (set! squash-E #t) 107 | (when (bvult brID misPredBr-brID-E) 108 | (set! misPredBr-ROBlink-E i-bv) 109 | (set! misPredBr-brID-E brID) 110 | (set! nextPC-E nextPC)) 111 | (set-array! pred-taken-array i-bv taken))) 112 | 113 | (set-array! waiting-array i-bv #f) 114 | (set-array! finished-array i-bv #t)]))) 115 | 116 | 117 | ; STEP: check the datainReady from alu and cache 118 | (define (check-datainReady! port port-datainReady) 119 | ; STEP-1: get datainReady packet 120 | (match-define (list datainReady ROBlink) (port-datainReady port)) 121 | ; (when param-debug-print-on (printf (~a 122 | ; "datainReady: " datainReady " " "ROBlink: " ROBlink "\n" 123 | ; ))) 124 | (when datainReady 125 | (when param-debug-assert (bug-assert 126 | (array-ref (ROB-waiting ROB) ROBlink) 127 | #:msg "adder/muler/Dcache ready to an un-waiting ROB entry")) 128 | 129 | ; STEP-2: fill in the ROB entry 130 | (set-array! (ROB-waiting ROB) ROBlink #f) 131 | (set-array! (ROB-executing ROB) ROBlink #t))) 132 | 133 | (check-datainReady! adder alu-datainReady) 134 | (check-datainReady! muler alu-datainReady) 135 | (check-datainReady! Dcache cache-datainReady) 136 | 137 | 138 | ; STEP: Forward the data from finished ROB 139 | (for-each 140 | (lambda (entry) (forward-ROB! ROB (first entry) (second entry))) 141 | forwardlist) 142 | 143 | (list squash-E misPredBr-ROBlink-E misPredBr-brID-E nextPC-E) 144 | ) 145 | 146 | -------------------------------------------------------------------------------- /src/CPU/renameTB.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "../lib/lib.rkt") 4 | (provide (struct-out renameTB) init-renameTB init-renameTB-copies) 5 | 6 | 7 | (struct renameTB (valid ROBlink) #:mutable #:transparent) 8 | 9 | 10 | (define (init-renameTB param-physical-size param-arch-size) 11 | (define param-physical-size-log (inexact->exact (log param-physical-size 2))) 12 | 13 | (renameTB 14 | (initFalseVec-array param-arch-size) 15 | (initZeroVec-array param-arch-size param-physical-size-log) 16 | ) 17 | ) 18 | 19 | 20 | (define (init-renameTB-copies param-physical-size param-arch-size 21 | param-size) 22 | (build-vector 23 | param-size 24 | (lambda (ignore) (init-renameTB param-physical-size param-arch-size))) 25 | ) 26 | 27 | -------------------------------------------------------------------------------- /src/ISASimulator.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "lib/lib.rkt" "sym-state/rf.rkt" "sym-state/memi.rkt" "sym-state/memd.rkt" 5 | "inst.rkt" "decode.rkt" 6 | ) 7 | (provide 8 | (struct-out ISASimulator-cfg) init-ISASimulator-cfg-pair 9 | ISASimulator-cfg-evaluate ISASimulator-cfg-pair->string 10 | init-ISASimulator simu-ISASimulator! 11 | ISASimulator-memTrace assume-ISASimulator-memTrace 12 | ISASimulator-debug-commitLog 13 | ) 14 | 15 | 16 | ; PART ISASimulator-cfg 17 | (struct ISASimulator-cfg (rf-cfg memi-cfg memd-cfg) 18 | #:mutable #:transparent 19 | #:methods gen:custom-write 20 | [(define (write-proc this port mode) 21 | (write-string (ISASimulator-cfg->string this) port))] 22 | ) 23 | 24 | 25 | (define (init-ISASimulator-cfg-pair) 26 | (define rf-cfg (init-rf-cfg param-rf-size param-reg-len param-rf-symType)) 27 | (define memi-cfg (init-memi-cfg 28 | param-memi-size param-reg-len param-rf-size-log param-rf-size-log 29 | param-memi-symType)) 30 | (match-define (list memd-cfg-0 memd-cfg-1) (init-memd-cfg-pair 31 | param-memd-size param-reg-len param-memd-symType)) 32 | 33 | (list (ISASimulator-cfg rf-cfg memi-cfg memd-cfg-0) 34 | (ISASimulator-cfg rf-cfg memi-cfg memd-cfg-1)) 35 | ) 36 | 37 | 38 | ; EXPLAIN: 39 | ; In general “evaluate a data structure (e.g., ISASimulator-cfg-0) using a 40 | ; solution (e.g., sol)” is a terminology in Rosette meaning “read the solution 41 | ; returned by the SMT solver, which is a special encoding of the counterexample. 42 | ; Then, learn what is the concrete value stored in that data structure in the 43 | ; counterexample”. 44 | ; Recall that the counterexample from SMT solver is basically a mapping from 45 | ; each symbolic value to a concrete value. 46 | ; The goal of having the returned concert value is to launch another simulation 47 | ; so that we know how the counterexample (i.e., the attack) looks like. 48 | ; In Rosette, it has a default function to evaluate a single symbolic term. 49 | ; But how to do the same thing for an arbitrary data structure? 50 | ; This will relying on following functions that I defined by myself for each 51 | ; data structure, such as `ISASimulator-cfg-evaluate` evaluates 52 | ; `ISASimulator-cfg` data structure. 53 | (define (ISASimulator-cfg-evaluate ISASimulator-cfg-sym sol) 54 | (define rf-cfg (ISASimulator-cfg-rf-cfg ISASimulator-cfg-sym)) 55 | (define memi-cfg (ISASimulator-cfg-memi-cfg ISASimulator-cfg-sym)) 56 | (define memd-cfg (ISASimulator-cfg-memd-cfg ISASimulator-cfg-sym)) 57 | 58 | (ISASimulator-cfg (rf-cfg-evaluate rf-cfg sol) 59 | (memi-cfg-evaluate memi-cfg sol) 60 | (memd-cfg-evaluate memd-cfg sol)) 61 | ) 62 | 63 | 64 | (define (ISASimulator-cfg->string ISASimulator-cfg) 65 | (define rf-cfg (ISASimulator-cfg-rf-cfg ISASimulator-cfg)) 66 | (define memi-cfg (ISASimulator-cfg-memi-cfg ISASimulator-cfg)) 67 | (define memd-cfg (ISASimulator-cfg-memd-cfg ISASimulator-cfg)) 68 | 69 | (~a "memi: \n" memi-cfg "\n" 70 | "rf: " rf-cfg "\n" 71 | "memd: " memd-cfg "\n") 72 | ) 73 | 74 | 75 | (define (ISASimulator-cfg-pair->string ISASimulator-cfg-0 ISASimulator-cfg-1) 76 | (define rf-cfg (ISASimulator-cfg-rf-cfg ISASimulator-cfg-0)) 77 | (define memi-cfg (ISASimulator-cfg-memi-cfg ISASimulator-cfg-0)) 78 | (define memd-cfg-0 (ISASimulator-cfg-memd-cfg ISASimulator-cfg-0)) 79 | (define memd-cfg-1 (ISASimulator-cfg-memd-cfg ISASimulator-cfg-1)) 80 | 81 | (~a "memi: \n" memi-cfg "\n" 82 | "rf: " rf-cfg "\n" 83 | "memd-0: " memd-cfg-0 " memd-1: " memd-cfg-1 "\n") 84 | ) 85 | 86 | 87 | ; PART ISASimulator 88 | (struct ISASimulator (pc rf memi memd debug-commitLog param-simuCycle 89 | param-resetsym-cycle param-debug-print-on) 90 | #:mutable #:transparent 91 | #:methods gen:custom-write 92 | [(define (write-proc this port mode) 93 | (write-string (ISASimulator->string this) port))] 94 | ) 95 | 96 | 97 | (define (init-ISASimulator ISASimulator-cfg param-simuCycle 98 | param-resetsym-cycle param-debug-print-on) 99 | (define rf-cfg (ISASimulator-cfg-rf-cfg ISASimulator-cfg)) 100 | (define memi-cfg (ISASimulator-cfg-memi-cfg ISASimulator-cfg)) 101 | (define memd-cfg (ISASimulator-cfg-memd-cfg ISASimulator-cfg)) 102 | 103 | (ISASimulator 104 | (bv 0 param-memi-size-log) 105 | (init-rf rf-cfg) 106 | (init-memi memi-cfg param-simuCycle) 107 | (init-memd memd-cfg param-simuCycle) 108 | (list) 109 | param-simuCycle 110 | param-resetsym-cycle 111 | param-debug-print-on) 112 | ) 113 | 114 | 115 | (define (resetsym-ISASimulator! ISASimulator) 116 | (define rf (ISASimulator-rf ISASimulator)) 117 | 118 | (resetsym-rf! rf) 119 | ) 120 | 121 | 122 | (define (simu-ISASimulator! ISASimulator MAXCLK) 123 | (define pc (ISASimulator-pc ISASimulator)) 124 | (define rf (ISASimulator-rf ISASimulator)) 125 | (define memi (ISASimulator-memi ISASimulator)) 126 | (define memd (ISASimulator-memd ISASimulator)) 127 | (define debug-commitLog (ISASimulator-debug-commitLog ISASimulator)) 128 | (define param-simuCycle (ISASimulator-param-simuCycle ISASimulator)) 129 | (define param-resetsym-cycle (ISASimulator-param-resetsym-cycle ISASimulator)) 130 | (define param-resetsym-cycle-bv 131 | (bv (sub1 param-resetsym-cycle) 132 | (inexact->exact (ceiling (log param-simuCycle 2))))) 133 | (define param-debug-print-on (ISASimulator-param-debug-print-on ISASimulator)) 134 | 135 | ; STEP Fetch 136 | (define inst (logref-memi! memi pc)) 137 | 138 | ; patch false counter example from SMT: branch target should not be next pc 139 | (when (bveq inst-op-Br (inst-op inst)) 140 | (assume (not (bvzero? (bvsub1 (extract (sub1 param-memi-size-log) 0 141 | (inst-rs1 inst))))))) 142 | 143 | ; STEP Decode & Execute 144 | (match-define (list wen addr data brjmp taken target mrd mwt maddr mdata) 145 | (decode inst pc rf memd)) 146 | 147 | ; STEP Memory 148 | (when mrd (set! data (logref-memd! memd maddr))) 149 | (when mwt (logset-memd! memd maddr mdata)) 150 | 151 | ; STEP Debug verify correctness 152 | (when param-debug-commitLog-on 153 | (set-ISASimulator-debug-commitLog! ISASimulator (append 154 | debug-commitLog 155 | (if wen (list (list pc addr data)) (list (list pc)))))) 156 | 157 | ; STEP Write Back 158 | (when wen (set-rf! rf addr data)) 159 | (set-ISASimulator-pc! ISASimulator (if brjmp target (bvadd1 pc))) 160 | 161 | ; STEP tick 162 | (tick-memi! memi) 163 | (tick-memd! memd) 164 | 165 | ; STEP inc clk for mem 166 | (when (not (bvzero? MAXCLK)) 167 | (when (and (not param-debug-print-on) 168 | (bvzero? (bvurem MAXCLK param-resetsym-cycle-bv))) 169 | (resetsym-ISASimulator! ISASimulator)) 170 | (simu-ISASimulator! ISASimulator (bvsub1 MAXCLK))) 171 | ) 172 | 173 | 174 | (define (ISASimulator->string ISASimulator) 175 | (define pc (ISASimulator-pc ISASimulator)) 176 | (define rf (ISASimulator-rf ISASimulator)) 177 | (define memi (ISASimulator-memi ISASimulator)) 178 | (define memd (ISASimulator-memd ISASimulator)) 179 | (define debug-commitLog (ISASimulator-debug-commitLog ISASimulator)) 180 | 181 | (define debug-commitLog-int (map 182 | (lambda (entry) (map bitvector->natural entry)) 183 | debug-commitLog)) 184 | 185 | (~a 186 | ; "debug-commitLog: " debug-commitLog-int "\n" 187 | "memi: " memi "\n" 188 | "memd: " memd "\n" 189 | ) 190 | ) 191 | 192 | 193 | (define (ISASimulator-memTrace ISASimulator) 194 | (define memi (ISASimulator-memi ISASimulator)) 195 | (define memd (ISASimulator-memd ISASimulator)) 196 | 197 | (list (memi-history memi) (memd-history memd)) 198 | ) 199 | 200 | 201 | (define (assume-ISASimulator-memTrace memTrace-0 memTrace-1) 202 | (assume (equal? (first memTrace-0) (first memTrace-1))) 203 | (assume (equal? (second memTrace-0) (second memTrace-1))) 204 | ) 205 | 206 | 207 | (define (testMe) 208 | (match-define (list ISASimulator-cfg-0 ISASimulator-cfg-1) 209 | (init-ISASimulator-cfg-pair)) 210 | 211 | (define ISASimulator (init-ISASimulator 212 | ISASimulator-cfg-0 213 | param-ISASimulator-simuCycle param-ISASimulator-resetsym-cycle #t)) 214 | 215 | (printf (~a ISASimulator "\n")) 216 | (simu-ISASimulator! ISASimulator param-ISASimulator-simuCycle-bv) 217 | (printf (~a ISASimulator "\n")) 218 | (printf (~a (ISASimulator-memTrace ISASimulator) "\n")) 219 | 220 | ) 221 | ;(testMe) 222 | 223 | -------------------------------------------------------------------------------- /src/abs-module/absArbiter.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "../lib/lib.rkt" "absDelay.rkt") 4 | (require "absFifo.rkt") ; for debug 5 | (provide 6 | init-absArbiter-cfg absArbiter-cfg-evaluate 7 | init-absArbiter absArbiter-dataoutValid dataout-absArbiter! 8 | datain-absArbiter! absArbiter-datainReady squash-absArbiter! 9 | squashPartial-absArbiter! tick-absArbiter! 10 | ) 11 | 12 | 13 | 14 | ; stateless 15 | ; module arbiter ( 16 | ; input datain_1; 17 | ; input datain_id_1; 18 | ; input datain_valid_1; 19 | ; output datain_ready_1; 20 | ; input timing_factors_1; 21 | 22 | ; input datain_2; 23 | ; input datain_id_2; 24 | ; input datain_valid_2; 25 | ; output datain_ready_2; 26 | ; input timing_factors_2; 27 | 28 | ; ... 29 | 30 | ; output dataout; 31 | ; output dataout_id; 32 | ; output dataout_valid; 33 | ; input dataout_ready; 34 | ; ) 35 | 36 | ;; Simulation Constrains: 37 | ; - fanin should be 2^n 38 | ; - we assume arbiter will out valid when there's at least one in valid 39 | 40 | 41 | (struct absArbiter-cfg (uninterF param-timFct-len param-fanin) 42 | #:mutable #:transparent 43 | #:methods gen:custom-write 44 | [(define (write-proc this port mode) 45 | (write-string (absArbiter-cfg->string this) port))] 46 | ) 47 | 48 | 49 | (define (init-absArbiter-cfg param-timFct-len param-fanin param-symType) 50 | (define param-fanin-log (inexact->exact (log param-fanin 2))) 51 | 52 | (absArbiter-cfg 53 | (cond 54 | [param-enable-arbiterPriority 55 | (lambda (history-brID history-valid) 56 | (define fanId (bv 0 param-fanin-log)) 57 | (define brID-mini (bv -1 param-brID-len)) 58 | (for ([i (in-range param-fanin)]) 59 | (define i-bv (integer->bitvector i (bitvector param-fanin-log))) 60 | (define brID (array-ref history-brID i-bv)) 61 | (define valid (array-ref history-valid i-bv)) 62 | (when (and (bveq valid (bv 1 1)) (bvule brID brID-mini)) 63 | (set! fanId i-bv) 64 | (set! brID-mini brID))) 65 | fanId)] 66 | 67 | ; NOTE: this concrete function return the smallest ready fanId 68 | [(equal? param-symType "func_concrete") 69 | (lambda (history-timFct-valid) 70 | (define history-valid (extract (- param-fanin 1) 0 71 | history-timFct-valid)) 72 | (define fanId (bv 0 param-fanin-log)) 73 | (for ([i (in-range (- param-fanin 1) -1 -1)]) 74 | (define i-bv (integer->bitvector i (bitvector param-fanin-log))) 75 | (define valid (extract i i history-valid)) 76 | (when (bveq valid (bv 1 1)) (set! fanId i-bv))) 77 | ; (printf (~a "Get: " history-valid "; Return: " fanId "\n")) 78 | fanId)] 79 | 80 | [(equal? param-symType "func_sym") 81 | (build-unfuncbv (* param-fanin (add1 param-timFct-len)) 82 | param-fanin-log)]) 83 | param-timFct-len 84 | param-fanin) 85 | ) 86 | 87 | 88 | (define (absArbiter-cfg-evaluate absArbiter-cfg-sym sol) 89 | (define uninterF (absArbiter-cfg-uninterF absArbiter-cfg-sym)) 90 | (define param-timFct-len (absArbiter-cfg-param-timFct-len absArbiter-cfg-sym)) 91 | (define param-fanin (absArbiter-cfg-param-fanin absArbiter-cfg-sym)) 92 | 93 | (absArbiter-cfg (evaluate uninterF sol) param-timFct-len param-fanin) 94 | ) 95 | 96 | 97 | (define (absArbiter-cfg->string absArbiter-cfg) 98 | "uninterF" 99 | ) 100 | 101 | 102 | ; PART absArbiter 103 | (struct absArbiter (buffer-data buffer-squashed buffer-brID history-timFct 104 | history-brID history-valid uninterF absDelay param-fanin) 105 | #:mutable #:transparent 106 | #:methods gen:custom-write 107 | [(define (write-proc this port mode) 108 | (write-string (absArbiter->string this) port))] 109 | ) 110 | 111 | 112 | (define (init-absArbiter absArbiter-cfg absDelay param-entry-len) 113 | (define param-timFct-len (absArbiter-cfg-param-timFct-len absArbiter-cfg)) 114 | (define param-fanin (absArbiter-cfg-param-fanin absArbiter-cfg)) 115 | (define param-fanin-log (inexact->exact (ceiling (log param-fanin 2)))) 116 | 117 | (absArbiter 118 | (initZeroVec-array param-fanin param-entry-len) 119 | (initFalseVec-array param-fanin) 120 | (initZeroVec-array param-fanin param-brID-len) 121 | 122 | (initZeroVec-array param-fanin param-timFct-len) 123 | (initZeroVec-array param-fanin param-brID-len) 124 | (initZeroVec-array param-fanin 1) 125 | (absArbiter-cfg-uninterF absArbiter-cfg) 126 | absDelay 127 | param-fanin) 128 | ) 129 | 130 | 131 | (define (datain-absArbiter! absArbiter datain brID fanId timFct) 132 | (define buffer-data (absArbiter-buffer-data absArbiter)) 133 | (define buffer-squashed (absArbiter-buffer-squashed absArbiter)) 134 | (define buffer-brID (absArbiter-buffer-brID absArbiter)) 135 | (define history-timFct (absArbiter-history-timFct absArbiter)) 136 | (define history-brID (absArbiter-history-brID absArbiter)) 137 | (define history-valid (absArbiter-history-valid absArbiter)) 138 | 139 | (set-array! buffer-data fanId datain) 140 | (set-array! buffer-squashed fanId #f) 141 | (set-array! buffer-brID fanId brID) 142 | (set-array! history-timFct fanId timFct) 143 | (when param-enable-arbiterPriority (set-array! history-brID fanId brID)) 144 | (set-array! history-valid fanId (bv 1 1)) 145 | ) 146 | 147 | 148 | (define (absArbiter-datainReady absArbiter) 149 | (define uninterF (absArbiter-uninterF absArbiter)) 150 | (define history-timFct (absArbiter-history-timFct absArbiter)) 151 | (define history-brID (absArbiter-history-brID absArbiter)) 152 | (define history-valid (absArbiter-history-valid absArbiter)) 153 | (define absDelay (absArbiter-absDelay absArbiter)) 154 | 155 | (define fanId (if param-enable-arbiterPriority 156 | (uninterF history-brID history-valid) 157 | (uninterF (concat (array->bv history-timFct) (array->bv history-valid))))) 158 | (define fanValid (array-ref history-valid fanId)) 159 | 160 | (list (and (absDelay-datainReady absDelay) (bitvector->bool fanValid)) fanId) 161 | ) 162 | 163 | 164 | (define (absArbiter-dataoutValid absArbiter) 165 | (match-define (list valid fanId) (absArbiter-datainReady absArbiter)) 166 | (define buffer-squashed (absArbiter-buffer-squashed absArbiter)) 167 | 168 | (and valid (not (array-ref buffer-squashed fanId))) 169 | ) 170 | 171 | 172 | (define (dataout-absArbiter! absArbiter) 173 | (define buffer-data (absArbiter-buffer-data absArbiter)) 174 | (define buffer-brID (absArbiter-buffer-brID absArbiter)) 175 | (define history-timFct (absArbiter-history-timFct absArbiter)) 176 | (match-define (list valid fanId) (absArbiter-datainReady absArbiter)) 177 | 178 | (list (array-ref buffer-data fanId) 179 | (array-ref buffer-brID fanId) 180 | (array-ref history-timFct fanId)) 181 | ) 182 | 183 | 184 | (define (squash-absArbiter! absArbiter) 185 | (define buffer-squashed (absArbiter-buffer-squashed absArbiter)) 186 | 187 | (resetToTrueVec-array! buffer-squashed) 188 | ) 189 | 190 | 191 | (define (squashPartial-absArbiter! absArbiter misPredBr-brID) 192 | (define buffer-squashed (absArbiter-buffer-squashed absArbiter)) 193 | (define buffer-brID (absArbiter-buffer-brID absArbiter)) 194 | (define history-valid (absArbiter-history-valid absArbiter)) 195 | (define param-fanin (absArbiter-param-fanin absArbiter)) 196 | (define param-fanin-log (inexact->exact (ceiling (log param-fanin 2)))) 197 | 198 | (for ([i (in-range param-fanin)]) 199 | (define i-bv (integer->bitvector i (bitvector param-fanin-log))) 200 | 201 | (define brID (array-ref buffer-brID i-bv)) 202 | (when (bvugt brID misPredBr-brID) 203 | (set-array! buffer-squashed i-bv #t))) 204 | ) 205 | 206 | 207 | (define (tick-absArbiter! absArbiter) 208 | (define buffer-data (absArbiter-buffer-data absArbiter)) 209 | (define buffer-squashed (absArbiter-buffer-squashed absArbiter)) 210 | (define buffer-brID (absArbiter-buffer-brID absArbiter)) 211 | (define history-timFct (absArbiter-history-timFct absArbiter)) 212 | (define history-valid (absArbiter-history-valid absArbiter)) 213 | 214 | (resetToZeroVec-array! buffer-data) 215 | (resetToFalseVec-array! buffer-squashed) 216 | (resetToZeroVec-array! buffer-brID) 217 | (resetToZeroVec-array! history-timFct) 218 | (resetToZeroVec-array! history-valid) 219 | ) 220 | 221 | 222 | (define (absArbiter->string absArbiter) 223 | (~a 224 | ; "buffer-data: " (absArbiter-buffer-data absArbiter) 225 | ; "buffer-squashed: " (absArbiter-buffer-squashed absArbiter) 226 | ; "buffer-brID: " (absArbiter-buffer-brID absArbiter) 227 | "timFct: " (absArbiter-history-timFct absArbiter) 228 | "valid: " (absArbiter-history-valid absArbiter) 229 | ) 230 | ) 231 | 232 | 233 | (define (testMe) 234 | 235 | 236 | (define absFifo-cfg (init-absFifo-cfg 2 10 "func_concrete")) 237 | (define absFifo (init-absFifo absFifo-cfg 5)) 238 | 239 | (define absArbiter-cfg (init-absArbiter-cfg 2 8 "func_concrete")) 240 | (define absArbiter (init-absArbiter absArbiter-cfg absFifo 4)) 241 | (printf (~a absArbiter "\n")) 242 | 243 | (printf (~a (absArbiter-dataoutValid absArbiter) "\n")) 244 | ;(printf (~a (dataout-absArbiter! absArbiter) "\n")) 245 | (printf (~a (datain-absArbiter! absArbiter (bv 1 5) (bv 0 3) (bv 1 2)) "\n")) 246 | (printf (~a (absArbiter-datainReady absArbiter) "\n")) 247 | (printf (~a absArbiter "\n")) 248 | 249 | (tick-absArbiter! absArbiter) 250 | (printf (~a "-----------------\n")) 251 | 252 | (printf (~a (absArbiter-dataoutValid absArbiter) "\n")) 253 | (printf (~a (dataout-absArbiter! absArbiter) "\n")) 254 | (printf (~a (datain-absArbiter! absArbiter (bv 8 5) (bv 1 3) (bv 2 2)) "\n")) 255 | (printf (~a (absArbiter-datainReady absArbiter) "\n")) 256 | (printf (~a absArbiter "\n")) 257 | ) 258 | ;(testMe) 259 | 260 | -------------------------------------------------------------------------------- /src/abs-module/absBufferGM.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "../lib/lib.rkt") 4 | (provide 5 | init-absBufferGM-cfg absBufferGM-cfg-evaluate absBufferGM-cfg? 6 | init-absBufferGM absBufferGM-dataoutValid dataout-absBufferGM! 7 | absBufferGM-datainReady datain-absBufferGM! 1cycleSquash-absBufferGM! 8 | drainSquash-absBufferGM! drainSquashPartial-absBufferGM! absBufferGM-obsv 9 | tick-absBufferGM! absBufferGM? 10 | ) 11 | 12 | 13 | ; module buffer ( 14 | ; input (datain, datain_id); 15 | ; output datain_ready; 16 | ; input datain_valid; 17 | ; input timing_factors; 18 | 19 | ; output (dataout, dataout_id); 20 | ; output dataout_valid; 21 | ; input dataout_ready; 22 | ; ) 23 | 24 | ;; Simulation Constrains: 25 | ; - Call valid/ready function to check availablity first, then call dataout/in. 26 | ; - Call dataout first, then datain, 27 | ; to avoid respond the same request at the cycle. 28 | ; - Only push into param-simuCycle number datain, 29 | ; and should not ask dataout after the last datain. 30 | ; - This is a delay buffer that can re-order requests 31 | 32 | 33 | ; PART absBufferGM-cfg 34 | (struct absBufferGM-cfg (uninterF param-timFct-len param-simuCycle) 35 | #:mutable #:transparent 36 | #:methods gen:custom-write 37 | [(define (write-proc this port mode) 38 | (write-string (absBufferGM-cfg->string this) port))] 39 | ) 40 | 41 | 42 | (define (init-absBufferGM-cfg param-timFct-len param-simuCycle param-symType) 43 | (absBufferGM-cfg 44 | (cond 45 | [(equal? param-symType "func_concrete") 46 | (lambda (ignore) (bv 1 1))] 47 | 48 | [(equal? param-symType "func_sym") 49 | (build-unfuncbv (* param-simuCycle (add1 param-timFct-len)) 1)]) 50 | param-timFct-len 51 | param-simuCycle) 52 | ) 53 | 54 | 55 | (define (absBufferGM-cfg-evaluate absBufferGM-cfg-sym sol) 56 | (define uninterF (absBufferGM-cfg-uninterF absBufferGM-cfg-sym)) 57 | (define param-timFct-len 58 | (absBufferGM-cfg-param-timFct-len absBufferGM-cfg-sym)) 59 | (define param-simuCycle (absBufferGM-cfg-param-simuCycle absBufferGM-cfg-sym)) 60 | 61 | (absBufferGM-cfg (evaluate uninterF sol) param-timFct-len param-simuCycle) 62 | ) 63 | 64 | 65 | (define (absBufferGM-cfg->string absBufferGM-cfg) 66 | "uninterF" 67 | ) 68 | 69 | 70 | ; PART absBufferGM 71 | (struct absBufferGM (buffer-data buffer-brID buffer-valid history-timFct 72 | history-valid uninterF clk param-simuCycle) 73 | #:mutable #:transparent 74 | #:methods gen:custom-write 75 | [(define (write-proc this port mode) 76 | (write-string (absBufferGM->string this) port))] 77 | ) 78 | 79 | 80 | (define (init-absBufferGM absBufferGM-cfg param-entry-len) 81 | (define uninterF (absBufferGM-cfg-uninterF absBufferGM-cfg)) 82 | (define param-timFct-len 83 | (absBufferGM-cfg-param-timFct-len absBufferGM-cfg)) 84 | (define param-simuCycle (absBufferGM-cfg-param-simuCycle absBufferGM-cfg)) 85 | (define param-simuCycle-log 86 | (inexact->exact (ceiling (log param-simuCycle 2)))) 87 | 88 | (absBufferGM 89 | (initZeroVec-array param-simuCycle param-entry-len) 90 | (initZeroVec-array param-simuCycle param-brID-len) 91 | (initZeroVec-array param-simuCycle 1) 92 | 93 | (initZeroVec-array param-simuCycle param-timFct-len) 94 | (initZeroVec-array param-simuCycle 1) 95 | uninterF 96 | 97 | (bv 0 param-simuCycle-log) 98 | param-simuCycle) 99 | ) 100 | 101 | 102 | (define (absBufferGM-nextOut-isEmpty-index-brID absBufferGM) 103 | (define buffer-brID (absBufferGM-buffer-brID absBufferGM)) 104 | (define buffer-valid (absBufferGM-buffer-valid absBufferGM)) 105 | (define param-simuCycle (absBufferGM-param-simuCycle absBufferGM)) 106 | (define param-simuCycle-log 107 | (inexact->exact (ceiling (log param-simuCycle 2)))) 108 | 109 | (define isEmpty #t) 110 | (define index (bv 0 param-simuCycle-log)) 111 | (define brID-mini (bv -1 param-brID-len)) 112 | (for ([i (in-range param-simuCycle)]) 113 | (define i-bv (integer->bitvector i (bitvector param-simuCycle-log))) 114 | (define brID (array-ref buffer-brID i-bv)) 115 | (define valid (array-ref buffer-valid i-bv)) 116 | (when (and (bveq valid (bv 1 1)) (bvule brID brID-mini)) 117 | (set! isEmpty #f) 118 | (set! index i-bv) 119 | (set! brID-mini brID))) 120 | 121 | (list isEmpty index brID-mini) 122 | ) 123 | 124 | 125 | (define (absBufferGM-dataoutValid absBufferGM) 126 | (define buffer-brID (absBufferGM-buffer-brID absBufferGM)) 127 | (define buffer-valid (absBufferGM-buffer-valid absBufferGM)) 128 | (define history-timFct (absBufferGM-history-timFct absBufferGM)) 129 | (define history-valid (absBufferGM-history-valid absBufferGM)) 130 | (define uninterF (absBufferGM-uninterF absBufferGM)) 131 | 132 | (match-define (list isEmpty index brID-mini) 133 | (absBufferGM-nextOut-isEmpty-index-brID absBufferGM)) 134 | 135 | ; NOTE: we assume buffer and history are indexed in a same way here 136 | (define (maskThisEntry i-bv) 137 | (define brID (array-ref buffer-brID i-bv)) 138 | (bvugt brID brID-mini)) 139 | (define history-timFct-masked (array->masked history-timFct maskThisEntry)) 140 | (define history-valid-masked (array->masked history-valid maskThisEntry)) 141 | 142 | (and (not isEmpty) 143 | (bitvector->bool (uninterF (concat (array->bv history-timFct-masked) 144 | (array->bv history-valid-masked))))) 145 | ) 146 | 147 | 148 | (define (dataout-absBufferGM! absBufferGM) 149 | (define buffer-data (absBufferGM-buffer-data absBufferGM)) 150 | (define buffer-valid (absBufferGM-buffer-valid absBufferGM)) 151 | 152 | (match-define (list isEmpty index brID-mini) 153 | (absBufferGM-nextOut-isEmpty-index-brID absBufferGM)) 154 | 155 | (resetToZero-array! buffer-valid index) 156 | (array-ref buffer-data index) 157 | ) 158 | 159 | 160 | (define (absBufferGM-datainReady absBufferGM) #t) 161 | 162 | 163 | (define (datain-absBufferGM! absBufferGM datain brID timFct) 164 | (define buffer-data (absBufferGM-buffer-data absBufferGM)) 165 | (define buffer-brID (absBufferGM-buffer-brID absBufferGM)) 166 | (define buffer-valid (absBufferGM-buffer-valid absBufferGM)) 167 | (define history-timFct (absBufferGM-history-timFct absBufferGM)) 168 | (define history-valid (absBufferGM-history-valid absBufferGM)) 169 | (define clk (absBufferGM-clk absBufferGM)) 170 | 171 | (set-array! buffer-data clk datain) 172 | (set-array! buffer-brID clk brID) 173 | (set-array! buffer-valid clk (bv 1 1)) 174 | 175 | (set-array! history-timFct clk timFct) 176 | (set-array! history-valid clk (bv 1 1)) 177 | ) 178 | 179 | 180 | ; NOTE: 1cycleSquash cannot be partial 181 | (define (1cycleSquash-absBufferGM! absBufferGM) 182 | (define buffer-data (absBufferGM-buffer-data absBufferGM)) 183 | (define buffer-brID (absBufferGM-buffer-brID absBufferGM)) 184 | (define buffer-valid (absBufferGM-buffer-valid absBufferGM)) 185 | (define history-timFct (absBufferGM-history-timFct absBufferGM)) 186 | (define history-valid (absBufferGM-history-valid absBufferGM)) 187 | 188 | (resetToZeroVec-array! buffer-data) 189 | (resetToZeroVec-array! buffer-brID) 190 | (resetToZeroVec-array! buffer-valid) 191 | (resetToZeroVec-array! history-timFct) 192 | (resetToZeroVec-array! history-valid) 193 | ) 194 | 195 | 196 | (define (drainSquash-absBufferGM! absBufferGM) 197 | (define buffer-data (absBufferGM-buffer-data absBufferGM)) 198 | (define buffer-brID (absBufferGM-buffer-brID absBufferGM)) 199 | (define buffer-valid (absBufferGM-buffer-valid absBufferGM)) 200 | 201 | (resetToZeroVec-array! buffer-data) 202 | (resetToZeroVec-array! buffer-brID) 203 | (resetToZeroVec-array! buffer-valid) 204 | ) 205 | 206 | 207 | (define (drainSquashPartial-absBufferGM! absBufferGM misPredBr-brID) 208 | (define buffer-data (absBufferGM-buffer-data absBufferGM)) 209 | (define buffer-brID (absBufferGM-buffer-brID absBufferGM)) 210 | (define buffer-valid (absBufferGM-buffer-valid absBufferGM)) 211 | (define param-simuCycle (absBufferGM-param-simuCycle absBufferGM)) 212 | (define param-simuCycle-log 213 | (inexact->exact (ceiling (log param-simuCycle 2)))) 214 | 215 | (for ([i (in-range param-simuCycle)]) 216 | (define i-bv (integer->bitvector i (bitvector param-simuCycle-log))) 217 | 218 | (define brID (array-ref buffer-brID i-bv)) 219 | (when (bvugt brID misPredBr-brID) 220 | (resetToZero-array! buffer-data i-bv) 221 | (resetToZero-array! buffer-brID i-bv) 222 | (resetToZero-array! buffer-valid i-bv))) 223 | ) 224 | 225 | 226 | (define (absBufferGM-obsv absBufferGM) 227 | (define history-timFct (absBufferGM-history-timFct absBufferGM)) 228 | (define history-valid (absBufferGM-history-valid absBufferGM)) 229 | 230 | (concat (array->bv history-timFct) (array->bv history-valid)) 231 | ) 232 | 233 | 234 | (define (tick-absBufferGM! absBufferGM) 235 | (define clk (absBufferGM-clk absBufferGM)) 236 | 237 | (set-absBufferGM-clk! absBufferGM (bvadd1 clk)) 238 | ) 239 | 240 | 241 | (define (absBufferGM->string absBufferGM) 242 | (~a "history-valid: " (absBufferGM-history-valid absBufferGM) 243 | "history-timFct: " (absBufferGM-history-timFct absBufferGM) 244 | ; "buffer-data: " (absBufferGM-buffer-data absBufferGM) 245 | "buffer-valid: " (absBufferGM-buffer-valid absBufferGM) 246 | "buffer-brID: " (absBufferGM-buffer-brID absBufferGM) 247 | ; "dataoutValid: " (absBufferGM-dataoutValid absBufferGM) 248 | ) 249 | ) 250 | 251 | 252 | (define (testMe) 253 | 254 | (define absBufferGM-cfg (init-absBufferGM-cfg 2 10 "func_concrete")) 255 | (define absBufferGM (init-absBufferGM absBufferGM-cfg 5)) 256 | (printf (~a absBufferGM "\n")) 257 | 258 | (printf (~a (absBufferGM-dataoutValid absBufferGM) "\n")) 259 | ;(printf (~a (dataout-absBufferGM! absBufferGM) "\n")) 260 | (printf (~a (absBufferGM-datainReady absBufferGM) "\n")) 261 | (printf (~a (datain-absBufferGM! absBufferGM (bv 31 5) (bv 3 2)) "\n")) 262 | (printf (~a absBufferGM "\n")) 263 | 264 | (tick-absBufferGM! absBufferGM) 265 | (printf (~a "-----------------\n")) 266 | 267 | (printf (~a (absBufferGM-dataoutValid absBufferGM) "\n")) 268 | (printf (~a (dataout-absBufferGM! absBufferGM) "\n")) 269 | (printf (~a (absBufferGM-datainReady absBufferGM) "\n")) 270 | (printf (~a (datain-absBufferGM! absBufferGM (bv 1 5) (bv 1 2)) "\n")) 271 | (printf (~a absBufferGM "\n")) 272 | ) 273 | ;(testMe) 274 | 275 | -------------------------------------------------------------------------------- /src/abs-module/absDelay.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "absFifo.rkt" "absFifo2.rkt" "absBufferGM.rkt" "../lib/lib.rkt") 4 | (provide 5 | absDelay-cfg-evaluate init-absDelay absDelay-dataoutValid dataout-absDelay! 6 | absDelay-datainReady datain-absDelay! 1cycleSquash-absDelay! 7 | drainSquash-absDelay! drainSquashPartial-absDelay! absDelay-obsv 8 | tick-absDelay! 9 | ) 10 | 11 | 12 | (define (absDelay-cfg-evaluate . arg) 13 | (cond 14 | [(absFifo-cfg? (car arg)) (apply absFifo-cfg-evaluate arg)] 15 | [(absFifo2-cfg? (car arg)) (apply absFifo2-cfg-evaluate arg)] 16 | [(absBufferGM-cfg? (car arg)) (apply absBufferGM-cfg-evaluate arg)] 17 | [else (bug-assert #f #:msg "absDelay unknown")]) 18 | ) 19 | 20 | 21 | (define (init-absDelay . arg) 22 | (cond 23 | [(absFifo-cfg? (car arg)) (apply init-absFifo arg)] 24 | [(absFifo2-cfg? (car arg)) (apply init-absFifo2 arg)] 25 | [(absBufferGM-cfg? (car arg)) (apply init-absBufferGM arg)] 26 | [else (bug-assert #f #:msg "absDelay unknown")]) 27 | ) 28 | 29 | 30 | (define (absDelay-dataoutValid . arg) 31 | (cond 32 | [(absFifo? (car arg)) (apply absFifo-dataoutValid arg)] 33 | [(absFifo2? (car arg)) (apply absFifo2-dataoutValid arg)] 34 | [(absBufferGM? (car arg)) (apply absBufferGM-dataoutValid arg)] 35 | [else (bug-assert #f #:msg "absDelay unknown")]) 36 | ) 37 | 38 | 39 | (define (dataout-absDelay! . arg) 40 | (cond 41 | [(absFifo? (car arg)) (apply dataout-absFifo! arg)] 42 | [(absFifo2? (car arg)) (apply dataout-absFifo2! arg)] 43 | [(absBufferGM? (car arg)) (apply dataout-absBufferGM! arg)] 44 | [else (bug-assert #f #:msg "absDelay unknown")]) 45 | ) 46 | 47 | 48 | (define (absDelay-datainReady . arg) 49 | (cond 50 | [(absFifo? (car arg)) (apply absFifo-datainReady arg)] 51 | [(absFifo2? (car arg)) (apply absFifo2-datainReady arg)] 52 | [(absBufferGM? (car arg)) (apply absBufferGM-datainReady arg)] 53 | [else (bug-assert #f #:msg "absDelay unknown")]) 54 | ) 55 | 56 | 57 | (define (datain-absDelay! . arg) 58 | (cond 59 | [(absFifo? (car arg)) (apply datain-absFifo! arg)] 60 | [(absFifo2? (car arg)) (apply datain-absFifo2! arg)] 61 | [(absBufferGM? (car arg)) (apply datain-absBufferGM! arg)] 62 | [else (bug-assert #f #:msg "absDelay unknown")]) 63 | ) 64 | 65 | 66 | (define (1cycleSquash-absDelay! . arg) 67 | (cond 68 | [(absFifo? (car arg)) (apply 1cycleSquash-absFifo! arg)] 69 | [(absFifo2? (car arg)) (apply 1cycleSquash-absFifo2! arg)] 70 | [(absBufferGM? (car arg)) (apply 1cycleSquash-absBufferGM! arg)] 71 | [else (bug-assert #f #:msg "absDelay unknown")]) 72 | ) 73 | 74 | 75 | (define (drainSquash-absDelay! . arg) 76 | (cond 77 | [(absFifo? (car arg)) (apply drainSquash-absFifo! arg)] 78 | [(absFifo2? (car arg)) (apply drainSquash-absFifo2! arg)] 79 | [(absBufferGM? (car arg)) (apply drainSquash-absBufferGM! arg)] 80 | [else (bug-assert #f #:msg "absDelay unknown")]) 81 | ) 82 | 83 | 84 | (define (drainSquashPartial-absDelay! . arg) 85 | (cond 86 | [(absFifo? (car arg)) (apply drainSquashPartial-absFifo! arg)] 87 | [(absBufferGM? (car arg)) (apply drainSquashPartial-absBufferGM! arg)] 88 | [else (bug-assert #f #:msg "absDelay unknown")]) 89 | ) 90 | 91 | 92 | (define (absDelay-obsv . arg) 93 | (cond 94 | [(absFifo? (car arg)) (apply absFifo-obsv arg)] 95 | [(absBufferGM? (car arg)) (apply absBufferGM-obsv arg)] 96 | [else (bug-assert #f #:msg "absDelay unknown")]) 97 | ) 98 | 99 | 100 | (define (tick-absDelay! . arg) 101 | (cond 102 | [(absFifo? (car arg)) (apply tick-absFifo! arg)] 103 | [(absFifo2? (car arg)) (apply tick-absFifo2! arg)] 104 | [(absBufferGM? (car arg)) (apply tick-absBufferGM! arg)] 105 | [else (bug-assert #f #:msg "absDelay unknown")]) 106 | ) 107 | 108 | -------------------------------------------------------------------------------- /src/abs-module/absFifo.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "../lib/lib.rkt") 4 | (provide 5 | init-absFifo-cfg absFifo-cfg-evaluate absFifo-cfg? 6 | init-absFifo absFifo-dataoutValid dataout-absFifo! absFifo-datainReady 7 | datain-absFifo! 1cycleSquash-absFifo! drainSquash-absFifo! 8 | drainSquashPartial-absFifo! absFifo-obsv tick-absFifo! absFifo? 9 | ) 10 | 11 | 12 | ; module fifo ( 13 | ; input (datain, datain_id); 14 | ; output datain_ready; 15 | ; input datain_valid; 16 | ; input timing_factors; 17 | 18 | ; output (dataout, dataout_id); 19 | ; output dataout_valid; 20 | ; input dataout_ready; 21 | ; ) 22 | 23 | ;; Simulation Constrains: 24 | ; - Call valid/ready function to check availablity first, then call dataout/in. 25 | ; - Call dataout first, then datain, 26 | ; to avoid respond the same request at the cycle. 27 | ; - Only push into param-simuCycle number datain, 28 | ; and should not ask dataout after the last datain. 29 | ; Because we simply use head==tail to detect full 30 | ; - This is a fifo, so id is just outputed in-order 31 | 32 | 33 | ; PART absFifo-cfg 34 | (struct absFifo-cfg (uninterF param-timFct-len param-simuCycle) 35 | #:mutable #:transparent 36 | #:methods gen:custom-write 37 | [(define (write-proc this port mode) 38 | (write-string (absFifo-cfg->string this) port))] 39 | ) 40 | 41 | 42 | (define (init-absFifo-cfg param-timFct-len param-simuCycle param-symType) 43 | (absFifo-cfg 44 | (cond 45 | [(equal? param-symType "func_concrete") 46 | (lambda (ignore) (bv 1 1))] 47 | 48 | [(equal? param-symType "func_sym") 49 | (build-unfuncbv (* param-simuCycle (add1 param-timFct-len)) 1)]) 50 | param-timFct-len 51 | param-simuCycle) 52 | ) 53 | 54 | 55 | (define (absFifo-cfg-evaluate absFifo-cfg-sym sol) 56 | (define uninterF (absFifo-cfg-uninterF absFifo-cfg-sym)) 57 | (define param-timFct-len (absFifo-cfg-param-timFct-len absFifo-cfg-sym)) 58 | (define param-simuCycle (absFifo-cfg-param-simuCycle absFifo-cfg-sym)) 59 | 60 | (absFifo-cfg (evaluate uninterF sol) param-timFct-len param-simuCycle) 61 | ) 62 | 63 | 64 | (define (absFifo-cfg->string absFifo-cfg) 65 | "uninterF" 66 | ) 67 | 68 | 69 | ; PART absFifo 70 | (struct absFifo (buffer-data buffer-squashed buffer-brID head tail 71 | history-timFct history-valid uninterF clk param-simuCycle) 72 | #:mutable #:transparent 73 | #:methods gen:custom-write 74 | [(define (write-proc this port mode) 75 | (write-string (absFifo->string this) port))] 76 | ) 77 | 78 | 79 | (define (init-absFifo absFifo-cfg param-entry-len) 80 | (define param-timFct-len 81 | (absFifo-cfg-param-timFct-len absFifo-cfg)) 82 | (define param-simuCycle (absFifo-cfg-param-simuCycle absFifo-cfg)) 83 | (define param-simuCycle-log 84 | (inexact->exact (ceiling (log param-simuCycle 2)))) 85 | 86 | (absFifo 87 | (initZeroVec-array param-simuCycle param-entry-len) 88 | (initFalseVec-array param-simuCycle) 89 | (initZeroVec-array param-simuCycle param-brID-len) 90 | (bv 0 param-simuCycle-log) 91 | (bv 0 param-simuCycle-log) 92 | (initZeroVec-array param-simuCycle param-timFct-len) 93 | (initZeroVec-array param-simuCycle 1) 94 | (absFifo-cfg-uninterF absFifo-cfg) 95 | (bv 0 param-simuCycle-log) 96 | param-simuCycle) 97 | ) 98 | 99 | 100 | (define (absFifo-empty absFifo) 101 | (define head (absFifo-head absFifo)) 102 | (define tail (absFifo-tail absFifo)) 103 | 104 | (bveq head tail) 105 | ) 106 | 107 | 108 | (define (absFifo-dataoutValid absFifo) 109 | (define buffer-squashed (absFifo-buffer-squashed absFifo)) 110 | (define head (absFifo-head absFifo)) 111 | (define uninterF (absFifo-uninterF absFifo)) 112 | (define history-timFct (absFifo-history-timFct absFifo)) 113 | (define history-valid (absFifo-history-valid absFifo)) 114 | 115 | (and (not (absFifo-empty absFifo)) 116 | (not (array-ref buffer-squashed head)) 117 | (bitvector->bool (uninterF (concat (array->bv history-timFct) 118 | (array->bv history-valid))))) 119 | ) 120 | 121 | 122 | (define (dataout-absFifo! absFifo) 123 | (define buffer-data (absFifo-buffer-data absFifo)) 124 | (define head (absFifo-head absFifo)) 125 | 126 | (when param-debug-assert (bug-assert 127 | (absFifo-dataoutValid absFifo) 128 | #:msg "dataout-absFifo!: test dataout_valid before dataout")) 129 | (set-absFifo-head! absFifo (bvadd1 head)) 130 | (array-ref buffer-data head) 131 | ) 132 | 133 | 134 | (define (absFifo-datainReady absFifo) #t) 135 | 136 | 137 | (define (datain-absFifo! absFifo datain brID timFct) 138 | (define buffer-data (absFifo-buffer-data absFifo)) 139 | (define buffer-squashed (absFifo-buffer-squashed absFifo)) 140 | (define buffer-brID (absFifo-buffer-brID absFifo)) 141 | (define tail (absFifo-tail absFifo)) 142 | (define history-timFct (absFifo-history-timFct absFifo)) 143 | (define history-valid (absFifo-history-valid absFifo)) 144 | (define clk (absFifo-clk absFifo)) 145 | 146 | (set-array! buffer-data tail datain) 147 | (set-array! buffer-squashed tail #f) 148 | (set-array! buffer-brID tail brID) 149 | (set-absFifo-tail! absFifo (bvadd1 tail)) 150 | 151 | (set-array! history-timFct clk timFct) 152 | (set-array! history-valid clk (bv 1 1)) 153 | ) 154 | 155 | 156 | ; NOTE: 1cycleSquash cannot be partial 157 | (define (1cycleSquash-absFifo! absFifo) 158 | (define buffer-data (absFifo-buffer-data absFifo)) 159 | (define history-timFct (absFifo-history-timFct absFifo)) 160 | (define history-valid (absFifo-history-valid absFifo)) 161 | (define param-simuCycle (absFifo-param-simuCycle absFifo)) 162 | (define param-simuCycle-log 163 | (inexact->exact (ceiling (log param-simuCycle 2)))) 164 | 165 | (resetToZeroVec-array! buffer-data) 166 | (set-absFifo-head! absFifo (bv 0 param-simuCycle-log)) 167 | (set-absFifo-tail! absFifo (bv 0 param-simuCycle-log)) 168 | (resetToZeroVec-array! history-timFct) 169 | (resetToZeroVec-array! history-valid) 170 | ) 171 | 172 | 173 | (define (drainSquash-absFifo! absFifo) 174 | (define buffer-data (absFifo-buffer-data absFifo)) 175 | (define param-simuCycle (absFifo-param-simuCycle absFifo)) 176 | (define param-simuCycle-log 177 | (inexact->exact (ceiling (log param-simuCycle 2)))) 178 | 179 | (resetToZeroVec-array! buffer-data) 180 | (set-absFifo-head! absFifo (bv 0 param-simuCycle-log)) 181 | (set-absFifo-tail! absFifo (bv 0 param-simuCycle-log)) 182 | ) 183 | 184 | 185 | ; TODO: can we have a version to change the head and tail of the buffer 186 | ; instead of using squahsed bit? 187 | (define (drainSquashPartial-absFifo! absFifo misPredBr-brID) 188 | (define buffer-data (absFifo-buffer-data absFifo)) 189 | (define buffer-squashed (absFifo-buffer-squashed absFifo)) 190 | (define buffer-brID (absFifo-buffer-brID absFifo)) 191 | (define param-simuCycle (absFifo-param-simuCycle absFifo)) 192 | (define param-simuCycle-log 193 | (inexact->exact (ceiling (log param-simuCycle 2)))) 194 | 195 | (for ([i (in-range param-simuCycle)]) 196 | (define i-bv (integer->bitvector i (bitvector param-simuCycle-log))) 197 | 198 | (define brID (array-ref buffer-brID i-bv)) 199 | (when (bvugt brID misPredBr-brID) 200 | (set-array! buffer-squashed i-bv #t))) 201 | ) 202 | 203 | 204 | (define (absFifo-obsv absFifo) 205 | (define history-timFct (absFifo-history-timFct absFifo)) 206 | (define history-valid (absFifo-history-valid absFifo)) 207 | 208 | (concat (array->bv history-timFct) (array->bv history-valid)) 209 | ) 210 | 211 | 212 | (define (tick-absFifo! absFifo) 213 | (define clk (absFifo-clk absFifo)) 214 | (define buffer-squashed (absFifo-buffer-squashed absFifo)) 215 | (define head (absFifo-head absFifo)) 216 | 217 | (when (and (not (absFifo-empty absFifo)) (array-ref buffer-squashed head)) 218 | (set-absFifo-head! absFifo (bvadd1 head))) 219 | (set-absFifo-clk! absFifo (bvadd1 clk)) 220 | 221 | ) 222 | 223 | 224 | (define (absFifo->string absFifo) 225 | (~a "Valid: " (absFifo-history-valid absFifo) 226 | "timFct: " (absFifo-history-timFct absFifo) 227 | ; "buffer-data: " (absFifo-buffer-data absFifo) 228 | "buffer-brID: " (absFifo-buffer-brID absFifo) 229 | ; "buffer-squashed: " (absFifo-buffer-squashed absFifo) 230 | ; "dataoutValid: " (absFifo-dataoutValid absFifo) 231 | ) 232 | ) 233 | 234 | 235 | (define (testMe) 236 | 237 | (define absFifo-cfg (init-absFifo-cfg 2 10 "func_concrete")) 238 | (define absFifo (init-absFifo absFifo-cfg 5)) 239 | (printf (~a absFifo "\n")) 240 | 241 | (printf (~a (absFifo-dataoutValid absFifo) "\n")) 242 | ;(printf (~a (dataout-absFifo! absFifo) "\n")) 243 | (printf (~a (absFifo-datainReady absFifo) "\n")) 244 | (printf (~a (datain-absFifo! absFifo (bv 31 5) (bv 3 2)) "\n")) 245 | (printf (~a absFifo "\n")) 246 | 247 | (tick-absFifo! absFifo) 248 | (printf (~a "-----------------\n")) 249 | 250 | (printf (~a (absFifo-dataoutValid absFifo) "\n")) 251 | (printf (~a (dataout-absFifo! absFifo) "\n")) 252 | (printf (~a (absFifo-datainReady absFifo) "\n")) 253 | (printf (~a (datain-absFifo! absFifo (bv 1 5) (bv 1 2)) "\n")) 254 | (printf (~a absFifo "\n")) 255 | ) 256 | ;(testMe) 257 | 258 | -------------------------------------------------------------------------------- /src/abs-module/absFifo2.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "../lib/lib.rkt") 4 | (provide 5 | init-absFifo2-cfg absFifo2-cfg-evaluate absFifo2-cfg? 6 | init-absFifo2 absFifo2-dataoutValid dataout-absFifo2! absFifo2-datainReady 7 | datain-absFifo2! 1cycleSquash-absFifo2! drainSquash-absFifo2! tick-absFifo2! 8 | absFifo2? 9 | ) 10 | 11 | 12 | ; This just double the input/output bandwidth to 2 13 | ; module fifo ( 14 | ; input (datain, dataout_id); 15 | ; output datain_ready; 16 | ; input timing_factors; 17 | ; input (datain, dataout_id); 18 | ; output datain_ready; 19 | ; input timing_factors; 20 | 21 | ; output (dataout, dataout_id); 22 | ; output dataout_valid; 23 | ; input dataout_ready; 24 | ; output (dataout, dataout_id); 25 | ; output dataout_valid; 26 | ; input dataout_ready; 27 | ; ) 28 | 29 | 30 | 31 | 32 | ; PART absFifo2-cfg 33 | (struct absFifo2-cfg (uninterF param-timFct-len param-simuCycle2) 34 | #:mutable #:transparent 35 | #:methods gen:custom-write 36 | [(define (write-proc this port mode) 37 | (write-string (absFifo2-cfg->string this) port))] 38 | ) 39 | 40 | 41 | (define (init-absFifo2-cfg param-timFct-len param-simuCycle param-symType) 42 | (absFifo2-cfg 43 | (cond 44 | [(equal? param-symType "func_concrete") 45 | (lambda (ignore) (bv 1 2))] 46 | 47 | [(equal? param-symType "func_sym") 48 | (build-unfuncbv (* 2 param-simuCycle (add1 param-timFct-len)) 2)]) 49 | param-timFct-len 50 | (* 2 param-simuCycle)) 51 | ) 52 | 53 | 54 | (define (absFifo2-cfg-evaluate absFifo2-cfg-sym sol) 55 | (define uninterF (absFifo2-cfg-uninterF absFifo2-cfg-sym)) 56 | (define param-timFct-len 57 | (absFifo2-cfg-param-timFct-len absFifo2-cfg-sym)) 58 | (define param-simuCycle2 (absFifo2-cfg-param-simuCycle2 absFifo2-cfg-sym)) 59 | 60 | (absFifo2-cfg (evaluate uninterF sol) param-timFct-len param-simuCycle2) 61 | ) 62 | 63 | 64 | (define (absFifo2-cfg->string absFifo2-cfg) 65 | "uninterF" 66 | ) 67 | 68 | 69 | ; PART absFifo2 70 | (struct absFifo2 (buffer head tail history historyValid uninterF clk 71 | param-simuCycle2) 72 | #:mutable #:transparent 73 | #:methods gen:custom-write 74 | [(define (write-proc this port mode) 75 | (write-string (absFifo2->string this) port))] 76 | ) 77 | 78 | 79 | (define (init-absFifo2 absFifo2-cfg param-entry-len) 80 | (define param-timFct-len 81 | (absFifo2-cfg-param-timFct-len absFifo2-cfg)) 82 | (define param-simuCycle2 (absFifo2-cfg-param-simuCycle2 absFifo2-cfg)) 83 | (define param-simuCycle2-log 84 | (inexact->exact (ceiling (log param-simuCycle2 2)))) 85 | 86 | (absFifo2 87 | (initZeroVec-array param-simuCycle2 param-entry-len) 88 | (bv 0 param-simuCycle2-log) 89 | (bv 0 param-simuCycle2-log) 90 | (initZeroVec-array param-simuCycle2 param-timFct-len) 91 | (initZeroVec-array param-simuCycle2 1) 92 | (absFifo2-cfg-uninterF absFifo2-cfg) 93 | (bv 0 (- param-simuCycle2-log 1)) 94 | param-simuCycle2) 95 | ) 96 | 97 | 98 | (define (absFifo2-dataoutValid absFifo2) 99 | (define head (absFifo2-head absFifo2)) 100 | (define tail (absFifo2-tail absFifo2)) 101 | (define uninterF (absFifo2-uninterF absFifo2)) 102 | (define history (absFifo2-history absFifo2)) 103 | (define historyValid (absFifo2-historyValid absFifo2)) 104 | 105 | (define notEmpty (not (bveq head tail))) 106 | (define valid-bv (uninterF (concat (array->bv history) 107 | (array->bv historyValid)))) 108 | (list (and notEmpty (bitvector->bool (msb valid-bv))) 109 | (and notEmpty (bitvector->bool (lsb valid-bv)))) 110 | ) 111 | 112 | 113 | ; NOTE: each call to this function only outputs 1 data each time 114 | (define (dataout-absFifo2! absFifo2) 115 | (define buffer (absFifo2-buffer absFifo2)) 116 | (define head (absFifo2-head absFifo2)) 117 | 118 | (set-absFifo2-head! absFifo2 (bvadd1 head)) 119 | (array-ref buffer head) 120 | ) 121 | 122 | 123 | (define (absFifo2-datainReady absFifo2) (list #t #t)) 124 | 125 | 126 | ; NOTE: assume both input channels are valid 127 | (define (datain-absFifo2! absFifo2 datain-0 timFct-0 datain-1 timFct-1) 128 | (define buffer (absFifo2-buffer absFifo2)) 129 | (define tail (absFifo2-tail absFifo2)) 130 | (define history (absFifo2-history absFifo2)) 131 | (define historyValid (absFifo2-historyValid absFifo2)) 132 | (define clk (absFifo2-clk absFifo2)) 133 | 134 | (set-array! buffer tail datain-0) 135 | (set-array! buffer (bvadd1 tail) datain-1) 136 | (set-absFifo2-tail! absFifo2 (bvadd1 (bvadd1 tail))) 137 | (set-array! history (concat clk (bv 0 1)) timFct-0) 138 | (set-array! history (concat clk (bv 1 1)) timFct-1) 139 | (set-array! historyValid (concat clk (bv 0 1)) (bv 1 1)) 140 | (set-array! historyValid (concat clk (bv 1 1)) (bv 1 1)) 141 | ) 142 | 143 | 144 | (define (1cycleSquash-absFifo2! absFifo2) 145 | (define buffer (absFifo2-buffer absFifo2)) 146 | (define history (absFifo2-history absFifo2)) 147 | (define historyValid (absFifo2-historyValid absFifo2)) 148 | (define param-simuCycle2 (absFifo2-param-simuCycle2 absFifo2)) 149 | (define param-simuCycle2-log 150 | (inexact->exact (ceiling (log param-simuCycle2 2)))) 151 | 152 | (resetToZeroVec-array! buffer) 153 | (set-absFifo2-head! absFifo2 (bv 0 param-simuCycle2-log)) 154 | (set-absFifo2-tail! absFifo2 (bv 0 param-simuCycle2-log)) 155 | (resetToZeroVec-array! history) 156 | (resetToZeroVec-array! historyValid) 157 | ) 158 | 159 | 160 | (define (drainSquash-absFifo2! absFifo2) 161 | (define buffer (absFifo2-buffer absFifo2)) 162 | (define param-simuCycle2 (absFifo2-param-simuCycle2 absFifo2)) 163 | (define param-simuCycle2-log 164 | (inexact->exact (ceiling (log param-simuCycle2 2)))) 165 | 166 | (resetToZeroVec-array! buffer) 167 | (set-absFifo2-head! absFifo2 (bv 0 param-simuCycle2-log)) 168 | (set-absFifo2-tail! absFifo2 (bv 0 param-simuCycle2-log)) 169 | ) 170 | 171 | 172 | (define (tick-absFifo2! absFifo2) 173 | (define clk (absFifo2-clk absFifo2)) 174 | 175 | (set-absFifo2-clk! absFifo2 (bvadd1 clk)) 176 | ) 177 | 178 | 179 | (define (absFifo2->string absFifo2) 180 | (~a (absFifo2-historyValid absFifo2)) 181 | ) 182 | 183 | 184 | (define (testMe) 185 | 186 | (define absFifo2-cfg (init-absFifo2-cfg 2 10 "func_concrete")) 187 | (define absFifo2 (init-absFifo2 absFifo2-cfg 5)) 188 | (printf (~a absFifo2 "\n")) 189 | 190 | (printf (~a (absFifo2-dataoutValid absFifo2) "\n")) 191 | ;(printf (~a (dataout-absFifo2! absFifo2) "\n")) 192 | (printf (~a (absFifo2-datainReady absFifo2) "\n")) 193 | (printf (~a (datain-absFifo2! absFifo2 (bv 31 5) (bv 3 2)) "\n")) 194 | (printf (~a absFifo2 "\n")) 195 | 196 | (tick-absFifo2! absFifo2) 197 | (printf (~a "-----------------\n")) 198 | 199 | (printf (~a (absFifo2-dataoutValid absFifo2) "\n")) 200 | (printf (~a (dataout-absFifo2! absFifo2) "\n")) 201 | (printf (~a (absFifo2-datainReady absFifo2) "\n")) 202 | (printf (~a (datain-absFifo2! absFifo2 (bv 1 5) (bv 1 2)) "\n")) 203 | (printf (~a absFifo2 "\n")) 204 | ) 205 | ;(testMe) 206 | 207 | -------------------------------------------------------------------------------- /src/abs-module/brPred.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "../lib/lib.rkt" "../inst.rkt") 4 | 5 | (provide 6 | init-brPred-cfg brPred-cfg-evaluate init-brPred 7 | brPred-predict feedBrInfo-brPred! tick-brPred! 8 | ) 9 | 10 | 11 | ; PART brPred-cfg 12 | (struct brPred-cfg (uninterF param-brInfo-len param-simuCycle) 13 | #:mutable #:transparent 14 | #:methods gen:custom-write 15 | [(define (write-proc this port mode) 16 | (write-string (brPred-cfg->string this) port))] 17 | ) 18 | 19 | 20 | (define (init-brPred-cfg param-brInfo-len param-simuCycle param-symType) 21 | (brPred-cfg 22 | (cond 23 | [(equal? param-symType "func_concrete") 24 | (lambda (ignore) (bv 0 1))] 25 | 26 | [(equal? param-symType "func_sym") 27 | (build-unfuncbv (* param-simuCycle (add1 param-brInfo-len)) 1)]) 28 | param-brInfo-len 29 | param-simuCycle) 30 | ) 31 | 32 | 33 | (define (brPred-cfg-evaluate brPred-cfg-sym sol) 34 | (define uninterF (brPred-cfg-uninterF brPred-cfg-sym)) 35 | (define param-brInfo-len (brPred-cfg-param-brInfo-len brPred-cfg-sym)) 36 | (define param-simuCycle (brPred-cfg-param-simuCycle brPred-cfg-sym)) 37 | 38 | (brPred-cfg (evaluate uninterF sol) param-brInfo-len param-simuCycle) 39 | ) 40 | 41 | 42 | (define (brPred-cfg->string brPred-cfg) 43 | "brPred-cfg" 44 | ) 45 | 46 | 47 | ; PART brPred 48 | (struct brPred (history historyValid uninterF clk) 49 | #:mutable #:transparent 50 | ; #:methods gen:custom-write 51 | ; [(define (write-proc this port mode) 52 | ; (write-string (brPred->string this) port))] 53 | ) 54 | 55 | 56 | (define (init-brPred brPred-cfg) 57 | (define uninterF (brPred-cfg-uninterF brPred-cfg)) 58 | (define param-brInfo-len (brPred-cfg-param-brInfo-len brPred-cfg)) 59 | (define param-simuCycle (brPred-cfg-param-simuCycle brPred-cfg)) 60 | (define param-simuCycle-log 61 | (inexact->exact (ceiling (log param-simuCycle 2)))) 62 | 63 | (brPred 64 | (initZeroVec-array param-simuCycle param-brInfo-len) 65 | (initZeroVec-array param-simuCycle 1) 66 | uninterF 67 | (bv 0 param-simuCycle-log)) 68 | ) 69 | 70 | 71 | ;; NOTE: The feedBrInfo happens at the commit stage. 72 | ; So, it will happen before the brPred-predict 73 | (define (feedBrInfo-brPred! brPred brInfo) 74 | (define history (brPred-history brPred)) 75 | (define historyValid (brPred-historyValid brPred)) 76 | (define clk (brPred-clk brPred)) 77 | 78 | (set-array! history clk brInfo) 79 | (set-array! historyValid clk (bv 1 1)) 80 | ) 81 | 82 | 83 | (define (brPred-predict brPred) 84 | (define uninterF (brPred-uninterF brPred)) 85 | (define history (brPred-history brPred)) 86 | (define historyValid (brPred-history brPred)) 87 | 88 | (bitvector->bool (uninterF (concat (array->bv history) 89 | (array->bv historyValid)))) 90 | ) 91 | 92 | 93 | (define (tick-brPred! brPred) 94 | (define clk (brPred-clk brPred)) 95 | 96 | (set-brPred-clk! brPred (bvadd1 clk)) 97 | ) 98 | 99 | 100 | (define (testMe) 101 | 102 | (define brPred-cfg (init-brPred-cfg 2 10 "func_concrete")) 103 | (define brPred (init-brPred brPred-cfg)) 104 | (printf (~a brPred "\n")) 105 | 106 | (printf (~a (brPred-predict brPred) "\n")) 107 | (printf (~a (feedBrInfo-brPred! brPred (bv 3 2)) "\n")) 108 | (printf (~a brPred "\n")) 109 | 110 | (tick-brPred! brPred) 111 | (printf (~a "-----------------\n")) 112 | 113 | (printf (~a (brPred-predict brPred) "\n")) 114 | (printf (~a (feedBrInfo-brPred! brPred (bv 1 2)) "\n")) 115 | (printf (~a brPred "\n")) 116 | ) 117 | ;(testMe) 118 | 119 | -------------------------------------------------------------------------------- /src/decode.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "lib/lib.rkt" "sym-state/rf.rkt" "inst.rkt") 4 | (provide decode) 5 | 6 | 7 | ; feed in functions 8 | (define (decode inst pc rf memd) 9 | 10 | (define wen #f) 11 | (define addr (bv 0 param-rf-size-log)) 12 | (define data (bv 0 param-rf-size)) 13 | (define brjmp #f) 14 | (define taken #f) 15 | (define target (bv 0 param-memi-size-log)) 16 | (define mrd #f) 17 | (define mwt #f) 18 | (define maddr (bv 0 param-memd-size-log)) 19 | (define mdata (bv 0 param-rf-size)) 20 | 21 | (cond 22 | [(bveq inst-op-Li (inst-op inst)) 23 | (set! wen #t) 24 | (set! addr (inst-rd inst)) 25 | (set! data (inst-rs1 inst)) 26 | (set! brjmp #f) 27 | (set! mrd #f) 28 | (set! mwt #f) 29 | ] 30 | 31 | [(bveq inst-op-Add (inst-op inst)) 32 | (set! wen #t) 33 | (set! addr (inst-rd inst)) 34 | (set! data (bvadd (rf-ref rf (extract (sub1 param-rf-size-log) 0 (inst-rs1 inst))) 35 | (rf-ref rf (inst-rs2 inst)))) 36 | (set! brjmp #f) 37 | (set! mrd #f) 38 | (set! mwt #f) 39 | ] 40 | 41 | [(bveq inst-op-Mul (inst-op inst)) 42 | (set! wen #t) 43 | (set! addr (inst-rd inst)) 44 | (set! data (bvmul (rf-ref rf (extract (sub1 param-rf-size-log) 0 (inst-rs1 inst))) 45 | (rf-ref rf (inst-rs2 inst)))) 46 | (set! brjmp #f) 47 | (set! mrd #f) 48 | (set! mwt #f) 49 | ] 50 | 51 | [(bveq inst-op-Ld (inst-op inst)) 52 | (set! wen #t) 53 | (set! addr (inst-rd inst)) 54 | (set! brjmp #f) 55 | (set! mrd #t) 56 | (set! maddr (extract (sub1 param-memd-size-log) 0 57 | (rf-ref rf (extract (sub1 param-rf-size-log) 0 (inst-rs1 inst))))) 58 | (set! mwt #f) 59 | ] 60 | 61 | [(bveq inst-op-St (inst-op inst)) 62 | (set! wen #f) 63 | (set! brjmp #f) 64 | (set! mrd #f) 65 | (set! mwt #t) 66 | (set! maddr (extract (sub1 param-memd-size-log) 0 67 | (rf-ref rf (extract (sub1 param-rf-size-log) 0 (inst-rs1 inst))))) 68 | (set! mdata (rf-ref rf (inst-rs2 inst))) 69 | ] 70 | 71 | [(bveq inst-op-Br (inst-op inst)) 72 | (set! wen #f) 73 | (set! brjmp #t) 74 | (set! taken (bvzero? (rf-ref rf (inst-rs2 inst)))) 75 | (set! target (if taken 76 | (bvadd (extract (sub1 param-memi-size-log) 0 (inst-rs1 inst)) pc) 77 | (bvadd1 pc))) 78 | (set! mrd #f) 79 | (set! mwt #f) 80 | ] 81 | ) 82 | 83 | (list wen addr data 84 | brjmp taken target 85 | mrd mwt maddr mdata) 86 | ) 87 | 88 | -------------------------------------------------------------------------------- /src/inst.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "lib/lib.rkt") 4 | 5 | (provide 6 | inst-size inst-size-log inst-len 7 | inst-op-Li inst-op-Add inst-op-Mul 8 | inst-op-Ld inst-op-St inst-op-Br 9 | inst-useSt 10 | (struct-out inst) 11 | init-inst init-syminst bv->inst assume-inst inst-evaluate 12 | ) 13 | 14 | 15 | ; PART Parameters 16 | (define inst-size 6) 17 | (define inst-size-log (inexact->exact (ceiling (log inst-size 2)))) 18 | (define inst-size-bv (bv (sub1 inst-size) inst-size-log)) 19 | (define inst-useSt #f) 20 | (define inst-len 21 | (+ inst-size-log param-reg-len param-rf-size-log param-rf-size-log)) 22 | 23 | (define inst-op-Li (bv 0 inst-size-log)) 24 | (define inst-op-Add (bv 1 inst-size-log)) 25 | (define inst-op-Mul (bv 2 inst-size-log)) 26 | (define inst-op-Ld (bv 3 inst-size-log)) 27 | (define inst-op-St (bv 4 inst-size-log)) 28 | (define inst-op-Br (bv 5 inst-size-log)) 29 | 30 | 31 | ; PART inst 32 | (struct inst (op rs1 rs2 rd) 33 | #:mutable #:transparent 34 | #:methods gen:custom-write 35 | [(define (write-proc this port mode) 36 | (write-string (inst->string this) port))] 37 | ) 38 | 39 | 40 | (define (init-inst op rs1 rs2 rd) 41 | (inst op rs1 rs2 rd) 42 | ) 43 | 44 | 45 | (define (init-syminst) 46 | (define syminst 47 | (init-inst 48 | (build-symbv inst-size-log) 49 | (build-symbv param-reg-len) 50 | (build-symbv param-rf-size-log) 51 | (build-symbv param-rf-size-log) 52 | ) 53 | ) 54 | syminst 55 | ) 56 | 57 | 58 | (define (bv->inst bv) 59 | (define inst (init-inst 60 | (extract (sub1 (+ inst-size-log param-reg-len 61 | param-rf-size-log param-rf-size-log)) 62 | (+ param-reg-len param-rf-size-log param-rf-size-log) bv) 63 | (extract (sub1 (+ param-reg-len param-rf-size-log param-rf-size-log)) 64 | (+ param-rf-size-log param-rf-size-log) bv) 65 | (extract (sub1 (+ param-rf-size-log param-rf-size-log)) 66 | (+ param-rf-size-log) bv) 67 | (extract (sub1 param-rf-size-log) 68 | 0 bv) 69 | )) 70 | (assume-inst inst) 71 | inst 72 | ) 73 | 74 | 75 | (define (assume-inst inst) 76 | (assume (bvule (inst-op inst) inst-size-bv)) 77 | (when (not inst-useSt) 78 | (assume (not (bveq (inst-op inst) inst-op-St)))) 79 | ) 80 | 81 | 82 | (define (inst->string inst) 83 | (define rs1 (bitvector->natural (inst-rs1 inst))) 84 | (define rs1-rfIndex (bitvector->natural 85 | (extract (sub1 param-rf-size-log) 0 (inst-rs1 inst)))) 86 | (define rs1-brOffset (bitvector->natural 87 | (extract (sub1 param-memi-size-log) 0 (inst-rs1 inst)))) 88 | (define rs2 (bitvector->natural (inst-rs2 inst))) 89 | (define rd (bitvector->natural (inst-rd inst))) 90 | 91 | (cond 92 | [(term? (inst-op inst)) 93 | (~a "(" (inst-op inst) " " (inst-rs1 inst) " " 94 | (inst-rs2 inst) " " (inst-rd inst) ")") 95 | ] 96 | [(bveq inst-op-Li (inst-op inst)) 97 | (~a " Li " rs1 " " rs2 " " rd " : " 98 | "Reg[" rd "] <- " rs1) 99 | ] 100 | [(bveq inst-op-Add (inst-op inst)) 101 | (~a "Add " rs1 " " rs2 " " rd " : " 102 | "Reg[" rd "] <- Reg[" rs1-rfIndex "] + Reg[" rs2 "]") 103 | ] 104 | [(bveq inst-op-Mul (inst-op inst)) 105 | (~a "Mul " rs1 " " rs2 " " rd " : " 106 | "Reg[" rd "] <- Reg[" rs1-rfIndex "] * Reg[" rs2 "]") 107 | ] 108 | [(bveq inst-op-Ld (inst-op inst)) 109 | (~a " Ld " rs1 " " rs2 " " rd " : " 110 | "Reg[" rd "] <- Mem[Reg[" rs1-rfIndex "]]") 111 | ] 112 | [(bveq inst-op-St (inst-op inst)) 113 | (~a " St " rs1 " " rs2 " " rd " : " 114 | "Mem[Reg[" rs1-rfIndex "]] <- Reg[" rs2 "]") 115 | ] 116 | [(bveq inst-op-Br (inst-op inst)) 117 | (~a " Br " rs1 " " rs2 " " rd " : " 118 | "If (Reg[" rs2 "]==0) PC <- PC + " rs1-brOffset) 119 | ] 120 | [else 121 | (~a "unknown")] 122 | ) 123 | ) 124 | 125 | 126 | (define (inst-evaluate inst-sym sol) 127 | (init-inst (evaluate (inst-op inst-sym) sol) 128 | (evaluate (inst-rs1 inst-sym) sol) 129 | (evaluate (inst-rs2 inst-sym) sol) 130 | (evaluate (inst-rd inst-sym) sol)) 131 | ) 132 | 133 | -------------------------------------------------------------------------------- /src/lib/array.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (provide 4 | init-array initZeroVec-array initFalseVec-array initFromCopy-array 5 | array-ref set-array! array->bv array-equal resetToZero-array! 6 | resetToZeroVec-array! resetToFalseVec-array! resetToTrueVec-array! 7 | resetsym-bvVec-array! resetsym-boolVec-array! array-evaluate 8 | array->masked array->custom-string 9 | ) 10 | 11 | 12 | ; TODO save the param-len, element-evaluate 13 | (struct array (content param-size param-len) 14 | #:mutable #:transparent 15 | #:methods gen:custom-write 16 | [(define (write-proc this port mode) 17 | (write-string (array->string this) port))]) 18 | 19 | (define (vector-copy-lifted vector) 20 | (for/all ([v vector #:exhaustive]) (vector-copy v)) 21 | ) 22 | 23 | (define (init-array content param-size param-len) 24 | (array 25 | (if (vector? content) (vector-copy-lifted content) content) 26 | param-size 27 | param-len 28 | ) 29 | ) 30 | 31 | 32 | (define (initZeroVec-array param-size param-len) 33 | (array 34 | (make-vector param-size (bv 0 param-len)) 35 | param-size 36 | param-len 37 | ) 38 | ) 39 | 40 | 41 | (define (initFalseVec-array param-size) 42 | (array 43 | (make-vector param-size #f) 44 | param-size 45 | 1 46 | ) 47 | ) 48 | 49 | 50 | (define (initFromCopy-array copyFrom) 51 | (init-array 52 | (array-content copyFrom) 53 | (array-param-size copyFrom) 54 | (array-param-len copyFrom)) 55 | ) 56 | 57 | 58 | (define (array-ref array pos) 59 | (if (vector? (array-content array)) 60 | (vector-ref-bv (array-content array) pos) 61 | ((array-content array) pos) 62 | ) 63 | ) 64 | 65 | 66 | (define (set-array! array pos v) 67 | (if (vector? (array-content array)) 68 | (vector-set!-bv (array-content array) pos v) 69 | (begin 70 | (define temp (array-content array)) 71 | (set-array-content! array (lambda (x) (if (equal? pos x) v (temp x))))) 72 | ) 73 | ) 74 | 75 | 76 | (define (array->bv array) 77 | (define param-size (array-param-size array)) 78 | (define param-size-log (inexact->exact (ceiling (log param-size 2)))) 79 | 80 | (apply concat 81 | (build-list param-size 82 | (lambda (i) (array-ref array (bv (- param-size (+ i 1)) 83 | param-size-log))))) 84 | ) 85 | 86 | 87 | (define (array-equal array-1 array-2) 88 | (define param-size (array-param-size array-1)) 89 | (define param-size-log (inexact->exact (ceiling (log param-size 2)))) 90 | 91 | (define is-equal #t) 92 | (for ([i (in-range param-size)]) 93 | (define i-bv (integer->bitvector i (bitvector param-size-log))) 94 | (set! is-equal (and is-equal (equal? (array-ref array-1 i-bv) 95 | (array-ref array-2 i-bv)))) 96 | ) 97 | is-equal 98 | ) 99 | 100 | 101 | (define (resetToZero-array! array pos) 102 | (define param-len (array-param-len array)) 103 | 104 | (set-array! array pos (bv 0 param-len)) 105 | ) 106 | 107 | 108 | (define (resetToZeroVec-array! array) 109 | (define param-size (array-param-size array)) 110 | (define param-len (array-param-len array)) 111 | 112 | (set-array-content! array (make-vector param-size (bv 0 param-len))) 113 | ) 114 | 115 | 116 | (define (resetToFalseVec-array! array) 117 | (define param-size (array-param-size array)) 118 | 119 | (set-array-content! array (make-vector param-size #f)) 120 | ) 121 | 122 | 123 | (define (resetToTrueVec-array! array) 124 | (define param-size (array-param-size array)) 125 | 126 | (set-array-content! array (make-vector param-size #t)) 127 | ) 128 | 129 | 130 | (define (resetsym-bvVec-array! array) 131 | (define param-size (array-param-size array)) 132 | (define param-size-log (inexact->exact (ceiling (log param-size 2)))) 133 | (define param-len (array-param-len array)) 134 | 135 | (for ([i (in-range param-size)]) 136 | (define i-bv (integer->bitvector i (bitvector param-size-log))) 137 | 138 | (when (term? (array-ref array i-bv)) 139 | (define-symbolic* entry-new (bitvector param-len)) 140 | (assume (bveq entry-new (array-ref array i-bv))) 141 | (set-array! array i-bv entry-new))) 142 | ) 143 | 144 | 145 | (define (resetsym-boolVec-array! array) 146 | (define param-size (array-param-size array)) 147 | (define param-size-log (inexact->exact (ceiling (log param-size 2)))) 148 | 149 | (for ([i (in-range param-size)]) 150 | (define i-bv (integer->bitvector i (bitvector param-size-log))) 151 | 152 | (when (term? (array-ref array i-bv)) 153 | (define-symbolic* entry-new boolean?) 154 | (assume (equal? entry-new (array-ref array i-bv))) 155 | (set-array! array i-bv entry-new))) 156 | ) 157 | 158 | 159 | (define (array->masked array maskThisEntry) 160 | (define param-size (array-param-size array)) 161 | (define param-size-log (inexact->exact (ceiling (log param-size 2)))) 162 | 163 | (define array-masked (initFromCopy-array array)) 164 | (for ([i (in-range param-size)]) 165 | (define i-bv (integer->bitvector i (bitvector param-size-log))) 166 | (when (maskThisEntry i-bv) 167 | (resetToZero-array! array-masked i-bv))) 168 | array-masked 169 | ) 170 | 171 | 172 | (define (array->custom-string array indexEntry->string separator) 173 | (define param-size (array-param-size array)) 174 | (define param-size-log (inexact->exact (ceiling (log param-size 2)))) 175 | 176 | (define string (~a "(")) 177 | (for ([i (in-range param-size)]) 178 | (define i-bv (integer->bitvector i (bitvector param-size-log))) 179 | (define entry (array-ref array i-bv)) 180 | (set! string (~a string (indexEntry->string i-bv entry) separator)) 181 | ) 182 | (~a string ")") 183 | ) 184 | 185 | 186 | (define (array->string array) 187 | (array->custom-string array (lambda (i e) 188 | (if (bv? e) (bitvector->natural e) e)) " ") 189 | ) 190 | 191 | 192 | ; EXPLAIN: 193 | ; The function takes in an `array` containing many elements. 194 | ; Each element might a symbolic term. 195 | ; It also takes a `sol` (short for solution) that is returned from SMT solver 196 | ; representing a counterexample, which is basically a mapping from symbolic 197 | ; values to concrete values. 198 | ; The goal of this function is to return the concrete value of the `array` 199 | ; based on `sol`. 200 | ; The `element-evaluate` is a fucntion that takes in an element in the array 201 | ; and the solution, and return the concrete value of the element. 202 | ; Thus, this function apply `element-evaluate` on each element and collect 203 | ; the concrete value of each element. 204 | ; Then, it create a new array with these concrete values and return it. 205 | ; Finally, what is `element-evaluate`? If you check the place this function 206 | ; is called, `element-evaluate` is a function called `evaluate`, 207 | ; which is a in Rosette library that evaluate a single symbolic term. 208 | (define (array-evaluate array-sym element-evaluate sol) 209 | (define param-size (array-param-size array-sym)) 210 | (define param-size-log (inexact->exact (ceiling (log param-size 2)))) 211 | (define param-len (array-param-len array-sym)) 212 | 213 | ; EXPLAIN: 214 | ; The function takes the index `i`, uses it to index `array-sym` 215 | ; and gets a symbolic term. 216 | ; It then looks at the `sol` and find the concrete value of the symbolic term 217 | ; and return the concrete value. 218 | (define (index-evaluate i) 219 | (define i-bv (integer->bitvector i (bitvector param-size-log))) 220 | (element-evaluate (array-ref array-sym i-bv) sol) 221 | ) 222 | (array (build-vector param-size index-evaluate) param-size param-len) 223 | ) 224 | 225 | -------------------------------------------------------------------------------- /src/lib/bv.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (provide build-unfuncbv build-symbv) 4 | 5 | 6 | (define (build-unfuncbv from to) 7 | (define-symbolic* unfuncbv (~> (bitvector from) (bitvector to))) 8 | unfuncbv 9 | ) 10 | 11 | 12 | (define (build-symbv size) 13 | (define-symbolic* symbv (bitvector size)) 14 | symbv 15 | ) 16 | 17 | -------------------------------------------------------------------------------- /src/lib/debug/assert-debug-commitLog.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (provide assert-debug-commitLog) 4 | 5 | 6 | (define (assert-debug-commitLog log-ISASimulator log-CPU) 7 | (define len-CPU (length-bv log-CPU (bitvector 32))) 8 | 9 | (set! log-ISASimulator (take-bv log-ISASimulator len-CPU)) 10 | 11 | (define (assert-entry entry-0 entry-1) 12 | (if (equal? (bv 3 32) (length-bv entry-0 (bitvector 32))) 13 | (begin 14 | (assert (equal? (bv 3 32) (length-bv entry-1 (bitvector 32)))) 15 | (assert (bveq (first entry-0) (first entry-1))) 16 | (assert (bveq (second entry-0) (second entry-1))) 17 | (assert (bveq (third entry-0) (third entry-1)))) 18 | (begin 19 | (assert (equal? (bv 1 32) (length-bv entry-1 (bitvector 32)))) 20 | (assert (bveq (first entry-0) (first entry-1)))))) 21 | 22 | (for-each assert-entry log-ISASimulator log-CPU) 23 | ) 24 | 25 | -------------------------------------------------------------------------------- /src/lib/debug/buginfo.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | ; This is copy from serval project. 3 | 4 | (require (for-syntax syntax/parse)) 5 | (provide (all-defined-out)) 6 | 7 | (define target-spectre (make-parameter #f)) 8 | 9 | (define (concrete?) 10 | (vc-true? (vc))) 11 | 12 | (struct bug-info (file line message) #:transparent) 13 | 14 | (define bug-db (make-parameter null)) 15 | 16 | (define (clear-bug-info!) (bug-db null)) 17 | 18 | (define (bug-format info sol) 19 | (define message (bug-info-message info)) 20 | (define evaluated-message 21 | (cond 22 | [(string? message) message] 23 | [(procedure? message) (message sol)] 24 | [else ""])) 25 | (format "~a:~a ~a" 26 | (bug-info-file info) 27 | (bug-info-line info) 28 | evaluated-message)) 29 | 30 | (define-syntax (bug-assert stx) 31 | (with-syntax ([line (syntax-line stx)] 32 | [file (path->string (syntax-source stx))]) 33 | (syntax-parse stx 34 | [(_ condition:expr (~optional (~seq #:msg msg:expr))) 35 | #'(add-assert condition #:file file #:line line #:msg (~? msg #f))]))) 36 | 37 | (define-syntax (bug-on stx) 38 | (with-syntax ([line (syntax-line stx)] 39 | [file (syntax-source stx)]) 40 | (syntax-parse stx 41 | [(_ condition:expr (~optional (~seq #:msg msg:expr))) 42 | #'(add-assert (! condition) #:file file #:line line #:msg (~? msg #f))]))) 43 | 44 | (define-syntax (bug stx) 45 | (with-syntax ([line (syntax-line stx)] 46 | [file (syntax-source stx)]) 47 | (syntax-parse stx 48 | [(_ (~optional (~seq #:msg msg:expr))) 49 | #'(add-assert #f #:file file #:line line #:msg (~? msg #f))]))) 50 | 51 | (define (add-assert assertion #:file [file ""] #:line [line ""] #:msg [msg #f]) 52 | ; Create debug information. 53 | (define info (bug-info file line msg)) 54 | ; Extract current assumptions and assertions. 55 | (define asserts (vc-asserts (vc))) 56 | (define assumes (vc-assumes (vc))) 57 | ; Set vc to true to add debug info. If the assertion is false given prior assumptions and assertions, 58 | ; the expression evaluates to the debug info. Otherwise it evaluates to #f. 59 | (with-vc vc-true 60 | (bug-db (cons (if (&& asserts assumes (! assertion)) info #f) (bug-db)))) 61 | ; show a concrete message if this is trivially false 62 | (define msg-str (bug-format info (sat))) 63 | (assert assertion msg-str)) 64 | 65 | (define (get-bug-info model) 66 | ; We want all assertion violates which are not unions (indicating incomplete solution) 67 | ; and are not concretely #f. 68 | (filter (lambda (i) (and (not (union? i)) (not (false? i)))) (evaluate (bug-db) model))) 69 | 70 | -------------------------------------------------------------------------------- /src/lib/debug/debug.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "buginfo.rkt" "unittest.rkt" "assert-debug-commitLog.rkt") 4 | (provide (all-from-out "buginfo.rkt") (all-from-out "unittest.rkt") 5 | (all-from-out "assert-debug-commitLog.rkt")) 6 | 7 | 8 | (define (testMe) 9 | (define (get-bug) 10 | (define-symbolic a boolean?) 11 | (bug-assert a #:msg "hello world")) 12 | (define (get-bug2) 13 | (define-symbolic a boolean?) 14 | (bug-assert a #:msg (lambda (sol) (format "a is ~v" (evaluate a sol))))) 15 | 16 | (define (get-codebug) 17 | (define-symbolic a boolean?) 18 | (bug-assert a #:msg "hello world") 19 | (assume a) 20 | (assert a)) 21 | 22 | (define (get-countercase) 23 | (define-symbolic a boolean?) 24 | (assert a)) 25 | 26 | (define (get-countercase-bug) 27 | (define-symbolic a boolean?) 28 | (assert a) 29 | (bug-assert a #:msg "hello world")) 30 | 31 | (define (get-normal) 32 | (define-symbolic a boolean?) 33 | (assume a) 34 | (bug-assert a #:msg "hello world") 35 | (assert a)) 36 | 37 | 38 | (define bug-info-tests 39 | (test-suite+ 40 | "Tests for bug info" 41 | (test-case+ "get-bug-info" (get-bug)) 42 | (test-case+ "get-bug2-info" (get-bug2)) 43 | (test-case+ "get-codebug-info" (get-codebug)) 44 | (test-case+ "get-countercase-info" (get-countercase)) 45 | (test-case+ "get-countercase-bug-info" (get-countercase-bug)) 46 | (test-case+ "get-normal-info" (get-normal)))) 47 | 48 | (time (run-tests bug-info-tests)) 49 | ) 50 | 51 | ;(testMe) 52 | 53 | -------------------------------------------------------------------------------- /src/lib/debug/unittest.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | ; This is copy from serval project. 3 | 4 | (require "buginfo.rkt" rackunit rackunit/text-ui rosette/lib/roseunit) 5 | (provide (all-defined-out) run-tests (all-from-out rackunit) (all-from-out rosette/lib/roseunit)) 6 | 7 | (define returnValue (void)) 8 | 9 | 10 | (define quickcheck-max-success (make-parameter 100)) 11 | 12 | (define-simple-check (check-unsat? sol) (unsat? sol)) 13 | (define-simple-check (check-sat? sol) (sat? sol)) 14 | 15 | (define (color-string prefix s [out (current-output-port)]) 16 | (if (terminal-port? out) 17 | (string-append prefix s "\033[0m") 18 | s)) 19 | 20 | (define color-succ (curry color-string "\033[0;32m")) 21 | 22 | (define (verify/debug-proc proc) 23 | (parameterize ([current-bitwidth (current-bitwidth)] 24 | [current-solver (current-solver)]) 25 | (clear-bug-info!) 26 | (clear-vc!) 27 | (define result (with-vc vc-true (proc))) 28 | (when (failed? result) 29 | (printf "procedure exited abnormally.\n") 30 | (parameterize ([error-print-width 9999]) 31 | (displayln (exn-message (result-value result)))) 32 | (proc) ; Run it again to get information about the concrete failure. 33 | (raise (result-value result))) 34 | (define assocs (result-value result)) 35 | (define v (result-state result)) 36 | (define s (current-solver)) 37 | (solver-assert s (list (vc-assumes v) (! (vc-asserts v)))) 38 | (define model (solver-check s)) 39 | (solver-clear s) 40 | (define info null) 41 | (set! returnValue model) 42 | (when (sat? model) 43 | (when (list? assocs) 44 | (set! info (map (lambda (p) (make-check-info (car p) (evaluate (cdr p) model))) assocs))) 45 | (printf "Failed assertions:\n") 46 | (for ([bug (get-bug-info model)]) 47 | (displayln (bug-format bug model)))) 48 | (with-check-info* 49 | info 50 | (thunk (check-unsat? model))) 51 | model)) 52 | 53 | (define-syntax-rule (test-case+ name body ...) 54 | (test-case name (begin 55 | (clear-terms!) 56 | (printf "~a ~v\n" (color-succ "[ RUN ]") name) 57 | (define (proc) (begin body ...)) 58 | (define-values (result cpu-time real-time gc-time) (time-apply verify/debug-proc (list proc))) 59 | (printf "~a ~v (~vms cpu) (~vms real) (~v terms)\n" (color-succ "[ OK ]") name cpu-time real-time (terms-count))))) 60 | 61 | (define-syntax-rule (test-failure-case+ name body ...) 62 | (test-case name (begin 63 | (printf "~a ~v\n" (color-succ "[ RUN ]") name) 64 | (define (proc) (begin body ...)) 65 | (define-values (result cpu-time real-time gc-time) 66 | (time-apply (thunk* (check-exn exn:fail? (thunk (verify/debug-proc proc)))) null)) 67 | (printf "~a ~v (~v ms)\n" (color-succ "[ OK ]") name real-time)))) 68 | 69 | ; random testing 70 | 71 | ; generate a random value from a symbolic expression 72 | (define (arbitrary expr) 73 | (define syms (symbolics expr)) 74 | (define sol 75 | (for/hash [(v syms)] 76 | (values v (cond 77 | [(boolean? v) 78 | (zero? (random 2))] 79 | [(bv? v) 80 | (apply concat (build-list (bitvector-size (type-of v)) 81 | (lambda (x) (bv (random 2) 1))))])))) 82 | (evaluate expr (sat sol))) 83 | 84 | (define-syntax-rule (check-vc expr) 85 | (begin 86 | (let ([result (with-vc expr)]) 87 | (check-true (normal? result)) 88 | (let ([v (result-state result)]) 89 | (check-unsat? (verify (assert (vc-asserts v)))) 90 | (result-value result))))) 91 | 92 | (define-syntax-rule (quickcheck body ...) 93 | (let ([n (quickcheck-max-success)]) 94 | (for ([i (in-range n)]) 95 | body ...) 96 | (printf "+++ OK, passed ~a tests.\n" n))) 97 | 98 | -------------------------------------------------------------------------------- /src/lib/lib.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "array.rkt" 5 | "bv.rkt" 6 | "param.rkt" 7 | "debug/debug.rkt" 8 | ) 9 | 10 | (provide 11 | (all-from-out "array.rkt") 12 | (all-from-out "bv.rkt") 13 | (all-from-out "param.rkt") 14 | (all-from-out "debug/debug.rkt") 15 | ) 16 | 17 | -------------------------------------------------------------------------------- /src/lib/param.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require rosette/solver/smt/z3 rosette/solver/smt/boolector) 4 | (provide (all-defined-out)) 5 | 6 | 7 | ; PART symbolic value type 8 | (define param-rf-symType "vec_sym") ; vec_concrete, vec_sym, 9 | ; func_concrete, func_sym 10 | (define param-memi-symType "func_sym") ; vec_concrete, vec_sym, func_sym 11 | (define param-memd-symType "func_sym") ; vec_concrete, vec_sym, func_sym 12 | 13 | (define param-adder-symType "func_sym") ; func_concrete, func_sym 14 | (define param-muler-symType "func_sym") ; func_concrete, func_sym 15 | (define param-Dcache-symType "func_sym") ; func_concrete, func_sym 16 | 17 | (define param-brPred-symType "func_sym") ; func_concrete, func_sym 18 | (define param-FDelay-symType "func_sym") ; func_concrete, func_sym 19 | 20 | 21 | 22 | ; PART Architecture 23 | (define param-rf-size 4) 24 | (define param-reg-len 4) 25 | (define param-memi-size 16) 26 | (define param-memd-size 4) 27 | 28 | 29 | 30 | 31 | ; PART Micro-architecture 32 | (define param-ROB-size 16) 33 | (define param-brInfo-len 1) 34 | (define param-enable-execute-squash #f) 35 | (define param-cache-useHit #f) 36 | 37 | 38 | 39 | 40 | ; PART: Observation Model 41 | (define param-obsvType "memTrace") ; memTrace, cacheState, commitPC 42 | 43 | 44 | 45 | 46 | ; PART: Defenses 47 | (define param-enable-DoM #f) 48 | (define param-enable-invisiSpec #f) 49 | (define param-enable-arbiterPriority #f) 50 | (define param-enable-GhostMinion #f) 51 | 52 | 53 | 54 | 55 | ; STEP Timing Factor 56 | ; Note: use 1 to mean no timing factor 57 | (define param-adder-timFct-len 1) 58 | (define param-muler-timFct-len 1) 59 | 60 | 61 | 62 | 63 | ; STEP Simulation 64 | (define param-CPU-simuCycle 4) ; 4 for spectre 65 | 66 | 67 | 68 | ; PART Symbolic Optimization 69 | (define param-ISASimulator-resetsym-cycle 16) 70 | (define param-CPU-resetsym-cycle 16) 71 | 72 | (current-solver (boolector)) ; z3, boolector 73 | 74 | 75 | 76 | ; STEP Debug 77 | (define param-debug-commitLog-on #t) 78 | (define param-debug-assert #t) 79 | (error-print-width 1000) 80 | 81 | 82 | 83 | 84 | ; STEP Saved params here 85 | (define param-saved-params "None") 86 | (define param-saved-sizes "None") 87 | 88 | 89 | 90 | 91 | ; STEP Override from command line 92 | (command-line 93 | #:once-each 94 | [("--param-debug-assert") v "param-debug-assert" 95 | (set! param-debug-assert (equal? 1 (string->number v)))] 96 | 97 | [("--param-enable-execute-squash") v "param-enable-execute-squash" 98 | (set! param-enable-execute-squash (equal? 1 (string->number v)))] 99 | 100 | [("--param-obsvType") v "param-obsvType" 101 | (set! param-obsvType v)] 102 | 103 | [("--param-cache-useHit") v "param-cache-useHit" 104 | (set! param-cache-useHit (equal? 1 (string->number v)))] 105 | [("--param-enable-DoM") v "param-enable-DoM" 106 | (set! param-enable-DoM (equal? 1 (string->number v)))] 107 | [("--param-enable-invisiSpec") v "param-enable-invisiSpec" 108 | (set! param-enable-invisiSpec (equal? 1 (string->number v)))] 109 | [("--param-enable-arbiterPriority") v "param-enable-arbiterPriority" 110 | (set! param-enable-arbiterPriority (equal? 1 (string->number v)))] 111 | [("--param-enable-GhostMinion") v "param-enable-GhostMinion" 112 | (set! param-enable-GhostMinion (equal? 1 (string->number v)))] 113 | 114 | [("--param-ROB-size") v "param-ROB-size" 115 | (set! param-ROB-size (string->number v))] 116 | [("--param-CPU-simuCycle") v "param-CPU-simuCycle" 117 | (set! param-CPU-simuCycle (string->number v))] 118 | 119 | [("--param-saved-params") v "param-saved-params" 120 | (set! param-saved-params v)] 121 | 122 | [("--param-saved-sizes") v "param-saved-sizes" 123 | (set! param-saved-sizes v)] 124 | ) 125 | 126 | 127 | 128 | 129 | ; STEP Saved params here 130 | (cond 131 | [(equal? param-saved-params "spectre") 132 | (void) 133 | ] 134 | 135 | [(equal? param-saved-params "DoM") 136 | (set! param-cache-useHit #t) 137 | (set! param-enable-DoM #t) 138 | ] 139 | 140 | [(equal? param-saved-params "DoM_arbiterPriority") 141 | (set! param-cache-useHit #t) 142 | (set! param-enable-DoM #t) 143 | (set! param-enable-arbiterPriority #t) 144 | ] 145 | 146 | [(equal? param-saved-params "invisiSpec") 147 | (set! param-obsvType "cacheState") 148 | (set! param-cache-useHit #t) 149 | (set! param-enable-invisiSpec #t) 150 | ] 151 | 152 | [(equal? param-saved-params "invisiSpec_arbiterPriority") 153 | (set! param-obsvType "cacheState") 154 | (set! param-cache-useHit #t) 155 | (set! param-enable-invisiSpec #t) 156 | (set! param-enable-arbiterPriority #t) 157 | ] 158 | 159 | [(equal? param-saved-params "GhostMinion") 160 | (set! param-obsvType "cacheState") 161 | (set! param-cache-useHit #t) 162 | (set! param-enable-invisiSpec #t) 163 | (set! param-enable-arbiterPriority #t) 164 | (set! param-enable-GhostMinion #t) 165 | ] 166 | ) 167 | 168 | (cond 169 | [(equal? param-saved-sizes "spectre") 170 | ; find attack ~10s 171 | (void) 172 | ] 173 | 174 | [(equal? param-saved-sizes "DoM") 175 | ; find attack ~10s 176 | (void) 177 | ] 178 | 179 | [(equal? param-saved-sizes "DoM_arbiterPriority") 180 | ; find attack ~1200s 181 | (set! param-ROB-size 8) 182 | (set! param-CPU-simuCycle 7) 183 | ] 184 | 185 | [(equal? param-saved-sizes "invisiSpec") 186 | ; find attack ~10s 187 | (void) 188 | ] 189 | 190 | [(equal? param-saved-sizes "invisiSpec_arbiterPriority") 191 | ; find attack ~200s 192 | (set! param-CPU-simuCycle 6) 193 | ] 194 | 195 | [(equal? param-saved-sizes "GhostMinion") 196 | ; find attack ~400s 197 | (set! param-ROB-size 4) 198 | (set! param-CPU-simuCycle 8) 199 | ] 200 | ) 201 | 202 | 203 | 204 | 205 | ; STEP: Computed parameters 206 | (define param-rf-size-log (inexact->exact (log param-rf-size 2))) 207 | (define param-memi-size-log (inexact->exact (log param-memi-size 2))) 208 | (define param-memd-size-log (inexact->exact (log param-memd-size 2))) 209 | 210 | (define param-ROB-size-log (inexact->exact (log param-ROB-size 2))) 211 | 212 | (define param-Dcache-timFct-len param-memd-size-log) 213 | (define param-FDelay-timFct-len param-memi-size-log) 214 | 215 | (define param-CPU-simuCycle-bv 216 | (bv (sub1 param-CPU-simuCycle) 217 | (inexact->exact (ceiling (log param-CPU-simuCycle 2))))) 218 | 219 | (define param-EXinst-size (* 2 (- param-CPU-simuCycle 2))) 220 | (define param-EXinst-size-log 221 | (inexact->exact (ceiling (log param-EXinst-size 2)))) 222 | 223 | (define param-brID-len param-EXinst-size-log) 224 | 225 | (define param-ISASimulator-simuCycle param-EXinst-size) 226 | (define param-ISASimulator-simuCycle-bv 227 | (bv (sub1 param-ISASimulator-simuCycle) param-EXinst-size-log)) 228 | 229 | 230 | 231 | 232 | ; STEP: Constrains on the parameters 233 | (when (equal? param-obsvType "cacheState") (assert param-cache-useHit)) 234 | 235 | (when param-enable-DoM (assert param-cache-useHit)) 236 | 237 | (when param-enable-invisiSpec (assert param-cache-useHit) 238 | (equal? param-obsvType "cacheState") 239 | (assert (not param-enable-DoM))) 240 | (when param-enable-GhostMinion (assert param-enable-invisiSpec) 241 | (assert param-enable-arbiterPriority)) 242 | 243 | -------------------------------------------------------------------------------- /src/main_veriCorr.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "ISASimulator.rkt" "CPU/CPU.rkt" 5 | "sym-state/rf.rkt" "sym-state/memi.rkt" "sym-state/memd.rkt" 6 | "abs-module/brPred.rkt" "abs-module/absFifo2.rkt" "CPU/alu.rkt" 7 | "CPU/cache.rkt" "lib/lib.rkt" 8 | ) 9 | 10 | 11 | (define (simu ISASimulator-cfg CPU-cfg param-debug-print-on) 12 | (define ISASimulator (init-ISASimulator 13 | ISASimulator-cfg param-ISASimulator-simuCycle 14 | param-ISASimulator-resetsym-cycle param-debug-print-on)) 15 | (define CPU (init-CPU 16 | CPU-cfg 17 | param-CPU-simuCycle param-CPU-resetsym-cycle param-debug-print-on)) 18 | 19 | (simu-ISASimulator! ISASimulator param-ISASimulator-simuCycle-bv) 20 | (simu-CPU! CPU param-CPU-simuCycle-bv) 21 | 22 | (list ISASimulator CPU) 23 | ) 24 | 25 | (define ISASimulator-cfg (void)) 26 | (define CPU-cfg (void)) 27 | 28 | 29 | (define (veriCorr) 30 | 31 | (match-define (list ISASimulator-cfg-0 ISASimulator-cfg-1) 32 | (init-ISASimulator-cfg-pair)) 33 | (match-define (list CPU-cfg-0 CPU-cfg-1) 34 | (init-CPU-cfg-pair ISASimulator-cfg-0 ISASimulator-cfg-1)) 35 | 36 | (set! ISASimulator-cfg ISASimulator-cfg-0) 37 | (set! CPU-cfg CPU-cfg-0) 38 | 39 | (match-define (list ISASimulator CPU) (simu ISASimulator-cfg-0 CPU-cfg-0 #f)) 40 | 41 | (printf (~a "Finish Generating SMT Formulas.\n")) 42 | 43 | 44 | 45 | (define sol (verify (assert-debug-commitLog 46 | (ISASimulator-debug-commitLog ISASimulator) 47 | (CPU-debug-commitLog CPU)))) 48 | 49 | (when (sat? sol) 50 | (printf (~a "Find Counterexample.\n")) 51 | 52 | (set! ISASimulator-cfg-0 (ISASimulator-cfg-evaluate ISASimulator-cfg-0 sol)) 53 | (set! ISASimulator-cfg-1 (ISASimulator-cfg-evaluate ISASimulator-cfg-1 sol)) 54 | (set! CPU-cfg-0 (CPU-cfg-evaluate CPU-cfg-0 sol)) 55 | (set! CPU-cfg-1 (CPU-cfg-evaluate CPU-cfg-1 sol)) 56 | 57 | (match-define (list t0 t1) (simu ISASimulator-cfg-0 CPU-cfg-0 #t)) 58 | (set! ISASimulator t0) 59 | (set! CPU t1) 60 | 61 | 62 | (printf (~a "Finish SMT Result Evaluation.\n")) 63 | 64 | (printf (~a 65 | "cfg: " ISASimulator-cfg-0 "\n" 66 | "ISASimulator: " ISASimulator "\n" 67 | "CPU: " CPU "\n" 68 | )) 69 | ) 70 | 71 | (when (not (sat? sol)) (printf (~a "No Counterexample.\n"))) 72 | ) 73 | 74 | 75 | (define (testMe) 76 | (if param-debug-assert 77 | (begin 78 | (define veri-secu-test 79 | (test-suite+ "Tests for veriCorr" 80 | (test-case+ "get-bug-info" (veriCorr)))) 81 | (time (run-tests veri-secu-test)) 82 | (when (sat? returnValue) 83 | (println returnValue) 84 | (printf (~a "cfg: " (ISASimulator-cfg-evaluate ISASimulator-cfg returnValue) "\n")) 85 | (simu (ISASimulator-cfg-evaluate ISASimulator-cfg returnValue) (CPU-cfg-evaluate CPU-cfg returnValue) #t) 86 | ) 87 | ) 88 | (time (veriCorr))) 89 | ) 90 | (testMe) 91 | 92 | -------------------------------------------------------------------------------- /src/main_veriSpec.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require 4 | "ISASimulator.rkt" "CPU/CPU.rkt" 5 | "sym-state/rf.rkt" "sym-state/memi.rkt" "sym-state/memd.rkt" 6 | "abs-module/brPred.rkt" "abs-module/absFifo2.rkt" "CPU/alu.rkt" 7 | "CPU/cache.rkt" "lib/lib.rkt" 8 | ) 9 | 10 | 11 | (define (simu ISASimulator-cfg CPU-cfg param-debug-print-on) 12 | (define ISASimulator (init-ISASimulator 13 | ISASimulator-cfg param-ISASimulator-simuCycle 14 | param-ISASimulator-resetsym-cycle param-debug-print-on)) 15 | (define CPU (init-CPU 16 | CPU-cfg 17 | param-CPU-simuCycle param-CPU-resetsym-cycle param-debug-print-on)) 18 | 19 | (simu-ISASimulator! ISASimulator param-ISASimulator-simuCycle-bv) 20 | (simu-CPU! CPU param-CPU-simuCycle-bv) 21 | 22 | (list ISASimulator CPU) 23 | ) 24 | 25 | 26 | (define (veriSpec) 27 | 28 | ; STEP Initialize Symbolic Values 29 | (match-define (list ISASimulator-cfg-0 ISASimulator-cfg-1) 30 | (init-ISASimulator-cfg-pair)) 31 | (match-define (list CPU-cfg-0 CPU-cfg-1) 32 | (init-CPU-cfg-pair ISASimulator-cfg-0 ISASimulator-cfg-1)) 33 | 34 | 35 | ; STEP Simu the 4 copies 36 | (match-define (list ISASimulator-0 CPU-0) 37 | (simu ISASimulator-cfg-0 CPU-cfg-0 #f)) 38 | (match-define (list ISASimulator-1 CPU-1) 39 | (simu ISASimulator-cfg-1 CPU-cfg-1 #f)) 40 | (printf (~a "Finish Symbolic Execution.\n")) 41 | 42 | 43 | ; STEP Assume 44 | (assume-ISASimulator-memTrace (ISASimulator-memTrace ISASimulator-0) 45 | (ISASimulator-memTrace ISASimulator-1)) 46 | 47 | 48 | ; STEP Assert 49 | (define sol (verify (assert-CPU-obsv (CPU-obsv CPU-0) (CPU-obsv CPU-1)))) 50 | (printf (~a "Finish STM Solver.\n")) 51 | 52 | 53 | ; STEP Output Counter Example 54 | (when (sat? sol) 55 | (printf (~a "Find Counterexample.\n")) 56 | 57 | (set! ISASimulator-cfg-0 (ISASimulator-cfg-evaluate ISASimulator-cfg-0 sol)) 58 | (set! ISASimulator-cfg-1 (ISASimulator-cfg-evaluate ISASimulator-cfg-1 sol)) 59 | (set! CPU-cfg-0 (CPU-cfg-evaluate CPU-cfg-0 sol)) 60 | (set! CPU-cfg-1 (CPU-cfg-evaluate CPU-cfg-1 sol)) 61 | 62 | (printf (~a "\n")) 63 | (printf (~a "\n")) 64 | (printf (~a "**************************\n")) 65 | (printf (~a "Simulate CPU with Secret 0\n")) 66 | (printf (~a "**************************\n")) 67 | (match-define (list t0 t1) (simu ISASimulator-cfg-0 CPU-cfg-0 #t)) 68 | (printf (~a "\n")) 69 | (printf (~a "**************************\n")) 70 | (printf (~a "Simulate CPU with Secret 1\n")) 71 | (printf (~a "**************************\n")) 72 | (match-define (list t2 t3) (simu ISASimulator-cfg-1 CPU-cfg-1 #t)) 73 | (set! ISASimulator-0 t0) 74 | (set! CPU-0 t1) 75 | (set! ISASimulator-1 t2) 76 | (set! CPU-1 t3) 77 | 78 | 79 | (printf (~a "\n")) 80 | (printf (~a "*****************************\n")) 81 | (printf (~a "Finish SMT Result Evaluation.\n")) 82 | (printf (~a "*****************************\n")) 83 | 84 | (printf (~a 85 | "******Init State******\n" (ISASimulator-cfg-pair->string 86 | ISASimulator-cfg-0 ISASimulator-cfg-1) "\n" 87 | "******ISASimulator-0******\n" ISASimulator-0 "\n" 88 | "******ISASimulator-1******\n" ISASimulator-1 "\n" 89 | "******CPU-0******\n" CPU-0 "\n" 90 | "******CPU-1******\n" CPU-1 "\n" 91 | )) 92 | ) 93 | 94 | (when (not (sat? sol)) (printf (~a "No Counterexample.\n"))) 95 | ) 96 | 97 | 98 | (define (testMe) 99 | (if param-debug-assert 100 | (begin 101 | (define veri-secu-test 102 | (test-suite+ "Tests for veriSpec" 103 | (test-case+ "get-bug-info" (veriSpec)))) 104 | (time (run-tests veri-secu-test))) 105 | (time (veriSpec))) 106 | ) 107 | (testMe) 108 | 109 | -------------------------------------------------------------------------------- /src/sym-state/mem.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "memi.rkt" "memd.rkt" "../lib/lib.rkt") 4 | (provide mem-ref logref-mem! set-mem! logset-mem! tick-mem!) 5 | 6 | 7 | (define (mem-ref . arg) 8 | (cond 9 | [(memi? (car arg)) (apply memi-ref arg)] 10 | [(memd? (car arg)) (apply memd-ref arg)] 11 | [else (bug-assert #f #:msg "mem unknown")]) 12 | ) 13 | 14 | 15 | (define (logref-mem! . arg) 16 | (cond 17 | [(memi? (car arg)) (apply logref-memi! arg)] 18 | [(memd? (car arg)) (apply logref-memd! arg)] 19 | [else (bug-assert #f #:msg "mem unknown")]) 20 | ) 21 | 22 | 23 | (define (set-mem! . arg) 24 | (cond 25 | [(memd? (car arg)) (apply set-memd! arg)] 26 | [else (bug-assert #f #:msg "mem unknown")]) 27 | ) 28 | 29 | 30 | (define (logset-mem! . arg) 31 | (cond 32 | [(memd? (car arg)) (apply logset-memd! arg)] 33 | [else (bug-assert #f #:msg "mem unknown")]) 34 | ) 35 | 36 | 37 | (define (tick-mem! . arg) 38 | (cond 39 | [(memi? (car arg)) (apply tick-memi! arg)] 40 | [(memd? (car arg)) (apply tick-memd! arg)] 41 | [else (bug-assert #f #:msg "mem unknown")]) 42 | ) 43 | 44 | -------------------------------------------------------------------------------- /src/sym-state/memd.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "../lib/lib.rkt") 4 | (provide 5 | init-memd-cfg-pair memd-cfg-evaluate 6 | init-memd memd-ref logref-memd! set-memd! logset-memd! tick-memd! 7 | memd-history->string memd-history 8 | memd? 9 | ) 10 | 11 | 12 | (define param-sec-len 1) 13 | 14 | 15 | ; module memd ( 16 | ; input datain; 17 | ; input addr; 18 | ; input valid; 19 | 20 | ; output dataout; 21 | ; ) 22 | 23 | 24 | ; PART memd-cfg 25 | (struct memd-cfg (array param-size) 26 | #:mutable #:transparent 27 | #:methods gen:custom-write 28 | [(define (write-proc this port mode) 29 | (write-string (memd-cfg->string this) port))] 30 | ) 31 | 32 | 33 | (define (init-memd-cfg-pair param-size param-len param-symType) 34 | (define param-size-log (inexact->exact (log param-size 2))) 35 | 36 | (match-define (list array-0 array-1) 37 | (cond 38 | [(equal? param-symType "vec_concrete") 39 | (list 40 | (init-array (vector (bv 0 param-len) 41 | (bv 0 param-len) 42 | (bv 0 param-len) 43 | (bv 0 param-len)) 44 | param-size 45 | param-len) 46 | (init-array (vector (bv 1 param-len) 47 | (bv 0 param-len) 48 | (bv 0 param-len) 49 | (bv 0 param-len)) 50 | param-size 51 | param-len))] 52 | 53 | [(equal? param-symType "vec_sym") 54 | (define array-pubbit (build-symbv (- param-len param-sec-len))) 55 | (define array-secbit (build-symbv param-sec-len)) 56 | (define array-secentry-0 (concat array-pubbit array-secbit)) 57 | (define array-secentry-1 (concat array-pubbit (bvnot array-secbit))) 58 | (define array-pubentries (build-vector 59 | (sub1 param-size) 60 | (lambda (ignore) (build-symbv param-len)))) 61 | 62 | (list 63 | (init-array (vector-append (vector array-secentry-0) 64 | array-pubentries) 65 | param-size 66 | param-len) 67 | (init-array (vector-append (vector array-secentry-1) 68 | array-pubentries) 69 | param-size 70 | param-len))] 71 | 72 | [(equal? param-symType "func_sym") 73 | (define array-secbit (build-symbv param-sec-len)) 74 | (define array-pub (build-unfuncbv param-size-log param-len)) 75 | (list 76 | (init-array 77 | (lambda (x) (if (bvzero? x) 78 | (concat (extract (sub1 param-len) param-sec-len (array-pub x)) 79 | array-secbit) 80 | (array-pub x))) 81 | param-size 82 | param-len) 83 | (init-array 84 | (lambda (x) (if (bvzero? x) 85 | (concat (extract (sub1 param-len) param-sec-len (array-pub x)) 86 | (bvnot array-secbit)) 87 | (array-pub x))) 88 | param-size 89 | param-len))] 90 | 91 | [else (bug-assert #f #:msg "memd: param-symType unknown")])) 92 | 93 | (list (memd-cfg array-0 param-size) 94 | (memd-cfg array-1 param-size)) 95 | ) 96 | 97 | 98 | (define (memd-cfg-evaluate memd-cfg-sym sol) 99 | (define array (memd-cfg-array memd-cfg-sym)) 100 | (define param-size (memd-cfg-param-size memd-cfg-sym)) 101 | 102 | (memd-cfg (array-evaluate array evaluate sol) param-size) 103 | ) 104 | 105 | 106 | (define (memd-cfg->string memd-cfg) 107 | (define array (memd-cfg-array memd-cfg)) 108 | 109 | (array->custom-string array (lambda (i e) (bitvector->natural e)) " ") 110 | ) 111 | 112 | 113 | ; PART memd 114 | (struct memd (array history clk param-size param-simuCycle) 115 | #:mutable #:transparent 116 | #:methods gen:custom-write 117 | [(define (write-proc this port mode) 118 | (write-string (memd->string this) port))] 119 | ) 120 | 121 | 122 | (define (init-memd memd-cfg param-simuCycle) 123 | (define array (memd-cfg-array memd-cfg)) 124 | (define param-size (memd-cfg-param-size memd-cfg)) 125 | (define param-size-log (inexact->exact (ceiling (log param-size 2)))) 126 | (define param-simuCycle-log 127 | (inexact->exact (ceiling (log param-simuCycle 2)))) 128 | 129 | (memd 130 | (initFromCopy-array array) 131 | (initZeroVec-array param-simuCycle (add1 param-size-log)) 132 | (bv 0 param-simuCycle-log) 133 | param-size 134 | param-simuCycle) 135 | ) 136 | 137 | 138 | (define (memd-ref memd pos) 139 | (define array (memd-array memd)) 140 | 141 | (array-ref array pos) 142 | ) 143 | 144 | 145 | (define (logref-memd! memd pos) 146 | (define history (memd-history memd)) 147 | (define clk (memd-clk memd)) 148 | 149 | (set-array! history clk (concat (bv 1 1) pos)) 150 | (memd-ref memd pos) 151 | ) 152 | 153 | 154 | (define (set-memd! memd pos v) 155 | (define array (memd-array memd)) 156 | 157 | (set-array! array pos v) 158 | ) 159 | 160 | 161 | (define (logset-memd! memd pos v) 162 | (define history (memd-history memd)) 163 | (define clk (memd-clk memd)) 164 | 165 | (set-array! history clk (concat (bv 1 1) pos)) 166 | (set-memd! memd pos v) 167 | ) 168 | 169 | 170 | (define (tick-memd! memd) 171 | (define clk (memd-clk memd)) 172 | 173 | (set-memd-clk! memd (bvadd1 clk)) 174 | ) 175 | 176 | 177 | (define (memd-history->string memd) 178 | (define history (memd-history memd)) 179 | (define param-size (memd-param-size memd)) 180 | (define param-size-log (inexact->exact (ceiling (log param-size 2)))) 181 | 182 | (define (indexEntry->string index entry) 183 | (define valid (extract param-size-log param-size-log entry)) 184 | (define addr (extract (sub1 param-size-log) 0 entry)) 185 | (if (bveq valid (bv 1 1)) 186 | (~a (bitvector->natural index) ": " (bitvector->natural addr) ", ") 187 | "") 188 | ) 189 | 190 | (array->custom-string history indexEntry->string "") 191 | ) 192 | 193 | 194 | (define (memd-array->string memd) 195 | (define array (memd-array memd)) 196 | 197 | (array->custom-string array (lambda (i e) (bitvector->natural e)) " ") 198 | ) 199 | 200 | 201 | (define (memd->string memd) 202 | (~a "history: " (memd-history->string memd) " " 203 | "array: " (memd-array->string memd)) 204 | ) 205 | 206 | 207 | (define (testMe) 208 | 209 | (match-define (list memd-cfg-0 memd-cfg-1) 210 | (init-memd-cfg-pair param-memd-size param-reg-len 211 | "vec_concrete")) 212 | (define memd (init-memd memd-cfg-0 10)) 213 | (printf (~a memd "\n")) 214 | 215 | (printf (~a (logref-memd! memd (bv 1 2)) "\n")) 216 | (printf (~a (logset-memd! memd (bv 1 2) (bv 7 param-reg-len)) "\n")) 217 | (printf (~a memd "\n")) 218 | 219 | (tick-memd! memd) 220 | 221 | (printf (~a (logref-memd! memd (bv 1 2)) "\n")) 222 | (printf (~a (logset-memd! memd (bv 0 2) (bv 3 param-reg-len)) "\n")) 223 | (printf (~a memd "\n")) 224 | ) 225 | ;(testMe) 226 | 227 | -------------------------------------------------------------------------------- /src/sym-state/memi.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "../lib/lib.rkt" "../inst.rkt") 4 | (provide 5 | init-memi-cfg memi-cfg-evaluate 6 | init-memi memi-ref logref-memi! tick-memi! memi-history->string memi-history 7 | memi? 8 | ) 9 | 10 | 11 | ; module memi ( 12 | ; input addr; 13 | ; output dataout; 14 | ; ) 15 | 16 | 17 | ; PART memi-cfg 18 | (struct memi-cfg (array param-size) 19 | #:mutable #:transparent 20 | #:methods gen:custom-write 21 | [(define (write-proc this port mode) 22 | (write-string (memi-cfg->string this) port))] 23 | ) 24 | 25 | 26 | (define (init-memi-cfg param-size param-rs1-len param-rs2-len param-rd-len 27 | param-symType) 28 | (define param-size-log (inexact->exact (log param-size 2))) 29 | (define param-len (+ inst-size-log param-rs1-len param-rs2-len param-rd-len)) 30 | 31 | (define array 32 | (cond 33 | [(equal? param-symType "vec_concrete") 34 | (define (initFromInt-inst op rs1 rs2 rd) (init-inst 35 | op 36 | (integer->bitvector rs1 (bitvector param-rs1-len)) 37 | (integer->bitvector rs2 (bitvector param-rs2-len)) 38 | (integer->bitvector rd (bitvector param-rd-len)))) 39 | (init-array 40 | (vector-immutable 41 | (initFromInt-inst inst-op-Ld 0 0 0) 42 | (initFromInt-inst inst-op-Add 1 1 1) 43 | (initFromInt-inst inst-op-Br 2 1 0) 44 | (initFromInt-inst inst-op-Ld 0 0 0) 45 | (initFromInt-inst inst-op-Ld 2 0 2) 46 | (initFromInt-inst inst-op-Li 0 0 0) 47 | (initFromInt-inst inst-op-Li 0 0 0) 48 | (initFromInt-inst inst-op-Li 0 0 0) 49 | (initFromInt-inst inst-op-Li 0 0 0) 50 | (initFromInt-inst inst-op-Li 0 0 0) 51 | (initFromInt-inst inst-op-Li 0 0 0) 52 | (initFromInt-inst inst-op-Li 0 0 0) 53 | (initFromInt-inst inst-op-Li 0 0 0) 54 | (initFromInt-inst inst-op-Li 0 0 0) 55 | (initFromInt-inst inst-op-Li 0 0 0) 56 | (initFromInt-inst inst-op-Li 0 0 0)) 57 | param-size 58 | param-len)] 59 | 60 | [(equal? param-symType "vec_sym") 61 | (init-array 62 | (vector->immutable-vector (build-vector 63 | param-size 64 | (lambda (ignore) 65 | (define inst (init-syminst)) 66 | (assume-inst inst) 67 | inst))) 68 | param-size 69 | param-len)] 70 | 71 | [(equal? param-symType "func_sym") 72 | (define inst-size-log (inexact->exact (ceiling (log inst-size 2)))) 73 | (define op (build-unfuncbv param-size-log inst-size-log)) 74 | (define rs1 (build-unfuncbv param-size-log param-rs1-len)) 75 | (define rs2 (build-unfuncbv param-size-log param-rs2-len)) 76 | (define rd (build-unfuncbv param-size-log param-rd-len)) 77 | (define (array-content pos) 78 | (init-inst (op pos) (rs1 pos) (rs2 pos) (rd pos))) 79 | 80 | (for ([pos (in-range param-size)]) 81 | (assume-inst (array-content (bv pos param-size-log)))) 82 | 83 | (define memi-array (init-array array-content param-size param-len)) 84 | memi-array] 85 | 86 | [else (bug-assert #f #:msg "memi: param-symType unknown")])) 87 | 88 | (memi-cfg array param-size) 89 | ) 90 | 91 | 92 | (define (memi-cfg-evaluate memi-cfg-sym sol) 93 | (define array (memi-cfg-array memi-cfg-sym)) 94 | (define param-size (memi-cfg-param-size memi-cfg-sym)) 95 | 96 | (memi-cfg (array-evaluate array inst-evaluate sol) param-size) 97 | ) 98 | 99 | 100 | (define (memi-cfg->string memi-cfg) 101 | (define array (memi-cfg-array memi-cfg)) 102 | 103 | (array->custom-string 104 | array 105 | (lambda (i e) (~a (bitvector->natural i) "-th INST " e)) 106 | "\n") 107 | ) 108 | 109 | 110 | ; PART memi 111 | ; NOTE: the i-th is to help log two memi read per cycle for OoO 112 | (struct memi (array history clk i-th param-size param-simuCycle) 113 | #:mutable #:transparent 114 | #:methods gen:custom-write 115 | [(define (write-proc this port mode) 116 | (write-string (memi->string this) port))] 117 | ) 118 | 119 | 120 | (define (init-memi memi-cfg param-simuCycle) 121 | (define array (memi-cfg-array memi-cfg)) 122 | (define param-size (memi-cfg-param-size memi-cfg)) 123 | (define param-size-log (inexact->exact (ceiling (log param-size 2)))) 124 | (define param-simuCycle-log 125 | (inexact->exact (ceiling (log param-simuCycle 2)))) 126 | 127 | (memi 128 | array 129 | (initZeroVec-array (* 2 param-simuCycle) (add1 param-size-log)) 130 | (bv 0 param-simuCycle-log) 131 | (bv 0 1) 132 | param-size 133 | param-simuCycle) 134 | ) 135 | 136 | 137 | (define (memi-ref memi pos) 138 | (define array (memi-array memi)) 139 | 140 | (array-ref array pos) 141 | ) 142 | 143 | 144 | (define (logref-memi! memi pos) 145 | (define history (memi-history memi)) 146 | (define clk (memi-clk memi)) 147 | (define i-th (memi-i-th memi)) 148 | (set-memi-i-th! memi (bv 1 1)) 149 | 150 | (set-array! history (concat clk i-th) (concat (bv 1 1) pos)) 151 | (memi-ref memi pos) 152 | ) 153 | 154 | 155 | (define (tick-memi! memi) 156 | (define clk (memi-clk memi)) 157 | 158 | (set-memi-clk! memi (bvadd1 clk)) 159 | (set-memi-i-th! memi (bv 0 1)) 160 | ) 161 | 162 | 163 | (define (memi-history->string memi) 164 | (define history (memi-history memi)) 165 | (define param-size (memi-param-size memi)) 166 | (define param-size-log (inexact->exact (ceiling (log param-size 2)))) 167 | 168 | (define (indexEntry->string index entry) 169 | (define valid (extract param-size-log param-size-log entry)) 170 | (define addr (extract (sub1 param-size-log) 0 entry)) 171 | (if (bveq valid (bv 1 1)) 172 | ;(~a (bitvector->natural index) ": " (bitvector->natural addr) ", ") 173 | (~a (bitvector->natural addr) " ") 174 | "") 175 | ) 176 | 177 | (array->custom-string history indexEntry->string "") 178 | ) 179 | 180 | 181 | (define (memi->string memi) 182 | (~a "history: " (memi-history->string memi)) 183 | ) 184 | 185 | 186 | (define (testMe) 187 | 188 | (define memi-cfg 189 | (init-memi-cfg param-memi-size param-reg-len param-rf-size-log 190 | param-rf-size-log "vec_concrete")) 191 | (define memi (init-memi memi-cfg 10)) 192 | (printf (~a memi "\n")) 193 | 194 | (printf (~a (logref-memi! memi (bv 1 param-memi-size-log)) "\n")) 195 | (printf (~a memi "\n")) 196 | 197 | (tick-memi! memi) 198 | 199 | (printf (~a (logref-memi! memi (bv 4 param-memi-size-log)) "\n")) 200 | (printf (~a memi "\n")) 201 | ) 202 | ;(testMe) 203 | 204 | -------------------------------------------------------------------------------- /src/sym-state/rf.rkt: -------------------------------------------------------------------------------- 1 | #lang rosette 2 | 3 | (require "../lib/lib.rkt") 4 | (provide init-rf-cfg rf-cfg-evaluate init-rf resetsym-rf! rf-ref set-rf!) 5 | 6 | 7 | ; PART rf-cfg 8 | (struct rf-cfg (array param-size param-len) 9 | #:mutable #:transparent 10 | #:methods gen:custom-write 11 | [(define (write-proc this port mode) 12 | (write-string (rf-cfg->string this) port))] 13 | ) 14 | 15 | 16 | (define (init-rf-cfg param-size param-len param-symType) 17 | (define param-size-log (inexact->exact (log param-size 2))) 18 | 19 | (define array 20 | (cond 21 | [(equal? param-symType "vec_concrete") 22 | (init-array (vector (bv 3 param-len) 23 | (bv 1 param-len) 24 | (bv 1 param-len) 25 | (bv 0 param-len)) 26 | param-size 27 | param-len)] 28 | [(equal? param-symType "vec_sym") 29 | (init-array (build-vector param-size 30 | (lambda (ignore) (build-symbv param-len))) 31 | param-size 32 | param-len)] 33 | [(equal? param-symType "func_concrete") 34 | (init-array (lambda (pos) (if (bvzero? pos) 35 | (bv 1 param-len) 36 | (bv 0 param-len))) 37 | param-size 38 | param-len)] 39 | [(equal? param-symType "func_sym") 40 | (init-array (build-unfuncbv param-size-log param-len) 41 | param-size param-len)] 42 | [else (bug-assert #f #:msg "rf: param-symType unknown")])) 43 | 44 | (rf-cfg array param-size param-len) 45 | ) 46 | 47 | 48 | (define (rf-cfg-evaluate rf-cfg-sym sol) 49 | (define array (rf-cfg-array rf-cfg-sym)) 50 | (define param-size (rf-cfg-param-size rf-cfg-sym)) 51 | (define param-len (rf-cfg-param-len rf-cfg-sym)) 52 | 53 | (rf-cfg (array-evaluate array evaluate sol) param-size param-len) 54 | ) 55 | 56 | 57 | (define (rf-cfg->string rf-cfg) 58 | (define array (rf-cfg-array rf-cfg)) 59 | 60 | (array->custom-string array (lambda (i e) (bitvector->natural e)) " ") 61 | ) 62 | 63 | 64 | ; PART rf 65 | (struct rf (array param-size param-len) 66 | #:mutable #:transparent 67 | #:methods gen:custom-write 68 | [(define (write-proc this port mode) 69 | (write-string (rf->string this) port))] 70 | ) 71 | 72 | 73 | (define (init-rf rf-cfg) 74 | (define array (rf-cfg-array rf-cfg)) 75 | (define param-size (rf-cfg-param-size rf-cfg)) 76 | (define param-len (rf-cfg-param-len rf-cfg)) 77 | 78 | (rf 79 | (initFromCopy-array array) 80 | param-size 81 | param-len) 82 | ) 83 | 84 | 85 | (define (resetsym-rf! rf) 86 | (define array (rf-array rf)) 87 | (define param-size (rf-param-size rf)) 88 | (define param-len (rf-param-len rf)) 89 | 90 | (define rf-cfg-new (init-rf-cfg param-size param-len "vec_sym")) 91 | (define array-new (rf-cfg-array rf-cfg-new)) 92 | (assume (array-equal array array-new)) 93 | (set-rf-array! rf array-new) 94 | ) 95 | 96 | 97 | (define (rf-ref rf pos) 98 | (define array (rf-array rf)) 99 | 100 | (array-ref array pos) 101 | ) 102 | 103 | 104 | (define (set-rf! rf pos v) 105 | (define array (rf-array rf)) 106 | 107 | (set-array! array pos v) 108 | ) 109 | 110 | 111 | (define (rf->string rf) 112 | (define array (rf-array rf)) 113 | 114 | (array->custom-string array (lambda (i e) (bitvector->natural e)) " ") 115 | ) 116 | 117 | 118 | (define (testMe) 119 | 120 | (define rf-cfg (init-rf-cfg param-rf-size param-reg-len "vec_concrete")) 121 | (define rf (init-rf rf-cfg)) 122 | (printf (~a rf "\n")) 123 | 124 | (printf (~a (rf-ref rf (bv 1 param-rf-size-log)) "\n")) 125 | (printf (~a (set-rf! rf (bv 1 param-rf-size-log) (bv 7 param-reg-len)) "\n")) 126 | (printf (~a (set-rf! rf (bv 2 param-rf-size-log) (bv 2 param-reg-len)) "\n")) 127 | (printf (~a rf "\n")) 128 | ) 129 | ;(testMe) 130 | 131 | --------------------------------------------------------------------------------