├── .gitignore ├── Design-Run.vlog ├── LA32R-pipeline-scala.code-workspace ├── LICENSE ├── Makefile ├── README.md ├── doc ├── Intro.md ├── Pipeline.drawio ├── README.assets │ └── Pipeline.png ├── Sync.md └── Zircon.png ├── scripts └── split-module.py ├── soc ├── cons │ └── soc.xdc └── src │ ├── Soc.sv │ └── ip │ ├── ip_clock │ └── ip_clock.xml │ └── main_memory │ └── main_memory.xml └── src └── main └── scala ├── 00-CPU └── CPU.scala ├── 01-Previous-Fetch-Stage ├── PC.scala └── Predict.scala ├── 02-Inst-Fetch-Stage ├── ICache.scala └── Inst_Replace.scala ├── 03-Previous-Decode-Stage ├── Fetch_Queue.scala └── Prev_Decode.scala ├── 04-Decode-Stage ├── Decode.scala └── Free_List.scala ├── 05-Rename-Stage ├── CRat.scala ├── Dispatch.scala └── Reg_Rename.scala ├── 06-Issue-Stage ├── Busy_Board.scala ├── Order_Issue_Queue.scala ├── Order_Select.scala ├── Unorder_Issue_Queue.scala └── Unorder_Select.scala ├── 07-Regfile-Read-Stage ├── CSR_Regfile.scala └── Physical_Regfile.scala ├── 08-Execute-Stage ├── Arith-Branch │ ├── ALU.scala │ └── Branch.scala ├── Load-Store │ ├── DCache.scala │ ├── Exception_LS.scala │ ├── MMU.scala │ ├── SB.scala │ └── TLB.scala ├── Mul-Div │ ├── Divide.scala │ ├── MDU.scala │ └── Multiply.scala └── Stable_Counter.scala ├── 09-Write-Back-Stage └── Bypass.scala ├── 10-Commit-Stage ├── Arch_Rat.scala └── ROB.scala ├── CPU_Main.scala ├── Cache-Test └── Cache_Top.scala ├── Loongarch ├── Architecture.scala ├── Config.scala ├── Inst_Pack.scala ├── Structure.scala └── Utils.scala ├── Memory ├── xilinx_simple_dual_port_1_clock_ram_no_change.scala ├── xilinx_simple_dual_port_1_clock_ram_read_first.scala ├── xilinx_simple_dual_port_1_clock_ram_write_first.scala ├── xilinx_simple_dual_port_byte_write_1_clock_ram_read_first.scala ├── xilinx_simple_dual_port_byte_write_1_clock_ram_write_first.scala ├── xilinx_single_port_ram_read_first.scala ├── xilinx_single_port_ram_read_no_change.scala └── xilinx_single_port_ram_write_first.scala ├── SegReg ├── FU1_EX_WB_Reg.scala ├── FU2_EX_WB_Reg.scala ├── ID_RN_Reg.scala ├── IF_PD_Reg.scala ├── IS_RF_Reg.scala ├── LS_EX2_WB_Reg.scala ├── LS_EX_MEM_Reg.scala ├── LS_RF_EX_Reg.scala ├── MD_EX1_EX2_Reg.scala ├── MD_EX_WB_Reg.scala ├── PD_FQ_Reg.scala ├── PF_IF_Reg.scala ├── RF_EX_Reg.scala └── RN_DP_Reg.scala └── Socket └── AXI_Arbiter.scala /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MAdrid1011/Zircon/HEAD/.gitignore -------------------------------------------------------------------------------- /Design-Run.vlog: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MAdrid1011/Zircon/HEAD/Design-Run.vlog -------------------------------------------------------------------------------- /LA32R-pipeline-scala.code-workspace: -------------------------------------------------------------------------------- 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