├── program ├── 00_counter │ ├── program.hex │ ├── 00_clean_all.sh │ ├── 01_run_mars.sh │ ├── 02_compile_to_hex_with_mars.sh │ ├── 05_copy_program_to_board.sh │ ├── main.S │ ├── 03_simulate_with_modelsim.sh │ ├── 04_simulate_with_icarus.sh │ └── modelsim_script.tcl ├── 02_sqrt │ ├── 00_clean_all.sh │ ├── 01_run_mars.sh │ ├── 05_copy_program_to_board.sh │ ├── 02_compile_to_hex_with_mars.sh │ ├── 03_simulate_with_modelsim.sh │ ├── program.hex │ ├── 04_simulate_with_icarus.sh │ ├── modelsim_script.tcl │ └── main.S └── 01_fibonacci │ ├── 00_clean_all.sh │ ├── 01_run_mars.sh │ ├── program.hex │ ├── 05_copy_program_to_board.sh │ ├── 02_compile_to_hex_with_mars.sh │ ├── 03_simulate_with_modelsim.sh │ ├── main.S │ ├── 04_simulate_with_icarus.sh │ └── modelsim_script.tcl ├── board ├── program │ └── program.hex ├── de0 │ ├── de0_top.qpf │ ├── make_project.sh │ ├── de0_top.sdc │ └── de0_top.v ├── de0_cv │ ├── de0_cv.qpf │ ├── make_project.sh │ ├── de0_cv.sdc │ └── de0_cv.v ├── zeowaa │ ├── zeowaa.qpf │ ├── make_project.sh │ ├── zeowaa.sdc │ ├── zeowaa.v │ └── zeowaa.qsf ├── de0_nano │ ├── de0_nano.qpf │ ├── doc │ │ ├── photo.jpg │ │ ├── pins.jpg │ │ └── pins_.jpg │ ├── make_project.sh │ ├── README.md │ ├── de0_nano.sdc │ ├── de0_nano.v │ └── de0_nano.qsf ├── de10_lite │ ├── de10_lite.qpf │ ├── make_project.sh │ ├── de10_lite.sdc │ ├── de10_lite.v │ └── de10_lite.qsf ├── de10_nano │ ├── de10_nano.qpf │ ├── make_project.sh │ ├── de10_nano.sdc │ ├── de10_nano.v │ └── de10_nano.qsf ├── de1_soc │ ├── de1_soc.qpf │ ├── make_project.sh │ ├── de1_soc.sdc │ └── de1_soc.v ├── de4_230 │ ├── DE4_230.qpf │ ├── doc │ │ └── de4_230.jpg │ ├── make_project.sh │ ├── DE4_230.sdc │ ├── de4_230.v │ └── DE4_230.qsf ├── marsohod_3 │ ├── marsohod_3.qpf │ ├── help.txt │ ├── make_project.sh │ ├── marsohod_3.sdc │ ├── marsohod_3.v │ └── marsohod_3.qsf ├── marsohod_3b │ ├── marsohod_3b.qpf │ ├── help.txt │ ├── make_project.sh │ ├── marsohod_3b.sdc │ ├── marsohod_3b.v │ └── marsohod_3b.qsf ├── max_10_neek │ ├── max_10_neek.qpf │ ├── make_project.sh │ ├── max_10_neek.sdc │ └── max_10_neek.v ├── de10_standard │ ├── de10_standard.qpf │ ├── make_project.sh │ ├── de10_standard.sdc │ ├── de10_standard.v │ └── de10_standard.qsf ├── rz_easyFPGA_A2.1 │ ├── rz_easyFPGA_A21.qpf │ ├── doc │ │ ├── photo.jpg │ │ └── pins.jpg │ ├── make_project.sh │ ├── rz_easyFPGA_A21.sdc │ ├── README.md │ ├── rz_easyFPGA_A21.v │ └── rz_easyFPGA_A21.qsf ├── max_10_evkit │ ├── images │ │ ├── sch.jpg │ │ ├── blaster.jpg │ │ └── max_10_eval_board.jpg │ ├── make_project.sh │ ├── max_10_evkit.v │ ├── README.md │ ├── max_10_evkit.qpf │ └── max_10_evkit.qsf ├── nexys4 │ ├── make_project.sh │ └── nexys4.v └── nexys4_ddr │ ├── make_project.sh │ ├── nexys4_ddr.v │ └── nexys4_ddr.xdc ├── scripts ├── program │ └── common │ │ ├── 00_clean_all.bat │ │ ├── 01_run_mars.bat │ │ ├── 00_clean_all.sh │ │ ├── 01_run_mars.sh │ │ ├── 02_compile_to_hex_with_mars.bat │ │ ├── 05_copy_program_to_board.bat │ │ ├── 02_compile_to_hex_with_mars.sh │ │ ├── 05_copy_program_to_board.sh │ │ ├── 03_simulate_with_modelsim.bat │ │ ├── 03_simulate_with_modelsim.sh │ │ ├── 04_simulate_with_icarus.sh │ │ └── 04_simulate_with_icarus.bat ├── bin │ └── Mars4_5.jar ├── board │ └── common │ │ ├── make_project.bat │ │ └── make_project.sh ├── README ├── init_linux.sh └── init_windows.bat ├── doc └── README.md ├── .gitignore ├── src ├── sm_rom.v ├── sm_register.v ├── sm_cpu.vh ├── sm_top.v ├── sm_hex_display.v └── sm_cpu.v ├── LICENSE ├── README.md └── testbench └── testbench.v /program/00_counter/program.hex: -------------------------------------------------------------------------------- 1 | 00001021 2 | 24420001 3 | 1000fffe 4 | -------------------------------------------------------------------------------- /board/program/program.hex: -------------------------------------------------------------------------------- 1 | 00001025 2 | 24420001 3 | 1000fffe 4 | 00000000 5 | -------------------------------------------------------------------------------- /scripts/program/common/00_clean_all.bat: -------------------------------------------------------------------------------- 1 | 2 | rd /s /q sim 3 | del program*.hex 4 | -------------------------------------------------------------------------------- /board/de0/de0_top.qpf: -------------------------------------------------------------------------------- 1 | # This file can be empty, all the settings are in .qsf file 2 | -------------------------------------------------------------------------------- /board/de0_cv/de0_cv.qpf: -------------------------------------------------------------------------------- 1 | # This file can be empty, all the settings are in .qsf file 2 | -------------------------------------------------------------------------------- /board/zeowaa/zeowaa.qpf: -------------------------------------------------------------------------------- 1 | # This file can be empty, all the settings are in .qsf file 2 | -------------------------------------------------------------------------------- /scripts/program/common/01_run_mars.bat: -------------------------------------------------------------------------------- 1 | 2 | javaw -jar ..\..\scripts\bin\Mars4_5.jar 3 | -------------------------------------------------------------------------------- /board/de0_nano/de0_nano.qpf: -------------------------------------------------------------------------------- 1 | # This file can be empty, all the settings are in .qsf file 2 | -------------------------------------------------------------------------------- /board/de10_lite/de10_lite.qpf: -------------------------------------------------------------------------------- 1 | # This file can be empty, all the settings are in .qsf file 2 | -------------------------------------------------------------------------------- /board/de10_nano/de10_nano.qpf: -------------------------------------------------------------------------------- 1 | # This file can be empty, all the settings are in .qsf file 2 | -------------------------------------------------------------------------------- /board/de1_soc/de1_soc.qpf: -------------------------------------------------------------------------------- 1 | # This file can be empty, all the settings are in .qsf file 2 | -------------------------------------------------------------------------------- /board/de4_230/DE4_230.qpf: -------------------------------------------------------------------------------- 1 | # This file can be empty, all the settings are in .qsf file 2 | -------------------------------------------------------------------------------- /program/00_counter/00_clean_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf sim 4 | rm -f program.hex 5 | -------------------------------------------------------------------------------- /program/02_sqrt/00_clean_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf sim 4 | rm -f program.hex 5 | -------------------------------------------------------------------------------- /board/marsohod_3/marsohod_3.qpf: -------------------------------------------------------------------------------- 1 | # This file can be empty, all the settings are in .qsf file 2 | -------------------------------------------------------------------------------- /board/marsohod_3b/marsohod_3b.qpf: -------------------------------------------------------------------------------- 1 | # This file can be empty, all the settings are in .qsf file 2 | -------------------------------------------------------------------------------- /board/max_10_neek/max_10_neek.qpf: -------------------------------------------------------------------------------- 1 | # This file can be empty, all the settings are in .qsf file 2 | -------------------------------------------------------------------------------- /program/01_fibonacci/00_clean_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf sim 4 | rm -f program.hex 5 | -------------------------------------------------------------------------------- /program/02_sqrt/01_run_mars.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | java -jar ../../scripts/bin/Mars4_5.jar & 4 | -------------------------------------------------------------------------------- /scripts/program/common/00_clean_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf sim 4 | rm -f program.hex 5 | -------------------------------------------------------------------------------- /board/de10_standard/de10_standard.qpf: -------------------------------------------------------------------------------- 1 | # This file can be empty, all the settings are in .qsf file 2 | -------------------------------------------------------------------------------- /program/00_counter/01_run_mars.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | java -jar ../../scripts/bin/Mars4_5.jar & 4 | -------------------------------------------------------------------------------- /program/01_fibonacci/01_run_mars.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | java -jar ../../scripts/bin/Mars4_5.jar & 4 | -------------------------------------------------------------------------------- /scripts/bin/Mars4_5.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MIPSfpga/schoolMIPS/HEAD/scripts/bin/Mars4_5.jar -------------------------------------------------------------------------------- /board/rz_easyFPGA_A2.1/rz_easyFPGA_A21.qpf: -------------------------------------------------------------------------------- 1 | # This file can be empty, all the settings are in .qsf file 2 | -------------------------------------------------------------------------------- /scripts/program/common/01_run_mars.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | java -jar ../../scripts/bin/Mars4_5.jar & 4 | -------------------------------------------------------------------------------- /board/de0_nano/doc/photo.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MIPSfpga/schoolMIPS/HEAD/board/de0_nano/doc/photo.jpg -------------------------------------------------------------------------------- /board/de0_nano/doc/pins.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MIPSfpga/schoolMIPS/HEAD/board/de0_nano/doc/pins.jpg -------------------------------------------------------------------------------- /board/de0_nano/doc/pins_.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MIPSfpga/schoolMIPS/HEAD/board/de0_nano/doc/pins_.jpg -------------------------------------------------------------------------------- /board/de4_230/doc/de4_230.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MIPSfpga/schoolMIPS/HEAD/board/de4_230/doc/de4_230.jpg -------------------------------------------------------------------------------- /board/max_10_evkit/images/sch.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MIPSfpga/schoolMIPS/HEAD/board/max_10_evkit/images/sch.jpg -------------------------------------------------------------------------------- /board/rz_easyFPGA_A2.1/doc/photo.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MIPSfpga/schoolMIPS/HEAD/board/rz_easyFPGA_A2.1/doc/photo.jpg -------------------------------------------------------------------------------- /board/rz_easyFPGA_A2.1/doc/pins.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MIPSfpga/schoolMIPS/HEAD/board/rz_easyFPGA_A2.1/doc/pins.jpg -------------------------------------------------------------------------------- /doc/README.md: -------------------------------------------------------------------------------- 1 | 2 | For docs and CPU diagrams please visit the project [wiki](https://github.com/MIPSfpga/schoolMIPS/wiki) 3 | -------------------------------------------------------------------------------- /board/max_10_evkit/images/blaster.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MIPSfpga/schoolMIPS/HEAD/board/max_10_evkit/images/blaster.jpg -------------------------------------------------------------------------------- /program/01_fibonacci/program.hex: -------------------------------------------------------------------------------- 1 | 00004021 2 | 24090001 3 | 00091021 4 | 01094021 5 | 00081021 6 | 01094821 7 | 00091021 8 | 1000fffb 9 | -------------------------------------------------------------------------------- /scripts/board/common/make_project.bat: -------------------------------------------------------------------------------- 1 | rd /s /q project 2 | mkdir project 3 | copy *.qpf project 4 | copy *.qsf project 5 | copy *.sdc project 6 | -------------------------------------------------------------------------------- /scripts/program/common/02_compile_to_hex_with_mars.bat: -------------------------------------------------------------------------------- 1 | 2 | java -jar ..\..\scripts\bin\Mars4_5.jar nc a dump .text HexText program.hex main.S 3 | -------------------------------------------------------------------------------- /scripts/program/common/05_copy_program_to_board.bat: -------------------------------------------------------------------------------- 1 | 2 | del ..\..\board\program\program.hex 3 | 4 | copy .\program.hex ..\..\board\program 5 | -------------------------------------------------------------------------------- /board/max_10_evkit/images/max_10_eval_board.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MIPSfpga/schoolMIPS/HEAD/board/max_10_evkit/images/max_10_eval_board.jpg -------------------------------------------------------------------------------- /program/02_sqrt/05_copy_program_to_board.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -f ../../board/program/program.hex 4 | 5 | cp ./program.hex ../../board/program 6 | -------------------------------------------------------------------------------- /program/00_counter/02_compile_to_hex_with_mars.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | java -jar ../../scripts/bin/Mars4_5.jar nc a dump .text HexText program.hex main.S 4 | -------------------------------------------------------------------------------- /program/00_counter/05_copy_program_to_board.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -f ../../board/program/program.hex 4 | 5 | cp ./program.hex ../../board/program 6 | -------------------------------------------------------------------------------- /program/01_fibonacci/05_copy_program_to_board.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -f ../../board/program/program.hex 4 | 5 | cp ./program.hex ../../board/program 6 | -------------------------------------------------------------------------------- /program/02_sqrt/02_compile_to_hex_with_mars.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | java -jar ../../scripts/bin/Mars4_5.jar nc a dump .text HexText program.hex main.S 4 | -------------------------------------------------------------------------------- /program/01_fibonacci/02_compile_to_hex_with_mars.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | java -jar ../../scripts/bin/Mars4_5.jar nc a dump .text HexText program.hex main.S 4 | -------------------------------------------------------------------------------- /scripts/program/common/02_compile_to_hex_with_mars.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | java -jar ../../scripts/bin/Mars4_5.jar nc a dump .text HexText program.hex main.S 4 | -------------------------------------------------------------------------------- /scripts/program/common/05_copy_program_to_board.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -f ../../board/program/program.hex 4 | 5 | cp ./program.hex ../../board/program 6 | -------------------------------------------------------------------------------- /program/00_counter/main.S: -------------------------------------------------------------------------------- 1 | 2 | 3 | .text 4 | 5 | start: move $v0, $0 6 | counter: addiu $v0, $v0, 1 7 | beqz $0, counter 8 | -------------------------------------------------------------------------------- /scripts/README: -------------------------------------------------------------------------------- 1 | 2 | Use init_linux.sh to replace all the *.bat (build, simulation and etc.) files with their linux analogs (*.sh). 3 | Batch init_windows.bat provides the reverse action. 4 | -------------------------------------------------------------------------------- /scripts/program/common/03_simulate_with_modelsim.bat: -------------------------------------------------------------------------------- 1 | rd /s /q sim 2 | md sim 3 | cd sim 4 | 5 | copy ..\*.hex . 6 | 7 | vsim -novopt -do ../modelsim_script.tcl 8 | 9 | cd .. 10 | -------------------------------------------------------------------------------- /program/00_counter/03_simulate_with_modelsim.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf sim 4 | mkdir sim 5 | cd sim 6 | 7 | cp ../*.hex . 8 | 9 | vsim -novopt -do ../modelsim_script.tcl 10 | 11 | cd .. 12 | -------------------------------------------------------------------------------- /program/02_sqrt/03_simulate_with_modelsim.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf sim 4 | mkdir sim 5 | cd sim 6 | 7 | cp ../*.hex . 8 | 9 | vsim -novopt -do ../modelsim_script.tcl 10 | 11 | cd .. 12 | -------------------------------------------------------------------------------- /program/01_fibonacci/03_simulate_with_modelsim.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf sim 4 | mkdir sim 5 | cd sim 6 | 7 | cp ../*.hex . 8 | 9 | vsim -novopt -do ../modelsim_script.tcl 10 | 11 | cd .. 12 | -------------------------------------------------------------------------------- /scripts/program/common/03_simulate_with_modelsim.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf sim 4 | mkdir sim 5 | cd sim 6 | 7 | cp ../*.hex . 8 | 9 | vsim -novopt -do ../modelsim_script.tcl 10 | 11 | cd .. 12 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | project/ 2 | run/ 3 | sim/ 4 | *.bak 5 | *.o 6 | *.elf 7 | *.lst 8 | *.map 9 | *.rec 10 | 11 | FPGA*.txt 12 | test.html 13 | test.html.imgtec_forum 14 | .vscode/ 15 | 16 | doc/src/archive/ 17 | -------------------------------------------------------------------------------- /board/marsohod_3/help.txt: -------------------------------------------------------------------------------- 1 | 0-й светодиод отсчитывает такты работы процессора 2 | 1 - 7 светодиод: вывод малдших 7 бит регистра $v0 3 |  нопка разрешени¤ работы процессора: KEY1. 4 |  нопка сброса процессора: KEY0. -------------------------------------------------------------------------------- /board/marsohod_3b/help.txt: -------------------------------------------------------------------------------- 1 | 0-й светодиод отсчитывает такты работы процессора 2 | 1 - 7 светодиод: вывод младших 7 бит регистра $v0 3 | Кнопка разрешения работы процессора: KEY1. 4 | Кнопка сброса процессора: KEY0. 5 | -------------------------------------------------------------------------------- /program/02_sqrt/program.hex: -------------------------------------------------------------------------------- 1 | 24040052 2 | 24020000 3 | 3c084000 4 | 00004821 5 | 01285025 6 | 00094842 7 | 008a582b 8 | 15600002 9 | 008a2023 10 | 01284825 11 | 00084082 12 | 1500fff8 13 | 00091021 14 | 1000ffff 15 | -------------------------------------------------------------------------------- /board/de0/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/de0_cv/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/de0_nano/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/de10_lite/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/de10_nano/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/de1_soc/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/de4_230/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/marsohod_3/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/nexys4/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/nexys4_ddr/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/zeowaa/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/de10_standard/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/marsohod_3b/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/max_10_evkit/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/max_10_neek/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /scripts/board/common/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /board/rz_easyFPGA_A2.1/make_project.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | PROJECTPATH=$SCRIPTPATH/project 5 | 6 | rm -rf $PROJECTPATH 7 | mkdir $PROJECTPATH 8 | 9 | cp $SCRIPTPATH/*.qpf $PROJECTPATH 10 | cp $SCRIPTPATH/*.qsf $PROJECTPATH 11 | cp $SCRIPTPATH/*.sdc $PROJECTPATH 12 | -------------------------------------------------------------------------------- /src/sm_rom.v: -------------------------------------------------------------------------------- 1 | 2 | module sm_rom 3 | #( 4 | parameter SIZE = 64 5 | ) 6 | ( 7 | input [31:0] a, 8 | output [31:0] rd 9 | ); 10 | reg [31:0] rom [SIZE - 1:0]; 11 | assign rd = rom [a]; 12 | 13 | initial begin 14 | $readmemh ("program.hex", rom); 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /program/01_fibonacci/main.S: -------------------------------------------------------------------------------- 1 | 2 | 3 | .text 4 | 5 | start: move $t0, $0 6 | li $t1, 1 7 | move $v0, $t1 8 | 9 | fibonacci: addu $t0, $t0, $t1 10 | move $v0, $t0 11 | addu $t1, $t0, $t1 12 | move $v0, $t1 13 | beqz $0, fibonacci 14 | -------------------------------------------------------------------------------- /board/marsohod_3/marsohod_3.sdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period "100.0 MHz" [get_ports CLK100MHZ] 3 | 4 | derive_clock_uncertainty 5 | create_generated_clock -name {clk} -divide_by 2 -source [get_ports {CLK100MHZ}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}] 6 | 7 | set_false_path -from * -to [get_ports {LED[*]}] 8 | 9 | set_false_path -from [get_ports {KEY0}] -to [all_clocks] 10 | set_false_path -from [get_ports {KEY1}] -to [all_clocks] 11 | -------------------------------------------------------------------------------- /board/marsohod_3b/marsohod_3b.sdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period "100.0 MHz" [get_ports CLK100MHZ] 3 | 4 | derive_clock_uncertainty 5 | create_generated_clock -name {clk} -divide_by 2 -source [get_ports {CLK100MHZ}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}] 6 | 7 | set_false_path -from * -to [get_ports {LED[*]}] 8 | 9 | set_false_path -from [get_ports {KEY0}] -to [all_clocks] 10 | set_false_path -from [get_ports {KEY1}] -to [all_clocks] 11 | -------------------------------------------------------------------------------- /board/rz_easyFPGA_A2.1/rz_easyFPGA_A21.sdc: -------------------------------------------------------------------------------- 1 | 2 | 3 | create_clock -period "100.0 MHz" [get_ports CLK100MHZ] 4 | 5 | derive_clock_uncertainty 6 | create_generated_clock -name {clk} -divide_by 2 -source [get_ports {CLK100MHZ}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}] 7 | 8 | set_false_path -from * -to [get_ports {LED[*]}] 9 | 10 | set_false_path -from [get_ports {KEY0}] -to [all_clocks] 11 | set_false_path -from [get_ports {KEY1}] -to [all_clocks] -------------------------------------------------------------------------------- /program/02_sqrt/04_simulate_with_icarus.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf sim 4 | mkdir sim 5 | cd sim 6 | 7 | cp ../*.hex . 8 | 9 | # default simulation params 10 | SIMULATION_CYCLESS=120 11 | 12 | # read local simulation params 13 | source ../icarus.cfg 14 | 15 | # compile 16 | iverilog -g2005 -D SIMULATION -D ICARUS -I ../../../src -I ../../../testbench -s sm_testbench ../../../src/*.v ../../../testbench/*.v 17 | 18 | # simulation 19 | vvp -la.lst -n a.out -vcd 20 | 21 | # output 22 | gtkwave dump.vcd 23 | 24 | cd .. 25 | -------------------------------------------------------------------------------- /program/00_counter/04_simulate_with_icarus.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf sim 4 | mkdir sim 5 | cd sim 6 | 7 | cp ../*.hex . 8 | 9 | # default simulation params 10 | SIMULATION_CYCLESS=120 11 | 12 | # read local simulation params 13 | source ../icarus.cfg 14 | 15 | # compile 16 | iverilog -g2005 -D SIMULATION -D ICARUS -I ../../../src -I ../../../testbench -s sm_testbench ../../../src/*.v ../../../testbench/*.v 17 | 18 | # simulation 19 | vvp -la.lst -n a.out -vcd 20 | 21 | # output 22 | gtkwave dump.vcd 23 | 24 | cd .. 25 | -------------------------------------------------------------------------------- /program/01_fibonacci/04_simulate_with_icarus.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf sim 4 | mkdir sim 5 | cd sim 6 | 7 | cp ../*.hex . 8 | 9 | # default simulation params 10 | SIMULATION_CYCLESS=120 11 | 12 | # read local simulation params 13 | source ../icarus.cfg 14 | 15 | # compile 16 | iverilog -g2005 -D SIMULATION -D ICARUS -I ../../../src -I ../../../testbench -s sm_testbench ../../../src/*.v ../../../testbench/*.v 17 | 18 | # simulation 19 | vvp -la.lst -n a.out -vcd 20 | 21 | # output 22 | gtkwave dump.vcd 23 | 24 | cd .. 25 | -------------------------------------------------------------------------------- /scripts/program/common/04_simulate_with_icarus.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf sim 4 | mkdir sim 5 | cd sim 6 | 7 | cp ../*.hex . 8 | 9 | # default simulation params 10 | SIMULATION_CYCLESS=120 11 | 12 | # read local simulation params 13 | source ../icarus.cfg 14 | 15 | # compile 16 | iverilog -g2005 -D SIMULATION -D ICARUS -I ../../../src -I ../../../testbench -s sm_testbench ../../../src/*.v ../../../testbench/*.v 17 | 18 | # simulation 19 | vvp -la.lst -n a.out -vcd 20 | 21 | # output 22 | gtkwave dump.vcd 23 | 24 | cd .. 25 | -------------------------------------------------------------------------------- /scripts/init_linux.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SCRIPTPATH=$( cd $(dirname $0) ; pwd -P ) 4 | TOP_BOARD=$SCRIPTPATH/../board 5 | TOP_PROGRAM=$SCRIPTPATH/../program 6 | 7 | for board in $TOP_BOARD/* 8 | do 9 | if [ -d $board ] && [ "$TOP_BOARD/program" != "$board" ]; then 10 | rm -f $board/*.bat 11 | cp $SCRIPTPATH/board/common/*.sh $board 12 | chmod a+x $board/*.sh 13 | fi 14 | done 15 | 16 | for program in $TOP_PROGRAM/* 17 | do 18 | if [ -d $program ]; then 19 | rm -f $program/*.bat 20 | cp $SCRIPTPATH/program/common/*.sh $program 21 | chmod a+x $program/*.sh 22 | fi 23 | done 24 | -------------------------------------------------------------------------------- /board/rz_easyFPGA_A2.1/README.md: -------------------------------------------------------------------------------- 1 | # RZ-EasyFPGA A2.1 (Altera Cyclone IV) 2 | 3 | Thanks to [@woodywitch](https://github.com/woodywitch) and [@Dluzhnevsky](https://github.com/Dluzhnevsky) for this port. 4 | 5 | ## Used pins 6 | 7 | Pin | Name | Description 8 | --- | ---- | ----------- 9 | pin_23 | CLK100MHZ | system clock 10 | pin_25 | KEY0 | system reset 11 | pin_88 | KEY1 | clock enable 12 | pin_87:84 | LED1-LED4 | system output 13 | 14 | ## Board photo 15 | 16 | ![photo](/board/rz_easyFPGA_A2.1/doc/photo.jpg) 17 | 18 | ## Board pinout 19 | 20 | ![pinout](/board/rz_easyFPGA_A2.1/doc/pins.jpg) 21 | -------------------------------------------------------------------------------- /program/00_counter/modelsim_script.tcl: -------------------------------------------------------------------------------- 1 | 2 | vlib work 3 | 4 | set p0 -vlog01compat 5 | set p1 +define+SIMULATION 6 | 7 | set i0 +incdir+../../../src 8 | set i1 +incdir+../../../testbench 9 | 10 | set s0 ../../../src/*.v 11 | set s1 ../../../testbench/*.v 12 | 13 | vlog $p0 $p1 $i0 $i1 $s0 $s1 14 | 15 | vsim work.sm_testbench 16 | 17 | # add wave -radix hex sim:/sm_testbench/* 18 | add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/* 19 | add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/rf/* 20 | add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/rf/rf 21 | 22 | run -all 23 | 24 | wave zoom full 25 | -------------------------------------------------------------------------------- /program/01_fibonacci/modelsim_script.tcl: -------------------------------------------------------------------------------- 1 | 2 | vlib work 3 | 4 | set p0 -vlog01compat 5 | set p1 +define+SIMULATION 6 | 7 | set i0 +incdir+../../../src 8 | set i1 +incdir+../../../testbench 9 | 10 | set s0 ../../../src/*.v 11 | set s1 ../../../testbench/*.v 12 | 13 | vlog $p0 $p1 $i0 $i1 $s0 $s1 14 | 15 | vsim work.sm_testbench 16 | 17 | # add wave -radix hex sim:/sm_testbench/* 18 | add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/* 19 | add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/rf/* 20 | add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/rf/rf 21 | 22 | run -all 23 | 24 | wave zoom full 25 | -------------------------------------------------------------------------------- /scripts/init_windows.bat: -------------------------------------------------------------------------------- 1 | 2 | set TOP_BOARD=..\board 3 | set TOP_PROGRAM=..\program 4 | 5 | rem replace board\*\*.sh with scripts\board\common\*.bat 6 | for /f %%f in ('dir /A:D /B %TOP_BOARD%') do ( 7 | if not %%f == program ( 8 | del %TOP_BOARD%\%%f\*.sh 9 | copy .\board\common\*.bat %TOP_BOARD%\%%f 10 | ) 11 | ) 12 | 13 | rem replace program\*\*.sh with scripts\program\common\*.bat 14 | for /f %%f in ('dir /A:D /B %TOP_PROGRAM%') do ( 15 | if not %%f == program ( 16 | del %TOP_PROGRAM%\%%f\*.sh 17 | copy .\program\common\*.bat %TOP_PROGRAM%\%%f 18 | ) 19 | ) 20 | -------------------------------------------------------------------------------- /board/de0_nano/README.md: -------------------------------------------------------------------------------- 1 | # Terasic DE0-Nano (Altera Cyclone IV) 2 | 3 | Thanks to [@dbkudryavtsevEduHSE](https://github.com/dbkudryavtsevEduHSE) for this port. 4 | 5 | ## Used pins 6 | 7 | Pin | Name | Description 8 | --- | ---- | ----------- 9 | pin_r8 | FPGA_CLK1_50 | system clock 10 | pin_j15 | KEY0 | system reset 11 | pin_e1 | KEY1 | clock enable 12 | pin_a15, a13, b13, a11, s1, f3, b1, l3 | LED0-LED7 | system output 13 | pin_m1, t8, b9, m15|SW0-SW3| 14 | 15 | ## Board photo 16 | 17 | ![photo](/board/de0_nano/doc/photo.jpg) 18 | 19 | ## Board pinout 20 | 21 | ![pinout](/board/de0_nano/doc/pins.jpg) 22 | ![pinout](/board/de0_nano/doc/pins_.jpg) -------------------------------------------------------------------------------- /program/02_sqrt/modelsim_script.tcl: -------------------------------------------------------------------------------- 1 | 2 | vlib work 3 | 4 | set p0 -vlog01compat 5 | set p1 +define+SIMULATION 6 | 7 | set i0 +incdir+../../../src 8 | set i1 +incdir+../../../testbench 9 | 10 | set s0 ../../../src/*.v 11 | set s1 ../../../testbench/*.v 12 | 13 | vlog $p0 $p1 $i0 $i1 $s0 $s1 14 | 15 | vsim work.sm_testbench 16 | 17 | # add wave -radix hex sim:/sm_testbench/* 18 | add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/* 19 | add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/rf/* 20 | add wave -radix hex sim:/sm_testbench/sm_top/sm_cpu/rf/rf 21 | add wave sim:/sm_testbench/cycle 22 | 23 | run -all 24 | 25 | wave zoom full 26 | -------------------------------------------------------------------------------- /board/max_10_neek/max_10_neek.sdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50] 3 | create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50] 4 | create_clock -period "50.0 MHz" [get_ports MAX10_CLK3_50] 5 | 6 | derive_clock_uncertainty 7 | create_generated_clock -name {clk} -divide_by 2 -source [get_ports {MAX10_CLK1_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}] 8 | 9 | set_false_path -from * -to [get_ports {LEDR[*]}] 10 | set_false_path -from * -to [get_ports {HEX0[*]}] 11 | set_false_path -from * -to [get_ports {HEX1[*]}] 12 | 13 | set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] 14 | set_false_path -from [get_ports {SW[*]}] -to [all_clocks] 15 | -------------------------------------------------------------------------------- /src/sm_register.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module sm_register 4 | ( 5 | input clk, 6 | input rst, 7 | input [ 31 : 0 ] d, 8 | output reg [ 31 : 0 ] q 9 | ); 10 | always @ (posedge clk or negedge rst) 11 | if(~rst) 12 | q <= 32'b0; 13 | else 14 | q <= d; 15 | endmodule 16 | 17 | 18 | module sm_register_we 19 | ( 20 | input clk, 21 | input rst, 22 | input we, 23 | input [ 31 : 0 ] d, 24 | output reg [ 31 : 0 ] q 25 | ); 26 | always @ (posedge clk or negedge rst) 27 | if(~rst) 28 | q <= 32'b0; 29 | else 30 | if(we) q <= d; 31 | endmodule 32 | -------------------------------------------------------------------------------- /board/zeowaa/zeowaa.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period "50.0 MHz" [get_ports clk_50] 2 | 3 | derive_clock_uncertainty 4 | create_generated_clock -name {clk} -divide_by 2 -source [get_ports {clk_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}] 5 | create_generated_clock -name {clk_hex} -divide_by 2 -source [get_ports {clk_50}] [get_registers {sm_clk_divider:hex_clk_divider|sm_register_we:r_cntr|q[16]}] 6 | 7 | set_false_path -from [get_ports {key[*]}] -to [all_clocks] 8 | set_false_path -from [get_ports {sw[*]}] -to [all_clocks] 9 | 10 | set_false_path -from * -to [get_ports {led[*]}] 11 | set_false_path -from * -to [get_ports {hex[*]}] 12 | set_false_path -from * -to [get_ports {digit[*]}] 13 | set_false_path -from * -to buzzer 14 | -------------------------------------------------------------------------------- /board/de1_soc/de1_soc.sdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period "50.0 MHz" [get_ports CLOCK_50] 3 | 4 | derive_clock_uncertainty 5 | create_generated_clock -name {clk} -divide_by 2 -source [get_ports {CLOCK_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}] 6 | 7 | set_false_path -from * -to [get_ports {LEDR[*]}] 8 | set_false_path -from * -to [get_ports {HEX0[*]}] 9 | set_false_path -from * -to [get_ports {HEX1[*]}] 10 | set_false_path -from * -to [get_ports {HEX2[*]}] 11 | set_false_path -from * -to [get_ports {HEX3[*]}] 12 | set_false_path -from * -to [get_ports {HEX4[*]}] 13 | set_false_path -from * -to [get_ports {HEX5[*]}] 14 | 15 | set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] 16 | set_false_path -from [get_ports {SW[*]}] -to [all_clocks] 17 | -------------------------------------------------------------------------------- /board/rz_easyFPGA_A2.1/rz_easyFPGA_A21.v: -------------------------------------------------------------------------------- 1 | module rz_easyFPGA_A21( 2 | input CLK100MHZ, 3 | input KEY0, 4 | input KEY1, 5 | output [3:0] LED 6 | ); 7 | 8 | // wires & inputs 9 | wire clk; 10 | wire clkIn = CLK100MHZ; 11 | wire rst_n = KEY0; 12 | wire clkEnable = ~KEY1; 13 | wire [ 31:0 ] regData; 14 | 15 | //cores 16 | sm_top sm_top 17 | ( 18 | .clkIn ( clkIn ), 19 | .rst_n ( rst_n ), 20 | .clkDevide ( 4'b1000 ), 21 | .clkEnable ( clkEnable ), 22 | .clk ( clk ), 23 | .regAddr ( 4'b0010 ), 24 | .regData ( regData ) 25 | ); 26 | 27 | //outputs 28 | assign LED[0] = clk; 29 | assign LED[3:1] = regData[2:0]; 30 | 31 | endmodule -------------------------------------------------------------------------------- /board/max_10_evkit/max_10_evkit.v: -------------------------------------------------------------------------------- 1 | module max_10_evkit( 2 | input CLK, 3 | input SW3_1, 4 | input SW3_2, 5 | output [4:0] LED 6 | 7 | ); 8 | 9 | // wires & inputs 10 | wire clk; 11 | wire clkIn = CLK; 12 | wire rst_n = SW3_1; 13 | wire clkEnable = ~SW3_2; 14 | wire [ 31:0 ] regData; 15 | 16 | //cores 17 | sm_top sm_top 18 | ( 19 | .clkIn ( clkIn ), 20 | .rst_n ( rst_n ), 21 | .clkDevide ( 4'b1010 ), 22 | .clkEnable ( clkEnable ), 23 | .clk ( clk ), 24 | .regAddr ( 4'b0010 ), 25 | .regData ( regData ) 26 | ); 27 | 28 | //outputs 29 | assign LED[0] = clk; 30 | assign LED[4:1] = ~{regData[0], regData[1], regData[2], regData[3]}; 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /board/marsohod_3/marsohod_3.v: -------------------------------------------------------------------------------- 1 | 2 | module marsohod_3( 3 | input CLK100MHZ, 4 | input KEY0, 5 | input KEY1, 6 | output [7:0] LED 7 | 8 | ); 9 | 10 | // wires & inputs 11 | wire clk; 12 | wire clkIn = CLK100MHZ; 13 | wire rst_n = KEY0; 14 | wire clkEnable = ~KEY1; 15 | wire [ 31:0 ] regData; 16 | 17 | //cores 18 | sm_top sm_top 19 | ( 20 | .clkIn ( clkIn ), 21 | .rst_n ( rst_n ), 22 | .clkDevide ( 4'b1000 ), 23 | .clkEnable ( clkEnable ), 24 | .clk ( clk ), 25 | .regAddr ( 4'b0010 ), 26 | .regData ( regData ) 27 | ); 28 | 29 | //outputs 30 | assign LED[0] = clk; 31 | assign LED[7:1] = regData[6:0]; 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /board/marsohod_3b/marsohod_3b.v: -------------------------------------------------------------------------------- 1 | 2 | module marsohod_3b( 3 | input CLK100MHZ, 4 | input KEY0, 5 | input KEY1, 6 | output [7:0] LED 7 | 8 | ); 9 | 10 | // wires & inputs 11 | wire clk; 12 | wire clkIn = CLK100MHZ; 13 | wire rst_n = KEY0; 14 | wire clkEnable = ~KEY1; 15 | wire [ 31:0 ] regData; 16 | 17 | //cores 18 | sm_top sm_top 19 | ( 20 | .clkIn ( clkIn ), 21 | .rst_n ( rst_n ), 22 | .clkDevide ( 4'b1000 ), 23 | .clkEnable ( clkEnable ), 24 | .clk ( clk ), 25 | .regAddr ( 4'b0010 ), 26 | .regData ( regData ) 27 | ); 28 | 29 | //outputs 30 | assign LED[0] = clk; 31 | assign LED[7:1] = regData[6:0]; 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /board/de0_nano/de0_nano.sdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50] 3 | 4 | # for enhancing USB BlasterII to be reliable, 25MHz 5 | create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} 6 | set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi] 7 | set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms] 8 | set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo] 9 | 10 | derive_pll_clocks 11 | 12 | derive_clock_uncertainty 13 | create_generated_clock -name {clk} -divide_by 2 -source [get_ports {FPGA_CLK1_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}] 14 | 15 | set_false_path -from * -to [get_ports {LED[*]}] 16 | 17 | set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] 18 | set_false_path -from [get_ports {SW[*]}] -to [all_clocks] 19 | 20 | -------------------------------------------------------------------------------- /board/de10_lite/de10_lite.sdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period "10.0 MHz" [get_ports ADC_CLK_10] 3 | create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50] 4 | create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50] 5 | 6 | derive_clock_uncertainty 7 | create_generated_clock -name {clk} -divide_by 2 -source [get_ports {MAX10_CLK1_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}] 8 | 9 | set_false_path -from * -to [get_ports {LEDR[*]}] 10 | set_false_path -from * -to [get_ports {HEX0[*]}] 11 | set_false_path -from * -to [get_ports {HEX1[*]}] 12 | set_false_path -from * -to [get_ports {HEX2[*]}] 13 | set_false_path -from * -to [get_ports {HEX3[*]}] 14 | set_false_path -from * -to [get_ports {HEX4[*]}] 15 | set_false_path -from * -to [get_ports {HEX5[*]}] 16 | 17 | set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] 18 | set_false_path -from [get_ports {SW[*]}] -to [all_clocks] 19 | -------------------------------------------------------------------------------- /board/de0/de0_top.sdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period "50.0 MHz" [get_ports CLOCK_50] 3 | create_clock -period "50.0 MHz" [get_ports CLOCK_50_2] 4 | 5 | derive_clock_uncertainty 6 | create_generated_clock -name {clk} -divide_by 2 -source [get_ports {CLOCK_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}] 7 | 8 | set_false_path -from * -to [get_ports {LEDG[*]}] 9 | set_false_path -from * -to [get_ports {HEX0_D[*]}] 10 | set_false_path -from * -to [get_ports {HEX1_D[*]}] 11 | set_false_path -from * -to [get_ports {HEX2_D[*]}] 12 | set_false_path -from * -to [get_ports {HEX3_D[*]}] 13 | set_false_path -from * -to [get_ports {HEX0_DP}] 14 | set_false_path -from * -to [get_ports {HEX1_DP}] 15 | set_false_path -from * -to [get_ports {HEX2_DP}] 16 | set_false_path -from * -to [get_ports {HEX3_DP}] 17 | 18 | set_false_path -from [get_ports {BUTTON[*]}] -to [all_clocks] 19 | set_false_path -from [get_ports {SW[*]}] -to [all_clocks] 20 | -------------------------------------------------------------------------------- /board/de0_nano/de0_nano.v: -------------------------------------------------------------------------------- 1 | 2 | module de0_nano 3 | ( 4 | input FPGA_CLK1_50, 5 | input [ 1:0] KEY, 6 | output [ 7:0] LED, 7 | input [ 3:0] SW 8 | ); 9 | 10 | // wires & inputs 11 | wire clk; 12 | wire clkIn = FPGA_CLK1_50; 13 | wire rst_n = KEY[0]; 14 | wire clkEnable = ~KEY[1]; 15 | wire [ 3:0 ] clkDevide = 4'b1000; 16 | wire [ 4:0 ] regAddr = { 1'b0, SW [3:0] }; 17 | wire [ 31:0 ] regData; 18 | 19 | //cores 20 | sm_top sm_top 21 | ( 22 | .clkIn ( clkIn ), 23 | .rst_n ( rst_n ), 24 | .clkDevide ( clkDevide ), 25 | .clkEnable ( clkEnable ), 26 | .clk ( clk ), 27 | .regAddr ( regAddr ), 28 | .regData ( regData ) 29 | ); 30 | 31 | //outputs 32 | assign LED[0] = clk; 33 | assign LED[7:1] = regData[6:0]; 34 | 35 | endmodule -------------------------------------------------------------------------------- /board/de0_cv/de0_cv.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 20 [get_ports CLOCK_50] 2 | create_clock -period 20 [get_ports CLOCK2_50] 3 | create_clock -period 20 [get_ports CLOCK3_50] 4 | create_clock -period 20 [get_ports CLOCK4_50] 5 | 6 | derive_clock_uncertainty 7 | create_generated_clock -name {clk} -divide_by 2 -source [get_ports {CLOCK_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}] 8 | 9 | set_false_path -from * -to [get_ports {LEDR[*]}] 10 | set_false_path -from * -to [get_ports {HEX0[*]}] 11 | set_false_path -from * -to [get_ports {HEX1[*]}] 12 | set_false_path -from * -to [get_ports {HEX2[*]}] 13 | set_false_path -from * -to [get_ports {HEX3[*]}] 14 | set_false_path -from * -to [get_ports {HEX4[*]}] 15 | set_false_path -from * -to [get_ports {HEX5[*]}] 16 | 17 | set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] 18 | set_false_path -from [get_ports {SW[*]}] -to [all_clocks] 19 | set_false_path -from [get_ports {RESET_N}] -to [all_clocks] 20 | -------------------------------------------------------------------------------- /board/de10_nano/de10_nano.sdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50] 3 | create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50] 4 | create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50] 5 | 6 | # for enhancing USB BlasterII to be reliable, 25MHz 7 | create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} 8 | set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi] 9 | set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms] 10 | set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo] 11 | 12 | derive_pll_clocks 13 | 14 | derive_clock_uncertainty 15 | create_generated_clock -name {clk} -divide_by 2 -source [get_ports {FPGA_CLK1_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}] 16 | 17 | set_false_path -from * -to [get_ports {LED[*]}] 18 | 19 | set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] 20 | set_false_path -from [get_ports {SW[*]}] -to [all_clocks] 21 | 22 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2017 Stanislav Zhelnio, 4 | Alexander Romanov 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | -------------------------------------------------------------------------------- /program/02_sqrt/main.S: -------------------------------------------------------------------------------- 1 | 2 | ## unsigned isqrt (unsigned x) { 3 | ## unsigned m, y, b; 4 | ## m = 0x40000000; 5 | ## y = 0; 6 | ## while (m != 0) { // Do 16 times 7 | ## b = y | m; 8 | ## y >>= 1; 9 | ## if (x >= b) { 10 | ## x -= b; 11 | ## y |= m; 12 | ## } 13 | ## m >>= 2; 14 | ## } 15 | ## return y; 16 | ## } 17 | 18 | .text 19 | 20 | init: li $a0, 82 ## x = 82 21 | li $v0, 0 ## calculation result reset 22 | 23 | sqrt: lui $t0, 0x4000 ## m = 0x40000000 24 | move $t1, $0 ## y = 0 25 | 26 | L0: or $t2, $t1, $t0 ## b = y | m; 27 | srl $t1, $t1, 1 ## y >>= 1 28 | sltu $t3, $a0, $t2 ## if (x < b) 29 | bnez $t3, L1 ## goto L1 30 | ## else 31 | subu $a0, $a0, $t2 ## x -= b 32 | or $t1, $t1, $t0 ## y |= m 33 | 34 | L1: srl $t0, $t0, 2 ## m >>= 2 35 | bnez $t0, L0 ## if(m != 0) goto L0 36 | move $v0, $t1 ## return y 37 | 38 | end: beqz $0, end ## while(1); 39 | -------------------------------------------------------------------------------- /board/de4_230/DE4_230.sdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 20 [get_ports OSC_50_BANK2] 3 | create_clock -period 20 [get_ports OSC_50_BANK3] 4 | create_clock -period 20 [get_ports OSC_50_BANK4] 5 | create_clock -period 20 [get_ports OSC_50_BANK5] 6 | create_clock -period 20 [get_ports OSC_50_BANK6] 7 | create_clock -period 20 [get_ports OSC_50_BANK7] 8 | 9 | derive_pll_clocks 10 | 11 | derive_clock_uncertainty 12 | create_generated_clock -name {clk} -divide_by 2 -source [get_ports {OSC_50_BANK2}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}] 13 | 14 | set_false_path -from * -to [get_ports {LED[*]}] 15 | set_false_path -from * -to [get_ports {SEG0_D[*]}] 16 | set_false_path -from * -to [get_ports {SEG1_D[*]}] 17 | set_false_path -from * -to [get_ports {SEG0_DP}] 18 | set_false_path -from * -to [get_ports {SEG1_DP}] 19 | set_false_path -from * -to [get_ports {HEX4[*]}] 20 | set_false_path -from * -to [get_ports {HEX5[*]}] 21 | 22 | set_false_path -from [get_ports {SLIDE_SW[*]}] -to [all_clocks] 23 | set_false_path -from [get_ports {BUTTON[*]}] -to [all_clocks] 24 | set_false_path -from [get_ports {SW[*]}] -to [all_clocks] 25 | set_false_path -from [get_ports {CPU_RESET_n}] -to [all_clocks] 26 | -------------------------------------------------------------------------------- /board/max_10_evkit/README.md: -------------------------------------------------------------------------------- 1 | # MAX 10 FPGA Evaluation Kit 2 | ## Описание платы 3 | Max 10 FPGA Evaluation Kit отладочная плата компании Intel начального уровня. В плате используется микросхема 10M08SAE144C8G серии MAX 10. 4 | 5 | ![board](images/max_10_eval_board.jpg) 6 | 7 | Плата включает следующие компоненты: 8 | 9 | - Микросхема серии MAX10 FPGA 10 | - Intel Enpirion® EP5388QI DC-DC понижающий преобразователь 11 | - JTAG разъем для программирования платы 12 | - Тактовый генератор на 50МГц 13 | - АЦП встроенный в микросхему MAX 10 14 | - Переключатели, кнопки, перемычки и сигнальные светодиоды 15 | - Пробная точка для измерения питания микросхемы 16 | - Разъемы формата Arduino UNO для подключения переферии 17 | - Отверстия GPIO для подключения переферии 18 | - Mini-USB разъем для питания платы 19 | ![board](images/sch.jpg) 20 | 21 | Для программирования платы используется внешний программатор, подключаемый через JTAG разъем. 22 | 23 | ![board](images/blaster.jpg) 24 | 25 | ## Ссылки 26 | 1. [Страница с описание платы MAX 10 FPGA Evaluation Kit на сайте Intel](https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-max-10-evaluation.html#Contents) 27 | 2. [Руководство пользователя платы MAX 10 FPGA Evaluation Kit](https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_max10_eval_10m80.pdf) 28 | 29 | -------------------------------------------------------------------------------- /board/de10_standard/de10_standard.sdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period "50.000000 MHz" [get_ports CLOCK2_50] 3 | create_clock -period "50.000000 MHz" [get_ports CLOCK3_50] 4 | create_clock -period "50.000000 MHz" [get_ports CLOCK4_50] 5 | create_clock -period "50.000000 MHz" [get_ports CLOCK_50] 6 | 7 | # for enhancing USB BlasterII to be reliable, 25MHz 8 | create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} 9 | set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi] 10 | set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms] 11 | set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo] 12 | 13 | derive_clock_uncertainty 14 | create_generated_clock -name {clk} -divide_by 2 -source [get_ports {CLOCK_50}] [get_registers {sm_top:sm_top|sm_clk_divider:sm_clk_divider|sm_register_we:r_cntr|q[*]}] 15 | 16 | set_false_path -from * -to [get_ports {LEDR[*]}] 17 | set_false_path -from * -to [get_ports {HEX0[*]}] 18 | set_false_path -from * -to [get_ports {HEX1[*]}] 19 | set_false_path -from * -to [get_ports {HEX2[*]}] 20 | set_false_path -from * -to [get_ports {HEX3[*]}] 21 | set_false_path -from * -to [get_ports {HEX4[*]}] 22 | set_false_path -from * -to [get_ports {HEX5[*]}] 23 | 24 | set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] 25 | set_false_path -from [get_ports {SW[*]}] -to [all_clocks] 26 | 27 | 28 | -------------------------------------------------------------------------------- /board/max_10_evkit/max_10_evkit.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2016 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Intel and sold by Intel or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition 22 | # Date created = 01:07:42 September 23, 2019 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "16.1" 27 | DATE = "01:07:42 September 23, 2019" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "max_10_evkit" 32 | -------------------------------------------------------------------------------- /board/zeowaa/zeowaa.v: -------------------------------------------------------------------------------- 1 | 2 | module zeowaa 3 | ( 4 | input clk_50, 5 | input [ 5:2] key, 6 | input [ 7:0] sw, 7 | output [11:0] led, 8 | output [ 7:0] hex, 9 | output [ 7:0] digit, 10 | output buzzer 11 | ); 12 | // wires & inputs 13 | wire clkCpu; 14 | wire clkIn = clk_50; 15 | wire rst_n = key[4]; 16 | wire clkEnable = ~sw[ 7] | ~key[5]; 17 | wire [ 3:0 ] clkDevide = { ~sw[6:5], 2'b00 }; 18 | wire [ 4:0 ] regAddr = ~sw[4:0]; 19 | wire [ 31:0 ] regData; 20 | 21 | //cores 22 | sm_top sm_top 23 | ( 24 | .clkIn ( clkIn ), 25 | .rst_n ( rst_n ), 26 | .clkDevide ( clkDevide ), 27 | .clkEnable ( clkEnable ), 28 | .clk ( clkCpu ), 29 | .regAddr ( regAddr ), 30 | .regData ( regData ) 31 | ); 32 | 33 | //outputs 34 | assign led[0] = ~clkCpu; 35 | assign led[11:1] = ~regData[11:0]; 36 | 37 | //hex out 38 | wire [ 31:0 ] h7segment = regData; 39 | wire clkHex; 40 | 41 | sm_clk_divider hex_clk_divider 42 | ( 43 | .clkIn ( clkIn ), 44 | .rst_n ( rst_n ), 45 | .devide ( 4'b0 ), 46 | .enable ( 1'b1 ), 47 | .clkOut ( clkHex ) 48 | ); 49 | 50 | sm_hex_display_8 sm_hex_display_8 51 | ( 52 | .clock ( clkHex ), 53 | .resetn ( rst_n ), 54 | .number ( h7segment ), 55 | .seven_segments ( hex[6:0] ), 56 | .dot ( hex[7] ), 57 | .anodes ( digit ) 58 | ); 59 | 60 | assign buzzer = 1'b1; 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /board/de10_nano/de10_nano.v: -------------------------------------------------------------------------------- 1 | 2 | module de10_nano 3 | ( 4 | output ADC_CONVST, 5 | output ADC_SCK, 6 | output ADC_SDI, 7 | input ADC_SDO, 8 | 9 | inout [15:0] ARDUINO_IO, 10 | inout ARDUINO_RESET_N, 11 | 12 | input FPGA_CLK1_50, 13 | input FPGA_CLK2_50, 14 | input FPGA_CLK3_50, 15 | 16 | inout HDMI_I2C_SCL, 17 | inout HDMI_I2C_SDA, 18 | inout HDMI_I2S, 19 | inout HDMI_LRCLK, 20 | inout HDMI_MCLK, 21 | inout HDMI_SCLK, 22 | output HDMI_TX_CLK, 23 | output HDMI_TX_DE, 24 | output [23:0] HDMI_TX_D, 25 | output HDMI_TX_HS, 26 | input HDMI_TX_INT, 27 | output HDMI_TX_VS, 28 | 29 | input [ 1:0] KEY, 30 | output [ 7:0] LED, 31 | input [ 3:0] SW, 32 | 33 | inout [35:0] GPIO_0, 34 | inout [35:0] GPIO_1 35 | ); 36 | 37 | // wires & inputs 38 | wire clk; 39 | wire clkIn = FPGA_CLK1_50; 40 | wire rst_n = KEY[0]; 41 | wire clkEnable = ~KEY[1]; 42 | wire [ 3:0 ] clkDevide = 4'b1000; 43 | wire [ 4:0 ] regAddr = { 1'b0, SW [3:0] }; 44 | wire [ 31:0 ] regData; 45 | 46 | //cores 47 | sm_top sm_top 48 | ( 49 | .clkIn ( clkIn ), 50 | .rst_n ( rst_n ), 51 | .clkDevide ( clkDevide ), 52 | .clkEnable ( clkEnable ), 53 | .clk ( clk ), 54 | .regAddr ( regAddr ), 55 | .regData ( regData ) 56 | ); 57 | 58 | //outputs 59 | assign LED[0] = clk; 60 | assign LED[7:1] = regData[6:0]; 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # schoolMIPS 2 | 3 | A small MIPS CPU core originally based on Sarah L. Harris MIPS CPU ("Digital Design and Computer Arhitecture" by David Money Harris and Sarah L Harris). The first version of schoolMIPS was written for [Young Russian Chip Architects](http://www.silicon-russia.com/2017/06/09/arduino-and-fpga/) summer school. 4 | 5 | Next version of schoolMIPS is based on RISC-V architecture: [schoolRISCV](https://github.com/zhelnio/schoolRISCV) 6 | 7 | The CPU have several versions (from simple to complex). Each of them is placed in the separate git branch: 8 | - **00_simple** - the simplest CPU without data memory, programs compiled with GNU gcc; 9 | - **01_mmio** - the same but with data memory, simple system bus and peripherals (pwm, gpio, als); 10 | - **01_mmio_sv_dpi** - the same but with data memory, simple system bus and peripherals (pwm, gpio, als); 11 | - **02_irq** - data memory, system timer, interrupts and exceptions (CP0 coprocessor); 12 | - **03_pipeline** - the pipelined version of the simplest core with data memory 13 | - **04_pipeline_irq** - the pipelined version of 02_irq 14 | 15 | Examples of using this kernel as an element of a multiprocessor system: 16 | 1. A.E. Ryazanova, A.A. Amerikanov, E. V Lezhnev, Development of multiprocessor system-on-chip based on soft processor cores schoolMIPS, J. Phys. Conf. Ser. 1163 (2019) 012026. [doi:10.1088/1742-6596/1163/1/012026](https://iopscience.iop.org/article/10.1088/1742-6596/1163/1/012026). 17 | 2. [Innovate FPGA 2019 project: EM028 » NoC-based multiprocessing system prototype](http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=EM028) 18 | 19 | For docs and CPU diagrams please visit the project [wiki](https://github.com/MIPSfpga/schoolMIPS/wiki) 20 | 21 | ![CPU diagram](../../wiki/img/schoolMIPS_diagram.gif) 22 | -------------------------------------------------------------------------------- /scripts/program/common/04_simulate_with_icarus.bat: -------------------------------------------------------------------------------- 1 | 2 | echo off 3 | 4 | rem START Simulation default params 5 | 6 | rem testbench top module name 7 | set TOPMODULE=sm_testbench 8 | rem simulation clock cycles count 9 | set SIMULATION_CYCLES=120 10 | 11 | rem END Simulation default params 12 | 13 | rem read simulation params from local icarus config file 14 | for /f "delims=" %%x in (icarus.cfg) do (set "%%x") 15 | 16 | rem iverilog compile settings 17 | set IVARG=-g2005 18 | set IVARG=%IVARG% -D SIMULATION 19 | set IVARG=%IVARG% -D ICARUS 20 | set IVARG=%IVARG% -D SIMULATION_CYCLES=%SIMULATION_CYCLES% 21 | set IVARG=%IVARG% -I ..\..\..\src 22 | set IVARG=%IVARG% -I ..\..\..\testbench 23 | set IVARG=%IVARG% -s %TOPMODULE% 24 | set IVARG=%IVARG% ..\..\..\src\*.v 25 | set IVARG=%IVARG% ..\..\..\testbench\*.v 26 | 27 | rem checks that iverilog & vvp are installed 28 | where iverilog.exe 29 | if errorlevel 1 ( 30 | echo "iverilog.exe not found!" 31 | echo "Please install IVERILOG and add 'iverilog\bin' and 'iverilog\gtkwave\bin' directories to PATH" 32 | goto return 33 | ) 34 | 35 | where vvp.exe 36 | if errorlevel 1 ( 37 | echo "vvp.exe not found!" 38 | echo "Please install IVERILOG and add 'iverilog\bin' and 'iverilog\gtkwave\bin' directories to PATH" 39 | goto return 40 | ) 41 | 42 | where gtkwave.exe 43 | if errorlevel 1 ( 44 | echo "gtkwave.exe not found!" 45 | echo "Please install IVERILOG and add 'iverilog\bin' and 'iverilog\gtkwave\bin' directories to PATH" 46 | goto return 47 | ) 48 | 49 | rem old simulation clear 50 | rd /s /q sim 51 | md sim 52 | cd sim 53 | 54 | copy ..\*.hex . 55 | 56 | rem compile 57 | iverilog %IVARG% 58 | 59 | rem simulation 60 | vvp -la.lst -n a.out -vcd 61 | 62 | rem output 63 | gtkwave dump.vcd 64 | 65 | cd .. 66 | 67 | :return 68 | -------------------------------------------------------------------------------- /board/de4_230/de4_230.v: -------------------------------------------------------------------------------- 1 | 2 | module de4_230 3 | ( 4 | input GCLKIN, 5 | output GCLKOUT_FPGA, 6 | input OSC_50_BANK2, 7 | input OSC_50_BANK3, 8 | input OSC_50_BANK4, 9 | input OSC_50_BANK5, 10 | input OSC_50_BANK6, 11 | input OSC_50_BANK7, 12 | input PLL_CLKIN_p, 13 | 14 | output [7:0] LED, 15 | input [3:0] BUTTON, 16 | input CPU_RESET_n, // CPU Reset Push Button 17 | inout EXT_IO, 18 | input [7:0] SW, // DIP Switches 19 | input [3:0] SLIDE_SW, // Slide switches 20 | output [6:0] SEG0_D, 21 | output SEG0_DP, 22 | output [6:0] SEG1_D, 23 | output SEG1_DP 24 | ); 25 | 26 | // wires & inputs 27 | wire clk; 28 | wire clkIn = OSC_50_BANK2; 29 | wire rst_n = CPU_RESET_n; 30 | wire clkEnable = SW [7] | ~BUTTON[0]; 31 | wire [ 3:0 ] clkDevide = SW [3:0]; 32 | wire [ 4:0 ] regAddr = { ~BUTTON[1], SLIDE_SW }; 33 | wire [ 31:0 ] regData; 34 | 35 | //cores 36 | sm_top sm_top 37 | ( 38 | .clkIn ( clkIn ), 39 | .rst_n ( rst_n ), 40 | .clkDevide ( clkDevide ), 41 | .clkEnable ( clkEnable ), 42 | .clk ( clk ), 43 | .regAddr ( regAddr ), 44 | .regData ( regData ) 45 | ); 46 | 47 | //outputs 48 | assign LED[0] = clk; 49 | assign LED[7:1] = regData[6:0]; 50 | 51 | wire [ 31:0 ] h7segment = regData; 52 | 53 | assign SEG0_DP = 1'b1; 54 | assign SEG1_DP = 1'b1; 55 | 56 | sm_hex_display digit_1 ( h7segment [ 7: 4] , SEG1_D ); 57 | sm_hex_display digit_0 ( h7segment [ 3: 0] , SEG0_D ); 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /src/sm_cpu.vh: -------------------------------------------------------------------------------- 1 | /* 2 | * schoolMIPS - small MIPS CPU for "Young Russian Chip Architects" 3 | * summer school ( yrca@googlegroups.com ) 4 | * 5 | * originally based on Sarah L. Harris MIPS CPU 6 | * 7 | * Copyright(c) 2017 Stanislav Zhelnio 8 | * Aleksandr Romanov 9 | */ 10 | 11 | //ALU commands 12 | `define ALU_ADD 3'b000 13 | `define ALU_OR 3'b001 14 | `define ALU_LUI 3'b010 15 | `define ALU_SRL 3'b011 16 | `define ALU_SLTU 3'b100 17 | `define ALU_SUBU 3'b101 18 | 19 | //instruction operation code 20 | `define C_SPEC 6'b000000 // Special instructions (depends on function field) 21 | `define C_ADDIU 6'b001001 // I-type, Integer Add Immediate Unsigned 22 | // Rd = Rs + Immed 23 | `define C_BEQ 6'b000100 // I-type, Branch On Equal 24 | // if (Rs == Rt) PC += (int)offset 25 | `define C_LUI 6'b001111 // I-type, Load Upper Immediate 26 | // Rt = Immed << 16 27 | `define C_BNE 6'b000101 // I-type, Branch on Not Equal 28 | // if (Rs != Rt) PC += (int)offset 29 | 30 | //instruction function field 31 | `define F_ADDU 6'b100001 // R-type, Integer Add Unsigned 32 | // Rd = Rs + Rt 33 | `define F_OR 6'b100101 // R-type, Logical OR 34 | // Rd = Rs | Rt 35 | `define F_SRL 6'b000010 // R-type, Shift Right Logical 36 | // Rd = Rs∅ >> shift 37 | `define F_SLTU 6'b101011 // R-type, Set on Less Than Unsigned 38 | // Rd = (Rs∅ < Rt∅) ? 1 : 0 39 | `define F_SUBU 6'b100011 // R-type, Unsigned Subtract 40 | // Rd = Rs – Rt 41 | `define F_ANY 6'b?????? 42 | -------------------------------------------------------------------------------- /board/de10_standard/de10_standard.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module de10_standard 4 | ( 5 | input CLOCK2_50, 6 | input CLOCK3_50, 7 | input CLOCK4_50, 8 | input CLOCK_50, 9 | 10 | input [3:0] KEY, 11 | 12 | input [9:0] SW, 13 | 14 | output [9:0] LEDR, 15 | 16 | output [6:0] HEX0, 17 | output [6:0] HEX1, 18 | output [6:0] HEX2, 19 | output [6:0] HEX3, 20 | output [6:0] HEX4, 21 | output [6:0] HEX5 22 | ); 23 | 24 | // wires & inputs 25 | wire clk; 26 | wire clkIn = CLOCK_50; 27 | wire rst_n = KEY[0]; 28 | wire clkEnable = SW [9] | ~KEY[1]; 29 | wire [ 3:0 ] clkDevide = SW [8:5]; 30 | wire [ 4:0 ] regAddr = SW [4:0]; 31 | wire [ 31:0 ] regData; 32 | 33 | //cores 34 | sm_top sm_top 35 | ( 36 | .clkIn ( clkIn ), 37 | .rst_n ( rst_n ), 38 | .clkDevide ( clkDevide ), 39 | .clkEnable ( clkEnable ), 40 | .clk ( clk ), 41 | .regAddr ( regAddr ), 42 | .regData ( regData ) 43 | ); 44 | 45 | //outputs 46 | assign LEDR[0] = clk; 47 | assign LEDR[9:1] = regData[8:0]; 48 | 49 | wire [ 31:0 ] h7segment = regData; 50 | 51 | sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] ); 52 | sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] ); 53 | sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] ); 54 | sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] ); 55 | sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] ); 56 | sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] ); 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /board/de10_lite/de10_lite.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module de10_lite( 4 | 5 | input ADC_CLK_10, 6 | input MAX10_CLK1_50, 7 | input MAX10_CLK2_50, 8 | 9 | output [ 7:0 ] HEX0, 10 | output [ 7:0 ] HEX1, 11 | output [ 7:0 ] HEX2, 12 | output [ 7:0 ] HEX3, 13 | output [ 7:0 ] HEX4, 14 | output [ 7:0 ] HEX5, 15 | 16 | input [ 1:0 ] KEY, 17 | 18 | output [ 9:0 ] LEDR, 19 | 20 | input [ 9:0 ] SW, 21 | 22 | inout [ 35:0 ] GPIO 23 | ); 24 | 25 | // wires & inputs 26 | wire clk; 27 | wire clkIn = MAX10_CLK1_50; 28 | wire rst_n = KEY[0]; 29 | wire clkEnable = SW [9] | ~KEY[1]; 30 | wire [ 3:0 ] clkDevide = SW [8:5]; 31 | wire [ 4:0 ] regAddr = SW [4:0]; 32 | wire [ 31:0 ] regData; 33 | 34 | //cores 35 | sm_top sm_top 36 | ( 37 | .clkIn ( clkIn ), 38 | .rst_n ( rst_n ), 39 | .clkDevide ( clkDevide ), 40 | .clkEnable ( clkEnable ), 41 | .clk ( clk ), 42 | .regAddr ( regAddr ), 43 | .regData ( regData ) 44 | ); 45 | 46 | //outputs 47 | assign LEDR[0] = clk; 48 | assign LEDR[9:1] = regData[8:0]; 49 | 50 | wire [ 31:0 ] h7segment = regData; 51 | 52 | assign HEX0 [7] = 1'b1; 53 | assign HEX1 [7] = 1'b1; 54 | assign HEX2 [7] = 1'b1; 55 | assign HEX3 [7] = 1'b1; 56 | assign HEX4 [7] = 1'b1; 57 | assign HEX5 [7] = 1'b1; 58 | 59 | sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] ); 60 | sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] ); 61 | sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] ); 62 | sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] ); 63 | sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] ); 64 | sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] ); 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /src/sm_top.v: -------------------------------------------------------------------------------- 1 | 2 | //hardware top level module 3 | module sm_top 4 | ( 5 | input clkIn, 6 | input rst_n, 7 | input [ 3:0 ] clkDevide, 8 | input clkEnable, 9 | output clk, 10 | input [ 4:0 ] regAddr, 11 | output [31:0 ] regData 12 | ); 13 | //metastability input filters 14 | wire [ 3:0 ] devide; 15 | wire enable; 16 | wire [ 4:0 ] addr; 17 | 18 | sm_debouncer #(.SIZE(4)) f0(clkIn, clkDevide, devide); 19 | sm_debouncer #(.SIZE(1)) f1(clkIn, clkEnable, enable); 20 | sm_debouncer #(.SIZE(5)) f2(clkIn, regAddr, addr ); 21 | 22 | //cores 23 | //clock devider 24 | sm_clk_divider sm_clk_divider 25 | ( 26 | .clkIn ( clkIn ), 27 | .rst_n ( rst_n ), 28 | .devide ( devide ), 29 | .enable ( enable ), 30 | .clkOut ( clk ) 31 | ); 32 | 33 | //instruction memory 34 | wire [31:0] imAddr; 35 | wire [31:0] imData; 36 | sm_rom reset_rom(imAddr, imData); 37 | 38 | sm_cpu sm_cpu 39 | ( 40 | .clk ( clk ), 41 | .rst_n ( rst_n ), 42 | .regAddr ( addr ), 43 | .regData ( regData ), 44 | .imAddr ( imAddr ), 45 | .imData ( imData ) 46 | ); 47 | 48 | endmodule 49 | 50 | //metastability input debouncer module 51 | module sm_debouncer 52 | #( 53 | parameter SIZE = 1 54 | ) 55 | ( 56 | input clk, 57 | input [ SIZE - 1 : 0] d, 58 | output reg [ SIZE - 1 : 0] q 59 | ); 60 | reg [ SIZE - 1 : 0] data; 61 | 62 | always @ (posedge clk) begin 63 | data <= d; 64 | q <= data; 65 | end 66 | 67 | endmodule 68 | 69 | //tunable clock devider 70 | module sm_clk_divider 71 | #( 72 | parameter shift = 16, 73 | bypass = 0 74 | ) 75 | ( 76 | input clkIn, 77 | input rst_n, 78 | input [ 3:0 ] devide, 79 | input enable, 80 | output clkOut 81 | ); 82 | wire [31:0] cntr; 83 | wire [31:0] cntrNext = cntr + 1; 84 | sm_register_we r_cntr(clkIn, rst_n, enable, cntrNext, cntr); 85 | 86 | assign clkOut = bypass ? clkIn 87 | : cntr[shift + devide]; 88 | endmodule 89 | -------------------------------------------------------------------------------- /board/nexys4/nexys4.v: -------------------------------------------------------------------------------- 1 | 2 | module nexys4 3 | ( 4 | input clk, 5 | input btnCpuReset, 6 | 7 | input btnC, 8 | input btnU, 9 | input btnL, 10 | input btnR, 11 | input btnD, 12 | 13 | input [15:0] sw, 14 | 15 | output [15:0] led, 16 | 17 | output RGB1_Red, 18 | output RGB1_Green, 19 | output RGB1_Blue, 20 | output RGB2_Red, 21 | output RGB2_Green, 22 | output RGB2_Blue, 23 | 24 | output [ 6:0] seg, 25 | output dp, 26 | output [ 7:0] an, 27 | 28 | inout [ 7:0] JA, 29 | inout [ 7:0] JB, 30 | 31 | input RsRx 32 | ); 33 | // wires & inputs 34 | wire clkCpu; 35 | wire clkIn = clk; 36 | wire rst_n = btnCpuReset; 37 | wire clkEnable = sw [9] | btnU; 38 | wire [ 3:0 ] clkDevide = sw [8:5]; 39 | wire [ 4:0 ] regAddr = sw [4:0]; 40 | wire [ 31:0 ] regData; 41 | 42 | //cores 43 | sm_top sm_top 44 | ( 45 | .clkIn ( clkIn ), 46 | .rst_n ( rst_n ), 47 | .clkDevide ( clkDevide ), 48 | .clkEnable ( clkEnable ), 49 | .clk ( clkCpu ), 50 | .regAddr ( regAddr ), 51 | .regData ( regData ) 52 | ); 53 | 54 | //outputs 55 | assign led[0] = clkCpu; 56 | assign led[15:1] = regData[14:0]; 57 | 58 | //hex out 59 | wire [ 31:0 ] h7segment = regData; 60 | wire clkHex; 61 | 62 | sm_clk_divider hex_clk_divider 63 | ( 64 | .clkIn ( clkIn ), 65 | .rst_n ( rst_n ), 66 | .devide ( 4'b1 ), 67 | .enable ( 1'b1 ), 68 | .clkOut ( clkHex ) 69 | ); 70 | 71 | sm_hex_display_8 sm_hex_display_8 72 | ( 73 | .clock ( clkHex ), 74 | .resetn ( rst_n ), 75 | .number ( h7segment ), 76 | 77 | .seven_segments ( seg ), 78 | .dot ( dp ), 79 | .anodes ( an ) 80 | ); 81 | 82 | assign RGB1_Red = 1'b0; 83 | assign RGB1_Green = 1'b0; 84 | assign RGB1_Blue = 1'b0; 85 | assign RGB2_Red = 1'b0; 86 | assign RGB2_Green = 1'b0; 87 | assign RGB2_Blue = 1'b0; 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /board/nexys4_ddr/nexys4_ddr.v: -------------------------------------------------------------------------------- 1 | 2 | module nexys4_ddr 3 | ( 4 | input CLK100MHZ, 5 | input CPU_RESETN, 6 | 7 | input BTNC, 8 | input BTNU, 9 | input BTNL, 10 | input BTNR, 11 | input BTND, 12 | 13 | input [15:0] SW, 14 | 15 | output [15:0] LED, 16 | 17 | output LED16_B, 18 | output LED16_G, 19 | output LED16_R, 20 | output LED17_B, 21 | output LED17_G, 22 | output LED17_R, 23 | 24 | output CA, 25 | output CB, 26 | output CC, 27 | output CD, 28 | output CE, 29 | output CF, 30 | output CG, 31 | output DP, 32 | 33 | output [ 7:0] AN, 34 | 35 | inout [12:1] JA, 36 | inout [12:1] JB, 37 | 38 | input UART_TXD_IN 39 | ); 40 | 41 | // wires & inputs 42 | wire clk; 43 | wire clkIn = CLK100MHZ; 44 | wire rst_n = CPU_RESETN; 45 | wire clkEnable = SW [9] | BTNU; 46 | wire [ 3:0 ] clkDevide = SW [8:5]; 47 | wire [ 4:0 ] regAddr = SW [4:0]; 48 | wire [ 31:0 ] regData; 49 | 50 | //cores 51 | sm_top sm_top 52 | ( 53 | .clkIn ( clkIn ), 54 | .rst_n ( rst_n ), 55 | .clkDevide ( clkDevide ), 56 | .clkEnable ( clkEnable ), 57 | .clk ( clk ), 58 | .regAddr ( regAddr ), 59 | .regData ( regData ) 60 | ); 61 | 62 | //outputs 63 | assign LED[0] = clk; 64 | assign LED[15:1] = regData[14:0]; 65 | 66 | //hex out 67 | wire [ 31:0 ] h7segment = regData; 68 | wire clkHex; 69 | 70 | sm_clk_divider hex_clk_divider 71 | ( 72 | .clkIn ( clkIn ), 73 | .rst_n ( rst_n ), 74 | .devide ( 4'b1 ), 75 | .enable ( 1'b1 ), 76 | .clkOut ( clkHex ) 77 | ); 78 | 79 | sm_hex_display_8 sm_hex_display_8 80 | ( 81 | .clock ( clkHex ), 82 | .resetn ( rst_n ), 83 | .number ( h7segment ), 84 | 85 | .seven_segments ( { CG, CF, CE, CD, CC, CB, CA } ), 86 | .dot ( DP ), 87 | .anodes ( AN ) 88 | ); 89 | 90 | assign LED16_B = 1'b0; 91 | assign LED16_G = 1'b0; 92 | assign LED16_R = 1'b0; 93 | assign LED17_B = 1'b0; 94 | assign LED17_G = 1'b0; 95 | assign LED17_R = 1'b0; 96 | 97 | endmodule 98 | -------------------------------------------------------------------------------- /board/de0_cv/de0_cv.v: -------------------------------------------------------------------------------- 1 | 2 | module de0_cv 3 | ( 4 | input CLOCK2_50, 5 | input CLOCK3_50, 6 | inout CLOCK4_50, 7 | input CLOCK_50, 8 | 9 | input RESET_N, 10 | 11 | input [ 3:0] KEY, 12 | input [ 9:0] SW, 13 | 14 | output [ 9:0] LEDR, 15 | 16 | output [ 6:0] HEX0, 17 | output [ 6:0] HEX1, 18 | output [ 6:0] HEX2, 19 | output [ 6:0] HEX3, 20 | output [ 6:0] HEX4, 21 | output [ 6:0] HEX5, 22 | 23 | output [12:0] DRAM_ADDR, 24 | output [ 1:0] DRAM_BA, 25 | output DRAM_CAS_N, 26 | output DRAM_CKE, 27 | output DRAM_CLK, 28 | output DRAM_CS_N, 29 | inout [15:0] DRAM_DQ, 30 | output DRAM_LDQM, 31 | output DRAM_RAS_N, 32 | output DRAM_UDQM, 33 | output DRAM_WE_N, 34 | 35 | output [ 3:0] VGA_B, 36 | output [ 3:0] VGA_G, 37 | output VGA_HS, 38 | output [ 3:0] VGA_R, 39 | output VGA_VS, 40 | 41 | inout PS2_CLK, 42 | inout PS2_CLK2, 43 | inout PS2_DAT, 44 | inout PS2_DAT2, 45 | 46 | output SD_CLK, 47 | inout SD_CMD, 48 | inout [ 3:0] SD_DATA, 49 | 50 | inout [35:0] GPIO_0, 51 | inout [35:0] GPIO_1 52 | ); 53 | 54 | // wires & inputs 55 | wire clk; 56 | wire clkIn = CLOCK_50; 57 | wire rst_n = KEY[0] & RESET_N; 58 | wire clkEnable = SW [9] | ~KEY[1]; 59 | wire [ 3:0 ] clkDevide = SW [8:5]; 60 | wire [ 4:0 ] regAddr = SW [4:0]; 61 | wire [ 31:0 ] regData; 62 | 63 | //cores 64 | sm_top sm_top 65 | ( 66 | .clkIn ( clkIn ), 67 | .rst_n ( rst_n ), 68 | .clkDevide ( clkDevide ), 69 | .clkEnable ( clkEnable ), 70 | .clk ( clk ), 71 | .regAddr ( regAddr ), 72 | .regData ( regData ) 73 | ); 74 | 75 | //outputs 76 | assign LEDR[0] = clk; 77 | assign LEDR[9:1] = regData[8:0]; 78 | 79 | wire [ 31:0 ] h7segment = regData; 80 | 81 | sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] ); 82 | sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] ); 83 | sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] ); 84 | sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] ); 85 | sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] ); 86 | sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] ); 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /src/sm_hex_display.v: -------------------------------------------------------------------------------- 1 | 2 | module sm_hex_display 3 | ( 4 | input [3:0] digit, 5 | output reg [6:0] seven_segments 6 | ); 7 | 8 | always @* 9 | case (digit) 10 | 'h0: seven_segments = 'b1000000; // g f e d c b a 11 | 'h1: seven_segments = 'b1111001; 12 | 'h2: seven_segments = 'b0100100; // --a-- 13 | 'h3: seven_segments = 'b0110000; // | | 14 | 'h4: seven_segments = 'b0011001; // f b 15 | 'h5: seven_segments = 'b0010010; // | | 16 | 'h6: seven_segments = 'b0000010; // --g-- 17 | 'h7: seven_segments = 'b1111000; // | | 18 | 'h8: seven_segments = 'b0000000; // e c 19 | 'h9: seven_segments = 'b0011000; // | | 20 | 'ha: seven_segments = 'b0001000; // --d-- 21 | 'hb: seven_segments = 'b0000011; 22 | 'hc: seven_segments = 'b1000110; 23 | 'hd: seven_segments = 'b0100001; 24 | 'he: seven_segments = 'b0000110; 25 | 'hf: seven_segments = 'b0001110; 26 | endcase 27 | 28 | endmodule 29 | 30 | //-------------------------------------------------------------------- 31 | 32 | module sm_hex_display_8 33 | ( 34 | input clock, 35 | input resetn, 36 | input [31:0] number, 37 | 38 | output reg [ 6:0] seven_segments, 39 | output reg dot, 40 | output reg [ 7:0] anodes 41 | ); 42 | 43 | function [6:0] bcd_to_seg (input [3:0] bcd); 44 | 45 | case (bcd) 46 | 'h0: bcd_to_seg = 'b1000000; // g f e d c b a 47 | 'h1: bcd_to_seg = 'b1111001; 48 | 'h2: bcd_to_seg = 'b0100100; // --a-- 49 | 'h3: bcd_to_seg = 'b0110000; // | | 50 | 'h4: bcd_to_seg = 'b0011001; // f b 51 | 'h5: bcd_to_seg = 'b0010010; // | | 52 | 'h6: bcd_to_seg = 'b0000010; // --g-- 53 | 'h7: bcd_to_seg = 'b1111000; // | | 54 | 'h8: bcd_to_seg = 'b0000000; // e c 55 | 'h9: bcd_to_seg = 'b0011000; // | | 56 | 'ha: bcd_to_seg = 'b0001000; // --d-- 57 | 'hb: bcd_to_seg = 'b0000011; 58 | 'hc: bcd_to_seg = 'b1000110; 59 | 'hd: bcd_to_seg = 'b0100001; 60 | 'he: bcd_to_seg = 'b0000110; 61 | 'hf: bcd_to_seg = 'b0001110; 62 | endcase 63 | 64 | endfunction 65 | 66 | reg [2:0] i; 67 | 68 | always @ (posedge clock or negedge resetn) 69 | begin 70 | if (! resetn) 71 | begin 72 | seven_segments <= bcd_to_seg (0); 73 | dot <= ~ 0; 74 | anodes <= ~ 8'b00000001; 75 | 76 | i <= 0; 77 | end 78 | else 79 | begin 80 | seven_segments <= bcd_to_seg (number [i * 4 +: 4]); 81 | dot <= ~ 0; 82 | anodes <= ~ (1 << i); 83 | 84 | i <= i + 1; 85 | end 86 | end 87 | 88 | endmodule -------------------------------------------------------------------------------- /board/zeowaa/zeowaa.qsf: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name FAMILY "Cyclone IV E" 3 | 4 | set_global_assignment -name DEVICE EP4CE6E22C8 5 | # set_global_assignment -name DEVICE EP4CE10E22C8 6 | 7 | set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 8 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY . 9 | 10 | set_global_assignment -name TOP_LEVEL_ENTITY zeowaa 11 | 12 | set_global_assignment -name SEARCH_PATH .. 13 | set_global_assignment -name VERILOG_FILE ../zeowaa.v 14 | set_global_assignment -name SDC_FILE ../zeowaa.sdc 15 | 16 | set_global_assignment -name VERILOG_FILE ../zeowaa.v 17 | 18 | set_global_assignment -name VERILOG_FILE ../../../src/sm_cpu.v 19 | set_global_assignment -name VERILOG_FILE ../../../src/sm_hex_display.v 20 | set_global_assignment -name VERILOG_FILE ../../../src/sm_register.v 21 | set_global_assignment -name VERILOG_FILE ../../../src/sm_rom.v 22 | set_global_assignment -name VERILOG_FILE ../../../src/sm_top.v 23 | 24 | set_global_assignment -name SEARCH_PATH .. 25 | set_global_assignment -name SEARCH_PATH ../../program 26 | set_global_assignment -name SEARCH_PATH ../../../src 27 | 28 | set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM" 29 | 30 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to * 31 | 32 | set_location_assignment PIN_23 -to clk_50 33 | 34 | set_location_assignment PIN_90 -to key[2] 35 | set_location_assignment PIN_91 -to key[3] 36 | set_location_assignment PIN_87 -to key[4] 37 | set_location_assignment PIN_86 -to key[5] 38 | 39 | set_location_assignment PIN_58 -to sw[7] 40 | set_location_assignment PIN_59 -to sw[6] 41 | set_location_assignment PIN_60 -to sw[5] 42 | set_location_assignment PIN_64 -to sw[4] 43 | set_location_assignment PIN_65 -to sw[3] 44 | set_location_assignment PIN_66 -to sw[2] 45 | set_location_assignment PIN_67 -to sw[1] 46 | set_location_assignment PIN_68 -to sw[0] 47 | 48 | set_location_assignment PIN_72 -to led[0] 49 | set_location_assignment PIN_73 -to led[1] 50 | set_location_assignment PIN_74 -to led[2] 51 | set_location_assignment PIN_80 -to led[3] 52 | set_location_assignment PIN_83 -to led[4] 53 | set_location_assignment PIN_84 -to led[5] 54 | set_location_assignment PIN_77 -to led[6] 55 | set_location_assignment PIN_76 -to led[7] 56 | set_location_assignment PIN_75 -to led[8] 57 | set_location_assignment PIN_71 -to led[9] 58 | set_location_assignment PIN_70 -to led[10] 59 | set_location_assignment PIN_69 -to led[11] 60 | 61 | set_location_assignment PIN_127 -to hex[0] 62 | set_location_assignment PIN_126 -to hex[1] 63 | set_location_assignment PIN_125 -to hex[2] 64 | set_location_assignment PIN_124 -to hex[3] 65 | set_location_assignment PIN_121 -to hex[4] 66 | set_location_assignment PIN_120 -to hex[5] 67 | set_location_assignment PIN_119 -to hex[6] 68 | set_location_assignment PIN_115 -to hex[7] 69 | 70 | set_location_assignment PIN_128 -to digit[0] 71 | set_location_assignment PIN_129 -to digit[1] 72 | set_location_assignment PIN_132 -to digit[2] 73 | set_location_assignment PIN_133 -to digit[3] 74 | set_location_assignment PIN_135 -to digit[4] 75 | set_location_assignment PIN_136 -to digit[5] 76 | set_location_assignment PIN_137 -to digit[6] 77 | set_location_assignment PIN_138 -to digit[7] 78 | 79 | set_location_assignment PIN_141 -to buzzer 80 | -------------------------------------------------------------------------------- /board/rz_easyFPGA_A2.1/rz_easyFPGA_A21.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2016 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Intel and sold by Intel or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition 22 | # Date created = 22:41:24 October 12, 2017 23 | # 24 | # -------------------------------------------------------------------------- # 25 | # 26 | # Notes: 27 | # 28 | # 1) The default values for assignments are stored in the file: 29 | # rz_easyFPGA_A21_assignment_defaults.qdf 30 | # If this file doesn't exist, see file: 31 | # assignment_defaults.qdf 32 | # 33 | # 2) Altera recommends that you do not modify this file. This 34 | # file is updated automatically by the Quartus Prime software 35 | # and any changes you make may be lost or overwritten. 36 | # 37 | # -------------------------------------------------------------------------- # 38 | 39 | 40 | set_global_assignment -name FAMILY "Cyclone IV E" 41 | set_global_assignment -name DEVICE EP4CE6E22C8 42 | set_global_assignment -name TOP_LEVEL_ENTITY rz_easyFPGA_A21 43 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 44 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:41:24 OCTOBER 12, 2017" 45 | set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" 46 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 47 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 48 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 49 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 50 | set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V 51 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 52 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 53 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 54 | set_location_assignment PIN_25 -to KEY0 55 | set_location_assignment PIN_49 -to HEX3[4] 56 | set_location_assignment PIN_88 -to KEY1 57 | set_location_assignment PIN_87 -to LED[3] 58 | set_location_assignment PIN_86 -to LED[2] 59 | set_location_assignment PIN_85 -to LED[1] 60 | set_location_assignment PIN_84 -to LED[0] 61 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 62 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 63 | 64 | set_global_assignment -name SEARCH_PATH .. 65 | set_global_assignment -name SEARCH_PATH ../../program 66 | set_global_assignment -name SEARCH_PATH ../../../src 67 | 68 | set_global_assignment -name VERILOG_FILE ../../../src/sm_top.v 69 | set_global_assignment -name VERILOG_FILE ../../../src/sm_rom.v 70 | set_global_assignment -name VERILOG_FILE ../../../src/sm_register.v 71 | set_global_assignment -name VERILOG_FILE ../../../src/sm_hex_display.v 72 | set_global_assignment -name VERILOG_FILE ../../../src/sm_cpu.v 73 | set_global_assignment -name VERILOG_FILE ../rz_easyFPGA_A21.v 74 | set_global_assignment -name SDC_FILE rz_easyFPGA_A21.sdc 75 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 76 | -------------------------------------------------------------------------------- /board/de0_nano/de0_nano.qsf: -------------------------------------------------------------------------------- 1 | #============================================================ 2 | # Build by Terasic System Builder 3 | #============================================================ 4 | 5 | set_global_assignment -name FAMILY "Cyclone IV" 6 | set_global_assignment -name DEVICE EP4CE22F17C6 7 | set_global_assignment -name TOP_LEVEL_ENTITY "de0_nano" 8 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "16.1" 9 | set_global_assignment -name LAST_QUARTUS_VERSION "16.1" 10 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:12:20 OCTOBER 27,2017" 11 | set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA 12 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 13 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 14 | set_global_assignment -name SDC_FILE de0_nano.SDC 15 | 16 | #============================================================ 17 | # CLOCK 18 | #============================================================ 19 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 20 | set_location_assignment PIN_R8 -to FPGA_CLK1_50 21 | 22 | #============================================================ 23 | # KEY 24 | #============================================================ 25 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] 26 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] 27 | set_location_assignment PIN_J15 -to KEY[0] 28 | set_location_assignment PIN_E1 -to KEY[1] 29 | 30 | #============================================================ 31 | # LED 32 | #============================================================ 33 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] 34 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] 35 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] 36 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] 37 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] 38 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] 39 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] 40 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] 41 | set_location_assignment PIN_A15 -to LED[0] 42 | set_location_assignment PIN_A13 -to LED[1] 43 | set_location_assignment PIN_B13 -to LED[2] 44 | set_location_assignment PIN_A11 -to LED[3] 45 | set_location_assignment PIN_D1 -to LED[4] 46 | set_location_assignment PIN_F3 -to LED[5] 47 | set_location_assignment PIN_B1 -to LED[6] 48 | set_location_assignment PIN_L3 -to LED[7] 49 | 50 | #============================================================ 51 | # SW 52 | #============================================================ 53 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] 54 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] 55 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] 56 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] 57 | set_location_assignment PIN_M1 -to SW[0] 58 | set_location_assignment PIN_T8 -to SW[1] 59 | set_location_assignment PIN_B9 -to SW[2] 60 | set_location_assignment PIN_M15 -to SW[3] 61 | 62 | #============================================================ 63 | # End of pin assignments by Terasic System Builder 64 | #============================================================ 65 | 66 | set_global_assignment -name VERILOG_FILE ../de0_nano.v 67 | 68 | set_global_assignment -name VERILOG_FILE ../../../src/sm_cpu.v 69 | set_global_assignment -name VERILOG_FILE ../../../src/sm_hex_display.v 70 | set_global_assignment -name VERILOG_FILE ../../../src/sm_register.v 71 | set_global_assignment -name VERILOG_FILE ../../../src/sm_rom.v 72 | set_global_assignment -name VERILOG_FILE ../../../src/sm_top.v 73 | 74 | set_global_assignment -name SEARCH_PATH .. 75 | set_global_assignment -name SEARCH_PATH ../../program 76 | set_global_assignment -name SEARCH_PATH ../../../src 77 | 78 | set_global_assignment -name HEX_FILE ../../program/program.hex 79 | 80 | set_global_assignment -name SDC_FILE de0_nano.sdc 81 | 82 | set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM" 83 | -------------------------------------------------------------------------------- /testbench/testbench.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1 ns / 100 ps 3 | 4 | `include "sm_cpu.vh" 5 | 6 | `ifndef SIMULATION_CYCLES 7 | `define SIMULATION_CYCLES 120 8 | `endif 9 | 10 | module sm_testbench; 11 | 12 | // simulation options 13 | parameter Tt = 20; 14 | 15 | reg clk; 16 | reg rst_n; 17 | reg [ 4:0] regAddr; 18 | wire [31:0] regData; 19 | wire cpuClk; 20 | 21 | // ***** DUT start ************************ 22 | 23 | sm_top sm_top 24 | ( 25 | .clkIn ( clk ), 26 | .rst_n ( rst_n ), 27 | .clkDevide ( 4'b0 ), 28 | .clkEnable ( 1'b1 ), 29 | .clk ( cpuClk ), 30 | .regAddr ( regAddr ), 31 | .regData ( regData ) 32 | ); 33 | 34 | defparam sm_top.sm_clk_divider.bypass = 1; 35 | 36 | // ***** DUT end ************************ 37 | 38 | `ifdef ICARUS 39 | //iverilog memory dump init workaround 40 | initial $dumpvars; 41 | genvar k; 42 | for (k = 0; k < 32; k = k + 1) begin 43 | initial $dumpvars(0, sm_top.sm_cpu.rf.rf[k]); 44 | end 45 | `endif 46 | 47 | // simulation init 48 | initial begin 49 | clk = 0; 50 | forever clk = #(Tt/2) ~clk; 51 | end 52 | 53 | initial begin 54 | rst_n = 0; 55 | repeat (4) @(posedge clk); 56 | rst_n = 1; 57 | end 58 | 59 | //register file reset 60 | integer i; 61 | initial begin 62 | for (i = 0; i < 32; i = i + 1) 63 | sm_top.sm_cpu.rf.rf[i] = 0; 64 | end 65 | 66 | task disasmInstr 67 | ( 68 | input [31:0] instr 69 | ); 70 | reg [ 5:0] cmdOper; 71 | reg [ 5:0] cmdFunk; 72 | reg [ 4:0] cmdRs; 73 | reg [ 4:0] cmdRt; 74 | reg [ 4:0] cmdRd; 75 | reg [ 4:0] cmdSa; 76 | reg [15:0] cmdImm; 77 | reg signed [15:0] cmdImmS; 78 | 79 | begin 80 | cmdOper = instr[31:26]; 81 | cmdFunk = instr[ 5:0 ]; 82 | cmdRs = instr[25:21]; 83 | cmdRt = instr[20:16]; 84 | cmdRd = instr[15:11]; 85 | cmdSa = instr[10:6 ]; 86 | cmdImm = instr[15:0 ]; 87 | cmdImmS = instr[15:0 ]; 88 | 89 | $write(" "); 90 | 91 | casez( {cmdOper,cmdFunk} ) 92 | default : if (instr == 32'b0) 93 | $write ("nop"); 94 | else 95 | $write ("new/unknown"); 96 | 97 | { `C_SPEC, `F_ADDU } : $write ("addu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt); 98 | { `C_SPEC, `F_OR } : $write ("or $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt); 99 | { `C_SPEC, `F_SRL } : $write ("srl $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt); 100 | { `C_SPEC, `F_SLTU } : $write ("sltu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt); 101 | { `C_SPEC, `F_SUBU } : $write ("subu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt); 102 | 103 | { `C_ADDIU, `F_ANY } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm); 104 | { `C_LUI, `F_ANY } : $write ("lui $%1d, %1d", cmdRt, cmdImm); 105 | 106 | { `C_BEQ, `F_ANY } : $write ("beq $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1); 107 | { `C_BNE, `F_ANY } : $write ("bne $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1); 108 | endcase 109 | end 110 | 111 | endtask 112 | 113 | 114 | //simulation debug output 115 | integer cycle; initial cycle = 0; 116 | 117 | initial regAddr = 0; // get PC 118 | 119 | always @ (posedge clk) 120 | begin 121 | $write ("%5d pc = %2d pcaddr = %h instr = %h v0 = %1d", 122 | cycle, regData, (regData << 2), sm_top.sm_cpu.instr, sm_top.sm_cpu.rf.rf[2]); 123 | 124 | disasmInstr(sm_top.sm_cpu.instr); 125 | 126 | $write("\n"); 127 | 128 | cycle = cycle + 1; 129 | 130 | if (cycle > `SIMULATION_CYCLES) 131 | begin 132 | $display ("Timeout"); 133 | $stop; 134 | end 135 | end 136 | 137 | endmodule 138 | -------------------------------------------------------------------------------- /board/max_10_evkit/max_10_evkit.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2016 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Intel and sold by Intel or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition 22 | # Date created = 01:07:42 September 23, 2019 23 | # 24 | # -------------------------------------------------------------------------- # 25 | # 26 | # Notes: 27 | # 28 | # 1) The default values for assignments are stored in the file: 29 | # max_10_evkit_assignment_defaults.qdf 30 | # If this file doesn't exist, see file: 31 | # assignment_defaults.qdf 32 | # 33 | # 2) Altera recommends that you do not modify this file. This 34 | # file is updated automatically by the Quartus Prime software 35 | # and any changes you make may be lost or overwritten. 36 | # 37 | # -------------------------------------------------------------------------- # 38 | 39 | 40 | set_global_assignment -name FAMILY "MAX 10" 41 | set_global_assignment -name DEVICE 10M08SAE144C8G 42 | set_global_assignment -name TOP_LEVEL_ENTITY max_10_evkit 43 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 44 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:07:42 SEPTEMBER 23, 2019" 45 | set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" 46 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 47 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 48 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 49 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 50 | set_global_assignment -name HEX_FILE ../program/program.hex 51 | set_global_assignment -name VERILOG_FILE ../../src/sm_top.v 52 | set_global_assignment -name VERILOG_FILE ../../src/sm_rom.v 53 | set_global_assignment -name VERILOG_FILE ../../src/sm_register.v 54 | set_global_assignment -name VERILOG_FILE ../../src/sm_hex_display.v 55 | set_global_assignment -name VERILOG_FILE ../../src/sm_cpu.v 56 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 57 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 58 | set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON 59 | set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" 60 | set_global_assignment -name VERILOG_FILE max_10_evkit.v 61 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 62 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 63 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 64 | set_global_assignment -name SEARCH_PATH ../../../src/ 65 | set_global_assignment -name SEARCH_PATH ../../program 66 | set_global_assignment -name SEARCH_PATH .. 67 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity evboard -section_id Top 68 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity evboard -section_id Top 69 | set_global_assignment -name PARTITION_COLOR 16764057 -entity evboard -section_id Top 70 | set_location_assignment PIN_27 -to CLK 71 | set_location_assignment PIN_120 -to SW3_1 72 | set_location_assignment PIN_124 -to SW3_2 73 | set_location_assignment PIN_132 -to LED[0] 74 | set_location_assignment PIN_134 -to LED[1] 75 | set_location_assignment PIN_135 -to LED[2] 76 | set_location_assignment PIN_140 -to LED[3] 77 | set_location_assignment PIN_141 -to LED[4] 78 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity evboard -section_id Top 79 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /board/marsohod_3b/marsohod_3b.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus II License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus II 64-Bit 21 | # Version 14.0.2 Build 209 09/17/2014 SJ Web Edition 22 | # Date created = 10:11:43 April 16, 2015 23 | # 24 | # -------------------------------------------------------------------------- # 25 | # 26 | # Notes: 27 | # 28 | # 1) The default values for assignments are stored in the file: 29 | # marsohod_3_assignment_defaults.qdf 30 | # If this file doesn't exist, see file: 31 | # assignment_defaults.qdf 32 | # 33 | # 2) Altera recommends that you do not modify this file. This 34 | # file is updated automatically by the Quartus II software 35 | # and any changes you make may be lost or overwritten. 36 | # 37 | # -------------------------------------------------------------------------- # 38 | 39 | 40 | set_global_assignment -name FAMILY "MAX 10" 41 | set_global_assignment -name DEVICE 10M08SAE144C8GES 42 | set_global_assignment -name TOP_LEVEL_ENTITY marsohod_3b 43 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 44 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:22:08 JULY 06, 2017" 45 | set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 46 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 47 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 48 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 49 | set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP 50 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2 51 | 52 | 53 | set_location_assignment PIN_26 -to CLK100MHZ 54 | set_location_assignment PIN_129 -to KEY0 55 | set_location_assignment PIN_25 -to KEY1 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | set_location_assignment PIN_79 -to LED[7] 64 | set_location_assignment PIN_80 -to LED[6] 65 | set_location_assignment PIN_81 -to LED[5] 66 | set_location_assignment PIN_84 -to LED[4] 67 | set_location_assignment PIN_85 -to LED[3] 68 | set_location_assignment PIN_86 -to LED[2] 69 | set_location_assignment PIN_87 -to LED[1] 70 | set_location_assignment PIN_88 -to LED[0] 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 80 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 81 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 82 | set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF 83 | set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF 84 | set_global_assignment -name USE_CONFIGURATION_DEVICE ON 85 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF 86 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise 87 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall 88 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise 89 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall 90 | set_global_assignment -name ENABLE_OCT_DONE ON 91 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" 92 | set_global_assignment -name ENABLE_SIGNALTAP OFF 93 | set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp 94 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 95 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 96 | set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON 97 | set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" 98 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" 99 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 100 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 101 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 102 | set_global_assignment -name HEX_FILE ../../program/program.hex 103 | set_global_assignment -name VERILOG_FILE ../../../src/sm_rom.v 104 | set_global_assignment -name VERILOG_FILE ../../../src/sm_register.v 105 | set_global_assignment -name VERILOG_FILE ../../../src/sm_hex_display.v 106 | set_global_assignment -name VERILOG_FILE ../../../src/sm_cpu.v 107 | set_global_assignment -name VERILOG_FILE ../../../src/sm_clk_divider.v 108 | set_global_assignment -name VERILOG_FILE ../marsohod_3b.v 109 | 110 | set_global_assignment -name SEARCH_PATH .. 111 | set_global_assignment -name SEARCH_PATH ../../program 112 | set_global_assignment -name SEARCH_PATH ../../../src 113 | 114 | 115 | set_global_assignment -name SDC_FILE marsohod_3b.sdc 116 | 117 | set_global_assignment -name VERILOG_FILE marsohod_3b.v 118 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to CLK100MHZ 119 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /board/de0/de0_top.v: -------------------------------------------------------------------------------- 1 | 2 | module de0_top 3 | ( 4 | input CLOCK_50, // Clock 50 MHz 5 | input CLOCK_50_2, // Clock 50 MHz 6 | 7 | input [ 2:0] BUTTON, // Pushbutton[2:0] 8 | 9 | input [ 9:0] SW, // Toggle Switch[9:0] 10 | 11 | output [ 6:0] HEX0_D, // Seven Segment Digit 0 12 | output HEX0_DP, // Seven Segment Digit DP 0 13 | output [ 6:0] HEX1_D, // Seven Segment Digit 1 14 | output HEX1_DP, // Seven Segment Digit DP 1 15 | output [ 6:0] HEX2_D, // Seven Segment Digit 2 16 | output HEX2_DP, // Seven Segment Digit DP 2 17 | output [ 6:0] HEX3_D, // Seven Segment Digit 3 18 | output HEX3_DP, // Seven Segment Digit DP 3 19 | 20 | output [ 9:0] LEDG, // LED Green[9:0] 21 | 22 | output UART_TXD, // UART Transmitter 23 | input UART_RXD, // UART Receiver 24 | output UART_CTS, // UART Clear To Send 25 | input UART_RTS, // UART Request To Send 26 | 27 | inout [15:0] DRAM_DQ, // SDRAM Data bus 16 Bits 28 | output [12:0] DRAM_ADDR, // SDRAM Address bus 13 Bits 29 | output DRAM_LDQM, // SDRAM Low-byte Data Mask 30 | output DRAM_UDQM, // SDRAM High-byte Data Mask 31 | output DRAM_WE_N, // SDRAM Write Enable 32 | output DRAM_CAS_N, // SDRAM Column Address Strobe 33 | output DRAM_RAS_N, // SDRAM Row Address Strobe 34 | output DRAM_CS_N, // SDRAM Chip Select 35 | output DRAM_BA_0, // SDRAM Bank Address 0 36 | output DRAM_BA_1, // SDRAM Bank Address 1 37 | output DRAM_CLK, // SDRAM Clock 38 | output DRAM_CKE, // SDRAM Clock Enable 39 | 40 | inout [14:0] FL_DQ, // FLASH Data bus 15 Bits 41 | inout FL_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1 42 | output [21:0] FL_ADDR, // FLASH Address bus 22 Bits 43 | output FL_WE_N, // FLASH Write Enable 44 | output FL_RST_N, // FLASH Reset 45 | output FL_OE_N, // FLASH Output Enable 46 | output FL_CE_N, // FLASH Chip Enable 47 | output FL_WP_N, // FLASH Hardware Write Protect 48 | output FL_BYTE_N, // FLASH Selects 8/16-bit mode 49 | input FL_RY, // FLASH Ready/Busy 50 | 51 | inout [ 7:0] LCD_DATA, // LCD Data bus 8 bits 52 | output LCD_BLON, // LCD Back Light ON/OFF 53 | output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read 54 | output LCD_EN, // LCD Enable 55 | output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data 56 | 57 | inout SD_DAT0, // SD Card Data 0 58 | inout SD_DAT3, // SD Card Data 3 59 | inout SD_CMD, // SD Card Command Signal 60 | output SD_CLK, // SD Card Clock 61 | input SD_WP_N, // SD Card Write Protect 62 | 63 | inout PS2_KBDAT, // PS2 Keyboard Data 64 | inout PS2_KBCLK, // PS2 Keyboard Clock 65 | inout PS2_MSDAT, // PS2 Mouse Data 66 | inout PS2_MSCLK, // PS2 Mouse Clock 67 | 68 | output VGA_HS, // VGA H_SYNC 69 | output VGA_VS, // VGA V_SYNC 70 | output [3:0] VGA_R, // VGA Red[3:0] 71 | output [3:0] VGA_G, // VGA Green[3:0] 72 | output [3:0] VGA_B, // VGA Blue[3:0] 73 | 74 | input [ 1:0] GPIO0_CLKIN, // GPIO Connection 0 Clock In Bus 75 | output [ 1:0] GPIO0_CLKOUT, // GPIO Connection 0 Clock Out Bus 76 | inout [31:0] GPIO0_D, // GPIO Connection 0 Data Bus 77 | input [ 1:0] GPIO1_CLKIN, // GPIO Connection 1 Clock In Bus 78 | output [ 1:0] GPIO1_CLKOUT, // GPIO Connection 1 Clock Out Bus 79 | inout [31:0] GPIO1_D // GPIO Connection 1 Data Bus 80 | ); 81 | 82 | // wires & inputs 83 | wire clk; 84 | wire clkIn = CLOCK_50; 85 | wire rst_n = BUTTON[0]; 86 | wire clkEnable = SW [9] | ~BUTTON[1]; 87 | wire [ 3:0 ] clkDevide = SW [8:5]; 88 | wire [ 4:0 ] regAddr = SW [4:0]; 89 | wire [ 31:0 ] regData; 90 | 91 | //cores 92 | sm_top sm_top 93 | ( 94 | .clkIn ( clkIn ), 95 | .rst_n ( rst_n ), 96 | .clkDevide ( clkDevide ), 97 | .clkEnable ( clkEnable ), 98 | .clk ( clk ), 99 | .regAddr ( regAddr ), 100 | .regData ( regData ) 101 | ); 102 | 103 | //outputs 104 | assign LEDG[0] = clk; 105 | assign LEDG[9:1] = regData[8:0]; 106 | 107 | wire [ 31:0 ] h7segment = regData; 108 | 109 | assign HEX0_DP = 1'b1; 110 | assign HEX0_DP = 1'b1; 111 | assign HEX0_DP = 1'b1; 112 | assign HEX0_DP = 1'b1; 113 | 114 | sm_hex_display digit_3 ( h7segment [15:12] , HEX3_D [6:0] ); 115 | sm_hex_display digit_2 ( h7segment [11: 8] , HEX2_D [6:0] ); 116 | sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1_D [6:0] ); 117 | sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0_D [6:0] ); 118 | 119 | endmodule 120 | -------------------------------------------------------------------------------- /src/sm_cpu.v: -------------------------------------------------------------------------------- 1 | /* 2 | * schoolMIPS - small MIPS CPU for "Young Russian Chip Architects" 3 | * summer school ( yrca@googlegroups.com ) 4 | * 5 | * originally based on Sarah L. Harris MIPS CPU 6 | * 7 | * Copyright(c) 2017 Stanislav Zhelnio 8 | * Aleksandr Romanov 9 | */ 10 | 11 | `include "sm_cpu.vh" 12 | 13 | module sm_cpu 14 | ( 15 | input clk, // clock 16 | input rst_n, // reset 17 | input [ 4:0] regAddr, // debug access reg address 18 | output [31:0] regData, // debug access reg data 19 | output [31:0] imAddr, // instruction memory address 20 | input [31:0] imData // instruction memory data 21 | ); 22 | //control wires 23 | wire pcSrc; 24 | wire regDst; 25 | wire regWrite; 26 | wire aluSrc; 27 | wire aluZero; 28 | wire [ 2:0] aluControl; 29 | 30 | //program counter 31 | wire [31:0] pc; 32 | wire [31:0] pcBranch; 33 | wire [31:0] pcNext = pc + 1; 34 | wire [31:0] pc_new = ~pcSrc ? pcNext : pcBranch; 35 | sm_register r_pc(clk ,rst_n, pc_new, pc); 36 | 37 | //program memory access 38 | assign imAddr = pc; 39 | wire [31:0] instr = imData; 40 | 41 | //debug register access 42 | wire [31:0] rd0; 43 | assign regData = (regAddr != 0) ? rd0 : pc; 44 | 45 | //register file 46 | wire [ 4:0] a3 = regDst ? instr[15:11] : instr[20:16]; 47 | wire [31:0] rd1; 48 | wire [31:0] rd2; 49 | wire [31:0] wd3; 50 | 51 | sm_register_file rf 52 | ( 53 | .clk ( clk ), 54 | .a0 ( regAddr ), 55 | .a1 ( instr[25:21] ), 56 | .a2 ( instr[20:16] ), 57 | .a3 ( a3 ), 58 | .rd0 ( rd0 ), 59 | .rd1 ( rd1 ), 60 | .rd2 ( rd2 ), 61 | .wd3 ( wd3 ), 62 | .we3 ( regWrite ) 63 | ); 64 | 65 | //sign extension 66 | wire [31:0] signImm = { {16 { instr[15] }}, instr[15:0] }; 67 | assign pcBranch = pcNext + signImm; 68 | 69 | //alu 70 | wire [31:0] srcB = aluSrc ? signImm : rd2; 71 | 72 | sm_alu alu 73 | ( 74 | .srcA ( rd1 ), 75 | .srcB ( srcB ), 76 | .oper ( aluControl ), 77 | .shift ( instr[10:6 ] ), 78 | .zero ( aluZero ), 79 | .result ( wd3 ) 80 | ); 81 | 82 | //control 83 | sm_control sm_control 84 | ( 85 | .cmdOper ( instr[31:26] ), 86 | .cmdFunk ( instr[ 5:0 ] ), 87 | .aluZero ( aluZero ), 88 | .pcSrc ( pcSrc ), 89 | .regDst ( regDst ), 90 | .regWrite ( regWrite ), 91 | .aluSrc ( aluSrc ), 92 | .aluControl ( aluControl ) 93 | ); 94 | 95 | endmodule 96 | 97 | module sm_control 98 | ( 99 | input [5:0] cmdOper, 100 | input [5:0] cmdFunk, 101 | input aluZero, 102 | output pcSrc, 103 | output reg regDst, 104 | output reg regWrite, 105 | output reg aluSrc, 106 | output reg [2:0] aluControl 107 | ); 108 | reg branch; 109 | reg condZero; 110 | assign pcSrc = branch & (aluZero == condZero); 111 | 112 | always @ (*) begin 113 | branch = 1'b0; 114 | condZero = 1'b0; 115 | regDst = 1'b0; 116 | regWrite = 1'b0; 117 | aluSrc = 1'b0; 118 | aluControl = `ALU_ADD; 119 | 120 | casez( {cmdOper,cmdFunk} ) 121 | default : ; 122 | 123 | { `C_SPEC, `F_ADDU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_ADD; end 124 | { `C_SPEC, `F_OR } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_OR; end 125 | { `C_SPEC, `F_SRL } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SRL; end 126 | { `C_SPEC, `F_SLTU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SLTU; end 127 | { `C_SPEC, `F_SUBU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SUBU; end 128 | 129 | { `C_ADDIU, `F_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD; end 130 | { `C_LUI, `F_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_LUI; end 131 | 132 | { `C_BEQ, `F_ANY } : begin branch = 1'b1; condZero = 1'b1; aluControl = `ALU_SUBU; end 133 | { `C_BNE, `F_ANY } : begin branch = 1'b1; aluControl = `ALU_SUBU; end 134 | endcase 135 | end 136 | endmodule 137 | 138 | 139 | module sm_alu 140 | ( 141 | input [31:0] srcA, 142 | input [31:0] srcB, 143 | input [ 2:0] oper, 144 | input [ 4:0] shift, 145 | output zero, 146 | output reg [31:0] result 147 | ); 148 | always @ (*) begin 149 | case (oper) 150 | default : result = srcA + srcB; 151 | `ALU_ADD : result = srcA + srcB; 152 | `ALU_OR : result = srcA | srcB; 153 | `ALU_LUI : result = (srcB << 16); 154 | `ALU_SRL : result = srcB >> shift; 155 | `ALU_SLTU : result = (srcA < srcB) ? 1 : 0; 156 | `ALU_SUBU : result = srcA - srcB; 157 | endcase 158 | end 159 | 160 | assign zero = (result == 0); 161 | endmodule 162 | 163 | module sm_register_file 164 | ( 165 | input clk, 166 | input [ 4:0] a0, 167 | input [ 4:0] a1, 168 | input [ 4:0] a2, 169 | input [ 4:0] a3, 170 | output [31:0] rd0, 171 | output [31:0] rd1, 172 | output [31:0] rd2, 173 | input [31:0] wd3, 174 | input we3 175 | ); 176 | reg [31:0] rf [31:0]; 177 | 178 | assign rd0 = (a0 != 0) ? rf [a0] : 32'b0; 179 | assign rd1 = (a1 != 0) ? rf [a1] : 32'b0; 180 | assign rd2 = (a2 != 0) ? rf [a2] : 32'b0; 181 | 182 | always @ (posedge clk) 183 | if(we3) rf [a3] <= wd3; 184 | endmodule 185 | -------------------------------------------------------------------------------- /board/de1_soc/de1_soc.v: -------------------------------------------------------------------------------- 1 | 2 | //`define ENABLE_ADC 3 | //`define ENABLE_AUD 4 | //`define ENABLE_CLOCK2 5 | //`define ENABLE_CLOCK3 6 | //`define ENABLE_CLOCK4 7 | `define ENABLE_CLOCK 8 | //`define ENABLE_DRAM 9 | //`define ENABLE_FAN 10 | `define ENABLE_FPGA 11 | `define ENABLE_GPIO 12 | `define ENABLE_HEX 13 | //`define ENABLE_HPS 14 | //`define ENABLE_IRDA 15 | `define ENABLE_KEY 16 | `define ENABLE_LEDR 17 | //`define ENABLE_PS2 18 | //`define ENABLE_TD 19 | //`define ENABLE_VGA 20 | `define ENABLE_SW 21 | 22 | module de1_soc( 23 | 24 | `ifdef ENABLE_ADC 25 | output ADC_CONVST, 26 | output ADC_DIN, 27 | input ADC_DOUT, 28 | output ADC_SCLK, 29 | `endif 30 | 31 | `ifdef ENABLE_AUD 32 | input AUD_ADCDAT, 33 | inout AUD_ADCLRCK, 34 | inout AUD_BCLK, 35 | output AUD_DACDAT, 36 | inout AUD_DACLRCK, 37 | output AUD_XCK, 38 | `endif 39 | 40 | `ifdef ENABLE_CLOCK2 41 | input CLOCK2_50, 42 | `endif 43 | 44 | `ifdef ENABLE_CLOCK3 45 | input CLOCK3_50, 46 | `endif 47 | 48 | `ifdef ENABLE_CLOCK4 49 | input CLOCK4_50, 50 | `endif 51 | 52 | `ifdef ENABLE_CLOCK 53 | input CLOCK_50, 54 | `endif 55 | 56 | `ifdef ENABLE_DRAM 57 | output [12:0] DRAM_ADDR, 58 | output [1:0] DRAM_BA, 59 | output DRAM_CAS_N, 60 | output DRAM_CKE, 61 | output DRAM_CLK, 62 | output DRAM_CS_N, 63 | inout [15:0] DRAM_DQ, 64 | output DRAM_LDQM, 65 | output DRAM_RAS_N, 66 | output DRAM_UDQM, 67 | output DRAM_WE_N, 68 | `endif 69 | 70 | `ifdef ENABLE_FAN 71 | output FAN_CTRL, 72 | `endif 73 | 74 | `ifdef ENABLE_FPGA 75 | output FPGA_I2C_SCLK, 76 | inout FPGA_I2C_SDAT, 77 | `endif 78 | 79 | `ifdef ENABLE_GPIO 80 | inout [35:0] GPIO_0, 81 | inout [35:0] GPIO_1, 82 | `endif 83 | 84 | `ifdef ENABLE_HEX 85 | output [6:0] HEX0, 86 | output [6:0] HEX1, 87 | output [6:0] HEX2, 88 | output [6:0] HEX3, 89 | output [6:0] HEX4, 90 | output [6:0] HEX5, 91 | `endif 92 | 93 | `ifdef ENABLE_HPS 94 | inout HPS_CONV_USB_N, 95 | output [14:0] HPS_DDR3_ADDR, 96 | output [2:0] HPS_DDR3_BA, 97 | output HPS_DDR3_CAS_N, 98 | output HPS_DDR3_CKE, 99 | output HPS_DDR3_CK_N, 100 | output HPS_DDR3_CK_P, 101 | output HPS_DDR3_CS_N, 102 | output [3:0] HPS_DDR3_DM, 103 | inout [31:0] HPS_DDR3_DQ, 104 | inout [3:0] HPS_DDR3_DQS_N, 105 | inout [3:0] HPS_DDR3_DQS_P, 106 | output HPS_DDR3_ODT, 107 | output HPS_DDR3_RAS_N, 108 | output HPS_DDR3_RESET_N, 109 | input HPS_DDR3_RZQ, 110 | output HPS_DDR3_WE_N, 111 | output HPS_ENET_GTX_CLK, 112 | inout HPS_ENET_INT_N, 113 | output HPS_ENET_MDC, 114 | inout HPS_ENET_MDIO, 115 | input HPS_ENET_RX_CLK, 116 | input [3:0] HPS_ENET_RX_DATA, 117 | input HPS_ENET_RX_DV, 118 | output [3:0] HPS_ENET_TX_DATA, 119 | output HPS_ENET_TX_EN, 120 | inout [3:0] HPS_FLASH_DATA, 121 | output HPS_FLASH_DCLK, 122 | output HPS_FLASH_NCSO, 123 | inout HPS_GSENSOR_INT, 124 | inout HPS_I2C1_SCLK, 125 | inout HPS_I2C1_SDAT, 126 | inout HPS_I2C2_SCLK, 127 | inout HPS_I2C2_SDAT, 128 | inout HPS_I2C_CONTROL, 129 | inout HPS_KEY, 130 | inout HPS_LED, 131 | inout HPS_LTC_GPIO, 132 | output HPS_SD_CLK, 133 | inout HPS_SD_CMD, 134 | inout [3:0] HPS_SD_DATA, 135 | output HPS_SPIM_CLK, 136 | input HPS_SPIM_MISO, 137 | output HPS_SPIM_MOSI, 138 | inout HPS_SPIM_SS, 139 | input HPS_UART_RX, 140 | output HPS_UART_TX, 141 | input HPS_USB_CLKOUT, 142 | inout [7:0] HPS_USB_DATA, 143 | input HPS_USB_DIR, 144 | input HPS_USB_NXT, 145 | output HPS_USB_STP, 146 | `endif 147 | 148 | `ifdef ENABLE_IRDA 149 | input IRDA_RXD, 150 | output IRDA_TXD, 151 | `endif 152 | 153 | `ifdef ENABLE_KEY 154 | input [3:0] KEY, 155 | `endif 156 | 157 | `ifdef ENABLE_LEDR 158 | output [9:0] LEDR, 159 | `endif 160 | 161 | `ifdef ENABLE_PS2 162 | inout PS2_CLK, 163 | inout PS2_CLK2, 164 | inout PS2_DAT, 165 | inout PS2_DAT2, 166 | `endif 167 | 168 | `ifdef ENABLE_TD 169 | input TD_CLK27, 170 | input [7:0] TD_DATA, 171 | input TD_HS, 172 | output TD_RESET_N, 173 | input TD_VS, 174 | `endif 175 | 176 | `ifdef ENABLE_VGA 177 | output [7:0] VGA_B, 178 | output VGA_BLANK_N, 179 | output VGA_CLK, 180 | output [7:0] VGA_G, 181 | output VGA_HS, 182 | output [7:0] VGA_R, 183 | output VGA_SYNC_N, 184 | output VGA_VS, 185 | `endif 186 | 187 | `ifdef ENABLE_SW 188 | input [9:0] SW 189 | `endif 190 | ); 191 | 192 | // wires & inputs 193 | wire clk; 194 | wire clkIn = CLOCK_50; 195 | wire rst_n = KEY[0]; 196 | wire clkEnable = SW [9] | ~KEY[1]; 197 | wire [ 3:0 ] clkDevide = SW [8:5]; 198 | wire [ 4:0 ] regAddr = SW [4:0]; 199 | wire [ 31:0 ] regData; 200 | 201 | //cores 202 | sm_top sm_top 203 | ( 204 | .clkIn ( clkIn ), 205 | .rst_n ( rst_n ), 206 | .clkDevide ( clkDevide ), 207 | .clkEnable ( clkEnable ), 208 | .clk ( clk ), 209 | .regAddr ( regAddr ), 210 | .regData ( regData ) 211 | ); 212 | 213 | //outputs 214 | assign LEDR[0] = clk; 215 | assign LEDR[9:1] = regData[8:0]; 216 | 217 | wire [ 31:0 ] h7segment = regData; 218 | 219 | sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] ); 220 | sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] ); 221 | sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] ); 222 | sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] ); 223 | sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] ); 224 | sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] ); 225 | 226 | endmodule 227 | -------------------------------------------------------------------------------- /board/max_10_neek/max_10_neek.v: -------------------------------------------------------------------------------- 1 | 2 | `define ENABLE_ADC 3 | `define ENABLE_AUDIO 4 | `define ENABLE_CAMERA 5 | `define ENABLE_DAC 6 | // `define ENABLE_DDR3 7 | `define ENABLE_FLASH 8 | `define ENABLE_GPIO 9 | `define ENABLE_GSENSOR 10 | `define ENABLE_HDMI 11 | `define ENABLE_HEX0 12 | `define ENABLE_HEX1 13 | `define ENABLE_KEY 14 | `define ENABLE_LEDR 15 | `define ENABLE_LSENSOR 16 | `define ENABLE_MAX10 17 | `define ENABLE_MIPI 18 | `define ENABLE_MTL2 19 | `define ENABLE_NET 20 | `define ENABLE_PM 21 | `define ENABLE_PS2 22 | `define ENABLE_RH 23 | `define ENABLE_SD 24 | `define ENABLE_SW 25 | `define ENABLE_UART 26 | 27 | module golden_top( 28 | 29 | `ifdef ENABLE_ADC 30 | ///////// ADC 3.3 V ///////// 31 | input ADC_CLK_10, 32 | `endif 33 | 34 | `ifdef ENABLE_AUDIO 35 | ///////// AUDIO 2.5 V ///////// 36 | inout AUDIO_BCLK, 37 | output AUDIO_DIN_MFP1, 38 | input AUDIO_DOUT_MFP2, 39 | inout AUDIO_GPIO_MFP5, 40 | output AUDIO_MCLK, 41 | input AUDIO_MISO_MFP4, 42 | inout AUDIO_RESET_n, 43 | output AUDIO_SCLK_MFP3, 44 | output AUDIO_SCL_SS_n, 45 | inout AUDIO_SDA_MOSI, 46 | output AUDIO_SPI_SELECT, 47 | inout AUDIO_WCLK, 48 | `endif 49 | 50 | `ifdef ENABLE_CAMERA 51 | // 2.5 V 52 | output CAMERA_I2C_SCL, 53 | inout CAMERA_I2C_SDA, 54 | // 3.3 V LVTTL 55 | output CAMERA_PWDN_n, 56 | `endif 57 | 58 | `ifdef ENABLE_DAC 59 | ///////// DAC 3.3 V LVTTL ///////// 60 | inout DAC_DATA, 61 | output DAC_SCLK, 62 | output DAC_SYNC_n, 63 | `endif 64 | 65 | `ifdef ENABLE_DDR3 66 | // "SSTL-15 CLASS I" 67 | output [14:0] DDR3_A, 68 | output [2:0] DDR3_BA, 69 | output DDR3_CKE, 70 | output DDR3_CAS_n, 71 | output DDR3_CS_n, 72 | output [2:0] DDR3_DM, 73 | inout [23:0] DDR3_DQ, 74 | output DDR3_ODT, 75 | output DDR3_RAS_n, 76 | output DDR3_RESET_n, 77 | output DDR3_WE_n, 78 | // "DIFFERENTIAL 1.5-V SSTL CLASS I" 79 | inout DDR3_CK_n, 80 | inout DDR3_CK_p, 81 | inout [2:0] DDR3_DQS_n, 82 | inout [2:0] DDR3_DQS_p, 83 | `endif 84 | 85 | `ifdef ENABLE_FLASH 86 | // "3.3-V LVTTL" 87 | inout [3:0] FLASH_DATA, 88 | output FLASH_DCLK, 89 | output FLASH_NCSO, 90 | output FLASH_RESET_n, 91 | `endif 92 | 93 | `ifdef ENABLE_GPIO 94 | // "3.3-V LVTTL" 95 | inout [7:0] GPIO, 96 | `endif 97 | 98 | `ifdef ENABLE_GSENSOR 99 | // 2.5 V 100 | output GSENSOR_CS_n, 101 | input [2:1] GSENSOR_INT, 102 | inout GSENSOR_SCLK, 103 | inout GSENSOR_SDI, 104 | inout GSENSOR_SDO, 105 | `endif 106 | 107 | `ifdef ENABLE_HDMI 108 | // "3.3-V LVTTL" 109 | input HDMI_AP, 110 | inout HDMI_I2C_SCL, 111 | inout HDMI_I2C_SDA, 112 | inout HDMI_LRCLK, 113 | inout HDMI_MCLK, 114 | input HDMI_RX_CLK, 115 | input [23:0] HDMI_RX_D, 116 | input HDMI_RX_DE, 117 | inout HDMI_RX_HS, 118 | input HDMI_RX_INT1, 119 | inout HDMI_RX_RESET_n, 120 | input HDMI_RX_VS, 121 | inout HDMI_SCLK, 122 | `endif 123 | 124 | `ifdef ENABLE_HEX0 125 | // "3.3-V LVTTL" 126 | output [6:0] HEX0, 127 | `endif 128 | 129 | `ifdef ENABLE_HEX1 130 | // "3.3-V LVTTL" 131 | output [6:0] HEX1, 132 | `endif 133 | 134 | `ifdef ENABLE_KEY 135 | // "1.5 V SCHMITT TRIGGER" 136 | input [4:0] KEY, 137 | `endif 138 | 139 | `ifdef ENABLE_LEDR 140 | // "3.3-V LVTTL" 141 | output [9:0] LEDR, 142 | `endif 143 | 144 | `ifdef ENABLE_LSENSOR 145 | // "3.3-V LVTTL" 146 | inout LSENSOR_INT, 147 | output LSENSOR_SCL, 148 | inout LSENSOR_SDA, 149 | `endif 150 | 151 | `ifdef ENABLE_MAX10 152 | // "3.3-V LVTTL" 153 | input MAX10_CLK1_50, 154 | input MAX10_CLK2_50, 155 | input MAX10_CLK3_50, 156 | `endif 157 | 158 | `ifdef ENABLE_MIPI 159 | // "3.3-V LVTTL" 160 | output MIPI_CS_n, 161 | output MIPI_I2C_SCL, 162 | inout MIPI_I2C_SDA, 163 | input MIPI_PIXEL_CLK, 164 | input [23:0] MIPI_PIXEL_D, 165 | input MIPI_PIXEL_HS, 166 | input MIPI_PIXEL_VS, 167 | output MIPI_REFCLK, 168 | output MIPI_RESET_n, 169 | `endif 170 | 171 | `ifdef ENABLE_MTL2 172 | // "3.3-V LVTTL" 173 | output [7:0] MTL2_B, 174 | inout MTL2_BL_ON_n, 175 | output MTL2_DCLK, 176 | output [7:0] MTL2_G, 177 | output MTL2_HSD, 178 | output MTL2_I2C_SCL, 179 | inout MTL2_I2C_SDA, 180 | input MTL2_INT, 181 | output [7:0] MTL2_R, 182 | output MTL2_VSD, 183 | `endif 184 | 185 | `ifdef ENABLE_NET 186 | // 2.5 V 187 | output NET_GTX_CLK, 188 | input NET_INT_n, 189 | input NET_LINK100, 190 | output NET_MDC, 191 | inout NET_MDIO, 192 | output NET_RST_N, 193 | input NET_RX_CLK, 194 | input NET_RX_COL, 195 | input NET_RX_CRS, 196 | input [3:0] NET_RX_D, 197 | input NET_RX_DV, 198 | input NET_RX_ER, 199 | input NET_TX_CLK, 200 | output [3:0] NET_TX_D, 201 | output NET_TX_EN, 202 | output NET_TX_ER, 203 | `endif 204 | 205 | `ifdef ENABLE_PM 206 | // "3.3-V LVTTL" 207 | output PM_I2C_SCL, 208 | inout PM_I2C_SDA, 209 | `endif 210 | 211 | `ifdef ENABLE_PS2 212 | // "3.3-V LVTTL" 213 | inout PS2_CLK, 214 | inout PS2_CLK2, 215 | inout PS2_DAT, 216 | inout PS2_DAT2, 217 | `endif 218 | 219 | `ifdef ENABLE_RH 220 | // "3.3-V LVTTL" 221 | input RH_TEMP_DRDY_n, 222 | output RH_TEMP_I2C_SCL, 223 | inout RH_TEMP_I2C_SDA, 224 | `endif 225 | 226 | `ifdef ENABLE_SD 227 | // 2.5 V 228 | output SD_CLK, 229 | inout SD_CMD, 230 | inout [3:0] SD_DATA, 231 | `endif 232 | 233 | `ifdef ENABLE_SW 234 | // 1.5 V 235 | input [9:0] SW, 236 | `endif 237 | 238 | `ifdef ENABLE_UART 239 | // 2.5 V 240 | output UART_RESET_n, 241 | input UART_RX, 242 | output UART_TX, 243 | `endif 244 | 245 | ///////// FPGA ///////// 246 | input FPGA_RESET_n 247 | 248 | ); 249 | 250 | // wires & inputs 251 | wire clk; 252 | wire clkIn = MAX10_CLK1_50; 253 | wire rst_n = KEY[0]; 254 | wire clkEnable = SW [9] | ~KEY[1]; 255 | wire [ 3:0 ] clkDevide = SW [8:5]; 256 | wire [ 4:0 ] regAddr = SW [4:0]; 257 | wire [ 31:0 ] regData; 258 | 259 | //cores 260 | sm_top sm_top 261 | ( 262 | .clkIn ( clkIn ), 263 | .rst_n ( rst_n ), 264 | .clkDevide ( clkDevide ), 265 | .clkEnable ( clkEnable ), 266 | .clk ( clk ), 267 | .regAddr ( regAddr ), 268 | .regData ( regData ) 269 | ); 270 | 271 | //outputs 272 | assign LEDR[0] = clk; 273 | assign LEDR[9:1] = regData[8:0]; 274 | 275 | wire [ 31:0 ] h7segment = regData; 276 | 277 | sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] ); 278 | sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] ); 279 | 280 | endmodule 281 | -------------------------------------------------------------------------------- /board/de4_230/DE4_230.qsf: -------------------------------------------------------------------------------- 1 | #============================================================ 2 | # Build by Terasic System Builder 3 | #============================================================ 4 | 5 | set_global_assignment -name FAMILY "Stratix IV" 6 | set_global_assignment -name DEVICE EP4SGX230KF40C2 7 | set_global_assignment -name TOP_LEVEL_ENTITY "de4_230" 8 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP1" 9 | set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP1" 10 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:44:26 DECEMBER 17,2017" 11 | set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA 12 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1517 13 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 2 14 | set_global_assignment -name SDC_FILE de4_230.SDC 15 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" 16 | set_location_assignment PIN_AF25 -to termination_blk0~_rup_pad 17 | set_location_assignment PIN_AG25 -to termination_blk0~_rdn_pad 18 | 19 | #============================================================ 20 | # CLOCK 21 | #============================================================ 22 | set_location_assignment PIN_AC35 -to OSC_50_BANK2 23 | set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK2 24 | set_location_assignment PIN_AV22 -to OSC_50_BANK3 25 | set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_BANK3 26 | set_location_assignment PIN_AV19 -to OSC_50_BANK4 27 | set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_BANK4 28 | set_location_assignment PIN_AC6 -to OSC_50_BANK5 29 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to OSC_50_BANK5 30 | set_location_assignment PIN_AB6 -to OSC_50_BANK6 31 | set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_BANK6 32 | set_location_assignment PIN_A19 -to OSC_50_BANK7 33 | set_instance_assignment -name IO_STANDARD "1.8 V" -to OSC_50_BANK7 34 | set_location_assignment PIN_AH19 -to GCLKOUT_FPGA 35 | set_instance_assignment -name IO_STANDARD "1.8 V" -to GCLKOUT_FPGA 36 | set_location_assignment PIN_A21 -to GCLKIN 37 | set_instance_assignment -name IO_STANDARD "1.8 V" -to GCLKIN 38 | set_location_assignment PIN_B22 -to PLL_CLKIN_p 39 | set_instance_assignment -name IO_STANDARD "LVDS" -to PLL_CLKIN_p 40 | 41 | #============================================================ 42 | # LED x 8 43 | #============================================================ 44 | set_location_assignment PIN_V28 -to LED[0] 45 | set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[0] 46 | set_location_assignment PIN_W28 -to LED[1] 47 | set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[1] 48 | set_location_assignment PIN_R29 -to LED[2] 49 | set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[2] 50 | set_location_assignment PIN_P29 -to LED[3] 51 | set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[3] 52 | set_location_assignment PIN_N29 -to LED[4] 53 | set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[4] 54 | set_location_assignment PIN_M29 -to LED[5] 55 | set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[5] 56 | set_location_assignment PIN_M30 -to LED[6] 57 | set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[6] 58 | set_location_assignment PIN_N30 -to LED[7] 59 | set_instance_assignment -name IO_STANDARD "2.5 V" -to LED[7] 60 | 61 | #============================================================ 62 | # BUTTON x 4, EXT_IO and CPU_RESET_n 63 | #============================================================ 64 | set_location_assignment PIN_AH5 -to BUTTON[0] 65 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to BUTTON[0] 66 | set_location_assignment PIN_AG5 -to BUTTON[1] 67 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to BUTTON[1] 68 | set_location_assignment PIN_AG7 -to BUTTON[2] 69 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to BUTTON[2] 70 | set_location_assignment PIN_AG8 -to BUTTON[3] 71 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to BUTTON[3] 72 | set_location_assignment PIN_AC11 -to EXT_IO 73 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to EXT_IO 74 | set_location_assignment PIN_V34 -to CPU_RESET_n 75 | set_instance_assignment -name IO_STANDARD "2.5 V" -to CPU_RESET_n 76 | 77 | #============================================================ 78 | # DIP SWITCH x 8 79 | #============================================================ 80 | set_location_assignment PIN_AB13 -to SW[0] 81 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[0] 82 | set_location_assignment PIN_AB12 -to SW[1] 83 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[1] 84 | set_location_assignment PIN_AB11 -to SW[2] 85 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[2] 86 | set_location_assignment PIN_AB10 -to SW[3] 87 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[3] 88 | set_location_assignment PIN_AB9 -to SW[4] 89 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[4] 90 | set_location_assignment PIN_AC8 -to SW[5] 91 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[5] 92 | set_location_assignment PIN_AH6 -to SW[6] 93 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[6] 94 | set_location_assignment PIN_AG6 -to SW[7] 95 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SW[7] 96 | 97 | #============================================================ 98 | # SLIDE SWITCH x 4 99 | #============================================================ 100 | set_location_assignment PIN_J7 -to SLIDE_SW[0] 101 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SLIDE_SW[0] 102 | set_location_assignment PIN_K7 -to SLIDE_SW[1] 103 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SLIDE_SW[1] 104 | set_location_assignment PIN_AK6 -to SLIDE_SW[2] 105 | set_instance_assignment -name IO_STANDARD "3.0-V PCI-X" -to SLIDE_SW[2] 106 | set_location_assignment PIN_L7 -to SLIDE_SW[3] 107 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SLIDE_SW[3] 108 | 109 | #============================================================ 110 | # SEG7 111 | #============================================================ 112 | set_location_assignment PIN_L34 -to SEG0_D[0] 113 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[0] 114 | set_location_assignment PIN_M34 -to SEG0_D[1] 115 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[1] 116 | set_location_assignment PIN_M33 -to SEG0_D[2] 117 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[2] 118 | set_location_assignment PIN_H31 -to SEG0_D[3] 119 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[3] 120 | set_location_assignment PIN_J33 -to SEG0_D[4] 121 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[4] 122 | set_location_assignment PIN_L35 -to SEG0_D[5] 123 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[5] 124 | set_location_assignment PIN_K32 -to SEG0_D[6] 125 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_D[6] 126 | set_location_assignment PIN_AL34 -to SEG0_DP 127 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG0_DP 128 | set_location_assignment PIN_E31 -to SEG1_D[0] 129 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[0] 130 | set_location_assignment PIN_F31 -to SEG1_D[1] 131 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[1] 132 | set_location_assignment PIN_G31 -to SEG1_D[2] 133 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[2] 134 | set_location_assignment PIN_C34 -to SEG1_D[3] 135 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[3] 136 | set_location_assignment PIN_C33 -to SEG1_D[4] 137 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[4] 138 | set_location_assignment PIN_D33 -to SEG1_D[5] 139 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[5] 140 | set_location_assignment PIN_D34 -to SEG1_D[6] 141 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_D[6] 142 | set_location_assignment PIN_AL35 -to SEG1_DP 143 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SEG1_DP 144 | 145 | #============================================================ 146 | # End of pin assignments by Terasic System Builder 147 | #============================================================ 148 | 149 | set_global_assignment -name VERILOG_FILE ../de4_230.v 150 | 151 | set_global_assignment -name VERILOG_FILE ../../../src/sm_cpu.v 152 | set_global_assignment -name VERILOG_FILE ../../../src/sm_hex_display.v 153 | set_global_assignment -name VERILOG_FILE ../../../src/sm_register.v 154 | set_global_assignment -name VERILOG_FILE ../../../src/sm_rom.v 155 | set_global_assignment -name VERILOG_FILE ../../../src/sm_top.v 156 | 157 | set_global_assignment -name SEARCH_PATH .. 158 | set_global_assignment -name SEARCH_PATH ../../program 159 | set_global_assignment -name SEARCH_PATH ../../../src 160 | 161 | set_global_assignment -name HEX_FILE ../../program/program.hex 162 | 163 | set_global_assignment -name SDC_FILE de4_230.sdc 164 | 165 | set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM" 166 | -------------------------------------------------------------------------------- /board/marsohod_3/marsohod_3.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus II License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus II 64-Bit 21 | # Version 14.0.2 Build 209 09/17/2014 SJ Web Edition 22 | # Date created = 10:11:43 April 16, 2015 23 | # 24 | # -------------------------------------------------------------------------- # 25 | # 26 | # Notes: 27 | # 28 | # 1) The default values for assignments are stored in the file: 29 | # marsohod_3_assignment_defaults.qdf 30 | # If this file doesn't exist, see file: 31 | # assignment_defaults.qdf 32 | # 33 | # 2) Altera recommends that you do not modify this file. This 34 | # file is updated automatically by the Quartus II software 35 | # and any changes you make may be lost or overwritten. 36 | # 37 | # -------------------------------------------------------------------------- # 38 | 39 | 40 | set_global_assignment -name FAMILY "MAX 10" 41 | set_global_assignment -name DEVICE 10M50SAE144C8GES 42 | set_global_assignment -name TOP_LEVEL_ENTITY marsohod_3 43 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 44 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:22:08 JULY 06, 2017" 45 | set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0 46 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 47 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 48 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 49 | set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP 50 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2 51 | 52 | set_location_assignment PIN_141 -to FTDI_BD0 53 | set_location_assignment PIN_140 -to FTDI_BD1 54 | set_location_assignment PIN_138 -to FTDI_BD2 55 | set_location_assignment PIN_136 -to FTDI_BD3 56 | 57 | set_location_assignment PIN_26 -to CLK100MHZ 58 | set_location_assignment PIN_130 -to KEY0 59 | set_location_assignment PIN_25 -to KEY1 60 | 61 | set_location_assignment PIN_27 -to SDRAM_DQ[15] 62 | set_location_assignment PIN_28 -to SDRAM_DQ[14] 63 | set_location_assignment PIN_29 -to SDRAM_DQ[13] 64 | set_location_assignment PIN_30 -to SDRAM_DQ[12] 65 | set_location_assignment PIN_32 -to SDRAM_DQ[11] 66 | set_location_assignment PIN_33 -to SDRAM_DQ[10] 67 | set_location_assignment PIN_38 -to SDRAM_DQ[9] 68 | set_location_assignment PIN_39 -to SDRAM_DQ[8] 69 | 70 | set_location_assignment PIN_66 -to SDRAM_DQ[7] 71 | set_location_assignment PIN_69 -to SDRAM_DQ[6] 72 | set_location_assignment PIN_70 -to SDRAM_DQ[5] 73 | set_location_assignment PIN_74 -to SDRAM_DQ[4] 74 | set_location_assignment PIN_75 -to SDRAM_DQ[3] 75 | set_location_assignment PIN_76 -to SDRAM_DQ[2] 76 | set_location_assignment PIN_77 -to SDRAM_DQ[1] 77 | set_location_assignment PIN_80 -to SDRAM_DQ[0] 78 | 79 | set_location_assignment PIN_57 -to SDRAM_A[0] 80 | set_location_assignment PIN_58 -to SDRAM_A[1] 81 | set_location_assignment PIN_60 -to SDRAM_A[2] 82 | set_location_assignment PIN_61 -to SDRAM_A[3] 83 | set_location_assignment PIN_42 -to SDRAM_A[4] 84 | set_location_assignment PIN_43 -to SDRAM_A[5] 85 | set_location_assignment PIN_44 -to SDRAM_A[6] 86 | set_location_assignment PIN_46 -to SDRAM_A[7] 87 | set_location_assignment PIN_49 -to SDRAM_A[8] 88 | set_location_assignment PIN_50 -to SDRAM_A[9] 89 | set_location_assignment PIN_55 -to SDRAM_A[10] 90 | set_location_assignment PIN_51 -to SDRAM_A[11] 91 | 92 | set_location_assignment PIN_65 -to SDRAM_LDQM 93 | set_location_assignment PIN_40 -to SDRAM_UDQM 94 | 95 | set_location_assignment PIN_52 -to SDRAM_BA0 96 | set_location_assignment PIN_53 -to SDRAM_BA1 97 | 98 | set_location_assignment PIN_62 -to SDRAM_RAS 99 | set_location_assignment PIN_63 -to SDRAM_CAS 100 | set_location_assignment PIN_64 -to SDRAM_WE 101 | set_location_assignment PIN_41 -to SDRAM_CLK 102 | 103 | set_location_assignment PIN_81 -to LED[7] 104 | set_location_assignment PIN_82 -to LED[6] 105 | set_location_assignment PIN_83 -to LED[5] 106 | set_location_assignment PIN_84 -to LED[4] 107 | set_location_assignment PIN_85 -to LED[3] 108 | set_location_assignment PIN_86 -to LED[2] 109 | set_location_assignment PIN_87 -to LED[1] 110 | set_location_assignment PIN_88 -to LED[0] 111 | 112 | set_location_assignment PIN_132 -to TMDS[7] 113 | set_location_assignment PIN_131 -to TMDS[6] 114 | set_location_assignment PIN_129 -to TMDS[5] 115 | set_location_assignment PIN_127 -to TMDS[4] 116 | set_location_assignment PIN_126 -to TMDS[3] 117 | set_location_assignment PIN_125 -to TMDS[2] 118 | set_location_assignment PIN_124 -to TMDS[1] 119 | set_location_assignment PIN_120 -to TMDS[0] 120 | 121 | set_location_assignment PIN_20 -to FTD[0] 122 | set_location_assignment PIN_135 -to FTD[1] 123 | set_location_assignment PIN_133 -to FTD[2] 124 | set_location_assignment PIN_134 -to FTD[3] 125 | set_location_assignment PIN_23 -to FTD[4] 126 | set_location_assignment PIN_22 -to FTD[5] 127 | set_location_assignment PIN_21 -to FTD[6] 128 | set_location_assignment PIN_15 -to FTD[7] 129 | set_location_assignment PIN_14 -to FTC[0] 130 | set_location_assignment PIN_13 -to FTC[1] 131 | set_location_assignment PIN_12 -to FTC[2] 132 | set_location_assignment PIN_11 -to FTC[3] 133 | set_location_assignment PIN_10 -to FTC[4] 134 | set_location_assignment PIN_8 -to FTC[5] 135 | set_location_assignment PIN_7 -to FTC[6] 136 | set_location_assignment PIN_6 -to FTC[7] 137 | 138 | 139 | set_location_assignment PIN_89 -to IO[0] 140 | set_location_assignment PIN_90 -to IO[1] 141 | set_location_assignment PIN_91 -to IO[2] 142 | set_location_assignment PIN_92 -to IO[3] 143 | set_location_assignment PIN_93 -to IO[4] 144 | set_location_assignment PIN_96 -to IO[5] 145 | set_location_assignment PIN_97 -to IO[6] 146 | set_location_assignment PIN_98 -to IO[7] 147 | set_location_assignment PIN_99 -to IO[8] 148 | set_location_assignment PIN_100 -to IO[9] 149 | set_location_assignment PIN_101 -to IO[10] 150 | set_location_assignment PIN_102 -to IO[11] 151 | set_location_assignment PIN_105 -to IO[12] 152 | set_location_assignment PIN_106 -to IO[13] 153 | set_location_assignment PIN_110 -to IO[14] 154 | set_location_assignment PIN_111 -to IO[15] 155 | set_location_assignment PIN_116 -to IO[16] 156 | set_location_assignment PIN_117 -to IO[17] 157 | set_location_assignment PIN_119 -to IO[18] 158 | set_location_assignment PIN_118 -to IO[19] 159 | 160 | set_location_assignment PIN_123 -to RESERVED 161 | set_location_assignment PIN_128 -to BOOT_SEL 162 | 163 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to key0 164 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to key1 165 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BOOT_SEL 166 | 167 | 168 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 169 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 170 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 171 | set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF 172 | set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF 173 | set_global_assignment -name USE_CONFIGURATION_DEVICE ON 174 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF 175 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise 176 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall 177 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise 178 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall 179 | set_global_assignment -name ENABLE_OCT_DONE ON 180 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" 181 | set_instance_assignment -name IO_STANDARD "2.5 V SCHMITT TRIGGER" -to key0 182 | set_instance_assignment -name IO_STANDARD "2.5 V SCHMITT TRIGGER" -to key1 183 | set_global_assignment -name ENABLE_SIGNALTAP OFF 184 | set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp 185 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 186 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 187 | set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON 188 | set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" 189 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" 190 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 191 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 192 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 193 | set_global_assignment -name HEX_FILE ../../program/program.hex 194 | set_global_assignment -name VERILOG_FILE ../../../src/sm_rom.v 195 | set_global_assignment -name VERILOG_FILE ../../../src/sm_register.v 196 | set_global_assignment -name VERILOG_FILE ../../../src/sm_hex_display.v 197 | set_global_assignment -name VERILOG_FILE ../../../src/sm_cpu.v 198 | set_global_assignment -name VERILOG_FILE ../../../src/sm_clk_divider.v 199 | set_global_assignment -name VERILOG_FILE ../marsohod_3.v 200 | 201 | set_global_assignment -name SEARCH_PATH .. 202 | set_global_assignment -name SEARCH_PATH ../../program 203 | set_global_assignment -name SEARCH_PATH ../../../src 204 | 205 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 206 | 207 | set_global_assignment -name SDC_FILE marsohod_3.sdc 208 | -------------------------------------------------------------------------------- /board/de10_standard/de10_standard.qsf: -------------------------------------------------------------------------------- 1 | #============================================================ 2 | # Build by Terasic System Builder 3 | #============================================================ 4 | 5 | set_global_assignment -name FAMILY "Cyclone V" 6 | set_global_assignment -name DEVICE 5CSXFC6D6F31C6 7 | set_global_assignment -name TOP_LEVEL_ENTITY "de10_standard" 8 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2 9 | set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0 10 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:15:44 JULY 21,2017" 11 | set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA 12 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896 13 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 14 | 15 | #============================================================ 16 | # CLOCK 17 | #============================================================ 18 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 19 | set_instance_assignment -name IO_STANDARD "2.5 V" -to CLOCK3_50 20 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK4_50 21 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 22 | set_location_assignment PIN_AA16 -to CLOCK2_50 23 | set_location_assignment PIN_Y26 -to CLOCK3_50 24 | set_location_assignment PIN_K14 -to CLOCK4_50 25 | set_location_assignment PIN_AF14 -to CLOCK_50 26 | 27 | #============================================================ 28 | # KEY 29 | #============================================================ 30 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] 31 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] 32 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] 33 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] 34 | set_location_assignment PIN_AJ4 -to KEY[0] 35 | set_location_assignment PIN_AK4 -to KEY[1] 36 | set_location_assignment PIN_AA14 -to KEY[2] 37 | set_location_assignment PIN_AA15 -to KEY[3] 38 | 39 | #============================================================ 40 | # SW 41 | #============================================================ 42 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] 43 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] 44 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] 45 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] 46 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4] 47 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5] 48 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6] 49 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7] 50 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8] 51 | set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9] 52 | set_location_assignment PIN_AB30 -to SW[0] 53 | set_location_assignment PIN_Y27 -to SW[1] 54 | set_location_assignment PIN_AB28 -to SW[2] 55 | set_location_assignment PIN_AC30 -to SW[3] 56 | set_location_assignment PIN_W25 -to SW[4] 57 | set_location_assignment PIN_V25 -to SW[5] 58 | set_location_assignment PIN_AC28 -to SW[6] 59 | set_location_assignment PIN_AD30 -to SW[7] 60 | set_location_assignment PIN_AC29 -to SW[8] 61 | set_location_assignment PIN_AA30 -to SW[9] 62 | 63 | #============================================================ 64 | # LED 65 | #============================================================ 66 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] 67 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] 68 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] 69 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] 70 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] 71 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] 72 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] 73 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] 74 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] 75 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] 76 | set_location_assignment PIN_AA24 -to LEDR[0] 77 | set_location_assignment PIN_AB23 -to LEDR[1] 78 | set_location_assignment PIN_AC23 -to LEDR[2] 79 | set_location_assignment PIN_AD24 -to LEDR[3] 80 | set_location_assignment PIN_AG25 -to LEDR[4] 81 | set_location_assignment PIN_AF25 -to LEDR[5] 82 | set_location_assignment PIN_AE24 -to LEDR[6] 83 | set_location_assignment PIN_AF24 -to LEDR[7] 84 | set_location_assignment PIN_AB22 -to LEDR[8] 85 | set_location_assignment PIN_AC22 -to LEDR[9] 86 | 87 | #============================================================ 88 | # Seg7 89 | #============================================================ 90 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] 91 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] 92 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] 93 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] 94 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] 95 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] 96 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] 97 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] 98 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] 99 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] 100 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] 101 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] 102 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] 103 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] 104 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] 105 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] 106 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] 107 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] 108 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] 109 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] 110 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] 111 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] 112 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] 113 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] 114 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] 115 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] 116 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] 117 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] 118 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] 119 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] 120 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] 121 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] 122 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] 123 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] 124 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] 125 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] 126 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] 127 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] 128 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] 129 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] 130 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] 131 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] 132 | set_location_assignment PIN_W17 -to HEX0[0] 133 | set_location_assignment PIN_V18 -to HEX0[1] 134 | set_location_assignment PIN_AG17 -to HEX0[2] 135 | set_location_assignment PIN_AG16 -to HEX0[3] 136 | set_location_assignment PIN_AH17 -to HEX0[4] 137 | set_location_assignment PIN_AG18 -to HEX0[5] 138 | set_location_assignment PIN_AH18 -to HEX0[6] 139 | set_location_assignment PIN_AF16 -to HEX1[0] 140 | set_location_assignment PIN_V16 -to HEX1[1] 141 | set_location_assignment PIN_AE16 -to HEX1[2] 142 | set_location_assignment PIN_AD17 -to HEX1[3] 143 | set_location_assignment PIN_AE18 -to HEX1[4] 144 | set_location_assignment PIN_AE17 -to HEX1[5] 145 | set_location_assignment PIN_V17 -to HEX1[6] 146 | set_location_assignment PIN_AA21 -to HEX2[0] 147 | set_location_assignment PIN_AB17 -to HEX2[1] 148 | set_location_assignment PIN_AA18 -to HEX2[2] 149 | set_location_assignment PIN_Y17 -to HEX2[3] 150 | set_location_assignment PIN_Y18 -to HEX2[4] 151 | set_location_assignment PIN_AF18 -to HEX2[5] 152 | set_location_assignment PIN_W16 -to HEX2[6] 153 | set_location_assignment PIN_Y19 -to HEX3[0] 154 | set_location_assignment PIN_W19 -to HEX3[1] 155 | set_location_assignment PIN_AD19 -to HEX3[2] 156 | set_location_assignment PIN_AA20 -to HEX3[3] 157 | set_location_assignment PIN_AC20 -to HEX3[4] 158 | set_location_assignment PIN_AA19 -to HEX3[5] 159 | set_location_assignment PIN_AD20 -to HEX3[6] 160 | set_location_assignment PIN_AD21 -to HEX4[0] 161 | set_location_assignment PIN_AG22 -to HEX4[1] 162 | set_location_assignment PIN_AE22 -to HEX4[2] 163 | set_location_assignment PIN_AE23 -to HEX4[3] 164 | set_location_assignment PIN_AG23 -to HEX4[4] 165 | set_location_assignment PIN_AF23 -to HEX4[5] 166 | set_location_assignment PIN_AH22 -to HEX4[6] 167 | set_location_assignment PIN_AF21 -to HEX5[0] 168 | set_location_assignment PIN_AG21 -to HEX5[1] 169 | set_location_assignment PIN_AF20 -to HEX5[2] 170 | set_location_assignment PIN_AG20 -to HEX5[3] 171 | set_location_assignment PIN_AE19 -to HEX5[4] 172 | set_location_assignment PIN_AF19 -to HEX5[5] 173 | set_location_assignment PIN_AB21 -to HEX5[6] 174 | 175 | #============================================================ 176 | # End of pin assignments by Terasic System Builder 177 | #============================================================ 178 | 179 | 180 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 181 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 182 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 183 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 184 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 185 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 186 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 187 | set_global_assignment -name HEX_FILE ../../program/program.hex 188 | set_global_assignment -name VERILOG_FILE ../../../src/sm_rom.v 189 | set_global_assignment -name VERILOG_FILE ../../../src/sm_register.v 190 | set_global_assignment -name VERILOG_FILE ../../../src/sm_hex_display.v 191 | set_global_assignment -name VERILOG_FILE ../../../src/sm_cpu.v 192 | set_global_assignment -name VERILOG_FILE ../../../src/sm_top.v 193 | set_global_assignment -name VERILOG_FILE ../de10_standard.v 194 | set_global_assignment -name SDC_FILE de10_standard.SDC 195 | 196 | set_global_assignment -name SEARCH_PATH .. 197 | set_global_assignment -name SEARCH_PATH ../../program 198 | set_global_assignment -name SEARCH_PATH ../../../src 199 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /board/de10_lite/de10_lite.qsf: -------------------------------------------------------------------------------- 1 | #============================================================ 2 | # Build by Terasic System Builder 3 | #============================================================ 4 | 5 | set_global_assignment -name FAMILY "MAX 10 FPGA" 6 | set_global_assignment -name DEVICE 10M50DAF484C7G 7 | set_global_assignment -name TOP_LEVEL_ENTITY "de10_lite" 8 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "16.0.0" 9 | set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" 10 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:47:39 JUNE 26,2017" 11 | set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA 12 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 13 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 14 | 15 | #============================================================ 16 | # CLOCK 17 | #============================================================ 18 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10 19 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50 20 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50 21 | set_location_assignment PIN_N5 -to ADC_CLK_10 22 | set_location_assignment PIN_P11 -to MAX10_CLK1_50 23 | set_location_assignment PIN_N14 -to MAX10_CLK2_50 24 | 25 | #============================================================ 26 | # SEG7 27 | #============================================================ 28 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] 29 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] 30 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] 31 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] 32 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] 33 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] 34 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] 35 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7] 36 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] 37 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] 38 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] 39 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] 40 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] 41 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] 42 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] 43 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7] 44 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] 45 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] 46 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] 47 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] 48 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] 49 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] 50 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] 51 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7] 52 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] 53 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] 54 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] 55 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] 56 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] 57 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] 58 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] 59 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7] 60 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] 61 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] 62 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] 63 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] 64 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] 65 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] 66 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] 67 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7] 68 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] 69 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] 70 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] 71 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] 72 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] 73 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] 74 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] 75 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7] 76 | set_location_assignment PIN_C14 -to HEX0[0] 77 | set_location_assignment PIN_E15 -to HEX0[1] 78 | set_location_assignment PIN_C15 -to HEX0[2] 79 | set_location_assignment PIN_C16 -to HEX0[3] 80 | set_location_assignment PIN_E16 -to HEX0[4] 81 | set_location_assignment PIN_D17 -to HEX0[5] 82 | set_location_assignment PIN_C17 -to HEX0[6] 83 | set_location_assignment PIN_D15 -to HEX0[7] 84 | set_location_assignment PIN_C18 -to HEX1[0] 85 | set_location_assignment PIN_D18 -to HEX1[1] 86 | set_location_assignment PIN_E18 -to HEX1[2] 87 | set_location_assignment PIN_B16 -to HEX1[3] 88 | set_location_assignment PIN_A17 -to HEX1[4] 89 | set_location_assignment PIN_A18 -to HEX1[5] 90 | set_location_assignment PIN_B17 -to HEX1[6] 91 | set_location_assignment PIN_A16 -to HEX1[7] 92 | set_location_assignment PIN_B20 -to HEX2[0] 93 | set_location_assignment PIN_A20 -to HEX2[1] 94 | set_location_assignment PIN_B19 -to HEX2[2] 95 | set_location_assignment PIN_A21 -to HEX2[3] 96 | set_location_assignment PIN_B21 -to HEX2[4] 97 | set_location_assignment PIN_C22 -to HEX2[5] 98 | set_location_assignment PIN_B22 -to HEX2[6] 99 | set_location_assignment PIN_A19 -to HEX2[7] 100 | set_location_assignment PIN_F21 -to HEX3[0] 101 | set_location_assignment PIN_E22 -to HEX3[1] 102 | set_location_assignment PIN_E21 -to HEX3[2] 103 | set_location_assignment PIN_C19 -to HEX3[3] 104 | set_location_assignment PIN_C20 -to HEX3[4] 105 | set_location_assignment PIN_D19 -to HEX3[5] 106 | set_location_assignment PIN_E17 -to HEX3[6] 107 | set_location_assignment PIN_D22 -to HEX3[7] 108 | set_location_assignment PIN_F18 -to HEX4[0] 109 | set_location_assignment PIN_E20 -to HEX4[1] 110 | set_location_assignment PIN_E19 -to HEX4[2] 111 | set_location_assignment PIN_J18 -to HEX4[3] 112 | set_location_assignment PIN_H19 -to HEX4[4] 113 | set_location_assignment PIN_F19 -to HEX4[5] 114 | set_location_assignment PIN_F20 -to HEX4[6] 115 | set_location_assignment PIN_F17 -to HEX4[7] 116 | set_location_assignment PIN_J20 -to HEX5[0] 117 | set_location_assignment PIN_K20 -to HEX5[1] 118 | set_location_assignment PIN_L18 -to HEX5[2] 119 | set_location_assignment PIN_N18 -to HEX5[3] 120 | set_location_assignment PIN_M20 -to HEX5[4] 121 | set_location_assignment PIN_N19 -to HEX5[5] 122 | set_location_assignment PIN_N20 -to HEX5[6] 123 | set_location_assignment PIN_L19 -to HEX5[7] 124 | 125 | #============================================================ 126 | # KEY 127 | #============================================================ 128 | set_instance_assignment -name IO_STANDARD "3.3 V Schmitt Trigger" -to KEY[0] 129 | set_instance_assignment -name IO_STANDARD "3.3 V Schmitt Trigger" -to KEY[1] 130 | set_location_assignment PIN_B8 -to KEY[0] 131 | set_location_assignment PIN_A7 -to KEY[1] 132 | 133 | #============================================================ 134 | # LED 135 | #============================================================ 136 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] 137 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] 138 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] 139 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] 140 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] 141 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] 142 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] 143 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] 144 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] 145 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] 146 | set_location_assignment PIN_A8 -to LEDR[0] 147 | set_location_assignment PIN_A9 -to LEDR[1] 148 | set_location_assignment PIN_A10 -to LEDR[2] 149 | set_location_assignment PIN_B10 -to LEDR[3] 150 | set_location_assignment PIN_D13 -to LEDR[4] 151 | set_location_assignment PIN_C13 -to LEDR[5] 152 | set_location_assignment PIN_E14 -to LEDR[6] 153 | set_location_assignment PIN_D14 -to LEDR[7] 154 | set_location_assignment PIN_A11 -to LEDR[8] 155 | set_location_assignment PIN_B11 -to LEDR[9] 156 | 157 | #============================================================ 158 | # SW 159 | #============================================================ 160 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] 161 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] 162 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] 163 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] 164 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] 165 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] 166 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] 167 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] 168 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] 169 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] 170 | set_location_assignment PIN_C10 -to SW[0] 171 | set_location_assignment PIN_C11 -to SW[1] 172 | set_location_assignment PIN_D12 -to SW[2] 173 | set_location_assignment PIN_C12 -to SW[3] 174 | set_location_assignment PIN_A12 -to SW[4] 175 | set_location_assignment PIN_B12 -to SW[5] 176 | set_location_assignment PIN_A13 -to SW[6] 177 | set_location_assignment PIN_A14 -to SW[7] 178 | set_location_assignment PIN_B14 -to SW[8] 179 | set_location_assignment PIN_F15 -to SW[9] 180 | 181 | #============================================================ 182 | # GPIO, GPIO connect to GPIO Default 183 | #============================================================ 184 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] 185 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] 186 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] 187 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] 188 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] 189 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] 190 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] 191 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] 192 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] 193 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] 194 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] 195 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] 196 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] 197 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] 198 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] 199 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] 200 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] 201 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] 202 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] 203 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] 204 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] 205 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] 206 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] 207 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] 208 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] 209 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] 210 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] 211 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] 212 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] 213 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] 214 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] 215 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] 216 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] 217 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] 218 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] 219 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] 220 | set_location_assignment PIN_V10 -to GPIO[0] 221 | set_location_assignment PIN_W10 -to GPIO[1] 222 | set_location_assignment PIN_V9 -to GPIO[2] 223 | set_location_assignment PIN_W9 -to GPIO[3] 224 | set_location_assignment PIN_V8 -to GPIO[4] 225 | set_location_assignment PIN_W8 -to GPIO[5] 226 | set_location_assignment PIN_V7 -to GPIO[6] 227 | set_location_assignment PIN_W7 -to GPIO[7] 228 | set_location_assignment PIN_W6 -to GPIO[8] 229 | set_location_assignment PIN_V5 -to GPIO[9] 230 | set_location_assignment PIN_W5 -to GPIO[10] 231 | set_location_assignment PIN_AA15 -to GPIO[11] 232 | set_location_assignment PIN_AA14 -to GPIO[12] 233 | set_location_assignment PIN_W13 -to GPIO[13] 234 | set_location_assignment PIN_W12 -to GPIO[14] 235 | set_location_assignment PIN_AB13 -to GPIO[15] 236 | set_location_assignment PIN_AB12 -to GPIO[16] 237 | set_location_assignment PIN_Y11 -to GPIO[17] 238 | set_location_assignment PIN_AB11 -to GPIO[18] 239 | set_location_assignment PIN_W11 -to GPIO[19] 240 | set_location_assignment PIN_AB10 -to GPIO[20] 241 | set_location_assignment PIN_AA10 -to GPIO[21] 242 | set_location_assignment PIN_AA9 -to GPIO[22] 243 | set_location_assignment PIN_Y8 -to GPIO[23] 244 | set_location_assignment PIN_AA8 -to GPIO[24] 245 | set_location_assignment PIN_Y7 -to GPIO[25] 246 | set_location_assignment PIN_AA7 -to GPIO[26] 247 | set_location_assignment PIN_Y6 -to GPIO[27] 248 | set_location_assignment PIN_AA6 -to GPIO[28] 249 | set_location_assignment PIN_Y5 -to GPIO[29] 250 | set_location_assignment PIN_AA5 -to GPIO[30] 251 | set_location_assignment PIN_Y4 -to GPIO[31] 252 | set_location_assignment PIN_AB3 -to GPIO[32] 253 | set_location_assignment PIN_Y3 -to GPIO[33] 254 | set_location_assignment PIN_AB2 -to GPIO[34] 255 | set_location_assignment PIN_AA2 -to GPIO[35] 256 | 257 | #============================================================ 258 | # End of pin assignments by Terasic System Builder 259 | #============================================================ 260 | 261 | set_global_assignment -name VERILOG_FILE ../de10_lite.v 262 | 263 | set_global_assignment -name VERILOG_FILE ../../../src/sm_cpu.v 264 | set_global_assignment -name VERILOG_FILE ../../../src/sm_hex_display.v 265 | set_global_assignment -name VERILOG_FILE ../../../src/sm_register.v 266 | set_global_assignment -name VERILOG_FILE ../../../src/sm_rom.v 267 | set_global_assignment -name VERILOG_FILE ../../../src/sm_top.v 268 | 269 | set_global_assignment -name SEARCH_PATH .. 270 | set_global_assignment -name SEARCH_PATH ../../program 271 | set_global_assignment -name SEARCH_PATH ../../../src 272 | 273 | set_global_assignment -name HEX_FILE ../../program/program.hex 274 | 275 | set_global_assignment -name SDC_FILE de10_lite.sdc 276 | 277 | set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM" -------------------------------------------------------------------------------- /board/de10_nano/de10_nano.qsf: -------------------------------------------------------------------------------- 1 | #============================================================ 2 | # Build by Terasic System Builder 3 | #============================================================ 4 | 5 | set_global_assignment -name FAMILY "Cyclone V" 6 | set_global_assignment -name DEVICE 5CSEBA6U23I7 7 | set_global_assignment -name TOP_LEVEL_ENTITY "de10_nano" 8 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "16.0.2" 9 | set_global_assignment -name LAST_QUARTUS_VERSION "16.0.2" 10 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:12:20 JULY 28,2017" 11 | set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA 12 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 13 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 14 | set_global_assignment -name SDC_FILE de10_nano.SDC 15 | 16 | #============================================================ 17 | # ADC 18 | #============================================================ 19 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST 20 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK 21 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI 22 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO 23 | set_location_assignment PIN_U9 -to ADC_CONVST 24 | set_location_assignment PIN_V10 -to ADC_SCK 25 | set_location_assignment PIN_AC4 -to ADC_SDI 26 | set_location_assignment PIN_AD4 -to ADC_SDO 27 | 28 | #============================================================ 29 | # ARDUINO 30 | #============================================================ 31 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] 32 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] 33 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] 34 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] 35 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] 36 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] 37 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] 38 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] 39 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] 40 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] 41 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] 42 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] 43 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] 44 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] 45 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] 46 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] 47 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N 48 | set_location_assignment PIN_AG13 -to ARDUINO_IO[0] 49 | set_location_assignment PIN_AF13 -to ARDUINO_IO[1] 50 | set_location_assignment PIN_AG10 -to ARDUINO_IO[2] 51 | set_location_assignment PIN_AG9 -to ARDUINO_IO[3] 52 | set_location_assignment PIN_U14 -to ARDUINO_IO[4] 53 | set_location_assignment PIN_U13 -to ARDUINO_IO[5] 54 | set_location_assignment PIN_AG8 -to ARDUINO_IO[6] 55 | set_location_assignment PIN_AH8 -to ARDUINO_IO[7] 56 | set_location_assignment PIN_AF17 -to ARDUINO_IO[8] 57 | set_location_assignment PIN_AE15 -to ARDUINO_IO[9] 58 | set_location_assignment PIN_AF15 -to ARDUINO_IO[10] 59 | set_location_assignment PIN_AG16 -to ARDUINO_IO[11] 60 | set_location_assignment PIN_AH11 -to ARDUINO_IO[12] 61 | set_location_assignment PIN_AH12 -to ARDUINO_IO[13] 62 | set_location_assignment PIN_AH9 -to ARDUINO_IO[14] 63 | set_location_assignment PIN_AG11 -to ARDUINO_IO[15] 64 | set_location_assignment PIN_AH7 -to ARDUINO_RESET_N 65 | 66 | #============================================================ 67 | # CLOCK 68 | #============================================================ 69 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 70 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 71 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 72 | set_location_assignment PIN_V11 -to FPGA_CLK1_50 73 | set_location_assignment PIN_Y13 -to FPGA_CLK2_50 74 | set_location_assignment PIN_E11 -to FPGA_CLK3_50 75 | 76 | #============================================================ 77 | # HDMI 78 | #============================================================ 79 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL 80 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA 81 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S 82 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK 83 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK 84 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK 85 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK 86 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE 87 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0] 88 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1] 89 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2] 90 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3] 91 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4] 92 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5] 93 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6] 94 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7] 95 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8] 96 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9] 97 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10] 98 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11] 99 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12] 100 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13] 101 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14] 102 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15] 103 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16] 104 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17] 105 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18] 106 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19] 107 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20] 108 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21] 109 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22] 110 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23] 111 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS 112 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT 113 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS 114 | set_location_assignment PIN_U10 -to HDMI_I2C_SCL 115 | set_location_assignment PIN_AA4 -to HDMI_I2C_SDA 116 | set_location_assignment PIN_T13 -to HDMI_I2S 117 | set_location_assignment PIN_T11 -to HDMI_LRCLK 118 | set_location_assignment PIN_U11 -to HDMI_MCLK 119 | set_location_assignment PIN_T12 -to HDMI_SCLK 120 | set_location_assignment PIN_AG5 -to HDMI_TX_CLK 121 | set_location_assignment PIN_AD19 -to HDMI_TX_DE 122 | set_location_assignment PIN_AD12 -to HDMI_TX_D[0] 123 | set_location_assignment PIN_AE12 -to HDMI_TX_D[1] 124 | set_location_assignment PIN_W8 -to HDMI_TX_D[2] 125 | set_location_assignment PIN_Y8 -to HDMI_TX_D[3] 126 | set_location_assignment PIN_AD11 -to HDMI_TX_D[4] 127 | set_location_assignment PIN_AD10 -to HDMI_TX_D[5] 128 | set_location_assignment PIN_AE11 -to HDMI_TX_D[6] 129 | set_location_assignment PIN_Y5 -to HDMI_TX_D[7] 130 | set_location_assignment PIN_AF10 -to HDMI_TX_D[8] 131 | set_location_assignment PIN_Y4 -to HDMI_TX_D[9] 132 | set_location_assignment PIN_AE9 -to HDMI_TX_D[10] 133 | set_location_assignment PIN_AB4 -to HDMI_TX_D[11] 134 | set_location_assignment PIN_AE7 -to HDMI_TX_D[12] 135 | set_location_assignment PIN_AF6 -to HDMI_TX_D[13] 136 | set_location_assignment PIN_AF8 -to HDMI_TX_D[14] 137 | set_location_assignment PIN_AF5 -to HDMI_TX_D[15] 138 | set_location_assignment PIN_AE4 -to HDMI_TX_D[16] 139 | set_location_assignment PIN_AH2 -to HDMI_TX_D[17] 140 | set_location_assignment PIN_AH4 -to HDMI_TX_D[18] 141 | set_location_assignment PIN_AH5 -to HDMI_TX_D[19] 142 | set_location_assignment PIN_AH6 -to HDMI_TX_D[20] 143 | set_location_assignment PIN_AG6 -to HDMI_TX_D[21] 144 | set_location_assignment PIN_AF9 -to HDMI_TX_D[22] 145 | set_location_assignment PIN_AE8 -to HDMI_TX_D[23] 146 | set_location_assignment PIN_T8 -to HDMI_TX_HS 147 | set_location_assignment PIN_AF11 -to HDMI_TX_INT 148 | set_location_assignment PIN_V13 -to HDMI_TX_VS 149 | 150 | #============================================================ 151 | # KEY 152 | #============================================================ 153 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] 154 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] 155 | set_location_assignment PIN_AH17 -to KEY[0] 156 | set_location_assignment PIN_AH16 -to KEY[1] 157 | 158 | #============================================================ 159 | # LED 160 | #============================================================ 161 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] 162 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] 163 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] 164 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] 165 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] 166 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] 167 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] 168 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] 169 | set_location_assignment PIN_W15 -to LED[0] 170 | set_location_assignment PIN_AA24 -to LED[1] 171 | set_location_assignment PIN_V16 -to LED[2] 172 | set_location_assignment PIN_V15 -to LED[3] 173 | set_location_assignment PIN_AF26 -to LED[4] 174 | set_location_assignment PIN_AE26 -to LED[5] 175 | set_location_assignment PIN_Y16 -to LED[6] 176 | set_location_assignment PIN_AA23 -to LED[7] 177 | 178 | #============================================================ 179 | # SW 180 | #============================================================ 181 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] 182 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] 183 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] 184 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] 185 | set_location_assignment PIN_Y24 -to SW[0] 186 | set_location_assignment PIN_W24 -to SW[1] 187 | set_location_assignment PIN_W21 -to SW[2] 188 | set_location_assignment PIN_W20 -to SW[3] 189 | 190 | #============================================================ 191 | # GPIO_0, GPIO connect to GPIO Default 192 | #============================================================ 193 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] 194 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] 195 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] 196 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] 197 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] 198 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] 199 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] 200 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] 201 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] 202 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] 203 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] 204 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] 205 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] 206 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] 207 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] 208 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] 209 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] 210 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] 211 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] 212 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] 213 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] 214 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] 215 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] 216 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] 217 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] 218 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] 219 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] 220 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] 221 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] 222 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] 223 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] 224 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] 225 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] 226 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] 227 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34] 228 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35] 229 | set_location_assignment PIN_V12 -to GPIO_0[0] 230 | set_location_assignment PIN_E8 -to GPIO_0[1] 231 | set_location_assignment PIN_W12 -to GPIO_0[2] 232 | set_location_assignment PIN_D11 -to GPIO_0[3] 233 | set_location_assignment PIN_D8 -to GPIO_0[4] 234 | set_location_assignment PIN_AH13 -to GPIO_0[5] 235 | set_location_assignment PIN_AF7 -to GPIO_0[6] 236 | set_location_assignment PIN_AH14 -to GPIO_0[7] 237 | set_location_assignment PIN_AF4 -to GPIO_0[8] 238 | set_location_assignment PIN_AH3 -to GPIO_0[9] 239 | set_location_assignment PIN_AD5 -to GPIO_0[10] 240 | set_location_assignment PIN_AG14 -to GPIO_0[11] 241 | set_location_assignment PIN_AE23 -to GPIO_0[12] 242 | set_location_assignment PIN_AE6 -to GPIO_0[13] 243 | set_location_assignment PIN_AD23 -to GPIO_0[14] 244 | set_location_assignment PIN_AE24 -to GPIO_0[15] 245 | set_location_assignment PIN_D12 -to GPIO_0[16] 246 | set_location_assignment PIN_AD20 -to GPIO_0[17] 247 | set_location_assignment PIN_C12 -to GPIO_0[18] 248 | set_location_assignment PIN_AD17 -to GPIO_0[19] 249 | set_location_assignment PIN_AC23 -to GPIO_0[20] 250 | set_location_assignment PIN_AC22 -to GPIO_0[21] 251 | set_location_assignment PIN_Y19 -to GPIO_0[22] 252 | set_location_assignment PIN_AB23 -to GPIO_0[23] 253 | set_location_assignment PIN_AA19 -to GPIO_0[24] 254 | set_location_assignment PIN_W11 -to GPIO_0[25] 255 | set_location_assignment PIN_AA18 -to GPIO_0[26] 256 | set_location_assignment PIN_W14 -to GPIO_0[27] 257 | set_location_assignment PIN_Y18 -to GPIO_0[28] 258 | set_location_assignment PIN_Y17 -to GPIO_0[29] 259 | set_location_assignment PIN_AB25 -to GPIO_0[30] 260 | set_location_assignment PIN_AB26 -to GPIO_0[31] 261 | set_location_assignment PIN_Y11 -to GPIO_0[32] 262 | set_location_assignment PIN_AA26 -to GPIO_0[33] 263 | set_location_assignment PIN_AA13 -to GPIO_0[34] 264 | set_location_assignment PIN_AA11 -to GPIO_0[35] 265 | 266 | #============================================================ 267 | # GPIO_1, GPIO connect to GPIO Default 268 | #============================================================ 269 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] 270 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] 271 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] 272 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] 273 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] 274 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] 275 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] 276 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] 277 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] 278 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] 279 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] 280 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] 281 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] 282 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] 283 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] 284 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] 285 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] 286 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] 287 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] 288 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] 289 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] 290 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] 291 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] 292 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] 293 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] 294 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] 295 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] 296 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] 297 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] 298 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] 299 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] 300 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] 301 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] 302 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] 303 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34] 304 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35] 305 | set_location_assignment PIN_Y15 -to GPIO_1[0] 306 | set_location_assignment PIN_AC24 -to GPIO_1[1] 307 | set_location_assignment PIN_AA15 -to GPIO_1[2] 308 | set_location_assignment PIN_AD26 -to GPIO_1[3] 309 | set_location_assignment PIN_AG28 -to GPIO_1[4] 310 | set_location_assignment PIN_AF28 -to GPIO_1[5] 311 | set_location_assignment PIN_AE25 -to GPIO_1[6] 312 | set_location_assignment PIN_AF27 -to GPIO_1[7] 313 | set_location_assignment PIN_AG26 -to GPIO_1[8] 314 | set_location_assignment PIN_AH27 -to GPIO_1[9] 315 | set_location_assignment PIN_AG25 -to GPIO_1[10] 316 | set_location_assignment PIN_AH26 -to GPIO_1[11] 317 | set_location_assignment PIN_AH24 -to GPIO_1[12] 318 | set_location_assignment PIN_AF25 -to GPIO_1[13] 319 | set_location_assignment PIN_AG23 -to GPIO_1[14] 320 | set_location_assignment PIN_AF23 -to GPIO_1[15] 321 | set_location_assignment PIN_AG24 -to GPIO_1[16] 322 | set_location_assignment PIN_AH22 -to GPIO_1[17] 323 | set_location_assignment PIN_AH21 -to GPIO_1[18] 324 | set_location_assignment PIN_AG21 -to GPIO_1[19] 325 | set_location_assignment PIN_AH23 -to GPIO_1[20] 326 | set_location_assignment PIN_AA20 -to GPIO_1[21] 327 | set_location_assignment PIN_AF22 -to GPIO_1[22] 328 | set_location_assignment PIN_AE22 -to GPIO_1[23] 329 | set_location_assignment PIN_AG20 -to GPIO_1[24] 330 | set_location_assignment PIN_AF21 -to GPIO_1[25] 331 | set_location_assignment PIN_AG19 -to GPIO_1[26] 332 | set_location_assignment PIN_AH19 -to GPIO_1[27] 333 | set_location_assignment PIN_AG18 -to GPIO_1[28] 334 | set_location_assignment PIN_AH18 -to GPIO_1[29] 335 | set_location_assignment PIN_AF18 -to GPIO_1[30] 336 | set_location_assignment PIN_AF20 -to GPIO_1[31] 337 | set_location_assignment PIN_AG15 -to GPIO_1[32] 338 | set_location_assignment PIN_AE20 -to GPIO_1[33] 339 | set_location_assignment PIN_AE19 -to GPIO_1[34] 340 | set_location_assignment PIN_AE17 -to GPIO_1[35] 341 | 342 | #============================================================ 343 | # End of pin assignments by Terasic System Builder 344 | #============================================================ 345 | 346 | set_global_assignment -name VERILOG_FILE ../de10_nano.v 347 | 348 | set_global_assignment -name VERILOG_FILE ../../../src/sm_cpu.v 349 | set_global_assignment -name VERILOG_FILE ../../../src/sm_hex_display.v 350 | set_global_assignment -name VERILOG_FILE ../../../src/sm_register.v 351 | set_global_assignment -name VERILOG_FILE ../../../src/sm_rom.v 352 | set_global_assignment -name VERILOG_FILE ../../../src/sm_top.v 353 | 354 | set_global_assignment -name SEARCH_PATH .. 355 | set_global_assignment -name SEARCH_PATH ../../program 356 | set_global_assignment -name SEARCH_PATH ../../../src 357 | 358 | set_global_assignment -name HEX_FILE ../../program/program.hex 359 | 360 | set_global_assignment -name SDC_FILE de10_nano.sdc 361 | 362 | set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM" 363 | -------------------------------------------------------------------------------- /board/nexys4_ddr/nexys4_ddr.xdc: -------------------------------------------------------------------------------- 1 | # This file is a general .xdc for the Nexys4 DDR Rev. C 2 | # To use it in a project: 3 | # - uncomment the lines corresponding to used pins 4 | # - rename the used ports (in each line, after get_ports) according to the top level signal names in the project 5 | 6 | # Clock signal 7 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz 8 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}]; 9 | 10 | #Switches 11 | 12 | set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] 13 | set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] 14 | set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] 15 | set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] 16 | set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] 17 | set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] 18 | set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] 19 | set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] 20 | set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8] 21 | set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9] 22 | set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] 23 | set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] 24 | set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12] 25 | set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] 26 | set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] 27 | set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] 28 | 29 | 30 | # LEDs 31 | 32 | set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] 33 | set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] 34 | set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] 35 | set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] 36 | set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] 37 | set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] 38 | set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] 39 | set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] 40 | set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] 41 | set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] 42 | set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] 43 | set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] 44 | set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] 45 | set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] 46 | set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] 47 | set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] 48 | 49 | set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b 50 | set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g 51 | set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r 52 | set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b 53 | set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g 54 | set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r 55 | 56 | 57 | #7 segment display 58 | 59 | set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca 60 | set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb 61 | set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc 62 | set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd 63 | set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce 64 | set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf 65 | set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg 66 | 67 | set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp 68 | 69 | set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] 70 | set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] 71 | set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] 72 | set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] 73 | set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] 74 | set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] 75 | set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] 76 | set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] 77 | 78 | 79 | #Buttons 80 | 81 | set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn 82 | 83 | set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc 84 | set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu 85 | set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl 86 | set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr 87 | set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd 88 | 89 | 90 | #Pmod Headers 91 | 92 | 93 | #Pmod Header JA 94 | 95 | set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1] 96 | set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] 97 | set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] 98 | set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4] 99 | set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7] 100 | set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8] 101 | set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9] 102 | set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10] 103 | 104 | 105 | #Pmod Header JB 106 | 107 | set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] 108 | set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] 109 | set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] 110 | set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] 111 | set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] 112 | set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] 113 | set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9] 114 | set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] 115 | 116 | 117 | ##Pmod Header JC 118 | 119 | #set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1] 120 | #set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] 121 | #set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3] 122 | #set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4] 123 | #set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7] 124 | #set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8] 125 | #set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] 126 | #set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] 127 | 128 | 129 | ##Pmod Header JD 130 | 131 | #set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] 132 | #set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2] 133 | #set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3] 134 | #set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4] 135 | #set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] 136 | #set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8] 137 | #set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] 138 | #set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] 139 | 140 | 141 | ##Pmod Header JXADC 142 | 143 | #set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] 144 | #set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] 145 | #set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] 146 | #set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] 147 | #set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] 148 | #set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] 149 | #set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] 150 | #set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] 151 | 152 | 153 | ##VGA Connector 154 | 155 | #set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] 156 | #set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] 157 | #set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] 158 | #set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] 159 | 160 | #set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] 161 | #set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] 162 | #set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] 163 | #set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] 164 | 165 | #set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] 166 | #set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] 167 | #set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] 168 | #set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] 169 | 170 | #set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs 171 | #set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs 172 | 173 | 174 | ##Micro SD Connector 175 | 176 | #set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset 177 | #set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd 178 | #set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck 179 | #set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd 180 | #set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] 181 | #set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] 182 | #set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] 183 | #set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] 184 | 185 | 186 | ##Accelerometer 187 | 188 | #set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso 189 | #set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi 190 | #set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk 191 | #set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn 192 | #set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] 193 | #set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] 194 | 195 | 196 | ##Temperature Sensor 197 | 198 | #set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl 199 | #set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda 200 | #set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int 201 | #set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct 202 | 203 | ##Omnidirectional Microphone 204 | 205 | #set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk 206 | #set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data 207 | #set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel 208 | 209 | 210 | ##PWM Audio Amplifier 211 | 212 | #set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm 213 | #set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd 214 | 215 | 216 | ##USB-RS232 Interface 217 | 218 | set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in 219 | #set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out 220 | #set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts 221 | #set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts 222 | 223 | ##USB HID (PS/2) 224 | 225 | #set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk 226 | #set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data 227 | 228 | 229 | ##SMSC Ethernet PHY 230 | 231 | #set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc 232 | #set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio 233 | #set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn 234 | #set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv 235 | #set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr 236 | #set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] 237 | #set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] 238 | #set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen 239 | #set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] 240 | #set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] 241 | #set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk 242 | #set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn 243 | 244 | 245 | ##Quad SPI Flash 246 | 247 | #set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] 248 | #set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] 249 | #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] 250 | #set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] 251 | #set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn 252 | 253 | 254 | # Slow clock 255 | 256 | create_clock -name "slow_clk_g" -period 40.0 257 | 258 | # I/O virtual clock 259 | 260 | #create_clock -period 10.000 -name "clk_virt" 261 | create_clock -period 40.000 -name "clk_virt" 262 | 263 | # EJTAG virtual clock 264 | 265 | #create_clock -name "ejtag_tck" -period 10.0 266 | create_clock -name "ejtag_tck" -period 40.0 267 | 268 | # cut all paths to and from "clk_virt", "tck" 269 | set_clock_groups -physically_exclusive -group "clk_virt" 270 | set_clock_groups -physically_exclusive -group "ejtag_tck" 271 | 272 | # tsu/th constraints 273 | set_input_delay -clock "clk_virt" -min -add_delay 0.000 [get_ports {SW[*]}] 274 | set_input_delay -clock "clk_virt" -max -add_delay 10.000 [get_ports {SW[*]}] 275 | set_input_delay -clock "clk_virt" -min -add_delay 0.000 [get_ports BTNC] 276 | set_input_delay -clock "clk_virt" -max -add_delay 10.000 [get_ports BTNC] 277 | set_input_delay -clock "clk_virt" -min -add_delay 0.000 [get_ports CPU_RESETN] 278 | set_input_delay -clock "clk_virt" -max -add_delay 10.000 [get_ports CPU_RESETN] 279 | set_input_delay -clock "clk_virt" -min -add_delay 0.000 [get_ports BTND] 280 | set_input_delay -clock "clk_virt" -max -add_delay 10.000 [get_ports BTND] 281 | set_input_delay -clock "clk_virt" -min -add_delay 0.000 [get_ports BTNL] 282 | set_input_delay -clock "clk_virt" -max -add_delay 10.000 [get_ports BTNL] 283 | set_input_delay -clock "clk_virt" -min -add_delay 0.000 [get_ports BTNR] 284 | set_input_delay -clock "clk_virt" -max -add_delay 10.000 [get_ports BTNR] 285 | set_input_delay -clock "clk_virt" -min -add_delay 0.000 [get_ports BTNU] 286 | set_input_delay -clock "clk_virt" -max -add_delay 10.000 [get_ports BTNU] 287 | set_input_delay -clock "clk_virt" -min -add_delay 0.000 [get_ports JB[1]] 288 | set_input_delay -clock "clk_virt" -max -add_delay 10.000 [get_ports JB[1]] 289 | set_input_delay -clock "clk_virt" -min -add_delay 0.000 [get_ports JB[2]] 290 | set_input_delay -clock "clk_virt" -max -add_delay 10.000 [get_ports JB[2]] 291 | set_input_delay -clock "clk_virt" -min -add_delay 0.000 [get_ports JB[4]] 292 | set_input_delay -clock "clk_virt" -max -add_delay 10.000 [get_ports JB[4]] 293 | 294 | set_output_delay -clock "clk_virt" -min -add_delay 0.000 [get_ports {LED[*]}] 295 | set_output_delay -clock "clk_virt" -max -add_delay 10.000 [get_ports {LED[*]}] 296 | set_output_delay -clock "clk_virt" -min -add_delay 0.000 [get_ports {JB[3]}] 297 | set_output_delay -clock "clk_virt" -max -add_delay 10.000 [get_ports {JB[3]}] 298 | --------------------------------------------------------------------------------