├── .github └── FUNDING.yml ├── .gitignore ├── LICENSE ├── README.md ├── docs ├── bus_matrix.png ├── option_bytes.png └── requirements.txt ├── drivers ├── CMSIS │ ├── Device │ │ └── ST │ │ │ └── STM32H7xx │ │ │ └── Include │ │ │ ├── stm32h745xx.h │ │ │ ├── stm32h7xx.h │ │ │ └── system_stm32h7xx.h │ └── Include │ │ ├── cmsis_armcc.h │ │ ├── cmsis_armclang.h │ │ ├── cmsis_compiler.h │ │ ├── cmsis_gcc.h │ │ ├── cmsis_iccarm.h │ │ ├── cmsis_version.h │ │ ├── core_armv8mbl.h │ │ ├── core_armv8mml.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm1.h │ │ ├── core_cm23.h │ │ ├── core_cm3.h │ │ ├── core_cm33.h │ │ ├── core_cm4.h │ │ ├── core_cm7.h │ │ ├── core_sc000.h │ │ ├── core_sc300.h │ │ ├── mpu_armv7.h │ │ ├── mpu_armv8.h │ │ └── tz_context.h └── STM32H7xx_HAL_Driver │ ├── Inc │ ├── Legacy │ │ └── stm32_hal_legacy.h │ ├── stm32h7xx_hal.h │ ├── stm32h7xx_hal_cortex.h │ ├── stm32h7xx_hal_def.h │ ├── stm32h7xx_hal_dma.h │ ├── stm32h7xx_hal_dma_ex.h │ ├── stm32h7xx_hal_exti.h │ ├── stm32h7xx_hal_flash.h │ ├── stm32h7xx_hal_flash_ex.h │ ├── stm32h7xx_hal_gpio.h │ ├── stm32h7xx_hal_gpio_ex.h │ ├── stm32h7xx_hal_hsem.h │ ├── stm32h7xx_hal_i2c.h │ ├── stm32h7xx_hal_i2c_ex.h │ ├── stm32h7xx_hal_mdma.h │ ├── stm32h7xx_hal_pwr.h │ ├── stm32h7xx_hal_pwr_ex.h │ ├── stm32h7xx_hal_rcc.h │ ├── stm32h7xx_hal_rcc_ex.h │ ├── stm32h7xx_hal_tim.h │ ├── stm32h7xx_hal_tim_ex.h │ ├── stm32h7xx_hal_uart.h │ └── stm32h7xx_hal_uart_ex.h │ └── Src │ ├── stm32h7xx_hal.c │ ├── stm32h7xx_hal_cortex.c │ ├── stm32h7xx_hal_dma.c │ ├── stm32h7xx_hal_dma_ex.c │ ├── stm32h7xx_hal_exti.c │ ├── stm32h7xx_hal_flash.c │ ├── stm32h7xx_hal_flash_ex.c │ ├── stm32h7xx_hal_gpio.c │ ├── stm32h7xx_hal_hsem.c │ ├── stm32h7xx_hal_i2c.c │ ├── stm32h7xx_hal_i2c_ex.c │ ├── stm32h7xx_hal_mdma.c │ ├── stm32h7xx_hal_pwr.c │ ├── stm32h7xx_hal_pwr_ex.c │ ├── stm32h7xx_hal_rcc.c │ ├── stm32h7xx_hal_rcc_ex.c │ ├── stm32h7xx_hal_tim.c │ ├── stm32h7xx_hal_tim_ex.c │ ├── stm32h7xx_hal_uart.c │ └── stm32h7xx_hal_uart_ex.c ├── middlewares └── ringbuff │ └── src │ ├── include │ └── ringbuff │ │ └── ringbuff.h │ └── ringbuff │ └── ringbuff.c └── projects ├── RemoteSystemsTempFiles └── .project └── nucleo_stm32h745_q_aync_comm ├── .project ├── CM4 ├── .cproject ├── .project ├── Core │ ├── Inc │ │ ├── main.h │ │ ├── stm32h7xx_hal_conf.h │ │ └── stm32h7xx_it.h │ ├── Src │ │ ├── main.c │ │ ├── stm32h7xx_hal_msp.c │ │ ├── stm32h7xx_it.c │ │ ├── syscalls.c │ │ └── sysmem.c │ └── Startup │ │ └── startup_stm32h745zitx.s ├── STM32H745ZITX_FLASH.ld ├── STM32H745ZITX_RAM.ld └── nucleo_stm32h745_q_aync_comm_CM4.launch ├── CM7 ├── .cproject ├── .project ├── Core │ ├── Inc │ │ ├── main.h │ │ ├── stm32h7xx_hal_conf.h │ │ └── stm32h7xx_it.h │ ├── Src │ │ ├── main.c │ │ ├── stm32h7xx_hal_msp.c │ │ ├── stm32h7xx_it.c │ │ ├── syscalls.c │ │ └── sysmem.c │ └── Startup │ │ └── startup_stm32h745zitx.s ├── STM32H745ZITX_FLASH.ld ├── STM32H745ZITX_RAM.ld └── nucleo_stm32h745_q_aync_comm_CM7.launch └── Common ├── Inc └── common.h └── Src └── system_stm32h7xx_dualcore_boot_cm4_cm7.c /.github/FUNDING.yml: -------------------------------------------------------------------------------- 1 | # These are supported funding model platforms 2 | 3 | custom: ['paypal.me/tilz0R'] 4 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | #Build Keil files 2 | *.rar 3 | *.o 4 | *.d 5 | *.crf 6 | *.htm 7 | *.dep 8 | *.map 9 | *.bak 10 | *.axf 11 | *.lnp 12 | *.lst 13 | *.ini 14 | *.scvd 15 | *.iex 16 | *.sct 17 | *.MajerleT 18 | *.tjuln 19 | *.tilen 20 | *.dbgconf 21 | *.uvguix 22 | *.uvoptx 23 | *.__i 24 | *.i 25 | *.txt 26 | !docs/*.txt 27 | RTE/ 28 | 29 | # IAR Settings 30 | **/settings/*.crun 31 | **/settings/*.dbgdt 32 | **/settings/*.cspy 33 | **/settings/*.cspy.* 34 | **/settings/*.xcl 35 | **/settings/*.dni 36 | **/settings/*.wsdt 37 | **/settings/*.wspos 38 | 39 | # IAR Debug Exe 40 | **/Exe/*.sim 41 | 42 | # IAR Debug Obj 43 | **/Obj/*.pbd 44 | **/Obj/*.pbd.* 45 | **/Obj/*.pbi 46 | **/Obj/*.pbi.* 47 | 48 | *.TMP 49 | /docs_src/x_Doxyfile.doxy 50 | 51 | .DS_Store 52 | 53 | ## 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Backup files are not needed, 290 | # because we have git ;-) 291 | _UpgradeReport_Files/ 292 | Backup*/ 293 | UpgradeLog*.XML 294 | UpgradeLog*.htm 295 | 296 | # SQL Server files 297 | *.mdf 298 | *.ldf 299 | *.ndf 300 | 301 | # Business Intelligence projects 302 | *.rdl.data 303 | *.bim.layout 304 | *.bim_*.settings 305 | 306 | # Microsoft Fakes 307 | FakesAssemblies/ 308 | 309 | # GhostDoc plugin setting file 310 | *.GhostDoc.xml 311 | 312 | # Node.js Tools for Visual Studio 313 | .ntvs_analysis.dat 314 | node_modules/ 315 | 316 | # TypeScript v1 declaration files 317 | typings/ 318 | 319 | # Visual Studio 6 build log 320 | *.plg 321 | 322 | # Visual Studio 6 workspace options file 323 | *.opt 324 | 325 | # Visual Studio 6 auto-generated workspace file (contains which files were open etc.) 326 | *.vbw 327 | 328 | # Visual Studio LightSwitch build output 329 | **/*.HTMLClient/GeneratedArtifacts 330 | **/*.DesktopClient/GeneratedArtifacts 331 | **/*.DesktopClient/ModelManifest.xml 332 | **/*.Server/GeneratedArtifacts 333 | **/*.Server/ModelManifest.xml 334 | _Pvt_Extensions 335 | 336 | # Paket dependency manager 337 | .paket/paket.exe 338 | paket-files/ 339 | 340 | # FAKE - F# Make 341 | .fake/ 342 | 343 | # JetBrains Rider 344 | .idea/ 345 | *.sln.iml 346 | 347 | # CodeRush 348 | .cr/ 349 | 350 | # Python Tools for Visual Studio (PTVS) 351 | __pycache__/ 352 | *.pyc 353 | 354 | # Cake - Uncomment if you are using it 355 | # tools/** 356 | # !tools/packages.config 357 | 358 | # Tabs Studio 359 | *.tss 360 | 361 | # Telerik's JustMock configuration file 362 | *.jmconfig 363 | 364 | # BizTalk build output 365 | *.btp.cs 366 | *.btm.cs 367 | *.odx.cs 368 | *.xsd.cs 369 | 370 | # OpenCover UI analysis results 371 | OpenCover/ 372 | 373 | # Azure Stream Analytics local run output 374 | ASALocalRun/ 375 | 376 | # MSBuild Binary and Structured Log 377 | *.binlog 378 | 379 | log_file.txt 380 | .metadata/ 381 | .mxproject 382 | .settings/ 383 | project.ioc 384 | mx.scratch 385 | *.tilen majerle 386 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2020 Tilen Majerle 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # STM32H7 dual-core inter-CPU communication 2 | 3 | Example project for inter-processor communication between 2 cores, ARM Cortex-M7 and ARM-Cortex-M4 cores. 4 | 5 | ## How it works 6 | 7 | This example demonstrates how to implement communication between both cores to exchange data. 8 | It uses shared RAM and `2` separate ring buffers, acting like pipe (single input, single output) 9 | in both direction. First buffer from CPU1 to CPU2, second buffer from CPU2 to CPU1. 10 | 11 | SRAM4 is used as shared RAM in D3 domain. This RAM is preferred and suggested to be used for shared RAM 12 | in dual-core STM32H7xx series for inter-CPU communication. It is outside both domains of both CPU cores, 13 | not affecting to low-power features of each domain. 14 | 15 | ![Bus matrix](docs/bus_matrix.png) 16 | 17 | ## Used hardware 18 | 19 | Example runs on official ST Nucleo boards for dual-core STM32H7 series, listed below. 20 | 21 | * [Nucleo-H745ZI-Q](https://www.st.com/en/evaluation-tools/nucleo-h745zi-q.html) 22 | * [Nucleo-H755ZI-Q](https://www.st.com/en/evaluation-tools/nucleo-h755zi-q.html) 23 | 24 | ## STM32H7 option bytes configuration 25 | 26 | STM32H7 dual-core CPU must have some option bytes configured to run the example properly. 27 | Example is configured for this configuration: 28 | 29 | * CPU1 (Cortex-M7) flash memory address is `0x08000000` and its size is `1MB` 30 | * CPU2 (Cortex-M4) flash memory address is `0x08100000` and its size is `1MB` 31 | * CPU1 boot option must be enabled to ensure Cortex-M7 starts after reset 32 | * CPU2 boot can be enabled or disabled. CPU1 always starts CPU2 by software, regardless of CPU2 boot configuration 33 | 34 | ![Option bytes snippet](docs/option_bytes.png) 35 | 36 | > Option bytes can be configured using [STM32CubeProgrammer](https://www.st.com/en/development-tools/stm32cubeprog.html) software 37 | 38 | ## Run examples 39 | 40 | Run examples with [STM32CubeIDE v1.3.0](https://www.st.com/en/development-tools/stm32cubeide.html) or later toolchain. 41 | -------------------------------------------------------------------------------- /docs/bus_matrix.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaJerle/stm32h7-dual-core-inter-cpu-async-communication/0a84cb42ccab63323a0e01a5a803251650656ab2/docs/bus_matrix.png -------------------------------------------------------------------------------- /docs/option_bytes.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaJerle/stm32h7-dual-core-inter-cpu-async-communication/0a84cb42ccab63323a0e01a5a803251650656ab2/docs/option_bytes.png -------------------------------------------------------------------------------- /docs/requirements.txt: -------------------------------------------------------------------------------- 1 | sphinx>=3.5.1 2 | breathe>=4.9.1 3 | urllib3==1.26.18 4 | docutils==0.16 5 | colorama 6 | sphinx_rtd_theme>=1.0.0 7 | sphinx-tabs 8 | sphinxcontrib-svg2pdfconverter 9 | sphinx-sitemap 10 | -------------------------------------------------------------------------------- /drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaJerle/stm32h7-dual-core-inter-cpu-async-communication/0a84cb42ccab63323a0e01a5a803251650656ab2/drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h -------------------------------------------------------------------------------- /drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32h7xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-Mx Device System Source File for STM32H7xx devices. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /** @addtogroup CMSIS 21 | * @{ 22 | */ 23 | 24 | /** @addtogroup stm32h7xx_system 25 | * @{ 26 | */ 27 | 28 | /** 29 | * @brief Define to prevent recursive inclusion 30 | */ 31 | #ifndef SYSTEM_STM32H7XX_H 32 | #define SYSTEM_STM32H7XX_H 33 | 34 | #ifdef __cplusplus 35 | extern "C" { 36 | #endif 37 | 38 | /** @addtogroup STM32H7xx_System_Includes 39 | * @{ 40 | */ 41 | 42 | /** 43 | * @} 44 | */ 45 | 46 | 47 | /** @addtogroup STM32H7xx_System_Exported_types 48 | * @{ 49 | */ 50 | /* This variable is updated in three ways: 51 | 1) by calling CMSIS function SystemCoreClockUpdate() 52 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq() 53 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 54 | Note: If you use this function to configure the system clock; then there 55 | is no need to call the 2 first functions listed above, since SystemCoreClock 56 | variable is updated automatically. 57 | */ 58 | extern uint32_t SystemCoreClock; /*!< System Domain1 Clock Frequency */ 59 | extern uint32_t SystemD2Clock; /*!< System Domain2 Clock Frequency */ 60 | extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @addtogroup STM32H7xx_System_Exported_Constants 67 | * @{ 68 | */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @addtogroup STM32H7xx_System_Exported_Macros 75 | * @{ 76 | */ 77 | 78 | /** 79 | * @} 80 | */ 81 | 82 | /** @addtogroup STM32H7xx_System_Exported_Functions 83 | * @{ 84 | */ 85 | 86 | extern void SystemInit(void); 87 | extern void SystemCoreClockUpdate(void); 88 | /** 89 | * @} 90 | */ 91 | 92 | #ifdef __cplusplus 93 | } 94 | #endif 95 | 96 | #endif /* SYSTEM_STM32H7XX_H */ 97 | 98 | /** 99 | * @} 100 | */ 101 | 102 | /** 103 | * @} 104 | */ 105 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 106 | -------------------------------------------------------------------------------- /drivers/CMSIS/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_compiler.h 3 | * @brief CMSIS compiler generic header file 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_COMPILER_H 26 | #define __CMSIS_COMPILER_H 27 | 28 | #include 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6 (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 41 | #include "cmsis_armclang.h" 42 | 43 | 44 | /* 45 | * GNU Compiler 46 | */ 47 | #elif defined ( __GNUC__ ) 48 | #include "cmsis_gcc.h" 49 | 50 | 51 | /* 52 | * IAR Compiler 53 | */ 54 | #elif defined ( __ICCARM__ ) 55 | #include 56 | 57 | 58 | /* 59 | * TI Arm Compiler 60 | */ 61 | #elif defined ( __TI_ARM__ ) 62 | #include 63 | 64 | #ifndef __ASM 65 | #define __ASM __asm 66 | #endif 67 | #ifndef __INLINE 68 | #define __INLINE inline 69 | #endif 70 | #ifndef __STATIC_INLINE 71 | #define __STATIC_INLINE static inline 72 | #endif 73 | #ifndef __STATIC_FORCEINLINE 74 | #define __STATIC_FORCEINLINE __STATIC_INLINE 75 | #endif 76 | #ifndef __NO_RETURN 77 | #define __NO_RETURN __attribute__((noreturn)) 78 | #endif 79 | #ifndef __USED 80 | #define __USED __attribute__((used)) 81 | #endif 82 | #ifndef __WEAK 83 | #define __WEAK __attribute__((weak)) 84 | #endif 85 | #ifndef __PACKED 86 | #define __PACKED __attribute__((packed)) 87 | #endif 88 | #ifndef __PACKED_STRUCT 89 | #define __PACKED_STRUCT struct __attribute__((packed)) 90 | #endif 91 | #ifndef __PACKED_UNION 92 | #define __PACKED_UNION union __attribute__((packed)) 93 | #endif 94 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 97 | #endif 98 | #ifndef __UNALIGNED_UINT16_WRITE 99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 101 | #endif 102 | #ifndef __UNALIGNED_UINT16_READ 103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 105 | #endif 106 | #ifndef __UNALIGNED_UINT32_WRITE 107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 109 | #endif 110 | #ifndef __UNALIGNED_UINT32_READ 111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 113 | #endif 114 | #ifndef __ALIGNED 115 | #define __ALIGNED(x) __attribute__((aligned(x))) 116 | #endif 117 | #ifndef __RESTRICT 118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 119 | #define __RESTRICT 120 | #endif 121 | 122 | 123 | /* 124 | * TASKING Compiler 125 | */ 126 | #elif defined ( __TASKING__ ) 127 | /* 128 | * The CMSIS functions have been implemented as intrinsics in the compiler. 129 | * Please use "carm -?i" to get an up to date list of all intrinsics, 130 | * Including the CMSIS ones. 131 | */ 132 | 133 | #ifndef __ASM 134 | #define __ASM __asm 135 | #endif 136 | #ifndef __INLINE 137 | #define __INLINE inline 138 | #endif 139 | #ifndef __STATIC_INLINE 140 | #define __STATIC_INLINE static inline 141 | #endif 142 | #ifndef __STATIC_FORCEINLINE 143 | #define __STATIC_FORCEINLINE __STATIC_INLINE 144 | #endif 145 | #ifndef __NO_RETURN 146 | #define __NO_RETURN __attribute__((noreturn)) 147 | #endif 148 | #ifndef __USED 149 | #define __USED __attribute__((used)) 150 | #endif 151 | #ifndef __WEAK 152 | #define __WEAK __attribute__((weak)) 153 | #endif 154 | #ifndef __PACKED 155 | #define __PACKED __packed__ 156 | #endif 157 | #ifndef __PACKED_STRUCT 158 | #define __PACKED_STRUCT struct __packed__ 159 | #endif 160 | #ifndef __PACKED_UNION 161 | #define __PACKED_UNION union __packed__ 162 | #endif 163 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 164 | struct __packed__ T_UINT32 { uint32_t v; }; 165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 166 | #endif 167 | #ifndef __UNALIGNED_UINT16_WRITE 168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 170 | #endif 171 | #ifndef __UNALIGNED_UINT16_READ 172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 174 | #endif 175 | #ifndef __UNALIGNED_UINT32_WRITE 176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 178 | #endif 179 | #ifndef __UNALIGNED_UINT32_READ 180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 182 | #endif 183 | #ifndef __ALIGNED 184 | #define __ALIGNED(x) __align(x) 185 | #endif 186 | #ifndef __RESTRICT 187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 188 | #define __RESTRICT 189 | #endif 190 | 191 | 192 | /* 193 | * COSMIC Compiler 194 | */ 195 | #elif defined ( __CSMC__ ) 196 | #include 197 | 198 | #ifndef __ASM 199 | #define __ASM _asm 200 | #endif 201 | #ifndef __INLINE 202 | #define __INLINE inline 203 | #endif 204 | #ifndef __STATIC_INLINE 205 | #define __STATIC_INLINE static inline 206 | #endif 207 | #ifndef __STATIC_FORCEINLINE 208 | #define __STATIC_FORCEINLINE __STATIC_INLINE 209 | #endif 210 | #ifndef __NO_RETURN 211 | // NO RETURN is automatically detected hence no warning here 212 | #define __NO_RETURN 213 | #endif 214 | #ifndef __USED 215 | #warning No compiler specific solution for __USED. __USED is ignored. 216 | #define __USED 217 | #endif 218 | #ifndef __WEAK 219 | #define __WEAK __weak 220 | #endif 221 | #ifndef __PACKED 222 | #define __PACKED @packed 223 | #endif 224 | #ifndef __PACKED_STRUCT 225 | #define __PACKED_STRUCT @packed struct 226 | #endif 227 | #ifndef __PACKED_UNION 228 | #define __PACKED_UNION @packed union 229 | #endif 230 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 231 | @packed struct T_UINT32 { uint32_t v; }; 232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 233 | #endif 234 | #ifndef __UNALIGNED_UINT16_WRITE 235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 237 | #endif 238 | #ifndef __UNALIGNED_UINT16_READ 239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 241 | #endif 242 | #ifndef __UNALIGNED_UINT32_WRITE 243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 245 | #endif 246 | #ifndef __UNALIGNED_UINT32_READ 247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 249 | #endif 250 | #ifndef __ALIGNED 251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 252 | #define __ALIGNED(x) 253 | #endif 254 | #ifndef __RESTRICT 255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 256 | #define __RESTRICT 257 | #endif 258 | 259 | 260 | #else 261 | #error Unknown compiler. 262 | #endif 263 | 264 | 265 | #endif /* __CMSIS_COMPILER_H */ 266 | 267 | -------------------------------------------------------------------------------- /drivers/CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.2 5 | * @date 19. April 2017 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /drivers/CMSIS/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ 78 | (MPU_RBAR_VALID_Msk)) 79 | 80 | /** 81 | * MPU Memory Access Attributes 82 | * 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 84 | * \param IsShareable Region is shareable between multiple bus masters. 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 87 | */ 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 93 | 94 | /** 95 | * MPU Region Attribute and Size Register Value 96 | * 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. 100 | * \param SubRegionDisable Sub-region disable field. 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. 102 | */ 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) 107 | 108 | /** 109 | * MPU Region Attribute and Size Register Value 110 | * 111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 114 | * \param IsShareable Region is shareable between multiple bus masters. 115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 117 | * \param SubRegionDisable Sub-region disable field. 118 | * \param Size Region size of the region to be configured, for example 4K, 8K. 119 | */ 120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 122 | 123 | /** 124 | * MPU Memory Access Attribute for strongly ordered memory. 125 | * - TEX: 000b 126 | * - Shareable 127 | * - Non-cacheable 128 | * - Non-bufferable 129 | */ 130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 131 | 132 | /** 133 | * MPU Memory Access Attribute for device memory. 134 | * - TEX: 000b (if non-shareable) or 010b (if shareable) 135 | * - Shareable or non-shareable 136 | * - Non-cacheable 137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 138 | * 139 | * \param IsShareable Configures the device memory as shareable or non-shareable. 140 | */ 141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 142 | 143 | /** 144 | * MPU Memory Access Attribute for normal memory. 145 | * - TEX: 1BBb (reflecting outer cacheability rules) 146 | * - Shareable or non-shareable 147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 149 | * 150 | * \param OuterCp Configures the outer cache policy. 151 | * \param InnerCp Configures the inner cache policy. 152 | * \param IsShareable Configures the memory as shareable or non-shareable. 153 | */ 154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) 155 | 156 | /** 157 | * MPU Memory Access Attribute non-cacheable policy. 158 | */ 159 | #define ARM_MPU_CACHEP_NOCACHE 0U 160 | 161 | /** 162 | * MPU Memory Access Attribute write-back, write and read allocate policy. 163 | */ 164 | #define ARM_MPU_CACHEP_WB_WRA 1U 165 | 166 | /** 167 | * MPU Memory Access Attribute write-through, no write allocate policy. 168 | */ 169 | #define ARM_MPU_CACHEP_WT_NWA 2U 170 | 171 | /** 172 | * MPU Memory Access Attribute write-back, no write allocate policy. 173 | */ 174 | #define ARM_MPU_CACHEP_WB_NWA 3U 175 | 176 | 177 | /** 178 | * Struct for a single MPU Region 179 | */ 180 | typedef struct { 181 | uint32_t RBAR; //!< The region base address register value (RBAR) 182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 183 | } ARM_MPU_Region_t; 184 | 185 | /** Enable the MPU. 186 | * \param MPU_Control Default access permissions for unconfigured regions. 187 | */ 188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 189 | { 190 | __DSB(); 191 | __ISB(); 192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 195 | #endif 196 | } 197 | 198 | /** Disable the MPU. 199 | */ 200 | __STATIC_INLINE void ARM_MPU_Disable(void) 201 | { 202 | __DSB(); 203 | __ISB(); 204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 206 | #endif 207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 208 | } 209 | 210 | /** Clear and disable the given MPU region. 211 | * \param rnr Region number to be cleared. 212 | */ 213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 214 | { 215 | MPU->RNR = rnr; 216 | MPU->RASR = 0U; 217 | } 218 | 219 | /** Configure an MPU region. 220 | * \param rbar Value for RBAR register. 221 | * \param rsar Value for RSAR register. 222 | */ 223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 224 | { 225 | MPU->RBAR = rbar; 226 | MPU->RASR = rasr; 227 | } 228 | 229 | /** Configure the given MPU region. 230 | * \param rnr Region number to be configured. 231 | * \param rbar Value for RBAR register. 232 | * \param rsar Value for RSAR register. 233 | */ 234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 235 | { 236 | MPU->RNR = rnr; 237 | MPU->RBAR = rbar; 238 | MPU->RASR = rasr; 239 | } 240 | 241 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 242 | * \param dst Destination data is copied to. 243 | * \param src Source data is copied from. 244 | * \param len Amount of data words to be copied. 245 | */ 246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 247 | { 248 | uint32_t i; 249 | for (i = 0U; i < len; ++i) 250 | { 251 | dst[i] = src[i]; 252 | } 253 | } 254 | 255 | /** Load the given number of MPU regions from a table. 256 | * \param table Pointer to the MPU configuration table. 257 | * \param cnt Amount of regions to be configured. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 260 | { 261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 262 | while (cnt > MPU_TYPE_RALIASES) { 263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); 264 | table += MPU_TYPE_RALIASES; 265 | cnt -= MPU_TYPE_RALIASES; 266 | } 267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); 268 | } 269 | 270 | #endif 271 | -------------------------------------------------------------------------------- /drivers/CMSIS/Include/mpu_armv8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv8.h 3 | * @brief CMSIS MPU API for Armv8-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV8_H 32 | #define ARM_MPU_ARMV8_H 33 | 34 | /** \brief Attribute for device memory (outer only) */ 35 | #define ARM_MPU_ATTR_DEVICE ( 0U ) 36 | 37 | /** \brief Attribute for non-cacheable, normal memory */ 38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) 39 | 40 | /** \brief Attribute for normal memory (outer and inner) 41 | * \param NT Non-Transient: Set to 1 for non-transient data. 42 | * \param WB Write-Back: Set to 1 to use write-back update policy. 43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 | */ 46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 | 49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ 50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 51 | 52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 54 | 55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 57 | 58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U) 60 | 61 | /** \brief Memory Attribute 62 | * \param O Outer memory attributes 63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 64 | */ 65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 66 | 67 | /** \brief Normal memory non-shareable */ 68 | #define ARM_MPU_SH_NON (0U) 69 | 70 | /** \brief Normal memory outer shareable */ 71 | #define ARM_MPU_SH_OUTER (2U) 72 | 73 | /** \brief Normal memory inner shareable */ 74 | #define ARM_MPU_SH_INNER (3U) 75 | 76 | /** \brief Memory access permissions 77 | * \param RO Read-Only: Set to 1 for read-only memory. 78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory. 79 | */ 80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 81 | 82 | /** \brief Region Base Address Register value 83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. 84 | * \param SH Defines the Shareability domain for this memory region. 85 | * \param RO Read-Only: Set to 1 for a read-only memory region. 86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. 87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. 88 | */ 89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 90 | ((BASE & MPU_RBAR_BASE_Msk) | \ 91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ 92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ 93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 94 | 95 | /** \brief Region Limit Address Register value 96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 97 | * \param IDX The attribute index to be associated with this memory region. 98 | */ 99 | #define ARM_MPU_RLAR(LIMIT, IDX) \ 100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 102 | (MPU_RLAR_EN_Msk)) 103 | 104 | /** 105 | * Struct for a single MPU Region 106 | */ 107 | typedef struct { 108 | uint32_t RBAR; /*!< Region Base Address Register value */ 109 | uint32_t RLAR; /*!< Region Limit Address Register value */ 110 | } ARM_MPU_Region_t; 111 | 112 | /** Enable the MPU. 113 | * \param MPU_Control Default access permissions for unconfigured regions. 114 | */ 115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 116 | { 117 | __DSB(); 118 | __ISB(); 119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 122 | #endif 123 | } 124 | 125 | /** Disable the MPU. 126 | */ 127 | __STATIC_INLINE void ARM_MPU_Disable(void) 128 | { 129 | __DSB(); 130 | __ISB(); 131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 133 | #endif 134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 135 | } 136 | 137 | #ifdef MPU_NS 138 | /** Enable the Non-secure MPU. 139 | * \param MPU_Control Default access permissions for unconfigured regions. 140 | */ 141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 142 | { 143 | __DSB(); 144 | __ISB(); 145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 148 | #endif 149 | } 150 | 151 | /** Disable the Non-secure MPU. 152 | */ 153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void) 154 | { 155 | __DSB(); 156 | __ISB(); 157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 159 | #endif 160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 161 | } 162 | #endif 163 | 164 | /** Set the memory attribute encoding to the given MPU. 165 | * \param mpu Pointer to the MPU to be configured. 166 | * \param idx The attribute index to be set [0-7] 167 | * \param attr The attribute value to be set. 168 | */ 169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 170 | { 171 | const uint8_t reg = idx / 4U; 172 | const uint32_t pos = ((idx % 4U) * 8U); 173 | const uint32_t mask = 0xFFU << pos; 174 | 175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { 176 | return; // invalid index 177 | } 178 | 179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 180 | } 181 | 182 | /** Set the memory attribute encoding. 183 | * \param idx The attribute index to be set [0-7] 184 | * \param attr The attribute value to be set. 185 | */ 186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 187 | { 188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr); 189 | } 190 | 191 | #ifdef MPU_NS 192 | /** Set the memory attribute encoding to the Non-secure MPU. 193 | * \param idx The attribute index to be set [0-7] 194 | * \param attr The attribute value to be set. 195 | */ 196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 197 | { 198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 199 | } 200 | #endif 201 | 202 | /** Clear and disable the given MPU region of the given MPU. 203 | * \param mpu Pointer to MPU to be used. 204 | * \param rnr Region number to be cleared. 205 | */ 206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 207 | { 208 | mpu->RNR = rnr; 209 | mpu->RLAR = 0U; 210 | } 211 | 212 | /** Clear and disable the given MPU region. 213 | * \param rnr Region number to be cleared. 214 | */ 215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 216 | { 217 | ARM_MPU_ClrRegionEx(MPU, rnr); 218 | } 219 | 220 | #ifdef MPU_NS 221 | /** Clear and disable the given Non-secure MPU region. 222 | * \param rnr Region number to be cleared. 223 | */ 224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 225 | { 226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr); 227 | } 228 | #endif 229 | 230 | /** Configure the given MPU region of the given MPU. 231 | * \param mpu Pointer to MPU to be used. 232 | * \param rnr Region number to be configured. 233 | * \param rbar Value for RBAR register. 234 | * \param rlar Value for RLAR register. 235 | */ 236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 237 | { 238 | mpu->RNR = rnr; 239 | mpu->RBAR = rbar; 240 | mpu->RLAR = rlar; 241 | } 242 | 243 | /** Configure the given MPU region. 244 | * \param rnr Region number to be configured. 245 | * \param rbar Value for RBAR register. 246 | * \param rlar Value for RLAR register. 247 | */ 248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 249 | { 250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 251 | } 252 | 253 | #ifdef MPU_NS 254 | /** Configure the given Non-secure MPU region. 255 | * \param rnr Region number to be configured. 256 | * \param rbar Value for RBAR register. 257 | * \param rlar Value for RLAR register. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 260 | { 261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 262 | } 263 | #endif 264 | 265 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 266 | * \param dst Destination data is copied to. 267 | * \param src Source data is copied from. 268 | * \param len Amount of data words to be copied. 269 | */ 270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 271 | { 272 | uint32_t i; 273 | for (i = 0U; i < len; ++i) 274 | { 275 | dst[i] = src[i]; 276 | } 277 | } 278 | 279 | /** Load the given number of MPU regions from a table to the given MPU. 280 | * \param mpu Pointer to the MPU registers to be used. 281 | * \param rnr First region number to be configured. 282 | * \param table Pointer to the MPU configuration table. 283 | * \param cnt Amount of regions to be configured. 284 | */ 285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 286 | { 287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 288 | if (cnt == 1U) { 289 | mpu->RNR = rnr; 290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 291 | } else { 292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); 293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 294 | 295 | mpu->RNR = rnrBase; 296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { 297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); 299 | table += c; 300 | cnt -= c; 301 | rnrOffset = 0U; 302 | rnrBase += MPU_TYPE_RALIASES; 303 | mpu->RNR = rnrBase; 304 | } 305 | 306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); 307 | } 308 | } 309 | 310 | /** Load the given number of MPU regions from a table. 311 | * \param rnr First region number to be configured. 312 | * \param table Pointer to the MPU configuration table. 313 | * \param cnt Amount of regions to be configured. 314 | */ 315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 316 | { 317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt); 318 | } 319 | 320 | #ifdef MPU_NS 321 | /** Load the given number of MPU regions from a table to the Non-secure MPU. 322 | * \param rnr First region number to be configured. 323 | * \param table Pointer to the MPU configuration table. 324 | * \param cnt Amount of regions to be configured. 325 | */ 326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 327 | { 328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 329 | } 330 | #endif 331 | 332 | #endif 333 | 334 | -------------------------------------------------------------------------------- /drivers/CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32h7xx_hal_def.h 4 | * @author MCD Application Team 5 | * @brief This file contains HAL common defines, enumeration, macros and 6 | * structures definitions. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2017 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef STM32H7xx_HAL_DEF 23 | #define STM32H7xx_HAL_DEF 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32h7xx.h" 31 | #include "Legacy/stm32_hal_legacy.h" 32 | #include 33 | #include 34 | 35 | /* Exported types ------------------------------------------------------------*/ 36 | 37 | /** 38 | * @brief HAL Status structures definition 39 | */ 40 | typedef enum 41 | { 42 | HAL_OK = 0x00, 43 | HAL_ERROR = 0x01, 44 | HAL_BUSY = 0x02, 45 | HAL_TIMEOUT = 0x03 46 | } HAL_StatusTypeDef; 47 | 48 | /** 49 | * @brief HAL Lock structures definition 50 | */ 51 | typedef enum 52 | { 53 | HAL_UNLOCKED = 0x00, 54 | HAL_LOCKED = 0x01 55 | } HAL_LockTypeDef; 56 | 57 | /* Exported macro ------------------------------------------------------------*/ 58 | 59 | #define HAL_MAX_DELAY 0xFFFFFFFFU 60 | 61 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) 62 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) 63 | 64 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ 65 | do{ \ 66 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ 67 | (__DMA_HANDLE__).Parent = (__HANDLE__); \ 68 | } while(0) 69 | 70 | #define UNUSED(x) ((void)(x)) 71 | 72 | /** @brief Reset the Handle's State field. 73 | * @param __HANDLE__: specifies the Peripheral Handle. 74 | * @note This macro can be used for the following purpose: 75 | * - When the Handle is declared as local variable; before passing it as parameter 76 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro 77 | * to set to 0 the Handle's "State" field. 78 | * Otherwise, "State" field may have any random value and the first time the function 79 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed 80 | * (i.e. HAL_PPP_MspInit() will not be executed). 81 | * - When there is a need to reconfigure the low level hardware: instead of calling 82 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). 83 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function 84 | * HAL_PPP_MspInit() which will reconfigure the low level hardware. 85 | * @retval None 86 | */ 87 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) 88 | 89 | #if (USE_RTOS == 1) 90 | #error " USE_RTOS should be 0 in the current HAL release " 91 | #else 92 | #define __HAL_LOCK(__HANDLE__) \ 93 | do{ \ 94 | if((__HANDLE__)->Lock == HAL_LOCKED) \ 95 | { \ 96 | return HAL_BUSY; \ 97 | } \ 98 | else \ 99 | { \ 100 | (__HANDLE__)->Lock = HAL_LOCKED; \ 101 | } \ 102 | }while (0) 103 | 104 | #define __HAL_UNLOCK(__HANDLE__) \ 105 | do{ \ 106 | (__HANDLE__)->Lock = HAL_UNLOCKED; \ 107 | }while (0) 108 | #endif /* USE_RTOS */ 109 | 110 | #if defined ( __GNUC__ ) 111 | #ifndef __weak 112 | #define __weak __attribute__((weak)) 113 | #endif /* __weak */ 114 | #ifndef __packed 115 | #define __packed __attribute__((__packed__)) 116 | #endif /* __packed */ 117 | #endif /* __GNUC__ */ 118 | 119 | 120 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ 121 | #if defined (__GNUC__) /* GNU Compiler */ 122 | #ifndef __ALIGN_END 123 | #define __ALIGN_END __attribute__ ((aligned (4))) 124 | #endif /* __ALIGN_END */ 125 | #ifndef __ALIGN_BEGIN 126 | #define __ALIGN_BEGIN 127 | #endif /* __ALIGN_BEGIN */ 128 | #else 129 | #ifndef __ALIGN_END 130 | #define __ALIGN_END 131 | #endif /* __ALIGN_END */ 132 | #ifndef __ALIGN_BEGIN 133 | #if defined (__CC_ARM) /* ARM Compiler */ 134 | #define __ALIGN_BEGIN __align(4) 135 | #elif defined (__ICCARM__) /* IAR Compiler */ 136 | #define __ALIGN_BEGIN 137 | #endif /* __CC_ARM */ 138 | #endif /* __ALIGN_BEGIN */ 139 | #endif /* __GNUC__ */ 140 | 141 | /* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */ 142 | #if defined (__GNUC__) /* GNU Compiler */ 143 | #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) 144 | #elif defined (__ICCARM__) /* IAR Compiler */ 145 | #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf 146 | #elif defined (__CC_ARM) /* ARM Compiler */ 147 | #define ALIGN_32BYTES(buf) __align(32) buf 148 | #endif 149 | 150 | /** 151 | * @brief __RAM_FUNC definition 152 | */ 153 | #if defined ( __CC_ARM ) 154 | /* ARM Compiler 155 | ------------ 156 | RAM functions are defined using the toolchain options. 157 | Functions that are executed in RAM should reside in a separate source module. 158 | Using the 'Options for File' dialog you can simply change the 'Code / Const' 159 | area of a module to a memory space in physical RAM. 160 | Available memory areas are declared in the 'Target' tab of the 'Options for Target' 161 | dialog. 162 | */ 163 | #define __RAM_FUNC 164 | 165 | #elif defined ( __ICCARM__ ) 166 | /* ICCARM Compiler 167 | --------------- 168 | RAM functions are defined using a specific toolchain keyword "__ramfunc". 169 | */ 170 | #define __RAM_FUNC __ramfunc 171 | 172 | #elif defined ( __GNUC__ ) 173 | /* GNU Compiler 174 | ------------ 175 | RAM functions are defined using a specific toolchain attribute 176 | "__attribute__((section(".RamFunc")))". 177 | */ 178 | #define __RAM_FUNC __attribute__((section(".RamFunc"))) 179 | 180 | #endif 181 | 182 | #ifdef __cplusplus 183 | } 184 | #endif 185 | 186 | #endif /* STM32H7xx_HAL_DEF */ 187 | 188 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 189 | -------------------------------------------------------------------------------- /drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32h7xx_hal_hsem.h 4 | * @author MCD Application Team 5 | * @brief Header file of HSEM HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32H7xx_HAL_HSEM_H 22 | #define STM32H7xx_HAL_HSEM_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32h7xx_hal_def.h" 30 | 31 | /** @addtogroup STM32H7xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup HSEM 36 | * @{ 37 | */ 38 | 39 | /* Exported macro ------------------------------------------------------------*/ 40 | /** @defgroup HSEM_Exported_Macros HSEM Exported Macros 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @brief SemID to mask helper Macro. 46 | * @param __SEMID__: semaphore ID from 0 to 31 47 | * @retval Semaphore Mask. 48 | */ 49 | #define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__)) 50 | 51 | /** 52 | * @brief Enables the specified HSEM interrupts. 53 | * @param __SEM_MASK__: semaphores Mask 54 | * @retval None. 55 | */ 56 | #if defined(DUAL_CORE) 57 | #define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ 58 | (HSEM->C1IER |= (__SEM_MASK__)) : \ 59 | (HSEM->C2IER |= (__SEM_MASK__))) 60 | #else 61 | #define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__)) 62 | #endif /* DUAL_CORE */ 63 | /** 64 | * @brief Disables the specified HSEM interrupts. 65 | * @param __SEM_MASK__: semaphores Mask 66 | * @retval None. 67 | */ 68 | #if defined(DUAL_CORE) 69 | #define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ 70 | (HSEM->C1IER &= ~(__SEM_MASK__)) : \ 71 | (HSEM->C2IER &= ~(__SEM_MASK__))) 72 | #else 73 | #define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__)) 74 | #endif /* DUAL_CORE */ 75 | 76 | /** 77 | * @brief Checks whether interrupt has occurred or not for semaphores specified by a mask. 78 | * @param __SEM_MASK__: semaphores Mask 79 | * @retval semaphores Mask : Semaphores where an interrupt occurred. 80 | */ 81 | #if defined(DUAL_CORE) 82 | #define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ 83 | ((__SEM_MASK__) & HSEM->C1MISR) : \ 84 | ((__SEM_MASK__) & HSEM->C2MISR1)) 85 | #else 86 | #define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR) 87 | #endif /* DUAL_CORE */ 88 | 89 | /** 90 | * @brief Get the semaphores release status flags. 91 | * @param __SEM_MASK__: semaphores Mask 92 | * @retval semaphores Mask : Semaphores where Release flags rise. 93 | */ 94 | #if defined(DUAL_CORE) 95 | #define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ 96 | (__SEM_MASK__) & HSEM->C1ISR : \ 97 | (__SEM_MASK__) & HSEM->C2ISR) 98 | #else 99 | #define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR) 100 | #endif /* DUAL_CORE */ 101 | 102 | /** 103 | * @brief Clears the HSEM Interrupt flags. 104 | * @param __SEM_MASK__: semaphores Mask 105 | * @retval None. 106 | */ 107 | #if defined(DUAL_CORE) 108 | #define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ 109 | (HSEM->C1ICR |= (__SEM_MASK__)) : \ 110 | (HSEM->C2ICR |= (__SEM_MASK__))) 111 | #else 112 | #define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__)) 113 | #endif /* DUAL_CORE */ 114 | 115 | /** 116 | * @} 117 | */ 118 | 119 | /* Exported functions --------------------------------------------------------*/ 120 | /** @defgroup HSEM_Exported_Functions HSEM Exported Functions 121 | * @{ 122 | */ 123 | 124 | /** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions 125 | * @brief HSEM Take and Release functions 126 | * @{ 127 | */ 128 | 129 | /* HSEM semaphore take (lock) using 2-Step method ****************************/ 130 | HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID); 131 | /* HSEM semaphore fast take (lock) using 1-Step method ***********************/ 132 | HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID); 133 | /* HSEM Check semaphore state Taken or not **********************************/ 134 | uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID); 135 | /* HSEM Release **************************************************************/ 136 | void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID); 137 | /* HSEM Release All************************************************************/ 138 | void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID); 139 | 140 | /** 141 | * @} 142 | */ 143 | 144 | /** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions 145 | * @brief HSEM Set and Get Key functions. 146 | * @{ 147 | */ 148 | /* HSEM Set Clear Key *********************************************************/ 149 | void HAL_HSEM_SetClearKey(uint32_t Key); 150 | /* HSEM Get Clear Key *********************************************************/ 151 | uint32_t HAL_HSEM_GetClearKey(void); 152 | /** 153 | * @} 154 | */ 155 | 156 | /** @addtogroup HSEM_Exported_Functions_Group3 157 | * @brief HSEM Notification functions 158 | * @{ 159 | */ 160 | /* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/ 161 | void HAL_HSEM_ActivateNotification(uint32_t SemMask); 162 | /* HSEM Deactivate HSEM Notification (When a semaphore is released) ****************/ 163 | void HAL_HSEM_DeactivateNotification(uint32_t SemMask); 164 | /* HSEM Free Callback (When a semaphore is released) *******************************/ 165 | void HAL_HSEM_FreeCallback(uint32_t SemMask); 166 | /* HSEM IRQ Handler **********************************************************/ 167 | void HAL_HSEM_IRQHandler(void); 168 | 169 | /** 170 | * @} 171 | */ 172 | 173 | /** 174 | * @} 175 | */ 176 | 177 | /* Private macros ------------------------------------------------------------*/ 178 | /** @defgroup HSEM_Private_Macros HSEM Private Macros 179 | * @{ 180 | */ 181 | 182 | #define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX ) 183 | 184 | #define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX ) 185 | 186 | #define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX ) 187 | 188 | #if defined(DUAL_CORE) 189 | #define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \ 190 | ((__COREID__) == HSEM_CPU2_COREID)) 191 | #else 192 | #define IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID) 193 | #endif 194 | 195 | 196 | /** 197 | * @} 198 | */ 199 | 200 | /** 201 | * @} 202 | */ 203 | 204 | /** 205 | * @} 206 | */ 207 | 208 | #ifdef __cplusplus 209 | } 210 | #endif 211 | 212 | #endif /* STM32H7xx_HAL_HSEM_H */ 213 | 214 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 215 | -------------------------------------------------------------------------------- /drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32h7xx_hal_i2c_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of I2C HAL Extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32H7xx_HAL_I2C_EX_H 22 | #define STM32H7xx_HAL_I2C_EX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32h7xx_hal_def.h" 30 | 31 | /** @addtogroup STM32H7xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup I2CEx 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /* Exported constants --------------------------------------------------------*/ 41 | 42 | /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants 43 | * @{ 44 | */ 45 | 46 | /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter 47 | * @{ 48 | */ 49 | #define I2C_ANALOGFILTER_ENABLE 0x00000000U 50 | #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 51 | /** 52 | * @} 53 | */ 54 | 55 | /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus 56 | * @{ 57 | */ 58 | #define I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ 59 | #define I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ 60 | #define I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ 61 | #define I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ 62 | #define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ 63 | #define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ 64 | #define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ 65 | #define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ 66 | /** 67 | * @} 68 | */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /* Exported macro ------------------------------------------------------------*/ 75 | /* Exported functions --------------------------------------------------------*/ 76 | 77 | /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions 78 | * @{ 79 | */ 80 | 81 | /** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions 82 | * @brief Extended features functions 83 | * @{ 84 | */ 85 | 86 | /* Peripheral Control functions ************************************************/ 87 | HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); 88 | HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); 89 | HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); 90 | HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); 91 | void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); 92 | void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); 93 | 94 | /* Private constants ---------------------------------------------------------*/ 95 | /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants 96 | * @{ 97 | */ 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /* Private macros ------------------------------------------------------------*/ 104 | /** @defgroup I2CEx_Private_Macro I2C Extended Private Macros 105 | * @{ 106 | */ 107 | #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ 108 | ((FILTER) == I2C_ANALOGFILTER_DISABLE)) 109 | 110 | #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 111 | 112 | #if (defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP)) 113 | #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ 114 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ 115 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ 116 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ 117 | (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ 118 | (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ 119 | (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ 120 | (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) 121 | #elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) 122 | #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ 123 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ 124 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ 125 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ 126 | (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ 127 | (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ 128 | (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3)) 129 | #elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) 130 | #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ 131 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ 132 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ 133 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ 134 | (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ 135 | (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2)) 136 | #elif defined(SYSCFG_PMCR_I2C1_FMP) 137 | #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ 138 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ 139 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ 140 | (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ 141 | (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1)) 142 | #endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */ 143 | 144 | 145 | 146 | /** 147 | * @} 148 | */ 149 | 150 | /* Private Functions ---------------------------------------------------------*/ 151 | /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions 152 | * @{ 153 | */ 154 | /* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */ 155 | /** 156 | * @} 157 | */ 158 | 159 | /** 160 | * @} 161 | */ 162 | 163 | /** 164 | * @} 165 | */ 166 | 167 | /** 168 | * @} 169 | */ 170 | 171 | /** 172 | * @} 173 | */ 174 | 175 | #ifdef __cplusplus 176 | } 177 | #endif 178 | 179 | #endif /* STM32H7xx_HAL_I2C_EX_H */ 180 | 181 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 182 | -------------------------------------------------------------------------------- /drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32h7xx_hal_i2c_ex.c 4 | * @author MCD Application Team 5 | * @brief I2C Extended HAL module driver. 6 | * This file provides firmware functions to manage the following 7 | * functionalities of I2C Extended peripheral: 8 | * + Extended features functions 9 | * 10 | @verbatim 11 | ============================================================================== 12 | ##### I2C peripheral Extended features ##### 13 | ============================================================================== 14 | 15 | [..] Comparing to other previous devices, the I2C interface for STM32H7xx 16 | devices contains the following additional features 17 | 18 | (+) Possibility to disable or enable Analog Noise Filter 19 | (+) Use of a configured Digital Noise Filter 20 | (+) Disable or enable wakeup from Stop mode(s) 21 | (+) Disable or enable Fast Mode Plus 22 | 23 | ##### How to use this driver ##### 24 | ============================================================================== 25 | [..] This driver provides functions to configure Noise Filter and Wake Up Feature 26 | (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() 27 | (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() 28 | (#) Configure the enable or disable of I2C Wake Up Mode using the functions : 29 | (++) HAL_I2CEx_EnableWakeUp() 30 | (++) HAL_I2CEx_DisableWakeUp() 31 | (#) Configure the enable or disable of fast mode plus driving capability using the functions : 32 | (++) HAL_I2CEx_EnableFastModePlus() 33 | (++) HAL_I2CEx_DisableFastModePlus() 34 | @endverbatim 35 | ****************************************************************************** 36 | * @attention 37 | * 38 | *

© Copyright (c) 2017 STMicroelectronics. 39 | * All rights reserved.

40 | * 41 | * This software component is licensed by ST under BSD 3-Clause license, 42 | * the "License"; You may not use this file except in compliance with the 43 | * License. You may obtain a copy of the License at: 44 | * opensource.org/licenses/BSD-3-Clause 45 | * 46 | ****************************************************************************** 47 | */ 48 | 49 | /* Includes ------------------------------------------------------------------*/ 50 | #include "stm32h7xx_hal.h" 51 | 52 | /** @addtogroup STM32H7xx_HAL_Driver 53 | * @{ 54 | */ 55 | 56 | /** @defgroup I2CEx I2CEx 57 | * @brief I2C Extended HAL module driver 58 | * @{ 59 | */ 60 | 61 | #ifdef HAL_I2C_MODULE_ENABLED 62 | 63 | /* Private typedef -----------------------------------------------------------*/ 64 | /* Private define ------------------------------------------------------------*/ 65 | /* Private macro -------------------------------------------------------------*/ 66 | /* Private variables ---------------------------------------------------------*/ 67 | /* Private function prototypes -----------------------------------------------*/ 68 | /* Private functions ---------------------------------------------------------*/ 69 | 70 | /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions 71 | * @{ 72 | */ 73 | 74 | /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions 75 | * @brief Extended features functions 76 | * 77 | @verbatim 78 | =============================================================================== 79 | ##### Extended features functions ##### 80 | =============================================================================== 81 | [..] This section provides functions allowing to: 82 | (+) Configure Noise Filters 83 | (+) Configure Wake Up Feature 84 | (+) Configure Fast Mode Plus 85 | 86 | @endverbatim 87 | * @{ 88 | */ 89 | 90 | /** 91 | * @brief Configure I2C Analog noise filter. 92 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 93 | * the configuration information for the specified I2Cx peripheral. 94 | * @param AnalogFilter New state of the Analog filter. 95 | * @retval HAL status 96 | */ 97 | HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) 98 | { 99 | /* Check the parameters */ 100 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); 101 | assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); 102 | 103 | if (hi2c->State == HAL_I2C_STATE_READY) 104 | { 105 | /* Process Locked */ 106 | __HAL_LOCK(hi2c); 107 | 108 | hi2c->State = HAL_I2C_STATE_BUSY; 109 | 110 | /* Disable the selected I2C peripheral */ 111 | __HAL_I2C_DISABLE(hi2c); 112 | 113 | /* Reset I2Cx ANOFF bit */ 114 | hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 115 | 116 | /* Set analog filter bit*/ 117 | hi2c->Instance->CR1 |= AnalogFilter; 118 | 119 | __HAL_I2C_ENABLE(hi2c); 120 | 121 | hi2c->State = HAL_I2C_STATE_READY; 122 | 123 | /* Process Unlocked */ 124 | __HAL_UNLOCK(hi2c); 125 | 126 | return HAL_OK; 127 | } 128 | else 129 | { 130 | return HAL_BUSY; 131 | } 132 | } 133 | 134 | /** 135 | * @brief Configure I2C Digital noise filter. 136 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 137 | * the configuration information for the specified I2Cx peripheral. 138 | * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. 139 | * @retval HAL status 140 | */ 141 | HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) 142 | { 143 | uint32_t tmpreg; 144 | 145 | /* Check the parameters */ 146 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); 147 | assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); 148 | 149 | if (hi2c->State == HAL_I2C_STATE_READY) 150 | { 151 | /* Process Locked */ 152 | __HAL_LOCK(hi2c); 153 | 154 | hi2c->State = HAL_I2C_STATE_BUSY; 155 | 156 | /* Disable the selected I2C peripheral */ 157 | __HAL_I2C_DISABLE(hi2c); 158 | 159 | /* Get the old register value */ 160 | tmpreg = hi2c->Instance->CR1; 161 | 162 | /* Reset I2Cx DNF bits [11:8] */ 163 | tmpreg &= ~(I2C_CR1_DNF); 164 | 165 | /* Set I2Cx DNF coefficient */ 166 | tmpreg |= DigitalFilter << 8U; 167 | 168 | /* Store the new register value */ 169 | hi2c->Instance->CR1 = tmpreg; 170 | 171 | __HAL_I2C_ENABLE(hi2c); 172 | 173 | hi2c->State = HAL_I2C_STATE_READY; 174 | 175 | /* Process Unlocked */ 176 | __HAL_UNLOCK(hi2c); 177 | 178 | return HAL_OK; 179 | } 180 | else 181 | { 182 | return HAL_BUSY; 183 | } 184 | } 185 | 186 | /** 187 | * @brief Enable I2C wakeup from Stop mode(s). 188 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 189 | * the configuration information for the specified I2Cx peripheral. 190 | * @retval HAL status 191 | */ 192 | HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) 193 | { 194 | /* Check the parameters */ 195 | assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); 196 | 197 | if (hi2c->State == HAL_I2C_STATE_READY) 198 | { 199 | /* Process Locked */ 200 | __HAL_LOCK(hi2c); 201 | 202 | hi2c->State = HAL_I2C_STATE_BUSY; 203 | 204 | /* Disable the selected I2C peripheral */ 205 | __HAL_I2C_DISABLE(hi2c); 206 | 207 | /* Enable wakeup from stop mode */ 208 | hi2c->Instance->CR1 |= I2C_CR1_WUPEN; 209 | 210 | __HAL_I2C_ENABLE(hi2c); 211 | 212 | hi2c->State = HAL_I2C_STATE_READY; 213 | 214 | /* Process Unlocked */ 215 | __HAL_UNLOCK(hi2c); 216 | 217 | return HAL_OK; 218 | } 219 | else 220 | { 221 | return HAL_BUSY; 222 | } 223 | } 224 | 225 | /** 226 | * @brief Disable I2C wakeup from Stop mode(s). 227 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 228 | * the configuration information for the specified I2Cx peripheral. 229 | * @retval HAL status 230 | */ 231 | HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) 232 | { 233 | /* Check the parameters */ 234 | assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); 235 | 236 | if (hi2c->State == HAL_I2C_STATE_READY) 237 | { 238 | /* Process Locked */ 239 | __HAL_LOCK(hi2c); 240 | 241 | hi2c->State = HAL_I2C_STATE_BUSY; 242 | 243 | /* Disable the selected I2C peripheral */ 244 | __HAL_I2C_DISABLE(hi2c); 245 | 246 | /* Enable wakeup from stop mode */ 247 | hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); 248 | 249 | __HAL_I2C_ENABLE(hi2c); 250 | 251 | hi2c->State = HAL_I2C_STATE_READY; 252 | 253 | /* Process Unlocked */ 254 | __HAL_UNLOCK(hi2c); 255 | 256 | return HAL_OK; 257 | } 258 | else 259 | { 260 | return HAL_BUSY; 261 | } 262 | } 263 | 264 | /** 265 | * @brief Enable the I2C fast mode plus driving capability. 266 | * @param ConfigFastModePlus Selects the pin. 267 | * This parameter can be one of the @ref I2CEx_FastModePlus values 268 | * @note For I2C1, fast mode plus driving capability can be enabled on all selected 269 | * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently 270 | * on each one of the following pins PB6, PB7, PB8 and PB9. 271 | * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability 272 | * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. 273 | * @note For all I2C2 pins fast mode plus driving capability can be enabled 274 | * only by using I2C_FASTMODEPLUS_I2C2 parameter. 275 | * @note For all I2C3 pins fast mode plus driving capability can be enabled 276 | * only by using I2C_FASTMODEPLUS_I2C3 parameter. 277 | * @note For all I2C4 pins fast mode plus driving capability can be enabled 278 | * only by using I2C_FASTMODEPLUS_I2C4 parameter. 279 | * @retval None 280 | */ 281 | void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) 282 | { 283 | /* Check the parameter */ 284 | assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); 285 | 286 | /* Enable SYSCFG clock */ 287 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 288 | 289 | /* Enable fast mode plus driving capability for selected pin */ 290 | SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); 291 | } 292 | 293 | /** 294 | * @brief Disable the I2C fast mode plus driving capability. 295 | * @param ConfigFastModePlus Selects the pin. 296 | * This parameter can be one of the @ref I2CEx_FastModePlus values 297 | * @note For I2C1, fast mode plus driving capability can be disabled on all selected 298 | * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently 299 | * on each one of the following pins PB6, PB7, PB8 and PB9. 300 | * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability 301 | * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. 302 | * @note For all I2C2 pins fast mode plus driving capability can be disabled 303 | * only by using I2C_FASTMODEPLUS_I2C2 parameter. 304 | * @note For all I2C3 pins fast mode plus driving capability can be disabled 305 | * only by using I2C_FASTMODEPLUS_I2C3 parameter. 306 | * @note For all I2C4 pins fast mode plus driving capability can be disabled 307 | * only by using I2C_FASTMODEPLUS_I2C4 parameter. 308 | * @retval None 309 | */ 310 | void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) 311 | { 312 | /* Check the parameter */ 313 | assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); 314 | 315 | /* Enable SYSCFG clock */ 316 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 317 | 318 | /* Disable fast mode plus driving capability for selected pin */ 319 | CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); 320 | } 321 | 322 | /** 323 | * @} 324 | */ 325 | 326 | /** 327 | * @} 328 | */ 329 | 330 | #endif /* HAL_I2C_MODULE_ENABLED */ 331 | /** 332 | * @} 333 | */ 334 | 335 | /** 336 | * @} 337 | */ 338 | 339 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 340 | -------------------------------------------------------------------------------- /middlewares/ringbuff/src/include/ringbuff/ringbuff.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file ringbuff.h 3 | * \brief Ring buffer manager 4 | */ 5 | 6 | /* 7 | * Copyright (c) 2020 Tilen MAJERLE 8 | * 9 | * Permission is hereby granted, free of charge, to any person 10 | * obtaining a copy of this software and associated documentation 11 | * files (the "Software"), to deal in the Software without restriction, 12 | * including without limitation the rights to use, copy, modify, merge, 13 | * publish, distribute, sublicense, and/or sell copies of the Software, 14 | * and to permit persons to whom the Software is furnished to do so, 15 | * subject to the following conditions: 16 | * 17 | * The above copyright notice and this permission notice shall be 18 | * included in all copies or substantial portions of the Software. 19 | * 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 22 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 23 | * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 24 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 25 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 26 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 27 | * OTHER DEALINGS IN THE SOFTWARE. 28 | * 29 | * This file is part of ring buffer library. 30 | * 31 | * Author: Tilen MAJERLE 32 | * Version: v1.3.1 33 | */ 34 | #ifndef RINGBUFF_HDR_H 35 | #define RINGBUFF_HDR_H 36 | 37 | #include 38 | #include 39 | 40 | #ifdef __cplusplus 41 | extern "C" { 42 | #endif /* __cplusplus */ 43 | 44 | /** 45 | * \defgroup RINGBUFF Ring buffer 46 | * \brief Generic ring buffer manager 47 | * \{ 48 | */ 49 | 50 | /** 51 | * \brief Enable buffer structure pointer parameter as volatile 52 | * To use this feature, uncomment keyword below 53 | */ 54 | #define RINGBUFF_VOLATILE volatile 55 | 56 | /** 57 | * \brief Adds 2 magic words to make sure if memory is corrupted 58 | * application can detect wrong data pointer and maximum size 59 | */ 60 | #define RINGBUFF_USE_MAGIC 1 61 | 62 | /** 63 | * \brief Event type for buffer operations 64 | */ 65 | typedef enum { 66 | RINGBUFF_EVT_READ, /*!< Read event */ 67 | RINGBUFF_EVT_WRITE, /*!< Write event */ 68 | RINGBUFF_EVT_RESET, /*!< Reset event */ 69 | } ringbuff_evt_type_t; 70 | 71 | /** 72 | * \brief Buffer structure forward declaration 73 | */ 74 | struct ringbuff; 75 | 76 | /** 77 | * \brief Event callback function type 78 | * \param[in] buff: Buffer handle for event 79 | * \param[in] evt: Event type 80 | * \param[in] bp: Number of bytes written or read (when used), depends on event type 81 | */ 82 | typedef void (*ringbuff_evt_fn)(RINGBUFF_VOLATILE struct ringbuff* buff, ringbuff_evt_type_t evt, size_t bp); 83 | 84 | /** 85 | * \brief Buffer structure 86 | */ 87 | typedef struct ringbuff { 88 | #if RINGBUFF_USE_MAGIC 89 | uint32_t magic1; /*!< Magic 1 word */ 90 | #endif /* RINGBUFF_USE_MAGIC */ 91 | uint8_t* buff; /*!< Pointer to buffer data. 92 | Buffer is considered initialized when `buff != NULL` and `size > 0` */ 93 | size_t size; /*!< Size of buffer data. Size of actual buffer is `1` byte less than value holds */ 94 | size_t r; /*!< Next read pointer. Buffer is considered empty when `r == w` and full when `w == r - 1` */ 95 | size_t w; /*!< Next write pointer. Buffer is considered empty when `r == w` and full when `w == r - 1` */ 96 | ringbuff_evt_fn evt_fn; /*!< Pointer to event callback function */ 97 | #if RINGBUFF_USE_MAGIC 98 | uint32_t magic2; /*!< Magic 2 word */ 99 | #endif /* RINGBUFF_USE_MAGIC */ 100 | } ringbuff_t; 101 | 102 | uint8_t ringbuff_init(RINGBUFF_VOLATILE ringbuff_t* buff, void* buffdata, size_t size); 103 | uint8_t ringbuff_is_ready(RINGBUFF_VOLATILE ringbuff_t* buff); 104 | void ringbuff_free(RINGBUFF_VOLATILE ringbuff_t* buff); 105 | void ringbuff_reset(RINGBUFF_VOLATILE ringbuff_t* buff); 106 | void ringbuff_set_evt_fn(RINGBUFF_VOLATILE ringbuff_t* buff, ringbuff_evt_fn fn); 107 | 108 | /* Read/Write functions */ 109 | size_t ringbuff_write(RINGBUFF_VOLATILE ringbuff_t* buff, const void* data, size_t btw); 110 | size_t ringbuff_read(RINGBUFF_VOLATILE ringbuff_t* buff, void* data, size_t btr); 111 | size_t ringbuff_peek(RINGBUFF_VOLATILE ringbuff_t* buff, size_t skip_count, void* data, size_t btp); 112 | 113 | /* Buffer size information */ 114 | size_t ringbuff_get_free(RINGBUFF_VOLATILE ringbuff_t* buff); 115 | size_t ringbuff_get_full(RINGBUFF_VOLATILE ringbuff_t* buff); 116 | 117 | /* Read data block management */ 118 | void * ringbuff_get_linear_block_read_address(RINGBUFF_VOLATILE ringbuff_t* buff); 119 | size_t ringbuff_get_linear_block_read_length(RINGBUFF_VOLATILE ringbuff_t* buff); 120 | size_t ringbuff_skip(RINGBUFF_VOLATILE ringbuff_t* buff, size_t len); 121 | 122 | /* Write data block management */ 123 | void * ringbuff_get_linear_block_write_address(RINGBUFF_VOLATILE ringbuff_t* buff); 124 | size_t ringbuff_get_linear_block_write_length(RINGBUFF_VOLATILE ringbuff_t* buff); 125 | size_t ringbuff_advance(RINGBUFF_VOLATILE ringbuff_t* buff, size_t len); 126 | 127 | /** 128 | * \} 129 | */ 130 | 131 | #ifdef __cplusplus 132 | } 133 | #endif /* __cplusplus */ 134 | 135 | #endif /* RINGBUFF_HDR_H */ 136 | -------------------------------------------------------------------------------- /projects/RemoteSystemsTempFiles/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | RemoteSystemsTempFiles 4 | 5 | 6 | 7 | 8 | 9 | 10 | org.eclipse.rse.ui.remoteSystemsTempNature 11 | 12 | 13 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | nucleo_stm32h745_q_aync_comm 4 | 5 | 6 | 7 | 8 | 9 | 10 | com.st.stm32cube.ide.mcu.MCUProjectNature 11 | com.st.stm32cube.ide.mcu.MCUCubeProjectNature 12 | com.st.stm32cube.ide.mcu.MCURootProjectNature 13 | com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature 14 | com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature 15 | com.st.stm32cube.ide.mcu.MCUMultiCpuProjectNature 16 | 17 | 18 | 19 | 1586929617426 20 | 21 | 22 22 | 23 | org.eclipse.ui.ide.multiFilter 24 | 1.0-name-matches-false-false-*.launch 25 | 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM4/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | nucleo_stm32h745_q_aync_comm_CM4 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | com.st.stm32cube.ide.mcu.MCUProjectNature 23 | org.eclipse.cdt.core.cnature 24 | com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature 25 | com.st.stm32cube.ide.mcu.MCUCubeProjectNature 26 | com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature 27 | com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature 28 | com.st.stm32cube.ide.mcu.MCUMultiCpuProjectNature 29 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 30 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 31 | 32 | 33 | 34 | Common 35 | 2 36 | $%7BPARENT-1-PROJECT_LOC%7D/Common 37 | 38 | 39 | Drivers 40 | 2 41 | $%7BPARENT-1-PROJECT_LOC%7D/Drivers 42 | 43 | 44 | Drivers/stm32h7xx_hal.c 45 | 1 46 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c 47 | 48 | 49 | Drivers/stm32h7xx_hal_cortex.c 50 | 1 51 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c 52 | 53 | 54 | Drivers/stm32h7xx_hal_dma.c 55 | 1 56 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c 57 | 58 | 59 | Drivers/stm32h7xx_hal_dma_ex.c 60 | 1 61 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c 62 | 63 | 64 | Drivers/stm32h7xx_hal_exti.c 65 | 1 66 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c 67 | 68 | 69 | Drivers/stm32h7xx_hal_flash.c 70 | 1 71 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c 72 | 73 | 74 | Drivers/stm32h7xx_hal_flash_ex.c 75 | 1 76 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c 77 | 78 | 79 | Drivers/stm32h7xx_hal_gpio.c 80 | 1 81 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c 82 | 83 | 84 | Drivers/stm32h7xx_hal_hsem.c 85 | 1 86 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c 87 | 88 | 89 | Drivers/stm32h7xx_hal_i2c.c 90 | 1 91 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c 92 | 93 | 94 | Drivers/stm32h7xx_hal_i2c_ex.c 95 | 1 96 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c 97 | 98 | 99 | Drivers/stm32h7xx_hal_mdma.c 100 | 1 101 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c 102 | 103 | 104 | Drivers/stm32h7xx_hal_pwr.c 105 | 1 106 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c 107 | 108 | 109 | Drivers/stm32h7xx_hal_pwr_ex.c 110 | 1 111 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c 112 | 113 | 114 | Drivers/stm32h7xx_hal_rcc.c 115 | 1 116 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c 117 | 118 | 119 | Drivers/stm32h7xx_hal_rcc_ex.c 120 | 1 121 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c 122 | 123 | 124 | Drivers/stm32h7xx_hal_tim.c 125 | 1 126 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c 127 | 128 | 129 | Drivers/stm32h7xx_hal_tim_ex.c 130 | 1 131 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c 132 | 133 | 134 | Drivers/stm32h7xx_hal_uart.c 135 | 1 136 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c 137 | 138 | 139 | Drivers/stm32h7xx_hal_uart_ex.c 140 | 1 141 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c 142 | 143 | 144 | Core/Src/ringbuff.c 145 | 1 146 | copy_PARENT/middlewares/ringbuff/src/ringbuff/ringbuff.c 147 | 148 | 149 | 150 | 151 | copy_PARENT 152 | $%7BPARENT-3-PROJECT_LOC%7D 153 | 154 | 155 | 156 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM4/Core/Inc/main.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.h 5 | * @brief : Header for main.c file. 6 | * This file contains the common defines of the application. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2020 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | /* USER CODE END Header */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __MAIN_H 24 | #define __MAIN_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32h7xx_hal.h" 32 | 33 | /* Private includes ----------------------------------------------------------*/ 34 | /* USER CODE BEGIN Includes */ 35 | 36 | /* USER CODE END Includes */ 37 | 38 | /* Exported types ------------------------------------------------------------*/ 39 | /* USER CODE BEGIN ET */ 40 | 41 | /* USER CODE END ET */ 42 | 43 | /* Exported constants --------------------------------------------------------*/ 44 | /* USER CODE BEGIN EC */ 45 | 46 | /* USER CODE END EC */ 47 | 48 | /* Exported macro ------------------------------------------------------------*/ 49 | /* USER CODE BEGIN EM */ 50 | 51 | /* USER CODE END EM */ 52 | 53 | /* Exported functions prototypes ---------------------------------------------*/ 54 | void Error_Handler(void); 55 | 56 | /* USER CODE BEGIN EFP */ 57 | 58 | /* USER CODE END EFP */ 59 | 60 | /* Private defines -----------------------------------------------------------*/ 61 | /* USER CODE BEGIN Private defines */ 62 | 63 | /* USER CODE END Private defines */ 64 | 65 | #ifdef __cplusplus 66 | } 67 | #endif 68 | 69 | #endif /* __MAIN_H */ 70 | 71 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 72 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM4/Core/Inc/stm32h7xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32h7xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2020 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32H7xx_IT_H 23 | #define __STM32H7xx_IT_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Private includes ----------------------------------------------------------*/ 30 | /* USER CODE BEGIN Includes */ 31 | 32 | /* USER CODE END Includes */ 33 | 34 | /* Exported types ------------------------------------------------------------*/ 35 | /* USER CODE BEGIN ET */ 36 | 37 | /* USER CODE END ET */ 38 | 39 | /* Exported constants --------------------------------------------------------*/ 40 | /* USER CODE BEGIN EC */ 41 | 42 | /* USER CODE END EC */ 43 | 44 | /* Exported macro ------------------------------------------------------------*/ 45 | /* USER CODE BEGIN EM */ 46 | 47 | /* USER CODE END EM */ 48 | 49 | /* Exported functions prototypes ---------------------------------------------*/ 50 | void NMI_Handler(void); 51 | void HardFault_Handler(void); 52 | void MemManage_Handler(void); 53 | void BusFault_Handler(void); 54 | void UsageFault_Handler(void); 55 | void SVC_Handler(void); 56 | void DebugMon_Handler(void); 57 | void PendSV_Handler(void); 58 | void SysTick_Handler(void); 59 | void HSEM2_IRQHandler(void); 60 | /* USER CODE BEGIN EFP */ 61 | 62 | /* USER CODE END EFP */ 63 | 64 | #ifdef __cplusplus 65 | } 66 | #endif 67 | 68 | #endif /* __STM32H7xx_IT_H */ 69 | 70 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 71 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM4/Core/Src/main.c: -------------------------------------------------------------------------------- 1 | /** 2 | * \file main.c 3 | * 4 | * Cortex-M4 main.c file 5 | */ 6 | 7 | /* Includes ------------------------------------------------------------------*/ 8 | #include "main.h" 9 | #include "common.h" 10 | 11 | /* Ringbuffer variables */ 12 | volatile ringbuff_t* rb_cm4_to_cm7 = (void *)BUFF_CM4_TO_CM7_ADDR; 13 | volatile ringbuff_t* rb_cm7_to_cm4 = (void *)BUFF_CM7_TO_CM4_ADDR; 14 | static void led_init(void); 15 | 16 | /** 17 | * \brief The application entry point 18 | */ 19 | int 20 | main(void) { 21 | uint32_t i = 0, time, t1, t2; 22 | 23 | /* CPU2 goes to STOP mode and waits CPU1 to initialize all the steps first */ 24 | /* CPU1 will wakeup CPU2 with semaphore take and release events */ 25 | /* HW semaphore Clock enable */ 26 | __HAL_RCC_HSEM_CLK_ENABLE(); 27 | HAL_HSEM_ActivateNotification(HSEM_WAKEUP_CPU2_MASK); 28 | HAL_PWREx_ClearPendingEvent(); 29 | HAL_PWREx_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFE, PWR_D2_DOMAIN); 30 | __HAL_HSEM_CLEAR_FLAG(HSEM_WAKEUP_CPU2_MASK); 31 | 32 | /* MCU Configuration--------------------------------------------------------*/ 33 | 34 | /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 35 | HAL_Init(); 36 | 37 | /* Init LED3 */ 38 | led_init(); 39 | 40 | /* 41 | * Wait for buffers to be ready by CPU1 42 | * 43 | * This should not wait and should go straight through 44 | */ 45 | while (!ringbuff_is_ready(rb_cm4_to_cm7) || !ringbuff_is_ready(rb_cm7_to_cm4)) {} 46 | 47 | /* Write message to buffer */ 48 | ringbuff_write(rb_cm4_to_cm7, "[CM4] Core ready\r\n", 18); 49 | 50 | /* Set default time */ 51 | time = t1 = t2 = HAL_GetTick(); 52 | while (1) { 53 | size_t len; 54 | void* addr; 55 | 56 | time = HAL_GetTick(); 57 | 58 | /* Send data to CPU1 */ 59 | if (time - t1 >= 1000) { 60 | t1 = time; 61 | char c = '0' + (++i % 10); 62 | 63 | /* Write to buffer from CPU2 to CPU1 */ 64 | ringbuff_write(rb_cm4_to_cm7, "[CM4] Number: ", 14); 65 | ringbuff_write(rb_cm4_to_cm7, &c, 1); 66 | ringbuff_write(rb_cm4_to_cm7, "\r\n", 2); 67 | } 68 | 69 | /* Toggle LED */ 70 | if (time - t2 >= 500) { 71 | t2 = time; 72 | HAL_GPIO_TogglePin(LD3_GPIO_PORT, LD3_GPIO_PIN); 73 | } 74 | 75 | /* Check if CPU1 sent some data to CPU2 core */ 76 | while ((len = ringbuff_get_linear_block_read_length(rb_cm7_to_cm4)) > 0) { 77 | addr = ringbuff_get_linear_block_read_address(rb_cm7_to_cm4); 78 | 79 | /* 80 | * `addr` holds pointer to beginning of data array 81 | * which can be used directly in linear form. 82 | * 83 | * Its length is `len` bytes 84 | */ 85 | /* Process data here */ 86 | 87 | /* Mark buffer as read to allow other writes from CPU1 */ 88 | ringbuff_skip(rb_cm7_to_cm4, len); 89 | } 90 | } 91 | } 92 | 93 | /** 94 | * \brief Initialize LEDs controlled by core 95 | */ 96 | void 97 | led_init(void) { 98 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 99 | 100 | LD3_GPIO_CLK_EN(); 101 | 102 | GPIO_InitStruct.Pin = LD3_GPIO_PIN; 103 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 104 | GPIO_InitStruct.Pull = GPIO_NOPULL; 105 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 106 | HAL_GPIO_Init(LD3_GPIO_PORT, &GPIO_InitStruct); 107 | } 108 | 109 | /** 110 | * \brief This function is executed in case of error occurrence 111 | */ 112 | void 113 | Error_Handler(void) { 114 | 115 | } 116 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM4/Core/Src/stm32h7xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * File Name : stm32h7xx_hal_msp.c 5 | * Description : This file provides code for the MSP Initialization 6 | * and de-Initialization codes. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2020 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | /* USER CODE END Header */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "main.h" 24 | /* USER CODE BEGIN Includes */ 25 | 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN TD */ 30 | 31 | /* USER CODE END TD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN Define */ 35 | 36 | /* USER CODE END Define */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN Macro */ 40 | 41 | /* USER CODE END Macro */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* USER CODE BEGIN PV */ 45 | 46 | /* USER CODE END PV */ 47 | 48 | /* Private function prototypes -----------------------------------------------*/ 49 | /* USER CODE BEGIN PFP */ 50 | 51 | /* USER CODE END PFP */ 52 | 53 | /* External functions --------------------------------------------------------*/ 54 | /* USER CODE BEGIN ExternalFunctions */ 55 | 56 | /* USER CODE END ExternalFunctions */ 57 | 58 | /* USER CODE BEGIN 0 */ 59 | 60 | /* USER CODE END 0 */ 61 | /** 62 | * Initializes the Global MSP. 63 | */ 64 | void HAL_MspInit(void) 65 | { 66 | /* USER CODE BEGIN MspInit 0 */ 67 | 68 | /* USER CODE END MspInit 0 */ 69 | 70 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 71 | 72 | /* System interrupt init*/ 73 | 74 | /* Peripheral interrupt init */ 75 | /* HSEM2_IRQn interrupt configuration */ 76 | HAL_NVIC_SetPriority(HSEM2_IRQn, 0, 0); 77 | HAL_NVIC_EnableIRQ(HSEM2_IRQn); 78 | 79 | /* USER CODE BEGIN MspInit 1 */ 80 | 81 | /* USER CODE END MspInit 1 */ 82 | } 83 | 84 | /* USER CODE BEGIN 1 */ 85 | 86 | /* USER CODE END 1 */ 87 | 88 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 89 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM4/Core/Src/stm32h7xx_it.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32h7xx_it.c 5 | * @brief Interrupt Service Routines. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2020 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "main.h" 23 | #include "stm32h7xx_it.h" 24 | /* Private includes ----------------------------------------------------------*/ 25 | /* USER CODE BEGIN Includes */ 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN TD */ 30 | 31 | /* USER CODE END TD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN PD */ 35 | 36 | /* USER CODE END PD */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN PM */ 40 | 41 | /* USER CODE END PM */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* USER CODE BEGIN PV */ 45 | 46 | /* USER CODE END PV */ 47 | 48 | /* Private function prototypes -----------------------------------------------*/ 49 | /* USER CODE BEGIN PFP */ 50 | 51 | /* USER CODE END PFP */ 52 | 53 | /* Private user code ---------------------------------------------------------*/ 54 | /* USER CODE BEGIN 0 */ 55 | 56 | /* USER CODE END 0 */ 57 | 58 | /* External variables --------------------------------------------------------*/ 59 | 60 | /* USER CODE BEGIN EV */ 61 | 62 | /* USER CODE END EV */ 63 | 64 | /******************************************************************************/ 65 | /* Cortex Processor Interruption and Exception Handlers */ 66 | /******************************************************************************/ 67 | /** 68 | * @brief This function handles Non maskable interrupt. 69 | */ 70 | void NMI_Handler(void) 71 | { 72 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 73 | 74 | /* USER CODE END NonMaskableInt_IRQn 0 */ 75 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 76 | 77 | /* USER CODE END NonMaskableInt_IRQn 1 */ 78 | } 79 | 80 | /** 81 | * @brief This function handles Hard fault interrupt. 82 | */ 83 | void HardFault_Handler(void) 84 | { 85 | /* USER CODE BEGIN HardFault_IRQn 0 */ 86 | 87 | /* USER CODE END HardFault_IRQn 0 */ 88 | while (1) 89 | { 90 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 91 | /* USER CODE END W1_HardFault_IRQn 0 */ 92 | } 93 | } 94 | 95 | /** 96 | * @brief This function handles Memory management fault. 97 | */ 98 | void MemManage_Handler(void) 99 | { 100 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */ 101 | 102 | /* USER CODE END MemoryManagement_IRQn 0 */ 103 | while (1) 104 | { 105 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ 106 | /* USER CODE END W1_MemoryManagement_IRQn 0 */ 107 | } 108 | } 109 | 110 | /** 111 | * @brief This function handles Pre-fetch fault, memory access fault. 112 | */ 113 | void BusFault_Handler(void) 114 | { 115 | /* USER CODE BEGIN BusFault_IRQn 0 */ 116 | 117 | /* USER CODE END BusFault_IRQn 0 */ 118 | while (1) 119 | { 120 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */ 121 | /* USER CODE END W1_BusFault_IRQn 0 */ 122 | } 123 | } 124 | 125 | /** 126 | * @brief This function handles Undefined instruction or illegal state. 127 | */ 128 | void UsageFault_Handler(void) 129 | { 130 | /* USER CODE BEGIN UsageFault_IRQn 0 */ 131 | 132 | /* USER CODE END UsageFault_IRQn 0 */ 133 | while (1) 134 | { 135 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ 136 | /* USER CODE END W1_UsageFault_IRQn 0 */ 137 | } 138 | } 139 | 140 | /** 141 | * @brief This function handles System service call via SWI instruction. 142 | */ 143 | void SVC_Handler(void) 144 | { 145 | /* USER CODE BEGIN SVCall_IRQn 0 */ 146 | 147 | /* USER CODE END SVCall_IRQn 0 */ 148 | /* USER CODE BEGIN SVCall_IRQn 1 */ 149 | 150 | /* USER CODE END SVCall_IRQn 1 */ 151 | } 152 | 153 | /** 154 | * @brief This function handles Debug monitor. 155 | */ 156 | void DebugMon_Handler(void) 157 | { 158 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 159 | 160 | /* USER CODE END DebugMonitor_IRQn 0 */ 161 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 162 | 163 | /* USER CODE END DebugMonitor_IRQn 1 */ 164 | } 165 | 166 | /** 167 | * @brief This function handles Pendable request for system service. 168 | */ 169 | void PendSV_Handler(void) 170 | { 171 | /* USER CODE BEGIN PendSV_IRQn 0 */ 172 | 173 | /* USER CODE END PendSV_IRQn 0 */ 174 | /* USER CODE BEGIN PendSV_IRQn 1 */ 175 | 176 | /* USER CODE END PendSV_IRQn 1 */ 177 | } 178 | 179 | /** 180 | * @brief This function handles System tick timer. 181 | */ 182 | void SysTick_Handler(void) 183 | { 184 | /* USER CODE BEGIN SysTick_IRQn 0 */ 185 | 186 | /* USER CODE END SysTick_IRQn 0 */ 187 | HAL_IncTick(); 188 | /* USER CODE BEGIN SysTick_IRQn 1 */ 189 | 190 | /* USER CODE END SysTick_IRQn 1 */ 191 | } 192 | 193 | /******************************************************************************/ 194 | /* STM32H7xx Peripheral Interrupt Handlers */ 195 | /* Add here the Interrupt Handlers for the used peripherals. */ 196 | /* For the available peripheral interrupt handler names, */ 197 | /* please refer to the startup file (startup_stm32h7xx.s). */ 198 | /******************************************************************************/ 199 | 200 | /** 201 | * @brief This function handles HSEM2 global interrupt. 202 | */ 203 | void HSEM2_IRQHandler(void) 204 | { 205 | /* USER CODE BEGIN HSEM2_IRQn 0 */ 206 | 207 | /* USER CODE END HSEM2_IRQn 0 */ 208 | HAL_HSEM_IRQHandler(); 209 | /* USER CODE BEGIN HSEM2_IRQn 1 */ 210 | 211 | /* USER CODE END HSEM2_IRQn 1 */ 212 | } 213 | 214 | /* USER CODE BEGIN 1 */ 215 | 216 | /* USER CODE END 1 */ 217 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 218 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM4/Core/Src/syscalls.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file syscalls.c 4 | * @author Auto-generated by STM32CubeIDE 5 | * @brief STM32CubeIDE Minimal System calls file 6 | * 7 | * For more information about which c-functions 8 | * need which of these lowlevel functions 9 | * please consult the Newlib libc-manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | *

© Copyright (c) 2020 STMicroelectronics. 14 | * All rights reserved.

15 | * 16 | * This software component is licensed by ST under BSD 3-Clause license, 17 | * the "License"; You may not use this file except in compliance with the 18 | * License. You may obtain a copy of the License at: 19 | * opensource.org/licenses/BSD-3-Clause 20 | * 21 | ****************************************************************************** 22 | */ 23 | 24 | /* Includes */ 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | #include 32 | #include 33 | 34 | 35 | /* Variables */ 36 | //#undef errno 37 | extern int errno; 38 | extern int __io_putchar(int ch) __attribute__((weak)); 39 | extern int __io_getchar(void) __attribute__((weak)); 40 | 41 | register char * stack_ptr asm("sp"); 42 | 43 | char *__env[1] = { 0 }; 44 | char **environ = __env; 45 | 46 | 47 | /* Functions */ 48 | void initialise_monitor_handles() 49 | { 50 | } 51 | 52 | int _getpid(void) 53 | { 54 | return 1; 55 | } 56 | 57 | int _kill(int pid, int sig) 58 | { 59 | errno = EINVAL; 60 | return -1; 61 | } 62 | 63 | void _exit (int status) 64 | { 65 | _kill(status, -1); 66 | while (1) {} /* Make sure we hang here */ 67 | } 68 | 69 | __attribute__((weak)) int _read(int file, char *ptr, int len) 70 | { 71 | int DataIdx; 72 | 73 | for (DataIdx = 0; DataIdx < len; DataIdx++) 74 | { 75 | *ptr++ = __io_getchar(); 76 | } 77 | 78 | return len; 79 | } 80 | 81 | __attribute__((weak)) int _write(int file, char *ptr, int len) 82 | { 83 | int DataIdx; 84 | 85 | for (DataIdx = 0; DataIdx < len; DataIdx++) 86 | { 87 | __io_putchar(*ptr++); 88 | } 89 | return len; 90 | } 91 | 92 | int _close(int file) 93 | { 94 | return -1; 95 | } 96 | 97 | 98 | int _fstat(int file, struct stat *st) 99 | { 100 | st->st_mode = S_IFCHR; 101 | return 0; 102 | } 103 | 104 | int _isatty(int file) 105 | { 106 | return 1; 107 | } 108 | 109 | int _lseek(int file, int ptr, int dir) 110 | { 111 | return 0; 112 | } 113 | 114 | int _open(char *path, int flags, ...) 115 | { 116 | /* Pretend like we always fail */ 117 | return -1; 118 | } 119 | 120 | int _wait(int *status) 121 | { 122 | errno = ECHILD; 123 | return -1; 124 | } 125 | 126 | int _unlink(char *name) 127 | { 128 | errno = ENOENT; 129 | return -1; 130 | } 131 | 132 | int _times(struct tms *buf) 133 | { 134 | return -1; 135 | } 136 | 137 | int _stat(char *file, struct stat *st) 138 | { 139 | st->st_mode = S_IFCHR; 140 | return 0; 141 | } 142 | 143 | int _link(char *old, char *new) 144 | { 145 | errno = EMLINK; 146 | return -1; 147 | } 148 | 149 | int _fork(void) 150 | { 151 | errno = EAGAIN; 152 | return -1; 153 | } 154 | 155 | int _execve(char *name, char **argv, char **env) 156 | { 157 | errno = ENOMEM; 158 | return -1; 159 | } 160 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM4/Core/Src/sysmem.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file sysmem.c 4 | * @author Auto-generated by STM32CubeIDE 5 | * @brief STM32CubeIDE Minimal System Memory calls file 6 | * 7 | * For more information about which c-functions 8 | * need which of these lowlevel functions 9 | * please consult the Newlib libc-manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | *

© Copyright (c) 2020 STMicroelectronics. 14 | * All rights reserved.

15 | * 16 | * This software component is licensed by ST under BSD 3-Clause license, 17 | * the "License"; You may not use this file except in compliance with the 18 | * License. You may obtain a copy of the License at: 19 | * opensource.org/licenses/BSD-3-Clause 20 | * 21 | ****************************************************************************** 22 | */ 23 | 24 | /* Includes */ 25 | #include 26 | #include 27 | 28 | /* Variables */ 29 | extern int errno; 30 | register char * stack_ptr asm("sp"); 31 | 32 | /* Functions */ 33 | 34 | /** 35 | _sbrk 36 | Increase program data space. Malloc and related functions depend on this 37 | **/ 38 | caddr_t _sbrk(int incr) 39 | { 40 | extern char end asm("end"); 41 | static char *heap_end; 42 | char *prev_heap_end; 43 | 44 | if (heap_end == 0) 45 | heap_end = &end; 46 | 47 | prev_heap_end = heap_end; 48 | if (heap_end + incr > stack_ptr) 49 | { 50 | errno = ENOMEM; 51 | return (caddr_t) -1; 52 | } 53 | 54 | heap_end += incr; 55 | 56 | return (caddr_t) prev_heap_end; 57 | } 58 | 59 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM4/STM32H745ZITX_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | 5 | ** File : LinkerScript.ld 6 | ** 7 | ** 8 | ** Abstract : Linker script for STM32H7 series 9 | ** 1024Kbytes FLASH and 288Kbytes RAM 10 | ** 11 | ** Set heap size, stack size and stack location according 12 | ** to application requirements. 13 | ** 14 | ** Set memory bank area and size if external memory is used. 15 | ** 16 | ** Target : STMicroelectronics STM32 17 | ** 18 | ** Distribution: The file is distributed as is, without any warranty 19 | ** of any kind. 20 | ** 21 | ***************************************************************************** 22 | ** @attention 23 | ** 24 | ** Copyright (c) 2019 STMicroelectronics. 25 | ** All rights reserved. 26 | ** 27 | ** This software component is licensed by ST under BSD 3-Clause license, 28 | ** the "License"; You may not use this file except in compliance with the 29 | ** License. You may obtain a copy of the License at: 30 | ** opensource.org/licenses/BSD-3-Clause 31 | ** 32 | **************************************************************************** 33 | */ 34 | 35 | /* Entry Point */ 36 | ENTRY(Reset_Handler) 37 | 38 | /* Highest address of the user mode stack */ 39 | _estack = 0x10048000; /* end of RAM */ 40 | /* Generate a link error if heap and stack don't fit into RAM */ 41 | _Min_Heap_Size = 0x200 ; /* required amount of heap */ 42 | _Min_Stack_Size = 0x400 ; /* required amount of stack */ 43 | 44 | /* Specify the memory areas */ 45 | MEMORY 46 | { 47 | FLASH (rx) : ORIGIN = 0x08100000, LENGTH = 1024K 48 | RAM (xrw) : ORIGIN = 0x10000000, LENGTH = 288K 49 | } 50 | 51 | /* Define output sections */ 52 | SECTIONS 53 | { 54 | /* The startup code goes first into FLASH */ 55 | .isr_vector : 56 | { 57 | . = ALIGN(4); 58 | KEEP(*(.isr_vector)) /* Startup code */ 59 | . = ALIGN(4); 60 | } >FLASH 61 | 62 | /* The program code and other data goes into FLASH */ 63 | .text : 64 | { 65 | . = ALIGN(4); 66 | *(.text) /* .text sections (code) */ 67 | *(.text*) /* .text* sections (code) */ 68 | *(.glue_7) /* glue arm to thumb code */ 69 | *(.glue_7t) /* glue thumb to arm code */ 70 | *(.eh_frame) 71 | 72 | KEEP (*(.init)) 73 | KEEP (*(.fini)) 74 | 75 | . = ALIGN(4); 76 | _etext = .; /* define a global symbols at end of code */ 77 | } >FLASH 78 | 79 | /* Constant data goes into FLASH */ 80 | .rodata : 81 | { 82 | . = ALIGN(4); 83 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 84 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 85 | . = ALIGN(4); 86 | } >FLASH 87 | 88 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH 89 | .ARM : { 90 | __exidx_start = .; 91 | *(.ARM.exidx*) 92 | __exidx_end = .; 93 | } >FLASH 94 | 95 | .preinit_array : 96 | { 97 | PROVIDE_HIDDEN (__preinit_array_start = .); 98 | KEEP (*(.preinit_array*)) 99 | PROVIDE_HIDDEN (__preinit_array_end = .); 100 | } >FLASH 101 | .init_array : 102 | { 103 | PROVIDE_HIDDEN (__init_array_start = .); 104 | KEEP (*(SORT(.init_array.*))) 105 | KEEP (*(.init_array*)) 106 | PROVIDE_HIDDEN (__init_array_end = .); 107 | } >FLASH 108 | .fini_array : 109 | { 110 | PROVIDE_HIDDEN (__fini_array_start = .); 111 | KEEP (*(SORT(.fini_array.*))) 112 | KEEP (*(.fini_array*)) 113 | PROVIDE_HIDDEN (__fini_array_end = .); 114 | } >FLASH 115 | 116 | /* used by the startup to initialize data */ 117 | _sidata = LOADADDR(.data); 118 | 119 | /* Initialized data sections goes into RAM, load LMA copy after code */ 120 | .data : 121 | { 122 | . = ALIGN(4); 123 | _sdata = .; /* create a global symbol at data start */ 124 | *(.data) /* .data sections */ 125 | *(.data*) /* .data* sections */ 126 | 127 | . = ALIGN(4); 128 | _edata = .; /* define a global symbol at data end */ 129 | } >RAM AT> FLASH 130 | 131 | 132 | /* Uninitialized data section */ 133 | . = ALIGN(4); 134 | .bss : 135 | { 136 | /* This is used by the startup in order to initialize the .bss secion */ 137 | _sbss = .; /* define a global symbol at bss start */ 138 | __bss_start__ = _sbss; 139 | *(.bss) 140 | *(.bss*) 141 | *(COMMON) 142 | 143 | . = ALIGN(4); 144 | _ebss = .; /* define a global symbol at bss end */ 145 | __bss_end__ = _ebss; 146 | } >RAM 147 | 148 | /* User_heap_stack section, used to check that there is enough RAM left */ 149 | ._user_heap_stack : 150 | { 151 | . = ALIGN(8); 152 | PROVIDE ( end = . ); 153 | PROVIDE ( _end = . ); 154 | . = . + _Min_Heap_Size; 155 | . = . + _Min_Stack_Size; 156 | . = ALIGN(8); 157 | } >RAM 158 | 159 | 160 | 161 | /* Remove information from the standard libraries */ 162 | /DISCARD/ : 163 | { 164 | libc.a ( * ) 165 | libm.a ( * ) 166 | libgcc.a ( * ) 167 | } 168 | 169 | .ARM.attributes 0 : { *(.ARM.attributes) } 170 | } 171 | 172 | 173 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM4/STM32H745ZITX_RAM.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | 5 | ** File : LinkerScript.ld 6 | ** 7 | ** 8 | ** Abstract : Linker script for STM32H7 series 9 | ** 128Kbytes RAM_EXEC and 160Kbytes RAM 10 | ** 11 | ** Set heap size, stack size and stack location according 12 | ** to application requirements. 13 | ** 14 | ** Set memory bank area and size if external memory is used. 15 | ** 16 | ** Target : STMicroelectronics STM32 17 | ** 18 | ** Distribution: The file is distributed as is, without any warranty 19 | ** of any kind. 20 | ** 21 | ***************************************************************************** 22 | ** @attention 23 | ** 24 | ** Copyright (c) 2019 STMicroelectronics. 25 | ** All rights reserved. 26 | ** 27 | ** This software component is licensed by ST under BSD 3-Clause license, 28 | ** the "License"; You may not use this file except in compliance with the 29 | ** License. You may obtain a copy of the License at: 30 | ** opensource.org/licenses/BSD-3-Clause 31 | ** 32 | **************************************************************************** 33 | */ 34 | 35 | /* Entry Point */ 36 | ENTRY(Reset_Handler) 37 | 38 | /* Highest address of the user mode stack */ 39 | _estack = 0x10048000; /* end of RAM */ 40 | /* Generate a link error if heap and stack don't fit into RAM */ 41 | _Min_Heap_Size = 0x200 ; /* required amount of heap */ 42 | _Min_Stack_Size = 0x400 ; /* required amount of stack */ 43 | 44 | /* Specify the memory areas */ 45 | MEMORY 46 | { 47 | RAM_EXEC (rx) : ORIGIN = 0x10000000, LENGTH = 128K 48 | RAM (xrw) : ORIGIN = 0x10020000, LENGTH = 160K 49 | } 50 | 51 | /* Define output sections */ 52 | SECTIONS 53 | { 54 | /* The startup code goes first into RAM_EXEC */ 55 | .isr_vector : 56 | { 57 | . = ALIGN(4); 58 | KEEP(*(.isr_vector)) /* Startup code */ 59 | . = ALIGN(4); 60 | } >RAM_EXEC 61 | 62 | /* The program code and other data goes into RAM_EXEC */ 63 | .text : 64 | { 65 | . = ALIGN(4); 66 | *(.text) /* .text sections (code) */ 67 | *(.text*) /* .text* sections (code) */ 68 | *(.glue_7) /* glue arm to thumb code */ 69 | *(.glue_7t) /* glue thumb to arm code */ 70 | *(.eh_frame) 71 | 72 | KEEP (*(.init)) 73 | KEEP (*(.fini)) 74 | 75 | . = ALIGN(4); 76 | _etext = .; /* define a global symbols at end of code */ 77 | } >RAM_EXEC 78 | 79 | /* Constant data goes into RAM_EXEC */ 80 | .rodata : 81 | { 82 | . = ALIGN(4); 83 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 84 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 85 | . = ALIGN(4); 86 | } >RAM_EXEC 87 | 88 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_EXEC 89 | .ARM : { 90 | __exidx_start = .; 91 | *(.ARM.exidx*) 92 | __exidx_end = .; 93 | } >RAM_EXEC 94 | 95 | .preinit_array : 96 | { 97 | PROVIDE_HIDDEN (__preinit_array_start = .); 98 | KEEP (*(.preinit_array*)) 99 | PROVIDE_HIDDEN (__preinit_array_end = .); 100 | } >RAM_EXEC 101 | .init_array : 102 | { 103 | PROVIDE_HIDDEN (__init_array_start = .); 104 | KEEP (*(SORT(.init_array.*))) 105 | KEEP (*(.init_array*)) 106 | PROVIDE_HIDDEN (__init_array_end = .); 107 | } >RAM_EXEC 108 | .fini_array : 109 | { 110 | PROVIDE_HIDDEN (__fini_array_start = .); 111 | KEEP (*(SORT(.fini_array.*))) 112 | KEEP (*(.fini_array*)) 113 | PROVIDE_HIDDEN (__fini_array_end = .); 114 | } >RAM_EXEC 115 | 116 | /* used by the startup to initialize data */ 117 | _sidata = LOADADDR(.data); 118 | 119 | /* Initialized data sections goes into RAM, load LMA copy after code */ 120 | .data : 121 | { 122 | . = ALIGN(4); 123 | _sdata = .; /* create a global symbol at data start */ 124 | *(.data) /* .data sections */ 125 | *(.data*) /* .data* sections */ 126 | 127 | . = ALIGN(4); 128 | _edata = .; /* define a global symbol at data end */ 129 | } >RAM AT> RAM_EXEC 130 | 131 | 132 | /* Uninitialized data section */ 133 | . = ALIGN(4); 134 | .bss : 135 | { 136 | /* This is used by the startup in order to initialize the .bss secion */ 137 | _sbss = .; /* define a global symbol at bss start */ 138 | __bss_start__ = _sbss; 139 | *(.bss) 140 | *(.bss*) 141 | *(COMMON) 142 | 143 | . = ALIGN(4); 144 | _ebss = .; /* define a global symbol at bss end */ 145 | __bss_end__ = _ebss; 146 | } >RAM 147 | 148 | /* User_heap_stack section, used to check that there is enough RAM left */ 149 | ._user_heap_stack : 150 | { 151 | . = ALIGN(8); 152 | PROVIDE ( end = . ); 153 | PROVIDE ( _end = . ); 154 | . = . + _Min_Heap_Size; 155 | . = . + _Min_Stack_Size; 156 | . = ALIGN(8); 157 | } >RAM 158 | 159 | 160 | 161 | /* Remove information from the standard libraries */ 162 | /DISCARD/ : 163 | { 164 | libc.a ( * ) 165 | libm.a ( * ) 166 | libgcc.a ( * ) 167 | } 168 | 169 | .ARM.attributes 0 : { *(.ARM.attributes) } 170 | } 171 | 172 | 173 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM4/nucleo_stm32h745_q_aync_comm_CM4.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM7/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | nucleo_stm32h745_q_aync_comm_CM7 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | com.st.stm32cube.ide.mcu.MCUProjectNature 23 | org.eclipse.cdt.core.cnature 24 | com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature 25 | com.st.stm32cube.ide.mcu.MCUCubeProjectNature 26 | com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature 27 | com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature 28 | com.st.stm32cube.ide.mcu.MCUMultiCpuProjectNature 29 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 30 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 31 | 32 | 33 | 34 | Common 35 | 2 36 | $%7BPARENT-1-PROJECT_LOC%7D/Common 37 | 38 | 39 | Drivers 40 | 2 41 | $%7BPARENT-1-PROJECT_LOC%7D/Drivers 42 | 43 | 44 | Drivers/stm32h7xx_hal.c 45 | 1 46 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c 47 | 48 | 49 | Drivers/stm32h7xx_hal_cortex.c 50 | 1 51 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c 52 | 53 | 54 | Drivers/stm32h7xx_hal_dma.c 55 | 1 56 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c 57 | 58 | 59 | Drivers/stm32h7xx_hal_dma_ex.c 60 | 1 61 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c 62 | 63 | 64 | Drivers/stm32h7xx_hal_exti.c 65 | 1 66 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c 67 | 68 | 69 | Drivers/stm32h7xx_hal_flash.c 70 | 1 71 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c 72 | 73 | 74 | Drivers/stm32h7xx_hal_flash_ex.c 75 | 1 76 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c 77 | 78 | 79 | Drivers/stm32h7xx_hal_gpio.c 80 | 1 81 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c 82 | 83 | 84 | Drivers/stm32h7xx_hal_hsem.c 85 | 1 86 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c 87 | 88 | 89 | Drivers/stm32h7xx_hal_i2c.c 90 | 1 91 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c 92 | 93 | 94 | Drivers/stm32h7xx_hal_i2c_ex.c 95 | 1 96 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c 97 | 98 | 99 | Drivers/stm32h7xx_hal_mdma.c 100 | 1 101 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c 102 | 103 | 104 | Drivers/stm32h7xx_hal_pwr.c 105 | 1 106 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c 107 | 108 | 109 | Drivers/stm32h7xx_hal_pwr_ex.c 110 | 1 111 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c 112 | 113 | 114 | Drivers/stm32h7xx_hal_rcc.c 115 | 1 116 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c 117 | 118 | 119 | Drivers/stm32h7xx_hal_rcc_ex.c 120 | 1 121 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c 122 | 123 | 124 | Drivers/stm32h7xx_hal_tim.c 125 | 1 126 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c 127 | 128 | 129 | Drivers/stm32h7xx_hal_tim_ex.c 130 | 1 131 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c 132 | 133 | 134 | Drivers/stm32h7xx_hal_uart.c 135 | 1 136 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c 137 | 138 | 139 | Drivers/stm32h7xx_hal_uart_ex.c 140 | 1 141 | PARENT-3-PROJECT_LOC/drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c 142 | 143 | 144 | Core/Src/ringbuff.c 145 | 1 146 | PARENT-3-PROJECT_LOC/middlewares/ringbuff/src/ringbuff/ringbuff.c 147 | 148 | 149 | 150 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM7/Core/Inc/main.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.h 5 | * @brief : Header for main.c file. 6 | * This file contains the common defines of the application. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2020 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | /* USER CODE END Header */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __MAIN_H 24 | #define __MAIN_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32h7xx_hal.h" 32 | 33 | /* Private includes ----------------------------------------------------------*/ 34 | /* USER CODE BEGIN Includes */ 35 | 36 | /* USER CODE END Includes */ 37 | 38 | /* Exported types ------------------------------------------------------------*/ 39 | /* USER CODE BEGIN ET */ 40 | 41 | /* USER CODE END ET */ 42 | 43 | /* Exported constants --------------------------------------------------------*/ 44 | /* USER CODE BEGIN EC */ 45 | 46 | /* USER CODE END EC */ 47 | 48 | /* Exported macro ------------------------------------------------------------*/ 49 | /* USER CODE BEGIN EM */ 50 | 51 | /* USER CODE END EM */ 52 | 53 | /* Exported functions prototypes ---------------------------------------------*/ 54 | void Error_Handler(void); 55 | 56 | /* USER CODE BEGIN EFP */ 57 | 58 | /* USER CODE END EFP */ 59 | 60 | /* Private defines -----------------------------------------------------------*/ 61 | /* USER CODE BEGIN Private defines */ 62 | 63 | /* USER CODE END Private defines */ 64 | 65 | #ifdef __cplusplus 66 | } 67 | #endif 68 | 69 | #endif /* __MAIN_H */ 70 | 71 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 72 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM7/Core/Inc/stm32h7xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32h7xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2020 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32H7xx_IT_H 23 | #define __STM32H7xx_IT_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Private includes ----------------------------------------------------------*/ 30 | /* USER CODE BEGIN Includes */ 31 | 32 | /* USER CODE END Includes */ 33 | 34 | /* Exported types ------------------------------------------------------------*/ 35 | /* USER CODE BEGIN ET */ 36 | 37 | /* USER CODE END ET */ 38 | 39 | /* Exported constants --------------------------------------------------------*/ 40 | /* USER CODE BEGIN EC */ 41 | 42 | /* USER CODE END EC */ 43 | 44 | /* Exported macro ------------------------------------------------------------*/ 45 | /* USER CODE BEGIN EM */ 46 | 47 | /* USER CODE END EM */ 48 | 49 | /* Exported functions prototypes ---------------------------------------------*/ 50 | void NMI_Handler(void); 51 | void HardFault_Handler(void); 52 | void MemManage_Handler(void); 53 | void BusFault_Handler(void); 54 | void UsageFault_Handler(void); 55 | void SVC_Handler(void); 56 | void DebugMon_Handler(void); 57 | void PendSV_Handler(void); 58 | void SysTick_Handler(void); 59 | void HSEM1_IRQHandler(void); 60 | /* USER CODE BEGIN EFP */ 61 | 62 | /* USER CODE END EFP */ 63 | 64 | #ifdef __cplusplus 65 | } 66 | #endif 67 | 68 | #endif /* __STM32H7xx_IT_H */ 69 | 70 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 71 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM7/Core/Src/main.c: -------------------------------------------------------------------------------- 1 | /** 2 | * \file main.c 3 | * 4 | * Cortex-M7 main.c file 5 | */ 6 | 7 | /* Includes ------------------------------------------------------------------*/ 8 | #include "main.h" 9 | #include "common.h" 10 | 11 | /* Private variables ---------------------------------------------------------*/ 12 | UART_HandleTypeDef huart3; 13 | 14 | /* Ringbuffer variables */ 15 | volatile ringbuff_t* rb_cm4_to_cm7 = (void *)BUFF_CM4_TO_CM7_ADDR; 16 | volatile ringbuff_t* rb_cm7_to_cm4 = (void *)BUFF_CM7_TO_CM4_ADDR; 17 | 18 | /* Private function prototypes -----------------------------------------------*/ 19 | void SystemClock_Config(void); 20 | static void MX_GPIO_Init(void); 21 | static void MX_USART3_UART_Init(void); 22 | static void led_init(void); 23 | 24 | /** 25 | * \brief The application entry point 26 | */ 27 | int 28 | main(void) { 29 | uint32_t time, t1; 30 | 31 | /* 32 | * To be independent on CM4 boot option bytes config, 33 | * application will force second core to start by setting its relevant bit in RCC registers. 34 | * 35 | * Application for second core will immediately enter to STOP mode. 36 | * This is done in CPU2 main.c file 37 | * 38 | * 1. Start CPU2 core 39 | * 2. Wait for CPU2 to enter low-power mode 40 | */ 41 | HAL_RCCEx_EnableBootCore(RCC_BOOT_C2); 42 | WAIT_COND_WITH_TIMEOUT(__HAL_RCC_GET_FLAG(RCC_FLAG_D2CKRDY) != RESET, 0xFFFF); 43 | 44 | /* MCU Configuration--------------------------------------------------------*/ 45 | 46 | /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 47 | HAL_Init(); 48 | 49 | /* Configure the system clock */ 50 | SystemClock_Config(); 51 | 52 | /* Initialize buffers that are used as shared memory */ 53 | ringbuff_init(rb_cm7_to_cm4, (void *)BUFFDATA_CM7_TO_CM4_ADDR, BUFFDATA_CM7_TO_CM4_LEN); 54 | ringbuff_init(rb_cm4_to_cm7, (void *)BUFFDATA_CM4_TO_CM7_ADDR, BUFFDATA_CM4_TO_CM7_LEN); 55 | 56 | /* Wakeup CPU2 */ 57 | __HAL_RCC_HSEM_CLK_ENABLE(); 58 | HSEM_TAKE_RELEASE(HSEM_WAKEUP_CPU2); 59 | WAIT_COND_WITH_TIMEOUT(__HAL_RCC_GET_FLAG(RCC_FLAG_D2CKRDY) == RESET, 0xFFFF); 60 | 61 | /* 62 | * Initialize other things, not being important for second core 63 | * 64 | * It is important to wakeup D2 domain before accessing any 65 | * peripherals that are linked there, otherwise clock is disabled 66 | * and any attempt will result to undefined write/read 67 | */ 68 | 69 | /* Init LED1 */ 70 | led_init(); 71 | 72 | /* Initialize all configured peripherals */ 73 | MX_GPIO_Init(); 74 | MX_USART3_UART_Init(); 75 | 76 | /* Send test message */ 77 | HAL_UART_Transmit(&huart3, (void *)"[CM7] Core ready\r\n", 18, 100); 78 | 79 | /* Set default time */ 80 | time = t1 = HAL_GetTick(); 81 | while (1) { 82 | size_t len; 83 | void* addr; 84 | 85 | time = HAL_GetTick(); 86 | 87 | /* Check if CPU2 sent some data to CPU1 core */ 88 | while ((len = ringbuff_get_linear_block_read_length(rb_cm4_to_cm7)) > 0) { 89 | addr = ringbuff_get_linear_block_read_address(rb_cm4_to_cm7); 90 | 91 | /* Transmit data */ 92 | HAL_UART_Transmit(&huart3, addr, len, 1000); 93 | 94 | /* Mark buffer as read */ 95 | ringbuff_skip(rb_cm4_to_cm7, len); 96 | } 97 | 98 | /* Toggle LED */ 99 | if (time - t1 >= 500) { 100 | t1 = time; 101 | HAL_GPIO_TogglePin(LD1_GPIO_PORT, LD1_GPIO_PIN); 102 | } 103 | 104 | /* 105 | * If CPU1 wants to send data to CPU2, 106 | * it uses second buffer pipe, rb_cm7_to_cm4 107 | * is written by CPU1 and read by CPU2. 108 | */ 109 | //ringbuff_write(rb_cm7_to_cm4, "my_data", 7); 110 | } 111 | } 112 | 113 | /** 114 | * \brief Initialize LEDs controlled by core 115 | */ 116 | void 117 | led_init(void) { 118 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 119 | 120 | LD1_GPIO_CLK_EN(); 121 | 122 | GPIO_InitStruct.Pin = LD1_GPIO_PIN; 123 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 124 | GPIO_InitStruct.Pull = GPIO_NOPULL; 125 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 126 | HAL_GPIO_Init(LD1_GPIO_PORT, &GPIO_InitStruct); 127 | } 128 | 129 | /** 130 | * \brief System Clock Configuration 131 | */ 132 | void 133 | SystemClock_Config(void) { 134 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 135 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 136 | RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 137 | 138 | /* Supply configuration update enable */ 139 | HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY); 140 | 141 | /* Configure the main internal regulator output voltage */ 142 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 143 | while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 144 | 145 | /** Initializes the CPU, AHB and APB busses clocks */ 146 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 147 | RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; 148 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 149 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 150 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { 151 | Error_Handler(); 152 | } 153 | 154 | /* Initializes the CPU, AHB and APB busses clocks */ 155 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK 156 | | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 157 | | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1; 158 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 159 | RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 160 | RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; 161 | RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1; 162 | RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; 163 | RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; 164 | RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; 165 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) { 166 | Error_Handler(); 167 | } 168 | 169 | PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3; 170 | PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 171 | if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { 172 | Error_Handler(); 173 | } 174 | } 175 | 176 | /** 177 | * \brief USART3 Initialization Function 178 | */ 179 | static void 180 | MX_USART3_UART_Init(void) { 181 | huart3.Instance = USART3; 182 | huart3.Init.BaudRate = 115200; 183 | huart3.Init.WordLength = UART_WORDLENGTH_8B; 184 | huart3.Init.StopBits = UART_STOPBITS_1; 185 | huart3.Init.Parity = UART_PARITY_NONE; 186 | huart3.Init.Mode = UART_MODE_TX_RX; 187 | huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 188 | huart3.Init.OverSampling = UART_OVERSAMPLING_16; 189 | huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 190 | huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1; 191 | huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 192 | if (HAL_UART_Init(&huart3) != HAL_OK) { 193 | Error_Handler(); 194 | } 195 | if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) { 196 | Error_Handler(); 197 | } 198 | if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) { 199 | Error_Handler(); 200 | } 201 | if (HAL_UARTEx_DisableFifoMode(&huart3) != HAL_OK) { 202 | Error_Handler(); 203 | } 204 | } 205 | 206 | /** 207 | * \brief GPIO Initialization function 208 | */ 209 | static void 210 | MX_GPIO_Init(void) { 211 | /* GPIO Ports Clock Enable */ 212 | __HAL_RCC_GPIOD_CLK_ENABLE(); 213 | } 214 | 215 | /** 216 | * @brief This function is executed in case of error occurrence 217 | */ 218 | void 219 | Error_Handler(void) { 220 | while (1) {} 221 | } 222 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM7/Core/Src/stm32h7xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * File Name : stm32h7xx_hal_msp.c 5 | * Description : This file provides code for the MSP Initialization 6 | * and de-Initialization codes. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2020 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | /* USER CODE END Header */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "main.h" 24 | /* USER CODE BEGIN Includes */ 25 | 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN TD */ 30 | 31 | /* USER CODE END TD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN Define */ 35 | 36 | /* USER CODE END Define */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN Macro */ 40 | 41 | /* USER CODE END Macro */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* USER CODE BEGIN PV */ 45 | 46 | /* USER CODE END PV */ 47 | 48 | /* Private function prototypes -----------------------------------------------*/ 49 | /* USER CODE BEGIN PFP */ 50 | 51 | /* USER CODE END PFP */ 52 | 53 | /* External functions --------------------------------------------------------*/ 54 | /* USER CODE BEGIN ExternalFunctions */ 55 | 56 | /* USER CODE END ExternalFunctions */ 57 | 58 | /* USER CODE BEGIN 0 */ 59 | 60 | /* USER CODE END 0 */ 61 | /** 62 | * Initializes the Global MSP. 63 | */ 64 | void HAL_MspInit(void) 65 | { 66 | /* USER CODE BEGIN MspInit 0 */ 67 | 68 | /* USER CODE END MspInit 0 */ 69 | 70 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 71 | 72 | /* System interrupt init*/ 73 | 74 | /* Peripheral interrupt init */ 75 | /* HSEM1_IRQn interrupt configuration */ 76 | HAL_NVIC_SetPriority(HSEM1_IRQn, 0, 0); 77 | HAL_NVIC_EnableIRQ(HSEM1_IRQn); 78 | 79 | /* USER CODE BEGIN MspInit 1 */ 80 | 81 | /* USER CODE END MspInit 1 */ 82 | } 83 | 84 | /** 85 | * @brief UART MSP Initialization 86 | * This function configures the hardware resources used in this example 87 | * @param huart: UART handle pointer 88 | * @retval None 89 | */ 90 | void HAL_UART_MspInit(UART_HandleTypeDef* huart) 91 | { 92 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 93 | if(huart->Instance==USART3) 94 | { 95 | /* USER CODE BEGIN USART3_MspInit 0 */ 96 | 97 | /* USER CODE END USART3_MspInit 0 */ 98 | /* Peripheral clock enable */ 99 | __HAL_RCC_USART3_CLK_ENABLE(); 100 | 101 | __HAL_RCC_GPIOD_CLK_ENABLE(); 102 | /**USART3 GPIO Configuration 103 | PD8 ------> USART3_TX 104 | PD9 ------> USART3_RX 105 | */ 106 | GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 107 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 108 | GPIO_InitStruct.Pull = GPIO_NOPULL; 109 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 110 | GPIO_InitStruct.Alternate = GPIO_AF7_USART3; 111 | HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 112 | 113 | /* USER CODE BEGIN USART3_MspInit 1 */ 114 | 115 | /* USER CODE END USART3_MspInit 1 */ 116 | } 117 | 118 | } 119 | 120 | /** 121 | * @brief UART MSP De-Initialization 122 | * This function freeze the hardware resources used in this example 123 | * @param huart: UART handle pointer 124 | * @retval None 125 | */ 126 | void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) 127 | { 128 | if(huart->Instance==USART3) 129 | { 130 | /* USER CODE BEGIN USART3_MspDeInit 0 */ 131 | 132 | /* USER CODE END USART3_MspDeInit 0 */ 133 | /* Peripheral clock disable */ 134 | __HAL_RCC_USART3_CLK_DISABLE(); 135 | 136 | /**USART3 GPIO Configuration 137 | PD8 ------> USART3_TX 138 | PD9 ------> USART3_RX 139 | */ 140 | HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9); 141 | 142 | /* USER CODE BEGIN USART3_MspDeInit 1 */ 143 | 144 | /* USER CODE END USART3_MspDeInit 1 */ 145 | } 146 | 147 | } 148 | 149 | /* USER CODE BEGIN 1 */ 150 | 151 | /* USER CODE END 1 */ 152 | 153 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 154 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM7/Core/Src/stm32h7xx_it.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32h7xx_it.c 5 | * @brief Interrupt Service Routines. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2020 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "main.h" 23 | #include "stm32h7xx_it.h" 24 | /* Private includes ----------------------------------------------------------*/ 25 | /* USER CODE BEGIN Includes */ 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN TD */ 30 | 31 | /* USER CODE END TD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN PD */ 35 | 36 | /* USER CODE END PD */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN PM */ 40 | 41 | /* USER CODE END PM */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* USER CODE BEGIN PV */ 45 | 46 | /* USER CODE END PV */ 47 | 48 | /* Private function prototypes -----------------------------------------------*/ 49 | /* USER CODE BEGIN PFP */ 50 | 51 | /* USER CODE END PFP */ 52 | 53 | /* Private user code ---------------------------------------------------------*/ 54 | /* USER CODE BEGIN 0 */ 55 | 56 | /* USER CODE END 0 */ 57 | 58 | /* External variables --------------------------------------------------------*/ 59 | 60 | /* USER CODE BEGIN EV */ 61 | 62 | /* USER CODE END EV */ 63 | 64 | /******************************************************************************/ 65 | /* Cortex Processor Interruption and Exception Handlers */ 66 | /******************************************************************************/ 67 | /** 68 | * @brief This function handles Non maskable interrupt. 69 | */ 70 | void NMI_Handler(void) 71 | { 72 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 73 | 74 | /* USER CODE END NonMaskableInt_IRQn 0 */ 75 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 76 | 77 | /* USER CODE END NonMaskableInt_IRQn 1 */ 78 | } 79 | 80 | /** 81 | * @brief This function handles Hard fault interrupt. 82 | */ 83 | void HardFault_Handler(void) 84 | { 85 | /* USER CODE BEGIN HardFault_IRQn 0 */ 86 | 87 | /* USER CODE END HardFault_IRQn 0 */ 88 | while (1) 89 | { 90 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 91 | /* USER CODE END W1_HardFault_IRQn 0 */ 92 | } 93 | } 94 | 95 | /** 96 | * @brief This function handles Memory management fault. 97 | */ 98 | void MemManage_Handler(void) 99 | { 100 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */ 101 | 102 | /* USER CODE END MemoryManagement_IRQn 0 */ 103 | while (1) 104 | { 105 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ 106 | /* USER CODE END W1_MemoryManagement_IRQn 0 */ 107 | } 108 | } 109 | 110 | /** 111 | * @brief This function handles Pre-fetch fault, memory access fault. 112 | */ 113 | void BusFault_Handler(void) 114 | { 115 | /* USER CODE BEGIN BusFault_IRQn 0 */ 116 | 117 | /* USER CODE END BusFault_IRQn 0 */ 118 | while (1) 119 | { 120 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */ 121 | /* USER CODE END W1_BusFault_IRQn 0 */ 122 | } 123 | } 124 | 125 | /** 126 | * @brief This function handles Undefined instruction or illegal state. 127 | */ 128 | void UsageFault_Handler(void) 129 | { 130 | /* USER CODE BEGIN UsageFault_IRQn 0 */ 131 | 132 | /* USER CODE END UsageFault_IRQn 0 */ 133 | while (1) 134 | { 135 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ 136 | /* USER CODE END W1_UsageFault_IRQn 0 */ 137 | } 138 | } 139 | 140 | /** 141 | * @brief This function handles System service call via SWI instruction. 142 | */ 143 | void SVC_Handler(void) 144 | { 145 | /* USER CODE BEGIN SVCall_IRQn 0 */ 146 | 147 | /* USER CODE END SVCall_IRQn 0 */ 148 | /* USER CODE BEGIN SVCall_IRQn 1 */ 149 | 150 | /* USER CODE END SVCall_IRQn 1 */ 151 | } 152 | 153 | /** 154 | * @brief This function handles Debug monitor. 155 | */ 156 | void DebugMon_Handler(void) 157 | { 158 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 159 | 160 | /* USER CODE END DebugMonitor_IRQn 0 */ 161 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 162 | 163 | /* USER CODE END DebugMonitor_IRQn 1 */ 164 | } 165 | 166 | /** 167 | * @brief This function handles Pendable request for system service. 168 | */ 169 | void PendSV_Handler(void) 170 | { 171 | /* USER CODE BEGIN PendSV_IRQn 0 */ 172 | 173 | /* USER CODE END PendSV_IRQn 0 */ 174 | /* USER CODE BEGIN PendSV_IRQn 1 */ 175 | 176 | /* USER CODE END PendSV_IRQn 1 */ 177 | } 178 | 179 | /** 180 | * @brief This function handles System tick timer. 181 | */ 182 | void SysTick_Handler(void) 183 | { 184 | /* USER CODE BEGIN SysTick_IRQn 0 */ 185 | 186 | /* USER CODE END SysTick_IRQn 0 */ 187 | HAL_IncTick(); 188 | /* USER CODE BEGIN SysTick_IRQn 1 */ 189 | 190 | /* USER CODE END SysTick_IRQn 1 */ 191 | } 192 | 193 | /******************************************************************************/ 194 | /* STM32H7xx Peripheral Interrupt Handlers */ 195 | /* Add here the Interrupt Handlers for the used peripherals. */ 196 | /* For the available peripheral interrupt handler names, */ 197 | /* please refer to the startup file (startup_stm32h7xx.s). */ 198 | /******************************************************************************/ 199 | 200 | /** 201 | * @brief This function handles HSEM1 global interrupt. 202 | */ 203 | void HSEM1_IRQHandler(void) 204 | { 205 | /* USER CODE BEGIN HSEM1_IRQn 0 */ 206 | 207 | /* USER CODE END HSEM1_IRQn 0 */ 208 | HAL_HSEM_IRQHandler(); 209 | /* USER CODE BEGIN HSEM1_IRQn 1 */ 210 | 211 | /* USER CODE END HSEM1_IRQn 1 */ 212 | } 213 | 214 | /* USER CODE BEGIN 1 */ 215 | 216 | /* USER CODE END 1 */ 217 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 218 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM7/Core/Src/syscalls.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file syscalls.c 4 | * @author Auto-generated by STM32CubeIDE 5 | * @brief STM32CubeIDE Minimal System calls file 6 | * 7 | * For more information about which c-functions 8 | * need which of these lowlevel functions 9 | * please consult the Newlib libc-manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | *

© Copyright (c) 2020 STMicroelectronics. 14 | * All rights reserved.

15 | * 16 | * This software component is licensed by ST under BSD 3-Clause license, 17 | * the "License"; You may not use this file except in compliance with the 18 | * License. You may obtain a copy of the License at: 19 | * opensource.org/licenses/BSD-3-Clause 20 | * 21 | ****************************************************************************** 22 | */ 23 | 24 | /* Includes */ 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | #include 32 | #include 33 | 34 | 35 | /* Variables */ 36 | //#undef errno 37 | extern int errno; 38 | extern int __io_putchar(int ch) __attribute__((weak)); 39 | extern int __io_getchar(void) __attribute__((weak)); 40 | 41 | register char * stack_ptr asm("sp"); 42 | 43 | char *__env[1] = { 0 }; 44 | char **environ = __env; 45 | 46 | 47 | /* Functions */ 48 | void initialise_monitor_handles() 49 | { 50 | } 51 | 52 | int _getpid(void) 53 | { 54 | return 1; 55 | } 56 | 57 | int _kill(int pid, int sig) 58 | { 59 | errno = EINVAL; 60 | return -1; 61 | } 62 | 63 | void _exit (int status) 64 | { 65 | _kill(status, -1); 66 | while (1) {} /* Make sure we hang here */ 67 | } 68 | 69 | __attribute__((weak)) int _read(int file, char *ptr, int len) 70 | { 71 | int DataIdx; 72 | 73 | for (DataIdx = 0; DataIdx < len; DataIdx++) 74 | { 75 | *ptr++ = __io_getchar(); 76 | } 77 | 78 | return len; 79 | } 80 | 81 | __attribute__((weak)) int _write(int file, char *ptr, int len) 82 | { 83 | int DataIdx; 84 | 85 | for (DataIdx = 0; DataIdx < len; DataIdx++) 86 | { 87 | __io_putchar(*ptr++); 88 | } 89 | return len; 90 | } 91 | 92 | int _close(int file) 93 | { 94 | return -1; 95 | } 96 | 97 | 98 | int _fstat(int file, struct stat *st) 99 | { 100 | st->st_mode = S_IFCHR; 101 | return 0; 102 | } 103 | 104 | int _isatty(int file) 105 | { 106 | return 1; 107 | } 108 | 109 | int _lseek(int file, int ptr, int dir) 110 | { 111 | return 0; 112 | } 113 | 114 | int _open(char *path, int flags, ...) 115 | { 116 | /* Pretend like we always fail */ 117 | return -1; 118 | } 119 | 120 | int _wait(int *status) 121 | { 122 | errno = ECHILD; 123 | return -1; 124 | } 125 | 126 | int _unlink(char *name) 127 | { 128 | errno = ENOENT; 129 | return -1; 130 | } 131 | 132 | int _times(struct tms *buf) 133 | { 134 | return -1; 135 | } 136 | 137 | int _stat(char *file, struct stat *st) 138 | { 139 | st->st_mode = S_IFCHR; 140 | return 0; 141 | } 142 | 143 | int _link(char *old, char *new) 144 | { 145 | errno = EMLINK; 146 | return -1; 147 | } 148 | 149 | int _fork(void) 150 | { 151 | errno = EAGAIN; 152 | return -1; 153 | } 154 | 155 | int _execve(char *name, char **argv, char **env) 156 | { 157 | errno = ENOMEM; 158 | return -1; 159 | } 160 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM7/Core/Src/sysmem.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file sysmem.c 4 | * @author Auto-generated by STM32CubeIDE 5 | * @brief STM32CubeIDE Minimal System Memory calls file 6 | * 7 | * For more information about which c-functions 8 | * need which of these lowlevel functions 9 | * please consult the Newlib libc-manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | *

© Copyright (c) 2020 STMicroelectronics. 14 | * All rights reserved.

15 | * 16 | * This software component is licensed by ST under BSD 3-Clause license, 17 | * the "License"; You may not use this file except in compliance with the 18 | * License. You may obtain a copy of the License at: 19 | * opensource.org/licenses/BSD-3-Clause 20 | * 21 | ****************************************************************************** 22 | */ 23 | 24 | /* Includes */ 25 | #include 26 | #include 27 | 28 | /* Variables */ 29 | extern int errno; 30 | register char * stack_ptr asm("sp"); 31 | 32 | /* Functions */ 33 | 34 | /** 35 | _sbrk 36 | Increase program data space. Malloc and related functions depend on this 37 | **/ 38 | caddr_t _sbrk(int incr) 39 | { 40 | extern char end asm("end"); 41 | static char *heap_end; 42 | char *prev_heap_end; 43 | 44 | if (heap_end == 0) 45 | heap_end = &end; 46 | 47 | prev_heap_end = heap_end; 48 | if (heap_end + incr > stack_ptr) 49 | { 50 | errno = ENOMEM; 51 | return (caddr_t) -1; 52 | } 53 | 54 | heap_end += incr; 55 | 56 | return (caddr_t) prev_heap_end; 57 | } 58 | 59 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM7/STM32H745ZITX_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | 5 | ** File : LinkerScript.ld 6 | ** 7 | ** 8 | ** Abstract : Linker script for STM32H7 series 9 | ** 1024Kbytes FLASH and 192Kbytes RAM 10 | ** 11 | ** Set heap size, stack size and stack location according 12 | ** to application requirements. 13 | ** 14 | ** Set memory bank area and size if external memory is used. 15 | ** 16 | ** Target : STMicroelectronics STM32 17 | ** 18 | ** Distribution: The file is distributed as is, without any warranty 19 | ** of any kind. 20 | ** 21 | ***************************************************************************** 22 | ** @attention 23 | ** 24 | ** Copyright (c) 2019 STMicroelectronics. 25 | ** All rights reserved. 26 | ** 27 | ** This software component is licensed by ST under BSD 3-Clause license, 28 | ** the "License"; You may not use this file except in compliance with the 29 | ** License. You may obtain a copy of the License at: 30 | ** opensource.org/licenses/BSD-3-Clause 31 | ** 32 | **************************************************************************** 33 | */ 34 | 35 | /* Entry Point */ 36 | ENTRY(Reset_Handler) 37 | 38 | /* Highest address of the user mode stack */ 39 | _estack = 0x20020000; /* end of RAM */ 40 | /* Generate a link error if heap and stack don't fit into RAM */ 41 | _Min_Heap_Size = 0x200 ; /* required amount of heap */ 42 | _Min_Stack_Size = 0x400 ; /* required amount of stack */ 43 | 44 | /* Specify the memory areas */ 45 | MEMORY 46 | { 47 | FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K 48 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K 49 | ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K 50 | } 51 | 52 | /* Define output sections */ 53 | SECTIONS 54 | { 55 | /* The startup code goes first into FLASH */ 56 | .isr_vector : 57 | { 58 | . = ALIGN(4); 59 | KEEP(*(.isr_vector)) /* Startup code */ 60 | . = ALIGN(4); 61 | } >FLASH 62 | 63 | /* The program code and other data goes into FLASH */ 64 | .text : 65 | { 66 | . = ALIGN(4); 67 | *(.text) /* .text sections (code) */ 68 | *(.text*) /* .text* sections (code) */ 69 | *(.glue_7) /* glue arm to thumb code */ 70 | *(.glue_7t) /* glue thumb to arm code */ 71 | *(.eh_frame) 72 | 73 | KEEP (*(.init)) 74 | KEEP (*(.fini)) 75 | 76 | . = ALIGN(4); 77 | _etext = .; /* define a global symbols at end of code */ 78 | } >FLASH 79 | 80 | /* Constant data goes into FLASH */ 81 | .rodata : 82 | { 83 | . = ALIGN(4); 84 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 85 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 86 | . = ALIGN(4); 87 | } >FLASH 88 | 89 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH 90 | .ARM : { 91 | __exidx_start = .; 92 | *(.ARM.exidx*) 93 | __exidx_end = .; 94 | } >FLASH 95 | 96 | .preinit_array : 97 | { 98 | PROVIDE_HIDDEN (__preinit_array_start = .); 99 | KEEP (*(.preinit_array*)) 100 | PROVIDE_HIDDEN (__preinit_array_end = .); 101 | } >FLASH 102 | .init_array : 103 | { 104 | PROVIDE_HIDDEN (__init_array_start = .); 105 | KEEP (*(SORT(.init_array.*))) 106 | KEEP (*(.init_array*)) 107 | PROVIDE_HIDDEN (__init_array_end = .); 108 | } >FLASH 109 | .fini_array : 110 | { 111 | PROVIDE_HIDDEN (__fini_array_start = .); 112 | KEEP (*(SORT(.fini_array.*))) 113 | KEEP (*(.fini_array*)) 114 | PROVIDE_HIDDEN (__fini_array_end = .); 115 | } >FLASH 116 | 117 | /* used by the startup to initialize data */ 118 | _sidata = LOADADDR(.data); 119 | 120 | /* Initialized data sections goes into RAM, load LMA copy after code */ 121 | .data : 122 | { 123 | . = ALIGN(4); 124 | _sdata = .; /* create a global symbol at data start */ 125 | *(.data) /* .data sections */ 126 | *(.data*) /* .data* sections */ 127 | 128 | . = ALIGN(4); 129 | _edata = .; /* define a global symbol at data end */ 130 | } >RAM AT> FLASH 131 | 132 | 133 | /* Uninitialized data section */ 134 | . = ALIGN(4); 135 | .bss : 136 | { 137 | /* This is used by the startup in order to initialize the .bss secion */ 138 | _sbss = .; /* define a global symbol at bss start */ 139 | __bss_start__ = _sbss; 140 | *(.bss) 141 | *(.bss*) 142 | *(COMMON) 143 | 144 | . = ALIGN(4); 145 | _ebss = .; /* define a global symbol at bss end */ 146 | __bss_end__ = _ebss; 147 | } >RAM 148 | 149 | /* User_heap_stack section, used to check that there is enough RAM left */ 150 | ._user_heap_stack : 151 | { 152 | . = ALIGN(8); 153 | PROVIDE ( end = . ); 154 | PROVIDE ( _end = . ); 155 | . = . + _Min_Heap_Size; 156 | . = . + _Min_Stack_Size; 157 | . = ALIGN(8); 158 | } >RAM 159 | 160 | 161 | 162 | /* Remove information from the standard libraries */ 163 | /DISCARD/ : 164 | { 165 | libc.a ( * ) 166 | libm.a ( * ) 167 | libgcc.a ( * ) 168 | } 169 | 170 | .ARM.attributes 0 : { *(.ARM.attributes) } 171 | } 172 | 173 | 174 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM7/STM32H745ZITX_RAM.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | 5 | ** File : LinkerScript.ld 6 | ** 7 | ** 8 | ** Abstract : Linker script for STM32H7 series 9 | ** 256Kbytes RAM_EXEC and 256Kbytes RAM 10 | ** 11 | ** Set heap size, stack size and stack location according 12 | ** to application requirements. 13 | ** 14 | ** Set memory bank area and size if external memory is used. 15 | ** 16 | ** Target : STMicroelectronics STM32 17 | ** 18 | ** Distribution: The file is distributed as is, without any warranty 19 | ** of any kind. 20 | ** 21 | ***************************************************************************** 22 | ** @attention 23 | ** 24 | ** Copyright (c) 2019 STMicroelectronics. 25 | ** All rights reserved. 26 | ** 27 | ** This software component is licensed by ST under BSD 3-Clause license, 28 | ** the "License"; You may not use this file except in compliance with the 29 | ** License. You may obtain a copy of the License at: 30 | ** opensource.org/licenses/BSD-3-Clause 31 | ** 32 | **************************************************************************** 33 | */ 34 | 35 | /* Entry Point */ 36 | ENTRY(Reset_Handler) 37 | 38 | /* Highest address of the user mode stack */ 39 | _estack = 0x24080000; /* end of RAM */ 40 | /* Generate a link error if heap and stack don't fit into RAM */ 41 | _Min_Heap_Size = 0x200 ; /* required amount of heap */ 42 | _Min_Stack_Size = 0x400 ; /* required amount of stack */ 43 | 44 | /* Specify the memory areas */ 45 | MEMORY 46 | { 47 | RAM_EXEC (rx) : ORIGIN = 0x24000000, LENGTH = 256K 48 | RAM (xrw) : ORIGIN = 0x24040000, LENGTH = 256K 49 | } 50 | 51 | /* Define output sections */ 52 | SECTIONS 53 | { 54 | /* The startup code goes first into RAM_EXEC */ 55 | .isr_vector : 56 | { 57 | . = ALIGN(4); 58 | KEEP(*(.isr_vector)) /* Startup code */ 59 | . = ALIGN(4); 60 | } >RAM_EXEC 61 | 62 | /* The program code and other data goes into RAM_EXEC */ 63 | .text : 64 | { 65 | . = ALIGN(4); 66 | *(.text) /* .text sections (code) */ 67 | *(.text*) /* .text* sections (code) */ 68 | *(.glue_7) /* glue arm to thumb code */ 69 | *(.glue_7t) /* glue thumb to arm code */ 70 | *(.eh_frame) 71 | 72 | KEEP (*(.init)) 73 | KEEP (*(.fini)) 74 | 75 | . = ALIGN(4); 76 | _etext = .; /* define a global symbols at end of code */ 77 | } >RAM_EXEC 78 | 79 | /* Constant data goes into RAM_EXEC */ 80 | .rodata : 81 | { 82 | . = ALIGN(4); 83 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 84 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 85 | . = ALIGN(4); 86 | } >RAM_EXEC 87 | 88 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_EXEC 89 | .ARM : { 90 | __exidx_start = .; 91 | *(.ARM.exidx*) 92 | __exidx_end = .; 93 | } >RAM_EXEC 94 | 95 | .preinit_array : 96 | { 97 | PROVIDE_HIDDEN (__preinit_array_start = .); 98 | KEEP (*(.preinit_array*)) 99 | PROVIDE_HIDDEN (__preinit_array_end = .); 100 | } >RAM_EXEC 101 | .init_array : 102 | { 103 | PROVIDE_HIDDEN (__init_array_start = .); 104 | KEEP (*(SORT(.init_array.*))) 105 | KEEP (*(.init_array*)) 106 | PROVIDE_HIDDEN (__init_array_end = .); 107 | } >RAM_EXEC 108 | .fini_array : 109 | { 110 | PROVIDE_HIDDEN (__fini_array_start = .); 111 | KEEP (*(SORT(.fini_array.*))) 112 | KEEP (*(.fini_array*)) 113 | PROVIDE_HIDDEN (__fini_array_end = .); 114 | } >RAM_EXEC 115 | 116 | /* used by the startup to initialize data */ 117 | _sidata = LOADADDR(.data); 118 | 119 | /* Initialized data sections goes into RAM, load LMA copy after code */ 120 | .data : 121 | { 122 | . = ALIGN(4); 123 | _sdata = .; /* create a global symbol at data start */ 124 | *(.data) /* .data sections */ 125 | *(.data*) /* .data* sections */ 126 | 127 | . = ALIGN(4); 128 | _edata = .; /* define a global symbol at data end */ 129 | } >RAM AT> RAM_EXEC 130 | 131 | 132 | /* Uninitialized data section */ 133 | . = ALIGN(4); 134 | .bss : 135 | { 136 | /* This is used by the startup in order to initialize the .bss secion */ 137 | _sbss = .; /* define a global symbol at bss start */ 138 | __bss_start__ = _sbss; 139 | *(.bss) 140 | *(.bss*) 141 | *(COMMON) 142 | 143 | . = ALIGN(4); 144 | _ebss = .; /* define a global symbol at bss end */ 145 | __bss_end__ = _ebss; 146 | } >RAM 147 | 148 | /* User_heap_stack section, used to check that there is enough RAM left */ 149 | ._user_heap_stack : 150 | { 151 | . = ALIGN(8); 152 | PROVIDE ( end = . ); 153 | PROVIDE ( _end = . ); 154 | . = . + _Min_Heap_Size; 155 | . = . + _Min_Stack_Size; 156 | . = ALIGN(8); 157 | } >RAM 158 | 159 | 160 | 161 | /* Remove information from the standard libraries */ 162 | /DISCARD/ : 163 | { 164 | libc.a ( * ) 165 | libm.a ( * ) 166 | libgcc.a ( * ) 167 | } 168 | 169 | .ARM.attributes 0 : { *(.ARM.attributes) } 170 | } 171 | 172 | 173 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/CM7/nucleo_stm32h745_q_aync_comm_CM7.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/Common/Inc/common.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file common.h 3 | * \brief Common configuration for both cores 4 | */ 5 | 6 | /* 7 | * Copyright (c) 2020 Tilen MAJERLE 8 | * 9 | * Permission is hereby granted, free of charge, to any person 10 | * obtaining a copy of this software and associated documentation 11 | * files (the "Software"), to deal in the Software without restriction, 12 | * including without limitation the rights to use, copy, modify, merge, 13 | * publish, distribute, sublicense, and/or sell copies of the Software, 14 | * and to permit persons to whom the Software is furnished to do so, 15 | * subject to the following conditions: 16 | * 17 | * The above copyright notice and this permission notice shall be 18 | * included in all copies or substantial portions of the Software. 19 | * 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 22 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 23 | * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 24 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 25 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 26 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 27 | * OTHER DEALINGS IN THE SOFTWARE. 28 | * 29 | * Author: Tilen MAJERLE 30 | */ 31 | #ifndef COMMON_HDR_H 32 | #define COMMON_HDR_H 33 | 34 | #include "stm32h7xx.h" 35 | #include "ringbuff/ringbuff.h" 36 | 37 | /* Align X to 4 bytes */ 38 | #define MEM_ALIGN(x) (((x) + 0x00000003) & ~0x00000003) 39 | 40 | /* Shared RAM between 2 cores is SRAM4 in D3 domain */ 41 | #define SHD_RAM_START_ADDR 0x38000000 42 | #define SHD_RAM_LEN 0x0000FFFF 43 | 44 | /* Buffer from CM4 to CM7 */ 45 | #define BUFF_CM4_TO_CM7_ADDR MEM_ALIGN(SHD_RAM_START_ADDR) 46 | #define BUFF_CM4_TO_CM7_LEN MEM_ALIGN(sizeof(ringbuff_t)) 47 | #define BUFFDATA_CM4_TO_CM7_ADDR MEM_ALIGN(BUFF_CM4_TO_CM7_ADDR + BUFF_CM4_TO_CM7_LEN) 48 | #define BUFFDATA_CM4_TO_CM7_LEN MEM_ALIGN(0x00000400) 49 | 50 | /* Buffer from CM7 to CM4 */ 51 | #define BUFF_CM7_TO_CM4_ADDR MEM_ALIGN(BUFFDATA_CM4_TO_CM7_ADDR + BUFFDATA_CM4_TO_CM7_LEN) 52 | #define BUFF_CM7_TO_CM4_LEN MEM_ALIGN(sizeof(ringbuff_t)) 53 | #define BUFFDATA_CM7_TO_CM4_ADDR MEM_ALIGN(BUFF_CM7_TO_CM4_ADDR + BUFF_CM7_TO_CM4_LEN) 54 | #define BUFFDATA_CM7_TO_CM4_LEN MEM_ALIGN(0x00000400) 55 | 56 | /* Define semaphores */ 57 | #define HSEM_TAKE_RELEASE(_id_) do { HAL_HSEM_FastTake((_id_)); HAL_HSEM_Release((_id_), 0); } while (0) 58 | #define HSEM_WAKEUP_CPU2 0 59 | #define HSEM_WAKEUP_CPU2_MASK __HAL_HSEM_SEMID_TO_MASK(HSEM_WAKEUP_CPU2) 60 | #define HSEM_CM4_TO_CM7 1 61 | #define HSEM_CM4_TO_CM7_MASK __HAL_HSEM_SEMID_TO_MASK(HSEM_CM4_TO_CM7) 62 | #define HSEM_CM7_TO_CM4 2 63 | #define HSEM_CM7_TO_CM4_MASK __HAL_HSEM_SEMID_TO_MASK(HSEM_CM7_TO_CM4) 64 | 65 | /* Flags management */ 66 | #define WAIT_COND_WITH_TIMEOUT(c, t) do { \ 67 | int32_t timeout = (int32_t)(t); \ 68 | while ((c) && timeout-- > 0) {} \ 69 | if (timeout < 0) { \ 70 | Error_Handler(); \ 71 | } \ 72 | } while (0) 73 | 74 | /* LEDs */ 75 | #define LD1_GPIO_CLK_EN __HAL_RCC_GPIOB_CLK_ENABLE 76 | #define LD1_GPIO_PORT GPIOB 77 | #define LD1_GPIO_PIN GPIO_PIN_0 78 | #define LD2_GPIO_CLK_EN __HAL_RCC_GPIOE_CLK_ENABLE 79 | #define LD2_GPIO_PORT GPIOE 80 | #define LD2_GPIO_PIN GPIO_PIN_1 81 | #define LD3_GPIO_CLK_EN __HAL_RCC_GPIOB_CLK_ENABLE 82 | #define LD3_GPIO_PORT GPIOB 83 | #define LD3_GPIO_PIN GPIO_PIN_14 84 | 85 | #endif /* COMMON_HDR_H */ 86 | -------------------------------------------------------------------------------- /projects/nucleo_stm32h745_q_aync_comm/Common/Src/system_stm32h7xx_dualcore_boot_cm4_cm7.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32h7xx_dualcore_boot_cm4_cm7.c 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. 6 | * This provides system initialization template function is case of 7 | * an application using a dual core STM32H7 device where 8 | * Cortex-M7 and Cortex-M4 boot are enabled at the FLASH option bytes 9 | * 10 | * This file provides two functions and one global variable to be called from 11 | * user application: 12 | * - SystemInit(): This function is called at startup just after reset and 13 | * before branch to main program. This call is made inside 14 | * the "startup_stm32h7xx.s" file. 15 | * 16 | * - SystemCoreClock variable: Contains the core clock, it can be used 17 | * by the user application to setup the SysTick 18 | * timer or configure other parameters. 19 | * 20 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 21 | * be called whenever the core clock is changed 22 | * during program execution. 23 | * 24 | * 25 | ****************************************************************************** 26 | * @attention 27 | * 28 | *

© Copyright (c) 2017 STMicroelectronics. 29 | * All rights reserved.

30 | * 31 | * This software component is licensed by ST under BSD 3-Clause license, 32 | * the "License"; You may not use this file except in compliance with the 33 | * License. You may obtain a copy of the License at: 34 | * opensource.org/licenses/BSD-3-Clause 35 | * 36 | ****************************************************************************** 37 | */ 38 | 39 | /** @addtogroup CMSIS 40 | * @{ 41 | */ 42 | 43 | /** @addtogroup stm32h7xx_system 44 | * @{ 45 | */ 46 | 47 | /** @addtogroup STM32H7xx_System_Private_Includes 48 | * @{ 49 | */ 50 | 51 | #include "stm32h7xx.h" 52 | #include 53 | 54 | #if !defined (HSE_VALUE) 55 | #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ 56 | #endif /* HSE_VALUE */ 57 | 58 | #if !defined (CSI_VALUE) 59 | #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ 60 | #endif /* CSI_VALUE */ 61 | 62 | #if !defined (HSI_VALUE) 63 | #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ 64 | #endif /* HSI_VALUE */ 65 | 66 | 67 | /** 68 | * @} 69 | */ 70 | 71 | /** @addtogroup STM32H7xx_System_Private_TypesDefinitions 72 | * @{ 73 | */ 74 | 75 | /** 76 | * @} 77 | */ 78 | 79 | /** @addtogroup STM32H7xx_System_Private_Defines 80 | * @{ 81 | */ 82 | 83 | /************************* Miscellaneous Configuration ************************/ 84 | /*!< Uncomment the following line if you need to relocate your vector Table in 85 | Internal SRAM. */ 86 | /* #define VECT_TAB_SRAM */ 87 | #define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. 88 | This value must be a multiple of 0x200. */ 89 | /******************************************************************************/ 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** @addtogroup STM32H7xx_System_Private_Macros 96 | * @{ 97 | */ 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /** @addtogroup STM32H7xx_System_Private_Variables 104 | * @{ 105 | */ 106 | /* This variable is updated in three ways: 107 | 1) by calling CMSIS function SystemCoreClockUpdate() 108 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 109 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 110 | Note: If you use this function to configure the system clock; then there 111 | is no need to call the 2 first functions listed above, since SystemCoreClock 112 | variable is updated automatically. 113 | */ 114 | uint32_t SystemCoreClock = 64000000; 115 | uint32_t SystemD2Clock = 64000000; 116 | const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; 117 | 118 | /** 119 | * @} 120 | */ 121 | 122 | /** @addtogroup STM32H7xx_System_Private_FunctionPrototypes 123 | * @{ 124 | */ 125 | 126 | /** 127 | * @} 128 | */ 129 | 130 | /** @addtogroup STM32H7xx_System_Private_Functions 131 | * @{ 132 | */ 133 | 134 | /** 135 | * @brief Setup the microcontroller system 136 | * Initialize the FPU setting and vector table location 137 | * configuration. 138 | * @param None 139 | * @retval None 140 | */ 141 | void SystemInit (void) 142 | { 143 | /* FPU settings ------------------------------------------------------------*/ 144 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 145 | SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 146 | #endif 147 | 148 | /*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is 149 | detectable by the CPU after a WFI/WFE instruction.*/ 150 | SCB->SCR |= SCB_SCR_SEVONPEND_Pos; 151 | 152 | #ifdef CORE_CM7 153 | /* Reset the RCC clock configuration to the default reset state ------------*/ 154 | /* Set HSION bit */ 155 | RCC->CR |= RCC_CR_HSION; 156 | 157 | /* Reset CFGR register */ 158 | RCC->CFGR = 0x00000000; 159 | 160 | /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ 161 | RCC->CR &= 0xEAF6ED7FU; 162 | 163 | /* Reset D1CFGR register */ 164 | RCC->D1CFGR = 0x00000000; 165 | 166 | /* Reset D2CFGR register */ 167 | RCC->D2CFGR = 0x00000000; 168 | 169 | /* Reset D3CFGR register */ 170 | RCC->D3CFGR = 0x00000000; 171 | 172 | /* Reset PLLCKSELR register */ 173 | RCC->PLLCKSELR = 0x00000000; 174 | 175 | /* Reset PLLCFGR register */ 176 | RCC->PLLCFGR = 0x00000000; 177 | /* Reset PLL1DIVR register */ 178 | RCC->PLL1DIVR = 0x00000000; 179 | /* Reset PLL1FRACR register */ 180 | RCC->PLL1FRACR = 0x00000000; 181 | 182 | /* Reset PLL2DIVR register */ 183 | RCC->PLL2DIVR = 0x00000000; 184 | 185 | /* Reset PLL2FRACR register */ 186 | 187 | RCC->PLL2FRACR = 0x00000000; 188 | /* Reset PLL3DIVR register */ 189 | RCC->PLL3DIVR = 0x00000000; 190 | 191 | /* Reset PLL3FRACR register */ 192 | RCC->PLL3FRACR = 0x00000000; 193 | 194 | /* Reset HSEBYP bit */ 195 | RCC->CR &= 0xFFFBFFFFU; 196 | 197 | /* Disable all interrupts */ 198 | RCC->CIER = 0x00000000; 199 | 200 | /* Enable CortexM7 HSEM EXTI line (line 78)*/ 201 | EXTI_D2->EMR3 |= 0x4000UL; 202 | 203 | 204 | if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 205 | { 206 | /* if stm32h7 revY*/ 207 | /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ 208 | *((__IO uint32_t*)0x51008108) = 0x000000001U; 209 | } 210 | 211 | #endif /* CORE_CM7*/ 212 | 213 | #ifdef CORE_CM4 214 | 215 | /* Configure the Vector Table location add offset address ------------------*/ 216 | #ifdef VECT_TAB_SRAM 217 | SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ 218 | #else 219 | SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 220 | #endif 221 | 222 | #else 223 | #ifdef CORE_CM7 224 | 225 | /* Configure the Vector Table location add offset address ------------------*/ 226 | #ifdef VECT_TAB_SRAM 227 | SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */ 228 | #else 229 | SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 230 | #endif 231 | 232 | #else 233 | #error Please #define CORE_CM4 or CORE_CM7 234 | #endif 235 | #endif 236 | 237 | } 238 | 239 | /** 240 | * @brief Update SystemCoreClock variable according to Clock Register Values. 241 | * The SystemCoreClock variable contains the core clock , it can 242 | * be used by the user application to setup the SysTick timer or configure 243 | * other parameters. 244 | * 245 | * @note Each time the core clock changes, this function must be called 246 | * to update SystemCoreClock variable value. Otherwise, any configuration 247 | * based on this variable will be incorrect. 248 | * 249 | * @note - The system frequency computed by this function is not the real 250 | * frequency in the chip. It is calculated based on the predefined 251 | * constant and the selected clock source: 252 | * 253 | * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) 254 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) 255 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) 256 | * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), 257 | * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. 258 | * 259 | * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value 260 | * 4 MHz) but the real value may vary depending on the variations 261 | * in voltage and temperature. 262 | * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value 263 | * 64 MHz) but the real value may vary depending on the variations 264 | * in voltage and temperature. 265 | * 266 | * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value 267 | * 25 MHz), user has to ensure that HSE_VALUE is same as the real 268 | * frequency of the crystal used. Otherwise, this function may 269 | * have wrong result. 270 | * 271 | * - The result of this function could be not correct when using fractional 272 | * value for HSE crystal. 273 | * @param None 274 | * @retval None 275 | */ 276 | void SystemCoreClockUpdate (void) 277 | { 278 | uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; 279 | uint32_t common_system_clock; 280 | float_t fracn1, pllvco; 281 | 282 | /* Get SYSCLK source -------------------------------------------------------*/ 283 | 284 | switch (RCC->CFGR & RCC_CFGR_SWS) 285 | { 286 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ 287 | common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); 288 | break; 289 | 290 | case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ 291 | common_system_clock = CSI_VALUE; 292 | break; 293 | 294 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ 295 | common_system_clock = HSE_VALUE; 296 | break; 297 | 298 | case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ 299 | 300 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN 301 | SYSCLK = PLL_VCO / PLLR 302 | */ 303 | pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 304 | pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; 305 | pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); 306 | fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); 307 | 308 | if (pllm != 0U) 309 | { 310 | switch (pllsource) 311 | { 312 | case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ 313 | 314 | hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; 315 | pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 316 | 317 | break; 318 | 319 | case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ 320 | pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 321 | break; 322 | 323 | case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ 324 | pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 325 | break; 326 | 327 | default: 328 | pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 329 | break; 330 | } 331 | pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; 332 | common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); 333 | } 334 | else 335 | { 336 | common_system_clock = 0U; 337 | } 338 | break; 339 | 340 | default: 341 | common_system_clock = CSI_VALUE; 342 | break; 343 | } 344 | 345 | /* Compute SystemClock frequency --------------------------------------------------*/ 346 | tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; 347 | 348 | /* common_system_clock frequency : CM7 CPU frequency */ 349 | common_system_clock >>= tmp; 350 | 351 | /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ 352 | SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 353 | 354 | #if defined(DUAL_CORE) && defined(CORE_CM4) 355 | SystemCoreClock = SystemD2Clock; 356 | #else 357 | SystemCoreClock = common_system_clock; 358 | #endif /* DUAL_CORE && CORE_CM4 */ 359 | } 360 | 361 | 362 | /** 363 | * @} 364 | */ 365 | 366 | /** 367 | * @} 368 | */ 369 | 370 | /** 371 | * @} 372 | */ 373 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 374 | --------------------------------------------------------------------------------