├── .DS_Store ├── .gitignore ├── .images ├── block_diagram.png ├── compression.png ├── hd.png ├── jpeg_algo.png └── lm.png ├── IMAGE_COMPRESSION_MATLAB ├── Quantization.m ├── cameraman.tif ├── imgCompression.m ├── inverseQuantization.m ├── newnewtest2.bmp ├── newtest2.bmp ├── test.JPG ├── test2.bmp ├── test3.jpg └── zigzag.m ├── IMAGE_COMPRESSION_VERILOG ├── DCT.v ├── DCT_TB.v ├── DiscreteCosineTransform.v ├── IMG_JPEG_COMPRESSION.v ├── IMG_JPEG_TB.v ├── IMG_ROM.v ├── IMG_ROM_synth.v ├── IMG_TB.v ├── JPEG_DCT.v ├── Matrix_Multiplier1_8X8.v ├── Mul_8x8_tb.v ├── Multiplier_8x8.v ├── Multiplier_8x8_tb.v ├── Quantization.v ├── Test.v ├── counter_3.v ├── counter_6.v ├── counter_64.v ├── counter_8.v ├── mul_test.v ├── ndndn.v └── test_tb.v ├── LICENSE └── README.md /.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaharshSuryawala/Image-Compression/a42ea6e48cb8e2088e0f5a64a56569fae55e87a6/.DS_Store -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store 2 | -------------------------------------------------------------------------------- /.images/block_diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaharshSuryawala/Image-Compression/a42ea6e48cb8e2088e0f5a64a56569fae55e87a6/.images/block_diagram.png -------------------------------------------------------------------------------- /.images/compression.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaharshSuryawala/Image-Compression/a42ea6e48cb8e2088e0f5a64a56569fae55e87a6/.images/compression.png -------------------------------------------------------------------------------- /.images/hd.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaharshSuryawala/Image-Compression/a42ea6e48cb8e2088e0f5a64a56569fae55e87a6/.images/hd.png -------------------------------------------------------------------------------- /.images/jpeg_algo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaharshSuryawala/Image-Compression/a42ea6e48cb8e2088e0f5a64a56569fae55e87a6/.images/jpeg_algo.png -------------------------------------------------------------------------------- /.images/lm.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaharshSuryawala/Image-Compression/a42ea6e48cb8e2088e0f5a64a56569fae55e87a6/.images/lm.png -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_MATLAB/Quantization.m: -------------------------------------------------------------------------------- 1 | function Q = Quantization(q,i) 2 | %load the quantization matrix and 3 | %round it off 4 | qMatrix=[16 11 10 16 24 40 51 61; 5 | 12 12 14 19 26 58 60 55; 6 | 14 13 16 24 40 57 69 56; 7 | 14 17 22 29 51 87 80 62; 8 | 18 22 37 56 68 109 103 77; 9 | 24 35 55 64 81 104 113 92; 10 | 49 64 78 87 103 121 120 101; 11 | 72 92 95 98 112 100 103 99]; 12 | if (i==8) 13 | Q=round(q./qMatrix); 14 | 15 | elseif (i==16) 16 | 17 | qMatrix16=[]; 18 | for i=1:8 19 | for j=1:8 20 | qMatrix16((2*i-1),(2*j-1))=qMatrix(i,j); 21 | qMatrix16((2*i-1),(2*j))=qMatrix(i,j); 22 | qMatrix16((2*i),(2*j-1))=qMatrix(i,j); 23 | qMatrix16((2*i),(2*j))=qMatrix(i,j); 24 | end 25 | end 26 | Q=round(q./qMatrix16); 27 | end 28 | 29 | end 30 | 31 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_MATLAB/cameraman.tif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaharshSuryawala/Image-Compression/a42ea6e48cb8e2088e0f5a64a56569fae55e87a6/IMAGE_COMPRESSION_MATLAB/cameraman.tif -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_MATLAB/imgCompression.m: -------------------------------------------------------------------------------- 1 | function image=imgCompression(x) 2 | 3 | %reading the image 4 | originalImage=imread(x); 5 | 6 | %get the number of pixels 7 | [rows,columns] = size(originalImage); 8 | 9 | Number_Pixels = rows*columns; 10 | 11 | copyofImage=originalImage; %copy of A 12 | 13 | %get the row and col size 14 | rowSize=size(copyofImage,1); 15 | colSize=size(copyofImage,2); 16 | 17 | %subtract the bytes from the image 18 | s=int16(copyofImage)-128; %level shifting 19 | DCT=[]; 20 | quantized=[]; 21 | count=1; 22 | 23 | 24 | blockSize=input('Enter 8 ---> 8X8 ||||| 16 ---> 16X16 : ') 25 | jump=0; 26 | zigzagcount=0; 27 | if blockSize==8 28 | jump=7; 29 | zigzagcount=64; 30 | printLimit=8; 31 | else 32 | jump=15; 33 | zigzagcount=256; 34 | printLimit=16; 35 | end 36 | 37 | %Encoding 38 | 39 | for i=1:blockSize:rowSize 40 | for j=1:blockSize:colSize 41 | %performing the DCT 42 | DCT(i:i+jump,j:j+jump) = dct2(s(i:i+jump,j:j+jump)); 43 | %performing the quantization 44 | quantized(i:i+jump,j:j+jump)=Quantization(DCT(i:i+jump,j:j+jump),blockSize); 45 | z(count,1:zigzagcount)=zigzag(quantized(i:i+jump,j:j+jump)); 46 | count=count+1; 47 | end 48 | end 49 | disp('Original Image'); 50 | copyofImage(1:printLimit,1:printLimit); 51 | disp('After Shifting'); 52 | s(1:printLimit,1:printLimit); 53 | disp('After Applying DCT'); 54 | DCT(1:printLimit,1:printLimit); 55 | disp('After Quantization'); 56 | quantized(1:printLimit,1:printLimit); 57 | z(1,1:zigzagcount); 58 | 59 | %------------------------------------------------------------------------------------------------------------- 60 | 61 | 62 | %Decoding 63 | 64 | DCTNew=[]; 65 | ImageNew=[]; 66 | 67 | 68 | for i=1:blockSize:rowSize 69 | for j=1:blockSize:colSize 70 | %Inverse of quantization 71 | DCTNew(i:i+jump,j:j+jump)=inverseQuantization(quantized(i:i+jump,j:j+jump),blockSize); 72 | %performing the inverse DCT 73 | ImageNew(i:i+jump,j:j+jump) = round(idct2(DCTNew(i:i+jump,j:j+jump))); 74 | end 75 | end 76 | 77 | image=ImageNew+128; %shifting 78 | 79 | image=uint8(image); 80 | 81 | 82 | %subplot(1,2,1) 83 | %imshow(originalImage) 84 | %title('Original Image') 85 | %subplot(1,2,2) 86 | imshow(image) 87 | %title('Compressed Image') 88 | %disp('Mean Squared Error') 89 | Error=abs(sum(sum(imsubtract(originalImage,image).^2)))/Number_Pixels %MSE 90 | 91 | end 92 | 93 | 94 | 95 | 96 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_MATLAB/inverseQuantization.m: -------------------------------------------------------------------------------- 1 | function matrix = inverseQuantization(B,i) 2 | %does the inverse of the quantization 3 | 4 | qMatrix=[16 11 10 16 24 40 51 61; 5 | 12 12 14 19 26 58 60 55; 6 | 14 13 16 24 40 57 69 56; 7 | 14 17 22 29 51 87 80 62; 8 | 18 22 37 56 68 109 103 77; 9 | 24 35 55 64 81 104 113 92; 10 | 49 64 78 87 103 121 120 101; 11 | 72 92 95 98 112 100 103 99]; 12 | 13 | 14 | if (i==8) 15 | matrix=round(B.*qMatrix); 16 | 17 | elseif (i==16) 18 | 19 | qMatrix16=[]; 20 | for i=1:8 21 | for j=1:8 22 | qMatrix16((2*i-1),(2*j-1))=qMatrix(i,j); 23 | qMatrix16((2*i-1),(2*j))=qMatrix(i,j); 24 | qMatrix16((2*i),(2*j-1))=qMatrix(i,j); 25 | qMatrix16((2*i),(2*j))=qMatrix(i,j); 26 | end 27 | end 28 | 29 | matrix=round(B.*qMatrix16); 30 | end 31 | 32 | end 33 | 34 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_MATLAB/newnewtest2.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaharshSuryawala/Image-Compression/a42ea6e48cb8e2088e0f5a64a56569fae55e87a6/IMAGE_COMPRESSION_MATLAB/newnewtest2.bmp -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_MATLAB/newtest2.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaharshSuryawala/Image-Compression/a42ea6e48cb8e2088e0f5a64a56569fae55e87a6/IMAGE_COMPRESSION_MATLAB/newtest2.bmp -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_MATLAB/test.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaharshSuryawala/Image-Compression/a42ea6e48cb8e2088e0f5a64a56569fae55e87a6/IMAGE_COMPRESSION_MATLAB/test.JPG -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_MATLAB/test2.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaharshSuryawala/Image-Compression/a42ea6e48cb8e2088e0f5a64a56569fae55e87a6/IMAGE_COMPRESSION_MATLAB/test2.bmp -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_MATLAB/test3.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MaharshSuryawala/Image-Compression/a42ea6e48cb8e2088e0f5a64a56569fae55e87a6/IMAGE_COMPRESSION_MATLAB/test3.jpg -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_MATLAB/zigzag.m: -------------------------------------------------------------------------------- 1 | function matrix = zigzag(in) 2 | %returns an 1*(n*m) array of zigzag order 3 | 4 | tmp=reshape(1:numel(in),size(in)); 5 | 6 | %flip l/r--diagonal matrix--flip l/r 7 | 8 | afterFliplr1=fliplr(tmp); 9 | afterSpdiags=spdiags(afterFliplr1); 10 | afterFliplr2=fliplr(afterSpdiags); 11 | 12 | %flip u/d (odd columns) 13 | 14 | afterFlipudOdd=afterFliplr2; 15 | afterFlipudOdd(:,1:2:end)=flipud(afterFliplr2(:,1:2:end)); %flipping all odd column elements 16 | 17 | %remove zero indexes 18 | 19 | orderNonZero=afterFlipudOdd; 20 | orderNonZero(orderNonZero==0)=[]; 21 | 22 | %get order 23 | 24 | matrix=in(orderNonZero); 25 | 26 | 27 | end 28 | 29 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/DCT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:45:52 10/30/2017 7 | // Design Name: 8 | // Module Name: DCT 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module DCT( 22 | input clk 23 | ); 24 | 25 | reg [15:0] DIMG [65536:0]; 26 | wire [31:0] DIMGtmp0, DIMGtmp1, DIMGtmp2, DIMGtmp3, DIMGtmp4, DIMGtmp5, DIMGtmp6, DIMGtmp7; 27 | wire [3:0] counter; 28 | wire [15:0] IMG_add_a; 29 | wire validtmp; 30 | reg valid = 0, transpose_valid = 1'b0; 31 | reg [7:0] counteri = 0, counterj = 0;//, qq <= 0; 32 | //reg [32:0] i=0; 33 | reg [15:0] swaptmp;//, mm1,mm2; 34 | 35 | 36 | //debugging 37 | // reg [15:0] a1,a0,a2,a3,a4,a5,a6,a7; 38 | //reg [15:0] aaa; 39 | 40 | Matrix_Multiplier1_8X8 DIMG1(DIMGtmp0, DIMGtmp1, DIMGtmp2, DIMGtmp3, DIMGtmp4, DIMGtmp5, DIMGtmp6, DIMGtmp7, counter, IMG_add_a, clk); 41 | 42 | //Debuging part 43 | /*assign a = IMG_add_a - 16; 44 | assign a0 = DIMG[IMG_add_a - 16]; 45 | assign a1 = DIMG[IMG_add_a - 15]; 46 | assign a2 = DIMG[IMG_add_a - 14]; 47 | assign a3 = DIMG[IMG_add_a - 13]; 48 | assign a4 = DIMG[IMG_add_a - 12]; 49 | assign a5 = DIMG[IMG_add_a - 11]; 50 | assign a6 = DIMG[IMG_add_a - 10]; 51 | assign a7 = DIMG[IMG_add_a - 9]; 52 | */ 53 | 54 | assign validtmp = (IMG_add_a == 16'hfffe) ? 1'b1 : 1'b0; 55 | //assign valid = (validtmp) ? 1'b1 : (IMG_add_a == 16'h0000) ? 1'b0 : (1'b0 | valid); 56 | //assign a = (counteri * 256) + counterj; 57 | 58 | always@(posedge clk) 59 | begin 60 | if(!(validtmp || valid)) 61 | begin 62 | //s qq = 7; 63 | if(counter == 4) 64 | begin 65 | DIMG[IMG_add_a - 16] <= DIMGtmp0[23:8]; 66 | DIMG[IMG_add_a - 15] <= DIMGtmp1[23:8]; 67 | DIMG[IMG_add_a - 14] <= DIMGtmp2[23:8]; 68 | DIMG[IMG_add_a - 13] <= DIMGtmp3[23:8]; 69 | DIMG[IMG_add_a - 12] <= DIMGtmp4[23:8]; 70 | DIMG[IMG_add_a - 11] <= DIMGtmp5[23:8]; 71 | DIMG[IMG_add_a - 10] <= DIMGtmp6[23:8]; 72 | DIMG[IMG_add_a - 9] <= DIMGtmp7[23:8]; 73 | 74 | end 75 | end 76 | if((validtmp || valid) && !transpose_valid) 77 | begin 78 | // $display($time, "\tEntered in validtmp if loop\n"); 79 | // qq <= 9; 80 | valid <= 1; 81 | 82 | 83 | if(counteri < 256) 84 | begin 85 | if(counterj < 256) 86 | begin 87 | swaptmp <= DIMG[(counteri * 256) + counterj]; 88 | DIMG[(counteri * 256) + counterj] <= DIMG[(counterj * 256) + counteri]; 89 | DIMG[(counterj * 256) + counteri] <= swaptmp; 90 | // mm1 <= DIMG[(counteri * 256) + counterj]; 91 | // mm2 <= DIMG[(counterj * 256) + counteri]; 92 | if(counterj == 255) 93 | begin 94 | counteri <= counteri + 1; 95 | counterj <= counteri + 1; 96 | //qq <= counteri + 1; 97 | end 98 | end 99 | if(counterj != 255) 100 | counterj <= counterj + 1; 101 | end 102 | end 103 | 104 | if(transpose_valid == 1'b1 || counteri == 255) 105 | transpose_valid <= 1'b1; 106 | // if (counteri == 255 || qq == 11) 107 | // qq<=11; 108 | /*if(qq == 11) 109 | begin 110 | aaa <= DIMG[i]; 111 | i <= i+1; 112 | 113 | end*/ 114 | 115 | 116 | 117 | // if(counterj == 255) 118 | /* if(counter == 0) 119 | begin 120 | // a0 <= DIMGtmp0[23:8]; 121 | //a1 <= IMG_add_a - 8; 122 | a <= IMG_add_a - 8; 123 | a0 <= DIMG [IMG_add_a - 8]; 124 | a1 <= DIMG [IMG_add_a - 7]; 125 | a2 <= DIMG [IMG_add_a - 6]; 126 | a3 = DIMG [IMG_add_a - 5]; 127 | a4 = DIMG [IMG_add_a - 4]; 128 | a5 = DIMG [IMG_add_a - 3]; 129 | a6 = DIMG [IMG_add_a - 2]; 130 | a7 = DIMG [IMG_add_a - 1]; 131 | 132 | end*/ 133 | 134 | 135 | end 136 | endmodule 137 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/DCT_TB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 15:21:59 11/04/2017 8 | // Design Name: DiscreteCosineTransform 9 | // Module Name: C:/Users/Maharsh Suryawala/Desktop/Functions/IMG/DCT_TB.v 10 | // Project Name: IMG 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: DiscreteCosineTransform 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module DCT_TB; 26 | 27 | // Inputs 28 | reg [15:0] H00; 29 | reg [15:0] H01; 30 | reg [15:0] H02; 31 | reg [15:0] H03; 32 | reg [15:0] H04; 33 | reg [15:0] H05; 34 | reg [15:0] H06; 35 | reg [15:0] H07; 36 | reg [15:0] H10; 37 | reg [15:0] H11; 38 | reg [15:0] H12; 39 | reg [15:0] H13; 40 | reg [15:0] H14; 41 | reg [15:0] H15; 42 | reg [15:0] H16; 43 | reg [15:0] H17; 44 | reg [15:0] H20; 45 | reg [15:0] H21; 46 | reg [15:0] H22; 47 | reg [15:0] H23; 48 | reg [15:0] H24; 49 | reg [15:0] H25; 50 | reg [15:0] H26; 51 | reg [15:0] H27; 52 | reg [15:0] H30; 53 | reg [15:0] H31; 54 | reg [15:0] H32; 55 | reg [15:0] H33; 56 | reg [15:0] H34; 57 | reg [15:0] H35; 58 | reg [15:0] H36; 59 | reg [15:0] H37; 60 | reg [15:0] H40; 61 | reg [15:0] H41; 62 | reg [15:0] H42; 63 | reg [15:0] H43; 64 | reg [15:0] H44; 65 | reg [15:0] H45; 66 | reg [15:0] H46; 67 | reg [15:0] H47; 68 | reg [15:0] H50; 69 | reg [15:0] H51; 70 | reg [15:0] H52; 71 | reg [15:0] H53; 72 | reg [15:0] H54; 73 | reg [15:0] H55; 74 | reg [15:0] H56; 75 | reg [15:0] H57; 76 | reg [15:0] H60; 77 | reg [15:0] H61; 78 | reg [15:0] H62; 79 | reg [15:0] H63; 80 | reg [15:0] H64; 81 | reg [15:0] H65; 82 | reg [15:0] H66; 83 | reg [15:0] H67; 84 | reg [15:0] H70; 85 | reg [15:0] H71; 86 | reg [15:0] H72; 87 | reg [15:0] H73; 88 | reg [15:0] H74; 89 | reg [15:0] H75; 90 | reg [15:0] H76; 91 | reg [15:0] H77; 92 | reg clk; 93 | 94 | // Outputs 95 | wire [15:0] D11_final; 96 | wire [15:0] D12_final; 97 | wire [15:0] D13_final; 98 | wire [15:0] D14_final; 99 | wire [15:0] D15_final; 100 | wire [15:0] D16_final; 101 | wire [15:0] D17_final; 102 | wire [15:0] D18_final; 103 | wire [15:0] D21_final; 104 | wire [15:0] D22_final; 105 | wire [15:0] D23_final; 106 | wire [15:0] D24_final; 107 | wire [15:0] D25_final; 108 | wire [15:0] D26_final; 109 | wire [15:0] D27_final; 110 | wire [15:0] D28_final; 111 | wire [15:0] D31_final; 112 | wire [15:0] D32_final; 113 | wire [15:0] D33_final; 114 | wire [15:0] D34_final; 115 | wire [15:0] D35_final; 116 | wire [15:0] D36_final; 117 | wire [15:0] D37_final; 118 | wire [15:0] D38_final; 119 | wire [15:0] D41_final; 120 | wire [15:0] D42_final; 121 | wire [15:0] D43_final; 122 | wire [15:0] D44_final; 123 | wire [15:0] D45_final; 124 | wire [15:0] D46_final; 125 | wire [15:0] D47_final; 126 | wire [15:0] D48_final; 127 | wire [15:0] D51_final; 128 | wire [15:0] D52_final; 129 | wire [15:0] D53_final; 130 | wire [15:0] D54_final; 131 | wire [15:0] D55_final; 132 | wire [15:0] D56_final; 133 | wire [15:0] D57_final; 134 | wire [15:0] D58_final; 135 | wire [15:0] D61_final; 136 | wire [15:0] D62_final; 137 | wire [15:0] D63_final; 138 | wire [15:0] D64_final; 139 | wire [15:0] D65_final; 140 | wire [15:0] D66_final; 141 | wire [15:0] D67_final; 142 | wire [15:0] D68_final; 143 | wire [15:0] D71_final; 144 | wire [15:0] D72_final; 145 | wire [15:0] D73_final; 146 | wire [15:0] D74_final; 147 | wire [15:0] D75_final; 148 | wire [15:0] D76_final; 149 | wire [15:0] D77_final; 150 | wire [15:0] D78_final; 151 | wire [15:0] D81_final; 152 | wire [15:0] D82_final; 153 | wire [15:0] D83_final; 154 | wire [15:0] D84_final; 155 | wire [15:0] D85_final; 156 | wire [15:0] D86_final; 157 | wire [15:0] D87_final; 158 | wire [15:0] D88_final; 159 | 160 | 161 | // Instantiate the Unit Under Test (UUT) 162 | DiscreteCosineTransform uut ( 163 | .D11_final(D11_final), 164 | .D12_final(D12_final), 165 | .D13_final(D13_final), 166 | .D14_final(D14_final), 167 | .D15_final(D15_final), 168 | .D16_final(D16_final), 169 | .D17_final(D17_final), 170 | .D18_final(D18_final), 171 | .D21_final(D21_final), 172 | .D22_final(D22_final), 173 | .D23_final(D23_final), 174 | .D24_final(D24_final), 175 | .D25_final(D25_final), 176 | .D26_final(D26_final), 177 | .D27_final(D27_final), 178 | .D28_final(D28_final), 179 | .D31_final(D31_final), 180 | .D32_final(D32_final), 181 | .D33_final(D33_final), 182 | .D34_final(D34_final), 183 | .D35_final(D35_final), 184 | .D36_final(D36_final), 185 | .D37_final(D37_final), 186 | .D38_final(D38_final), 187 | .D41_final(D41_final), 188 | .D42_final(D42_final), 189 | .D43_final(D43_final), 190 | .D44_final(D44_final), 191 | .D45_final(D45_final), 192 | .D46_final(D46_final), 193 | .D47_final(D47_final), 194 | .D48_final(D48_final), 195 | .D51_final(D51_final), 196 | .D52_final(D52_final), 197 | .D53_final(D53_final), 198 | .D54_final(D54_final), 199 | .D55_final(D55_final), 200 | .D56_final(D56_final), 201 | .D57_final(D57_final), 202 | .D58_final(D58_final), 203 | .D61_final(D61_final), 204 | .D62_final(D62_final), 205 | .D63_final(D63_final), 206 | .D64_final(D64_final), 207 | .D65_final(D65_final), 208 | .D66_final(D66_final), 209 | .D67_final(D67_final), 210 | .D68_final(D68_final), 211 | .D71_final(D71_final), 212 | .D72_final(D72_final), 213 | .D73_final(D73_final), 214 | .D74_final(D74_final), 215 | .D75_final(D75_final), 216 | .D76_final(D76_final), 217 | .D77_final(D77_final), 218 | .D78_final(D78_final), 219 | .D81_final(D81_final), 220 | .D82_final(D82_final), 221 | .D83_final(D83_final), 222 | .D84_final(D84_final), 223 | .D85_final(D85_final), 224 | .D86_final(D86_final), 225 | .D87_final(D87_final), 226 | .D88_final(D88_final), 227 | .H00(H00), 228 | .H01(H01), 229 | .H02(H02), 230 | .H03(H03), 231 | .H04(H04), 232 | .H05(H05), 233 | .H06(H06), 234 | .H07(H07), 235 | .H10(H10), 236 | .H11(H11), 237 | .H12(H12), 238 | .H13(H13), 239 | .H14(H14), 240 | .H15(H15), 241 | .H16(H16), 242 | .H17(H17), 243 | .H20(H20), 244 | .H21(H21), 245 | .H22(H22), 246 | .H23(H23), 247 | .H24(H24), 248 | .H25(H25), 249 | .H26(H26), 250 | .H27(H27), 251 | .H30(H30), 252 | .H31(H31), 253 | .H32(H32), 254 | .H33(H33), 255 | .H34(H34), 256 | .H35(H35), 257 | .H36(H36), 258 | .H37(H37), 259 | .H40(H40), 260 | .H41(H41), 261 | .H42(H42), 262 | .H43(H43), 263 | .H44(H44), 264 | .H45(H45), 265 | .H46(H46), 266 | .H47(H47), 267 | .H50(H50), 268 | .H51(H51), 269 | .H52(H52), 270 | .H53(H53), 271 | .H54(H54), 272 | .H55(H55), 273 | .H56(H56), 274 | .H57(H57), 275 | .H60(H60), 276 | .H61(H61), 277 | .H62(H62), 278 | .H63(H63), 279 | .H64(H64), 280 | .H65(H65), 281 | .H66(H66), 282 | .H67(H67), 283 | .H70(H70), 284 | .H71(H71), 285 | .H72(H72), 286 | .H73(H73), 287 | .H74(H74), 288 | .H75(H75), 289 | .H76(H76), 290 | .H77(H77), 291 | 292 | .clk(clk) 293 | ); 294 | 295 | initial begin 296 | // Initialize Inputs 297 | H00 = 0; 298 | H01 = 0; 299 | H02 = 0; 300 | H03 = 0; 301 | H04 = 0; 302 | H05 = 0; 303 | H06 = 0; 304 | H07 = 0; 305 | H10 = 0; 306 | H11 = 0; 307 | H12 = 0; 308 | H13 = 0; 309 | H14 = 0; 310 | H15 = 0; 311 | H16 = 0; 312 | H17 = 0; 313 | H20 = 0; 314 | H21 = 0; 315 | H22 = 0; 316 | H23 = 0; 317 | H24 = 0; 318 | H25 = 0; 319 | H26 = 0; 320 | H27 = 0; 321 | H30 = 0; 322 | H31 = 0; 323 | H32 = 0; 324 | H33 = 0; 325 | H34 = 0; 326 | H35 = 0; 327 | H36 = 0; 328 | H37 = 0; 329 | H40 = 0; 330 | H41 = 0; 331 | H42 = 0; 332 | H43 = 0; 333 | H44 = 0; 334 | H45 = 0; 335 | H46 = 0; 336 | H47 = 0; 337 | H50 = 0; 338 | H51 = 0; 339 | H52 = 0; 340 | H53 = 0; 341 | H54 = 0; 342 | H55 = 0; 343 | H56 = 0; 344 | H57 = 0; 345 | H60 = 0; 346 | H61 = 0; 347 | H62 = 0; 348 | H63 = 0; 349 | H64 = 0; 350 | H65 = 0; 351 | H66 = 0; 352 | H67 = 0; 353 | H70 = 0; 354 | H71 = 0; 355 | H72 = 0; 356 | H73 = 0; 357 | H74 = 0; 358 | H75 = 0; 359 | H76 = 0; 360 | H77 = 0; 361 | clk = 0; 362 | 363 | // Wait 100 ns for global reset to finish 364 | #100; 365 | 366 | H00=16'b0001110000000000; 367 | H01=16'b0010000000000000; 368 | H02=16'b0001110000000000; 369 | H03=16'b0010000000000000; 370 | H04=16'b0001110000000000; 371 | H05=16'b0001101100000000; 372 | H06=16'b0001110000000000; 373 | H07=16'b0001111100000000; 374 | 375 | H10=16'b0001111100000000; 376 | H11=16'b0001101000000000; 377 | H12=16'b0001111100000000; 378 | H13=16'b0001101000000000; 379 | H14=16'b0001100100000000; 380 | H15=16'b0001101100000000; 381 | H16=16'b0001100100000000; 382 | H17=16'b0001111100000000; 383 | 384 | H20=16'b0001111000000000; 385 | H21=16'b0001110100000000; 386 | H22=16'b0001111000000000; 387 | H23=16'b0001110100000000; 388 | H24=16'b0001101100000000; 389 | H25=16'b0001101100000000; 390 | H26=16'b0001110100000000; 391 | H27=16'b0001110000000000; 392 | 393 | H30=16'b0001101100000000; 394 | H31=16'b0001111000000000; 395 | H32=16'b0001101100000000; 396 | H33=16'b0001111000000000; 397 | H34=16'b0001111100000000; 398 | H35=16'b0001110100000000; 399 | H36=16'b0001110000000000; 400 | H37=16'b0001111000000000; 401 | 402 | H40=16'b0001111000000000; 403 | H41=16'b0001110100000000; 404 | H42=16'b0001111000000000; 405 | H43=16'b0001110100000000; 406 | H44=16'b0001111100000000; 407 | H45=16'b0001110000000000; 408 | H46=16'b0001100100000000; 409 | H47=16'b0001110000000000; 410 | 411 | 412 | H50=16'b0001110000000000; 413 | H51=16'b0001111100000000; 414 | H52=16'b0001110000000000; 415 | H53=16'b0001111100000000; 416 | H54=16'b0001101100000000; 417 | H55=16'b0001111100000000; 418 | H56=16'b0001101100000000; 419 | H57=16'b0001111100000000; 420 | 421 | H60=16'b0001111100000000; 422 | H61=16'b0001111000000000; 423 | H62=16'b0001111100000000; 424 | H63=16'b0001111000000000; 425 | H64=16'b0001110000000000; 426 | H65=16'b0001100000000000; 427 | H66=16'b0001101000000000; 428 | H67=16'b0001110100000000; 429 | 430 | 431 | H70=16'b0001111000000000; 432 | H71=16'b0001111000000000; 433 | H72=16'b0001111000000000; 434 | H73=16'b0001111000000000; 435 | H74=16'b0001101100000000; 436 | H75=16'b0001111000000000; 437 | H76=16'b0001101100000000; 438 | H77=16'b0010000100000000; 439 | 440 | // Add stimulus here 441 | 442 | end 443 | 444 | endmodule 445 | 446 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/DiscreteCosineTransform.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 23:38:45 10/30/2017 7 | // Design Name: 8 | // Module Name: DiscreteCosineTransform 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module DiscreteCosineTransform( 22 | // Dfinal=D(data_in)Din 23 | D11_final, D12_final, D13_final, D14_final, D15_final, D16_final, D17_final, D18_final, 24 | D21_final, D22_final, D23_final, D24_final, D25_final, D26_final, D27_final, D28_final, 25 | D31_final, D32_final, D33_final, D34_final, D35_final, D36_final, D37_final, D38_final, 26 | D41_final, D42_final, D43_final, D44_final, D45_final, D46_final, D47_final, D48_final, 27 | D51_final, D52_final, D53_final, D54_final, D55_final, D56_final, D57_final, D58_final, 28 | D61_final, D62_final, D63_final, D64_final, D65_final, D66_final, D67_final, D68_final, 29 | D71_final, D72_final, D73_final, D74_final, D75_final, D76_final, D77_final, D78_final, 30 | D81_final, D82_final, D83_final, D84_final, D85_final, D86_final, D87_final, D88_final, 31 | 32 | H00, H01, H02, H03, H04, H05, H06, H07, 33 | H10, H11, H12, H13, H14, H15, H16, H17, 34 | H20, H21, H22, H23, H24, H25, H26, H27, 35 | H30, H31, H32, H33, H34, H35, H36, H37, 36 | H40, H41, H42, H43, H44, H45, H46, H47, 37 | H50, H51, H52, H53, H54, H55, H56, H57, 38 | H60, H61, H62, H63, H64, H65, H66, H67, 39 | H70, H71, H72, H73, H74, H75, H76, H77 40 | ); 41 | 42 | output [15:0] D11_final, D12_final, D13_final, D14_final, D15_final, D16_final, D17_final, D18_final; 43 | output [15:0] D21_final, D22_final, D23_final, D24_final, D25_final, D26_final, D27_final, D28_final; 44 | output [15:0] D31_final, D32_final, D33_final, D34_final, D35_final, D36_final, D37_final, D38_final; 45 | output [15:0] D41_final, D42_final, D43_final, D44_final, D45_final, D46_final, D47_final, D48_final; 46 | output [15:0] D51_final, D52_final, D53_final, D54_final, D55_final, D56_final, D57_final, D58_final; 47 | output [15:0] D61_final, D62_final, D63_final, D64_final, D65_final, D66_final, D67_final, D68_final; 48 | output [15:0] D71_final, D72_final, D73_final, D74_final, D75_final, D76_final, D77_final, D78_final; 49 | output [15:0] D81_final, D82_final, D83_final, D84_final, D85_final, D86_final, D87_final, D88_final; 50 | 51 | //input [15:0] datain; 52 | //input clk; 53 | //reg [2:0] counti3=0; 54 | //reg [7:0] 8_bit_counter; 55 | 56 | wire[15:0] tmpD11_final, tmpD12_final, tmpD13_final, tmpD14_final, tmpD15_final, tmpD16_final, tmpD17_final, tmpD18_final; 57 | wire[15:0] tmpD21_final, tmpD22_final, tmpD23_final, tmpD24_final, tmpD25_final, tmpD26_final, tmpD27_final, tmpD28_final; 58 | wire[15:0] tmpD31_final, tmpD32_final, tmpD33_final, tmpD34_final, tmpD35_final, tmpD36_final, tmpD37_final, tmpD38_final; 59 | wire[15:0] tmpD41_final, tmpD42_final, tmpD43_final, tmpD44_final, tmpD45_final, tmpD46_final, tmpD47_final, tmpD48_final; 60 | wire[15:0] tmpD51_final, tmpD52_final, tmpD53_final, tmpD54_final, tmpD55_final, tmpD56_final, tmpD57_final, tmpD58_final; 61 | wire[15:0] tmpD61_final, tmpD62_final, tmpD63_final, tmpD64_final, tmpD65_final, tmpD66_final, tmpD67_final, tmpD68_final; 62 | wire[15:0] tmpD71_final, tmpD72_final, tmpD73_final, tmpD74_final, tmpD75_final, tmpD76_final, tmpD77_final, tmpD78_final; 63 | wire[15:0] tmpD81_final, tmpD82_final, tmpD83_final, tmpD84_final, tmpD85_final, tmpD86_final, tmpD87_final, tmpD88_final; 64 | 65 | 66 | input[15:0] H00, H01, H02, H03, H04, H05, H06, H07; 67 | input[15:0] H10, H11, H12, H13, H14, H15, H16, H17; 68 | input[15:0] H20, H21, H22, H23, H24, H25, H26, H27; 69 | input[15:0] H30, H31, H32, H33, H34, H35, H36, H37; 70 | input[15:0] H40, H41, H42, H43, H44, H45, H46, H47; 71 | input[15:0] H50, H51, H52, H53, H54, H55, H56, H57; 72 | input[15:0] H60, H61, H62, H63, H64, H65, H66, H67; 73 | input[15:0] H70, H71, H72, H73, H74, H75, H76, H77; 74 | 75 | 76 | 77 | //reg [5:0] bit_counter_6=0; 78 | wire [15:0] D[7:0][7:0]; 79 | wire [15:0] Din[7:0][7:0]; 80 | 81 | //counter_3 inst1(3_bit_counteri, clk, reset); 82 | //counter_3 inst2(3_bit_counterj, clk, reset); 83 | //counter_6 inst4(bit_counter_6, clk, 1); 84 | 85 | //counter_8 inst3(8_bit_counter, clk, reset); 86 | 87 | //DCT Matrix /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 88 | assign D[0][0] = 16'b0000000001011010; assign D[0][1] = 16'b0000000001011010; assign D[0][2] = 16'b0000000001011010; assign D[0][3] = 16'b0000000001011010; assign D[0][4] = 16'b0000000001011010; assign D[0][5] = 16'b0000000001011010; assign D[0][6] = 16'b0000000001011010; assign D[0][7] = 16'b0000000001011010; 89 | assign D[1][0] = 16'b0000000001111101; assign D[1][1] = 16'b0000000001101010; assign D[1][2] = 16'b0000000001000111; assign D[1][3] = 16'b0000000000011000; assign D[1][4] = 16'b1111111111100111; assign D[1][5] = 16'b1111111110111000; assign D[1][6] = 16'b1111111110010101; assign D[1][7] = 16'b1111111110000010; 90 | assign D[2][0] = 16'b0000000001110110; assign D[2][1] = 16'b0000000000110000; assign D[2][2] = 16'b1111111111001111; assign D[2][3] = 16'b1111111110001001; assign D[2][4] = 16'b1111111110001001; assign D[2][5] = 16'b1111111111001111; assign D[2][6] = 16'b0000000000110000; assign D[2][7] = 16'b0000000001110110; 91 | assign D[3][0] = 16'b0000000001101010; assign D[3][1] = 16'b1111111111100111; assign D[3][2] = 16'b1111111110000010; assign D[3][3] = 16'b1111111110111000; assign D[3][4] = 16'b0000000001000111; assign D[3][5] = 16'b0000000001111101; assign D[3][6] = 16'b0000000000011000; assign D[3][7] = 16'b0000000001101010; 92 | assign D[4][0] = 16'b0000000001011010; assign D[4][1] = 16'b1111111110100101; assign D[4][2] = 16'b1111111110100101; assign D[4][3] = 16'b0000000001011010; assign D[4][4] = 16'b0000000001011010; assign D[4][5] = 16'b1111111110100101; assign D[4][6] = 16'b1111111110100101; assign D[4][7] = 16'b0000000001011010; 93 | assign D[5][0] = 16'b0000000001000111; assign D[5][1] = 16'b1111111110000010; assign D[5][2] = 16'b0000000000011000; assign D[5][3] = 16'b0000000001101010; assign D[5][4] = 16'b1111111110010101; assign D[5][5] = 16'b1111111111100111; assign D[5][6] = 16'b0000000001111101; assign D[5][7] = 16'b1111111110111000; 94 | assign D[6][0] = 16'b0000000000110000; assign D[6][1] = 16'b1111111110001001; assign D[6][2] = 16'b0000000001110110; assign D[6][3] = 16'b1111111111001111; assign D[6][4] = 16'b1111111111001111; assign D[6][5] = 16'b0000000001110110; assign D[6][6] = 16'b1111111110001001; assign D[6][7] = 16'b0000000000110000; 95 | assign D[7][0] = 16'b0000000000011000; assign D[7][1] = 16'b1111111110111000; assign D[7][2] = 16'b0000000001101010; assign D[7][3] = 16'b1111101100011000; assign D[7][4] = 16'b0000000001111101; assign D[7][5] = 16'b1111111110010101; assign D[7][6] = 16'b0000000001000111; assign D[7][7] = 16'b1111111111100111; 96 | 97 | //DCT Transpose Matrix ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 98 | 99 | assign Din[0][0] = 16'b0000000001011010; 100 | assign Din[1][0] = 16'b0000000001011010; 101 | assign Din[2][0] = 16'b0000000001011010; 102 | assign Din[3][0] = 16'b0000000001011010; 103 | assign Din[4][0] = 16'b0000000001011010; 104 | assign Din[5][0] = 16'b0000000001011010; 105 | assign Din[6][0] = 16'b0000000001011010; 106 | assign Din[7][0] = 16'b0000000001011010; 107 | 108 | assign Din[0][1] = 16'b0000000001111101; 109 | assign Din[1][1] = 16'b0000000001101010; 110 | assign Din[2][1] = 16'b0000000001000111; 111 | assign Din[3][1] = 16'b0000000000011000; 112 | assign Din[4][1] = 16'b1111111111100111; 113 | assign Din[5][1] = 16'b1111111110111000; 114 | assign Din[6][1] = 16'b1111111110010101; 115 | assign Din[7][1] = 16'b1111111110000010; 116 | 117 | assign Din[0][2] = 16'b0000000001110110; 118 | assign Din[1][2] = 16'b0000000000110000; 119 | assign Din[2][2] = 16'b1111111111001111; 120 | assign Din[3][2] = 16'b1111111110001001; 121 | assign Din[4][2] = 16'b1111111110001001; 122 | assign Din[5][2] = 16'b1111111111001111; 123 | assign Din[6][2] = 16'b0000000000110000; 124 | assign Din[7][2] = 16'b0000000001110110; 125 | 126 | assign Din[0][3] = 16'b0000000001101010; 127 | assign Din[1][3] = 16'b1111111111100111; 128 | assign Din[2][3] = 16'b1111111110000010; 129 | assign Din[3][3] = 16'b1111111110111000; 130 | assign Din[4][3] = 16'b0000000001000111; 131 | assign Din[5][3] = 16'b0000000001111101; 132 | assign Din[6][3] = 16'b0000000000011000; 133 | assign Din[7][3] = 16'b0000000001101010; 134 | 135 | assign Din[0][4] = 16'b0000000001011010; 136 | assign Din[1][4] = 16'b1111111110100101; 137 | assign Din[2][4] = 16'b1111111110100101; 138 | assign Din[3][4] = 16'b0000000001011010; 139 | assign Din[4][4] = 16'b0000000001011010; 140 | assign Din[5][4] = 16'b1111111110100101; 141 | assign Din[6][4] = 16'b1111111110100101; 142 | assign Din[7][4] = 16'b0000000001011010; 143 | 144 | assign Din[0][5] = 16'b0000000001000111; 145 | assign Din[1][5] = 16'b1111111110000010; 146 | assign Din[2][5] = 16'b0000000000011000; 147 | assign Din[3][5] = 16'b0000000001101010; 148 | assign Din[4][5] = 16'b1111111110010101; 149 | assign Din[5][5] = 16'b1111111111100111; 150 | assign Din[6][5] = 16'b0000000001111101; 151 | assign Din[7][5] = 16'b1111111110111000; 152 | 153 | assign Din[0][6] = 16'b0000000000110000; 154 | assign Din[1][6] = 16'b1111111110001001; 155 | assign Din[2][6] = 16'b0000000001110110; 156 | assign Din[3][6] = 16'b1111111111001111; 157 | assign Din[4][6] = 16'b1111111111001111; 158 | assign Din[5][6] = 16'b0000000001110110; 159 | assign Din[6][6] = 16'b1111111110001001; 160 | assign Din[7][6] = 16'b0000000000110000; 161 | 162 | assign Din[0][7] = 16'b0000000000011000; 163 | assign Din[1][7] = 16'b1111111110111000; 164 | assign Din[2][7] = 16'b0000000001101010; 165 | assign Din[3][7] = 16'b1111101100011000; 166 | assign Din[4][7] = 16'b0000000001111101; 167 | assign Din[5][7] = 16'b1111111110010101; 168 | assign Din[6][7] = 16'b0000000001000111; 169 | assign Din[7][7] = 16'b1111111111100111; 170 | 171 | 172 | 173 | 174 | /*always@(posedge clk) 175 | begin 176 | if(bit_counter_6 < 64) 177 | begin 178 | 179 | tmp[bit_counter_6] = datain; 180 | bit_counter_6 = bit_counter_6 + 1; 181 | end 182 | end*/ 183 | 184 | 185 | ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 186 | //8x8 image block 187 | /*assign H[0][0] = tmp[0] ; assign H[0][1] = tmp[1] ; assign H[0][2] = tmp[2] ; assign H[0][3] = tmp[3] ; assign H[0][4] = tmp[4] ; assign H[0][5] = tmp[5] ; assign H[0][6] = tmp[6] ; assign H[0][7] = tmp[7] ; 188 | assign H[1][0] = tmp[8] ; assign H[1][1] = tmp[9] ; assign H[1][2] = tmp[10] ; assign H[1][3] = tmp[11] ; assign H[1][4] = tmp[12] ; assign H[1][5] = tmp[13] ; assign H[1][6] = tmp[14] ; assign H[1][7] = tmp[15] ; 189 | assign H[2][0] = tmp[16] ; assign H[2][1] = tmp[17] ; assign H[2][2] = tmp[18] ; assign H[2][3] = tmp[19] ; assign H[2][4] = tmp[20] ; assign H[2][5] = tmp[21] ; assign H[2][6] = tmp[22] ; assign H[2][7] = tmp[23] ; 190 | assign H[3][0] = tmp[24] ; assign H[3][1] = tmp[25] ; assign H[3][2] = tmp[26] ; assign H[3][3] = tmp[27] ; assign H[3][4] = tmp[28] ; assign H[3][5] = tmp[29] ; assign H[3][6] = tmp[30] ; assign H[3][7] = tmp[31] ; 191 | assign H[4][0] = tmp[32] ; assign H[4][1] = tmp[33] ; assign H[4][2] = tmp[34] ; assign H[4][3] = tmp[35] ; assign H[4][4] = tmp[36] ; assign H[4][5] = tmp[37] ; assign H[4][6] = tmp[38] ; assign H[4][7] = tmp[39] ; 192 | assign H[5][0] = tmp[40] ; assign H[5][1] = tmp[41] ; assign H[5][2] = tmp[42] ; assign H[5][3] = tmp[43] ; assign H[5][4] = tmp[44] ; assign H[5][5] = tmp[45] ; assign H[5][6] = tmp[46] ; assign H[5][7] = tmp[47] ; 193 | assign H[6][0] = tmp[48] ; assign H[6][1] = tmp[49] ; assign H[6][2] = tmp[50] ; assign H[6][3] = tmp[51] ; assign H[6][4] = tmp[52] ; assign H[6][5] = tmp[53] ; assign H[6][6] = tmp[54] ; assign H[6][7] = tmp[55] ; 194 | assign H[7][0] = tmp[56] ; assign H[7][1] = tmp[57] ; assign H[7][2] = tmp[58] ; assign H[7][3] = tmp[59] ; assign H[7][4] = tmp[60] ; assign H[7][5] = tmp[61] ; assign H[7][6] = tmp[62] ; assign H[7][7] = tmp[63] ; 195 | */ 196 | ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 197 | 198 | 199 | Multiplier_8x8 mul1( 200 | tmpD11_final, tmpD12_final, tmpD13_final, tmpD14_final, tmpD15_final, tmpD16_final, tmpD17_final, tmpD18_final, 201 | tmpD21_final, tmpD22_final, tmpD23_final, tmpD24_final, tmpD25_final, tmpD26_final, tmpD27_final, tmpD28_final, 202 | tmpD31_final, tmpD32_final, tmpD33_final, tmpD34_final, tmpD35_final, tmpD36_final, tmpD37_final, tmpD38_final, 203 | tmpD41_final, tmpD42_final, tmpD43_final, tmpD44_final, tmpD45_final, tmpD46_final, tmpD47_final, tmpD48_final, 204 | tmpD51_final, tmpD52_final, tmpD53_final, tmpD54_final, tmpD55_final, tmpD56_final, tmpD57_final, tmpD58_final, 205 | tmpD61_final, tmpD62_final, tmpD63_final, tmpD64_final, tmpD65_final, tmpD66_final, tmpD67_final, tmpD68_final, 206 | tmpD71_final, tmpD72_final, tmpD73_final, tmpD74_final, tmpD75_final, tmpD76_final, tmpD77_final, tmpD78_final, 207 | tmpD81_final, tmpD82_final, tmpD83_final, tmpD84_final, tmpD85_final, tmpD86_final, tmpD87_final, tmpD88_final, 208 | 209 | D[0][0], D[0][1], D[0][2], D[0][3], D[0][4], D[0][5], D[0][6], D[0][7], 210 | D[1][0], D[1][1], D[1][2], D[1][3], D[1][4], D[1][5], D[1][6], D[1][7], 211 | D[2][0], D[2][1], D[2][2], D[2][3], D[2][4], D[2][5], D[2][6], D[2][7], 212 | D[3][0], D[3][1], D[3][2], D[3][3], D[3][4], D[3][5], D[3][6], D[3][7], 213 | D[4][0], D[4][1], D[4][2], D[4][3], D[4][4], D[4][5], D[4][6], D[4][7], 214 | D[5][0], D[5][1], D[5][2], D[5][3], D[5][4], D[5][5], D[5][6], D[5][7], 215 | D[6][0], D[6][1], D[6][2], D[6][3], D[6][4], D[6][5], D[6][6], D[6][7], 216 | D[7][0], D[7][1], D[7][2], D[7][3], D[7][4], D[7][5], D[7][6], D[7][7], 217 | 218 | H00, H01, H02, H03, H04, H05, H06, H07, 219 | H10, H11, H12, H13, H14, H15, H16, H17, 220 | H20, H21, H22, H23, H24, H25, H26, H27, 221 | H30, H31, H32, H33, H34, H35, H36, H37, 222 | H40, H41, H42, H43, H44, H45, H46, H47, 223 | H50, H51, H52, H53, H54, H55, H56, H57, 224 | H60, H61, H62, H63, H64, H65, H66, H67, 225 | H70, H71, H72, H73, H74, H75, H76, H77 226 | ); 227 | 228 | Multiplier_8x8 mul2( 229 | D11_final, D12_final, D13_final, D14_final, D15_final, D16_final, D17_final, D18_final, 230 | D21_final, D22_final, D23_final, D24_final, D25_final, D26_final, D27_final, D28_final, 231 | D31_final, D32_final, D33_final, D34_final, D35_final, D36_final, D37_final, D38_final, 232 | D41_final, D42_final, D43_final, D44_final, D45_final, D46_final, D47_final, D48_final, 233 | D51_final, D52_final, D53_final, D54_final, D55_final, D56_final, D57_final, D58_final, 234 | D61_final, D62_final, D63_final, D64_final, D65_final, D66_final, D67_final, D68_final, 235 | D71_final, D72_final, D73_final, D74_final, D75_final, D76_final, D77_final, D78_final, 236 | D81_final, D82_final, D83_final, D84_final, D85_final, D86_final, D87_final, D88_final, 237 | 238 | tmpD11_final, tmpD12_final, tmpD13_final, tmpD14_final, tmpD15_final, tmpD16_final, tmpD17_final, tmpD18_final, 239 | tmpD21_final, tmpD22_final, tmpD23_final, tmpD24_final, tmpD25_final, tmpD26_final, tmpD27_final, tmpD28_final, 240 | tmpD31_final, tmpD32_final, tmpD33_final, tmpD34_final, tmpD35_final, tmpD36_final, tmpD37_final, tmpD38_final, 241 | tmpD41_final, tmpD42_final, tmpD43_final, tmpD44_final, tmpD45_final, tmpD46_final, tmpD47_final, tmpD48_final, 242 | tmpD51_final, tmpD52_final, tmpD53_final, tmpD54_final, tmpD55_final, tmpD56_final, tmpD57_final, tmpD58_final, 243 | tmpD61_final, tmpD62_final, tmpD63_final, tmpD64_final, tmpD65_final, tmpD66_final, tmpD67_final, tmpD68_final, 244 | tmpD71_final, tmpD72_final, tmpD73_final, tmpD74_final, tmpD75_final, tmpD76_final, tmpD77_final, tmpD78_final, 245 | tmpD81_final, tmpD82_final, tmpD83_final, tmpD84_final, tmpD85_final, tmpD86_final, tmpD87_final, tmpD88_final, 246 | 247 | Din[0][0], Din[0][1], Din[0][2], Din[0][3], Din[0][4], Din[0][5], Din[0][6], Din[0][7], 248 | Din[1][0], Din[1][1], Din[1][2], Din[1][3], Din[1][4], Din[1][5], Din[1][6], Din[1][7], 249 | Din[2][0], Din[2][1], Din[2][2], Din[2][3], Din[2][4], Din[2][5], Din[2][6], Din[2][7], 250 | Din[3][0], Din[3][1], Din[3][2], Din[3][3], Din[3][4], Din[3][5], Din[3][6], Din[3][7], 251 | Din[4][0], Din[4][1], Din[4][2], Din[4][3], Din[4][4], Din[4][5], Din[4][6], Din[4][7], 252 | Din[5][0], Din[5][1], Din[5][2], Din[5][3], Din[5][4], Din[5][5], Din[5][6], Din[5][7], 253 | Din[6][0], Din[6][1], Din[6][2], Din[6][3], Din[6][4], Din[6][5], Din[6][6], Din[6][7], 254 | Din[7][0], Din[7][1], Din[7][2], Din[7][3], Din[7][4], Din[7][5], Din[7][6], Din[7][7] 255 | ); 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | endmodule 274 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/IMG_JPEG_COMPRESSION.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 11:23:21 11/05/2017 7 | // Design Name: 8 | // Module Name: IMG_JPEG_COMPRESSION 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module IMG_JPEG_COMPRESSION( 22 | 23 | I11_final, I12_final, I13_final, I14_final, I15_final, I16_final, I17_final, I18_final, 24 | I21_final, I22_final, I23_final, I24_final, I25_final, I26_final, I27_final, I28_final, 25 | I31_final, I32_final, I33_final, I34_final, I35_final, I36_final, I37_final, I38_final, 26 | I41_final, I42_final, I43_final, I44_final, I45_final, I46_final, I47_final, I48_final, 27 | I51_final, I52_final, I53_final, I54_final, I55_final, I56_final, I57_final, I58_final, 28 | I61_final, I62_final, I63_final, I64_final, I65_final, I66_final, I67_final, I68_final, 29 | I71_final, I72_final, I73_final, I74_final, I75_final, I76_final, I77_final, I78_final, 30 | I81_final, I82_final, I83_final, I84_final, I85_final, I86_final, I87_final, I88_final, 31 | 32 | H00, H01, H02, H03, H04, H05, H06, H07, 33 | H10, H11, H12, H13, H14, H15, H16, H17, 34 | H20, H21, H22, H23, H24, H25, H26, H27, 35 | H30, H31, H32, H33, H34, H35, H36, H37, 36 | H40, H41, H42, H43, H44, H45, H46, H47, 37 | H50, H51, H52, H53, H54, H55, H56, H57, 38 | H60, H61, H62, H63, H64, H65, H66, H67, 39 | H70, H71, H72, H73, H74, H75, H76, H77 40 | 41 | ); 42 | 43 | output [15:0] I11_final, I12_final, I13_final, I14_final, I15_final, I16_final, I17_final, I18_final; 44 | output [15:0] I21_final, I22_final, I23_final, I24_final, I25_final, I26_final, I27_final, I28_final; 45 | output [15:0] I31_final, I32_final, I33_final, I34_final, I35_final, I36_final, I37_final, I38_final; 46 | output [15:0] I41_final, I42_final, I43_final, I44_final, I45_final, I46_final, I47_final, I48_final; 47 | output [15:0] I51_final, I52_final, I53_final, I54_final, I55_final, I56_final, I57_final, I58_final; 48 | output [15:0] I61_final, I62_final, I63_final, I64_final, I65_final, I66_final, I67_final, I68_final; 49 | output [15:0] I71_final, I72_final, I73_final, I74_final, I75_final, I76_final, I77_final, I78_final; 50 | output [15:0] I81_final, I82_final, I83_final, I84_final, I85_final, I86_final, I87_final, I88_final; 51 | 52 | input[15:0] H00, H01, H02, H03, H04, H05, H06, H07; 53 | input[15:0] H10, H11, H12, H13, H14, H15, H16, H17; 54 | input[15:0] H20, H21, H22, H23, H24, H25, H26, H27; 55 | input[15:0] H30, H31, H32, H33, H34, H35, H36, H37; 56 | input[15:0] H40, H41, H42, H43, H44, H45, H46, H47; 57 | input[15:0] H50, H51, H52, H53, H54, H55, H56, H57; 58 | input[15:0] H60, H61, H62, H63, H64, H65, H66, H67; 59 | input[15:0] H70, H71, H72, H73, H74, H75, H76, H77; 60 | 61 | wire[15:0] D11_final, D12_final, D13_final, D14_final, D15_final, D16_final, D17_final, D18_final; 62 | wire[15:0] D21_final, D22_final, D23_final, D24_final, D25_final, D26_final, D27_final, D28_final; 63 | wire[15:0] D31_final, D32_final, D33_final, D34_final, D35_final, D36_final, D37_final, D38_final; 64 | wire[15:0] D41_final, D42_final, D43_final, D44_final, D45_final, D46_final, D47_final, D48_final; 65 | wire[15:0] D51_final, D52_final, D53_final, D54_final, D55_final, D56_final, D57_final, D58_final; 66 | wire[15:0] D61_final, D62_final, D63_final, D64_final, D65_final, D66_final, D67_final, D68_final; 67 | wire[15:0] D71_final, D72_final, D73_final, D74_final, D75_final, D76_final, D77_final, D78_final; 68 | wire[15:0] D81_final, D82_final, D83_final, D84_final, D85_final, D86_final, D87_final, D88_final; 69 | 70 | DiscreteCosineTransform DCT1( 71 | 72 | D11_final, D12_final, D13_final, D14_final, D15_final, D16_final, D17_final, D18_final, 73 | D21_final, D22_final, D23_final, D24_final, D25_final, D26_final, D27_final, D28_final, 74 | D31_final, D32_final, D33_final, D34_final, D35_final, D36_final, D37_final, D38_final, 75 | D41_final, D42_final, D43_final, D44_final, D45_final, D46_final, D47_final, D48_final, 76 | D51_final, D52_final, D53_final, D54_final, D55_final, D56_final, D57_final, D58_final, 77 | D61_final, D62_final, D63_final, D64_final, D65_final, D66_final, D67_final, D68_final, 78 | D71_final, D72_final, D73_final, D74_final, D75_final, D76_final, D77_final, D78_final, 79 | D81_final, D82_final, D83_final, D84_final, D85_final, D86_final, D87_final, D88_final, 80 | 81 | H00, H01, H02, H03, H04, H05, H06, H07, 82 | H10, H11, H12, H13, H14, H15, H16, H17, 83 | H20, H21, H22, H23, H24, H25, H26, H27, 84 | H30, H31, H32, H33, H34, H35, H36, H37, 85 | H40, H41, H42, H43, H44, H45, H46, H47, 86 | H50, H51, H52, H53, H54, H55, H56, H57, 87 | H60, H61, H62, H63, H64, H65, H66, H67, 88 | H70, H71, H72, H73, H74, H75, H76, H77 89 | ); 90 | 91 | Quantization quantize( 92 | I11_final, I12_final, I13_final, I14_final, I15_final, I16_final, I17_final, I18_final, 93 | I21_final, I22_final, I23_final, I24_final, I25_final, I26_final, I27_final, I28_final, 94 | I31_final, I32_final, I33_final, I34_final, I35_final, I36_final, I37_final, I38_final, 95 | I41_final, I42_final, I43_final, I44_final, I45_final, I46_final, I47_final, I48_final, 96 | I51_final, I52_final, I53_final, I54_final, I55_final, I56_final, I57_final, I58_final, 97 | I61_final, I62_final, I63_final, I64_final, I65_final, I66_final, I67_final, I68_final, 98 | I71_final, I72_final, I73_final, I74_final, I75_final, I76_final, I77_final, I78_final, 99 | I81_final, I82_final, I83_final, I84_final, I85_final, I86_final, I87_final, I88_final, 100 | 101 | H00, H01, H02, H03, H04, H05, H06, H07, 102 | H10, H11, H12, H13, H14, H15, H16, H17, 103 | H20, H21, H22, H23, H24, H25, H26, H27, 104 | H30, H31, H32, H33, H34, H35, H36, H37, 105 | H40, H41, H42, H43, H44, H45, H46, H47, 106 | H50, H51, H52, H53, H54, H55, H56, H57, 107 | H60, H61, H62, H63, H64, H65, H66, H67, 108 | H70, H71, H72, H73, H74, H75, H76, H77 109 | ); 110 | 111 | 112 | endmodule 113 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/IMG_JPEG_TB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 11:34:13 11/05/2017 8 | // Design Name: IMG_JPEG_COMPRESSION 9 | // Module Name: C:/Users/Maharsh Suryawala/Desktop/Functions/IMG/IMG_JPEG_TB.v 10 | // Project Name: IMG 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: IMG_JPEG_COMPRESSION 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module IMG_JPEG_TB; 26 | 27 | // Inputs 28 | reg [15:0] H00; 29 | reg [15:0] H01; 30 | reg [15:0] H02; 31 | reg [15:0] H03; 32 | reg [15:0] H04; 33 | reg [15:0] H05; 34 | reg [15:0] H06; 35 | reg [15:0] H07; 36 | reg [15:0] H10; 37 | reg [15:0] H11; 38 | reg [15:0] H12; 39 | reg [15:0] H13; 40 | reg [15:0] H14; 41 | reg [15:0] H15; 42 | reg [15:0] H16; 43 | reg [15:0] H17; 44 | reg [15:0] H20; 45 | reg [15:0] H21; 46 | reg [15:0] H22; 47 | reg [15:0] H23; 48 | reg [15:0] H24; 49 | reg [15:0] H25; 50 | reg [15:0] H26; 51 | reg [15:0] H27; 52 | reg [15:0] H30; 53 | reg [15:0] H31; 54 | reg [15:0] H32; 55 | reg [15:0] H33; 56 | reg [15:0] H34; 57 | reg [15:0] H35; 58 | reg [15:0] H36; 59 | reg [15:0] H37; 60 | reg [15:0] H40; 61 | reg [15:0] H41; 62 | reg [15:0] H42; 63 | reg [15:0] H43; 64 | reg [15:0] H44; 65 | reg [15:0] H45; 66 | reg [15:0] H46; 67 | reg [15:0] H47; 68 | reg [15:0] H50; 69 | reg [15:0] H51; 70 | reg [15:0] H52; 71 | reg [15:0] H53; 72 | reg [15:0] H54; 73 | reg [15:0] H55; 74 | reg [15:0] H56; 75 | reg [15:0] H57; 76 | reg [15:0] H60; 77 | reg [15:0] H61; 78 | reg [15:0] H62; 79 | reg [15:0] H63; 80 | reg [15:0] H64; 81 | reg [15:0] H65; 82 | reg [15:0] H66; 83 | reg [15:0] H67; 84 | reg [15:0] H70; 85 | reg [15:0] H71; 86 | reg [15:0] H72; 87 | reg [15:0] H73; 88 | reg [15:0] H74; 89 | reg [15:0] H75; 90 | reg [15:0] H76; 91 | reg [15:0] H77; 92 | 93 | // Outputs 94 | wire [15:0] I11_final; 95 | wire [15:0] I12_final; 96 | wire [15:0] I13_final; 97 | wire [15:0] I14_final; 98 | wire [15:0] I15_final; 99 | wire [15:0] I16_final; 100 | wire [15:0] I17_final; 101 | wire [15:0] I18_final; 102 | wire [15:0] I21_final; 103 | wire [15:0] I22_final; 104 | wire [15:0] I23_final; 105 | wire [15:0] I24_final; 106 | wire [15:0] I25_final; 107 | wire [15:0] I26_final; 108 | wire [15:0] I27_final; 109 | wire [15:0] I28_final; 110 | wire [15:0] I31_final; 111 | wire [15:0] I32_final; 112 | wire [15:0] I33_final; 113 | wire [15:0] I34_final; 114 | wire [15:0] I35_final; 115 | wire [15:0] I36_final; 116 | wire [15:0] I37_final; 117 | wire [15:0] I38_final; 118 | wire [15:0] I41_final; 119 | wire [15:0] I42_final; 120 | wire [15:0] I43_final; 121 | wire [15:0] I44_final; 122 | wire [15:0] I45_final; 123 | wire [15:0] I46_final; 124 | wire [15:0] I47_final; 125 | wire [15:0] I48_final; 126 | wire [15:0] I51_final; 127 | wire [15:0] I52_final; 128 | wire [15:0] I53_final; 129 | wire [15:0] I54_final; 130 | wire [15:0] I55_final; 131 | wire [15:0] I56_final; 132 | wire [15:0] I57_final; 133 | wire [15:0] I58_final; 134 | wire [15:0] I61_final; 135 | wire [15:0] I62_final; 136 | wire [15:0] I63_final; 137 | wire [15:0] I64_final; 138 | wire [15:0] I65_final; 139 | wire [15:0] I66_final; 140 | wire [15:0] I67_final; 141 | wire [15:0] I68_final; 142 | wire [15:0] I71_final; 143 | wire [15:0] I72_final; 144 | wire [15:0] I73_final; 145 | wire [15:0] I74_final; 146 | wire [15:0] I75_final; 147 | wire [15:0] I76_final; 148 | wire [15:0] I77_final; 149 | wire [15:0] I78_final; 150 | wire [15:0] I81_final; 151 | wire [15:0] I82_final; 152 | wire [15:0] I83_final; 153 | wire [15:0] I84_final; 154 | wire [15:0] I85_final; 155 | wire [15:0] I86_final; 156 | wire [15:0] I87_final; 157 | wire [15:0] I88_final; 158 | 159 | // Instantiate the Unit Under Test (UUT) 160 | IMG_JPEG_COMPRESSION uut ( 161 | .I11_final(I11_final), 162 | .I12_final(I12_final), 163 | .I13_final(I13_final), 164 | .I14_final(I14_final), 165 | .I15_final(I15_final), 166 | .I16_final(I16_final), 167 | .I17_final(I17_final), 168 | .I18_final(I18_final), 169 | .I21_final(I21_final), 170 | .I22_final(I22_final), 171 | .I23_final(I23_final), 172 | .I24_final(I24_final), 173 | .I25_final(I25_final), 174 | .I26_final(I26_final), 175 | .I27_final(I27_final), 176 | .I28_final(I28_final), 177 | .I31_final(I31_final), 178 | .I32_final(I32_final), 179 | .I33_final(I33_final), 180 | .I34_final(I34_final), 181 | .I35_final(I35_final), 182 | .I36_final(I36_final), 183 | .I37_final(I37_final), 184 | .I38_final(I38_final), 185 | .I41_final(I41_final), 186 | .I42_final(I42_final), 187 | .I43_final(I43_final), 188 | .I44_final(I44_final), 189 | .I45_final(I45_final), 190 | .I46_final(I46_final), 191 | .I47_final(I47_final), 192 | .I48_final(I48_final), 193 | .I51_final(I51_final), 194 | .I52_final(I52_final), 195 | .I53_final(I53_final), 196 | .I54_final(I54_final), 197 | .I55_final(I55_final), 198 | .I56_final(I56_final), 199 | .I57_final(I57_final), 200 | .I58_final(I58_final), 201 | .I61_final(I61_final), 202 | .I62_final(I62_final), 203 | .I63_final(I63_final), 204 | .I64_final(I64_final), 205 | .I65_final(I65_final), 206 | .I66_final(I66_final), 207 | .I67_final(I67_final), 208 | .I68_final(I68_final), 209 | .I71_final(I71_final), 210 | .I72_final(I72_final), 211 | .I73_final(I73_final), 212 | .I74_final(I74_final), 213 | .I75_final(I75_final), 214 | .I76_final(I76_final), 215 | .I77_final(I77_final), 216 | .I78_final(I78_final), 217 | .I81_final(I81_final), 218 | .I82_final(I82_final), 219 | .I83_final(I83_final), 220 | .I84_final(I84_final), 221 | .I85_final(I85_final), 222 | .I86_final(I86_final), 223 | .I87_final(I87_final), 224 | .I88_final(I88_final), 225 | .H00(H00), 226 | .H01(H01), 227 | .H02(H02), 228 | .H03(H03), 229 | .H04(H04), 230 | .H05(H05), 231 | .H06(H06), 232 | .H07(H07), 233 | .H10(H10), 234 | .H11(H11), 235 | .H12(H12), 236 | .H13(H13), 237 | .H14(H14), 238 | .H15(H15), 239 | .H16(H16), 240 | .H17(H17), 241 | .H20(H20), 242 | .H21(H21), 243 | .H22(H22), 244 | .H23(H23), 245 | .H24(H24), 246 | .H25(H25), 247 | .H26(H26), 248 | .H27(H27), 249 | .H30(H30), 250 | .H31(H31), 251 | .H32(H32), 252 | .H33(H33), 253 | .H34(H34), 254 | .H35(H35), 255 | .H36(H36), 256 | .H37(H37), 257 | .H40(H40), 258 | .H41(H41), 259 | .H42(H42), 260 | .H43(H43), 261 | .H44(H44), 262 | .H45(H45), 263 | .H46(H46), 264 | .H47(H47), 265 | .H50(H50), 266 | .H51(H51), 267 | .H52(H52), 268 | .H53(H53), 269 | .H54(H54), 270 | .H55(H55), 271 | .H56(H56), 272 | .H57(H57), 273 | .H60(H60), 274 | .H61(H61), 275 | .H62(H62), 276 | .H63(H63), 277 | .H64(H64), 278 | .H65(H65), 279 | .H66(H66), 280 | .H67(H67), 281 | .H70(H70), 282 | .H71(H71), 283 | .H72(H72), 284 | .H73(H73), 285 | .H74(H74), 286 | .H75(H75), 287 | .H76(H76), 288 | .H77(H77) 289 | ); 290 | 291 | initial begin 292 | // Initialize Inputs 293 | H00 = 0; 294 | H01 = 0; 295 | H02 = 0; 296 | H03 = 0; 297 | H04 = 0; 298 | H05 = 0; 299 | H06 = 0; 300 | H07 = 0; 301 | H10 = 0; 302 | H11 = 0; 303 | H12 = 0; 304 | H13 = 0; 305 | H14 = 0; 306 | H15 = 0; 307 | H16 = 0; 308 | H17 = 0; 309 | H20 = 0; 310 | H21 = 0; 311 | H22 = 0; 312 | H23 = 0; 313 | H24 = 0; 314 | H25 = 0; 315 | H26 = 0; 316 | H27 = 0; 317 | H30 = 0; 318 | H31 = 0; 319 | H32 = 0; 320 | H33 = 0; 321 | H34 = 0; 322 | H35 = 0; 323 | H36 = 0; 324 | H37 = 0; 325 | H40 = 0; 326 | H41 = 0; 327 | H42 = 0; 328 | H43 = 0; 329 | H44 = 0; 330 | H45 = 0; 331 | H46 = 0; 332 | H47 = 0; 333 | H50 = 0; 334 | H51 = 0; 335 | H52 = 0; 336 | H53 = 0; 337 | H54 = 0; 338 | H55 = 0; 339 | H56 = 0; 340 | H57 = 0; 341 | H60 = 0; 342 | H61 = 0; 343 | H62 = 0; 344 | H63 = 0; 345 | H64 = 0; 346 | H65 = 0; 347 | H66 = 0; 348 | H67 = 0; 349 | H70 = 0; 350 | H71 = 0; 351 | H72 = 0; 352 | H73 = 0; 353 | H74 = 0; 354 | H75 = 0; 355 | H76 = 0; 356 | H77 = 0; 357 | 358 | // Wait 100 ns for global reset to finish 359 | #100; 360 | 361 | H00=16'b0001110000000000; 362 | H01=16'b0010000000000000; 363 | H02=16'b0001110000000000; 364 | H03=16'b0010000000000000; 365 | H04=16'b0001110000000000; 366 | H05=16'b0001101100000000; 367 | H06=16'b0001110000000000; 368 | H07=16'b0001111100000000; 369 | 370 | H10=16'b0001111100000000; 371 | H11=16'b0001101000000000; 372 | H12=16'b0001111100000000; 373 | H13=16'b0001101000000000; 374 | H14=16'b0001100100000000; 375 | H15=16'b0001101100000000; 376 | H16=16'b0001100100000000; 377 | H17=16'b0001111100000000; 378 | 379 | H20=16'b0001111000000000; 380 | H21=16'b0001110100000000; 381 | H22=16'b0001111000000000; 382 | H23=16'b0001110100000000; 383 | H24=16'b0001101100000000; 384 | H25=16'b0001101100000000; 385 | H26=16'b0001110100000000; 386 | H27=16'b0001110000000000; 387 | 388 | H30=16'b0001101100000000; 389 | H31=16'b0001111000000000; 390 | H32=16'b0001101100000000; 391 | H33=16'b0001111000000000; 392 | H34=16'b0001111100000000; 393 | H35=16'b0001110100000000; 394 | H36=16'b0001110000000000; 395 | H37=16'b0001111000000000; 396 | 397 | H40=16'b0001111000000000; 398 | H41=16'b0001110100000000; 399 | H42=16'b0001111000000000; 400 | H43=16'b0001110100000000; 401 | H44=16'b0001111100000000; 402 | H45=16'b0001110000000000; 403 | H46=16'b0001100100000000; 404 | H47=16'b0001110000000000; 405 | 406 | 407 | H50=16'b0001110000000000; 408 | H51=16'b0001111100000000; 409 | H52=16'b0001110000000000; 410 | H53=16'b0001111100000000; 411 | H54=16'b0001101100000000; 412 | H55=16'b0001111100000000; 413 | H56=16'b0001101100000000; 414 | H57=16'b0001111100000000; 415 | 416 | H60=16'b0001111100000000; 417 | H61=16'b0001111000000000; 418 | H62=16'b0001111100000000; 419 | H63=16'b0001111000000000; 420 | H64=16'b0001110000000000; 421 | H65=16'b0001100000000000; 422 | H66=16'b0001101000000000; 423 | H67=16'b0001110100000000; 424 | 425 | 426 | H70=16'b0001111000000000; 427 | H71=16'b0001111000000000; 428 | H72=16'b0001111000000000; 429 | H73=16'b0001111000000000; 430 | H74=16'b0001101100000000; 431 | H75=16'b0001111000000000; 432 | H76=16'b0001101100000000; 433 | H77=16'b0010000100000000; 434 | 435 | 436 | // Add stimulus here 437 | 438 | end 439 | 440 | endmodule 441 | 442 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/IMG_ROM.v: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used solely * 3 | * for design, simulation, implementation and creation of design files * 4 | * limited to Xilinx devices or technologies. Use with non-Xilinx * 5 | * devices or technologies is expressly prohibited and immediately * 6 | * terminates your license. * 7 | * * 8 | * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * 9 | * FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * 10 | * PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * 11 | * IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * 12 | * MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * 13 | * CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * 14 | * RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * 15 | * DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * 16 | * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * 17 | * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * 18 | * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * 19 | * PARTICULAR PURPOSE. * 20 | * * 21 | * Xilinx products are not intended for use in life support appliances, * 22 | * devices, or systems. Use in such applications are expressly * 23 | * prohibited. * 24 | * * 25 | * (c) Copyright 1995-2017 Xilinx, Inc. * 26 | * All rights reserved. * 27 | *******************************************************************************/ 28 | // You must compile the wrapper file IMG_ROM.v when simulating 29 | // the core, IMG_ROM. When compiling the wrapper file, be sure to 30 | // reference the XilinxCoreLib Verilog simulation library. For detailed 31 | // instructions, please refer to the "CORE Generator Help". 32 | 33 | // The synthesis directives "translate_off/translate_on" specified below are 34 | // supported by Xilinx, Mentor Graphics and Synplicity synthesis 35 | // tools. Ensure they are correct for your synthesis tool(s). 36 | 37 | `timescale 1ns/1ps 38 | 39 | module IMG_ROM( 40 | clka, 41 | addra, 42 | douta, 43 | clkb, 44 | addrb, 45 | doutb 46 | ); 47 | 48 | input clka; 49 | input [15 : 0] addra; 50 | output [7 : 0] douta; 51 | input clkb; 52 | input [15 : 0] addrb; 53 | output [7 : 0] doutb; 54 | 55 | // synthesis translate_off 56 | 57 | BLK_MEM_GEN_V7_2 #( 58 | .C_ADDRA_WIDTH(16), 59 | .C_ADDRB_WIDTH(16), 60 | .C_ALGORITHM(1), 61 | .C_AXI_ID_WIDTH(4), 62 | .C_AXI_SLAVE_TYPE(0), 63 | .C_AXI_TYPE(1), 64 | .C_BYTE_SIZE(9), 65 | .C_COMMON_CLK(0), 66 | .C_DEFAULT_DATA("0"), 67 | .C_DISABLE_WARN_BHV_COLL(0), 68 | .C_DISABLE_WARN_BHV_RANGE(0), 69 | .C_ENABLE_32BIT_ADDRESS(0), 70 | .C_FAMILY("artix7"), 71 | .C_HAS_AXI_ID(0), 72 | .C_HAS_ENA(0), 73 | .C_HAS_ENB(0), 74 | .C_HAS_INJECTERR(0), 75 | .C_HAS_MEM_OUTPUT_REGS_A(0), 76 | .C_HAS_MEM_OUTPUT_REGS_B(0), 77 | .C_HAS_MUX_OUTPUT_REGS_A(0), 78 | .C_HAS_MUX_OUTPUT_REGS_B(0), 79 | .C_HAS_REGCEA(0), 80 | .C_HAS_REGCEB(0), 81 | .C_HAS_RSTA(0), 82 | .C_HAS_RSTB(0), 83 | .C_HAS_SOFTECC_INPUT_REGS_A(0), 84 | .C_HAS_SOFTECC_OUTPUT_REGS_B(0), 85 | .C_INIT_FILE_NAME("IMG_ROM.mif"), 86 | .C_INITA_VAL("0"), 87 | .C_INITB_VAL("0"), 88 | .C_INTERFACE_TYPE(0), 89 | .C_LOAD_INIT_FILE(1), 90 | .C_MEM_TYPE(4), 91 | .C_MUX_PIPELINE_STAGES(0), 92 | .C_PRIM_TYPE(1), 93 | .C_READ_DEPTH_A(65536), 94 | .C_READ_DEPTH_B(65536), 95 | .C_READ_WIDTH_A(8), 96 | .C_READ_WIDTH_B(8), 97 | .C_RST_PRIORITY_A("CE"), 98 | .C_RST_PRIORITY_B("CE"), 99 | .C_RST_TYPE("SYNC"), 100 | .C_RSTRAM_A(0), 101 | .C_RSTRAM_B(0), 102 | .C_SIM_COLLISION_CHECK("ALL"), 103 | .C_USE_BYTE_WEA(0), 104 | .C_USE_BYTE_WEB(0), 105 | .C_USE_DEFAULT_DATA(0), 106 | .C_USE_ECC(0), 107 | .C_USE_SOFTECC(0), 108 | .C_WEA_WIDTH(1), 109 | .C_WEB_WIDTH(1), 110 | .C_WRITE_DEPTH_A(65536), 111 | .C_WRITE_DEPTH_B(65536), 112 | .C_WRITE_MODE_A("WRITE_FIRST"), 113 | .C_WRITE_MODE_B("WRITE_FIRST"), 114 | .C_WRITE_WIDTH_A(8), 115 | .C_WRITE_WIDTH_B(8), 116 | .C_XDEVICEFAMILY("artix7") 117 | ) 118 | inst ( 119 | .CLKA(clka), 120 | .ADDRA(addra), 121 | .DOUTA(douta), 122 | .CLKB(clkb), 123 | .ADDRB(addrb), 124 | .DOUTB(doutb), 125 | .RSTA(), 126 | .ENA(), 127 | .REGCEA(), 128 | .WEA(), 129 | .DINA(), 130 | .RSTB(), 131 | .ENB(), 132 | .REGCEB(), 133 | .WEB(), 134 | .DINB(), 135 | .INJECTSBITERR(), 136 | .INJECTDBITERR(), 137 | .SBITERR(), 138 | .DBITERR(), 139 | .RDADDRECC(), 140 | .S_ACLK(), 141 | .S_ARESETN(), 142 | .S_AXI_AWID(), 143 | .S_AXI_AWADDR(), 144 | .S_AXI_AWLEN(), 145 | .S_AXI_AWSIZE(), 146 | .S_AXI_AWBURST(), 147 | .S_AXI_AWVALID(), 148 | .S_AXI_AWREADY(), 149 | .S_AXI_WDATA(), 150 | .S_AXI_WSTRB(), 151 | .S_AXI_WLAST(), 152 | .S_AXI_WVALID(), 153 | .S_AXI_WREADY(), 154 | .S_AXI_BID(), 155 | .S_AXI_BRESP(), 156 | .S_AXI_BVALID(), 157 | .S_AXI_BREADY(), 158 | .S_AXI_ARID(), 159 | .S_AXI_ARADDR(), 160 | .S_AXI_ARLEN(), 161 | .S_AXI_ARSIZE(), 162 | .S_AXI_ARBURST(), 163 | .S_AXI_ARVALID(), 164 | .S_AXI_ARREADY(), 165 | .S_AXI_RID(), 166 | .S_AXI_RDATA(), 167 | .S_AXI_RRESP(), 168 | .S_AXI_RLAST(), 169 | .S_AXI_RVALID(), 170 | .S_AXI_RREADY(), 171 | .S_AXI_INJECTSBITERR(), 172 | .S_AXI_INJECTDBITERR(), 173 | .S_AXI_SBITERR(), 174 | .S_AXI_DBITERR(), 175 | .S_AXI_RDADDRECC() 176 | ); 177 | 178 | // synthesis translate_on 179 | 180 | endmodule 181 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/IMG_ROM_synth.v: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used solely * 3 | * for design, simulation, implementation and creation of design files * 4 | * limited to Xilinx devices or technologies. Use with non-Xilinx * 5 | * devices or technologies is expressly prohibited and immediately * 6 | * terminates your license. * 7 | * * 8 | * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * 9 | * FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * 10 | * PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * 11 | * IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * 12 | * MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * 13 | * CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * 14 | * RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * 15 | * DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * 16 | * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * 17 | * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * 18 | * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * 19 | * PARTICULAR PURPOSE. * 20 | * * 21 | * Xilinx products are not intended for use in life support appliances, * 22 | * devices, or systems. Use in such applications are expressly * 23 | * prohibited. * 24 | * * 25 | * (c) Copyright 1995-2017 Xilinx, Inc. * 26 | * All rights reserved. * 27 | *******************************************************************************/ 28 | 29 | /******************************************************************************* 30 | * Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.2 * 31 | * * 32 | * The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port * 33 | * Block Memory and Single Port Block Memory LogiCOREs, but is not a * 34 | * direct drop-in replacement. It should be used in all new Xilinx * 35 | * designs. The core supports RAM and ROM functions over a wide range of * 36 | * widths and depths. Use this core to generate block memories with * 37 | * symmetric or asymmetric read and write port widths, as well as cores * 38 | * which can perform simultaneous write operations to separate * 39 | * locations, and simultaneous read operations from the same location. * 40 | * For more information on differences in interface and feature support * 41 | * between this core and the Dual Port Block Memory and Single Port * 42 | * Block Memory LogiCOREs, please consult the data sheet. * 43 | *******************************************************************************/ 44 | // Synthesized Netlist Wrapper 45 | // This file is provided to wrap around the synthesized netlist (if appropriate) 46 | 47 | // Interfaces: 48 | // CLK.ACLK 49 | // AXI4 Interconnect Clock Input 50 | // RST.ARESETN 51 | // AXI4 Interconnect Reset Input 52 | // AXI_SLAVE_S_AXI 53 | // AXI_SLAVE 54 | // AXILite_SLAVE_S_AXI 55 | // AXILite_SLAVE 56 | // BRAM_PORTA 57 | // BRAM_PORTA 58 | // BRAM_PORTB 59 | // BRAM_PORTB 60 | 61 | module IMG_ROM ( 62 | clka, 63 | addra, 64 | douta, 65 | clkb, 66 | addrb, 67 | doutb 68 | ); 69 | 70 | input clka; 71 | input [15 : 0] addra; 72 | output [7 : 0] douta; 73 | input clkb; 74 | input [15 : 0] addrb; 75 | output [7 : 0] doutb; 76 | 77 | // WARNING: This file provides a module declaration only, it does not support 78 | // direct instantiation. Please use an instantiation template (VEO) to 79 | // instantiate the IP within a design. 80 | 81 | endmodule 82 | 83 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/IMG_TB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 20:57:15 10/30/2017 8 | // Design Name: DCT 9 | // Module Name: C:/Users/Maharsh Suryawala/Desktop/Functions/IMG/IMG_TB.v 10 | // Project Name: IMG 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: DCT 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module IMG_TB; 26 | 27 | // Inputs 28 | reg clk; 29 | 30 | // Instantiate the Unit Under Test (UUT) 31 | DCT uut ( 32 | .clk(clk) 33 | ); 34 | 35 | initial begin 36 | // Initialize Inputs 37 | clk = 0; 38 | 39 | // Wait 100 ns for global reset to finish 40 | #100; 41 | 42 | // Add stimulus here 43 | 44 | end 45 | always #500 clk = ~clk; 46 | endmodule 47 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/JPEG_DCT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:26:59 10/30/2017 7 | // Design Name: 8 | // Module Name: JPEG_DCT 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module JPEG_DCT(clk, reset, enable, data_in, 22 | 23 | Z11_final, Z12_final, Z13_final, Z14_final, Z15_final, Z16_final, Z17_final, Z18_final, 24 | Z21_final, Z22_final, Z23_final, Z24_final, Z25_final, Z26_final, Z27_final, Z28_final, 25 | Z31_final, Z32_final, Z33_final, Z34_final, Z35_final, Z36_final, Z37_final, Z38_final, 26 | Z41_final, Z42_final, Z43_final, Z44_final, Z45_final, Z46_final, Z47_final, Z48_final, 27 | Z51_final, Z52_final, Z53_final, Z54_final, Z55_final, Z56_final, Z57_final, Z58_final, 28 | Z61_final, Z62_final, Z63_final, Z64_final, Z65_final, Z66_final, Z67_final, Z68_final, 29 | Z71_final, Z72_final, Z73_final, Z74_final, Z75_final, Z76_final, Z77_final, Z78_final, 30 | Z81_final, Z82_final, Z83_final, Z84_final, Z85_final, Z86_final, Z87_final, Z88_final, 31 | 32 | output_enable); 33 | 34 | input clk; 35 | input rst; 36 | input enable; 37 | 38 | input [7:0] data_in; 39 | 40 | output [10:0] Z11_final, Z12_final, Z13_final, Z14_final; 41 | output [10:0] Z15_final, Z16_final, Z17_final, Z18_final; 42 | output [10:0] Z21_final, Z22_final, Z23_final, Z24_final; 43 | output [10:0] Z25_final, Z26_final, Z27_final, Z28_final; 44 | output [10:0] Z31_final, Z32_final, Z33_final, Z34_final; 45 | output [10:0] Z35_final, Z36_final, Z37_final, Z38_final; 46 | output [10:0] Z41_final, Z42_final, Z43_final, Z44_final; 47 | output [10:0] Z45_final, Z46_final, Z47_final, Z48_final; 48 | output [10:0] Z51_final, Z52_final, Z53_final, Z54_final; 49 | output [10:0] Z55_final, Z56_final, Z57_final, Z58_final; 50 | output [10:0] Z61_final, Z62_final, Z63_final, Z64_final; 51 | output [10:0] Z65_final, Z66_final, Z67_final, Z68_final; 52 | output [10:0] Z71_final, Z72_final, Z73_final, Z74_final; 53 | output [10:0] Z75_final, Z76_final, Z77_final, Z78_final; 54 | output [10:0] Z81_final, Z82_final, Z83_final, Z84_final; 55 | output [10:0] Z85_final, Z86_final, Z87_final, Z88_final; 56 | 57 | output output_enable; 58 | 59 | 60 | integer T1, T21, T22, T23, T24, T25, T26, T27, T28, T31, T32, T33, T34, T52; 61 | integer Ti1, Ti21, Ti22, Ti23, Ti24, Ti25, Ti26, Ti27, Ti28, Ti31, Ti32, Ti33, Ti34, Ti52; 62 | 63 | reg [24:0] Y_temp_11; 64 | reg [24:0] Y11, Y21, Y31, Y41, Y51, Y61, Y71, Y81, Y11_final; 65 | 66 | reg [31:0] Y_temp_21, Y_temp_31, Y_temp_41, Y_temp_51; 67 | reg [31:0] Y_temp_61, Y_temp_71, Y_temp_81; 68 | 69 | reg [31:0] Z_temp_11, Z_temp_12, Z_temp_13, Z_temp_14; 70 | reg [31:0] Z_temp_15, Z_temp_16, Z_temp_17, Z_temp_18; 71 | reg [31:0] Z_temp_21, Z_temp_22, Z_temp_23, Z_temp_24; 72 | reg [31:0] Z_temp_25, Z_temp_26, Z_temp_27, Z_temp_28; 73 | reg [31:0] Z_temp_31, Z_temp_32, Z_temp_33, Z_temp_34; 74 | reg [31:0] Z_temp_35, Z_temp_36, Z_temp_37, Z_temp_38; 75 | reg [31:0] Z_temp_41, Z_temp_42, Z_temp_43, Z_temp_44; 76 | reg [31:0] Z_temp_45, Z_temp_46, Z_temp_47, Z_temp_48; 77 | reg [31:0] Z_temp_51, Z_temp_52, Z_temp_53, Z_temp_54; 78 | reg [31:0] Z_temp_55, Z_temp_56, Z_temp_57, Z_temp_58; 79 | reg [31:0] Z_temp_61, Z_temp_62, Z_temp_63, Z_temp_64; 80 | reg [31:0] Z_temp_65, Z_temp_66, Z_temp_67, Z_temp_68; 81 | reg [31:0] Z_temp_71, Z_temp_72, Z_temp_73, Z_temp_74; 82 | reg [31:0] Z_temp_75, Z_temp_76, Z_temp_77, Z_temp_78; 83 | reg [31:0] Z_temp_81, Z_temp_82, Z_temp_83, Z_temp_84; 84 | reg [31:0] Z_temp_85, Z_temp_86, Z_temp_87, Z_temp_88; 85 | 86 | reg [26:0] Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18; 87 | reg [26:0] Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28; 88 | reg [26:0] Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38; 89 | reg [26:0] Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48; 90 | reg [26:0] Z51, Z52, Z53, Z54, Z55, Z56, Z57, Z58; 91 | reg [26:0] Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68; 92 | reg [26:0] Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78; 93 | reg [26:0] Z81, Z82, Z83, Z84, Z85, Z86, Z87, Z88; 94 | 95 | reg [31:0] Y11_final_2, Y21_final_2, Y11_final_3, Y11_final_4, Y31_final_2, Y41_final_2; 96 | reg [31:0] Y51_final_2, Y61_final_2, Y71_final_2, Y81_final_2; 97 | 98 | reg [12:0] Y11_final_1, Y21_final_1, Y31_final_1, Y41_final_1; 99 | reg [12:0] Y51_final_1, Y61_final_1, Y71_final_1, Y81_final_1; 100 | 101 | reg [24:0] Y21_final, Y31_final, Y41_final, Y51_final; 102 | reg [24:0] Y61_final, Y71_final, Y81_final; 103 | reg [24:0] Y21_final_prev, Y21_final_diff; 104 | reg [24:0] Y31_final_prev, Y31_final_diff; 105 | reg [24:0] Y41_final_prev, Y41_final_diff; 106 | reg [24:0] Y51_final_prev, Y51_final_diff; 107 | reg [24:0] Y61_final_prev, Y61_final_diff; 108 | reg [24:0] Y71_final_prev, Y71_final_diff; 109 | reg [24:0] Y81_final_prev, Y81_final_diff; 110 | 111 | reg [10:0] Z11_final, Z12_final, Z13_final, Z14_final; 112 | reg [10:0] Z15_final, Z16_final, Z17_final, Z18_final; 113 | reg [10:0] Z21_final, Z22_final, Z23_final, Z24_final; 114 | reg [10:0] Z25_final, Z26_final, Z27_final, Z28_final; 115 | reg [10:0] Z31_final, Z32_final, Z33_final, Z34_final; 116 | reg [10:0] Z35_final, Z36_final, Z37_final, Z38_final; 117 | reg [10:0] Z41_final, Z42_final, Z43_final, Z44_final; 118 | reg [10:0] Z45_final, Z46_final, Z47_final, Z48_final; 119 | reg [10:0] Z51_final, Z52_final, Z53_final, Z54_final; 120 | reg [10:0] Z55_final, Z56_final, Z57_final, Z58_final; 121 | reg [10:0] Z61_final, Z62_final, Z63_final, Z64_final; 122 | reg [10:0] Z65_final, Z66_final, Z67_final, Z68_final; 123 | reg [10:0] Z71_final, Z72_final, Z73_final, Z74_final; 124 | reg [10:0] Z75_final, Z76_final, Z77_final, Z78_final; 125 | reg [10:0] Z81_final, Z82_final, Z83_final, Z84_final; 126 | reg [10:0] Z85_final, Z86_final, Z87_final, Z88_final; 127 | 128 | reg [2:0] count; 129 | reg [2:0] count_of, count_of_copy; 130 | reg count_1, count_3, count_4, count_5, count_6, count_7, count_8, enable_1, output_enable; 131 | reg count_9, count_10; 132 | 133 | reg [7:0] data_1; 134 | 135 | integer Y2_mul_input, Y3_mul_input, Y4_mul_input, Y5_mul_input; 136 | integer Y6_mul_input, Y7_mul_input, Y8_mul_input; 137 | integer Ti2_mul_input, Ti3_mul_input, Ti4_mul_input, Ti5_mul_input; 138 | integer Ti6_mul_input, Ti7_mul_input, Ti8_mul_input; 139 | 140 | always @(posedge clk) 141 | begin // DCT matrix values 142 | //0.3536 143 | T1 = 5793; 144 | //0.4904 145 | T21 = 8035; 146 | //0.4157 147 | T22 = 6811; 148 | //0.2778 149 | T23 = 4551; 150 | //0.0975 151 | T24 = 1598; 152 | //-0.0975 153 | T25 = -1598; 154 | //-0.2778 155 | T26 = -4551; 156 | //-0.4157 157 | T27 = -6811; 158 | //-0.4904 159 | T28 = -8035; 160 | //0.4619 161 | T31 = 7568; 162 | //0.1913 163 | T32 = 3135; 164 | //-0.1913 165 | T33 = -3135; 166 | //-0.4619 167 | T34 = -7568; 168 | //-0.3536 169 | T52 = -5793; 170 | end 171 | 172 | always @(posedge clk) 173 | begin // The inverse DCT matrix values 174 | Ti1 = 5793; 175 | //0.4904 176 | Ti21 = 8035; 177 | //0.4157 178 | Ti22 = 6811; 179 | //0.2778 180 | Ti23 = 4551; 181 | //0.0975 182 | Ti24 = 1598; 183 | //-0.0975 184 | Ti25 = -1598; 185 | //-0.2778 186 | Ti26 = -4551; 187 | //-0.4157 188 | Ti27 = -6811; 189 | //-0.4904 190 | Ti28 = -8035; 191 | //0.4619 192 | Ti31 = 7568; 193 | //0.1913 194 | Ti32 = 3135; 195 | //-0.1913 196 | Ti33 = -3135; 197 | //-0.4619 198 | Ti34 = -7568; 199 | //-0.3536 200 | Ti52 = -5793; 201 | end 202 | 203 | always @(posedge clk) 204 | begin 205 | if (reset) begin 206 | Z_temp_11 <= 0; Z_temp_12 <= 0; Z_temp_13 <= 0; Z_temp_14 <= 0; 207 | Z_temp_15 <= 0; Z_temp_16 <= 0; Z_temp_17 <= 0; Z_temp_18 <= 0; 208 | Z_temp_21 <= 0; Z_temp_22 <= 0; Z_temp_23 <= 0; Z_temp_24 <= 0; 209 | Z_temp_25 <= 0; Z_temp_26 <= 0; Z_temp_27 <= 0; Z_temp_28 <= 0; 210 | Z_temp_31 <= 0; Z_temp_32 <= 0; Z_temp_33 <= 0; Z_temp_34 <= 0; 211 | Z_temp_35 <= 0; Z_temp_36 <= 0; Z_temp_37 <= 0; Z_temp_38 <= 0; 212 | Z_temp_41 <= 0; Z_temp_42 <= 0; Z_temp_43 <= 0; Z_temp_44 <= 0; 213 | Z_temp_45 <= 0; Z_temp_46 <= 0; Z_temp_47 <= 0; Z_temp_48 <= 0; 214 | Z_temp_51 <= 0; Z_temp_52 <= 0; Z_temp_53 <= 0; Z_temp_54 <= 0; 215 | Z_temp_55 <= 0; Z_temp_56 <= 0; Z_temp_57 <= 0; Z_temp_58 <= 0; 216 | Z_temp_61 <= 0; Z_temp_62 <= 0; Z_temp_63 <= 0; Z_temp_64 <= 0; 217 | Z_temp_65 <= 0; Z_temp_66 <= 0; Z_temp_67 <= 0; Z_temp_68 <= 0; 218 | Z_temp_71 <= 0; Z_temp_72 <= 0; Z_temp_73 <= 0; Z_temp_74 <= 0; 219 | Z_temp_75 <= 0; Z_temp_76 <= 0; Z_temp_77 <= 0; Z_temp_78 <= 0; 220 | Z_temp_81 <= 0; Z_temp_82 <= 0; Z_temp_83 <= 0; Z_temp_84 <= 0; 221 | Z_temp_85 <= 0; Z_temp_86 <= 0; Z_temp_87 <= 0; Z_temp_88 <= 0; 222 | end 223 | else if (enable_1 & count_8) begin 224 | Z_temp_11 <= Y11_final_4 * Ti1; Z_temp_12 <= Y11_final_4 * Ti2_mul_input; 225 | Z_temp_13 <= Y11_final_4 * Ti3_mul_input; Z_temp_14 <= Y11_final_4 * Ti4_mul_input; 226 | Z_temp_15 <= Y11_final_4 * Ti5_mul_input; Z_temp_16 <= Y11_final_4 * Ti6_mul_input; 227 | Z_temp_17 <= Y11_final_4 * Ti7_mul_input; Z_temp_18 <= Y11_final_4 * Ti8_mul_input; 228 | Z_temp_21 <= Y21_final_2 * Ti1; Z_temp_22 <= Y21_final_2 * Ti2_mul_input; 229 | Z_temp_23 <= Y21_final_2 * Ti3_mul_input; Z_temp_24 <= Y21_final_2 * Ti4_mul_input; 230 | Z_temp_25 <= Y21_final_2 * Ti5_mul_input; Z_temp_26 <= Y21_final_2 * Ti6_mul_input; 231 | Z_temp_27 <= Y21_final_2 * Ti7_mul_input; Z_temp_28 <= Y21_final_2 * Ti8_mul_input; 232 | Z_temp_31 <= Y31_final_2 * Ti1; Z_temp_32 <= Y31_final_2 * Ti2_mul_input; 233 | Z_temp_33 <= Y31_final_2 * Ti3_mul_input; Z_temp_34 <= Y31_final_2 * Ti4_mul_input; 234 | Z_temp_35 <= Y31_final_2 * Ti5_mul_input; Z_temp_36 <= Y31_final_2 * Ti6_mul_input; 235 | Z_temp_37 <= Y31_final_2 * Ti7_mul_input; Z_temp_38 <= Y31_final_2 * Ti8_mul_input; 236 | Z_temp_41 <= Y41_final_2 * Ti1; Z_temp_42 <= Y41_final_2 * Ti2_mul_input; 237 | Z_temp_43 <= Y41_final_2 * Ti3_mul_input; Z_temp_44 <= Y41_final_2 * Ti4_mul_input; 238 | Z_temp_45 <= Y41_final_2 * Ti5_mul_input; Z_temp_46 <= Y41_final_2 * Ti6_mul_input; 239 | Z_temp_47 <= Y41_final_2 * Ti7_mul_input; Z_temp_48 <= Y41_final_2 * Ti8_mul_input; 240 | Z_temp_51 <= Y51_final_2 * Ti1; Z_temp_52 <= Y51_final_2 * Ti2_mul_input; 241 | Z_temp_53 <= Y51_final_2 * Ti3_mul_input; Z_temp_54 <= Y51_final_2 * Ti4_mul_input; 242 | Z_temp_55 <= Y51_final_2 * Ti5_mul_input; Z_temp_56 <= Y51_final_2 * Ti6_mul_input; 243 | Z_temp_57 <= Y51_final_2 * Ti7_mul_input; Z_temp_58 <= Y51_final_2 * Ti8_mul_input; 244 | Z_temp_61 <= Y61_final_2 * Ti1; Z_temp_62 <= Y61_final_2 * Ti2_mul_input; 245 | Z_temp_63 <= Y61_final_2 * Ti3_mul_input; Z_temp_64 <= Y61_final_2 * Ti4_mul_input; 246 | Z_temp_65 <= Y61_final_2 * Ti5_mul_input; Z_temp_66 <= Y61_final_2 * Ti6_mul_input; 247 | Z_temp_67 <= Y61_final_2 * Ti7_mul_input; Z_temp_68 <= Y61_final_2 * Ti8_mul_input; 248 | Z_temp_71 <= Y71_final_2 * Ti1; Z_temp_72 <= Y71_final_2 * Ti2_mul_input; 249 | Z_temp_73 <= Y71_final_2 * Ti3_mul_input; Z_temp_74 <= Y71_final_2 * Ti4_mul_input; 250 | Z_temp_75 <= Y71_final_2 * Ti5_mul_input; Z_temp_76 <= Y71_final_2 * Ti6_mul_input; 251 | Z_temp_77 <= Y71_final_2 * Ti7_mul_input; Z_temp_78 <= Y71_final_2 * Ti8_mul_input; 252 | Z_temp_81 <= Y81_final_2 * Ti1; Z_temp_82 <= Y81_final_2 * Ti2_mul_input; 253 | Z_temp_83 <= Y81_final_2 * Ti3_mul_input; Z_temp_84 <= Y81_final_2 * Ti4_mul_input; 254 | Z_temp_85 <= Y81_final_2 * Ti5_mul_input; Z_temp_86 <= Y81_final_2 * Ti6_mul_input; 255 | Z_temp_87 <= Y81_final_2 * Ti7_mul_input; Z_temp_88 <= Y81_final_2 * Ti8_mul_input; 256 | end 257 | end 258 | 259 | always @(posedge clk) 260 | begin 261 | if (rst) begin 262 | Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0; Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0; 263 | Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0; Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0; 264 | Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0; Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0; 265 | Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0; Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0; 266 | Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0; Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0; 267 | Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0; Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0; 268 | Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0; Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0; 269 | Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0; Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0; 270 | end 271 | else if (count_8 & count_of == 1) begin 272 | Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0; 273 | Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0; 274 | Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0; 275 | Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0; 276 | Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0; 277 | Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0; 278 | Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0; 279 | Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0; 280 | Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0; 281 | Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0; 282 | Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0; 283 | Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0; 284 | Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0; 285 | Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0; 286 | Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0; 287 | Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0; 288 | end 289 | else if (enable & count_9) begin 290 | Z11 <= Z_temp_11 + Z11; Z12 <= Z_temp_12 + Z12; Z13 <= Z_temp_13 + Z13; Z14 <= Z_temp_14 + Z14; 291 | Z15 <= Z_temp_15 + Z15; Z16 <= Z_temp_16 + Z16; Z17 <= Z_temp_17 + Z17; Z18 <= Z_temp_18 + Z18; 292 | Z21 <= Z_temp_21 + Z21; Z22 <= Z_temp_22 + Z22; Z23 <= Z_temp_23 + Z23; Z24 <= Z_temp_24 + Z24; 293 | Z25 <= Z_temp_25 + Z25; Z26 <= Z_temp_26 + Z26; Z27 <= Z_temp_27 + Z27; Z28 <= Z_temp_28 + Z28; 294 | Z31 <= Z_temp_31 + Z31; Z32 <= Z_temp_32 + Z32; Z33 <= Z_temp_33 + Z33; Z34 <= Z_temp_34 + Z34; 295 | Z35 <= Z_temp_35 + Z35; Z36 <= Z_temp_36 + Z36; Z37 <= Z_temp_37 + Z37; Z38 <= Z_temp_38 + Z38; 296 | Z41 <= Z_temp_41 + Z41; Z42 <= Z_temp_42 + Z42; Z43 <= Z_temp_43 + Z43; Z44 <= Z_temp_44 + Z44; 297 | Z45 <= Z_temp_45 + Z45; Z46 <= Z_temp_46 + Z46; Z47 <= Z_temp_47 + Z47; Z48 <= Z_temp_48 + Z48; 298 | Z51 <= Z_temp_51 + Z51; Z52 <= Z_temp_52 + Z52; Z53 <= Z_temp_53 + Z53; Z54 <= Z_temp_54 + Z54; 299 | Z55 <= Z_temp_55 + Z55; Z56 <= Z_temp_56 + Z56; Z57 <= Z_temp_57 + Z57; Z58 <= Z_temp_58 + Z58; 300 | Z61 <= Z_temp_61 + Z61; Z62 <= Z_temp_62 + Z62; Z63 <= Z_temp_63 + Z63; Z64 <= Z_temp_64 + Z64; 301 | Z65 <= Z_temp_65 + Z65; Z66 <= Z_temp_66 + Z66; Z67 <= Z_temp_67 + Z67; Z68 <= Z_temp_68 + Z68; 302 | Z71 <= Z_temp_71 + Z71; Z72 <= Z_temp_72 + Z72; Z73 <= Z_temp_73 + Z73; Z74 <= Z_temp_74 + Z74; 303 | Z75 <= Z_temp_75 + Z75; Z76 <= Z_temp_76 + Z76; Z77 <= Z_temp_77 + Z77; Z78 <= Z_temp_78 + Z78; 304 | Z81 <= Z_temp_81 + Z81; Z82 <= Z_temp_82 + Z82; Z83 <= Z_temp_83 + Z83; Z84 <= Z_temp_84 + Z84; 305 | Z85 <= Z_temp_85 + Z85; Z86 <= Z_temp_86 + Z86; Z87 <= Z_temp_87 + Z87; Z88 <= Z_temp_88 + Z88; 306 | end 307 | end 308 | 309 | always @(posedge clk) 310 | begin 311 | if (rst) begin 312 | Z11_final <= 0; Z12_final <= 0; Z13_final <= 0; Z14_final <= 0; 313 | Z15_final <= 0; Z16_final <= 0; Z17_final <= 0; Z18_final <= 0; 314 | Z21_final <= 0; Z22_final <= 0; Z23_final <= 0; Z24_final <= 0; 315 | Z25_final <= 0; Z26_final <= 0; Z27_final <= 0; Z28_final <= 0; 316 | Z31_final <= 0; Z32_final <= 0; Z33_final <= 0; Z34_final <= 0; 317 | Z35_final <= 0; Z36_final <= 0; Z37_final <= 0; Z38_final <= 0; 318 | Z41_final <= 0; Z42_final <= 0; Z43_final <= 0; Z44_final <= 0; 319 | Z45_final <= 0; Z46_final <= 0; Z47_final <= 0; Z48_final <= 0; 320 | Z51_final <= 0; Z52_final <= 0; Z53_final <= 0; Z54_final <= 0; 321 | Z55_final <= 0; Z56_final <= 0; Z57_final <= 0; Z58_final <= 0; 322 | Z61_final <= 0; Z62_final <= 0; Z63_final <= 0; Z64_final <= 0; 323 | Z65_final <= 0; Z66_final <= 0; Z67_final <= 0; Z68_final <= 0; 324 | Z71_final <= 0; Z72_final <= 0; Z73_final <= 0; Z74_final <= 0; 325 | Z75_final <= 0; Z76_final <= 0; Z77_final <= 0; Z78_final <= 0; 326 | Z81_final <= 0; Z82_final <= 0; Z83_final <= 0; Z84_final <= 0; 327 | Z85_final <= 0; Z86_final <= 0; Z87_final <= 0; Z88_final <= 0; 328 | end 329 | else if (count_10 & count_of == 0) begin 330 | Z11_final <= Z11[15] ? Z11[26:16] + 1 : Z11[26:16]; 331 | Z12_final <= Z12[15] ? Z12[26:16] + 1 : Z12[26:16]; 332 | Z13_final <= Z13[15] ? Z13[26:16] + 1 : Z13[26:16]; 333 | Z14_final <= Z14[15] ? Z14[26:16] + 1 : Z14[26:16]; 334 | Z15_final <= Z15[15] ? Z15[26:16] + 1 : Z15[26:16]; 335 | Z16_final <= Z16[15] ? Z16[26:16] + 1 : Z16[26:16]; 336 | Z17_final <= Z17[15] ? Z17[26:16] + 1 : Z17[26:16]; 337 | Z18_final <= Z18[15] ? Z18[26:16] + 1 : Z18[26:16]; 338 | Z21_final <= Z21[15] ? Z21[26:16] + 1 : Z21[26:16]; 339 | Z22_final <= Z22[15] ? Z22[26:16] + 1 : Z22[26:16]; 340 | Z23_final <= Z23[15] ? Z23[26:16] + 1 : Z23[26:16]; 341 | Z24_final <= Z24[15] ? Z24[26:16] + 1 : Z24[26:16]; 342 | Z25_final <= Z25[15] ? Z25[26:16] + 1 : Z25[26:16]; 343 | Z26_final <= Z26[15] ? Z26[26:16] + 1 : Z26[26:16]; 344 | Z27_final <= Z27[15] ? Z27[26:16] + 1 : Z27[26:16]; 345 | Z28_final <= Z28[15] ? Z28[26:16] + 1 : Z28[26:16]; 346 | Z31_final <= Z31[15] ? Z31[26:16] + 1 : Z31[26:16]; 347 | Z32_final <= Z32[15] ? Z32[26:16] + 1 : Z32[26:16]; 348 | Z33_final <= Z33[15] ? Z33[26:16] + 1 : Z33[26:16]; 349 | Z34_final <= Z34[15] ? Z34[26:16] + 1 : Z34[26:16]; 350 | Z35_final <= Z35[15] ? Z35[26:16] + 1 : Z35[26:16]; 351 | Z36_final <= Z36[15] ? Z36[26:16] + 1 : Z36[26:16]; 352 | Z37_final <= Z37[15] ? Z37[26:16] + 1 : Z37[26:16]; 353 | Z38_final <= Z38[15] ? Z38[26:16] + 1 : Z38[26:16]; 354 | Z41_final <= Z41[15] ? Z41[26:16] + 1 : Z41[26:16]; 355 | Z42_final <= Z42[15] ? Z42[26:16] + 1 : Z42[26:16]; 356 | Z43_final <= Z43[15] ? Z43[26:16] + 1 : Z43[26:16]; 357 | Z44_final <= Z44[15] ? Z44[26:16] + 1 : Z44[26:16]; 358 | Z45_final <= Z45[15] ? Z45[26:16] + 1 : Z45[26:16]; 359 | Z46_final <= Z46[15] ? Z46[26:16] + 1 : Z46[26:16]; 360 | Z47_final <= Z47[15] ? Z47[26:16] + 1 : Z47[26:16]; 361 | Z48_final <= Z48[15] ? Z48[26:16] + 1 : Z48[26:16]; 362 | Z51_final <= Z51[15] ? Z51[26:16] + 1 : Z51[26:16]; 363 | Z52_final <= Z52[15] ? Z52[26:16] + 1 : Z52[26:16]; 364 | Z53_final <= Z53[15] ? Z53[26:16] + 1 : Z53[26:16]; 365 | Z54_final <= Z54[15] ? Z54[26:16] + 1 : Z54[26:16]; 366 | Z55_final <= Z55[15] ? Z55[26:16] + 1 : Z55[26:16]; 367 | Z56_final <= Z56[15] ? Z56[26:16] + 1 : Z56[26:16]; 368 | Z57_final <= Z57[15] ? Z57[26:16] + 1 : Z57[26:16]; 369 | Z58_final <= Z58[15] ? Z58[26:16] + 1 : Z58[26:16]; 370 | Z61_final <= Z61[15] ? Z61[26:16] + 1 : Z61[26:16]; 371 | Z62_final <= Z62[15] ? Z62[26:16] + 1 : Z62[26:16]; 372 | Z63_final <= Z63[15] ? Z63[26:16] + 1 : Z63[26:16]; 373 | Z64_final <= Z64[15] ? Z64[26:16] + 1 : Z64[26:16]; 374 | Z65_final <= Z65[15] ? Z65[26:16] + 1 : Z65[26:16]; 375 | Z66_final <= Z66[15] ? Z66[26:16] + 1 : Z66[26:16]; 376 | Z67_final <= Z67[15] ? Z67[26:16] + 1 : Z67[26:16]; 377 | Z68_final <= Z68[15] ? Z68[26:16] + 1 : Z68[26:16]; 378 | Z71_final <= Z71[15] ? Z71[26:16] + 1 : Z71[26:16]; 379 | Z72_final <= Z72[15] ? Z72[26:16] + 1 : Z72[26:16]; 380 | Z73_final <= Z73[15] ? Z73[26:16] + 1 : Z73[26:16]; 381 | Z74_final <= Z74[15] ? Z74[26:16] + 1 : Z74[26:16]; 382 | Z75_final <= Z75[15] ? Z75[26:16] + 1 : Z75[26:16]; 383 | Z76_final <= Z76[15] ? Z76[26:16] + 1 : Z76[26:16]; 384 | Z77_final <= Z77[15] ? Z77[26:16] + 1 : Z77[26:16]; 385 | Z78_final <= Z78[15] ? Z78[26:16] + 1 : Z78[26:16]; 386 | Z81_final <= Z81[15] ? Z81[26:16] + 1 : Z81[26:16]; 387 | Z82_final <= Z82[15] ? Z82[26:16] + 1 : Z82[26:16]; 388 | Z83_final <= Z83[15] ? Z83[26:16] + 1 : Z83[26:16]; 389 | Z84_final <= Z84[15] ? Z84[26:16] + 1 : Z84[26:16]; 390 | Z85_final <= Z85[15] ? Z85[26:16] + 1 : Z85[26:16]; 391 | Z86_final <= Z86[15] ? Z86[26:16] + 1 : Z86[26:16]; 392 | Z87_final <= Z87[15] ? Z87[26:16] + 1 : Z87[26:16]; 393 | Z88_final <= Z88[15] ? Z88[26:16] + 1 : Z88[26:16]; 394 | end 395 | end 396 | 397 | // output_enable signals the next block, the quantizer, that the input data is ready 398 | /*always @(posedge clk) 399 | begin 400 | if (rst) 401 | output_enable <= 0; 402 | else if (!enable_1) 403 | output_enable <= 0; 404 | else if (count_10 == 0 | count_of) 405 | output_enable <= 0; 406 | else if (count_10 & count_of == 0) 407 | output_enable <= 1; 408 | end*/ 409 | 410 | always @(posedge clk) 411 | begin 412 | if (rst) 413 | Y_temp_11 <= 0; 414 | else if (enable) 415 | Y_temp_11 <= data_in * T1; 416 | end 417 | 418 | always @(posedge clk) 419 | begin 420 | if (rst) 421 | Y11 <= 0; 422 | else if (count == 1 & enable == 1) 423 | Y11 <= Y_temp_11; 424 | else if (enable) 425 | Y11 <= Y_temp_11 + Y11; 426 | end 427 | 428 | always @(posedge clk) 429 | begin 430 | if (rst) begin 431 | Y_temp_21 <= 0; 432 | Y_temp_31 <= 0; 433 | Y_temp_41 <= 0; 434 | Y_temp_51 <= 0; 435 | Y_temp_61 <= 0; 436 | Y_temp_71 <= 0; 437 | Y_temp_81 <= 0; 438 | end 439 | else if (!enable_1) begin 440 | Y_temp_21 <= 0; 441 | Y_temp_31 <= 0; 442 | Y_temp_41 <= 0; 443 | Y_temp_51 <= 0; 444 | Y_temp_61 <= 0; 445 | Y_temp_71 <= 0; 446 | Y_temp_81 <= 0; 447 | end 448 | else if (enable_1) begin 449 | Y_temp_21 <= data_1 * Y2_mul_input; 450 | Y_temp_31 <= data_1 * Y3_mul_input; 451 | Y_temp_41 <= data_1 * Y4_mul_input; 452 | Y_temp_51 <= data_1 * Y5_mul_input; 453 | Y_temp_61 <= data_1 * Y6_mul_input; 454 | Y_temp_71 <= data_1 * Y7_mul_input; 455 | Y_temp_81 <= data_1 * Y8_mul_input; 456 | end 457 | end 458 | 459 | always @(posedge clk) 460 | begin 461 | if (rst) begin 462 | Y21 <= 0; 463 | Y31 <= 0; 464 | Y41 <= 0; 465 | Y51 <= 0; 466 | Y61 <= 0; 467 | Y71 <= 0; 468 | Y81 <= 0; 469 | end 470 | else if (!enable_1) begin 471 | Y21 <= 0; 472 | Y31 <= 0; 473 | Y41 <= 0; 474 | Y51 <= 0; 475 | Y61 <= 0; 476 | Y71 <= 0; 477 | Y81 <= 0; 478 | end 479 | else if (enable_1) begin 480 | Y21 <= Y_temp_21 + Y21; 481 | Y31 <= Y_temp_31 + Y31; 482 | Y41 <= Y_temp_41 + Y41; 483 | Y51 <= Y_temp_51 + Y51; 484 | Y61 <= Y_temp_61 + Y61; 485 | Y71 <= Y_temp_71 + Y71; 486 | Y81 <= Y_temp_81 + Y81; 487 | end 488 | end 489 | 490 | always @(posedge clk) 491 | begin 492 | if (rst) begin 493 | count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0; 494 | count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0; 495 | count_10 <= 0; 496 | end 497 | else if (!enable) begin 498 | count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0; 499 | count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0; 500 | count_10 <= 0; 501 | end 502 | else if (enable) begin 503 | count <= count + 1; count_3 <= count_1; count_4 <= count_3; 504 | count_5 <= count_4; count_6 <= count_5; count_7 <= count_6; 505 | count_8 <= count_7; count_9 <= count_8; count_10 <= count_9; 506 | end 507 | end 508 | 509 | always @(posedge clk) 510 | begin 511 | if (rst) begin 512 | count_1 <= 0; 513 | end 514 | else if (count != 7 | !enable) begin 515 | count_1 <= 0; 516 | end 517 | else if (count == 7) begin 518 | count_1 <= 1; 519 | end 520 | end 521 | 522 | always @(posedge clk) 523 | begin 524 | if (rst) begin 525 | count_of <= 0; 526 | count_of_copy <= 0; 527 | end 528 | else if (!enable) begin 529 | count_of <= 0; 530 | count_of_copy <= 0; 531 | end 532 | else if (count_1 == 1) begin 533 | count_of <= count_of + 1; 534 | count_of_copy <= count_of_copy + 1; 535 | end 536 | end 537 | 538 | always @(posedge clk) 539 | begin 540 | if (rst) begin 541 | Y11_final <= 0; 542 | end 543 | else if (count_3 & enable_1) begin 544 | Y11_final <= Y11 - 25'd5932032; 545 | /* The Y values weren't centered on 0 before doing the DCT 546 | 128 needs to be subtracted from each Y value before, or in this 547 | case, 362 is subtracted from the total, because this is the 548 | total obtained by subtracting 128 from each element 549 | and then multiplying by the weight 550 | assigned by the DCT matrix : 128*8*5793 = 5932032 551 | This is only needed for the first row, the values in the rest of 552 | the rows add up to 0 */ 553 | end 554 | end 555 | 556 | 557 | always @(posedge clk) 558 | begin 559 | if (rst) begin 560 | Y21_final <= 0; Y21_final_prev <= 0; 561 | Y31_final <= 0; Y31_final_prev <= 0; 562 | Y41_final <= 0; Y41_final_prev <= 0; 563 | Y51_final <= 0; Y51_final_prev <= 0; 564 | Y61_final <= 0; Y61_final_prev <= 0; 565 | Y71_final <= 0; Y71_final_prev <= 0; 566 | Y81_final <= 0; Y81_final_prev <= 0; 567 | end 568 | else if (!enable_1) begin 569 | Y21_final <= 0; Y21_final_prev <= 0; 570 | Y31_final <= 0; Y31_final_prev <= 0; 571 | Y41_final <= 0; Y41_final_prev <= 0; 572 | Y51_final <= 0; Y51_final_prev <= 0; 573 | Y61_final <= 0; Y61_final_prev <= 0; 574 | Y71_final <= 0; Y71_final_prev <= 0; 575 | Y81_final <= 0; Y81_final_prev <= 0; 576 | end 577 | else if (count_4 & enable_1) begin 578 | Y21_final <= Y21; Y21_final_prev <= Y21_final; 579 | Y31_final <= Y31; Y31_final_prev <= Y31_final; 580 | Y41_final <= Y41; Y41_final_prev <= Y41_final; 581 | Y51_final <= Y51; Y51_final_prev <= Y51_final; 582 | Y61_final <= Y61; Y61_final_prev <= Y61_final; 583 | Y71_final <= Y71; Y71_final_prev <= Y71_final; 584 | Y81_final <= Y81; Y81_final_prev <= Y81_final; 585 | end 586 | end 587 | 588 | always @(posedge clk) 589 | begin 590 | if (rst) begin 591 | Y21_final_diff <= 0; Y31_final_diff <= 0; 592 | Y41_final_diff <= 0; Y51_final_diff <= 0; 593 | Y61_final_diff <= 0; Y71_final_diff <= 0; 594 | Y81_final_diff <= 0; 595 | end 596 | else if (count_5 & enable_1) begin 597 | Y21_final_diff <= Y21_final - Y21_final_prev; 598 | Y31_final_diff <= Y31_final - Y31_final_prev; 599 | Y41_final_diff <= Y41_final - Y41_final_prev; 600 | Y51_final_diff <= Y51_final - Y51_final_prev; 601 | Y61_final_diff <= Y61_final - Y61_final_prev; 602 | Y71_final_diff <= Y71_final - Y71_final_prev; 603 | Y81_final_diff <= Y81_final - Y81_final_prev; 604 | end 605 | end 606 | always @(posedge clk) 607 | begin 608 | case (count) 609 | 3'b000: Y2_mul_input <= T21; 610 | 3'b001: Y2_mul_input <= T22; 611 | 3'b010: Y2_mul_input <= T23; 612 | 3'b011: Y2_mul_input <= T24; 613 | 3'b100: Y2_mul_input <= T25; 614 | 3'b101: Y2_mul_input <= T26; 615 | 3'b110: Y2_mul_input <= T27; 616 | 3'b111: Y2_mul_input <= T28; 617 | endcase 618 | end 619 | 620 | always @(posedge clk) 621 | begin 622 | case (count) 623 | 3'b000: Y3_mul_input <= T31; 624 | 3'b001: Y3_mul_input <= T32; 625 | 3'b010: Y3_mul_input <= T33; 626 | 3'b011: Y3_mul_input <= T34; 627 | 3'b100: Y3_mul_input <= T34; 628 | 3'b101: Y3_mul_input <= T33; 629 | 3'b110: Y3_mul_input <= T32; 630 | 3'b111: Y3_mul_input <= T31; 631 | endcase 632 | end 633 | 634 | always @(posedge clk) 635 | begin 636 | case (count) 637 | 3'b000: Y4_mul_input <= T22; 638 | 3'b001: Y4_mul_input <= T25; 639 | 3'b010: Y4_mul_input <= T28; 640 | 3'b011: Y4_mul_input <= T26; 641 | 3'b100: Y4_mul_input <= T23; 642 | 3'b101: Y4_mul_input <= T21; 643 | 3'b110: Y4_mul_input <= T24; 644 | 3'b111: Y4_mul_input <= T27; 645 | endcase 646 | end 647 | 648 | always @(posedge clk) 649 | begin 650 | case (count) 651 | 3'b000: Y5_mul_input <= T1; 652 | 3'b001: Y5_mul_input <= T52; 653 | 3'b010: Y5_mul_input <= T52; 654 | 3'b011: Y5_mul_input <= T1; 655 | 3'b100: Y5_mul_input <= T1; 656 | 3'b101: Y5_mul_input <= T52; 657 | 3'b110: Y5_mul_input <= T52; 658 | 3'b111: Y5_mul_input <= T1; 659 | endcase 660 | end 661 | 662 | always @(posedge clk) 663 | begin 664 | case (count) 665 | 3'b000: Y6_mul_input <= T23; 666 | 3'b001: Y6_mul_input <= T28; 667 | 3'b010: Y6_mul_input <= T24; 668 | 3'b011: Y6_mul_input <= T22; 669 | 3'b100: Y6_mul_input <= T27; 670 | 3'b101: Y6_mul_input <= T25; 671 | 3'b110: Y6_mul_input <= T21; 672 | 3'b111: Y6_mul_input <= T26; 673 | endcase 674 | end 675 | 676 | always @(posedge clk) 677 | begin 678 | case (count) 679 | 3'b000: Y7_mul_input <= T32; 680 | 3'b001: Y7_mul_input <= T34; 681 | 3'b010: Y7_mul_input <= T31; 682 | 3'b011: Y7_mul_input <= T33; 683 | 3'b100: Y7_mul_input <= T33; 684 | 3'b101: Y7_mul_input <= T31; 685 | 3'b110: Y7_mul_input <= T34; 686 | 3'b111: Y7_mul_input <= T32; 687 | endcase 688 | end 689 | 690 | always @(posedge clk) 691 | begin 692 | case (count) 693 | 3'b000: Y8_mul_input <= T24; 694 | 3'b001: Y8_mul_input <= T26; 695 | 3'b010: Y8_mul_input <= T22; 696 | 3'b011: Y8_mul_input <= T28; 697 | 3'b100: Y8_mul_input <= T21; 698 | 3'b101: Y8_mul_input <= T27; 699 | 3'b110: Y8_mul_input <= T23; 700 | 3'b111: Y8_mul_input <= T25; 701 | endcase 702 | end 703 | 704 | // Inverse DCT matrix entries 705 | always @(posedge clk) 706 | begin 707 | case (count_of_copy) 708 | 3'b000: Ti2_mul_input <= Ti28; 709 | 3'b001: Ti2_mul_input <= Ti21; 710 | 3'b010: Ti2_mul_input <= Ti22; 711 | 3'b011: Ti2_mul_input <= Ti23; 712 | 3'b100: Ti2_mul_input <= Ti24; 713 | 3'b101: Ti2_mul_input <= Ti25; 714 | 3'b110: Ti2_mul_input <= Ti26; 715 | 3'b111: Ti2_mul_input <= Ti27; 716 | endcase 717 | end 718 | 719 | always @(posedge clk) 720 | begin 721 | case (count_of_copy) 722 | 3'b000: Ti3_mul_input <= Ti31; 723 | 3'b001: Ti3_mul_input <= Ti31; 724 | 3'b010: Ti3_mul_input <= Ti32; 725 | 3'b011: Ti3_mul_input <= Ti33; 726 | 3'b100: Ti3_mul_input <= Ti34; 727 | 3'b101: Ti3_mul_input <= Ti34; 728 | 3'b110: Ti3_mul_input <= Ti33; 729 | 3'b111: Ti3_mul_input <= Ti32; 730 | endcase 731 | end 732 | 733 | always @(posedge clk) 734 | begin 735 | case (count_of_copy) 736 | 3'b000: Ti4_mul_input <= Ti27; 737 | 3'b001: Ti4_mul_input <= Ti22; 738 | 3'b010: Ti4_mul_input <= Ti25; 739 | 3'b011: Ti4_mul_input <= Ti28; 740 | 3'b100: Ti4_mul_input <= Ti26; 741 | 3'b101: Ti4_mul_input <= Ti23; 742 | 3'b110: Ti4_mul_input <= Ti21; 743 | 3'b111: Ti4_mul_input <= Ti24; 744 | endcase 745 | end 746 | 747 | always @(posedge clk) 748 | begin 749 | case (count_of_copy) 750 | 3'b000: Ti5_mul_input <= Ti1; 751 | 3'b001: Ti5_mul_input <= Ti1; 752 | 3'b010: Ti5_mul_input <= Ti52; 753 | 3'b011: Ti5_mul_input <= Ti52; 754 | 3'b100: Ti5_mul_input <= Ti1; 755 | 3'b101: Ti5_mul_input <= Ti1; 756 | 3'b110: Ti5_mul_input <= Ti52; 757 | 3'b111: Ti5_mul_input <= Ti52; 758 | endcase 759 | end 760 | 761 | always @(posedge clk) 762 | begin 763 | case (count_of_copy) 764 | 3'b000: Ti6_mul_input <= Ti26; 765 | 3'b001: Ti6_mul_input <= Ti23; 766 | 3'b010: Ti6_mul_input <= Ti28; 767 | 3'b011: Ti6_mul_input <= Ti24; 768 | 3'b100: Ti6_mul_input <= Ti22; 769 | 3'b101: Ti6_mul_input <= Ti27; 770 | 3'b110: Ti6_mul_input <= Ti25; 771 | 3'b111: Ti6_mul_input <= Ti21; 772 | endcase 773 | end 774 | 775 | always @(posedge clk) 776 | begin 777 | case (count_of_copy) 778 | 3'b000: Ti7_mul_input <= Ti32; 779 | 3'b001: Ti7_mul_input <= Ti32; 780 | 3'b010: Ti7_mul_input <= Ti34; 781 | 3'b011: Ti7_mul_input <= Ti31; 782 | 3'b100: Ti7_mul_input <= Ti33; 783 | 3'b101: Ti7_mul_input <= Ti33; 784 | 3'b110: Ti7_mul_input <= Ti31; 785 | 3'b111: Ti7_mul_input <= Ti34; 786 | endcase 787 | end 788 | 789 | always @(posedge clk) 790 | begin 791 | case (count_of_copy) 792 | 3'b000: Ti8_mul_input <= Ti25; 793 | 3'b001: Ti8_mul_input <= Ti24; 794 | 3'b010: Ti8_mul_input <= Ti26; 795 | 3'b011: Ti8_mul_input <= Ti22; 796 | 3'b100: Ti8_mul_input <= Ti28; 797 | 3'b101: Ti8_mul_input <= Ti21; 798 | 3'b110: Ti8_mul_input <= Ti27; 799 | 3'b111: Ti8_mul_input <= Ti23; 800 | endcase 801 | end 802 | 803 | // Rounding stage 804 | always @(posedge clk) 805 | begin 806 | if (rst) begin 807 | data_1 <= 0; 808 | Y11_final_1 <= 0; Y21_final_1 <= 0; Y31_final_1 <= 0; Y41_final_1 <= 0; 809 | Y51_final_1 <= 0; Y61_final_1 <= 0; Y71_final_1 <= 0; Y81_final_1 <= 0; 810 | Y11_final_2 <= 0; Y21_final_2 <= 0; Y31_final_2 <= 0; Y41_final_2 <= 0; 811 | Y51_final_2 <= 0; Y61_final_2 <= 0; Y71_final_2 <= 0; Y81_final_2 <= 0; 812 | Y11_final_3 <= 0; Y11_final_4 <= 0; 813 | end 814 | else if (enable) begin 815 | data_1 <= data_in; 816 | Y11_final_1 <= Y11_final[11] ? Y11_final[24:12] + 1 : Y11_final[24:12]; 817 | Y11_final_2[31:13] <= Y11_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; 818 | Y11_final_2[12:0] <= Y11_final_1; 819 | // Need to sign extend Y11_final_1 and the other registers to store a negative 820 | // number as a twos complement number. If you don't sign extend, then a negative number 821 | // will be stored incorrectly as a positive number. For example, -215 would be stored 822 | // as 1833 without sign extending 823 | Y11_final_3 <= Y11_final_2; 824 | Y11_final_4 <= Y11_final_3; 825 | Y21_final_1 <= Y21_final_diff[11] ? Y21_final_diff[24:12] + 1 : Y21_final_diff[24:12]; 826 | Y21_final_2[31:13] <= Y21_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; 827 | Y21_final_2[12:0] <= Y21_final_1; 828 | Y31_final_1 <= Y31_final_diff[11] ? Y31_final_diff[24:12] + 1 : Y31_final_diff[24:12]; 829 | Y31_final_2[31:13] <= Y31_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; 830 | Y31_final_2[12:0] <= Y31_final_1; 831 | Y41_final_1 <= Y41_final_diff[11] ? Y41_final_diff[24:12] + 1 : Y41_final_diff[24:12]; 832 | Y41_final_2[31:13] <= Y41_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; 833 | Y41_final_2[12:0] <= Y41_final_1; 834 | Y51_final_1 <= Y51_final_diff[11] ? Y51_final_diff[24:12] + 1 : Y51_final_diff[24:12]; 835 | Y51_final_2[31:13] <= Y51_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; 836 | Y51_final_2[12:0] <= Y51_final_1; 837 | Y61_final_1 <= Y61_final_diff[11] ? Y61_final_diff[24:12] + 1 : Y61_final_diff[24:12]; 838 | Y61_final_2[31:13] <= Y61_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; 839 | Y61_final_2[12:0] <= Y61_final_1; 840 | Y71_final_1 <= Y71_final_diff[11] ? Y71_final_diff[24:12] + 1 : Y71_final_diff[24:12]; 841 | Y71_final_2[31:13] <= Y71_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; 842 | Y71_final_2[12:0] <= Y71_final_1; 843 | Y81_final_1 <= Y81_final_diff[11] ? Y81_final_diff[24:12] + 1 : Y81_final_diff[24:12]; 844 | Y81_final_2[31:13] <= Y81_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; 845 | Y81_final_2[12:0] <= Y81_final_1; 846 | // The bit in place 11 is the fraction part, for rounding purposes 847 | // if it is 1, then you need to add 1 to the bits in 24-12, 848 | // if bit 11 is 0, then the bits in 24-12 won't change 849 | end 850 | end 851 | 852 | always @(posedge clk) 853 | begin 854 | if (rst) begin 855 | enable_1 <= 0; 856 | end 857 | else begin 858 | enable_1 <= enable; 859 | end 860 | end 861 | 862 | endmodule 863 | 864 | 865 | endmodule 866 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/Matrix_Multiplier1_8X8.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:47:07 10/30/2017 7 | // Design Name: 8 | // Module Name: Matrix_Multiplier1_8X8 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Matrix_Multiplier1_8X8( 22 | //input [15:0] IMG_add_a, 23 | //input [15:0] IMG_add_b, 24 | // input [5:0] D_add_a, 25 | // input [5:0] D_add_b, 26 | //input [3:0] counter, 27 | output reg [31:0] DIMGtmp0, 28 | output reg [31:0] DIMGtmp1, 29 | output reg [31:0] DIMGtmp2, 30 | output reg [31:0] DIMGtmp3, 31 | output reg [31:0] DIMGtmp4, 32 | output reg [31:0] DIMGtmp5, 33 | output reg [31:0] DIMGtmp6, 34 | output reg [31:0] DIMGtmp7, 35 | output [3:0] counter, 36 | output [15:0] IMG_add_a, 37 | input clk 38 | ); 39 | 40 | wire [15:0] IMG_add_b; 41 | reg [15:0] tmp[7:0]; 42 | //wire [7:0] Douta, Doutb; 43 | wire [7:0] IMGouta, IMGoutb; 44 | wire [16:0] D[7:0][7:0]; 45 | reg[15:0] countertmp1 = 0, counter1 = 0, counter2 = 1; 46 | 47 | // wire [31:0] t1; 48 | // assign t1 = (D[0][1] * tmp[0]) + (D[1][1] * tmp[1]) + (D[2][1] * tmp[2]) + (D[3][1] * tmp[3]) + (D[4][1] * tmp[4]) 49 | // + (D[5][1] * tmp[5]) + (D[6][1] * tmp[6]) + (D[7][1] * tmp[7]); 50 | 51 | assign IMG_add_a = counter1; 52 | assign IMG_add_b = counter2; 53 | assign counter = countertmp1; 54 | 55 | assign D[0][0] = 16'b0000000001011010; 56 | assign D[0][1] = 16'b0000000001011010; 57 | assign D[0][2] = 16'b0000000001011010; 58 | assign D[0][3] = 16'b0000000001011010; 59 | assign D[0][4] = 16'b0000000001011010; 60 | assign D[0][5] = 16'b0000000001011010; 61 | assign D[0][7] = 16'b0000000001011010; 62 | assign D[0][6] = 16'b0000000001011010; 63 | 64 | assign D[1][0] = 16'b0000000001111101; 65 | assign D[1][1] = 16'b0000000001101010; 66 | assign D[1][2] = 16'b0000000001000111; 67 | assign D[1][3] = 16'b0000000000011000; 68 | assign D[1][4] = 16'b1111111111100111; 69 | assign D[1][5] = 16'b1111111110111000; 70 | assign D[1][7] = 16'b1111111110000010; 71 | assign D[1][6] = 16'b1111111110010101; 72 | 73 | assign D[2][0] = 16'b0000000001110110; 74 | assign D[2][1] = 16'b0000000000110000; 75 | assign D[2][2] = 16'b1111111111001111; 76 | assign D[2][3] = 16'b1111111110001001; 77 | assign D[2][4] = 16'b1111111110001001; 78 | assign D[2][5] = 16'b1111111111001111; 79 | assign D[2][7] = 16'b0000000001110110; 80 | assign D[2][6] = 16'b0000000000110000; 81 | 82 | assign D[3][0] = 16'b0000000001101010; 83 | assign D[3][1] = 16'b1111111111100111; 84 | assign D[3][2] = 16'b1111111110000010; 85 | assign D[3][3] = 16'b1111111110111000; 86 | assign D[3][4] = 16'b0000000001000111; 87 | assign D[3][5] = 16'b0000000001111101; 88 | assign D[3][7] = 16'b0000000001101010; 89 | assign D[3][6] = 16'b0000000000011000; 90 | 91 | 92 | assign D[4][0] = 16'b0000000001011010; 93 | assign D[4][1] = 16'b1111111110100101; 94 | assign D[4][2] = 16'b1111111110100101; 95 | assign D[4][3] = 16'b0000000001011010; 96 | assign D[4][4] = 16'b0000000001011010; 97 | assign D[4][5] = 16'b1111111110100101; 98 | assign D[4][6] = 16'b1111111110100101; 99 | assign D[4][7] = 16'b0000000001011010; 100 | 101 | assign D[5][0] = 16'b0000000001000111; 102 | assign D[5][1] = 16'b1111111110000010; 103 | assign D[5][2] = 16'b0000000000011000; 104 | assign D[5][3] = 16'b0000000001101010; 105 | assign D[5][4] = 16'b1111111110010101; 106 | assign D[5][5] = 16'b1111111111100111; 107 | assign D[5][6] = 16'b0000000001111101; 108 | assign D[5][7] = 16'b1111111110111000; 109 | 110 | assign D[6][0] = 16'b0000000000110000; 111 | assign D[6][1] = 16'b1111111110001001; 112 | assign D[6][2] = 16'b0000000001110110; 113 | assign D[6][3] = 16'b1111111111001111; 114 | assign D[6][4] = 16'b1111111111001111; 115 | assign D[6][5] = 16'b0000000001110110; 116 | assign D[6][6] = 16'b1111111110001001; 117 | assign D[6][7] = 16'b0000000000110000; 118 | 119 | assign D[7][0] = 16'b0000000000011000; 120 | assign D[7][1] = 16'b1111111110111000; 121 | assign D[7][2] = 16'b0000000001101010; 122 | assign D[7][3] = 16'b1111101100011000; 123 | assign D[7][4] = 16'b0000000001111101; 124 | assign D[7][5] = 16'b1111111110010101; 125 | assign D[7][6] = 16'b0000000001000111; 126 | assign D[7][7] = 16'b1111111111100111; 127 | 128 | 129 | IMG_ROM IMG ( 130 | .clka(clk), // input clka 131 | .addra(IMG_add_a), // input [15 : 0] addra 132 | .douta(IMGouta), // output [7 : 0] douta 133 | .clkb(clk), // input clkb 134 | .addrb(IMG_add_b), // input [15 : 0] addrb 135 | .doutb(IMGoutb) // output [7 : 0] doutb 136 | ); 137 | 138 | assign a = (counter<<1); 139 | /* 140 | D_ROM D ( 141 | .clka(clk), // input clka 142 | .addra(D_add_a), // input [5 : 0] addra 143 | .douta(Douta), // output [15 : 0] douta 144 | .clkb(clk), // input clkb 145 | .addrb(D_add_b), // input [5 : 0] addrb 146 | .doutb(Doutb) // output [15 : 0] doutb 147 | );*/ 148 | 149 | 150 | // assign D_add_a = counter3; 151 | // assign D_add_b = counter4; 152 | 153 | always@(posedge clk) 154 | begin 155 | if((counter<<1) - 2 >= 0) 156 | begin 157 | tmp[(counter<<1) - 2] = {IMGouta, 8'b0000_0000}; 158 | tmp[(counter<<1) - 1] = {IMGoutb, 8'h00}; 159 | end 160 | if(counter == 4) 161 | begin 162 | DIMGtmp0 = (tmp[0] * D[0][0]) + (tmp[1] * D[1][0]) + (tmp[2] * D[2][0]) + (tmp[3] * D[3][0]) 163 | + (tmp[4] * D[4][0]) + (tmp[5] * D[5][0]) + (tmp[6] * D[6][0]) + (tmp[7] * D[7][0]); 164 | DIMGtmp1 = (tmp[0] * D[0][1]) + (tmp[1] * D[1][1]) + (tmp[2] * D[2][1]) + (tmp[3] * D[3][1]) 165 | + (tmp[4] * D[4][1]) + (tmp[5] * D[5][1]) + (tmp[6] * D[6][1]) + (tmp[7] * D[7][1]); 166 | DIMGtmp2 = (tmp[0] * D[0][2]) + (tmp[1] * D[1][2]) + (tmp[2] * D[2][2]) + (tmp[3] * D[3][2]) 167 | + (tmp[4] * D[4][2]) + (tmp[5] * D[5][2]) + (tmp[6] * D[6][2]) + (tmp[7] * D[7][2]); 168 | DIMGtmp3 = (tmp[0] * D[0][3]) + (tmp[1] * D[1][3]) + (tmp[2] * D[2][3]) + (tmp[3] * D[3][3]) 169 | + (tmp[4] * D[4][3]) + (tmp[5] * D[5][3]) + (tmp[6] * D[6][3]) + (tmp[7] * D[7][3]); 170 | DIMGtmp4 = (tmp[0] * D[0][4]) + (tmp[1] * D[1][4]) + (tmp[2] * D[2][4]) + (tmp[3] * D[3][4]) 171 | + (tmp[4] * D[4][4]) + (tmp[5] * D[5][4]) + (tmp[6] * D[6][4]) + (tmp[7] * D[7][4]); 172 | DIMGtmp5 = (tmp[0] * D[0][5]) + (tmp[1] * D[1][5]) + (tmp[2] * D[2][5]) + (tmp[3] * D[3][5]) 173 | + (tmp[4] * D[4][5]) + (tmp[5] * D[5][5]) + (tmp[6] * D[6][5]) + (tmp[7] * D[7][5]); 174 | DIMGtmp6 = (tmp[0] * D[0][6]) + (tmp[1] * D[1][6]) + (tmp[2] * D[2][6]) + (tmp[3] * D[3][6]) 175 | + (tmp[4] * D[4][6]) + (tmp[5] * D[5][6]) + (tmp[6] * D[6][6]) + (tmp[7] * D[7][6]); 176 | DIMGtmp7 = (tmp[0] * D[0][7]) + (tmp[1] * D[1][7]) + (tmp[2] * D[2][7]) + (tmp[3] * D[3][7]) 177 | + (tmp[4] * D[4][7]) + (tmp[5] * D[5][7]) + (tmp[6] * D[6][7]) + (tmp[7] * D[7][7]); 178 | 179 | // DIMG[IMG_add_a - 6] = DIMGtmp0[23:8]; 180 | // DIMG[IMG_add_b - 6] = DIMGtmp1[23:8]; 181 | // DIMG[IMG_add_a - 4] = DIMGtmp2[23:8]; 182 | // DIMG[IMG_add_b - 4] = DIMGtmp3[23:8]; 183 | // DIMG[IMG_add_a - 2] = DIMGtmp4[23:8]; 184 | // DIMG[IMG_add_b - 2] = DIMGtmp5[23:8]; 185 | // DIMG[IMG_add_a] = DIMGtmp6[23:8]; 186 | // DIMG[IMG_add_b] = DIMGtmp7[23:8]; 187 | end 188 | 189 | if(countertmp1 < 4) 190 | begin 191 | 192 | counter1 <= counter1 + 2; 193 | counter2 <= counter2 + 2; 194 | countertmp1 <= countertmp1 + 1; 195 | end 196 | 197 | if(countertmp1 == 4) 198 | begin 199 | 200 | countertmp1 <= 0; 201 | end 202 | // end 203 | 204 | end 205 | 206 | // always@(posedge clk) 207 | //begin 208 | // if(~hold) 209 | // begin 210 | // end 211 | endmodule 212 | 213 | /*module CounterMUl1( 214 | input clk 215 | ); 216 | reg[15:0] countertmp1 = 0, countertmp2 = 0, counter1, counter2; 217 | Matrix_Multiplier1_8X8(counter1, counter2, countertmp1, clk); 218 | 219 | always@(posedge clk) 220 | begin 221 | // if(~hold) 222 | // begin 223 | if(countertmp1 < 4) 224 | begin 225 | counter1 <= counter1 + 2; 226 | counter2 <= counter2 + 2; 227 | countertmp1 <= countertmp1 + 1; 228 | end 229 | 230 | if(countertmp1 == 4) 231 | begin 232 | countertmp1 <= 0; 233 | end 234 | // end 235 | end 236 | endmodule 237 | */ 238 | 239 | 240 | 241 | 242 | 243 | /* 244 | module Matrix_Multiplier1_8X8( 245 | input [15:0] IMG_add_a, 246 | input [15:0] IMG_add_b, 247 | // input [5:0] D_add_a, 248 | // input [5:0] D_add_b, 249 | input [3:0] counter, 250 | input clk 251 | ); 252 | 253 | reg [16:0] tmp[7:0]; 254 | //wire [7:0] Douta, Doutb; 255 | wire [8:0] IMGouta, IMGoutb; 256 | reg [15:0] DIMG[65536:0]; 257 | wire [16:0] D[7:0][7:0]; 258 | reg [32:0] DIMGtmp0, DIMGtmp1, DIMGtmp2, DIMGtmp3, DIMGtmp4, DIMGtmp5, DIMGtmp6, DIMGtmp7; 259 | 260 | 261 | assign D[0][0] = 16'b0000000001011010; 262 | assign D[0][1] = 16'b0000000001011010; 263 | assign D[0][2] = 16'b0000000001011010; 264 | assign D[0][3] = 16'b0000000001011010; 265 | assign D[0][4] = 16'b0000000001011010; 266 | assign D[0][5] = 16'b0000000001011010; 267 | assign D[0][7] = 16'b0000000001011010; 268 | assign D[0][6] = 16'b0000000001011010; 269 | 270 | assign D[1][0] = 16'b0000000001111101; 271 | assign D[1][1] = 16'b0000000001101010; 272 | assign D[1][2] = 16'b0000000001000111; 273 | assign D[1][3] = 16'b0000000000011000; 274 | assign D[1][4] = 16'b1111111111100111; 275 | assign D[1][5] = 16'b1111111110111000; 276 | assign D[1][7] = 16'b1111111110000010; 277 | assign D[1][6] = 16'b1111111110010101; 278 | 279 | assign D[2][0] = 16'b0000000001110110; 280 | assign D[2][1] = 16'b0000000000110000; 281 | assign D[2][2] = 16'b1111111111001111; 282 | assign D[2][3] = 16'b1111111110001001; 283 | assign D[2][4] = 16'b1111111110001001; 284 | assign D[2][5] = 16'b1111111111001111; 285 | assign D[2][7] = 16'b0000000001110110; 286 | assign D[2][6] = 16'b0000000000110000; 287 | 288 | assign D[3][0] = 16'b0000000001101010; 289 | assign D[3][1] = 16'b1111111111100111; 290 | assign D[3][2] = 16'b1111111110000010; 291 | assign D[3][3] = 16'b1111111110111000; 292 | assign D[3][4] = 16'b0000000001000111; 293 | assign D[3][5] = 16'b0000000001111101; 294 | assign D[3][7] = 16'b0000000001101010; 295 | assign D[3][6] = 16'b0000000000011000; 296 | 297 | 298 | assign D[4][0] = 16'b0000000001011010; 299 | assign D[4][1] = 16'b1111111110100101; 300 | assign D[4][2] = 16'b1111111110100101; 301 | assign D[4][3] = 16'b0000000001011010; 302 | assign D[4][4] = 16'b0000000001011010; 303 | assign D[4][5] = 16'b1111111110100101; 304 | assign D[4][6] = 16'b1111111110100101; 305 | assign D[4][7] = 16'b0000000001011010; 306 | 307 | assign D[5][0] = 16'b0000000001000111; 308 | assign D[5][1] = 16'b1111111110000010; 309 | assign D[5][2] = 16'b0000000000011000; 310 | assign D[5][3] = 16'b0000000001101010; 311 | assign D[5][4] = 16'b1111111110010101; 312 | assign D[5][5] = 16'b1111111111100111; 313 | assign D[5][6] = 16'b0000000001111101; 314 | assign D[5][7] = 16'b1111111110111000; 315 | 316 | assign D[6][0] = 16'b0000000000110000; 317 | assign D[6][1] = 16'b1111111110001001; 318 | assign D[6][2] = 16'b0000000001110110; 319 | assign D[6][3] = 16'b1111111111001111; 320 | assign D[6][4] = 16'b1111111111001111; 321 | assign D[6][5] = 16'b0000000001110110; 322 | assign D[6][6] = 16'b1111111110001001; 323 | assign D[6][7] = 16'b0000000000110000; 324 | 325 | assign D[7][0] = 16'b0000000000011000; 326 | assign D[7][1] = 16'b1111111110111000; 327 | assign D[7][2] = 16'b0000000001101010; 328 | assign D[7][3] = 16'b1111101100011000; 329 | assign D[7][4] = 16'b0000000001111101; 330 | assign D[7][5] = 16'b1111111110010101; 331 | assign D[7][6] = 16'b0000000001000111; 332 | assign D[7][7] = 16'b1111111111100111; 333 | 334 | 335 | IMG_ROM IMG ( 336 | .clka(clk), // input clka 337 | .addra(IMG_add_a), // input [15 : 0] addra 338 | .douta(IMGouta), // output [7 : 0] douta 339 | .clkb(clk), // input clkb 340 | .addrb(IMG_add_b), // input [15 : 0] addrb 341 | .doutb(IMGoutb) // output [7 : 0] doutb 342 | ); 343 | 344 | 345 | 346 | // D_ROM D ( 347 | // .clka(clk), // input clka 348 | // .addra(D_add_a), // input [5 : 0] addra 349 | // .douta(Douta), // output [15 : 0] douta 350 | // .clkb(clk), // input clkb 351 | // .addrb(D_add_b), // input [5 : 0] addrb 352 | // .doutb(Doutb) // output [15 : 0] doutb 353 | // ); 354 | 355 | 356 | // assign D_add_a = counter3; 357 | // assign D_add_b = counter4; 358 | 359 | always@(posedge clk) 360 | begin 361 | if(counter < 4) 362 | begin 363 | tmp[(counter<<1)] = {IMGouta, 8'b0000_0000}; 364 | tmp[(counter<<1) + 1] = {IMGoutb, 8'h00}; 365 | end 366 | if(counter < 4 && counter == 3) 367 | begin 368 | DIMGtmp0 = (tmp[0] * D[0][0]) + (tmp[1] * D[1][0]) + (tmp[2] * D[2][0]) + (tmp[3] * D[3][0]) 369 | + (tmp[4] * D[4][0]) + (tmp[5] * D[5][0]) + (tmp[6] * D[6][0]) + (tmp[7] * D[7][0]); 370 | DIMGtmp1 = (tmp[0] * D[0][1]) + (tmp[1] * D[1][1]) + (tmp[2] * D[2][1]) + (tmp[3] * D[3][1]) 371 | + (tmp[4] * D[4][1]) + (tmp[5] * D[5][1]) + (tmp[6] * D[6][1]) + (tmp[7] * D[7][1]); 372 | DIMGtmp2 = (tmp[0] * D[0][2]) + (tmp[1] * D[1][2]) + (tmp[2] * D[2][2]) + (tmp[3] * D[3][2]) 373 | + (tmp[4] * D[4][2]) + (tmp[5] * D[5][2]) + (tmp[6] * D[6][2]) + (tmp[7] * D[7][2]); 374 | DIMGtmp3 = (tmp[0] * D[0][3]) + (tmp[1] * D[1][3]) + (tmp[2] * D[2][3]) + (tmp[3] * D[3][3]) 375 | + (tmp[4] * D[4][3]) + (tmp[5] * D[5][3]) + (tmp[6] * D[6][3]) + (tmp[7] * D[7][3]); 376 | DIMGtmp4 = (tmp[0] * D[0][4]) + (tmp[1] * D[1][4]) + (tmp[2] * D[2][4]) + (tmp[3] * D[3][4]) 377 | + (tmp[4] * D[4][4]) + (tmp[5] * D[5][4]) + (tmp[6] * D[6][4]) + (tmp[7] * D[7][4]); 378 | DIMGtmp5 = (tmp[0] * D[0][5]) + (tmp[1] * D[1][5]) + (tmp[2] * D[2][5]) + (tmp[3] * D[3][5]) 379 | + (tmp[4] * D[4][5]) + (tmp[5] * D[5][5]) + (tmp[6] * D[6][5]) + (tmp[7] * D[7][5]); 380 | DIMGtmp6 = (tmp[0] * D[0][6]) + (tmp[1] * D[1][6]) + (tmp[2] * D[2][6]) + (tmp[3] * D[3][6]) 381 | + (tmp[4] * D[4][6]) + (tmp[5] * D[5][6]) + (tmp[6] * D[6][6]) + (tmp[7] * D[7][6]); 382 | DIMGtmp7 = (tmp[0] * D[0][7]) + (tmp[1] * D[1][7]) + (tmp[2] * D[2][7]) + (tmp[3] * D[3][7]) 383 | + (tmp[4] * D[4][7]) + (tmp[5] * D[5][7]) + (tmp[6] * D[6][7]) + (tmp[7] * D[7][7]); 384 | 385 | DIMG[IMG_add_a - 6] = DIMGtmp0[23:8]; 386 | DIMG[IMG_add_a - 6] = DIMGtmp1[23:8]; 387 | DIMG[IMG_add_a - 4] = DIMGtmp2[23:8]; 388 | DIMG[IMG_add_a - 4] = DIMGtmp3[23:8]; 389 | DIMG[IMG_add_a - 2] = DIMGtmp4[23:8]; 390 | DIMG[IMG_add_a - 2] = DIMGtmp5[23:8]; 391 | DIMG[IMG_add_a] = DIMGtmp6[23:8]; 392 | DIMG[IMG_add_b] = DIMGtmp7[23:8]; 393 | end 394 | end 395 | 396 | endmodule 397 | */ -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/Mul_8x8_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 23:44:38 11/01/2017 8 | // Design Name: Multiplier_8x8 9 | // Module Name: C:/Users/Maharsh Suryawala/Desktop/Functions/IMG/Mul_8x8_tb.v 10 | // Project Name: IMG 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: Multiplier_8x8 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module Mul_8x8_tb; 26 | 27 | // Inputs 28 | reg F; 29 | reg [15:0] H; 30 | reg [15:0] D; 31 | 32 | // Instantiate the Unit Under Test (UUT) 33 | Multiplier_8x8 uut ( 34 | .F(F), 35 | .H(H), 36 | .D(D) 37 | ); 38 | 39 | initial begin 40 | // Initialize Inputs 41 | F = 0; 42 | H[0][0] = 0; 43 | D[0][0] = 0; 44 | 45 | // Wait 100 ns for global reset to finish 46 | #100; 47 | 48 | // Add stimulus here 49 | 50 | end 51 | 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/Multiplier_8x8.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:11:16 11/01/2017 7 | // Design Name: 8 | // Module Name: Multiplier_8x8 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Multiplier_8x8( 22 | F00, F01, F02, F03, F04, F05, F06, F07, 23 | F10, F11, F12, F13, F14, F15, F16, F17, 24 | F20, F21, F22, F23, F24, F25, F26, F27, 25 | F30, F31, F32, F33, F34, F35, F36, F37, 26 | F40, F41, F42, F43, F44, F45, F46, F47, 27 | F50, F51, F52, F53, F54, F55, F56, F57, 28 | F60, F61, F62, F63, F64, F65, F66, F67, 29 | F70, F71, F72, F73, F74, F75, F76, F77, 30 | 31 | D00, D01, D02, D03, D04, D05, D06, D07, 32 | D10, D11, D12, D13, D14, D15, D16, D17, 33 | D20, D21, D22, D23, D24, D25, D26, D27, 34 | D30, D31, D32, D33, D34, D35, D36, D37, 35 | D40, D41, D42, D43, D44, D45, D46, D47, 36 | D50, D51, D52, D53, D54, D55, D56, D57, 37 | D60, D61, D62, D63, D64, D65, D66, D67, 38 | D70, D71, D72, D73, D74, D75, D76, D77, 39 | 40 | H00, H01, H02, H03, H04, H05, H06, H07, 41 | H10, H11, H12, H13, H14, H15, H16, H17, 42 | H20, H21, H22, H23, H24, H25, H26, H27, 43 | H30, H31, H32, H33, H34, H35, H36, H37, 44 | H40, H41, H42, H43, H44, H45, H46, H47, 45 | H50, H51, H52, H53, H54, H55, H56, H57, 46 | H60, H61, H62, H63, H64, H65, H66, H67, 47 | H70, H71, H72, H73, H74, H75, H76, H77 48 | 49 | ); 50 | 51 | /*input[15:0] H[7:0][7:0]; 52 | input[15:0] [7:0][7:0]; 53 | output[15:0] F[7:0][7:0]; 54 | */ 55 | 56 | //D*H 57 | 58 | output[15:0] F00, F01, F02, F03, F04, F05, F06, F07; 59 | output[15:0] F10, F11, F12, F13, F14, F15, F16, F17; 60 | output[15:0] F20, F21, F22, F23, F24, F25, F26, F27; 61 | output[15:0] F30, F31, F32, F33, F34, F35, F36, F37; 62 | output[15:0] F40, F41, F42, F43, F44, F45, F46, F47; 63 | output[15:0] F50, F51, F52, F53, F54, F55, F56, F57; 64 | output[15:0] F60, F61, F62, F63, F64, F65, F66, F67; 65 | output[15:0] F70, F71, F72, F73, F74, F75, F76, F77; 66 | 67 | wire[31:0] tF00, tF01, tF02, tF03, tF04, tF05, tF06, tF07; 68 | wire[31:0] tF10, tF11, tF12, tF13, tF14, tF15, tF16, tF17; 69 | wire[31:0] tF20, tF21, tF22, tF23, tF24, tF25, tF26, tF27; 70 | wire[31:0] tF30, tF31, tF32, tF33, tF34, tF35, tF36, tF37; 71 | wire[31:0] tF40, tF41, tF42, tF43, tF44, tF45, tF46, tF47; 72 | wire[31:0] tF50, tF51, tF52, tF53, tF54, tF55, tF56, tF57; 73 | wire[31:0] tF60, tF61, tF62, tF63, tF64, tF65, tF66, tF67; 74 | wire[31:0] tF70, tF71, tF72, tF73, tF74, tF75, tF76, tF77; 75 | 76 | 77 | input[15:0] D00, D01, D02, D03, D04, D05, D06, D07; 78 | input[15:0] D10, D11, D12, D13, D14, D15, D16, D17; 79 | input[15:0] D20, D21, D22, D23, D24, D25, D26, D27; 80 | input[15:0] D30, D31, D32, D33, D34, D35, D36, D37; 81 | input[15:0] D40, D41, D42, D43, D44, D45, D46, D47; 82 | input[15:0] D50, D51, D52, D53, D54, D55, D56, D57; 83 | input[15:0] D60, D61, D62, D63, D64, D65, D66, D67; 84 | input[15:0] D70, D71, D72, D73, D74, D75, D76, D77; 85 | 86 | input[15:0] H00, H01, H02, H03, H04, H05, H06, H07; 87 | input[15:0] H10, H11, H12, H13, H14, H15, H16, H17; 88 | input[15:0] H20, H21, H22, H23, H24, H25, H26, H27; 89 | input[15:0] H30, H31, H32, H33, H34, H35, H36, H37; 90 | input[15:0] H40, H41, H42, H43, H44, H45, H46, H47; 91 | input[15:0] H50, H51, H52, H53, H54, H55, H56, H57; 92 | input[15:0] H60, H61, H62, H63, H64, H65, H66, H67; 93 | input[15:0] H70, H71, H72, H73, H74, H75, H76, H77; 94 | 95 | 96 | assign tF00= D00*H00 + D01*H10 + D02*H20 + D03*H30 + D04*H40 + D05*H50 + D06*H60 + D07*H70; 97 | assign tF01= D00*H01 + D01*H11 + D02*H21 + D03*H31 + D04*H41 + D05*H51 + D06*H61 + D07*H71; 98 | assign tF02= D00*H02 + D01*H12 + D02*H22 + D03*H32 + D04*H42 + D05*H52 + D06*H62 + D07*H72; 99 | assign tF03= D00*H03 + D01*H13 + D02*H23 + D03*H33 + D04*H43 + D05*H53 + D06*H63 + D07*H73; 100 | assign tF04= D00*H04 + D01*H14 + D02*H24 + D03*H34 + D04*H44 + D05*H54 + D06*H64 + D07*H74; 101 | assign tF05= D00*H05 + D01*H15 + D02*H25 + D03*H35 + D04*H45 + D05*H55 + D06*H65 + D07*H75; 102 | assign tF06= D00*H06 + D01*H16 + D02*H26 + D03*H36 + D04*H46 + D05*H56 + D06*H66 + D07*H76; 103 | assign tF07= D00*H07 + D01*H17 + D02*H27 + D03*H37 + D04*H47 + D05*H57 + D06*H67 + D07*H77; 104 | 105 | assign tF10= D10*H00 + D11*H10 + D12*H20 + D13*H30 + D14*H40 + D15*H50 + D16*H60 + D17*H70; 106 | assign tF11= D10*H01 + D11*H11 + D12*H21 + D13*H31 + D14*H41 + D15*H51 + D16*H61 + D17*H71; 107 | assign tF12= D10*H02 + D11*H12 + D12*H22 + D13*H32 + D14*H42 + D15*H52 + D16*H62 + D17*H72; 108 | assign tF13= D10*H03 + D11*H13 + D12*H23 + D13*H33 + D14*H43 + D15*H53 + D16*H63 + D17*H73; 109 | assign tF14= D10*H04 + D11*H14 + D12*H24 + D13*H34 + D14*H44 + D15*H54 + D16*H64 + D17*H74; 110 | assign tF15= D10*H05 + D11*H15 + D12*H25 + D13*H35 + D14*H45 + D15*H55 + D16*H65 + D17*H75; 111 | assign tF16= D10*H06 + D11*H16 + D12*H26 + D13*H36 + D14*H46 + D15*H56 + D16*H66 + D17*H76; 112 | assign tF17= D10*H07 + D11*H17 + D12*H27 + D13*H37 + D14*H47 + D15*H57 + D16*H67 + D17*H77; 113 | 114 | assign tF20= D20*H00 + D21*H10 + D22*H20 + D23*H30 + D24*H40 + D25*H50 + D26*H60 + D27*H70; 115 | assign tF21= D20*H01 + D21*H11 + D22*H21 + D23*H31 + D24*H41 + D25*H51 + D26*H61 + D27*H71; 116 | assign tF22= D20*H02 + D21*H12 + D22*H22 + D23*H32 + D24*H42 + D25*H52 + D26*H62 + D27*H72; 117 | assign tF23= D20*H03 + D21*H13 + D22*H23 + D23*H33 + D24*H43 + D25*H53 + D26*H63 + D27*H73; 118 | assign tF24= D20*H04 + D21*H14 + D22*H24 + D23*H34 + D24*H44 + D25*H54 + D26*H64 + D27*H74; 119 | assign tF25= D20*H05 + D21*H15 + D22*H25 + D23*H35 + D24*H45 + D25*H55 + D26*H65 + D27*H75; 120 | assign tF26= D20*H06 + D21*H16 + D22*H26 + D23*H36 + D24*H46 + D25*H56 + D26*H66 + D27*H76; 121 | assign tF27= D20*H07 + D21*H17 + D22*H27 + D23*H37 + D24*H47 + D25*H57 + D26*H67 + D27*H77; 122 | 123 | assign tF30= D30*H00 + D31*H10 + D32*H20 + D33*H30 + D34*H40 + D35*H50 + D36*H60 + D37*H70; 124 | assign tF31= D30*H01 + D31*H11 + D32*H21 + D33*H31 + D34*H41 + D35*H51 + D36*H61 + D37*H71; 125 | assign tF32= D30*H02 + D31*H12 + D32*H22 + D33*H32 + D34*H42 + D35*H52 + D36*H62 + D37*H72; 126 | assign tF33= D30*H03 + D31*H13 + D32*H23 + D33*H33 + D34*H43 + D35*H53 + D36*H63 + D37*H73; 127 | assign tF34= D30*H04 + D31*H14 + D32*H24 + D33*H34 + D34*H44 + D35*H54 + D36*H64 + D37*H74; 128 | assign tF35= D30*H05 + D31*H15 + D32*H25 + D33*H35 + D34*H45 + D35*H55 + D36*H65 + D37*H75; 129 | assign tF36= D30*H06 + D31*H16 + D32*H26 + D33*H36 + D34*H46 + D35*H56 + D36*H66 + D37*H76; 130 | assign tF37= D30*H07 + D31*H17 + D32*H27 + D33*H37 + D34*H47 + D35*H57 + D36*H67 + D37*H77; 131 | 132 | assign tF40= D40*H00 + D41*H10 + D42*H20 + D43*H30 + D44*H40 + D45*H50 + D46*H60 + D47*H70; 133 | assign tF41= D40*H01 + D41*H11 + D42*H21 + D43*H31 + D44*H41 + D45*H51 + D46*H61 + D47*H71; 134 | assign tF42= D40*H02 + D41*H12 + D42*H22 + D43*H32 + D44*H42 + D45*H52 + D46*H62 + D47*H72; 135 | assign tF43= D40*H03 + D41*H13 + D42*H23 + D43*H33 + D44*H43 + D45*H53 + D46*H63 + D47*H73; 136 | assign tF44= D40*H04 + D41*H14 + D42*H24 + D43*H34 + D44*H44 + D45*H54 + D46*H64 + D47*H74; 137 | assign tF45= D40*H05 + D41*H15 + D42*H25 + D43*H35 + D44*H45 + D45*H55 + D46*H65 + D47*H75; 138 | assign tF46= D40*H06 + D41*H16 + D42*H26 + D43*H36 + D44*H46 + D45*H56 + D46*H66 + D47*H76; 139 | assign tF47= D40*H07 + D41*H17 + D42*H27 + D43*H37 + D44*H47 + D45*H57 + D46*H67 + D47*H77; 140 | 141 | assign tF50= D50*H00 + D51*H10 + D52*H20 + D53*H30 + D54*H40 + D55*H50 + D56*H60 + D57*H70; 142 | assign tF51= D50*H01 + D51*H11 + D52*H21 + D53*H31 + D54*H41 + D55*H51 + D56*H61 + D57*H71; 143 | assign tF52= D50*H02 + D51*H12 + D52*H22 + D53*H32 + D54*H42 + D55*H52 + D56*H62 + D57*H72; 144 | assign tF53= D50*H03 + D51*H13 + D52*H23 + D53*H33 + D54*H43 + D55*H53 + D56*H63 + D57*H73; 145 | assign tF54= D50*H04 + D51*H14 + D52*H24 + D53*H34 + D54*H44 + D55*H54 + D56*H64 + D57*H74; 146 | assign tF55= D50*H05 + D51*H15 + D52*H25 + D53*H35 + D54*H45 + D55*H55 + D56*H65 + D57*H75; 147 | assign tF56= D50*H06 + D51*H16 + D52*H26 + D53*H36 + D54*H46 + D55*H56 + D56*H66 + D57*H76; 148 | assign tF57= D50*H07 + D51*H17 + D52*H27 + D53*H37 + D54*H47 + D55*H57 + D56*H67 + D57*H77; 149 | 150 | assign tF60= D60*H00 + D61*H10 + D62*H20 + D63*H30 + D64*H40 + D65*H50 + D66*H60 + D67*H70; 151 | assign tF61= D60*H01 + D61*H11 + D62*H21 + D63*H31 + D64*H41 + D65*H51 + D66*H61 + D67*H71; 152 | assign tF62= D60*H02 + D61*H12 + D62*H22 + D63*H32 + D64*H42 + D65*H52 + D66*H62 + D67*H72; 153 | assign tF63= D60*H03 + D61*H13 + D62*H23 + D63*H33 + D64*H43 + D65*H53 + D66*H63 + D67*H73; 154 | assign tF64= D60*H04 + D61*H14 + D62*H24 + D63*H34 + D64*H44 + D65*H54 + D66*H64 + D67*H74; 155 | assign tF65= D60*H05 + D61*H15 + D62*H25 + D63*H35 + D64*H45 + D65*H55 + D66*H65 + D67*H75; 156 | assign tF66= D60*H06 + D61*H16 + D62*H26 + D63*H36 + D64*H46 + D65*H56 + D66*H66 + D67*H76; 157 | assign tF67= D60*H07 + D61*H17 + D62*H27 + D63*H37 + D64*H47 + D65*H57 + D66*H67 + D67*H77; 158 | 159 | assign tF70= D70*H00 + D71*H10 + D72*H20 + D73*H30 + D74*H40 + D75*H50 + D76*H60 + D77*H70; 160 | assign tF71= D70*H01 + D71*H11 + D72*H21 + D73*H31 + D74*H41 + D75*H51 + D76*H61 + D77*H71; 161 | assign tF72= D70*H02 + D71*H12 + D72*H22 + D73*H32 + D74*H42 + D75*H52 + D76*H62 + D77*H72; 162 | assign tF73= D70*H03 + D71*H13 + D72*H23 + D73*H33 + D74*H43 + D75*H53 + D76*H63 + D77*H73; 163 | assign tF74= D70*H04 + D71*H14 + D72*H24 + D73*H34 + D74*H44 + D75*H54 + D76*H64 + D77*H74; 164 | assign tF75= D70*H05 + D71*H15 + D72*H25 + D73*H35 + D74*H45 + D75*H55 + D76*H65 + D77*H75; 165 | assign tF76= D70*H06 + D71*H16 + D72*H26 + D73*H36 + D74*H46 + D75*H56 + D76*H66 + D77*H76; 166 | assign tF77= D70*H07 + D71*H17 + D72*H27 + D73*H37 + D74*H47 + D75*H57 + D76*H67 + D77*H77; 167 | 168 | 169 | 170 | 171 | assign F00= tF00[23:8]; 172 | assign F01= tF01[23:8]; 173 | assign F02= tF02[23:8]; 174 | assign F03= tF03[23:8]; 175 | assign F04= tF04[23:8]; 176 | assign F05= tF05[23:8]; 177 | assign F06= tF06[23:8]; 178 | assign F07= tF07[23:8]; 179 | 180 | assign F10= tF10[23:8]; 181 | assign F11= tF11[23:8]; 182 | assign F12= tF12[23:8]; 183 | assign F13= tF13[23:8]; 184 | assign F14= tF14[23:8]; 185 | assign F15= tF15[23:8]; 186 | assign F16= tF16[23:8]; 187 | assign F17= tF17[23:8]; 188 | 189 | assign F20= tF20[23:8]; 190 | assign F21= tF21[23:8]; 191 | assign F22= tF22[23:8]; 192 | assign F23= tF23[23:8]; 193 | assign F24= tF24[23:8]; 194 | assign F25= tF25[23:8]; 195 | assign F26= tF26[23:8]; 196 | assign F27= tF27[23:8]; 197 | 198 | assign F30= tF30[23:8]; 199 | assign F31= tF31[23:8]; 200 | assign F32= tF32[23:8]; 201 | assign F33= tF33[23:8]; 202 | assign F34= tF34[23:8]; 203 | assign F35= tF35[23:8]; 204 | assign F36= tF36[23:8]; 205 | assign F37= tF37[23:8]; 206 | 207 | assign F40= tF40[23:8]; 208 | assign F41= tF41[23:8]; 209 | assign F42= tF42[23:8]; 210 | assign F43= tF43[23:8]; 211 | assign F44= tF44[23:8]; 212 | assign F45= tF45[23:8]; 213 | assign F46= tF46[23:8]; 214 | assign F47= tF47[23:8]; 215 | 216 | assign F50= tF50[23:8]; 217 | assign F51= tF51[23:8]; 218 | assign F52= tF52[23:8]; 219 | assign F53= tF53[23:8]; 220 | assign F54= tF54[23:8]; 221 | assign F55= tF55[23:8]; 222 | assign F56= tF56[23:8]; 223 | assign F57= tF57[23:8]; 224 | 225 | assign F60= tF60[23:8]; 226 | assign F61= tF61[23:8]; 227 | assign F62= tF62[23:8]; 228 | assign F63= tF63[23:8]; 229 | assign F64= tF64[23:8]; 230 | assign F65= tF65[23:8]; 231 | assign F66= tF66[23:8]; 232 | assign F67= tF67[23:8]; 233 | 234 | assign F70= tF70[23:8]; 235 | assign F71= tF71[23:8]; 236 | assign F72= tF72[23:8]; 237 | assign F73= tF73[23:8]; 238 | assign F74= tF74[23:8]; 239 | assign F75= tF75[23:8]; 240 | assign F76= tF76[23:8]; 241 | assign F77= tF77[23:8]; 242 | 243 | 244 | /*assign F[1][0]= D[1][0]*H[0][0] + D[1][1]*H[1][0] + D[1][2]*H[2][0] + D[1][3]*H[3][0] + D[1][4]*H[4][0] + D[1][5]*H[5][0] + D[1][6]*H[6][0] + D[1][7]*H[7][0]; 245 | assign F[1][1]= D[1][0]*H[0][1] + D[1][1]*H[1][1] + D[1][2]*H[2][1] + D[1][3]*H[3][1] + D[1][4]*H[4][1] + D[1][5]*H[5][1] + D[1][6]*H[6][1] + D[1][7]*H[7][1]; 246 | assign F[1][2]= D[1][0]*H[0][2] + D[1][1]*H[1][2] + D[1][2]*H[2][2] + D[1][3]*H[3][2] + D[1][4]*H[4][2] + D[1][5]*H[5][2] + D[1][6]*H[6][2] + D[1][7]*H[7][2]; 247 | assign F[1][3]= D[1][0]*H[0][3] + D[1][1]*H[1][3] + D[1][2]*H[2][3] + D[1][3]*H[3][3] + D[1][4]*H[4][3] + D[1][5]*H[5][3] + D[1][6]*H[6][3] + D[1][7]*H[7][3]; 248 | assign F[1][4]= D[1][0]*H[0][4] + D[1][1]*H[1][4] + D[1][2]*H[2][4] + D[1][3]*H[3][4] + D[1][4]*H[4][4] + D[1][5]*H[5][4] + D[1][6]*H[6][4] + D[1][7]*H[7][4]; 249 | assign F[1][5]= D[1][0]*H[0][5] + D[1][1]*H[1][5] + D[1][2]*H[2][5] + D[1][3]*H[3][5] + D[1][4]*H[4][5] + D[1][5]*H[5][5] + D[1][6]*H[6][5] + D[1][7]*H[7][5]; 250 | assign F[1][6]= D[1][0]*H[0][6] + D[1][1]*H[1][6] + D[1][2]*H[2][6] + D[1][3]*H[3][6] + D[1][4]*H[4][6] + D[1][5]*H[5][6] + D[1][6]*H[6][6] + D[1][7]*H[7][6]; 251 | assign F[1][7]= D[1][0]*H[0][7] + D[1][1]*H[1][7] + D[1][2]*H[2][7] + D[1][3]*H[3][7] + D[1][4]*H[4][7] + D[1][5]*H[5][7] + D[1][6]*H[6][7] + D[1][7]*H[7][7]; 252 | 253 | 254 | assign F[2][0]= D[2][0]*H[0][0] + D[2][1]*H[1][0] + D[2][2]*H[2][0] + D[2][3]*H[3][0] + D[2][4]*H[4][0] + D[2][5]*H[5][0] + D[2][6]*H[6][0] + D[2][7]*H[7][0]; 255 | assign F[2][1]= D[2][0]*H[0][1] + D[2][1]*H[1][1] + D[2][2]*H[2][1] + D[2][3]*H[3][1] + D[2][4]*H[4][1] + D[2][5]*H[5][1] + D[2][6]*H[6][1] + D[2][7]*H[7][1]; 256 | assign F[2][2]= D[2][0]*H[0][2] + D[2][1]*H[1][2] + D[2][2]*H[2][2] + D[2][3]*H[3][2] + D[2][4]*H[4][2] + D[2][5]*H[5][2] + D[2][6]*H[6][2] + D[2][7]*H[7][2]; 257 | assign F[2][3]= D[2][0]*H[0][3] + D[2][1]*H[1][3] + D[2][2]*H[2][3] + D[2][3]*H[3][3] + D[2][4]*H[4][3] + D[2][5]*H[5][3] + D[2][6]*H[6][3] + D[2][7]*H[7][3]; 258 | assign F[2][4]= D[2][0]*H[0][4] + D[2][1]*H[1][4] + D[2][2]*H[2][4] + D[2][3]*H[3][4] + D[2][4]*H[4][4] + D[2][5]*H[5][4] + D[2][6]*H[6][4] + D[2][7]*H[7][4]; 259 | assign F[2][5]= D[2][0]*H[0][5] + D[2][1]*H[1][5] + D[2][2]*H[2][5] + D[2][3]*H[3][5] + D[2][4]*H[4][5] + D[2][5]*H[5][5] + D[2][6]*H[6][5] + D[2][7]*H[7][5]; 260 | assign F[2][6]= D[2][0]*H[0][6] + D[2][1]*H[1][6] + D[2][2]*H[2][6] + D[2][3]*H[3][6] + D[2][4]*H[4][6] + D[2][5]*H[5][6] + D[2][6]*H[6][6] + D[2][7]*H[7][6]; 261 | assign F[2][7]= D[2][0]*H[0][7] + D[2][1]*H[1][7] + D[2][2]*H[2][7] + D[2][3]*H[3][7] + D[2][4]*H[4][7] + D[2][5]*H[5][7] + D[2][6]*H[6][7] + D[2][7]*H[7][7]; 262 | 263 | 264 | assign F[3][0]= D[3][0]*H[0][0] + D[3][1]*H[1][0] + D[3][2]*H[2][0] + D[3][3]*H[3][0] + D[3][4]*H[4][0] + D[3][5]*H[5][0] + D[3][6]*H[6][0] + D[3][7]*H[7][0]; 265 | assign F[3][1]= D[3][0]*H[0][1] + D[3][1]*H[1][1] + D[3][2]*H[2][1] + D[3][3]*H[3][1] + D[3][4]*H[4][1] + D[3][5]*H[5][1] + D[3][6]*H[6][1] + D[3][7]*H[7][1]; 266 | assign F[3][2]= D[3][0]*H[0][2] + D[3][1]*H[1][2] + D[3][2]*H[2][2] + D[3][3]*H[3][2] + D[3][4]*H[4][2] + D[3][5]*H[5][2] + D[3][6]*H[6][2] + D[3][7]*H[7][2]; 267 | assign F[3][3]= D[3][0]*H[0][3] + D[3][1]*H[1][3] + D[3][2]*H[2][3] + D[3][3]*H[3][3] + D[3][4]*H[4][3] + D[3][5]*H[5][3] + D[3][6]*H[6][3] + D[3][7]*H[7][3]; 268 | assign F[3][4]= D[3][0]*H[0][4] + D[3][1]*H[1][4] + D[3][2]*H[2][4] + D[3][3]*H[3][4] + D[3][4]*H[4][4] + D[3][5]*H[5][4] + D[3][6]*H[6][4] + D[3][7]*H[7][4]; 269 | assign F[3][5]= D[3][0]*H[0][5] + D[3][1]*H[1][5] + D[3][2]*H[2][5] + D[3][3]*H[3][5] + D[3][4]*H[4][5] + D[3][5]*H[5][5] + D[3][6]*H[6][5] + D[3][7]*H[7][5]; 270 | assign F[3][6]= D[3][0]*H[0][6] + D[3][1]*H[1][6] + D[3][2]*H[2][6] + D[3][3]*H[3][6] + D[3][4]*H[4][6] + D[3][5]*H[5][6] + D[3][6]*H[6][6] + D[3][7]*H[7][6]; 271 | assign F[3][7]= D[3][0]*H[0][7] + D[3][1]*H[1][7] + D[3][2]*H[2][7] + D[3][3]*H[3][7] + D[3][4]*H[4][7] + D[3][5]*H[5][7] + D[3][6]*H[6][7] + D[3][7]*H[7][7]; 272 | 273 | 274 | assign F[4][0]= D[4][0]*H[0][0] + D[4][1]*H[1][0] + D[4][2]*H[2][0] + D[4][3]*H[3][0] + D[4][4]*H[4][0] + D[4][5]*H[5][0] + D[4][6]*H[6][0] + D[4][7]*H[7][0]; 275 | assign F[4][1]= D[4][0]*H[0][1] + D[4][1]*H[1][1] + D[4][2]*H[2][1] + D[4][3]*H[3][1] + D[4][4]*H[4][1] + D[4][5]*H[5][1] + D[4][6]*H[6][1] + D[4][7]*H[7][1]; 276 | assign F[4][2]= D[4][0]*H[0][2] + D[4][1]*H[1][2] + D[4][2]*H[2][2] + D[4][3]*H[3][2] + D[4][4]*H[4][2] + D[4][5]*H[5][2] + D[4][6]*H[6][2] + D[4][7]*H[7][2]; 277 | assign F[4][3]= D[4][0]*H[0][3] + D[4][1]*H[1][3] + D[4][2]*H[2][3] + D[4][3]*H[3][3] + D[4][4]*H[4][3] + D[4][5]*H[5][3] + D[4][6]*H[6][3] + D[4][7]*H[7][3]; 278 | assign F[4][4]= D[4][0]*H[0][4] + D[4][1]*H[1][4] + D[4][2]*H[2][4] + D[4][3]*H[3][4] + D[4][4]*H[4][4] + D[4][5]*H[5][4] + D[4][6]*H[6][4] + D[4][7]*H[7][4]; 279 | assign F[4][5]= D[4][0]*H[0][5] + D[4][1]*H[1][5] + D[4][2]*H[2][5] + D[4][3]*H[3][5] + D[4][4]*H[4][5] + D[4][5]*H[5][5] + D[4][6]*H[6][5] + D[4][7]*H[7][5]; 280 | assign F[4][6]= D[4][0]*H[0][6] + D[4][1]*H[1][6] + D[4][2]*H[2][6] + D[4][3]*H[3][6] + D[4][4]*H[4][6] + D[4][5]*H[5][6] + D[4][6]*H[6][6] + D[4][7]*H[7][6]; 281 | assign F[4][7]= D[4][0]*H[0][7] + D[4][1]*H[1][7] + D[4][2]*H[2][7] + D[4][3]*H[3][7] + D[4][4]*H[4][7] + D[4][5]*H[5][7] + D[4][6]*H[6][7] + D[4][7]*H[7][7]; 282 | 283 | 284 | assign F[5][0]= D[5][0]*H[0][0] + D[5][1]*H[1][0] + D[5][2]*H[2][0] + D[5][3]*H[3][0] + D[5][4]*H[4][0] + D[5][5]*H[5][0] + D[5][6]*H[6][0] + D[5][7]*H[7][0]; 285 | assign F[5][1]= D[5][0]*H[0][1] + D[5][1]*H[1][1] + D[5][2]*H[2][1] + D[5][3]*H[3][1] + D[5][4]*H[4][1] + D[5][5]*H[5][1] + D[5][6]*H[6][1] + D[5][7]*H[7][1]; 286 | assign F[5][2]= D[5][0]*H[0][2] + D[5][1]*H[1][2] + D[5][2]*H[2][2] + D[5][3]*H[3][2] + D[5][4]*H[4][2] + D[5][5]*H[5][2] + D[5][6]*H[6][2] + D[5][7]*H[7][2]; 287 | assign F[5][3]= D[5][0]*H[0][3] + D[5][1]*H[1][3] + D[5][2]*H[2][3] + D[5][3]*H[3][3] + D[5][4]*H[4][3] + D[5][5]*H[5][3] + D[5][6]*H[6][3] + D[5][7]*H[7][3]; 288 | assign F[5][4]= D[5][0]*H[0][4] + D[5][1]*H[1][4] + D[5][2]*H[2][4] + D[5][3]*H[3][4] + D[5][4]*H[4][4] + D[5][5]*H[5][4] + D[5][6]*H[6][4] + D[5][7]*H[7][4]; 289 | assign F[5][5]= D[5][0]*H[0][5] + D[5][1]*H[1][5] + D[5][2]*H[2][5] + D[5][3]*H[3][5] + D[5][4]*H[4][5] + D[5][5]*H[5][5] + D[5][6]*H[6][5] + D[5][7]*H[7][5]; 290 | assign F[5][6]= D[5][0]*H[0][6] + D[5][1]*H[1][6] + D[5][2]*H[2][6] + D[5][3]*H[3][6] + D[5][4]*H[4][6] + D[5][5]*H[5][6] + D[5][6]*H[6][6] + D[5][7]*H[7][6]; 291 | assign F[5][7]= D[5][0]*H[0][7] + D[5][1]*H[1][7] + D[5][2]*H[2][7] + D[5][3]*H[3][7] + D[5][4]*H[4][7] + D[5][5]*H[5][7] + D[5][6]*H[6][7] + D[5][7]*H[7][7]; 292 | 293 | 294 | assign F[6][0]= D[6][0]*H[0][0] + D[6][1]*H[1][0] + D[6][2]*H[2][0] + D[6][3]*H[3][0] + D[6][4]*H[4][0] + D[6][5]*H[5][0] + D[6][6]*H[6][0] + D[6][7]*H[7][0]; 295 | assign F[6][1]= D[6][0]*H[0][1] + D[6][1]*H[1][1] + D[6][2]*H[2][1] + D[6][3]*H[3][1] + D[6][4]*H[4][1] + D[6][5]*H[5][1] + D[6][6]*H[6][1] + D[6][7]*H[7][1]; 296 | assign F[6][2]= D[6][0]*H[0][2] + D[6][1]*H[1][2] + D[6][2]*H[2][2] + D[6][3]*H[3][2] + D[6][4]*H[4][2] + D[6][5]*H[5][2] + D[6][6]*H[6][2] + D[6][7]*H[7][2]; 297 | assign F[6][3]= D[6][0]*H[0][3] + D[6][1]*H[1][3] + D[6][2]*H[2][3] + D[6][3]*H[3][3] + D[6][4]*H[4][3] + D[6][5]*H[5][3] + D[6][6]*H[6][3] + D[6][7]*H[7][3]; 298 | assign F[6][4]= D[6][0]*H[0][4] + D[6][1]*H[1][4] + D[6][2]*H[2][4] + D[6][3]*H[3][4] + D[6][4]*H[4][4] + D[6][5]*H[5][4] + D[6][6]*H[6][4] + D[6][7]*H[7][4]; 299 | assign F[6][5]= D[6][0]*H[0][5] + D[6][1]*H[1][5] + D[6][2]*H[2][5] + D[6][3]*H[3][5] + D[6][4]*H[4][5] + D[6][5]*H[5][5] + D[6][6]*H[6][5] + D[6][7]*H[7][5]; 300 | assign F[6][6]= D[6][0]*H[0][6] + D[6][1]*H[1][6] + D[6][2]*H[2][6] + D[6][3]*H[3][6] + D[6][4]*H[4][6] + D[6][5]*H[5][6] + D[6][6]*H[6][6] + D[6][7]*H[7][6]; 301 | assign F[6][7]= D[6][0]*H[0][7] + D[6][1]*H[1][7] + D[6][2]*H[2][7] + D[6][3]*H[3][7] + D[6][4]*H[4][7] + D[6][5]*H[5][7] + D[6][6]*H[6][7] + D[6][7]*H[7][7]; 302 | 303 | 304 | assign F[7][0]= D[7][0]*H[0][0] + D[7][1]*H[1][0] + D[7][2]*H[2][0] + D[7][3]*H[3][0] + D[7][4]*H[4][0] + D[7][5]*H[5][0] + D[7][6]*H[6][0] + D[7][7]*H[7][0]; 305 | assign F[7][1]= D[7][0]*H[0][1] + D[7][1]*H[1][1] + D[7][2]*H[2][1] + D[7][3]*H[3][1] + D[7][4]*H[4][1] + D[7][5]*H[5][1] + D[7][6]*H[6][1] + D[7][7]*H[7][1]; 306 | assign F[7][2]= D[7][0]*H[0][2] + D[7][1]*H[1][2] + D[7][2]*H[2][2] + D[7][3]*H[3][2] + D[7][4]*H[4][2] + D[7][5]*H[5][2] + D[7][6]*H[6][2] + D[7][7]*H[7][2]; 307 | assign F[7][3]= D[7][0]*H[0][3] + D[7][1]*H[1][3] + D[7][2]*H[2][3] + D[7][3]*H[3][3] + D[7][4]*H[4][3] + D[7][5]*H[5][3] + D[7][6]*H[6][3] + D[7][7]*H[7][3]; 308 | assign F[7][4]= D[7][0]*H[0][4] + D[7][1]*H[1][4] + D[7][2]*H[2][4] + D[7][3]*H[3][4] + D[7][4]*H[4][4] + D[7][5]*H[5][4] + D[7][6]*H[6][4] + D[7][7]*H[7][4]; 309 | assign F[7][5]= D[7][0]*H[0][5] + D[7][1]*H[1][5] + D[7][2]*H[2][5] + D[7][3]*H[3][5] + D[7][4]*H[4][5] + D[7][5]*H[5][5] + D[7][6]*H[6][5] + D[7][7]*H[7][5]; 310 | assign F[7][6]= D[7][0]*H[0][6] + D[7][1]*H[1][6] + D[7][2]*H[2][6] + D[7][3]*H[3][6] + D[7][4]*H[4][6] + D[7][5]*H[5][6] + D[7][6]*H[6][6] + D[7][7]*H[7][6]; 311 | assign F[7][7]= D[7][0]*H[0][7] + D[7][1]*H[1][7] + D[7][2]*H[2][7] + D[7][3]*H[3][7] + D[7][4]*H[4][7] + D[7][5]*H[5][7] + D[7][6]*H[6][7] + D[7][7]*H[7][7]; 312 | */ 313 | 314 | endmodule 315 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/Multiplier_8x8_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 23:42:29 11/01/2017 8 | // Design Name: Multiplier_8x8 9 | // Module Name: C:/Users/Maharsh Suryawala/Desktop/Functions/IMG/Multiplier_8x8_tb.v 10 | // Project Name: IMG 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: Multiplier_8x8 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module Multiplier_8x8_tb; 26 | 27 | // Inputs 28 | reg F; 29 | reg [15:0] H; 30 | reg [15:0] D; 31 | 32 | // Instantiate the Unit Under Test (UUT) 33 | Multiplier_8x8 uut ( 34 | .F(F), 35 | .H(H), 36 | .D(D) 37 | ); 38 | 39 | initial begin 40 | // Initialize Inputs 41 | F = 0; 42 | H = 0; 43 | D = 0; 44 | 45 | // Wait 100 ns for global reset to finish 46 | #100; 47 | 48 | // Add stimulus here 49 | 50 | end 51 | 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/Quantization.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:29:01 11/05/2017 7 | // Design Name: 8 | // Module Name: Qmuantization 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Quantization( 22 | Q00, Q01, Q02, Q03, Q04, Q05, Q06, Q07, 23 | Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, 24 | Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, 25 | Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, 26 | Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, 27 | Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, 28 | Q60, Q61, Q62, Q63, Q64, Q65, Q66, Q67, 29 | Q70, Q71, Q72, Q73, Q74, Q75, Q76, Q77, 30 | 31 | H00, H01, H02, H03, H04, H05, H06, H07, 32 | H10, H11, H12, H13, H14, H15, H16, H17, 33 | H20, H21, H22, H23, H24, H25, H26, H27, 34 | H30, H31, H32, H33, H34, H35, H36, H37, 35 | H40, H41, H42, H43, H44, H45, H46, H47, 36 | H50, H51, H52, H53, H54, H55, H56, H57, 37 | H60, H61, H62, H63, H64, H65, H66, H67, 38 | H70, H71, H72, H73, H74, H75, H76, H77 39 | ); 40 | input[15:0] H00, H01, H02, H03, H04, H05, H06, H07; 41 | input[15:0] H10, H11, H12, H13, H14, H15, H16, H17; 42 | input[15:0] H20, H21, H22, H23, H24, H25, H26, H27; 43 | input[15:0] H30, H31, H32, H33, H34, H35, H36, H37; 44 | input[15:0] H40, H41, H42, H43, H44, H45, H46, H47; 45 | input[15:0] H50, H51, H52, H53, H54, H55, H56, H57; 46 | input[15:0] H60, H61, H62, H63, H64, H65, H66, H67; 47 | input[15:0] H70, H71, H72, H73, H74, H75, H76, H77; 48 | 49 | output[15:0] Q00, Q01, Q02, Q03, Q04, Q05, Q06, Q07; 50 | output[15:0] Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17; 51 | output[15:0] Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27; 52 | output[15:0] Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37; 53 | output[15:0] Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47; 54 | output[15:0] Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57; 55 | output[15:0] Q60, Q61, Q62, Q63, Q64, Q65, Q66, Q67; 56 | output[15:0] Q70, Q71, Q72, Q73, Q74, Q75, Q76, Q77; 57 | 58 | wire[31:0] Qtmp00, Qtmp01, Qtmp02, Qtmp03, Qtmp04, Qtmp05, Qtmp06, Qtmp07; 59 | wire[31:0] Qtmp10, Qtmp11, Qtmp12, Qtmp13, Qtmp14, Qtmp15, Qtmp16, Qtmp17; 60 | wire[31:0] Qtmp20, Qtmp21, Qtmp22, Qtmp23, Qtmp24, Qtmp25, Qtmp26, Qtmp27; 61 | wire[31:0] Qtmp30, Qtmp31, Qtmp32, Qtmp33, Qtmp34, Qtmp35, Qtmp36, Qtmp37; 62 | wire[31:0] Qtmp40, Qtmp41, Qtmp42, Qtmp43, Qtmp44, Qtmp45, Qtmp46, Qtmp47; 63 | wire[31:0] Qtmp50, Qtmp51, Qtmp52, Qtmp53, Qtmp54, Qtmp55, Qtmp56, Qtmp57; 64 | wire[31:0] Qtmp60, Qtmp61, Qtmp62, Qtmp63, Qtmp64, Qtmp65, Qtmp66, Qtmp67; 65 | wire[31:0] Qtmp70, Qtmp71, Qtmp72, Qtmp73, Qtmp74, Qtmp75, Qtmp76, Qtmp77; 66 | wire [15:0] Qm[7:0][7:0]; 67 | 68 | assign Qm[0][0]=16'b0000000000010000; 69 | assign Qm[0][1]=16'b0000000000010101; 70 | assign Qm[0][2]=16'b0000000000010010; 71 | assign Qm[0][3]=16'b0000000000010010; 72 | assign Qm[0][4]=16'b0000000000001110; 73 | assign Qm[0][5]=16'b0000000000001010; 74 | assign Qm[0][6]=16'b0000000000000101; 75 | assign Qm[0][7]=16'b0000000000000011; 76 | 77 | assign Qm[1][0]=16'b0000000000010111; 78 | assign Qm[1][1]=16'b0000000000010101; 79 | assign Qm[1][2]=16'b0000000000010011; 80 | assign Qm[1][3]=16'b0000000000001111; 81 | assign Qm[1][4]=16'b0000000000001011; 82 | assign Qm[1][5]=16'b0000000000000111; 83 | assign Qm[1][6]=16'b0000000000000100; 84 | assign Qm[1][7]=16'b0000000000000010; 85 | 86 | assign Qm[2][0]=16'b0000000000011001; 87 | assign Qm[2][1]=16'b0000000000010010; 88 | assign Qm[2][2]=16'b0000000000010000; 89 | assign Qm[2][3]=16'b0000000000001011; 90 | assign Qm[2][4]=16'b0000000000000110; 91 | assign Qm[2][5]=16'b0000000000000100; 92 | assign Qm[2][6]=16'b0000000000000011; 93 | assign Qm[2][7]=16'b0000000000000010; 94 | 95 | assign Qm[3][0]=16'b0000000000010000; 96 | assign Qm[3][1]=16'b0000000000001101; 97 | assign Qm[3][2]=16'b0000000000001010; 98 | assign Qm[3][3]=16'b0000000000001000; 99 | assign Qm[3][4]=16'b0000000000000100; 100 | assign Qm[3][5]=16'b0000000000000100; 101 | assign Qm[3][6]=16'b0000000000000010; 102 | assign Qm[3][7]=16'b0000000000000010; 103 | 104 | assign Qm[4][0]=16'b0000000000001010; 105 | assign Qm[4][1]=16'b0000000000001001; 106 | assign Qm[4][2]=16'b0000000000000110; 107 | assign Qm[4][3]=16'b0000000000000101; 108 | assign Qm[4][4]=16'b0000000000000011; 109 | assign Qm[4][5]=16'b0000000000000011; 110 | assign Qm[4][6]=16'b0000000000000010; 111 | assign Qm[4][7]=16'b0000000000000010; 112 | 113 | 114 | assign Qm[5][0]=16'b0000000000000110; 115 | assign Qm[5][1]=16'b0000000000000100; 116 | assign Qm[5][2]=16'b0000000000000100; 117 | assign Qm[5][3]=16'b0000000000000010; 118 | assign Qm[5][4]=16'b0000000000000010; 119 | assign Qm[5][5]=16'b0000000000000010; 120 | assign Qm[5][6]=16'b0000000000000010; 121 | assign Qm[5][7]=16'b0000000000000010; 122 | 123 | assign Qm[6][0]=16'b0000000000000101; 124 | assign Qm[6][1]=16'b0000000000000100; 125 | assign Qm[6][2]=16'b0000000000000011; 126 | assign Qm[6][3]=16'b0000000000000011; 127 | assign Qm[6][4]=16'b0000000000000010; 128 | assign Qm[6][5]=16'b0000000000000010; 129 | assign Qm[6][6]=16'b0000000000000010; 130 | assign Qm[6][7]=16'b0000000000000010; 131 | 132 | 133 | assign Qm[7][0]=16'b0000000000000100; 134 | assign Qm[7][1]=16'b0000000000000100; 135 | assign Qm[7][2]=16'b0000000000000100; 136 | assign Qm[7][3]=16'b0000000000000100; 137 | assign Qm[7][4]=16'b0000000000000011; 138 | assign Qm[7][5]=16'b0000000000000010; 139 | assign Qm[7][6]=16'b0000000000000010; 140 | assign Qm[7][7]=16'b0000000000000010; 141 | 142 | assign Qtmp00=H00*Qm[0][0]; 143 | assign Qtmp01=H01*Qm[0][1]; 144 | assign Qtmp02=H02*Qm[0][2]; 145 | assign Qtmp03=H03*Qm[0][3]; 146 | assign Qtmp04=H04*Qm[0][4]; 147 | assign Qtmp05=H05*Qm[0][5]; 148 | assign Qtmp06=H06*Qm[0][6]; 149 | assign Qtmp07=H07*Qm[0][7]; 150 | 151 | assign Qtmp10=H10*Qm[1][0]; 152 | assign Qtmp11=H11*Qm[1][1]; 153 | assign Qtmp12=H12*Qm[1][2]; 154 | assign Qtmp13=H13*Qm[1][3]; 155 | assign Qtmp14=H14*Qm[1][4]; 156 | assign Qtmp15=H15*Qm[1][5]; 157 | assign Qtmp16=H16*Qm[1][6]; 158 | assign Qtmp17=H17*Qm[1][7]; 159 | 160 | assign Qtmp20=H20*Qm[2][0]; 161 | assign Qtmp21=H21*Qm[2][1]; 162 | assign Qtmp22=H22*Qm[2][2]; 163 | assign Qtmp23=H23*Qm[2][3]; 164 | assign Qtmp24=H24*Qm[2][4]; 165 | assign Qtmp25=H25*Qm[2][5]; 166 | assign Qtmp26=H26*Qm[2][6]; 167 | assign Qtmp27=H27*Qm[2][7]; 168 | 169 | assign Qtmp30=H30*Qm[3][0]; 170 | assign Qtmp31=H31*Qm[3][1]; 171 | assign Qtmp32=H32*Qm[3][2]; 172 | assign Qtmp33=H33*Qm[3][3]; 173 | assign Qtmp34=H34*Qm[3][4]; 174 | assign Qtmp35=H35*Qm[3][5]; 175 | assign Qtmp36=H36*Qm[3][6]; 176 | assign Qtmp37=H37*Qm[3][7]; 177 | 178 | assign Qtmp40=H40*Qm[4][0]; 179 | assign Qtmp41=H41*Qm[4][1]; 180 | assign Qtmp42=H42*Qm[4][2]; 181 | assign Qtmp43=H43*Qm[4][3]; 182 | assign Qtmp44=H44*Qm[4][4]; 183 | assign Qtmp45=H45*Qm[4][5]; 184 | assign Qtmp46=H46*Qm[4][6]; 185 | assign Qtmp47=H47*Qm[4][7]; 186 | 187 | assign Qtmp50=H50*Qm[5][0]; 188 | assign Qtmp51=H51*Qm[5][1]; 189 | assign Qtmp52=H52*Qm[5][2]; 190 | assign Qtmp53=H53*Qm[5][3]; 191 | assign Qtmp54=H54*Qm[5][4]; 192 | assign Qtmp55=H55*Qm[5][5]; 193 | assign Qtmp56=H56*Qm[5][6]; 194 | assign Qtmp57=H57*Qm[5][7]; 195 | 196 | assign Qtmp60=H60*Qm[6][0]; 197 | assign Qtmp61=H61*Qm[6][1]; 198 | assign Qtmp62=H62*Qm[6][2]; 199 | assign Qtmp63=H63*Qm[6][3]; 200 | assign Qtmp64=H64*Qm[6][4]; 201 | assign Qtmp65=H65*Qm[6][5]; 202 | assign Qtmp66=H66*Qm[6][6]; 203 | assign Qtmp67=H67*Qm[6][7]; 204 | 205 | assign Qtmp70=H70*Qm[7][0]; 206 | assign Qtmp71=H71*Qm[7][1]; 207 | assign Qtmp72=H72*Qm[7][2]; 208 | assign Qtmp73=H73*Qm[7][3]; 209 | assign Qtmp74=H74*Qm[7][4]; 210 | assign Qtmp75=H75*Qm[7][5]; 211 | assign Qtmp76=H76*Qm[7][6]; 212 | assign Qtmp77=H77*Qm[7][7]; 213 | 214 | assign Q00= Qtmp00[23:8]; 215 | assign Q01= Qtmp01[23:8]; 216 | assign Q02= Qtmp02[23:8]; 217 | assign Q03= Qtmp03[23:8]; 218 | assign Q04= Qtmp04[23:8]; 219 | assign Q05= Qtmp05[23:8]; 220 | assign Q06= Qtmp06[23:8]; 221 | assign Q07= Qtmp07[23:8]; 222 | 223 | assign Q10= Qtmp10[23:8]; 224 | assign Q11= Qtmp11[23:8]; 225 | assign Q12= Qtmp12[23:8]; 226 | assign Q13= Qtmp13[23:8]; 227 | assign Q14= Qtmp14[23:8]; 228 | assign Q15= Qtmp15[23:8]; 229 | assign Q16= Qtmp16[23:8]; 230 | assign Q17= Qtmp17[23:8]; 231 | 232 | assign Q20= Qtmp20[23:8]; 233 | assign Q21= Qtmp21[23:8]; 234 | assign Q22= Qtmp22[23:8]; 235 | assign Q23= Qtmp23[23:8]; 236 | assign Q24= Qtmp24[23:8]; 237 | assign Q25= Qtmp25[23:8]; 238 | assign Q26= Qtmp26[23:8]; 239 | assign Q27= Qtmp27[23:8]; 240 | 241 | assign Q30= Qtmp30[23:8]; 242 | assign Q31= Qtmp31[23:8]; 243 | assign Q32= Qtmp32[23:8]; 244 | assign Q33= Qtmp33[23:8]; 245 | assign Q34= Qtmp34[23:8]; 246 | assign Q35= Qtmp35[23:8]; 247 | assign Q36= Qtmp36[23:8]; 248 | assign Q37= Qtmp37[23:8]; 249 | 250 | assign Q40= Qtmp40[23:8]; 251 | assign Q41= Qtmp41[23:8]; 252 | assign Q42= Qtmp42[23:8]; 253 | assign Q43= Qtmp43[23:8]; 254 | assign Q44= Qtmp44[23:8]; 255 | assign Q45= Qtmp45[23:8]; 256 | assign Q46= Qtmp46[23:8]; 257 | assign Q47= Qtmp47[23:8]; 258 | 259 | assign Q50= Qtmp50[23:8]; 260 | assign Q51= Qtmp51[23:8]; 261 | assign Q52= Qtmp52[23:8]; 262 | assign Q53= Qtmp53[23:8]; 263 | assign Q54= Qtmp54[23:8]; 264 | assign Q55= Qtmp55[23:8]; 265 | assign Q56= Qtmp56[23:8]; 266 | assign Q57= Qtmp57[23:8]; 267 | 268 | assign Q60= Qtmp60[23:8]; 269 | assign Q61= Qtmp61[23:8]; 270 | assign Q62= Qtmp62[23:8]; 271 | assign Q63= Qtmp63[23:8]; 272 | assign Q64= Qtmp64[23:8]; 273 | assign Q65= Qtmp65[23:8]; 274 | assign Q66= Qtmp66[23:8]; 275 | assign Q67= Qtmp67[23:8]; 276 | 277 | assign Q70= Qtmp70[23:8]; 278 | assign Q71= Qtmp71[23:8]; 279 | assign Q72= Qtmp72[23:8]; 280 | assign Q73= Qtmp73[23:8]; 281 | assign Q74= Qtmp74[23:8]; 282 | assign Q75= Qtmp75[23:8]; 283 | assign Q76= Qtmp76[23:8]; 284 | assign Q77= Qtmp77[23:8]; 285 | 286 | 287 | endmodule 288 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/Test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 19:03:05 10/31/2017 7 | // Design Name: 8 | // Module Name: Test 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Test(clk 22 | ); 23 | input clk; 24 | real D1,D12; 25 | //integer [15:0] Din[7:0][7:0]; 26 | 27 | always@(posedge clk)begin 28 | D1 = 0.3535533; 29 | D12 = -0.490392640201615; 30 | end 31 | 32 | 33 | 34 | 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/counter_3.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 00:00:37 10/31/2017 7 | // Design Name: 8 | // Module Name: counter_3 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module counter_3(count, clk, rst); 22 | parameter n=2; 23 | 24 | output reg [n:0] count; 25 | input clk; 26 | input rst; 27 | 28 | // Set the initial value 29 | initial 30 | count = 0; 31 | 32 | // Increment count on clock 33 | always @(posedge clk or negedge rst) 34 | if (!rst) 35 | count = 0; 36 | else 37 | count = count + 1; 38 | 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/counter_6.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 01:44:09 10/31/2017 7 | // Design Name: 8 | // Module Name: counter_6 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module counter_6(count, clk, rst); 22 | parameter n=5; 23 | 24 | output reg [n:0] count; 25 | input clk; 26 | input rst; 27 | 28 | // Set the initial value 29 | initial 30 | count = 0; 31 | 32 | // Increment count on clock 33 | always @(posedge clk ) 34 | 35 | count = count + 1; 36 | 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/counter_64.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 01:41:35 10/31/2017 7 | // Design Name: 8 | // Module Name: counter_64 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module counter_64(count, clk, rst); 22 | parameter n=63 23 | 24 | output reg [n:0] count; 25 | input clk; 26 | input rst; 27 | 28 | // Set the initial value 29 | initial 30 | count = 0; 31 | 32 | // Increment count on clock 33 | always @(posedge clk or negedge rst) 34 | if (!rst) 35 | count = 0; 36 | else 37 | count = count + 1; 38 | 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/counter_8.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 00:00:22 10/31/2017 7 | // Design Name: 8 | // Module Name: counter_8 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module counter_8(count, clk, rst); 22 | parameter n=7; 23 | 24 | output reg [n:0] count; 25 | input clk; 26 | input rst; 27 | 28 | // Set the initial value 29 | initial 30 | count = 0; 31 | 32 | // Increment count on clock 33 | always @(posedge clk) 34 | 35 | count = count + 1; 36 | 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/mul_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 13:04:24 11/04/2017 8 | // Design Name: DiscreteCosineTransform 9 | // Module Name: C:/Users/Maharsh Suryawala/Desktop/Functions/IMG/mul_test.v 10 | // Project Name: IMG 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: DiscreteCosineTransform 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module mul_test; 26 | 27 | // Inputs 28 | reg [15:0] datain; 29 | reg clk; 30 | reg reset; 31 | 32 | // Outputs 33 | wire [31:0] D11_final; 34 | wire [31:0] D12_final; 35 | wire [31:0] D13_final; 36 | wire [31:0] D14_final; 37 | wire [31:0] D15_final; 38 | wire [31:0] D16_final; 39 | wire [31:0] D17_final; 40 | wire [31:0] D18_final; 41 | wire [31:0] D21_final; 42 | wire [31:0] D22_final; 43 | wire [31:0] D23_final; 44 | wire [31:0] D24_final; 45 | wire [31:0] D25_final; 46 | wire [31:0] D26_final; 47 | wire [31:0] D27_final; 48 | wire [31:0] D28_final; 49 | wire [31:0] D31_final; 50 | wire [31:0] D32_final; 51 | wire [31:0] D33_final; 52 | wire [31:0] D34_final; 53 | wire [31:0] D35_final; 54 | wire [31:0] D36_final; 55 | wire [31:0] D37_final; 56 | wire [31:0] D38_final; 57 | wire [31:0] D41_final; 58 | wire [31:0] D42_final; 59 | wire [31:0] D43_final; 60 | wire [31:0] D44_final; 61 | wire [31:0] D45_final; 62 | wire [31:0] D46_final; 63 | wire [31:0] D47_final; 64 | wire [31:0] D48_final; 65 | wire [31:0] D51_final; 66 | wire [31:0] D52_final; 67 | wire [31:0] D53_final; 68 | wire [31:0] D54_final; 69 | wire [31:0] D55_final; 70 | wire [31:0] D56_final; 71 | wire [31:0] D57_final; 72 | wire [31:0] D58_final; 73 | wire [31:0] D61_final; 74 | wire [31:0] D62_final; 75 | wire [31:0] D63_final; 76 | wire [31:0] D64_final; 77 | wire [31:0] D65_final; 78 | wire [31:0] D66_final; 79 | wire [31:0] D67_final; 80 | wire [31:0] D68_final; 81 | wire [31:0] D71_final; 82 | wire [31:0] D72_final; 83 | wire [31:0] D73_final; 84 | wire [31:0] D74_final; 85 | wire [31:0] D75_final; 86 | wire [31:0] D76_final; 87 | wire [31:0] D77_final; 88 | wire [31:0] D78_final; 89 | wire [31:0] D81_final; 90 | wire [31:0] D82_final; 91 | wire [31:0] D83_final; 92 | wire [31:0] D84_final; 93 | wire [31:0] D85_final; 94 | wire [31:0] D86_final; 95 | wire [31:0] D87_final; 96 | wire [31:0] D88_final; 97 | 98 | // Instantiate the Unit Under Test (UUT) 99 | DiscreteCosineTransform uut ( 100 | .D11_final(D11_final), 101 | .D12_final(D12_final), 102 | .D13_final(D13_final), 103 | .D14_final(D14_final), 104 | .D15_final(D15_final), 105 | .D16_final(D16_final), 106 | .D17_final(D17_final), 107 | .D18_final(D18_final), 108 | .D21_final(D21_final), 109 | .D22_final(D22_final), 110 | .D23_final(D23_final), 111 | .D24_final(D24_final), 112 | .D25_final(D25_final), 113 | .D26_final(D26_final), 114 | .D27_final(D27_final), 115 | .D28_final(D28_final), 116 | .D31_final(D31_final), 117 | .D32_final(D32_final), 118 | .D33_final(D33_final), 119 | .D34_final(D34_final), 120 | .D35_final(D35_final), 121 | .D36_final(D36_final), 122 | .D37_final(D37_final), 123 | .D38_final(D38_final), 124 | .D41_final(D41_final), 125 | .D42_final(D42_final), 126 | .D43_final(D43_final), 127 | .D44_final(D44_final), 128 | .D45_final(D45_final), 129 | .D46_final(D46_final), 130 | .D47_final(D47_final), 131 | .D48_final(D48_final), 132 | .D51_final(D51_final), 133 | .D52_final(D52_final), 134 | .D53_final(D53_final), 135 | .D54_final(D54_final), 136 | .D55_final(D55_final), 137 | .D56_final(D56_final), 138 | .D57_final(D57_final), 139 | .D58_final(D58_final), 140 | .D61_final(D61_final), 141 | .D62_final(D62_final), 142 | .D63_final(D63_final), 143 | .D64_final(D64_final), 144 | .D65_final(D65_final), 145 | .D66_final(D66_final), 146 | .D67_final(D67_final), 147 | .D68_final(D68_final), 148 | .D71_final(D71_final), 149 | .D72_final(D72_final), 150 | .D73_final(D73_final), 151 | .D74_final(D74_final), 152 | .D75_final(D75_final), 153 | .D76_final(D76_final), 154 | .D77_final(D77_final), 155 | .D78_final(D78_final), 156 | .D81_final(D81_final), 157 | .D82_final(D82_final), 158 | .D83_final(D83_final), 159 | .D84_final(D84_final), 160 | .D85_final(D85_final), 161 | .D86_final(D86_final), 162 | .D87_final(D87_final), 163 | .D88_final(D88_final), 164 | .datain(datain), 165 | .clk(clk), 166 | .reset(reset) 167 | ); 168 | 169 | initial begin 170 | // Initialize Inputs 171 | datain = 0; 172 | clk = 0; 173 | reset = 0; 174 | 175 | 176 | 177 | // Wait 100 ns for global reset to finish 178 | #100; 179 | 180 | datain=16'b0001110000000000; 181 | #1000; 182 | datain=16'b0010000000000000; 183 | #1000; 184 | datain=16'b0001110000000000; 185 | #1000; 186 | datain=16'b0010000000000000; 187 | #1000; 188 | datain=16'b0001110000000000; 189 | #1000; 190 | datain=16'b0001101100000000; 191 | #1000; 192 | datain=16'b0001110000000000; 193 | #1000; 194 | datain=16'b0001111100000000; 195 | #1000; 196 | 197 | datain=16'b0001111100000000; 198 | #1000; 199 | datain=16'b0001101000000000; 200 | #1000; 201 | datain=16'b0001111100000000; 202 | #1000; 203 | datain=16'b0001101000000000; 204 | #1000; 205 | datain=16'b0001100100000000; 206 | #1000; 207 | datain=16'b0001101100000000; 208 | #1000; 209 | datain=16'b0001100100000000; 210 | #1000; 211 | datain=16'b0001111100000000; 212 | #1000; 213 | 214 | datain=16'b0001111000000000; 215 | #1000; 216 | datain=16'b0001110100000000; 217 | #1000; 218 | datain=16'b0001111000000000; 219 | #1000; 220 | datain=16'b0001110100000000; 221 | #1000; 222 | datain=16'b0001101100000000; 223 | #1000; 224 | datain=16'b0001101100000000; 225 | #1000; 226 | datain=16'b0001110100000000; 227 | #1000; 228 | datain=16'b0001110000000000; 229 | #1000; 230 | 231 | datain=16'b0001101100000000; 232 | #1000; 233 | datain=16'b0001111000000000; 234 | #1000; 235 | datain=16'b0001101100000000; 236 | #1000; 237 | datain=16'b0001111000000000; 238 | #1000; 239 | datain=16'b0001111100000000; 240 | #1000; 241 | datain=16'b0001110100000000; 242 | #1000; 243 | datain=16'b0001110000000000; 244 | #1000; 245 | datain=16'b0001111000000000; 246 | #1000; 247 | 248 | datain=16'b0001111000000000; 249 | #1000; 250 | datain=16'b0001110100000000; 251 | #1000; 252 | datain=16'b0001111000000000; 253 | #1000; 254 | datain=16'b0001110100000000; 255 | #1000; 256 | datain=16'b0001111100000000; 257 | #1000; 258 | datain=16'b0001110000000000; 259 | #1000; 260 | datain=16'b0001100100000000; 261 | #1000; 262 | datain=16'b0001110000000000; 263 | #1000; 264 | 265 | 266 | datain=16'b0001110000000000; 267 | #1000; 268 | datain=16'b0001111100000000; 269 | #1000; 270 | datain=16'b0001110000000000; 271 | #1000; 272 | datain=16'b0001111100000000; 273 | #1000; 274 | datain=16'b0001101100000000; 275 | #1000; 276 | datain=16'b0001111100000000; 277 | #1000; 278 | datain=16'b0001101100000000; 279 | #1000; 280 | datain=16'b0001111100000000; 281 | #1000; 282 | 283 | datain=16'b0001111100000000; 284 | #1000; 285 | datain=16'b0001111000000000; 286 | #1000; 287 | datain=16'b0001111100000000; 288 | #1000; 289 | datain=16'b0001111000000000; 290 | #1000; 291 | datain=16'b0001110000000000; 292 | #1000; 293 | datain=16'b0001100000000000; 294 | #1000; 295 | datain=16'b0001101000000000; 296 | #1000; 297 | datain=16'b0001110100000000; 298 | #1000; 299 | 300 | 301 | datain=16'b0001111000000000; 302 | #1000; 303 | datain=16'b0001111000000000; 304 | #1000; 305 | datain=16'b0001111000000000; 306 | #1000; 307 | datain=16'b0001111000000000; 308 | #1000; 309 | datain=16'b0001101100000000; 310 | #1000; 311 | datain=16'b0001111000000000; 312 | #1000; 313 | datain=16'b0001101100000000; 314 | #1000; 315 | datain=16'b0010000100000000; 316 | #1000; 317 | 318 | // Add stimulus here 319 | 320 | end 321 | always #500 clk = ~clk; 322 | 323 | endmodule 324 | 325 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/ndndn.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12:21:30 10/31/2017 7 | // Design Name: 8 | // Module Name: ndndn 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ndndn( 22 | ); 23 | 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /IMAGE_COMPRESSION_VERILOG/test_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 19:04:40 10/31/2017 8 | // Design Name: Test 9 | // Module Name: C:/Users/Maharsh Suryawala/Desktop/Functions/IMG/test_tb.v 10 | // Project Name: IMG 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: Test 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module test_tb; 26 | 27 | // Inputs 28 | reg clk; 29 | 30 | // Instantiate the Unit Under Test (UUT) 31 | Test uut ( 32 | .clk(clk) 33 | ); 34 | 35 | initial begin 36 | // Initialize Inputs 37 | clk = 0; 38 | 39 | // Wait 100 ns for global reset to finish 40 | #100; 41 | 42 | // Add stimulus here 43 | 44 | end 45 | always #500 clk = ~clk; 46 | endmodule 47 | 48 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2020 Maharsh Suryawala 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Image-Compression 2 | 3 | ## Overview 4 | 5 | * Implementation of JPEG Image Compression algorithm with Lloyds-Max quantizer in MATLAB. 6 | * Implemented and tested on Xilinx Artix-7 FPGA. 7 | 8 | ![Algorthm](.images/jpeg_algo.png) 9 | 10 | ## Block Diagram 11 | 12 | ![Block Diagram](.images/block_diagram.png) 13 | 14 | ## LLOYDS-MAX ALGORITHM 15 | 16 | * Aim- Minimize data loss. 17 | * Assume that the number M of quantizer levels and the pdf fU (u) are given. 18 | 1. Choose an arbitrary initial set of M representation points a1 < a2 < ··· < aM. 19 | 2. For each j;1 ≤ j ≤ M−1, set bj = 1/2 (aj+1 + aj ). 20 | 3. For each j;1 ≤ j ≤ M, set aj equal to the conditional mean of U given U ∈ (bj−1, bj ] (where b0 and bM are taken to be −∞ and +∞ respectively). 21 | 4. Repeat steps (2) and (3) until further improvement in MSE is negligible; then stop. 22 | 23 | * The MSE decreases (or remains the same) for each execution of step (2) and step (3). 24 | * Since the MSE is nonnegative, it approaches some limit. 25 | * Thus if the algorithm terminates when the MSE improvement is less than some given ε > 0, then the algorithm must terminate after a finite number of iterations. 26 | 27 | ## Results 28 | 29 | ![lloys-max](.images/lm.png) 30 | 31 | ![compression](.images/compression.png) 32 | --------------------------------------------------------------------------------