├── Constraint └── h ├── README.md ├── Sims └── TestBench.v └── sources ├── ALU_decoder.v ├── Branch_controller.v ├── Controller.v ├── DATAPATH.v ├── DataMem.v ├── Extend.v ├── Hazard_unit.v ├── InstMem_icache.v ├── InstMemory.v ├── Jal_stall.v ├── Load_Unit.v ├── Main_decoder.v ├── Mux2to1.v ├── Mux4to1.v ├── PC_register.v ├── RISC_DATAPATH.v ├── RISC_V.v ├── RegEX_MM.v ├── RegID_EX.v ├── RegIF_ID.v ├── RegMM_WB.v ├── RegisterFile.v ├── Store_Unit.v ├── Store_delay.v ├── adder.v ├── alu.v ├── load_controller.v ├── mux8to1.v ├── mux8to1_result.v ├── register.v ├── stall_PC.v ├── stall_jal.v └── store_controller.v /Constraint/h: -------------------------------------------------------------------------------- 1 | hi 2 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Manish4403/RISC_V_with_ICACHE/HEAD/README.md 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