├── README.md ├── Sample ├── TSH_LIB.v ├── buff.v ├── sample.v ├── singlethread.v ├── tb.v ├── trng_drive.v ├── trng_fpga_define.v └── trng_fpga_top.v ├── trng ├── trng.srcs │ └── sources_1 │ │ └── ip │ │ └── xilinx_pll │ │ ├── clk_wiz_v5_3_1 │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ └── mmcm_pll_drp_func_us_pll.vh │ │ ├── doc │ │ └── clk_wiz_v5_3_changelog.txt │ │ ├── xilinx_pll.dcp │ │ ├── xilinx_pll.v │ │ ├── xilinx_pll.veo │ │ ├── xilinx_pll.xci │ │ ├── xilinx_pll.xdc │ │ ├── xilinx_pll.xml │ │ ├── xilinx_pll_board.xdc │ │ ├── xilinx_pll_clk_wiz.v │ │ ├── xilinx_pll_ooc.xdc │ │ ├── xilinx_pll_sim_netlist.v │ │ ├── xilinx_pll_sim_netlist.vhdl │ │ ├── xilinx_pll_stub.v │ │ └── xilinx_pll_stub.vhdl ├── trng.xpr ├── vivado.jou ├── vivado.log ├── vivado_300.backup.jou └── vivado_300.backup.log ├── trng_top.edf ├── trng_top.v ├── vivado.jou ├── vivado.log ├── vivado_45080.backup.jou ├── vivado_45080.backup.log ├── vivado_pid45080.str └── xdc └── trng.xdc /README.md: -------------------------------------------------------------------------------- 1 | # Sampling-Model 2 | Hardware of sampling model performing parallel MCMC 3 | -------------------------------------------------------------------------------- /Sample/TSH_LIB.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | module TSH_BUF(input A , output X); 3 | 4 | //`ifndef SYNTHESIS 5 | // assign #1 X = A; 6 | `define FPGA 7 | LUT6 #( 8 | .INIT(64'hffffffff00000000) 9 | ) LUT6_inst_tsh_buf ( 10 | .O(X_TMP), 11 | .I0(), 12 | .I1(), 13 | .I2(), 14 | .I3(), 15 | .I4(), 16 | .I5(A) 17 | ); 18 | assign #1 X= X_TMP; 19 | // assign #1 X = A; 20 | //`else 21 | // SEP_BUF_2 SEP_BUF_2(.A(A),.X(X)); 22 | //`endif 23 | 24 | endmodule 25 | 26 | ////////////////////////////////////////////////////////////////////// 27 | module TSH_MUX2(output X,input S,input D0,input D1); 28 | 29 | //`ifndef SYNTHESIS 30 | // assign #1 X = S ? D1 : D0; 31 | //`define FPGA 32 | // LUT6 #( 33 | // .INIT(64'hffff0000ff00ff00) 34 | // ) LUT6_inst_tsh_mux ( 35 | // .O(X_TMP), 36 | // .I0(), 37 | // .I1(), 38 | // .I2(), 39 | // .I3(D0), 40 | // .I4(D1), 41 | // .I5(S) 42 | // ); 43 | // 44 | //assign #1 X= X_TMP; 45 | assign #1 X = S ? D1 : D0; 46 | //`else 47 | // SEP_MUX2_2 SEP_MUX2_2(.X(X),.S(S),.D0(D0),D1(D1)); 48 | //`endif 49 | endmodule 50 | 51 | ////////////////////////////////////////////////////////////////////// 52 | module TSH_RO_AN2 (input A1, input A2, output X); 53 | 54 | //`ifndef SYNTHESIS 55 | // assign #1 X = A1 & A2; 56 | //`define FPGA 57 | // LUT6 #( 58 | // .INIT(64'hffff000000000000) 59 | // ) LUT6_inst_an2 ( 60 | // .O(X_TMP), 61 | // .I0(), 62 | // .I1(), 63 | // .I2(), 64 | // .I3(), 65 | // .I4(A1), 66 | // .I5(A2) 67 | // ); 68 | //assign #1 X= X_TMP; 69 | assign #1 X = A1 & A2; 70 | //`else 71 | // SEP_AN2_S_4 SEP_AN2_S_4(.A1(A1),.A2(A2),.X(X)); 72 | //`endif 73 | 74 | endmodule 75 | 76 | ////////////////////////////////////////////////////////////////////// 77 | module TSH_RO_INV (input A, output X); 78 | 79 | //`ifndef SYNTHESIS 80 | // assign #1 X = !A; 81 | //`define FPGA 82 | // LUT6 #( 83 | // .INIT(64'h00000000ffffffff) 84 | // ) LUT6_inst_inv ( 85 | // .O(X_TMP), 86 | // .I0(), 87 | // .I1(), 88 | // .I2(), 89 | // .I3(), 90 | // .I4(), 91 | // .I5(A) 92 | // ); 93 | //assign #1 X= X_TMP; 94 | assign #1 X = !A; 95 | //`else 96 | // SEP_INV_S_4 SEP_INV_S_4 (.A(andout),.X(a[0])); 97 | //`endif 98 | 99 | endmodule 100 | 101 | ////////////////////////////////////////////////////////////////////// 102 | module TSH_RO_DEL(input A, output X); 103 | 104 | //`ifndef SYNTHESIS 105 | // reg X_TMP; 106 | // always #(100+$random%15) X_TMP = A; 107 | // assign X = X_TMP; 108 | //`define FPGA 109 | reg X_TMP1; 110 | LUT6 #( 111 | .INIT(64'hffffffff00000000) 112 | //.INIT(64'h00000000ffffffff) 113 | ) LUT6_inst_del ( 114 | .O(X_TMP0), 115 | .I0(), 116 | .I1(), 117 | .I2(), 118 | .I3(), 119 | .I4(), 120 | .I5(A) 121 | ); 122 | always #(100+$random%15) X_TMP1= X_TMP0; 123 | assign #1 X= X_TMP1; 124 | //`else 125 | // SEP_DEL_L6_8 SEP_DEL_L6_8(.A(a[i]),.X(a[i+1])); 126 | //`endif 127 | endmodule 128 | 129 | ////////////////////////////////////////////////////////////////////// 130 | module TSH_RO_BUF(input A, output X); 131 | 132 | //`ifndef SYNTHESIS 133 | // assign #1 X = A; 134 | //`define FPGA 135 | LUT6 #( 136 | .INIT(64'hffffffff00000000) 137 | ) LUT6_inst_buf ( 138 | .O(X_TMP), 139 | .I0(), 140 | .I1(), 141 | .I2(), 142 | .I3(), 143 | .I4(), 144 | .I5(A) 145 | ); 146 | assign #1 X= X_TMP; 147 | // assign #1 X = A; 148 | //`else 149 | // SEP_BUF_S_10 SEP_BUF_S_10(.A(a[stage-1]),.X(ro_out)); 150 | //`endif 151 | 152 | endmodule 153 | 154 | 155 | -------------------------------------------------------------------------------- /Sample/buff.v: -------------------------------------------------------------------------------- 1 | //all 'size' means real size -1. 2 | `define PARA_SIZE 3 3 | `define PARA_PTR_SIZE 1 4 | `define STAT_WAIT 0 5 | `define STAT_READY 1 6 | `define STAT_FULL 2 7 | `define STAT_WRITE 3 8 | `define QUEUE_SIZE 7 9 | `define PTR_SIZE 2 10 | 11 | //needs improving: if one thread is empty, it should be filled first. 12 | 13 | module buff 14 | ( 15 | input clk_trng, 16 | input clk_sample, 17 | input rstn, 18 | input [31:0] data_I, 19 | 20 | input [`PARA_SIZE:0] rd, 21 | output [`PARA_SIZE:0] ready, 22 | output [32*(`PARA_SIZE+1)-1:0] data_O 23 | ); 24 | 25 | reg[1:0] state_I; 26 | 27 | reg [`PARA_SIZE:0] full; 28 | reg [31:0] queue [`PARA_SIZE:0][`QUEUE_SIZE:0]; 29 | reg [`PTR_SIZE:0] ptr_I [`PARA_SIZE:0]; 30 | wire [`PTR_SIZE:0] ptr_O [`PARA_SIZE:0]; 31 | wire empty[`PARA_SIZE:0]; 32 | wire [`PTR_SIZE:0] ptr_I_p1[`PARA_SIZE:0], ptr_I_p2[`PARA_SIZE:0]; 33 | 34 | generate 35 | genvar i; 36 | for(i = 0; i <= `PARA_SIZE; i = i+1) begin: gen_threads 37 | singlethread thread(.clk_sample(clk_sample), 38 | .rstn(rstn), 39 | .full(full[i]), 40 | .ptr_I(ptr_I[i]), 41 | .rd(rd[i]), 42 | .empty(empty[i]), 43 | .ready(ready[i]), 44 | .ptr_O(ptr_O[i]) 45 | ); 46 | assign data_O[(i+1)*32-1:i*32] = queue[i][ptr_O[i]]; 47 | assign ptr_I_p1[i] = ptr_I[i] + 1; 48 | assign ptr_I_p2[i] = ptr_I[i] + 2; 49 | end 50 | endgenerate 51 | 52 | /*singlethread thread1(.clk_sample(clk_sample), 53 | .rstn(rstn), 54 | .full(full[0]), 55 | .ptr_I(ptr_I[0]), 56 | .rd(rd[0]), 57 | .empty(empty[0]), 58 | .ready(ready[0]), 59 | .ptr_O(ptr_O[0]) 60 | ); 61 | 62 | singlethread thread2(.clk_sample(clk_sample), 63 | .rstn(rstn), 64 | .full(full[1]), 65 | .ptr_I(ptr_I[1]), 66 | .rd(rd[1]), 67 | .empty(empty[1]), 68 | .ready(ready[1]), 69 | .ptr_O(ptr_O[1]) 70 | ); 71 | 72 | assign data_O[31:0] = queue[0][ptr_O[0]]; 73 | assign data_O[63:32] = queue[1][ptr_O[1]]; 74 | 75 | 76 | assign ptr_I_p1[0] = ptr_I[0] + 1; 77 | assign ptr_I_p2[0] = ptr_I[0] + 2; 78 | assign ptr_I_p1[1] = ptr_I[1] + 1; 79 | assign ptr_I_p2[1] = ptr_I[1] + 2;*/ 80 | 81 | 82 | reg [`PARA_PTR_SIZE:0] para_ptr; 83 | integer j; 84 | 85 | always @(posedge clk_trng or negedge rstn) begin 86 | if(~rstn) begin 87 | 88 | for(j = 0; j <= `PARA_SIZE; j = j+1) 89 | ptr_I[j] <= -1; 90 | 91 | //ptr_I[0] <= -1; 92 | //ptr_I[1] <= -1; 93 | 94 | state_I <= `STAT_WAIT; 95 | para_ptr <= 0; 96 | full <= 0; 97 | end 98 | else begin 99 | case(state_I) 100 | `STAT_WAIT : begin 101 | if(full[para_ptr]) begin 102 | state_I <= `STAT_FULL; 103 | end 104 | else if(data_I == 32'h00000071) begin 105 | state_I <= `STAT_READY; 106 | end 107 | else begin 108 | state_I <= `STAT_WAIT; 109 | end 110 | end 111 | `STAT_READY : begin 112 | if(data_I == 32'h0280f76b) begin 113 | state_I <= `STAT_WRITE; 114 | end 115 | else begin 116 | state_I <= `STAT_READY; 117 | end 118 | end 119 | `STAT_WRITE : begin 120 | if(ptr_I_p2[para_ptr] == ptr_O[para_ptr]) begin 121 | state_I <= `STAT_WAIT; 122 | para_ptr <= (para_ptr == `PARA_SIZE) ? 0 : (para_ptr+1); 123 | full[para_ptr] <= 1; 124 | ptr_I[para_ptr] <= ptr_I[para_ptr] + 1; 125 | queue[para_ptr][(ptr_I[para_ptr]+1)&`QUEUE_SIZE] <= data_I; 126 | end 127 | else begin 128 | state_I <= `STAT_WAIT; 129 | para_ptr <= (para_ptr == `PARA_SIZE) ? 0 : (para_ptr+1); 130 | ptr_I[para_ptr] <= ptr_I[para_ptr] + 1; 131 | queue[para_ptr][(ptr_I[para_ptr]+1)&`QUEUE_SIZE] <= data_I; 132 | end 133 | end 134 | `STAT_FULL : begin 135 | if(ptr_I_p1[para_ptr] != ptr_O[para_ptr] || empty[para_ptr]) begin 136 | state_I <= `STAT_WAIT; 137 | full[para_ptr] <= 0; 138 | end 139 | else begin 140 | state_I <= `STAT_WAIT; 141 | para_ptr <= (para_ptr == `PARA_SIZE) ? 0 : (para_ptr+1); 142 | end 143 | end 144 | default : begin 145 | state_I <= `STAT_WAIT; 146 | end 147 | endcase 148 | end 149 | end 150 | 151 | 152 | endmodule 153 | -------------------------------------------------------------------------------- /Sample/sample.v: -------------------------------------------------------------------------------- 1 | //all 'size' is real size 2 | `define PARA_SIZE 4 // the number of rand_buff ports, the total number parallel FSMs is `PARA_SIZE*`BLOCKS_PER_32 3 | `define BIT_WID 8 4 | `define BLOCKS_PER_32 4 //32/BIT_WID 5 | `define POSSI_S 32 //the number of all possible states 6 | `define RESULT_SIZE 5 // log(2,POSSI_S) 7 | 8 | `define STAT_WAIT 0 9 | `define STAT_READ 1 10 | `define STAT_FINI 2 11 | module sample 12 | ( 13 | output [`PARA_SIZE-1:0] rand_rd, 14 | input [`PARA_SIZE-1:0] rand_ready, 15 | input [32*`PARA_SIZE-1:0] rand_data, 16 | 17 | input clk, 18 | input rstn, 19 | input enable, 20 | input [`BIT_WID*`POSSI_S-1:0] accu_distr, 21 | output done, 22 | output ready, 23 | output [`RESULT_SIZE*`PARA_SIZE*`BLOCKS_PER_32-1:0] result 24 | ); 25 | 26 | wire [`BLOCKS_PER_32-1:0] temp_rd [`PARA_SIZE-1:0]; 27 | wire [`PARA_SIZE*`BLOCKS_PER_32-1:0] finish; 28 | wire [`PARA_SIZE*`BLOCKS_PER_32-1:0] temp_ready; 29 | wire [`BIT_WID-1:0] rand [`PARA_SIZE-1:0][`BLOCKS_PER_32-1:0]; 30 | assign done = &finish; 31 | assign ready = &temp_ready; 32 | 33 | generate 34 | genvar k1, k2; 35 | for(k1 = 0; k1 < `PARA_SIZE; k1=k1+1) begin: ports 36 | 37 | assign rand_rd[k1] = &temp_rd[k1]; 38 | 39 | for(k2 = 0; k2 < `BLOCKS_PER_32; k2=k2+1) begin: blocks 40 | sample_FSM fsm( 41 | .clk(clk), 42 | .rstn(rstn), 43 | .done(done), 44 | .enable(enable), 45 | .rand_ready(rand_ready[k1]), 46 | .rand_data(rand_data[32*k1+`BIT_WID*(k2+1)-1:32*k1+`BIT_WID*k2]), 47 | 48 | .rand_rd(rand_rd[k1]), 49 | .temp_rd(temp_rd[k1][k2]), 50 | .finish(finish[k1*`BLOCKS_PER_32+k2]), 51 | .ready(temp_ready[k1*`BLOCKS_PER_32+k2]), 52 | .rand(rand[k1][k2]) //maybe prob 53 | ); 54 | sample_comb_32S comb_32s( 55 | .accu_distr(accu_distr), 56 | .rand(rand[k1][k2]), 57 | .result(result[`RESULT_SIZE*`BLOCKS_PER_32*k1+`RESULT_SIZE*(k2+1)-1:`RESULT_SIZE*`BLOCKS_PER_32*k1+`RESULT_SIZE*k2]) //unfinished 58 | ); 59 | end 60 | end 61 | endgenerate 62 | 63 | endmodule 64 | 65 | module sample_FSM 66 | ( 67 | input clk, 68 | input rstn, 69 | input done, 70 | input enable, 71 | input rand_ready, 72 | input[`BIT_WID-1:0] rand_data, 73 | 74 | input rand_rd, 75 | output temp_rd, 76 | output finish, 77 | output ready, 78 | output reg[`BIT_WID-1:0] rand 79 | ); 80 | 81 | reg [1:0] state; 82 | 83 | always @(posedge clk or negedge rstn) begin 84 | if(~rstn) begin 85 | state <= `STAT_WAIT; 86 | rand <= 0; 87 | end 88 | else begin 89 | case(state) 90 | `STAT_WAIT: begin 91 | if(enable&rand_ready) begin 92 | state <= `STAT_READ; 93 | rand <= rand_data; 94 | end 95 | else begin 96 | state <= `STAT_WAIT; 97 | end 98 | end 99 | `STAT_READ: begin 100 | if(rand_rd) begin 101 | state <= `STAT_FINI; 102 | end 103 | else begin 104 | state <= `STAT_READ; 105 | end 106 | end 107 | `STAT_FINI: begin 108 | if(done) begin 109 | state <= `STAT_WAIT; 110 | end 111 | else begin 112 | state <= `STAT_FINI; 113 | end 114 | end 115 | endcase 116 | end 117 | end 118 | 119 | assign ready = (state == `STAT_WAIT); 120 | assign temp_rd = (state == `STAT_READ); 121 | assign finish = (state == `STAT_FINI); 122 | endmodule 123 | 124 | module sample_comb_32S //only use for `POSSI_S == 32 125 | ( 126 | input[`BIT_WID*`POSSI_S-1:0] accu_distr, 127 | input[`BIT_WID-1:0] rand, 128 | output[`RESULT_SIZE-1:0] result 129 | ); 130 | 131 | wire[1:0] stage1 [15:0]; 132 | wire[2:0] stage2 [7:0]; 133 | wire[3:0] stage3 [3:0]; 134 | wire[4:0] stage4 [1:0]; 135 | 136 | assign stage1[1] = (rand>accu_distr[(2*1+1)*`BIT_WID-1:2*1*`BIT_WID]) + (rand>accu_distr[(2*1+2)*`BIT_WID-1:(2*1+1)*`BIT_WID]); 137 | 138 | generate 139 | genvar s1; 140 | for(s1 = 0; s1 < 16; s1=s1+1) begin: sta1 141 | assign stage1[s1] = (rand>accu_distr[(2*s1+1)*`BIT_WID-1:2*s1*`BIT_WID]) + (rand>accu_distr[(2*s1+2)*`BIT_WID-1:(2*s1+1)*`BIT_WID]); 142 | end 143 | endgenerate 144 | 145 | generate 146 | genvar s2; 147 | for(s2 = 0; s2 < 8; s2=s2+1) begin: sta2 148 | assign stage2[s2] = stage1[2*s2] + stage1[2*s2+1]; 149 | end 150 | endgenerate 151 | 152 | generate 153 | genvar s3; 154 | for(s3 = 0; s3 < 4; s3=s3+1) begin: sta3 155 | assign stage3[s3] = stage2[2*s3] + stage2[2*s3+1]; 156 | end 157 | endgenerate 158 | 159 | assign stage4[0] = stage3[0] + stage3[1]; 160 | assign stage4[1] = stage3[2] + stage3[3]; 161 | 162 | assign result = stage4[0] + stage4[1]; 163 | endmodule -------------------------------------------------------------------------------- /Sample/singlethread.v: -------------------------------------------------------------------------------- 1 | `define STAT_WAIT 0 2 | `define STAT_READY 1 3 | `define STAT_FULL 2 4 | `define STAT_WRITE 3 5 | `define QUEUE_SIZE 7 6 | `define PTR_SIZE 2 7 | 8 | module singlethread 9 | ( 10 | input clk_sample, 11 | input rstn, 12 | input full, 13 | input[`PTR_SIZE:0] ptr_I, 14 | input rd, 15 | 16 | output empty, 17 | output reg[`PTR_SIZE:0] ptr_O, 18 | output ready 19 | ); 20 | 21 | reg state; 22 | wire [`PTR_SIZE:0] ptr_I_p1, ptr_I_p2; 23 | assign ptr_I_p1 = ptr_I + 1; //if we directly write (ptr_I+2 == ptr_O) as a condition, it won't be triggered 24 | assign ptr_I_p2 = ptr_I + 2; 25 | 26 | always @(posedge clk_sample or negedge rstn) begin 27 | if(~rstn) begin 28 | state <= `STAT_WAIT; 29 | ptr_O <= 0; 30 | end 31 | else if(state == `STAT_WAIT) begin 32 | if(ptr_I_p1 != ptr_O || full) begin 33 | state <= `STAT_READY; 34 | end 35 | else begin 36 | state <= `STAT_WAIT; 37 | end 38 | end 39 | else if(state == `STAT_READY) begin 40 | if(~rd) begin 41 | state <= `STAT_READY; 42 | end 43 | else begin 44 | if(ptr_I == ptr_O) begin 45 | state <= `STAT_WAIT; 46 | ptr_O <= ptr_O + 1; 47 | end 48 | else begin 49 | state <= `STAT_READY; 50 | ptr_O <= ptr_O + 1; 51 | end 52 | end 53 | end 54 | end 55 | 56 | assign ready = (state == `STAT_READY); 57 | assign empty = (state == `STAT_WAIT); 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /Sample/tb.v: -------------------------------------------------------------------------------- 1 | //all 'size' is real size 2 | `define PARA_SIZE 4 // the number of rand_buff ports, the total number parallel FSMs is `PARA_SIZE*`BLOCKS_PER_32 3 | `define BIT_WID 8 4 | `define BLOCKS_PER_32 4 //32/BIT_WID 5 | `define POSSI_S 32 //the number of all possible states 6 | `define RESULT_SIZE 5 // log(2,POSSI_S) 7 | 8 | `define STAT_WAIT 0 9 | `define STAT_READ 1 10 | `define STAT_FINI 2 11 | 12 | module tb(input clk, 13 | 14 | input rstn, 15 | input [31:0] data_I, 16 | input enable, 17 | output[`RESULT_SIZE*`PARA_SIZE*`BLOCKS_PER_32-1:0] result, 18 | output done); 19 | 20 | wire [3:0] rd; 21 | wire [3:0] ready; 22 | wire [127:0] data_O; 23 | //reg [31:0] cnt; 24 | buff inst(.clk_trng(clk), 25 | .clk_sample(clk), 26 | .rstn(rstn), 27 | .rd(rd), 28 | .data_I(data_I), 29 | .data_O(data_O), 30 | .ready(ready)); 31 | 32 | // wire done; 33 | wire sam_ready; 34 | wire [`BIT_WID*`POSSI_S-1:0] accu_distr; 35 | // wire [`RESULT_SIZE*`PARA_SIZE*`BLOCKS_PER_32-1:0] result; 36 | 37 | generate 38 | genvar dis; 39 | for(dis = 0; dis < 32; dis = dis+1) begin: test_dis 40 | assign accu_distr[(dis+1)*`BIT_WID-1:dis*`BIT_WID] = (dis+1)*8-1; // uniform distribution 41 | end 42 | endgenerate 43 | 44 | sample ss1 45 | ( 46 | .rand_rd(rd), 47 | .rand_ready(ready), 48 | .rand_data(data_O), 49 | 50 | .clk(clk), 51 | .rstn(rstn), 52 | .enable(enable), 53 | .accu_distr(accu_distr), 54 | 55 | .done(done), 56 | .ready(sam_ready), 57 | .result(result) 58 | ); 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /Sample/trng_drive.v: -------------------------------------------------------------------------------- 1 | 2 | module trng_drive 3 | ( 4 | input CLK_I, 5 | input RESETN_I, 6 | input [31:0] RDATA_I, 7 | output reg SEL_O, 8 | output reg [31:0] ADDR_O, 9 | output reg WRITE_O, 10 | output reg [31:0] WDATA_O, 11 | output SCAN_MODE_O 12 | ); 13 | 14 | ////////////////////////////////////////////////////////////////////// 15 | // parameter 16 | ////////////////////////////////////////////////////////////////////// 17 | parameter S_IDLE = 3'b000; 18 | parameter S_RST_TRNG = 3'b001; 19 | parameter S_TRNG_EN = 3'b010; 20 | parameter S_TRNG_RUN = 3'b011; 21 | parameter S_RD_STAT = 3'b100; 22 | parameter S_RD_DATA = 3'b101; 23 | 24 | 25 | parameter DCS_TRNG_CTRL_ADDR = 16'h0000; // trng_start_ctrl 26 | parameter DCS_TRNG_BIT_ADDR_0 = 16'h0004; // Out_bit0_reg 27 | parameter DCS_TRNG_STATE_ADDR_0 = 16'h0008; // Out_state0 28 | parameter DCS_TRNG_BIT_ADDR_1 = 16'h000c; // Out_bit1_reg 29 | parameter DCS_TRNG_STATE_ADDR_1 = 16'h0010; // Out_state1 30 | parameter DCS_TRNG_BIT_ADDR_2 = 16'h0014; // Out_bit2_reg 31 | parameter DCS_TRNG_STATE_ADDR_2 = 16'h0018; // Out_state2 32 | parameter DCS_TRNG_BIT_ADDR_3 = 16'h001c; // Out_bit3_reg 33 | parameter DCS_TRNG_STATE_ADDR_3 = 16'h0020; // Out_state3 34 | parameter DCS_TRNG_BIT_XOR_ADDR = 16'h0024; // Out_bit_xor_reg 35 | parameter DCS_TRNG_STATE_CTRL_ADDR = 16'h0028; // Out_control 36 | 37 | parameter DCS_TRNG_RESET = 32'h0280f700; 38 | parameter DCS_TRNG_ENABLE = 32'h0280f70b; 39 | parameter DCS_TRNG_RUN = 32'h0280f76b; 40 | parameter DCS_TRNG_RD_EN = 32'h0280f77b; 41 | 42 | ////////////////////////////////////////////////////////////////////// 43 | // internal signal 44 | ////////////////////////////////////////////////////////////////////// 45 | reg [2:0] cur_state; 46 | reg [2:0] next_state; 47 | 48 | 49 | reg [7:0] srst_delay_cnt; 50 | reg [7:0] trng_rst_cnt; 51 | reg rd_stat_valid; 52 | reg trng_data_valid; 53 | wire srst_cnt_flag; 54 | wire trng_rst_finish; 55 | reg trng_rst; 56 | 57 | reg trng_rd_data_s0; 58 | reg trng_rd_data_s1; 59 | reg trng_rd_data_s2; 60 | reg trng_rd_data_s3; 61 | wire trng_rd_data_s; 62 | 63 | reg trng_enable; 64 | reg trng_run; 65 | reg trng_rdata_en; 66 | reg trng_rd_stat_en; 67 | 68 | assign SCAN_MODE_O = 1'b0; 69 | 70 | always @(posedge CLK_I or negedge RESETN_I) begin 71 | if(~RESETN_I) begin 72 | srst_delay_cnt <= 8'h0; 73 | end 74 | else if(~srst_cnt_flag)begin 75 | srst_delay_cnt <= srst_delay_cnt + 8'h1; 76 | end 77 | end 78 | 79 | assign srst_cnt_flag = &srst_delay_cnt; 80 | 81 | 82 | always @(posedge CLK_I or negedge RESETN_I) begin 83 | if(~RESETN_I) begin 84 | trng_rst_cnt <= 8'h0; 85 | end 86 | else if(trng_rst_finish)begin 87 | trng_rst_cnt <= trng_rst_cnt; 88 | end 89 | else if(~trng_rst)begin 90 | trng_rst_cnt<= trng_rst_cnt+ 8'h1; 91 | end 92 | end 93 | 94 | assign trng_rst_finish = &trng_rst_cnt; 95 | 96 | always @(posedge CLK_I or negedge RESETN_I) begin 97 | if(~RESETN_I) begin 98 | cur_state <= 3'h0; 99 | end 100 | else begin 101 | cur_state <= next_state; 102 | end 103 | end 104 | 105 | always @(*) begin 106 | next_state = S_IDLE; 107 | trng_rst = 1'b0; 108 | trng_enable = 1'b0; 109 | trng_run = 1'b0; 110 | trng_rdata_en = 1'b0; 111 | trng_rd_stat_en = 1'b0; 112 | case(cur_state) 113 | S_IDLE : begin 114 | if(srst_cnt_flag) begin 115 | next_state = S_RST_TRNG; 116 | trng_rst = 1'b1; 117 | end 118 | end 119 | S_RST_TRNG : begin 120 | if(trng_rst_finish) begin 121 | next_state = S_TRNG_EN; 122 | end 123 | else begin 124 | next_state = S_RST_TRNG; 125 | end 126 | end 127 | S_TRNG_EN : begin 128 | trng_enable = 1'b1; 129 | next_state = S_TRNG_RUN; 130 | end 131 | S_TRNG_RUN : begin 132 | trng_run = 1'b1; 133 | next_state = S_RD_STAT; 134 | end 135 | S_RD_STAT : begin 136 | if(trng_data_valid) begin 137 | trng_rdata_en = 1'b1; 138 | next_state = S_RD_DATA; 139 | end 140 | else begin 141 | trng_rd_stat_en = 1'b1; 142 | next_state = S_RD_STAT; 143 | end 144 | end 145 | S_RD_DATA : begin 146 | if(trng_rd_data_s3 ) begin 147 | next_state = S_RD_STAT; 148 | end 149 | else begin 150 | next_state = S_RD_DATA; 151 | end 152 | end 153 | default: begin 154 | next_state = S_IDLE; 155 | end 156 | endcase 157 | end 158 | 159 | always @(posedge CLK_I or negedge RESETN_I) begin 160 | if(~RESETN_I) begin 161 | end 162 | else begin 163 | end 164 | end 165 | 166 | 167 | 168 | always @(posedge CLK_I or negedge RESETN_I) begin 169 | if(~RESETN_I) begin 170 | trng_rd_data_s0 <= 1'b0; 171 | trng_rd_data_s1 <= 1'b0; 172 | trng_rd_data_s2 <= 1'b0; 173 | trng_rd_data_s3 <= 1'b0; 174 | end 175 | else begin 176 | trng_rd_data_s0 <= trng_rdata_en; 177 | trng_rd_data_s1 <= trng_rd_data_s0; 178 | trng_rd_data_s2 <= trng_rd_data_s1; 179 | trng_rd_data_s3 <= trng_rd_data_s2; 180 | end 181 | end 182 | 183 | assign trng_rd_data_s = trng_rd_data_s0 || trng_rd_data_s1 || trng_rd_data_s2; 184 | 185 | 186 | 187 | always @(posedge CLK_I or negedge RESETN_I) begin 188 | if(~RESETN_I) begin 189 | SEL_O <= 1'b0; 190 | end 191 | else if(trng_rst || trng_enable || trng_run || trng_rd_stat_en || trng_rd_data_s) begin 192 | SEL_O <= 1'b1; 193 | end 194 | else begin 195 | SEL_O <= 1'b0; 196 | end 197 | end 198 | 199 | always @(posedge CLK_I or negedge RESETN_I) begin 200 | if(~RESETN_I) begin 201 | WRITE_O <= 1'b0; 202 | end 203 | else if(trng_rst || trng_enable || trng_run || trng_rd_data_s0 || trng_rd_data_s2) begin 204 | WRITE_O <= 1'b1; 205 | end 206 | else begin 207 | WRITE_O <= 1'b0; 208 | end 209 | end 210 | 211 | always @(posedge CLK_I or negedge RESETN_I) begin 212 | if(~RESETN_I) begin 213 | ADDR_O <= 32'h0; 214 | end 215 | else if(trng_rst || trng_enable || trng_run) begin 216 | ADDR_O <= DCS_TRNG_CTRL_ADDR ; 217 | end 218 | else if(trng_rd_stat_en) begin 219 | ADDR_O <= DCS_TRNG_STATE_CTRL_ADDR; 220 | end 221 | else if(trng_rd_data_s0 || trng_rd_data_s2) begin 222 | ADDR_O <= DCS_TRNG_CTRL_ADDR ; 223 | end 224 | else if(trng_rd_data_s1 ) begin 225 | ADDR_O <= DCS_TRNG_BIT_XOR_ADDR; 226 | end 227 | end 228 | 229 | always @(posedge CLK_I or negedge RESETN_I) begin 230 | if(~RESETN_I) begin 231 | WDATA_O <= 32'h0; 232 | end 233 | else if(trng_rst) begin 234 | WDATA_O <= DCS_TRNG_RESET; 235 | end 236 | else if(trng_enable) begin 237 | WDATA_O <= DCS_TRNG_ENABLE; 238 | end 239 | else if(trng_run) begin 240 | WDATA_O <= DCS_TRNG_RUN; 241 | end 242 | else if(trng_rd_data_s0) begin 243 | WDATA_O <= DCS_TRNG_RD_EN; 244 | end 245 | else if(trng_rd_data_s2 ) begin 246 | WDATA_O <= DCS_TRNG_RUN; 247 | end 248 | end 249 | 250 | always @(posedge CLK_I or negedge RESETN_I) begin 251 | if(~RESETN_I) begin 252 | rd_stat_valid <= 1'b0; 253 | end 254 | else if(SEL_O && (ADDR_O == DCS_TRNG_STATE_CTRL_ADDR)) begin 255 | rd_stat_valid <= 1'b1; 256 | end 257 | else begin 258 | rd_stat_valid <= 1'b0; 259 | end 260 | end 261 | 262 | always @(posedge CLK_I or negedge RESETN_I) begin 263 | if(~RESETN_I) begin 264 | trng_data_valid <= 1'b0; 265 | end 266 | else if(rd_stat_valid &&(RDATA_I[2] == 1'b0))begin 267 | trng_data_valid <= 1'b1; 268 | end 269 | else begin 270 | trng_data_valid <= 1'b0; 271 | end 272 | end 273 | 274 | 275 | 276 | 277 | 278 | endmodule 279 | -------------------------------------------------------------------------------- /Sample/trng_fpga_define.v: -------------------------------------------------------------------------------- 1 | `define XILINX_FPGA 2 | -------------------------------------------------------------------------------- /Sample/trng_fpga_top.v: -------------------------------------------------------------------------------- 1 | //all 'size' is real size 2 | `define PARA_SIZE 4 // the number of rand_buff ports, the total number parallel FSMs is `PARA_SIZE*`BLOCKS_PER_32 3 | `define BIT_WID 8 4 | `define BLOCKS_PER_32 4 //32/BIT_WID 5 | `define POSSI_S 32 //the number of all possible states 6 | `define RESULT_SIZE 5 // log(2,POSSI_S) 7 | 8 | //`define STAT_WAIT 0 9 | `define STAT_READ 1 10 | `define STAT_FINI 2 11 | 12 | module trng_fpga_top( 13 | input clk_p_i, 14 | input clk_n_i, 15 | input reset_i 16 | // output done 17 | ); 18 | 19 | (*MARK_DEBUG = "TRUE"*) wire [31:0] rdata; 20 | wire sel; 21 | wire clk; 22 | wire [31:0] addr; 23 | wire [31:0] wdata; 24 | wire scan_mode; 25 | wire resetn; 26 | (*MARK_DEBUG = "TRUE"*) wire write; 27 | 28 | assign resetn = ~reset_i; 29 | 30 | `ifdef XILINX_FPGA 31 | wire locked; 32 | xilinx_pll u_xilinx_pll 33 | ( 34 | .clk_in1_p(clk_p_i), 35 | .clk_in1_n(clk_n_i), 36 | 37 | .clk_out1(clk), 38 | .reset(reset_i), 39 | .locked(locked) 40 | ); 41 | 42 | `else 43 | assign clk = clk_p_i; 44 | `endif 45 | 46 | 47 | trng_drive u_trng_drive 48 | ( 49 | .CLK_I(clk), 50 | .RESETN_I(resetn), 51 | .RDATA_I(rdata), 52 | .SEL_O(sel), 53 | .ADDR_O(addr), 54 | .WRITE_O(write), 55 | .WDATA_O(wdata), 56 | .SCAN_MODE_O(scan_mode) 57 | ); 58 | 59 | 60 | trng_top dut( 61 | .CLK_I (clk), 62 | .RESETN_I (resetn), 63 | 64 | .SEL_I (sel), //chip select 65 | .ADDR_I (addr), //address 66 | .WRITE_I (write), //1:write 0:read 67 | .WDATA_I (wdata), //write data 68 | .RDATA_I (rdata), //read data 69 | 70 | .SCAN_MODE_I (scan_mode) //scan mode enable 71 | ); 72 | 73 | 74 | wire [3:0] rd; 75 | (*MARK_DEBUG = "TRUE"*) wire [3:0] ready; 76 | wire [127:0] data_O; 77 | 78 | buff inst(.clk_trng(clk), 79 | .clk_sample(clk), 80 | .rstn(resetn), 81 | .rd(rd), 82 | .data_I(rdata), 83 | .data_O(data_O), 84 | .ready(ready)); 85 | 86 | //reg enable; 87 | wire sam_ready; 88 | wire [`BIT_WID*`POSSI_S-1:0] accu_distr; 89 | (*MARK_DEBUG = "TRUE"*) wire [`RESULT_SIZE*`PARA_SIZE*`BLOCKS_PER_32-1:0] result; 90 | (*MARK_DEBUG = "TRUE"*) wire done; 91 | 92 | generate 93 | genvar dis; 94 | for(dis = 0; dis < 32; dis = dis+1) begin: test_dis 95 | assign accu_distr[(dis+1)*`BIT_WID-1:dis*`BIT_WID] = (dis+1)*8-1; // uniform distribution, 2^`BIT_WID / `POSSI 96 | end 97 | endgenerate 98 | 99 | sample ss1 100 | ( 101 | .rand_rd(rd), 102 | .rand_ready(ready), 103 | .rand_data(data_O), 104 | 105 | .clk(clk), 106 | .rstn(resetn), 107 | .enable(1'b1), 108 | .accu_distr(accu_distr), 109 | 110 | .done(done), 111 | .ready(sam_ready), 112 | .result(result) 113 | ); 114 | 115 | 116 | endmodule 117 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/clk_wiz_v5_3_1/mmcm_pll_drp_func_7s_mmcm.vh: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Company: Xilinx 4 | // Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing 5 | // Date: 7/30/2014 6 | // Design Name: MMCME2 DRP 7 | // Module Name: mmcme2_drp_func.h 8 | // Version: 1.04 9 | // Target Devices: 7 Series || MMCM 10 | // Tool versions: 2014.3 11 | // Description: This header provides the functions necessary to 12 | // calculate the DRP register values for the V6 MMCM. 13 | // 14 | // Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR) 15 | // 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 16 | // 17 | // Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR 18 | // INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING 19 | // PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY 20 | // PROVIDING THIS DESIGN, CODE, OR INFORMATION AS 21 | // ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 22 | // APPLICATION OR STANDARD, XILINX IS MAKING NO 23 | // REPRESENTATION THAT THIS IMPLEMENTATION IS FREE 24 | // FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE 25 | // RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY 26 | // REQUIRE FOR YOUR IMPLEMENTATION. XILINX 27 | // EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH 28 | // RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, 29 | // INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 30 | // REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 31 | // FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES 32 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 33 | // PURPOSE. 34 | // 35 | // (c) Copyright 2009-2010 Xilinx, Inc. 36 | // All rights reserved. 37 | // 38 | /////////////////////////////////////////////////////////////////////////////// 39 | 40 | // These are user functions that should not be modified. Changes to the defines 41 | // or code within the functions may alter the accuracy of the calculations. 42 | 43 | // Define debug to provide extra messages durring elaboration 44 | //`define DEBUG 1 45 | 46 | // FRAC_PRECISION describes the width of the fractional portion of the fixed 47 | // point numbers. These should not be modified, they are for development 48 | // only 49 | `define FRAC_PRECISION 10 50 | // FIXED_WIDTH describes the total size for fixed point calculations(int+frac). 51 | // Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 52 | // greater than 32 53 | `define FIXED_WIDTH 32 54 | 55 | // This function takes a fixed point number and rounds it to the nearest 56 | // fractional precision bit. 57 | function [`FIXED_WIDTH:1] round_frac 58 | ( 59 | // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number 60 | input [`FIXED_WIDTH:1] decimal, 61 | 62 | // This describes the precision of the fraction, for example a value 63 | // of 1 would modify the fractional so that instead of being a .16 64 | // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) 65 | input [`FIXED_WIDTH:1] precision 66 | ); 67 | 68 | begin 69 | 70 | `ifdef DEBUG 71 | $display("round_frac - decimal: %h, precision: %h", decimal, precision); 72 | `endif 73 | // If the fractional precision bit is high then round up 74 | if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin 75 | round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); 76 | end else begin 77 | round_frac = decimal; 78 | end 79 | `ifdef DEBUG 80 | $display("round_frac: %h", round_frac); 81 | `endif 82 | end 83 | endfunction 84 | 85 | // This function calculates high_time, low_time, w_edge, and no_count 86 | // of a non-fractional counter based on the divide and duty cycle 87 | // 88 | // NOTE: high_time and low_time are returned as integers between 0 and 63 89 | // inclusive. 64 should equal 6'b000000 (in other words it is okay to 90 | // ignore the overflow) 91 | function [13:0] mmcm_pll_divider 92 | ( 93 | input [7:0] divide, // Max divide is 128 94 | input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 95 | ); 96 | 97 | reg [`FIXED_WIDTH:1] duty_cycle_fix; 98 | 99 | // High/Low time is initially calculated with a wider integer to prevent a 100 | // calculation error when it overflows to 64. 101 | reg [6:0] high_time; 102 | reg [6:0] low_time; 103 | reg w_edge; 104 | reg no_count; 105 | 106 | reg [`FIXED_WIDTH:1] temp; 107 | 108 | begin 109 | // Duty Cycle must be between 0 and 1,000 110 | if(duty_cycle <=0 || duty_cycle >= 100000) begin 111 | $display("ERROR: duty_cycle: %d is invalid", duty_cycle); 112 | $finish; 113 | end 114 | 115 | // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point 116 | duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; 117 | 118 | `ifdef DEBUG 119 | $display("duty_cycle_fix: %h", duty_cycle_fix); 120 | `endif 121 | 122 | // If the divide is 1 nothing needs to be set except the no_count bit. 123 | // Other values are dummies 124 | if(divide == 7'h01) begin 125 | high_time = 7'h01; 126 | w_edge = 1'b0; 127 | low_time = 7'h01; 128 | no_count = 1'b1; 129 | end else begin 130 | temp = round_frac(duty_cycle_fix*divide, 1); 131 | 132 | // comes from above round_frac 133 | high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 134 | // If the duty cycle * divide rounded is .5 or greater then this bit 135 | // is set. 136 | w_edge = temp[`FRAC_PRECISION]; // comes from round_frac 137 | 138 | // If the high time comes out to 0, it needs to be set to at least 1 139 | // and w_edge set to 0 140 | if(high_time == 7'h00) begin 141 | high_time = 7'h01; 142 | w_edge = 1'b0; 143 | end 144 | 145 | if(high_time == divide) begin 146 | high_time = divide - 1; 147 | w_edge = 1'b1; 148 | end 149 | 150 | // Calculate low_time based on the divide setting and set no_count to 151 | // 0 as it is only used when divide is 1. 152 | low_time = divide - high_time; 153 | no_count = 1'b0; 154 | end 155 | 156 | // Set the return value. 157 | mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; 158 | end 159 | endfunction 160 | 161 | // This function calculates mx, delay_time, and phase_mux 162 | // of a non-fractional counter based on the divide and phase 163 | // 164 | // NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux 165 | // is used. 166 | function [10:0] mmcm_pll_phase 167 | ( 168 | // divide must be an integer (use fractional if not) 169 | // assumed that divide already checked to be valid 170 | input [7:0] divide, // Max divide is 128 171 | 172 | // Phase is given in degrees (-360,000 to 360,000) 173 | input signed [31:0] phase 174 | ); 175 | 176 | reg [`FIXED_WIDTH:1] phase_in_cycles; 177 | reg [`FIXED_WIDTH:1] phase_fixed; 178 | reg [1:0] mx; 179 | reg [5:0] delay_time; 180 | reg [2:0] phase_mux; 181 | 182 | reg [`FIXED_WIDTH:1] temp; 183 | 184 | begin 185 | `ifdef DEBUG 186 | $display("mmcm_pll_phase-divide:%d,phase:%d", 187 | divide, phase); 188 | `endif 189 | 190 | if ((phase < -360000) || (phase > 360000)) begin 191 | $display("ERROR: phase of $phase is not between -360000 and 360000"); 192 | $finish; 193 | end 194 | 195 | // If phase is less than 0, convert it to a positive phase shift 196 | // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point 197 | if(phase < 0) begin 198 | phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; 199 | end else begin 200 | phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; 201 | end 202 | 203 | // Put phase in terms of decimal number of vco clock cycles 204 | phase_in_cycles = ( phase_fixed * divide ) / 360; 205 | 206 | `ifdef DEBUG 207 | $display("phase_in_cycles: %h", phase_in_cycles); 208 | `endif 209 | 210 | 211 | temp = round_frac(phase_in_cycles, 3); 212 | 213 | // set mx to 2'b00 that the phase mux from the VCO is enabled 214 | mx = 2'b00; 215 | phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; 216 | delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; 217 | 218 | `ifdef DEBUG 219 | $display("temp: %h", temp); 220 | `endif 221 | 222 | // Setup the return value 223 | mmcm_pll_phase={mx, phase_mux, delay_time}; 224 | end 225 | endfunction 226 | 227 | // This function takes the divide value and outputs the necessary lock values 228 | function [39:0] mmcm_pll_lock_lookup 229 | ( 230 | input [6:0] divide // Max divide is 64 231 | ); 232 | 233 | reg [2559:0] lookup; 234 | 235 | begin 236 | lookup = { 237 | // This table is composed of: 238 | // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt 239 | 40'b00110_00110_1111101000_1111101001_0000000001, 240 | 40'b00110_00110_1111101000_1111101001_0000000001, 241 | 40'b01000_01000_1111101000_1111101001_0000000001, 242 | 40'b01011_01011_1111101000_1111101001_0000000001, 243 | 40'b01110_01110_1111101000_1111101001_0000000001, 244 | 40'b10001_10001_1111101000_1111101001_0000000001, 245 | 40'b10011_10011_1111101000_1111101001_0000000001, 246 | 40'b10110_10110_1111101000_1111101001_0000000001, 247 | 40'b11001_11001_1111101000_1111101001_0000000001, 248 | 40'b11100_11100_1111101000_1111101001_0000000001, 249 | 40'b11111_11111_1110000100_1111101001_0000000001, 250 | 40'b11111_11111_1100111001_1111101001_0000000001, 251 | 40'b11111_11111_1011101110_1111101001_0000000001, 252 | 40'b11111_11111_1010111100_1111101001_0000000001, 253 | 40'b11111_11111_1010001010_1111101001_0000000001, 254 | 40'b11111_11111_1001110001_1111101001_0000000001, 255 | 40'b11111_11111_1000111111_1111101001_0000000001, 256 | 40'b11111_11111_1000100110_1111101001_0000000001, 257 | 40'b11111_11111_1000001101_1111101001_0000000001, 258 | 40'b11111_11111_0111110100_1111101001_0000000001, 259 | 40'b11111_11111_0111011011_1111101001_0000000001, 260 | 40'b11111_11111_0111000010_1111101001_0000000001, 261 | 40'b11111_11111_0110101001_1111101001_0000000001, 262 | 40'b11111_11111_0110010000_1111101001_0000000001, 263 | 40'b11111_11111_0110010000_1111101001_0000000001, 264 | 40'b11111_11111_0101110111_1111101001_0000000001, 265 | 40'b11111_11111_0101011110_1111101001_0000000001, 266 | 40'b11111_11111_0101011110_1111101001_0000000001, 267 | 40'b11111_11111_0101000101_1111101001_0000000001, 268 | 40'b11111_11111_0101000101_1111101001_0000000001, 269 | 40'b11111_11111_0100101100_1111101001_0000000001, 270 | 40'b11111_11111_0100101100_1111101001_0000000001, 271 | 40'b11111_11111_0100101100_1111101001_0000000001, 272 | 40'b11111_11111_0100010011_1111101001_0000000001, 273 | 40'b11111_11111_0100010011_1111101001_0000000001, 274 | 40'b11111_11111_0100010011_1111101001_0000000001, 275 | 40'b11111_11111_0011111010_1111101001_0000000001, 276 | 40'b11111_11111_0011111010_1111101001_0000000001, 277 | 40'b11111_11111_0011111010_1111101001_0000000001, 278 | 40'b11111_11111_0011111010_1111101001_0000000001, 279 | 40'b11111_11111_0011111010_1111101001_0000000001, 280 | 40'b11111_11111_0011111010_1111101001_0000000001, 281 | 40'b11111_11111_0011111010_1111101001_0000000001, 282 | 40'b11111_11111_0011111010_1111101001_0000000001, 283 | 40'b11111_11111_0011111010_1111101001_0000000001, 284 | 40'b11111_11111_0011111010_1111101001_0000000001, 285 | 40'b11111_11111_0011111010_1111101001_0000000001, 286 | 40'b11111_11111_0011111010_1111101001_0000000001, 287 | 40'b11111_11111_0011111010_1111101001_0000000001, 288 | 40'b11111_11111_0011111010_1111101001_0000000001, 289 | 40'b11111_11111_0011111010_1111101001_0000000001, 290 | 40'b11111_11111_0011111010_1111101001_0000000001, 291 | 40'b11111_11111_0011111010_1111101001_0000000001, 292 | 40'b11111_11111_0011111010_1111101001_0000000001, 293 | 40'b11111_11111_0011111010_1111101001_0000000001, 294 | 40'b11111_11111_0011111010_1111101001_0000000001, 295 | 40'b11111_11111_0011111010_1111101001_0000000001, 296 | 40'b11111_11111_0011111010_1111101001_0000000001, 297 | 40'b11111_11111_0011111010_1111101001_0000000001, 298 | 40'b11111_11111_0011111010_1111101001_0000000001, 299 | 40'b11111_11111_0011111010_1111101001_0000000001, 300 | 40'b11111_11111_0011111010_1111101001_0000000001, 301 | 40'b11111_11111_0011111010_1111101001_0000000001, 302 | 40'b11111_11111_0011111010_1111101001_0000000001 303 | }; 304 | 305 | // Set lookup_entry with the explicit bits from lookup with a part select 306 | mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; 307 | `ifdef DEBUG 308 | $display("lock_lookup: %b", mmcm_pll_lock_lookup); 309 | `endif 310 | end 311 | endfunction 312 | 313 | // This function takes the divide value and the bandwidth setting of the MMCM 314 | // and outputs the digital filter settings necessary. 315 | function [9:0] mmcm_pll_filter_lookup 316 | ( 317 | input [6:0] divide, // Max divide is 64 318 | input [8*9:0] BANDWIDTH 319 | ); 320 | 321 | reg [639:0] lookup_low; 322 | reg [639:0] lookup_high; 323 | 324 | reg [9:0] lookup_entry; 325 | 326 | begin 327 | lookup_low = { 328 | // CP_RES_LFHF 329 | 10'b0010_1111_00, 330 | 10'b0010_1111_00, 331 | 10'b0010_1111_00, 332 | 10'b0010_1111_00, 333 | 10'b0010_0111_00, 334 | 10'b0010_1011_00, 335 | 10'b0010_1101_00, 336 | 10'b0010_0011_00, 337 | 10'b0010_0101_00, 338 | 10'b0010_0101_00, 339 | 10'b0010_1001_00, 340 | 10'b0010_1110_00, 341 | 10'b0010_1110_00, 342 | 10'b0010_1110_00, 343 | 10'b0010_1110_00, 344 | 10'b0010_0001_00, 345 | 10'b0010_0001_00, 346 | 10'b0010_0001_00, 347 | 10'b0010_0110_00, 348 | 10'b0010_0110_00, 349 | 10'b0010_0110_00, 350 | 10'b0010_0110_00, 351 | 10'b0010_0110_00, 352 | 10'b0010_0110_00, 353 | 10'b0010_0110_00, 354 | 10'b0010_1010_00, 355 | 10'b0010_1010_00, 356 | 10'b0010_1010_00, 357 | 10'b0010_1010_00, 358 | 10'b0010_1010_00, 359 | 10'b0010_1100_00, 360 | 10'b0010_1100_00, 361 | 10'b0010_1100_00, 362 | 10'b0010_1100_00, 363 | 10'b0010_1100_00, 364 | 10'b0010_1100_00, 365 | 10'b0010_1100_00, 366 | 10'b0010_1100_00, 367 | 10'b0010_1100_00, 368 | 10'b0010_1100_00, 369 | 10'b0010_1100_00, 370 | 10'b0010_1100_00, 371 | 10'b0010_1100_00, 372 | 10'b0010_1100_00, 373 | 10'b0010_1100_00, 374 | 10'b0010_1100_00, 375 | 10'b0010_1100_00, 376 | 10'b0010_0010_00, 377 | 10'b0010_0010_00, 378 | 10'b0010_0010_00, 379 | 10'b0010_0010_00, 380 | 10'b0010_0010_00, 381 | 10'b0010_0010_00, 382 | 10'b0010_0010_00, 383 | 10'b0010_0010_00, 384 | 10'b0010_0010_00, 385 | 10'b0010_0010_00, 386 | 10'b0010_0010_00, 387 | 10'b0010_0010_00, 388 | 10'b0010_0010_00, 389 | 10'b0010_0010_00, 390 | 10'b0010_0010_00, 391 | 10'b0010_0010_00, 392 | 10'b0010_0010_00 393 | }; 394 | 395 | lookup_high = { 396 | // CP_RES_LFHF 397 | 10'b0010_1111_00, 398 | 10'b0100_1111_00, 399 | 10'b0101_1011_00, 400 | 10'b0111_0111_00, 401 | 10'b1101_0111_00, 402 | 10'b1110_1011_00, 403 | 10'b1110_1101_00, 404 | 10'b1111_0011_00, 405 | 10'b1110_0101_00, 406 | 10'b1111_0101_00, 407 | 10'b1111_1001_00, 408 | 10'b1101_0001_00, 409 | 10'b1111_1001_00, 410 | 10'b1111_1001_00, 411 | 10'b1111_1001_00, 412 | 10'b1111_1001_00, 413 | 10'b1111_0101_00, 414 | 10'b1111_0101_00, 415 | 10'b1100_0001_00, 416 | 10'b1100_0001_00, 417 | 10'b1100_0001_00, 418 | 10'b0101_1100_00, 419 | 10'b0101_1100_00, 420 | 10'b0101_1100_00, 421 | 10'b0101_1100_00, 422 | 10'b0011_0100_00, 423 | 10'b0011_0100_00, 424 | 10'b0011_0100_00, 425 | 10'b0011_0100_00, 426 | 10'b0011_0100_00, 427 | 10'b0011_0100_00, 428 | 10'b0011_0100_00, 429 | 10'b0011_0100_00, 430 | 10'b0011_0100_00, 431 | 10'b0011_0100_00, 432 | 10'b0011_0100_00, 433 | 10'b0011_0100_00, 434 | 10'b0011_0100_00, 435 | 10'b0011_0100_00, 436 | 10'b0011_0100_00, 437 | 10'b0011_0100_00, 438 | 10'b0010_1000_00, 439 | 10'b0010_1000_00, 440 | 10'b0010_1000_00, 441 | 10'b0010_1000_00, 442 | 10'b0010_1000_00, 443 | 10'b0111_0001_00, 444 | 10'b0111_0001_00, 445 | 10'b0100_1100_00, 446 | 10'b0100_1100_00, 447 | 10'b0100_1100_00, 448 | 10'b0100_1100_00, 449 | 10'b0110_0001_00, 450 | 10'b0110_0001_00, 451 | 10'b0101_0110_00, 452 | 10'b0101_0110_00, 453 | 10'b0101_0110_00, 454 | 10'b0010_0100_00, 455 | 10'b0010_0100_00, 456 | 10'b0010_0100_00, 457 | 10'b0010_0100_00, 458 | 10'b0100_1010_00, 459 | 10'b0011_1100_00, 460 | 10'b0011_1100_00 461 | }; 462 | 463 | // Set lookup_entry with the explicit bits from lookup with a part select 464 | if(BANDWIDTH == "LOW") begin 465 | // Low Bandwidth 466 | mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; 467 | end else begin 468 | // High or optimized bandwidth 469 | mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; 470 | end 471 | 472 | `ifdef DEBUG 473 | $display("filter_lookup: %b", mmcm_pll_filter_lookup); 474 | `endif 475 | end 476 | endfunction 477 | 478 | // This function takes in the divide, phase, and duty cycle 479 | // setting to calculate the upper and lower counter registers. 480 | function [37:0] mmcm_pll_count_calc 481 | ( 482 | input [7:0] divide, // Max divide is 128 483 | input signed [31:0] phase, 484 | input [31:0] duty_cycle // Multiplied by 100,000 485 | ); 486 | 487 | reg [13:0] div_calc; 488 | reg [16:0] phase_calc; 489 | 490 | begin 491 | `ifdef DEBUG 492 | $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", 493 | divide, phase, duty_cycle); 494 | `endif 495 | 496 | // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] 497 | div_calc = mmcm_pll_divider(divide, duty_cycle); 498 | // mx[10:9], pm[8:6], dt[5:0] 499 | phase_calc = mmcm_pll_phase(divide, phase); 500 | 501 | // Return value is the upper and lower address of counter 502 | // Upper address is: 503 | // RESERVED [31:26] 504 | // MX [25:24] 505 | // EDGE [23] 506 | // NOCOUNT [22] 507 | // DELAY_TIME [21:16] 508 | // Lower Address is: 509 | // PHASE_MUX [15:13] 510 | // RESERVED [12] 511 | // HIGH_TIME [11:6] 512 | // LOW_TIME [5:0] 513 | 514 | `ifdef DEBUG 515 | $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", 516 | divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 517 | div_calc[13], div_calc[12], 518 | phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); 519 | `endif 520 | 521 | mmcm_pll_count_calc = 522 | { 523 | // Upper Address 524 | 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 525 | // Lower Address 526 | phase_calc[8:6], 1'b0, div_calc[11:0] 527 | }; 528 | end 529 | endfunction 530 | 531 | 532 | // This function takes in the divide, phase, and duty cycle 533 | // setting to calculate the upper and lower counter registers. 534 | // for fractional multiply/divide functions. 535 | // 536 | // 537 | function [37:0] mmcm_frac_count_calc 538 | ( 539 | input [7:0] divide, // Max divide is 128 540 | input signed [31:0] phase, 541 | input [31:0] duty_cycle, // Multiplied by 1,000 542 | input [9:0] frac // Multiplied by 1000 543 | ); 544 | 545 | //Required for fractional divide calculations 546 | reg [7:0] lt_frac; 547 | reg [7:0] ht_frac; 548 | 549 | reg /*[7:0]*/ wf_fall_frac; 550 | reg /*[7:0]*/ wf_rise_frac; 551 | 552 | reg [31:0] a; 553 | reg [7:0] pm_rise_frac_filtered ; 554 | reg [7:0] pm_fall_frac_filtered ; 555 | reg [7:0] clkout0_divide_int; 556 | reg [2:0] clkout0_divide_frac; 557 | reg [7:0] even_part_high; 558 | reg [7:0] even_part_low; 559 | 560 | reg [7:0] odd; 561 | reg [7:0] odd_and_frac; 562 | 563 | reg [7:0] pm_fall; 564 | reg [7:0] pm_rise; 565 | reg [7:0] dt; 566 | reg [7:0] dt_int; 567 | reg [63:0] dt_calc; 568 | 569 | reg [7:0] pm_rise_frac; 570 | reg [7:0] pm_fall_frac; 571 | 572 | reg [31:0] a_per_in_octets; 573 | reg [31:0] a_phase_in_cycles; 574 | 575 | parameter precision = 0.125; 576 | 577 | reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 578 | reg [31: 0] phase_pos; 579 | reg [31: 0] phase_vco; 580 | reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 581 | reg [13:0] div_calc; 582 | reg [16:0] phase_calc; 583 | 584 | begin 585 | `ifdef DEBUG 586 | $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", 587 | divide, phase, duty_cycle); 588 | `endif 589 | 590 | //convert phase to fixed 591 | if ((phase < -360000) || (phase > 360000)) begin 592 | $display("ERROR: phase of $phase is not between -360000 and 360000"); 593 | $finish; 594 | end 595 | 596 | 597 | // Return value is 598 | // Transfer data 599 | // RESERVED [37:36] 600 | // FRAC_TIME [35:33] 601 | // FRAC_WF_FALL [32] 602 | // Upper address is: 603 | // RESERVED [31:26] 604 | // MX [25:24] 605 | // EDGE [23] 606 | // NOCOUNT [22] 607 | // DELAY_TIME [21:16] 608 | // Lower Address is: 609 | // PHASE_MUX [15:13] 610 | // RESERVED [12] 611 | // HIGH_TIME [11:6] 612 | // LOW_TIME [5:0] 613 | 614 | 615 | 616 | clkout0_divide_frac = frac / 125; 617 | clkout0_divide_int = divide; 618 | 619 | even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); 620 | even_part_low = even_part_high; 621 | 622 | odd = clkout0_divide_int - even_part_high - even_part_low; 623 | odd_and_frac = (8*odd) + clkout0_divide_frac; 624 | 625 | lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) 626 | ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) 627 | 628 | pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 629 | pm_rise = 0; //0 630 | 631 | wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 632 | wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) 633 | 634 | 635 | 636 | //Calculate phase in fractional cycles 637 | a_per_in_octets = (8 * divide) + (frac / 125) ; 638 | a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors 639 | pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; 640 | 641 | dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) 642 | dt = dt_calc[7:0]; 643 | 644 | pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; 645 | 646 | dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) 647 | pm_fall_frac = pm_fall + pm_rise_frac; 648 | pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; 649 | 650 | div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] 651 | phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} 652 | 653 | mmcm_frac_count_calc[37:0] = 654 | { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, 655 | 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 656 | pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] 657 | } ; 658 | 659 | `ifdef DEBUG 660 | $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); 661 | `endif 662 | 663 | end 664 | endfunction 665 | 666 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/clk_wiz_v5_3_1/mmcm_pll_drp_func_7s_pll.vh: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Company: Xilinx 4 | // Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing 5 | // Date: 7/30/2014 6 | // Design Name: PLLE2 DRP 7 | // Module Name: plle2_drp_func.h 8 | // Version: 2.00 9 | // Target Devices: 7 Series || PLL 10 | // Tool versions: 2014.3 11 | // Description: This header provides the functions necessary to 12 | // calculate the DRP register values for the V6 PLL. 13 | // Updated for CR663854. 14 | // 15 | // Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR 16 | // INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING 17 | // PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY 18 | // PROVIDING THIS DESIGN, CODE, OR INFORMATION AS 19 | // ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 20 | // APPLICATION OR STANDARD, XILINX IS MAKING NO 21 | // REPRESENTATION THAT THIS IMPLEMENTATION IS FREE 22 | // FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE 23 | // RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY 24 | // REQUIRE FOR YOUR IMPLEMENTATION. XILINX 25 | // EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH 26 | // RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, 27 | // INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 28 | // REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 29 | // FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES 30 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 | // PURPOSE. 32 | // 33 | // (c) Copyright 2009-2010 Xilinx, Inc. 34 | // All rights reserved. 35 | // 36 | /////////////////////////////////////////////////////////////////////////////// 37 | 38 | // These are user functions that should not be modified. Changes to the defines 39 | // or code within the functions may alter the accuracy of the calculations. 40 | 41 | // Define debug to provide extra messages durring elaboration 42 | //`define DEBUG 1 43 | 44 | // FRAC_PRECISION describes the width of the fractional portion of the fixed 45 | // point numbers. These should not be modified, they are for development 46 | // only 47 | `define FRAC_PRECISION 10 48 | // FIXED_WIDTH describes the total size for fixed point calculations(int+frac). 49 | // Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 50 | // greater than 32 51 | `define FIXED_WIDTH 32 52 | 53 | // This function takes a fixed point number and rounds it to the nearest 54 | // fractional precision bit. 55 | function [`FIXED_WIDTH:1] round_frac 56 | ( 57 | // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number 58 | input [`FIXED_WIDTH:1] decimal, 59 | 60 | // This describes the precision of the fraction, for example a value 61 | // of 1 would modify the fractional so that instead of being a .16 62 | // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) 63 | input [`FIXED_WIDTH:1] precision 64 | ); 65 | 66 | begin 67 | 68 | `ifdef DEBUG 69 | $display("round_frac - decimal: %h, precision: %h", decimal, precision); 70 | `endif 71 | // If the fractional precision bit is high then round up 72 | if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin 73 | round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); 74 | end else begin 75 | round_frac = decimal; 76 | end 77 | `ifdef DEBUG 78 | $display("round_frac: %h", round_frac); 79 | `endif 80 | end 81 | endfunction 82 | 83 | // This function calculates high_time, low_time, w_edge, and no_count 84 | // of a non-fractional counter based on the divide and duty cycle 85 | // 86 | // NOTE: high_time and low_time are returned as integers between 0 and 63 87 | // inclusive. 64 should equal 6'b000000 (in other words it is okay to 88 | // ignore the overflow) 89 | function [13:0] mmcm_pll_divider 90 | ( 91 | input [7:0] divide, // Max divide is 128 92 | input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 93 | ); 94 | 95 | reg [`FIXED_WIDTH:1] duty_cycle_fix; 96 | 97 | // High/Low time is initially calculated with a wider integer to prevent a 98 | // calculation error when it overflows to 64. 99 | reg [6:0] high_time; 100 | reg [6:0] low_time; 101 | reg w_edge; 102 | reg no_count; 103 | 104 | reg [`FIXED_WIDTH:1] temp; 105 | 106 | begin 107 | // Duty Cycle must be between 0 and 1,000 108 | if(duty_cycle <=0 || duty_cycle >= 100000) begin 109 | $display("ERROR: duty_cycle: %d is invalid", duty_cycle); 110 | $finish; 111 | end 112 | 113 | // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point 114 | duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; 115 | 116 | `ifdef DEBUG 117 | $display("duty_cycle_fix: %h", duty_cycle_fix); 118 | `endif 119 | 120 | // If the divide is 1 nothing needs to be set except the no_count bit. 121 | // Other values are dummies 122 | if(divide == 7'h01) begin 123 | high_time = 7'h01; 124 | w_edge = 1'b0; 125 | low_time = 7'h01; 126 | no_count = 1'b1; 127 | end else begin 128 | temp = round_frac(duty_cycle_fix*divide, 1); 129 | 130 | // comes from above round_frac 131 | high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 132 | // If the duty cycle * divide rounded is .5 or greater then this bit 133 | // is set. 134 | w_edge = temp[`FRAC_PRECISION]; // comes from round_frac 135 | 136 | // If the high time comes out to 0, it needs to be set to at least 1 137 | // and w_edge set to 0 138 | if(high_time == 7'h00) begin 139 | high_time = 7'h01; 140 | w_edge = 1'b0; 141 | end 142 | 143 | if(high_time == divide) begin 144 | high_time = divide - 1; 145 | w_edge = 1'b1; 146 | end 147 | 148 | // Calculate low_time based on the divide setting and set no_count to 149 | // 0 as it is only used when divide is 1. 150 | low_time = divide - high_time; 151 | no_count = 1'b0; 152 | end 153 | 154 | // Set the return value. 155 | mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; 156 | end 157 | endfunction 158 | 159 | // This function calculates mx, delay_time, and phase_mux 160 | // of a non-fractional counter based on the divide and phase 161 | // 162 | // NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux 163 | // is used. 164 | function [10:0] mmcm_pll_phase 165 | ( 166 | // divide must be an integer (use fractional if not) 167 | // assumed that divide already checked to be valid 168 | input [7:0] divide, // Max divide is 128 169 | 170 | // Phase is given in degrees (-360,000 to 360,000) 171 | input signed [31:0] phase 172 | ); 173 | 174 | reg [`FIXED_WIDTH:1] phase_in_cycles; 175 | reg [`FIXED_WIDTH:1] phase_fixed; 176 | reg [1:0] mx; 177 | reg [5:0] delay_time; 178 | reg [2:0] phase_mux; 179 | 180 | reg [`FIXED_WIDTH:1] temp; 181 | 182 | begin 183 | `ifdef DEBUG 184 | $display("mmcm_pll_phase-divide:%d,phase:%d", 185 | divide, phase); 186 | `endif 187 | 188 | if ((phase < -360000) || (phase > 360000)) begin 189 | $display("ERROR: phase of $phase is not between -360000 and 360000"); 190 | $finish; 191 | end 192 | 193 | // If phase is less than 0, convert it to a positive phase shift 194 | // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point 195 | if(phase < 0) begin 196 | phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; 197 | end else begin 198 | phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; 199 | end 200 | 201 | // Put phase in terms of decimal number of vco clock cycles 202 | phase_in_cycles = ( phase_fixed * divide ) / 360; 203 | 204 | `ifdef DEBUG 205 | $display("phase_in_cycles: %h", phase_in_cycles); 206 | `endif 207 | 208 | 209 | temp = round_frac(phase_in_cycles, 3); 210 | 211 | // set mx to 2'b00 that the phase mux from the VCO is enabled 212 | mx = 2'b00; 213 | phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; 214 | delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; 215 | 216 | `ifdef DEBUG 217 | $display("temp: %h", temp); 218 | `endif 219 | 220 | // Setup the return value 221 | mmcm_pll_phase={mx, phase_mux, delay_time}; 222 | end 223 | endfunction 224 | 225 | // This function takes the divide value and outputs the necessary lock values 226 | function [39:0] mmcm_pll_lock_lookup 227 | ( 228 | input [6:0] divide // Max divide is 64 229 | ); 230 | 231 | reg [2559:0] lookup; 232 | 233 | begin 234 | lookup = { 235 | // This table is composed of: 236 | // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt 237 | 40'b00110_00110_1111101000_1111101001_0000000001, 238 | 40'b00110_00110_1111101000_1111101001_0000000001, 239 | 40'b01000_01000_1111101000_1111101001_0000000001, 240 | 40'b01011_01011_1111101000_1111101001_0000000001, 241 | 40'b01110_01110_1111101000_1111101001_0000000001, 242 | 40'b10001_10001_1111101000_1111101001_0000000001, 243 | 40'b10011_10011_1111101000_1111101001_0000000001, 244 | 40'b10110_10110_1111101000_1111101001_0000000001, 245 | 40'b11001_11001_1111101000_1111101001_0000000001, 246 | 40'b11100_11100_1111101000_1111101001_0000000001, 247 | 40'b11111_11111_1110000100_1111101001_0000000001, 248 | 40'b11111_11111_1100111001_1111101001_0000000001, 249 | 40'b11111_11111_1011101110_1111101001_0000000001, 250 | 40'b11111_11111_1010111100_1111101001_0000000001, 251 | 40'b11111_11111_1010001010_1111101001_0000000001, 252 | 40'b11111_11111_1001110001_1111101001_0000000001, 253 | 40'b11111_11111_1000111111_1111101001_0000000001, 254 | 40'b11111_11111_1000100110_1111101001_0000000001, 255 | 40'b11111_11111_1000001101_1111101001_0000000001, 256 | 40'b11111_11111_0111110100_1111101001_0000000001, 257 | 40'b11111_11111_0111011011_1111101001_0000000001, 258 | 40'b11111_11111_0111000010_1111101001_0000000001, 259 | 40'b11111_11111_0110101001_1111101001_0000000001, 260 | 40'b11111_11111_0110010000_1111101001_0000000001, 261 | 40'b11111_11111_0110010000_1111101001_0000000001, 262 | 40'b11111_11111_0101110111_1111101001_0000000001, 263 | 40'b11111_11111_0101011110_1111101001_0000000001, 264 | 40'b11111_11111_0101011110_1111101001_0000000001, 265 | 40'b11111_11111_0101000101_1111101001_0000000001, 266 | 40'b11111_11111_0101000101_1111101001_0000000001, 267 | 40'b11111_11111_0100101100_1111101001_0000000001, 268 | 40'b11111_11111_0100101100_1111101001_0000000001, 269 | 40'b11111_11111_0100101100_1111101001_0000000001, 270 | 40'b11111_11111_0100010011_1111101001_0000000001, 271 | 40'b11111_11111_0100010011_1111101001_0000000001, 272 | 40'b11111_11111_0100010011_1111101001_0000000001, 273 | 40'b11111_11111_0011111010_1111101001_0000000001, 274 | 40'b11111_11111_0011111010_1111101001_0000000001, 275 | 40'b11111_11111_0011111010_1111101001_0000000001, 276 | 40'b11111_11111_0011111010_1111101001_0000000001, 277 | 40'b11111_11111_0011111010_1111101001_0000000001, 278 | 40'b11111_11111_0011111010_1111101001_0000000001, 279 | 40'b11111_11111_0011111010_1111101001_0000000001, 280 | 40'b11111_11111_0011111010_1111101001_0000000001, 281 | 40'b11111_11111_0011111010_1111101001_0000000001, 282 | 40'b11111_11111_0011111010_1111101001_0000000001, 283 | 40'b11111_11111_0011111010_1111101001_0000000001, 284 | 40'b11111_11111_0011111010_1111101001_0000000001, 285 | 40'b11111_11111_0011111010_1111101001_0000000001, 286 | 40'b11111_11111_0011111010_1111101001_0000000001, 287 | 40'b11111_11111_0011111010_1111101001_0000000001, 288 | 40'b11111_11111_0011111010_1111101001_0000000001, 289 | 40'b11111_11111_0011111010_1111101001_0000000001, 290 | 40'b11111_11111_0011111010_1111101001_0000000001, 291 | 40'b11111_11111_0011111010_1111101001_0000000001, 292 | 40'b11111_11111_0011111010_1111101001_0000000001, 293 | 40'b11111_11111_0011111010_1111101001_0000000001, 294 | 40'b11111_11111_0011111010_1111101001_0000000001, 295 | 40'b11111_11111_0011111010_1111101001_0000000001, 296 | 40'b11111_11111_0011111010_1111101001_0000000001, 297 | 40'b11111_11111_0011111010_1111101001_0000000001, 298 | 40'b11111_11111_0011111010_1111101001_0000000001, 299 | 40'b11111_11111_0011111010_1111101001_0000000001, 300 | 40'b11111_11111_0011111010_1111101001_0000000001 301 | }; 302 | 303 | // Set lookup_entry with the explicit bits from lookup with a part select 304 | mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; 305 | `ifdef DEBUG 306 | $display("lock_lookup: %b", mmcm_pll_lock_lookup); 307 | `endif 308 | end 309 | endfunction 310 | 311 | // This function takes the divide value and the bandwidth setting of the PLL 312 | // and outputs the digital filter settings necessary. 313 | function [9:0] mmcm_pll_filter_lookup 314 | ( 315 | input [6:0] divide, // Max divide is 64 316 | input [8*9:0] BANDWIDTH 317 | ); 318 | 319 | reg [639:0] lookup_low; 320 | reg [639:0] lookup_high; 321 | 322 | reg [9:0] lookup_entry; 323 | 324 | begin 325 | lookup_low = { 326 | // CP_RES_LFHF 327 | 10'b0010_1111_00, 328 | 10'b0010_1111_00, 329 | 10'b0010_0111_00, 330 | 10'b0010_1101_00, 331 | 10'b0010_0101_00, 332 | 10'b0010_0101_00, 333 | 10'b0010_1001_00, 334 | 10'b0010_1110_00, 335 | 10'b0010_1110_00, 336 | 10'b0010_0001_00, 337 | 10'b0010_0001_00, 338 | 10'b0010_0110_00, 339 | 10'b0010_0110_00, 340 | 10'b0010_0110_00, 341 | 10'b0010_0110_00, 342 | 10'b0010_1010_00, 343 | 10'b0010_1010_00, 344 | 10'b0010_1010_00, 345 | 10'b0010_1010_00, 346 | 10'b0010_1100_00, 347 | 10'b0010_1100_00, 348 | 10'b0010_1100_00, 349 | 10'b0010_1100_00, 350 | 10'b0010_1100_00, 351 | 10'b0010_1100_00, 352 | 10'b0010_1100_00, 353 | 10'b0010_1100_00, 354 | 10'b0010_1100_00, 355 | 10'b0010_1100_00, 356 | 10'b0010_1100_00, 357 | 10'b0010_0010_00, 358 | 10'b0010_0010_00, 359 | 10'b0010_0010_00, 360 | 10'b0010_0010_00, 361 | 10'b0010_0010_00, 362 | 10'b0010_0010_00, 363 | 10'b0010_0010_00, 364 | 10'b0010_0010_00, 365 | 10'b0010_0010_00, 366 | 10'b0010_0010_00, 367 | 10'b0011_1100_00, 368 | 10'b0011_1100_00, 369 | 10'b0011_1100_00, 370 | 10'b0011_1100_00, 371 | 10'b0011_1100_00, 372 | 10'b0011_1100_00, 373 | 10'b0011_1100_00, 374 | 10'b0010_0100_00, 375 | 10'b0010_0100_00, 376 | 10'b0010_0100_00, 377 | 10'b0010_0100_00, 378 | 10'b0010_0100_00, 379 | 10'b0010_0100_00, 380 | 10'b0010_0100_00, 381 | 10'b0010_0100_00, 382 | 10'b0010_0100_00, 383 | 10'b0010_0100_00, 384 | 10'b0010_0100_00, 385 | 10'b0010_0100_00, 386 | 10'b0010_0100_00, 387 | 10'b0010_0100_00, 388 | 10'b0010_0100_00, 389 | 10'b0010_0100_00, 390 | 10'b0010_0100_00 391 | }; 392 | 393 | lookup_high = { 394 | // CP_RES_LFHF 395 | 10'b0011_0111_00, 396 | 10'b0011_0111_00, 397 | 10'b0101_1111_00, 398 | 10'b0111_1111_00, 399 | 10'b0111_1011_00, 400 | 10'b1101_0111_00, 401 | 10'b1110_1011_00, 402 | 10'b1110_1101_00, 403 | 10'b1111_1101_00, 404 | 10'b1111_0111_00, 405 | 10'b1111_1011_00, 406 | 10'b1111_1101_00, 407 | 10'b1111_0011_00, 408 | 10'b1110_0101_00, 409 | 10'b1111_0101_00, 410 | 10'b1111_0101_00, 411 | 10'b1111_0101_00, 412 | 10'b1111_0101_00, 413 | 10'b0111_0110_00, 414 | 10'b0111_0110_00, 415 | 10'b0111_0110_00, 416 | 10'b0111_0110_00, 417 | 10'b0101_1100_00, 418 | 10'b0101_1100_00, 419 | 10'b0101_1100_00, 420 | 10'b1100_0001_00, 421 | 10'b1100_0001_00, 422 | 10'b1100_0001_00, 423 | 10'b1100_0001_00, 424 | 10'b1100_0001_00, 425 | 10'b1100_0001_00, 426 | 10'b1100_0001_00, 427 | 10'b1100_0001_00, 428 | 10'b0100_0010_00, 429 | 10'b0100_0010_00, 430 | 10'b0100_0010_00, 431 | 10'b0010_1000_00, 432 | 10'b0010_1000_00, 433 | 10'b0010_1000_00, 434 | 10'b0011_0100_00, 435 | 10'b0010_1000_00, 436 | 10'b0010_1000_00, 437 | 10'b0010_1000_00, 438 | 10'b0010_1000_00, 439 | 10'b0010_1000_00, 440 | 10'b0010_1000_00, 441 | 10'b0010_1000_00, 442 | 10'b0010_1000_00, 443 | 10'b0010_1000_00, 444 | 10'b0010_1000_00, 445 | 10'b0010_1000_00, 446 | 10'b0010_1000_00, 447 | 10'b0010_1000_00, 448 | 10'b0100_1100_00, 449 | 10'b0100_1100_00, 450 | 10'b0100_1100_00, 451 | 10'b0100_1100_00, 452 | 10'b0100_1100_00, 453 | 10'b0100_1100_00, 454 | 10'b0100_1100_00, 455 | 10'b0010_0100_00, 456 | 10'b0010_0100_00, 457 | 10'b0010_0100_00, 458 | 10'b0010_0100_00 459 | }; 460 | 461 | // Set lookup_entry with the explicit bits from lookup with a part select 462 | if(BANDWIDTH == "LOW") begin 463 | // Low Bandwidth 464 | mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; 465 | end else begin 466 | // High or optimized bandwidth 467 | mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; 468 | end 469 | 470 | `ifdef DEBUG 471 | $display("filter_lookup: %b", mmcm_pll_filter_lookup); 472 | `endif 473 | end 474 | endfunction 475 | 476 | // This function takes in the divide, phase, and duty cycle 477 | // setting to calculate the upper and lower counter registers. 478 | function [37:0] mmcm_pll_count_calc 479 | ( 480 | input [7:0] divide, // Max divide is 128 481 | input signed [31:0] phase, 482 | input [31:0] duty_cycle // Multiplied by 100,000 483 | ); 484 | 485 | reg [13:0] div_calc; 486 | reg [16:0] phase_calc; 487 | 488 | begin 489 | `ifdef DEBUG 490 | $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", 491 | divide, phase, duty_cycle); 492 | `endif 493 | 494 | // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] 495 | div_calc = mmcm_pll_divider(divide, duty_cycle); 496 | // mx[10:9], pm[8:6], dt[5:0] 497 | phase_calc = mmcm_pll_phase(divide, phase); 498 | 499 | // Return value is the upper and lower address of counter 500 | // Upper address is: 501 | // RESERVED [31:26] 502 | // MX [25:24] 503 | // EDGE [23] 504 | // NOCOUNT [22] 505 | // DELAY_TIME [21:16] 506 | // Lower Address is: 507 | // PHASE_MUX [15:13] 508 | // RESERVED [12] 509 | // HIGH_TIME [11:6] 510 | // LOW_TIME [5:0] 511 | 512 | `ifdef DEBUG 513 | $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", 514 | divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 515 | div_calc[13], div_calc[12], 516 | phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); 517 | `endif 518 | 519 | mmcm_pll_count_calc = 520 | { 521 | // Upper Address 522 | 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 523 | // Lower Address 524 | phase_calc[8:6], 1'b0, div_calc[11:0] 525 | }; 526 | end 527 | endfunction 528 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/clk_wiz_v5_3_1/mmcm_pll_drp_func_us_mmcm.vh: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Company: Xilinx 4 | // Engineer: Jim Tatsukawa 5 | // Date: 7/30/2014 6 | // Design Name: MMCME2 DRP 7 | // Module Name: mmcme2_drp_func.h 8 | // Version: 1.04 9 | // Target Devices: UltraScale Architecture || MMCM 10 | // Tool versions: 2014.3 11 | // Description: This header provides the functions necessary to 12 | // calculate the DRP register values for the V6 MMCM. 13 | // 14 | // Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR) 15 | // 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807 16 | // 17 | // Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR 18 | // INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING 19 | // PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY 20 | // PROVIDING THIS DESIGN, CODE, OR INFORMATION AS 21 | // ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 22 | // APPLICATION OR STANDARD, XILINX IS MAKING NO 23 | // REPRESENTATION THAT THIS IMPLEMENTATION IS FREE 24 | // FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE 25 | // RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY 26 | // REQUIRE FOR YOUR IMPLEMENTATION. XILINX 27 | // EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH 28 | // RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, 29 | // INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 30 | // REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 31 | // FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES 32 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 33 | // PURPOSE. 34 | // 35 | // (c) Copyright 2009-2010 Xilinx, Inc. 36 | // All rights reserved. 37 | // 38 | /////////////////////////////////////////////////////////////////////////////// 39 | 40 | // These are user functions that should not be modified. Changes to the defines 41 | // or code within the functions may alter the accuracy of the calculations. 42 | 43 | // Define debug to provide extra messages durring elaboration 44 | //`define DEBUG 1 45 | 46 | // FRAC_PRECISION describes the width of the fractional portion of the fixed 47 | // point numbers. These should not be modified, they are for development 48 | // only 49 | `define FRAC_PRECISION 10 50 | // FIXED_WIDTH describes the total size for fixed point calculations(int+frac). 51 | // Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 52 | // greater than 32 53 | `define FIXED_WIDTH 32 54 | 55 | // This function takes a fixed point number and rounds it to the nearest 56 | // fractional precision bit. 57 | function [`FIXED_WIDTH:1] round_frac 58 | ( 59 | // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number 60 | input [`FIXED_WIDTH:1] decimal, 61 | 62 | // This describes the precision of the fraction, for example a value 63 | // of 1 would modify the fractional so that instead of being a .16 64 | // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) 65 | input [`FIXED_WIDTH:1] precision 66 | ); 67 | 68 | begin 69 | 70 | `ifdef DEBUG 71 | $display("round_frac - decimal: %h, precision: %h", decimal, precision); 72 | `endif 73 | // If the fractional precision bit is high then round up 74 | if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin 75 | round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); 76 | end else begin 77 | round_frac = decimal; 78 | end 79 | `ifdef DEBUG 80 | $display("round_frac: %h", round_frac); 81 | `endif 82 | end 83 | endfunction 84 | 85 | // This function calculates high_time, low_time, w_edge, and no_count 86 | // of a non-fractional counter based on the divide and duty cycle 87 | // 88 | // NOTE: high_time and low_time are returned as integers between 0 and 63 89 | // inclusive. 64 should equal 6'b000000 (in other words it is okay to 90 | // ignore the overflow) 91 | function [13:0] mmcm_pll_divider 92 | ( 93 | input [7:0] divide, // Max divide is 128 94 | input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 95 | ); 96 | 97 | reg [`FIXED_WIDTH:1] duty_cycle_fix; 98 | 99 | // High/Low time is initially calculated with a wider integer to prevent a 100 | // calculation error when it overflows to 64. 101 | reg [6:0] high_time; 102 | reg [6:0] low_time; 103 | reg w_edge; 104 | reg no_count; 105 | 106 | reg [`FIXED_WIDTH:1] temp; 107 | 108 | begin 109 | // Duty Cycle must be between 0 and 1,000 110 | if(duty_cycle <=0 || duty_cycle >= 100000) begin 111 | $display("ERROR: duty_cycle: %d is invalid", duty_cycle); 112 | $finish; 113 | end 114 | 115 | // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point 116 | duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; 117 | 118 | `ifdef DEBUG 119 | $display("duty_cycle_fix: %h", duty_cycle_fix); 120 | `endif 121 | 122 | // If the divide is 1 nothing needs to be set except the no_count bit. 123 | // Other values are dummies 124 | if(divide == 7'h01) begin 125 | high_time = 7'h01; 126 | w_edge = 1'b0; 127 | low_time = 7'h01; 128 | no_count = 1'b1; 129 | end else begin 130 | temp = round_frac(duty_cycle_fix*divide, 1); 131 | 132 | // comes from above round_frac 133 | high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 134 | // If the duty cycle * divide rounded is .5 or greater then this bit 135 | // is set. 136 | w_edge = temp[`FRAC_PRECISION]; // comes from round_frac 137 | 138 | // If the high time comes out to 0, it needs to be set to at least 1 139 | // and w_edge set to 0 140 | if(high_time == 7'h00) begin 141 | high_time = 7'h01; 142 | w_edge = 1'b0; 143 | end 144 | 145 | if(high_time == divide) begin 146 | high_time = divide - 1; 147 | w_edge = 1'b1; 148 | end 149 | 150 | // Calculate low_time based on the divide setting and set no_count to 151 | // 0 as it is only used when divide is 1. 152 | low_time = divide - high_time; 153 | no_count = 1'b0; 154 | end 155 | 156 | // Set the return value. 157 | mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; 158 | end 159 | endfunction 160 | 161 | // This function calculates mx, delay_time, and phase_mux 162 | // of a non-fractional counter based on the divide and phase 163 | // 164 | // NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux 165 | // is used. 166 | function [10:0] mmcm_pll_phase 167 | ( 168 | // divide must be an integer (use fractional if not) 169 | // assumed that divide already checked to be valid 170 | input [7:0] divide, // Max divide is 128 171 | 172 | // Phase is given in degrees (-360,000 to 360,000) 173 | input signed [31:0] phase 174 | ); 175 | 176 | reg [`FIXED_WIDTH:1] phase_in_cycles; 177 | reg [`FIXED_WIDTH:1] phase_fixed; 178 | reg [1:0] mx; 179 | reg [5:0] delay_time; 180 | reg [2:0] phase_mux; 181 | 182 | reg [`FIXED_WIDTH:1] temp; 183 | 184 | begin 185 | `ifdef DEBUG 186 | $display("mmcm_pll_phase-divide:%d,phase:%d", 187 | divide, phase); 188 | `endif 189 | 190 | if ((phase < -360000) || (phase > 360000)) begin 191 | $display("ERROR: phase of $phase is not between -360000 and 360000"); 192 | $finish; 193 | end 194 | 195 | // If phase is less than 0, convert it to a positive phase shift 196 | // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point 197 | if(phase < 0) begin 198 | phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; 199 | end else begin 200 | phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; 201 | end 202 | 203 | // Put phase in terms of decimal number of vco clock cycles 204 | phase_in_cycles = ( phase_fixed * divide ) / 360; 205 | 206 | `ifdef DEBUG 207 | $display("phase_in_cycles: %h", phase_in_cycles); 208 | `endif 209 | 210 | 211 | temp = round_frac(phase_in_cycles, 3); 212 | 213 | // set mx to 2'b00 that the phase mux from the VCO is enabled 214 | mx = 2'b00; 215 | phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; 216 | delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; 217 | 218 | `ifdef DEBUG 219 | $display("temp: %h", temp); 220 | `endif 221 | 222 | // Setup the return value 223 | mmcm_pll_phase={mx, phase_mux, delay_time}; 224 | end 225 | endfunction 226 | 227 | // This function takes the divide value and outputs the necessary lock values 228 | function [39:0] mmcm_pll_lock_lookup 229 | ( 230 | input [6:0] divide // Max divide is 64 231 | ); 232 | 233 | reg [2559:0] lookup; 234 | 235 | begin 236 | lookup = { 237 | // This table is composed of: 238 | // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt 239 | 40'b00110_00110_1111101000_1111101001_0000000001, 240 | 40'b00110_00110_1111101000_1111101001_0000000001, 241 | 40'b01000_01000_1111101000_1111101001_0000000001, 242 | 40'b01011_01011_1111101000_1111101001_0000000001, 243 | 40'b01110_01110_1111101000_1111101001_0000000001, 244 | 40'b10001_10001_1111101000_1111101001_0000000001, 245 | 40'b10011_10011_1111101000_1111101001_0000000001, 246 | 40'b10110_10110_1111101000_1111101001_0000000001, 247 | 40'b11001_11001_1111101000_1111101001_0000000001, 248 | 40'b11100_11100_1111101000_1111101001_0000000001, 249 | 40'b11111_11111_1110000100_1111101001_0000000001, 250 | 40'b11111_11111_1100111001_1111101001_0000000001, 251 | 40'b11111_11111_1011101110_1111101001_0000000001, 252 | 40'b11111_11111_1010111100_1111101001_0000000001, 253 | 40'b11111_11111_1010001010_1111101001_0000000001, 254 | 40'b11111_11111_1001110001_1111101001_0000000001, 255 | 40'b11111_11111_1000111111_1111101001_0000000001, 256 | 40'b11111_11111_1000100110_1111101001_0000000001, 257 | 40'b11111_11111_1000001101_1111101001_0000000001, 258 | 40'b11111_11111_0111110100_1111101001_0000000001, 259 | 40'b11111_11111_0111011011_1111101001_0000000001, 260 | 40'b11111_11111_0111000010_1111101001_0000000001, 261 | 40'b11111_11111_0110101001_1111101001_0000000001, 262 | 40'b11111_11111_0110010000_1111101001_0000000001, 263 | 40'b11111_11111_0110010000_1111101001_0000000001, 264 | 40'b11111_11111_0101110111_1111101001_0000000001, 265 | 40'b11111_11111_0101011110_1111101001_0000000001, 266 | 40'b11111_11111_0101011110_1111101001_0000000001, 267 | 40'b11111_11111_0101000101_1111101001_0000000001, 268 | 40'b11111_11111_0101000101_1111101001_0000000001, 269 | 40'b11111_11111_0100101100_1111101001_0000000001, 270 | 40'b11111_11111_0100101100_1111101001_0000000001, 271 | 40'b11111_11111_0100101100_1111101001_0000000001, 272 | 40'b11111_11111_0100010011_1111101001_0000000001, 273 | 40'b11111_11111_0100010011_1111101001_0000000001, 274 | 40'b11111_11111_0100010011_1111101001_0000000001, 275 | 40'b11111_11111_0011111010_1111101001_0000000001, 276 | 40'b11111_11111_0011111010_1111101001_0000000001, 277 | 40'b11111_11111_0011111010_1111101001_0000000001, 278 | 40'b11111_11111_0011111010_1111101001_0000000001, 279 | 40'b11111_11111_0011111010_1111101001_0000000001, 280 | 40'b11111_11111_0011111010_1111101001_0000000001, 281 | 40'b11111_11111_0011111010_1111101001_0000000001, 282 | 40'b11111_11111_0011111010_1111101001_0000000001, 283 | 40'b11111_11111_0011111010_1111101001_0000000001, 284 | 40'b11111_11111_0011111010_1111101001_0000000001, 285 | 40'b11111_11111_0011111010_1111101001_0000000001, 286 | 40'b11111_11111_0011111010_1111101001_0000000001, 287 | 40'b11111_11111_0011111010_1111101001_0000000001, 288 | 40'b11111_11111_0011111010_1111101001_0000000001, 289 | 40'b11111_11111_0011111010_1111101001_0000000001, 290 | 40'b11111_11111_0011111010_1111101001_0000000001, 291 | 40'b11111_11111_0011111010_1111101001_0000000001, 292 | 40'b11111_11111_0011111010_1111101001_0000000001, 293 | 40'b11111_11111_0011111010_1111101001_0000000001, 294 | 40'b11111_11111_0011111010_1111101001_0000000001, 295 | 40'b11111_11111_0011111010_1111101001_0000000001, 296 | 40'b11111_11111_0011111010_1111101001_0000000001, 297 | 40'b11111_11111_0011111010_1111101001_0000000001, 298 | 40'b11111_11111_0011111010_1111101001_0000000001, 299 | 40'b11111_11111_0011111010_1111101001_0000000001, 300 | 40'b11111_11111_0011111010_1111101001_0000000001, 301 | 40'b11111_11111_0011111010_1111101001_0000000001, 302 | 40'b11111_11111_0011111010_1111101001_0000000001 303 | }; 304 | 305 | // Set lookup_entry with the explicit bits from lookup with a part select 306 | mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; 307 | `ifdef DEBUG 308 | $display("lock_lookup: %b", mmcm_pll_lock_lookup); 309 | `endif 310 | end 311 | endfunction 312 | 313 | // This function takes the divide value and the bandwidth setting of the MMCM 314 | // and outputs the digital filter settings necessary. 315 | function [9:0] mmcm_pll_filter_lookup 316 | ( 317 | input [6:0] divide, // Max divide is 64 318 | input [8*9:0] BANDWIDTH 319 | ); 320 | 321 | reg [639:0] lookup_low; 322 | reg [639:0] lookup_high; 323 | 324 | reg [9:0] lookup_entry; 325 | 326 | begin 327 | lookup_low = { 328 | // CP_RES_LFHF 329 | 10'b0010_1111_11, 330 | 10'b0010_1111_11, 331 | 10'b0010_1111_11, 332 | 10'b0010_1111_11, 333 | 10'b0010_1111_11, 334 | 10'b0010_1111_11, 335 | 10'b0010_0111_11, 336 | 10'b0010_0111_11, 337 | 10'b0010_0111_11, 338 | 10'b0010_1101_11, 339 | 10'b0010_1101_11, 340 | 10'b0010_1101_11, 341 | 10'b0010_0011_11, 342 | 10'b0010_0101_11, 343 | 10'b0010_0101_11, 344 | 10'b0010_0101_11, 345 | 10'b0010_1001_11, 346 | 10'b0010_1001_11, 347 | 10'b0010_1110_11, 348 | 10'b0010_1110_11, 349 | 10'b0010_1110_11, 350 | 10'b0010_1110_11, 351 | 10'b0010_1110_11, 352 | 10'b0010_1110_11, 353 | 10'b0010_0001_11, 354 | 10'b0010_0001_11, 355 | 10'b0010_0001_11, 356 | 10'b0010_0001_11, 357 | 10'b0010_0001_11, 358 | 10'b0010_0110_11, 359 | 10'b0010_0110_11, 360 | 10'b0010_0110_11, 361 | 10'b0010_0110_11, 362 | 10'b0010_0110_11, 363 | 10'b0010_0110_11, 364 | 10'b0010_0110_11, 365 | 10'b0010_0110_11, 366 | 10'b0010_0110_11, 367 | 10'b0010_0110_11, 368 | 10'b0010_1010_11, 369 | 10'b0010_1010_11, 370 | 10'b0010_1010_11, 371 | 10'b0010_1010_11, 372 | 10'b0010_1010_11, 373 | 10'b0010_1010_11, 374 | 10'b0010_1010_11, 375 | 10'b0010_1010_11, 376 | 10'b0010_1100_11, 377 | 10'b0010_1100_11, 378 | 10'b0010_1100_11, 379 | 10'b0010_1100_11, 380 | 10'b0010_1100_11, 381 | 10'b0010_1100_11, 382 | 10'b0010_1100_11, 383 | 10'b0010_1100_11, 384 | 10'b0010_1100_11, 385 | 10'b0010_1100_11, 386 | 10'b0010_1100_11, 387 | 10'b0010_1100_11, 388 | 10'b0010_1100_11, 389 | 10'b0010_1100_11, 390 | 10'b0010_1100_11, 391 | 10'b0010_1100_11, 392 | 10'b0010_1100_11 393 | }; 394 | 395 | lookup_high = { 396 | // CP_RES_LFHF 397 | 10'b0010_1111_11, 398 | 10'b0010_1111_11, 399 | 10'b0010_1011_11, 400 | 10'b0011_1111_11, 401 | 10'b0100_1111_11, 402 | 10'b0100_1111_11, 403 | 10'b0101_1111_11, 404 | 10'b0110_1111_11, 405 | 10'b0111_1111_11, 406 | 10'b0111_1111_11, 407 | 10'b1100_1111_11, 408 | 10'b1101_1111_11, 409 | 10'b1110_1111_11, 410 | 10'b1111_1111_11, 411 | 10'b1111_1111_11, 412 | 10'b1110_0111_11, 413 | 10'b1110_1011_11, 414 | 10'b1111_0111_11, 415 | 10'b1111_1011_11, 416 | 10'b1111_1011_11, 417 | 10'b1110_1101_11, 418 | 10'b1111_1101_11, 419 | 10'b1111_1101_11, 420 | 10'b1111_0011_11, 421 | 10'b1111_0011_11, 422 | 10'b1111_0011_11, 423 | 10'b1110_0101_11, 424 | 10'b1110_0101_11, 425 | 10'b1110_0101_11, 426 | 10'b1111_0101_11, 427 | 10'b1111_0101_11, 428 | 10'b1111_0101_11, 429 | 10'b1111_1001_11, 430 | 10'b1111_1001_11, 431 | 10'b1111_1001_11, 432 | 10'b1111_1001_11, 433 | 10'b1111_1001_11, 434 | 10'b1110_1110_11, 435 | 10'b1110_1110_11, 436 | 10'b1110_1110_11, 437 | 10'b1110_1110_11, 438 | 10'b1111_1110_11, 439 | 10'b1111_1110_11, 440 | 10'b1111_1110_11, 441 | 10'b1111_1110_11, 442 | 10'b1111_1110_11, 443 | 10'b1111_1110_11, 444 | 10'b1111_1110_11, 445 | 10'b1110_0001_11, 446 | 10'b1110_0001_11, 447 | 10'b1110_0001_11, 448 | 10'b1110_0001_11, 449 | 10'b1110_0001_11, 450 | 10'b1100_0110_11, 451 | 10'b1100_0110_11, 452 | 10'b1100_0110_11, 453 | 10'b1100_0110_11, 454 | 10'b1100_0110_11, 455 | 10'b1100_0110_11, 456 | 10'b1100_0110_11, 457 | 10'b1100_1010_11, 458 | 10'b1100_1010_11, 459 | 10'b1100_1010_11, 460 | 10'b1100_1010_11 461 | }; 462 | 463 | // Set lookup_entry with the explicit bits from lookup with a part select 464 | if(BANDWIDTH == "LOW") begin 465 | // Low Bandwidth 466 | mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10]; 467 | end else begin 468 | // High or optimized bandwidth 469 | mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10]; 470 | end 471 | 472 | `ifdef DEBUG 473 | $display("filter_lookup: %b", mmcm_pll_filter_lookup); 474 | `endif 475 | end 476 | endfunction 477 | 478 | // This function takes in the divide, phase, and duty cycle 479 | // setting to calculate the upper and lower counter registers. 480 | function [37:0] mmcm_pll_count_calc 481 | ( 482 | input [7:0] divide, // Max divide is 128 483 | input signed [31:0] phase, 484 | input [31:0] duty_cycle // Multiplied by 100,000 485 | ); 486 | 487 | reg [13:0] div_calc; 488 | reg [16:0] phase_calc; 489 | 490 | begin 491 | `ifdef DEBUG 492 | $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", 493 | divide, phase, duty_cycle); 494 | `endif 495 | 496 | // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] 497 | div_calc = mmcm_pll_divider(divide, duty_cycle); 498 | // mx[10:9], pm[8:6], dt[5:0] 499 | phase_calc = mmcm_pll_phase(divide, phase); 500 | 501 | // Return value is the upper and lower address of counter 502 | // Upper address is: 503 | // RESERVED [31:26] 504 | // MX [25:24] 505 | // EDGE [23] 506 | // NOCOUNT [22] 507 | // DELAY_TIME [21:16] 508 | // Lower Address is: 509 | // PHASE_MUX [15:13] 510 | // RESERVED [12] 511 | // HIGH_TIME [11:6] 512 | // LOW_TIME [5:0] 513 | 514 | `ifdef DEBUG 515 | $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", 516 | divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 517 | div_calc[13], div_calc[12], 518 | phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]); 519 | `endif 520 | 521 | mmcm_pll_count_calc = 522 | { 523 | // Upper Address 524 | 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 525 | // Lower Address 526 | phase_calc[8:6], 1'b0, div_calc[11:0] 527 | }; 528 | end 529 | endfunction 530 | 531 | 532 | // This function takes in the divide, phase, and duty cycle 533 | // setting to calculate the upper and lower counter registers. 534 | // for fractional multiply/divide functions. 535 | // 536 | // 537 | function [37:0] mmcm_frac_count_calc 538 | ( 539 | input [7:0] divide, // Max divide is 128 540 | input signed [31:0] phase, 541 | input [31:0] duty_cycle, // Multiplied by 1,000 542 | input [9:0] frac // Multiplied by 1000 543 | ); 544 | 545 | //Required for fractional divide calculations 546 | reg [7:0] lt_frac; 547 | reg [7:0] ht_frac; 548 | 549 | reg /*[7:0]*/ wf_fall_frac; 550 | reg /*[7:0]*/ wf_rise_frac; 551 | 552 | reg [31:0] a; 553 | reg [7:0] pm_rise_frac_filtered ; 554 | reg [7:0] pm_fall_frac_filtered ; 555 | reg [7:0] clkout0_divide_int; 556 | reg [2:0] clkout0_divide_frac; 557 | reg [7:0] even_part_high; 558 | reg [7:0] even_part_low; 559 | 560 | reg [7:0] odd; 561 | reg [7:0] odd_and_frac; 562 | 563 | reg [7:0] pm_fall; 564 | reg [7:0] pm_rise; 565 | reg [7:0] dt; 566 | reg [7:0] dt_int; 567 | reg [63:0] dt_calc; 568 | 569 | reg [7:0] pm_rise_frac; 570 | reg [7:0] pm_fall_frac; 571 | 572 | reg [31:0] a_per_in_octets; 573 | reg [31:0] a_phase_in_cycles; 574 | 575 | parameter precision = 0.125; 576 | 577 | reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 578 | reg [31: 0] phase_pos; 579 | reg [31: 0] phase_vco; 580 | reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 581 | reg [13:0] div_calc; 582 | reg [16:0] phase_calc; 583 | 584 | begin 585 | `ifdef DEBUG 586 | $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", 587 | divide, phase, duty_cycle); 588 | `endif 589 | 590 | //convert phase to fixed 591 | if ((phase < -360000) || (phase > 360000)) begin 592 | $display("ERROR: phase of $phase is not between -360000 and 360000"); 593 | $finish; 594 | end 595 | 596 | 597 | // Return value is 598 | // Transfer data 599 | // RESERVED [37:36] 600 | // FRAC_TIME [35:33] 601 | // FRAC_WF_FALL [32] 602 | // Upper address is: 603 | // RESERVED [31:26] 604 | // MX [25:24] 605 | // EDGE [23] 606 | // NOCOUNT [22] 607 | // DELAY_TIME [21:16] 608 | // Lower Address is: 609 | // PHASE_MUX [15:13] 610 | // RESERVED [12] 611 | // HIGH_TIME [11:6] 612 | // LOW_TIME [5:0] 613 | 614 | 615 | 616 | clkout0_divide_frac = frac / 125; 617 | clkout0_divide_int = divide; 618 | 619 | even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); 620 | even_part_low = even_part_high; 621 | 622 | odd = clkout0_divide_int - even_part_high - even_part_low; 623 | odd_and_frac = (8*odd) + clkout0_divide_frac; 624 | 625 | lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) 626 | ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) 627 | 628 | pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 629 | pm_rise = 0; //0 630 | 631 | wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807 632 | wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) 633 | 634 | 635 | 636 | //Calculate phase in fractional cycles 637 | a_per_in_octets = (8 * divide) + (frac / 125) ; 638 | a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors 639 | pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; 640 | 641 | dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) 642 | dt = dt_calc[7:0]; 643 | 644 | pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; 645 | 646 | dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) 647 | pm_fall_frac = pm_fall + pm_rise_frac; 648 | pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; 649 | 650 | div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] 651 | phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} 652 | 653 | mmcm_frac_count_calc[37:0] = 654 | { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, 655 | 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 656 | pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] 657 | } ; 658 | 659 | `ifdef DEBUG 660 | $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac); 661 | `endif 662 | 663 | end 664 | endfunction 665 | 666 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/clk_wiz_v5_3_1/mmcm_pll_drp_func_us_pll.vh: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Company: Xilinx 4 | // Engineer: Jim Tatsukawa 5 | // Date: 7/30/2014 6 | // Design Name: PLLE2 DRP 7 | // Module Name: plle2_drp_func.h 8 | // Version: 1.00 9 | // Target Devices: UltraScale Architecture || PLL 10 | // Tool versions: 2014.2 11 | // Description: This header provides the functions necessary to 12 | // calculate the DRP register values for the V6 PLL. 13 | // 14 | // Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419 15 | // 16 | // Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR 17 | // INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING 18 | // PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY 19 | // PROVIDING THIS DESIGN, CODE, OR INFORMATION AS 20 | // ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 21 | // APPLICATION OR STANDARD, XILINX IS MAKING NO 22 | // REPRESENTATION THAT THIS IMPLEMENTATION IS FREE 23 | // FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE 24 | // RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY 25 | // REQUIRE FOR YOUR IMPLEMENTATION. XILINX 26 | // EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH 27 | // RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, 28 | // INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 29 | // REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 30 | // FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES 31 | // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 | // PURPOSE. 33 | // 34 | // (c) Copyright 2009-2010 Xilinx, Inc. 35 | // All rights reserved. 36 | // 37 | /////////////////////////////////////////////////////////////////////////////// 38 | 39 | // These are user functions that should not be modified. Changes to the defines 40 | // or code within the functions may alter the accuracy of the calculations. 41 | 42 | // Define debug to provide extra messages durring elaboration 43 | //`define DEBUG 1 44 | 45 | // FRAC_PRECISION describes the width of the fractional portion of the fixed 46 | // point numbers. These should not be modified, they are for development 47 | // only 48 | `define FRAC_PRECISION 10 49 | // FIXED_WIDTH describes the total size for fixed point calculations(int+frac). 50 | // Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 51 | // greater than 32 52 | `define FIXED_WIDTH 32 53 | 54 | // This function takes a fixed point number and rounds it to the nearest 55 | // fractional precision bit. 56 | function [`FIXED_WIDTH:1] round_frac 57 | ( 58 | // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number 59 | input [`FIXED_WIDTH:1] decimal, 60 | 61 | // This describes the precision of the fraction, for example a value 62 | // of 1 would modify the fractional so that instead of being a .16 63 | // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) 64 | input [`FIXED_WIDTH:1] precision 65 | ); 66 | 67 | begin 68 | 69 | `ifdef DEBUG 70 | $display("round_frac - decimal: %h, precision: %h", decimal, precision); 71 | `endif 72 | // If the fractional precision bit is high then round up 73 | if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin 74 | round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); 75 | end else begin 76 | round_frac = decimal; 77 | end 78 | `ifdef DEBUG 79 | $display("round_frac: %h", round_frac); 80 | `endif 81 | end 82 | endfunction 83 | 84 | // This function calculates high_time, low_time, w_edge, and no_count 85 | // of a non-fractional counter based on the divide and duty cycle 86 | // 87 | // NOTE: high_time and low_time are returned as integers between 0 and 63 88 | // inclusive. 64 should equal 6'b000000 (in other words it is okay to 89 | // ignore the overflow) 90 | function [13:0] mmcm_pll_divider 91 | ( 92 | input [7:0] divide, // Max divide is 128 93 | input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 94 | ); 95 | 96 | reg [`FIXED_WIDTH:1] duty_cycle_fix; 97 | 98 | // High/Low time is initially calculated with a wider integer to prevent a 99 | // calculation error when it overflows to 64. 100 | reg [6:0] high_time; 101 | reg [6:0] low_time; 102 | reg w_edge; 103 | reg no_count; 104 | 105 | reg [`FIXED_WIDTH:1] temp; 106 | 107 | begin 108 | // Duty Cycle must be between 0 and 1,000 109 | if(duty_cycle <=0 || duty_cycle >= 100000) begin 110 | $display("ERROR: duty_cycle: %d is invalid", duty_cycle); 111 | $finish; 112 | end 113 | 114 | // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point 115 | duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; 116 | 117 | `ifdef DEBUG 118 | $display("duty_cycle_fix: %h", duty_cycle_fix); 119 | `endif 120 | 121 | // If the divide is 1 nothing needs to be set except the no_count bit. 122 | // Other values are dummies 123 | if(divide == 7'h01) begin 124 | high_time = 7'h01; 125 | w_edge = 1'b0; 126 | low_time = 7'h01; 127 | no_count = 1'b1; 128 | end else begin 129 | temp = round_frac(duty_cycle_fix*divide, 1); 130 | 131 | // comes from above round_frac 132 | high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 133 | // If the duty cycle * divide rounded is .5 or greater then this bit 134 | // is set. 135 | w_edge = temp[`FRAC_PRECISION]; // comes from round_frac 136 | 137 | // If the high time comes out to 0, it needs to be set to at least 1 138 | // and w_edge set to 0 139 | if(high_time == 7'h00) begin 140 | high_time = 7'h01; 141 | w_edge = 1'b0; 142 | end 143 | 144 | if(high_time == divide) begin 145 | high_time = divide - 1; 146 | w_edge = 1'b1; 147 | end 148 | 149 | // Calculate low_time based on the divide setting and set no_count to 150 | // 0 as it is only used when divide is 1. 151 | low_time = divide - high_time; 152 | no_count = 1'b0; 153 | end 154 | 155 | // Set the return value. 156 | mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; 157 | end 158 | endfunction 159 | 160 | // This function calculates mx, delay_time, and phase_mux 161 | // of a non-fractional counter based on the divide and phase 162 | // 163 | // NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux 164 | // is used. 165 | function [10:0] mmcm_pll_phase 166 | ( 167 | // divide must be an integer (use fractional if not) 168 | // assumed that divide already checked to be valid 169 | input [7:0] divide, // Max divide is 128 170 | 171 | // Phase is given in degrees (-360,000 to 360,000) 172 | input signed [31:0] phase 173 | ); 174 | 175 | reg [`FIXED_WIDTH:1] phase_in_cycles; 176 | reg [`FIXED_WIDTH:1] phase_fixed; 177 | reg [1:0] mx; 178 | reg [5:0] delay_time; 179 | reg [2:0] phase_mux; 180 | 181 | reg [`FIXED_WIDTH:1] temp; 182 | 183 | begin 184 | `ifdef DEBUG 185 | $display("mmcm_pll_phase-divide:%d,phase:%d", 186 | divide, phase); 187 | `endif 188 | 189 | if ((phase < -360000) || (phase > 360000)) begin 190 | $display("ERROR: phase of $phase is not between -360000 and 360000"); 191 | $finish; 192 | end 193 | 194 | // If phase is less than 0, convert it to a positive phase shift 195 | // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point 196 | if(phase < 0) begin 197 | phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; 198 | end else begin 199 | phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; 200 | end 201 | 202 | // Put phase in terms of decimal number of vco clock cycles 203 | phase_in_cycles = ( phase_fixed * divide ) / 360; 204 | 205 | `ifdef DEBUG 206 | $display("phase_in_cycles: %h", phase_in_cycles); 207 | `endif 208 | 209 | 210 | temp = round_frac(phase_in_cycles, 3); 211 | 212 | // set mx to 2'b00 that the phase mux from the VCO is enabled 213 | mx = 2'b00; 214 | phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; 215 | delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; 216 | 217 | `ifdef DEBUG 218 | $display("temp: %h", temp); 219 | `endif 220 | 221 | // Setup the return value 222 | mmcm_pll_phase={mx, phase_mux, delay_time}; 223 | end 224 | endfunction 225 | 226 | // This function takes the divide value and outputs the necessary lock values 227 | function [39:0] mmcm_pll_lock_lookup 228 | ( 229 | input [6:0] divide // Max divide is 64 230 | ); 231 | 232 | reg [2559:0] lookup; 233 | 234 | begin 235 | lookup = { 236 | // This table is composed of: 237 | // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt 238 | 40'b00110_00110_0111101000_0111101001_0000000001, //1 239 | 40'b00110_00110_0111101000_0111101001_0000000001, //2 240 | 40'b01000_01000_0111101000_0111101001_0000000001, //3 241 | 40'b01011_01011_0111101000_0111101001_0000000001, //4 242 | 40'b01110_01110_0111101000_0111101001_0000000001, //5 243 | 40'b10001_10001_0111101000_0111101001_0000000001, //6 244 | 40'b10011_10011_0111101000_0111101001_0000000001, //7 245 | 40'b10110_10110_0111101000_0111101001_0000000001, //8 246 | 40'b11001_11001_0111101000_0111101001_0000000001, //9 247 | 40'b11100_11100_0111101000_0111101001_0000000001, //10 248 | 40'b11111_11111_0110000100_0111101001_0000000001, //11 249 | 40'b11111_11111_0100111001_0111101001_0000000001, //12 250 | 40'b11111_11111_0111101110_0111101001_0000000001, //13 251 | 40'b11111_11111_0110111100_0111101001_0000000001, //14 252 | 40'b11111_11111_0110001010_0111101001_0000000001, //15 253 | 40'b11111_11111_0101110001_0111101001_0000000001, //16 254 | 40'b11111_11111_0100111111_0111101001_0000000001, //17 255 | 40'b11111_11111_0100100110_0111101001_0000000001, //18 256 | 40'b11111_11111_0100001101_0111101001_0000000001, //19 257 | 40'b11111_11111_0011110100_0111101001_0000000001, //20 258 | 40'b11111_11111_0011011011_0111101001_0000000001, //21 259 | 40'b11111_11111_0011000010_0111101001_0000000001, //22 260 | 40'b11111_11111_0010101001_0111101001_0000000001, //23 261 | 40'b11111_11111_0010010000_0111101001_0000000001, //24 262 | 40'b11111_11111_0010010000_0111101001_0000000001, //25 263 | 40'b11111_11111_0001110111_0111101001_0000000001, //26 264 | 40'b11111_11111_0001011110_0111101001_0000000001, //27 265 | 40'b11111_11111_0001011110_0111101001_0000000001, //28 266 | 40'b11111_11111_0001000101_0111101001_0000000001, //29 267 | 40'b11111_11111_0001000101_0111101001_0000000001, //30 268 | 40'b11111_11111_0000101100_0111101001_0000000001, //31 269 | 40'b11111_11111_0000101100_0111101001_0000000001, //32 270 | 40'b11111_11111_0000101100_0111101001_0000000001, //33 271 | 40'b11111_11111_0000010011_0111101001_0000000001, //34 272 | 40'b11111_11111_0000010011_0111101001_0000000001, //35 273 | 40'b11111_11111_0000010011_0111101001_0000000001, //36 274 | 40'b11111_11111_0011111010_0111101001_0000000001, //37 275 | 40'b11111_11111_0011111010_0111101001_0000000001, //38 276 | 40'b11111_11111_0011111010_0111101001_0000000001, //39 277 | 40'b11111_11111_0011111010_0111101001_0000000001, //40 278 | 40'b11111_11111_0011111010_0111101001_0000000001, //41 279 | 40'b11111_11111_0011111010_0111101001_0000000001, //42 280 | 40'b11111_11111_0011111010_0111101001_0000000001, //43 281 | 40'b11111_11111_0011111010_0111101001_0000000001, //44 282 | 40'b11111_11111_0011111010_0111101001_0000000001, //45 283 | 40'b11111_11111_0011111010_0111101001_0000000001, //46 284 | 40'b11111_11111_0011111010_0111101001_0000000001, //47 285 | 40'b11111_11111_0011111010_0111101001_0000000001, //48 286 | 40'b11111_11111_0011111010_0111101001_0000000001, //49 287 | 40'b11111_11111_0011111010_0111101001_0000000001, //50 288 | 40'b11111_11111_0011111010_0111101001_0000000001, //51 289 | 40'b11111_11111_0011111010_0111101001_0000000001, //52 290 | 40'b11111_11111_0011111010_0111101001_0000000001, //53 291 | 40'b11111_11111_0011111010_0111101001_0000000001, //54 292 | 40'b11111_11111_0011111010_0111101001_0000000001, //55 293 | 40'b11111_11111_0011111010_0111101001_0000000001, //56 294 | 40'b11111_11111_0011111010_0111101001_0000000001, //57 295 | 40'b11111_11111_0011111010_0111101001_0000000001, //58 296 | 40'b11111_11111_0011111010_0111101001_0000000001, //59 297 | 40'b11111_11111_0011111010_0111101001_0000000001, //60 298 | 40'b11111_11111_0011111010_0111101001_0000000001, //61 299 | 40'b11111_11111_0011111010_0111101001_0000000001, //62 300 | 40'b11111_11111_0011111010_0111101001_0000000001, //63 301 | 40'b11111_11111_0011111010_0111101001_0000000001 //64 302 | }; 303 | 304 | // Set lookup_entry with the explicit bits from lookup with a part select 305 | mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; 306 | `ifdef DEBUG 307 | $display("lock_lookup: %b", mmcm_pll_lock_lookup); 308 | `endif 309 | end 310 | endfunction 311 | 312 | // This function takes the divide value and the bandwidth setting of the PLL 313 | // and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3. 314 | function [9:0] mmcm_pll_filter_lookup 315 | ( 316 | input [6:0] divide // Max divide is 19 317 | ); 318 | 319 | reg [639:0] lookup; 320 | reg [9:0] lookup_entry; 321 | 322 | begin 323 | 324 | lookup = { 325 | // CP_RES_LFHF 326 | 10'b0010_1111_01, //1 327 | 10'b0010_0011_11, //2 328 | 10'b0011_0011_11, //3 329 | 10'b0010_0001_11, //4 330 | 10'b0010_0110_11, //5 331 | 10'b0010_1010_11, //6 332 | 10'b0010_1010_11, //7 333 | 10'b0011_0110_11, //8 334 | 10'b0010_1100_11, //9 335 | 10'b0010_1100_11, //10 336 | 10'b0010_1100_11, //11 337 | 10'b0010_0010_11, //12 338 | 10'b0011_1100_11, //13 339 | 10'b0011_1100_11, //14 340 | 10'b0011_1100_11, //15 341 | 10'b0011_1100_11, //16 342 | 10'b0011_0010_11, //17 343 | 10'b0011_0010_11, //18 344 | 10'b0011_0010_11 //19 345 | }; 346 | 347 | mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10]; 348 | 349 | `ifdef DEBUG 350 | $display("filter_lookup: %b", mmcm_pll_filter_lookup); 351 | `endif 352 | end 353 | endfunction 354 | 355 | // This function set the CLKOUTPHY divide settings to match 356 | // the desired CLKOUTPHY_MODE setting. To create VCO_X2, then 357 | // the CLKOUTPHY will be set to 2'b00 since the VCO is internally 358 | // doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10 359 | function [9:0] mmcm_pll_clkoutphy_calc 360 | ( 361 | input [8*9:0] CLKOUTPHY_MODE 362 | ); 363 | 364 | if(CLKOUTPHY_MODE == "VCO_X2") begin 365 | mmcm_pll_clkoutphy_calc= 2'b00; 366 | end else if(CLKOUTPHY_MODE == "VCO") begin 367 | mmcm_pll_clkoutphy_calc= 2'b01; 368 | end else if(CLKOUTPHY_MODE == "CLKIN") begin 369 | mmcm_pll_clkoutphy_calc= 2'b11; 370 | end else begin // Assume "VCO_HALF" 371 | mmcm_pll_clkoutphy_calc= 2'b10; 372 | end 373 | 374 | endfunction 375 | 376 | 377 | // This function takes in the divide, phase, and duty cycle 378 | // setting to calculate the upper and lower counter registers. 379 | function [37:0] mmcm_pll_count_calc 380 | ( 381 | input [7:0] divide, // Max divide is 128 382 | input signed [31:0] phase, 383 | input [31:0] duty_cycle // Multiplied by 100,000 384 | ); 385 | 386 | reg [13:0] div_calc; 387 | reg [16:0] phase_calc; 388 | 389 | begin 390 | `ifdef DEBUG 391 | $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", 392 | divide, phase, duty_cycle); 393 | `endif 394 | 395 | // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] 396 | div_calc = mmcm_pll_divider(divide, duty_cycle); 397 | // mx[10:9], pm[8:6], dt[5:0] 398 | phase_calc = mmcm_pll_phase(divide, phase); 399 | 400 | // Return value is the upper and lower address of counter 401 | // Upper address is: 402 | // RESERVED [31:26] 403 | // MX [25:24] 404 | // EDGE [23] 405 | // NOCOUNT [22] 406 | // DELAY_TIME [21:16] 407 | // Lower Address is: 408 | // PHASE_MUX [15:13] 409 | // RESERVED [12] 410 | // HIGH_TIME [11:6] 411 | // LOW_TIME [5:0] 412 | 413 | `ifdef DEBUG 414 | $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d", 415 | divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 416 | div_calc[13], div_calc[12], 417 | phase_calc[16:15], phase_calc[5:0], 3'b000);//phase_calc[14:12]); 418 | `endif 419 | 420 | mmcm_pll_count_calc = 421 | { 422 | // Upper Address 423 | 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 424 | // Lower Address 425 | phase_calc[8:6], 1'b0, div_calc[11:0] 426 | }; 427 | end 428 | endfunction 429 | 430 | 431 | // This function takes in the divide, phase, and duty cycle 432 | // setting to calculate the upper and lower counter registers. 433 | // for fractional multiply/divide functions. 434 | // 435 | // 436 | function [37:0] mmcm_pll_frac_count_calc 437 | ( 438 | input [7:0] divide, // Max divide is 128 439 | input signed [31:0] phase, 440 | input [31:0] duty_cycle, // Multiplied by 1,000 441 | input [9:0] frac // Multiplied by 1000 442 | ); 443 | 444 | //Required for fractional divide calculations 445 | reg [7:0] lt_frac; 446 | reg [7:0] ht_frac; 447 | 448 | reg /*[7:0]*/ wf_fall_frac; 449 | reg /*[7:0]*/ wf_rise_frac; 450 | 451 | reg [31:0] a; 452 | reg [7:0] pm_rise_frac_filtered ; 453 | reg [7:0] pm_fall_frac_filtered ; 454 | reg [7:0] clkout0_divide_int; 455 | reg [2:0] clkout0_divide_frac; 456 | reg [7:0] even_part_high; 457 | reg [7:0] even_part_low; 458 | 459 | reg [7:0] odd; 460 | reg [7:0] odd_and_frac; 461 | 462 | reg [7:0] pm_fall; 463 | reg [7:0] pm_rise; 464 | reg [7:0] dt; 465 | reg [7:0] dt_int; 466 | reg [63:0] dt_calc; 467 | 468 | reg [7:0] pm_rise_frac; 469 | reg [7:0] pm_fall_frac; 470 | 471 | reg [31:0] a_per_in_octets; 472 | reg [31:0] a_phase_in_cycles; 473 | 474 | parameter precision = 0.125; 475 | 476 | reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11 477 | reg [31: 0] phase_pos; 478 | reg [31: 0] phase_vco; 479 | reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11 480 | reg [13:0] div_calc; 481 | reg [16:0] phase_calc; 482 | 483 | begin 484 | `ifdef DEBUG 485 | $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d", 486 | divide, phase, duty_cycle); 487 | `endif 488 | 489 | //convert phase to fixed 490 | if ((phase < -360000) || (phase > 360000)) begin 491 | $display("ERROR: phase of $phase is not between -360000 and 360000"); 492 | $finish; 493 | end 494 | 495 | 496 | // Return value is 497 | // Transfer data 498 | // RESERVED [37:36] 499 | // FRAC_TIME [35:33] 500 | // FRAC_WF_FALL [32] 501 | // Upper address is: 502 | // RESERVED [31:26] 503 | // MX [25:24] 504 | // EDGE [23] 505 | // NOCOUNT [22] 506 | // DELAY_TIME [21:16] 507 | // Lower Address is: 508 | // PHASE_MUX [15:13] 509 | // RESERVED [12] 510 | // HIGH_TIME [11:6] 511 | // LOW_TIME [5:0] 512 | 513 | 514 | 515 | clkout0_divide_frac = frac / 125; 516 | clkout0_divide_int = divide; 517 | 518 | even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2); 519 | even_part_low = even_part_high; 520 | 521 | odd = clkout0_divide_int - even_part_high - even_part_low; 522 | odd_and_frac = (8*odd) + clkout0_divide_frac; 523 | 524 | lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1) 525 | ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1) 526 | 527 | pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 528 | pm_rise = 0; //0 529 | 530 | wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0) 531 | wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0) 532 | 533 | 534 | 535 | //Calculate phase in fractional cycles 536 | a_per_in_octets = (8 * divide) + (frac / 125) ; 537 | a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors 538 | pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000}; 539 | 540 | dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8) 541 | dt = dt_calc[7:0]; 542 | 543 | pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a; 544 | 545 | dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt) 546 | pm_fall_frac = pm_fall + pm_rise_frac; 547 | pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000}; 548 | 549 | div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6] 550 | phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]} 551 | 552 | mmcm_pll_frac_count_calc[37:0] = 553 | { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac, 554 | 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 555 | 3'b000, 1'b0, ht_frac[5:0],lt_frac[5:0] 556 | // pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] 557 | } ; 558 | 559 | `ifdef DEBUG 560 | $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac); 561 | `endif 562 | 563 | end 564 | endfunction 565 | 566 | 567 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/doc/clk_wiz_v5_3_changelog.txt: -------------------------------------------------------------------------------- 1 | 2016.2: 2 | * Version 5.3 (Rev. 1) 3 | * Internal register bit update, no effect on customer designs. 4 | 5 | 2016.1: 6 | * Version 5.3 7 | * Added Clock Monitor Feature as part of clocking wizard 8 | * DRP registers can be directly written through AXI without resource utilization 9 | * Changes to HDL library management to support Vivado IP simulation library 10 | 11 | 2015.4.2: 12 | * Version 5.2 (Rev. 1) 13 | * No changes 14 | 15 | 2015.4.1: 16 | * Version 5.2 (Rev. 1) 17 | * No changes 18 | 19 | 2015.4: 20 | * Version 5.2 (Rev. 1) 21 | * Internal device family change, no functional changes 22 | 23 | 2015.3: 24 | * Version 5.2 25 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 26 | * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported 27 | * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature 28 | * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format 29 | * Example design and simulation files are delivered in verilog only 30 | 31 | 2015.2.1: 32 | * Version 5.1 (Rev. 6) 33 | * No changes 34 | 35 | 2015.2: 36 | * Version 5.1 (Rev. 6) 37 | * No changes 38 | 39 | 2015.1: 40 | * Version 5.1 (Rev. 6) 41 | * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices 42 | * Supported devices and production status are now determined automatically, to simplify support for future devices 43 | 44 | 2014.4.1: 45 | * Version 5.1 (Rev. 5) 46 | * No changes 47 | 48 | 2014.4: 49 | * Version 5.1 (Rev. 5) 50 | * Internal device family change, no functional changes 51 | * updates related to the source selection based on board interface for zed board 52 | 53 | 2014.3: 54 | * Version 5.1 (Rev. 4) 55 | * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface 56 | 57 | 2014.2: 58 | * Version 5.1 (Rev. 3) 59 | * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 60 | 61 | 2014.1: 62 | * Version 5.1 (Rev. 2) 63 | * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock 64 | * Internal device family name change, no functional changes 65 | 66 | 2013.4: 67 | * Version 5.1 (Rev. 1) 68 | * Added support for Ultrascale devices 69 | * Updated Board Flow GUI to select the clock interfaces 70 | * Fixed issue with Stub file parameter error for BUFR output driver 71 | 72 | 2013.3: 73 | * Version 5.1 74 | * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL 75 | * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies 76 | * Fixed precision issues between displayed and actual frequencies 77 | * Added tool tips to GUI 78 | * Added Jitter and Phase error values to IP properties 79 | * Added support for Cadence IES and Synopsys VCS simulators 80 | * Reduced warnings in synthesis and simulation 81 | * Enhanced support for IP Integrator 82 | 83 | 2013.2: 84 | * Version 5.0 (Rev. 1) 85 | * Fixed issue with clock constraints for multiple instances of clocking wizard 86 | * Updated Life-Cycle status of devices 87 | 88 | 2013.1: 89 | * Version 5.0 90 | * Lower case ports for Verilog 91 | * Added Safe Clock Startup and Clock Sequencing 92 | 93 | (c) Copyright 2008 - 2016 Xilinx, Inc. All rights reserved. 94 | 95 | This file contains confidential and proprietary information 96 | of Xilinx, Inc. and is protected under U.S. and 97 | international copyright and other intellectual property 98 | laws. 99 | 100 | DISCLAIMER 101 | This disclaimer is not a license and does not grant any 102 | rights to the materials distributed herewith. Except as 103 | otherwise provided in a valid license issued to you by 104 | Xilinx, and to the maximum extent permitted by applicable 105 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 106 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 107 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 108 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 109 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 110 | (2) Xilinx shall not be liable (whether in contract or tort, 111 | including negligence, or under any other theory of 112 | liability) for any loss or damage of any kind or nature 113 | related to, arising under or in connection with these 114 | materials, including for any direct, or any indirect, 115 | special, incidental, or consequential loss or damage 116 | (including loss of data, profits, goodwill, or any type of 117 | loss or damage suffered as a result of any action brought 118 | by a third party) even if such damage or loss was 119 | reasonably foreseeable or Xilinx had been advised of the 120 | possibility of the same. 121 | 122 | CRITICAL APPLICATIONS 123 | Xilinx products are not designed or intended to be fail- 124 | safe, or for use in any application requiring fail-safe 125 | performance, such as life-support or safety devices or 126 | systems, Class III medical devices, nuclear facilities, 127 | applications related to the deployment of airbags, or any 128 | other applications that could lead to death, personal 129 | injury, or severe property or environmental damage 130 | (individually and collectively, "Critical 131 | Applications"). Customer assumes the sole risk and 132 | liability of any use of Xilinx products in Critical 133 | Applications, subject only to applicable laws and 134 | regulations governing limitations on product liability. 135 | 136 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 137 | PART OF THIS FILE AT ALL TIMES. 138 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MatrixAINetwork/Sampling-Model/79633a0de8b1432e0e17c7ad56800d3922596361/trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll.dcp -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll.v: -------------------------------------------------------------------------------- 1 | 2 | // file: xilinx_pll.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1____25.000______0.000______50.0______178.502____104.359 60 | // 61 | //---------------------------------------------------------------------------- 62 | // Input Clock Freq (MHz) Input Jitter (UI) 63 | //---------------------------------------------------------------------------- 64 | // __primary_________200.000____________0.010 65 | 66 | `timescale 1ps/1ps 67 | 68 | (* CORE_GENERATION_INFO = "xilinx_pll,clk_wiz_v5_3_1,{component_name=xilinx_pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=5.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 69 | 70 | module xilinx_pll 71 | ( 72 | // Clock in ports 73 | input clk_in1_p, 74 | input clk_in1_n, 75 | // Clock out ports 76 | output clk_out1, 77 | // Status and control signals 78 | input reset, 79 | output locked 80 | ); 81 | 82 | xilinx_pll_clk_wiz inst 83 | ( 84 | // Clock in ports 85 | .clk_in1_p(clk_in1_p), 86 | .clk_in1_n(clk_in1_n), 87 | // Clock out ports 88 | .clk_out1(clk_out1), 89 | // Status and control signals 90 | .reset(reset), 91 | .locked(locked) 92 | ); 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll.veo: -------------------------------------------------------------------------------- 1 | 2 | // 3 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //---------------------------------------------------------------------------- 50 | // User entered comments 51 | //---------------------------------------------------------------------------- 52 | // None 53 | // 54 | //---------------------------------------------------------------------------- 55 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 56 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 57 | //---------------------------------------------------------------------------- 58 | // clk_out1____25.000______0.000______50.0______178.502____104.359 59 | // 60 | //---------------------------------------------------------------------------- 61 | // Input Clock Freq (MHz) Input Jitter (UI) 62 | //---------------------------------------------------------------------------- 63 | // __primary_________200.000____________0.010 64 | 65 | // The following must be inserted into your Verilog file for this 66 | // core to be instantiated. Change the instance name and port connections 67 | // (in parentheses) to your own signal names. 68 | 69 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 70 | 71 | xilinx_pll instance_name 72 | ( 73 | // Clock in ports 74 | .clk_in1_p(clk_in1_p), // input clk_in1_p 75 | .clk_in1_n(clk_in1_n), // input clk_in1_n 76 | // Clock out ports 77 | .clk_out1(clk_out1), // output clk_out1 78 | // Status and control signals 79 | .reset(reset), // input reset 80 | .locked(locked)); // output locked 81 | // INST_TAG_END ------ End INSTANTIATION Template --------- 82 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: xilinx_pll.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # Input clock periods. These duplicate the values entered for the 52 | # input clocks. You can use these to time your system. If required 53 | # commented constraints can be used in the top level xdc 54 | #---------------------------------------------------------------- 55 | # Differential clock only needs one constraint 56 | create_clock -period 5.0 [get_ports clk_in1_p] 57 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1_p]] 0.05 58 | 59 | 60 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | set_property BOARD_PIN {clk_p} [get_ports clk_in1_p] 4 | set_property BOARD_PIN {clk_n} [get_ports clk_in1_n] 5 | set_property BOARD_PIN {reset} [get_ports reset] 6 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll_clk_wiz.v: -------------------------------------------------------------------------------- 1 | 2 | // file: xilinx_pll.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1____25.000______0.000______50.0______178.502____104.359 60 | // 61 | //---------------------------------------------------------------------------- 62 | // Input Clock Freq (MHz) Input Jitter (UI) 63 | //---------------------------------------------------------------------------- 64 | // __primary_________200.000____________0.010 65 | 66 | `timescale 1ps/1ps 67 | 68 | module xilinx_pll_clk_wiz 69 | 70 | (// Clock in ports 71 | input clk_in1_p, 72 | input clk_in1_n, 73 | // Clock out ports 74 | output clk_out1, 75 | // Status and control signals 76 | input reset, 77 | output locked 78 | ); 79 | // Input buffering 80 | //------------------------------------ 81 | wire clk_in1_xilinx_pll; 82 | wire clk_in2_xilinx_pll; 83 | IBUFDS clkin1_ibufgds 84 | (.O (clk_in1_xilinx_pll), 85 | .I (clk_in1_p), 86 | .IB (clk_in1_n)); 87 | 88 | 89 | // Clocking PRIMITIVE 90 | //------------------------------------ 91 | 92 | // Instantiation of the MMCM PRIMITIVE 93 | // * Unused inputs are tied off 94 | // * Unused outputs are labeled unused 95 | 96 | wire clk_out1_xilinx_pll; 97 | wire clk_out2_xilinx_pll; 98 | wire clk_out3_xilinx_pll; 99 | wire clk_out4_xilinx_pll; 100 | wire clk_out5_xilinx_pll; 101 | wire clk_out6_xilinx_pll; 102 | wire clk_out7_xilinx_pll; 103 | 104 | wire [15:0] do_unused; 105 | wire drdy_unused; 106 | wire psdone_unused; 107 | wire locked_int; 108 | wire clkfbout_xilinx_pll; 109 | wire clkfbout_buf_xilinx_pll; 110 | wire clkfboutb_unused; 111 | wire clkout0b_unused; 112 | wire clkout1_unused; 113 | wire clkout1b_unused; 114 | wire clkout2_unused; 115 | wire clkout2b_unused; 116 | wire clkout3_unused; 117 | wire clkout3b_unused; 118 | wire clkout4_unused; 119 | wire clkout5_unused; 120 | wire clkout6_unused; 121 | wire clkfbstopped_unused; 122 | wire clkinstopped_unused; 123 | wire reset_high; 124 | 125 | MMCME2_ADV 126 | #(.BANDWIDTH ("OPTIMIZED"), 127 | .CLKOUT4_CASCADE ("FALSE"), 128 | .COMPENSATION ("ZHOLD"), 129 | .STARTUP_WAIT ("FALSE"), 130 | .DIVCLK_DIVIDE (2), 131 | .CLKFBOUT_MULT_F (9.125), 132 | .CLKFBOUT_PHASE (0.000), 133 | .CLKFBOUT_USE_FINE_PS ("FALSE"), 134 | .CLKOUT0_DIVIDE_F (36.500), 135 | .CLKOUT0_PHASE (0.000), 136 | .CLKOUT0_DUTY_CYCLE (0.500), 137 | .CLKOUT0_USE_FINE_PS ("FALSE"), 138 | .CLKIN1_PERIOD (5.0)) 139 | mmcm_adv_inst 140 | // Output clocks 141 | ( 142 | .CLKFBOUT (clkfbout_xilinx_pll), 143 | .CLKFBOUTB (clkfboutb_unused), 144 | .CLKOUT0 (clk_out1_xilinx_pll), 145 | .CLKOUT0B (clkout0b_unused), 146 | .CLKOUT1 (clkout1_unused), 147 | .CLKOUT1B (clkout1b_unused), 148 | .CLKOUT2 (clkout2_unused), 149 | .CLKOUT2B (clkout2b_unused), 150 | .CLKOUT3 (clkout3_unused), 151 | .CLKOUT3B (clkout3b_unused), 152 | .CLKOUT4 (clkout4_unused), 153 | .CLKOUT5 (clkout5_unused), 154 | .CLKOUT6 (clkout6_unused), 155 | // Input clock control 156 | .CLKFBIN (clkfbout_buf_xilinx_pll), 157 | .CLKIN1 (clk_in1_xilinx_pll), 158 | .CLKIN2 (1'b0), 159 | // Tied to always select the primary input clock 160 | .CLKINSEL (1'b1), 161 | // Ports for dynamic reconfiguration 162 | .DADDR (7'h0), 163 | .DCLK (1'b0), 164 | .DEN (1'b0), 165 | .DI (16'h0), 166 | .DO (do_unused), 167 | .DRDY (drdy_unused), 168 | .DWE (1'b0), 169 | // Ports for dynamic phase shift 170 | .PSCLK (1'b0), 171 | .PSEN (1'b0), 172 | .PSINCDEC (1'b0), 173 | .PSDONE (psdone_unused), 174 | // Other control and status signals 175 | .LOCKED (locked_int), 176 | .CLKINSTOPPED (clkinstopped_unused), 177 | .CLKFBSTOPPED (clkfbstopped_unused), 178 | .PWRDWN (1'b0), 179 | .RST (reset_high)); 180 | 181 | assign reset_high = reset; 182 | 183 | assign locked = locked_int; 184 | // Clock Monitor clock assigning 185 | //-------------------------------------- 186 | // Output buffering 187 | //----------------------------------- 188 | 189 | BUFG clkf_buf 190 | (.O (clkfbout_buf_xilinx_pll), 191 | .I (clkfbout_xilinx_pll)); 192 | 193 | 194 | 195 | BUFG clkout1_buf 196 | (.O (clk_out1), 197 | .I (clk_out1_xilinx_pll)); 198 | 199 | 200 | 201 | 202 | endmodule 203 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: xilinx_pll_ooc.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | ################# 52 | #DEFAULT CLOCK CONSTRAINTS 53 | 54 | ############################################################ 55 | # Clock Period Constraints # 56 | ############################################################ 57 | # Differential clock only needs one constraint 58 | #create_clock -period 5.0 [get_ports clk_in1_p] 59 | 60 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll_sim_netlist.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016 4 | // Date : Thu Apr 27 18:01:59 2017 5 | // Host : wds040 running 64-bit CentOS release 6.8 (Final) 6 | // Command : write_verilog -force -mode funcsim 7 | // /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709/trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll_sim_netlist.v 8 | // Design : xilinx_pll 9 | // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified 10 | // or synthesized. This netlist cannot be used for SDF annotated simulation. 11 | // Device : xc7vx690tffg1761-2 12 | // -------------------------------------------------------------------------------- 13 | `timescale 1 ps / 1 ps 14 | 15 | (* NotValidForBitStream *) 16 | module xilinx_pll 17 | (clk_in1_p, 18 | clk_in1_n, 19 | clk_out1, 20 | reset, 21 | locked); 22 | input clk_in1_p; 23 | input clk_in1_n; 24 | output clk_out1; 25 | input reset; 26 | output locked; 27 | 28 | (* IBUF_LOW_PWR *) wire clk_in1_n; 29 | (* IBUF_LOW_PWR *) wire clk_in1_p; 30 | wire clk_out1; 31 | wire locked; 32 | wire reset; 33 | 34 | xilinx_pll_xilinx_pll_clk_wiz inst 35 | (.clk_in1_n(clk_in1_n), 36 | .clk_in1_p(clk_in1_p), 37 | .clk_out1(clk_out1), 38 | .locked(locked), 39 | .reset(reset)); 40 | endmodule 41 | 42 | (* ORIG_REF_NAME = "xilinx_pll_clk_wiz" *) 43 | module xilinx_pll_xilinx_pll_clk_wiz 44 | (clk_in1_p, 45 | clk_in1_n, 46 | clk_out1, 47 | reset, 48 | locked); 49 | input clk_in1_p; 50 | input clk_in1_n; 51 | output clk_out1; 52 | input reset; 53 | output locked; 54 | 55 | wire clk_in1_n; 56 | wire clk_in1_p; 57 | wire clk_in1_xilinx_pll; 58 | wire clk_out1; 59 | wire clk_out1_xilinx_pll; 60 | wire clkfbout_buf_xilinx_pll; 61 | wire clkfbout_xilinx_pll; 62 | wire locked; 63 | wire reset; 64 | wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; 65 | wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; 66 | wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; 67 | wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; 68 | wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED; 69 | wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; 70 | wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; 71 | wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; 72 | wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; 73 | wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; 74 | wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; 75 | wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; 76 | wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; 77 | wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; 78 | wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; 79 | wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; 80 | 81 | (* BOX_TYPE = "PRIMITIVE" *) 82 | BUFG clkf_buf 83 | (.I(clkfbout_xilinx_pll), 84 | .O(clkfbout_buf_xilinx_pll)); 85 | (* BOX_TYPE = "PRIMITIVE" *) 86 | (* CAPACITANCE = "DONT_CARE" *) 87 | (* IBUF_DELAY_VALUE = "0" *) 88 | (* IFD_DELAY_VALUE = "AUTO" *) 89 | IBUFDS #( 90 | .DQS_BIAS("FALSE"), 91 | .IOSTANDARD("DEFAULT")) 92 | clkin1_ibufgds 93 | (.I(clk_in1_p), 94 | .IB(clk_in1_n), 95 | .O(clk_in1_xilinx_pll)); 96 | (* BOX_TYPE = "PRIMITIVE" *) 97 | BUFG clkout1_buf 98 | (.I(clk_out1_xilinx_pll), 99 | .O(clk_out1)); 100 | (* BOX_TYPE = "PRIMITIVE" *) 101 | MMCME2_ADV #( 102 | .BANDWIDTH("OPTIMIZED"), 103 | .CLKFBOUT_MULT_F(9.125000), 104 | .CLKFBOUT_PHASE(0.000000), 105 | .CLKFBOUT_USE_FINE_PS("FALSE"), 106 | .CLKIN1_PERIOD(5.000000), 107 | .CLKIN2_PERIOD(0.000000), 108 | .CLKOUT0_DIVIDE_F(36.500000), 109 | .CLKOUT0_DUTY_CYCLE(0.500000), 110 | .CLKOUT0_PHASE(0.000000), 111 | .CLKOUT0_USE_FINE_PS("FALSE"), 112 | .CLKOUT1_DIVIDE(1), 113 | .CLKOUT1_DUTY_CYCLE(0.500000), 114 | .CLKOUT1_PHASE(0.000000), 115 | .CLKOUT1_USE_FINE_PS("FALSE"), 116 | .CLKOUT2_DIVIDE(1), 117 | .CLKOUT2_DUTY_CYCLE(0.500000), 118 | .CLKOUT2_PHASE(0.000000), 119 | .CLKOUT2_USE_FINE_PS("FALSE"), 120 | .CLKOUT3_DIVIDE(1), 121 | .CLKOUT3_DUTY_CYCLE(0.500000), 122 | .CLKOUT3_PHASE(0.000000), 123 | .CLKOUT3_USE_FINE_PS("FALSE"), 124 | .CLKOUT4_CASCADE("FALSE"), 125 | .CLKOUT4_DIVIDE(1), 126 | .CLKOUT4_DUTY_CYCLE(0.500000), 127 | .CLKOUT4_PHASE(0.000000), 128 | .CLKOUT4_USE_FINE_PS("FALSE"), 129 | .CLKOUT5_DIVIDE(1), 130 | .CLKOUT5_DUTY_CYCLE(0.500000), 131 | .CLKOUT5_PHASE(0.000000), 132 | .CLKOUT5_USE_FINE_PS("FALSE"), 133 | .CLKOUT6_DIVIDE(1), 134 | .CLKOUT6_DUTY_CYCLE(0.500000), 135 | .CLKOUT6_PHASE(0.000000), 136 | .CLKOUT6_USE_FINE_PS("FALSE"), 137 | .COMPENSATION("ZHOLD"), 138 | .DIVCLK_DIVIDE(2), 139 | .IS_CLKINSEL_INVERTED(1'b0), 140 | .IS_PSEN_INVERTED(1'b0), 141 | .IS_PSINCDEC_INVERTED(1'b0), 142 | .IS_PWRDWN_INVERTED(1'b0), 143 | .IS_RST_INVERTED(1'b0), 144 | .REF_JITTER1(0.010000), 145 | .REF_JITTER2(0.010000), 146 | .SS_EN("FALSE"), 147 | .SS_MODE("CENTER_HIGH"), 148 | .SS_MOD_PERIOD(10000), 149 | .STARTUP_WAIT("FALSE")) 150 | mmcm_adv_inst 151 | (.CLKFBIN(clkfbout_buf_xilinx_pll), 152 | .CLKFBOUT(clkfbout_xilinx_pll), 153 | .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), 154 | .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), 155 | .CLKIN1(clk_in1_xilinx_pll), 156 | .CLKIN2(1'b0), 157 | .CLKINSEL(1'b1), 158 | .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), 159 | .CLKOUT0(clk_out1_xilinx_pll), 160 | .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), 161 | .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED), 162 | .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), 163 | .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), 164 | .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), 165 | .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), 166 | .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), 167 | .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), 168 | .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), 169 | .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), 170 | .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), 171 | .DCLK(1'b0), 172 | .DEN(1'b0), 173 | .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), 174 | .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), 175 | .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), 176 | .DWE(1'b0), 177 | .LOCKED(locked), 178 | .PSCLK(1'b0), 179 | .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), 180 | .PSEN(1'b0), 181 | .PSINCDEC(1'b0), 182 | .PWRDWN(1'b0), 183 | .RST(reset)); 184 | endmodule 185 | `ifndef GLBL 186 | `define GLBL 187 | `timescale 1 ps / 1 ps 188 | 189 | module glbl (); 190 | 191 | parameter ROC_WIDTH = 100000; 192 | parameter TOC_WIDTH = 0; 193 | 194 | //-------- STARTUP Globals -------------- 195 | wire GSR; 196 | wire GTS; 197 | wire GWE; 198 | wire PRLD; 199 | tri1 p_up_tmp; 200 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 201 | 202 | wire PROGB_GLBL; 203 | wire CCLKO_GLBL; 204 | wire FCSBO_GLBL; 205 | wire [3:0] DO_GLBL; 206 | wire [3:0] DI_GLBL; 207 | 208 | reg GSR_int; 209 | reg GTS_int; 210 | reg PRLD_int; 211 | 212 | //-------- JTAG Globals -------------- 213 | wire JTAG_TDO_GLBL; 214 | wire JTAG_TCK_GLBL; 215 | wire JTAG_TDI_GLBL; 216 | wire JTAG_TMS_GLBL; 217 | wire JTAG_TRST_GLBL; 218 | 219 | reg JTAG_CAPTURE_GLBL; 220 | reg JTAG_RESET_GLBL; 221 | reg JTAG_SHIFT_GLBL; 222 | reg JTAG_UPDATE_GLBL; 223 | reg JTAG_RUNTEST_GLBL; 224 | 225 | reg JTAG_SEL1_GLBL = 0; 226 | reg JTAG_SEL2_GLBL = 0 ; 227 | reg JTAG_SEL3_GLBL = 0; 228 | reg JTAG_SEL4_GLBL = 0; 229 | 230 | reg JTAG_USER_TDO1_GLBL = 1'bz; 231 | reg JTAG_USER_TDO2_GLBL = 1'bz; 232 | reg JTAG_USER_TDO3_GLBL = 1'bz; 233 | reg JTAG_USER_TDO4_GLBL = 1'bz; 234 | 235 | assign (weak1, weak0) GSR = GSR_int; 236 | assign (weak1, weak0) GTS = GTS_int; 237 | assign (weak1, weak0) PRLD = PRLD_int; 238 | 239 | initial begin 240 | GSR_int = 1'b1; 241 | PRLD_int = 1'b1; 242 | #(ROC_WIDTH) 243 | GSR_int = 1'b0; 244 | PRLD_int = 1'b0; 245 | end 246 | 247 | initial begin 248 | GTS_int = 1'b1; 249 | #(TOC_WIDTH) 250 | GTS_int = 1'b0; 251 | end 252 | 253 | endmodule 254 | `endif 255 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll_sim_netlist.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016 4 | -- Date : Thu Apr 27 18:01:59 2017 5 | -- Host : wds040 running 64-bit CentOS release 6.8 (Final) 6 | -- Command : write_vhdl -force -mode funcsim 7 | -- /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709/trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll_sim_netlist.vhdl 8 | -- Design : xilinx_pll 9 | -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or 10 | -- synthesized. This netlist cannot be used for SDF annotated simulation. 11 | -- Device : xc7vx690tffg1761-2 12 | -- -------------------------------------------------------------------------------- 13 | library IEEE; 14 | use IEEE.STD_LOGIC_1164.ALL; 15 | library UNISIM; 16 | use UNISIM.VCOMPONENTS.ALL; 17 | entity xilinx_pll_xilinx_pll_clk_wiz is 18 | port ( 19 | clk_in1_p : in STD_LOGIC; 20 | clk_in1_n : in STD_LOGIC; 21 | clk_out1 : out STD_LOGIC; 22 | reset : in STD_LOGIC; 23 | locked : out STD_LOGIC 24 | ); 25 | attribute ORIG_REF_NAME : string; 26 | attribute ORIG_REF_NAME of xilinx_pll_xilinx_pll_clk_wiz : entity is "xilinx_pll_clk_wiz"; 27 | end xilinx_pll_xilinx_pll_clk_wiz; 28 | 29 | architecture STRUCTURE of xilinx_pll_xilinx_pll_clk_wiz is 30 | signal clk_in1_xilinx_pll : STD_LOGIC; 31 | signal clk_out1_xilinx_pll : STD_LOGIC; 32 | signal clkfbout_buf_xilinx_pll : STD_LOGIC; 33 | signal clkfbout_xilinx_pll : STD_LOGIC; 34 | signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; 35 | signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; 36 | signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; 37 | signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; 38 | signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; 39 | signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; 40 | signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; 41 | signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; 42 | signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; 43 | signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; 44 | signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; 45 | signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; 46 | signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; 47 | signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; 48 | signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; 49 | signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); 50 | attribute BOX_TYPE : string; 51 | attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; 52 | attribute BOX_TYPE of clkin1_ibufgds : label is "PRIMITIVE"; 53 | attribute CAPACITANCE : string; 54 | attribute CAPACITANCE of clkin1_ibufgds : label is "DONT_CARE"; 55 | attribute IBUF_DELAY_VALUE : string; 56 | attribute IBUF_DELAY_VALUE of clkin1_ibufgds : label is "0"; 57 | attribute IFD_DELAY_VALUE : string; 58 | attribute IFD_DELAY_VALUE of clkin1_ibufgds : label is "AUTO"; 59 | attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; 60 | attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; 61 | begin 62 | clkf_buf: unisim.vcomponents.BUFG 63 | port map ( 64 | I => clkfbout_xilinx_pll, 65 | O => clkfbout_buf_xilinx_pll 66 | ); 67 | clkin1_ibufgds: unisim.vcomponents.IBUFDS 68 | generic map( 69 | DQS_BIAS => "FALSE", 70 | IOSTANDARD => "DEFAULT" 71 | ) 72 | port map ( 73 | I => clk_in1_p, 74 | IB => clk_in1_n, 75 | O => clk_in1_xilinx_pll 76 | ); 77 | clkout1_buf: unisim.vcomponents.BUFG 78 | port map ( 79 | I => clk_out1_xilinx_pll, 80 | O => clk_out1 81 | ); 82 | mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV 83 | generic map( 84 | BANDWIDTH => "OPTIMIZED", 85 | CLKFBOUT_MULT_F => 9.125000, 86 | CLKFBOUT_PHASE => 0.000000, 87 | CLKFBOUT_USE_FINE_PS => false, 88 | CLKIN1_PERIOD => 5.000000, 89 | CLKIN2_PERIOD => 0.000000, 90 | CLKOUT0_DIVIDE_F => 36.500000, 91 | CLKOUT0_DUTY_CYCLE => 0.500000, 92 | CLKOUT0_PHASE => 0.000000, 93 | CLKOUT0_USE_FINE_PS => false, 94 | CLKOUT1_DIVIDE => 1, 95 | CLKOUT1_DUTY_CYCLE => 0.500000, 96 | CLKOUT1_PHASE => 0.000000, 97 | CLKOUT1_USE_FINE_PS => false, 98 | CLKOUT2_DIVIDE => 1, 99 | CLKOUT2_DUTY_CYCLE => 0.500000, 100 | CLKOUT2_PHASE => 0.000000, 101 | CLKOUT2_USE_FINE_PS => false, 102 | CLKOUT3_DIVIDE => 1, 103 | CLKOUT3_DUTY_CYCLE => 0.500000, 104 | CLKOUT3_PHASE => 0.000000, 105 | CLKOUT3_USE_FINE_PS => false, 106 | CLKOUT4_CASCADE => false, 107 | CLKOUT4_DIVIDE => 1, 108 | CLKOUT4_DUTY_CYCLE => 0.500000, 109 | CLKOUT4_PHASE => 0.000000, 110 | CLKOUT4_USE_FINE_PS => false, 111 | CLKOUT5_DIVIDE => 1, 112 | CLKOUT5_DUTY_CYCLE => 0.500000, 113 | CLKOUT5_PHASE => 0.000000, 114 | CLKOUT5_USE_FINE_PS => false, 115 | CLKOUT6_DIVIDE => 1, 116 | CLKOUT6_DUTY_CYCLE => 0.500000, 117 | CLKOUT6_PHASE => 0.000000, 118 | CLKOUT6_USE_FINE_PS => false, 119 | COMPENSATION => "ZHOLD", 120 | DIVCLK_DIVIDE => 2, 121 | IS_CLKINSEL_INVERTED => '0', 122 | IS_PSEN_INVERTED => '0', 123 | IS_PSINCDEC_INVERTED => '0', 124 | IS_PWRDWN_INVERTED => '0', 125 | IS_RST_INVERTED => '0', 126 | REF_JITTER1 => 0.010000, 127 | REF_JITTER2 => 0.010000, 128 | SS_EN => "FALSE", 129 | SS_MODE => "CENTER_HIGH", 130 | SS_MOD_PERIOD => 10000, 131 | STARTUP_WAIT => false 132 | ) 133 | port map ( 134 | CLKFBIN => clkfbout_buf_xilinx_pll, 135 | CLKFBOUT => clkfbout_xilinx_pll, 136 | CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, 137 | CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, 138 | CLKIN1 => clk_in1_xilinx_pll, 139 | CLKIN2 => '0', 140 | CLKINSEL => '1', 141 | CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, 142 | CLKOUT0 => clk_out1_xilinx_pll, 143 | CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, 144 | CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, 145 | CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, 146 | CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, 147 | CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, 148 | CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, 149 | CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, 150 | CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, 151 | CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, 152 | CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, 153 | DADDR(6 downto 0) => B"0000000", 154 | DCLK => '0', 155 | DEN => '0', 156 | DI(15 downto 0) => B"0000000000000000", 157 | DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), 158 | DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, 159 | DWE => '0', 160 | LOCKED => locked, 161 | PSCLK => '0', 162 | PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, 163 | PSEN => '0', 164 | PSINCDEC => '0', 165 | PWRDWN => '0', 166 | RST => reset 167 | ); 168 | end STRUCTURE; 169 | library IEEE; 170 | use IEEE.STD_LOGIC_1164.ALL; 171 | library UNISIM; 172 | use UNISIM.VCOMPONENTS.ALL; 173 | entity xilinx_pll is 174 | port ( 175 | clk_in1_p : in STD_LOGIC; 176 | clk_in1_n : in STD_LOGIC; 177 | clk_out1 : out STD_LOGIC; 178 | reset : in STD_LOGIC; 179 | locked : out STD_LOGIC 180 | ); 181 | attribute NotValidForBitStream : boolean; 182 | attribute NotValidForBitStream of xilinx_pll : entity is true; 183 | end xilinx_pll; 184 | 185 | architecture STRUCTURE of xilinx_pll is 186 | begin 187 | inst: entity work.xilinx_pll_xilinx_pll_clk_wiz 188 | port map ( 189 | clk_in1_n => clk_in1_n, 190 | clk_in1_p => clk_in1_p, 191 | clk_out1 => clk_out1, 192 | locked => locked, 193 | reset => reset 194 | ); 195 | end STRUCTURE; 196 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016 4 | // Date : Thu Apr 27 18:01:58 2017 5 | // Host : wds040 running 64-bit CentOS release 6.8 (Final) 6 | // Command : write_verilog -force -mode synth_stub 7 | // /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709/trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll_stub.v 8 | // Design : xilinx_pll 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7vx690tffg1761-2 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | module xilinx_pll(clk_in1_p, clk_in1_n, clk_out1, reset, locked) 17 | /* synthesis syn_black_box black_box_pad_pin="clk_in1_p,clk_in1_n,clk_out1,reset,locked" */; 18 | input clk_in1_p; 19 | input clk_in1_n; 20 | output clk_out1; 21 | input reset; 22 | output locked; 23 | endmodule 24 | -------------------------------------------------------------------------------- /trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016 4 | -- Date : Thu Apr 27 18:01:58 2017 5 | -- Host : wds040 running 64-bit CentOS release 6.8 (Final) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709/trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll_stub.vhdl 8 | -- Design : xilinx_pll 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7vx690tffg1761-2 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity xilinx_pll is 16 | Port ( 17 | clk_in1_p : in STD_LOGIC; 18 | clk_in1_n : in STD_LOGIC; 19 | clk_out1 : out STD_LOGIC; 20 | reset : in STD_LOGIC; 21 | locked : out STD_LOGIC 22 | ); 23 | 24 | end xilinx_pll; 25 | 26 | architecture stub of xilinx_pll is 27 | attribute syn_black_box : boolean; 28 | attribute black_box_pad_pin : string; 29 | attribute syn_black_box of stub : architecture is true; 30 | attribute black_box_pad_pin of stub : architecture is "clk_in1_p,clk_in1_n,clk_out1,reset,locked"; 31 | begin 32 | end; 33 | -------------------------------------------------------------------------------- /trng/trng.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 120 | 121 | 122 | 123 | 124 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 145 | 146 | 147 | 148 | 149 | 152 | 153 | 155 | 156 | 158 | 159 | 161 | 162 | 164 | 165 | 167 | 168 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | -------------------------------------------------------------------------------- /trng/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2016.2 (64-bit) 3 | # SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 4 | # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 5 | # Start of session at: Tue Jun 27 10:51:52 2017 6 | # Process ID: 4316 7 | # Current directory: C:/Users/Gao Fei/Desktop/all/fpga_proj_release/vc709/trng 8 | # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent732 C:\Users\Gao Fei\Desktop\all\fpga_proj_release\vc709\trng\trng.xpr 9 | # Log file: C:/Users/Gao Fei/Desktop/all/fpga_proj_release/vc709/trng/vivado.log 10 | # Journal file: C:/Users/Gao Fei/Desktop/all/fpga_proj_release/vc709/trng\vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project {C:/Users/Gao Fei/Desktop/all/fpga_proj_release/vc709/trng/trng.xpr} 14 | update_compile_order -fileset sources_1 15 | -------------------------------------------------------------------------------- /trng/vivado.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2016.2 (64-bit) 3 | # SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 4 | # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 5 | # Start of session at: Tue Jun 27 10:51:52 2017 6 | # Process ID: 4316 7 | # Current directory: C:/Users/Gao Fei/Desktop/all/fpga_proj_release/vc709/trng 8 | # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent732 C:\Users\Gao Fei\Desktop\all\fpga_proj_release\vc709\trng\trng.xpr 9 | # Log file: C:/Users/Gao Fei/Desktop/all/fpga_proj_release/vc709/trng/vivado.log 10 | # Journal file: C:/Users/Gao Fei/Desktop/all/fpga_proj_release/vc709/trng\vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project {C:/Users/Gao Fei/Desktop/all/fpga_proj_release/vc709/trng/trng.xpr} 14 | Scanning sources... 15 | Finished scanning sources 16 | INFO: [IP_Flow 19-234] Refreshing IP repositories 17 | INFO: [IP_Flow 19-1704] No user IP repositories specified 18 | INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.2/data/ip'. 19 | open_project: Time (s): cpu = 00:00:19 ; elapsed = 00:00:09 . Memory (MB): peak = 787.891 ; gain = 131.246 20 | update_compile_order -fileset sources_1 21 | exit 22 | INFO: [Common 17-206] Exiting Vivado at Tue Jun 27 10:57:07 2017... 23 | -------------------------------------------------------------------------------- /trng/vivado_300.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2016.2 (64-bit) 3 | # SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 4 | # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 5 | # Start of session at: Tue May 23 21:27:45 2017 6 | # Process ID: 300 7 | # Current directory: C:/Users/Gao Fei/Desktop/all/fpga_proj_release/vc709/trng 8 | # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6896 C:\Users\Gao Fei\Desktop\all\fpga_proj_release\vc709\trng\trng.xpr 9 | # Log file: C:/Users/Gao Fei/Desktop/all/fpga_proj_release/vc709/trng/vivado.log 10 | # Journal file: C:/Users/Gao Fei/Desktop/all/fpga_proj_release/vc709/trng\vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project {C:/Users/Gao Fei/Desktop/all/fpga_proj_release/vc709/trng/trng.xpr} 14 | update_compile_order -fileset sources_1 15 | add_files -norecurse {{C:/Users/Gao Fei/Desktop/all/fpga_proj_release/hack/singlethread.v} {C:/Users/Gao Fei/Desktop/all/fpga_proj_release/hack/buff.v} {C:/Users/Gao Fei/Desktop/all/fpga_proj_release/hack/sample.v}} 16 | update_compile_order -fileset sources_1 17 | open_run synth_1 -name synth_1 18 | report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -name timing_1 19 | update_compile_order -fileset sources_1 20 | show_objects -name NET_ONLY [get_nets -hierarchical -top_net_of_hierarchical_group "*resu*" ] 21 | show_objects -name NET_ONLY [get_nets -hierarchical -top_net_of_hierarchical_group "*result*" ] 22 | show_objects -name NET_ONLY [get_nets -hierarchical -top_net_of_hierarchical_group "*done*" ] 23 | show_objects -name NET_ONLY [get_nets -hierarchical -top_net_of_hierarchical_group "*done*" ] 24 | reset_run synth_1 25 | launch_runs synth_1 26 | wait_on_run synth_1 27 | refresh_design 28 | show_objects -name NET_ONLY [get_nets -hierarchical -top_net_of_hierarchical_group "*done*" ] 29 | show_objects -name NET_ONLY [get_nets -hierarchical -top_net_of_hierarchical_group "*result*" ] 30 | delete_debug_core [get_debug_cores {u_ila_0 }] 31 | create_debug_core u_ila_0 ila 32 | set_property C_DATA_DEPTH 65536 [get_debug_cores u_ila_0] 33 | set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] 34 | set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] 35 | set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] 36 | set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] 37 | set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] 38 | set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] 39 | set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] 40 | set_property port_width 1 [get_debug_ports u_ila_0/clk] 41 | connect_debug_port u_ila_0/clk [get_nets [list u_xilinx_pll/inst/clk_out1 ]] 42 | set_property port_width 80 [get_debug_ports u_ila_0/probe0] 43 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] 44 | connect_debug_port u_ila_0/probe0 [get_nets [list {ss1/result[0]} {ss1/result[1]} {ss1/result[2]} {ss1/result[3]} {ss1/result[4]} {ss1/result[5]} {ss1/result[6]} {ss1/result[7]} {ss1/result[8]} {ss1/result[9]} {ss1/result[10]} {ss1/result[11]} {ss1/result[12]} {ss1/result[13]} {ss1/result[14]} {ss1/result[15]} {ss1/result[16]} {ss1/result[17]} {ss1/result[18]} {ss1/result[19]} {ss1/result[20]} {ss1/result[21]} {ss1/result[22]} {ss1/result[23]} {ss1/result[24]} {ss1/result[25]} {ss1/result[26]} {ss1/result[27]} {ss1/result[28]} {ss1/result[29]} {ss1/result[30]} {ss1/result[31]} {ss1/result[32]} {ss1/result[33]} {ss1/result[34]} {ss1/result[35]} {ss1/result[36]} {ss1/result[37]} {ss1/result[38]} {ss1/result[39]} {ss1/result[40]} {ss1/result[41]} {ss1/result[42]} {ss1/result[43]} {ss1/result[44]} {ss1/result[45]} {ss1/result[46]} {ss1/result[47]} {ss1/result[48]} {ss1/result[49]} {ss1/result[50]} {ss1/result[51]} {ss1/result[52]} {ss1/result[53]} {ss1/result[54]} {ss1/result[55]} {ss1/result[56]} {ss1/result[57]} {ss1/result[58]} {ss1/result[59]} {ss1/result[60]} {ss1/result[61]} {ss1/result[62]} {ss1/result[63]} {ss1/result[64]} {ss1/result[65]} {ss1/result[66]} {ss1/result[67]} {ss1/result[68]} {ss1/result[69]} {ss1/result[70]} {ss1/result[71]} {ss1/result[72]} {ss1/result[73]} {ss1/result[74]} {ss1/result[75]} {ss1/result[76]} {ss1/result[77]} {ss1/result[78]} {ss1/result[79]} ]] 45 | create_debug_port u_ila_0 probe 46 | set_property port_width 32 [get_debug_ports u_ila_0/probe1] 47 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] 48 | connect_debug_port u_ila_0/probe1 [get_nets [list {addr[0]} {addr[1]} {addr[2]} {addr[3]} {addr[4]} {addr[5]} {addr[6]} {addr[7]} {addr[8]} {addr[9]} {addr[10]} {addr[11]} {addr[12]} {addr[13]} {addr[14]} {addr[15]} {addr[16]} {addr[17]} {addr[18]} {addr[19]} {addr[20]} {addr[21]} {addr[22]} {addr[23]} {addr[24]} {addr[25]} {addr[26]} {addr[27]} {addr[28]} {addr[29]} {addr[30]} {addr[31]} ]] 49 | create_debug_port u_ila_0 probe 50 | set_property port_width 32 [get_debug_ports u_ila_0/probe2] 51 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] 52 | connect_debug_port u_ila_0/probe2 [get_nets [list {rdata[0]} {rdata[1]} {rdata[2]} {rdata[3]} {rdata[4]} {rdata[5]} {rdata[6]} {rdata[7]} {rdata[8]} {rdata[9]} {rdata[10]} {rdata[11]} {rdata[12]} {rdata[13]} {rdata[14]} {rdata[15]} {rdata[16]} {rdata[17]} {rdata[18]} {rdata[19]} {rdata[20]} {rdata[21]} {rdata[22]} {rdata[23]} {rdata[24]} {rdata[25]} {rdata[26]} {rdata[27]} {rdata[28]} {rdata[29]} {rdata[30]} {rdata[31]} ]] 53 | create_debug_port u_ila_0 probe 54 | set_property port_width 32 [get_debug_ports u_ila_0/probe3] 55 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] 56 | connect_debug_port u_ila_0/probe3 [get_nets [list {wdata[0]} {wdata[1]} {wdata[2]} {wdata[3]} {wdata[4]} {wdata[5]} {wdata[6]} {wdata[7]} {wdata[8]} {wdata[9]} {wdata[10]} {wdata[11]} {wdata[12]} {wdata[13]} {wdata[14]} {wdata[15]} {wdata[16]} {wdata[17]} {wdata[18]} {wdata[19]} {wdata[20]} {wdata[21]} {wdata[22]} {wdata[23]} {wdata[24]} {wdata[25]} {wdata[26]} {wdata[27]} {wdata[28]} {wdata[29]} {wdata[30]} {wdata[31]} ]] 57 | create_debug_port u_ila_0 probe 58 | set_property port_width 1 [get_debug_ports u_ila_0/probe4] 59 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] 60 | connect_debug_port u_ila_0/probe4 [get_nets [list resetn ]] 61 | create_debug_port u_ila_0 probe 62 | set_property port_width 1 [get_debug_ports u_ila_0/probe5] 63 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] 64 | connect_debug_port u_ila_0/probe5 [get_nets [list scan_mode ]] 65 | create_debug_port u_ila_0 probe 66 | set_property port_width 1 [get_debug_ports u_ila_0/probe6] 67 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] 68 | connect_debug_port u_ila_0/probe6 [get_nets [list sel ]] 69 | create_debug_port u_ila_0 probe 70 | set_property port_width 1 [get_debug_ports u_ila_0/probe7] 71 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] 72 | connect_debug_port u_ila_0/probe7 [get_nets [list write ]] 73 | create_debug_port u_ila_0 probe 74 | set_property port_width 1 [get_debug_ports u_ila_0/probe8] 75 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] 76 | connect_debug_port u_ila_0/probe8 [get_nets [list ss1/done ]] 77 | show_objects -name NET_ONLY [get_nets -hierarchical -top_net_of_hierarchical_group "*done*" ] 78 | show_objects -name NET_ONLY [get_nets -hierarchical -top_net_of_hierarchical_group "*done*" ] 79 | show_objects -name NET_ONLY [get_nets -hierarchical -top_net_of_hierarchical_group "*done*" ] 80 | delete_debug_core [get_debug_cores {u_ila_0 }] 81 | create_debug_core u_ila_0 ila 82 | set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] 83 | set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] 84 | set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] 85 | set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] 86 | set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] 87 | set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] 88 | set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] 89 | set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] 90 | set_property port_width 1 [get_debug_ports u_ila_0/clk] 91 | connect_debug_port u_ila_0/clk [get_nets [list u_xilinx_pll/inst/clk_out1 ]] 92 | set_property port_width 32 [get_debug_ports u_ila_0/probe0] 93 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] 94 | connect_debug_port u_ila_0/probe0 [get_nets [list {addr[0]} {addr[1]} {addr[2]} {addr[3]} {addr[4]} {addr[5]} {addr[6]} {addr[7]} {addr[8]} {addr[9]} {addr[10]} {addr[11]} {addr[12]} {addr[13]} {addr[14]} {addr[15]} {addr[16]} {addr[17]} {addr[18]} {addr[19]} {addr[20]} {addr[21]} {addr[22]} {addr[23]} {addr[24]} {addr[25]} {addr[26]} {addr[27]} {addr[28]} {addr[29]} {addr[30]} {addr[31]} ]] 95 | create_debug_port u_ila_0 probe 96 | set_property port_width 32 [get_debug_ports u_ila_0/probe1] 97 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] 98 | connect_debug_port u_ila_0/probe1 [get_nets [list {rdata[0]} {rdata[1]} {rdata[2]} {rdata[3]} {rdata[4]} {rdata[5]} {rdata[6]} {rdata[7]} {rdata[8]} {rdata[9]} {rdata[10]} {rdata[11]} {rdata[12]} {rdata[13]} {rdata[14]} {rdata[15]} {rdata[16]} {rdata[17]} {rdata[18]} {rdata[19]} {rdata[20]} {rdata[21]} {rdata[22]} {rdata[23]} {rdata[24]} {rdata[25]} {rdata[26]} {rdata[27]} {rdata[28]} {rdata[29]} {rdata[30]} {rdata[31]} ]] 99 | create_debug_port u_ila_0 probe 100 | set_property port_width 32 [get_debug_ports u_ila_0/probe2] 101 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] 102 | connect_debug_port u_ila_0/probe2 [get_nets [list {wdata[0]} {wdata[1]} {wdata[2]} {wdata[3]} {wdata[4]} {wdata[5]} {wdata[6]} {wdata[7]} {wdata[8]} {wdata[9]} {wdata[10]} {wdata[11]} {wdata[12]} {wdata[13]} {wdata[14]} {wdata[15]} {wdata[16]} {wdata[17]} {wdata[18]} {wdata[19]} {wdata[20]} {wdata[21]} {wdata[22]} {wdata[23]} {wdata[24]} {wdata[25]} {wdata[26]} {wdata[27]} {wdata[28]} {wdata[29]} {wdata[30]} {wdata[31]} ]] 103 | create_debug_port u_ila_0 probe 104 | set_property port_width 1 [get_debug_ports u_ila_0/probe3] 105 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] 106 | connect_debug_port u_ila_0/probe3 [get_nets [list resetn ]] 107 | create_debug_port u_ila_0 probe 108 | set_property port_width 1 [get_debug_ports u_ila_0/probe4] 109 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] 110 | connect_debug_port u_ila_0/probe4 [get_nets [list scan_mode ]] 111 | create_debug_port u_ila_0 probe 112 | set_property port_width 1 [get_debug_ports u_ila_0/probe5] 113 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] 114 | connect_debug_port u_ila_0/probe5 [get_nets [list sel ]] 115 | create_debug_port u_ila_0 probe 116 | set_property port_width 1 [get_debug_ports u_ila_0/probe6] 117 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] 118 | connect_debug_port u_ila_0/probe6 [get_nets [list write ]] 119 | save_constraints 120 | reset_run synth_1 121 | launch_runs synth_1 122 | wait_on_run synth_1 123 | show_objects -name NET_ONLY [get_nets -hierarchical -top_net_of_hierarchical_group "*done*" ] 124 | reset_run synth_1 125 | launch_runs synth_1 126 | wait_on_run synth_1 127 | show_objects -name NET_ONLY [get_nets -hierarchical -top_net_of_hierarchical_group "*ready*" ] 128 | delete_debug_core [get_debug_cores {u_ila_0 }] 129 | create_debug_core u_ila_0 ila 130 | set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] 131 | set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] 132 | set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] 133 | set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] 134 | set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] 135 | set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] 136 | set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] 137 | set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] 138 | set_property port_width 1 [get_debug_ports u_ila_0/clk] 139 | connect_debug_port u_ila_0/clk [get_nets [list u_xilinx_pll/inst/clk_out1 ]] 140 | set_property port_width 32 [get_debug_ports u_ila_0/probe0] 141 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] 142 | connect_debug_port u_ila_0/probe0 [get_nets [list {addr[0]} {addr[1]} {addr[2]} {addr[3]} {addr[4]} {addr[5]} {addr[6]} {addr[7]} {addr[8]} {addr[9]} {addr[10]} {addr[11]} {addr[12]} {addr[13]} {addr[14]} {addr[15]} {addr[16]} {addr[17]} {addr[18]} {addr[19]} {addr[20]} {addr[21]} {addr[22]} {addr[23]} {addr[24]} {addr[25]} {addr[26]} {addr[27]} {addr[28]} {addr[29]} {addr[30]} {addr[31]} ]] 143 | create_debug_port u_ila_0 probe 144 | set_property port_width 32 [get_debug_ports u_ila_0/probe1] 145 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] 146 | connect_debug_port u_ila_0/probe1 [get_nets [list {rdata[0]} {rdata[1]} {rdata[2]} {rdata[3]} {rdata[4]} {rdata[5]} {rdata[6]} {rdata[7]} {rdata[8]} {rdata[9]} {rdata[10]} {rdata[11]} {rdata[12]} {rdata[13]} {rdata[14]} {rdata[15]} {rdata[16]} {rdata[17]} {rdata[18]} {rdata[19]} {rdata[20]} {rdata[21]} {rdata[22]} {rdata[23]} {rdata[24]} {rdata[25]} {rdata[26]} {rdata[27]} {rdata[28]} {rdata[29]} {rdata[30]} {rdata[31]} ]] 147 | create_debug_port u_ila_0 probe 148 | set_property port_width 4 [get_debug_ports u_ila_0/probe2] 149 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] 150 | connect_debug_port u_ila_0/probe2 [get_nets [list {ready[0]} {ready[1]} {ready[2]} {ready[3]} ]] 151 | create_debug_port u_ila_0 probe 152 | set_property port_width 32 [get_debug_ports u_ila_0/probe3] 153 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] 154 | connect_debug_port u_ila_0/probe3 [get_nets [list {wdata[0]} {wdata[1]} {wdata[2]} {wdata[3]} {wdata[4]} {wdata[5]} {wdata[6]} {wdata[7]} {wdata[8]} {wdata[9]} {wdata[10]} {wdata[11]} {wdata[12]} {wdata[13]} {wdata[14]} {wdata[15]} {wdata[16]} {wdata[17]} {wdata[18]} {wdata[19]} {wdata[20]} {wdata[21]} {wdata[22]} {wdata[23]} {wdata[24]} {wdata[25]} {wdata[26]} {wdata[27]} {wdata[28]} {wdata[29]} {wdata[30]} {wdata[31]} ]] 155 | create_debug_port u_ila_0 probe 156 | set_property port_width 1 [get_debug_ports u_ila_0/probe4] 157 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] 158 | connect_debug_port u_ila_0/probe4 [get_nets [list ss1/done ]] 159 | create_debug_port u_ila_0 probe 160 | set_property port_width 1 [get_debug_ports u_ila_0/probe5] 161 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] 162 | connect_debug_port u_ila_0/probe5 [get_nets [list resetn ]] 163 | create_debug_port u_ila_0 probe 164 | set_property port_width 1 [get_debug_ports u_ila_0/probe6] 165 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] 166 | connect_debug_port u_ila_0/probe6 [get_nets [list scan_mode ]] 167 | create_debug_port u_ila_0 probe 168 | set_property port_width 1 [get_debug_ports u_ila_0/probe7] 169 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] 170 | connect_debug_port u_ila_0/probe7 [get_nets [list sel ]] 171 | create_debug_port u_ila_0 probe 172 | set_property port_width 1 [get_debug_ports u_ila_0/probe8] 173 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] 174 | connect_debug_port u_ila_0/probe8 [get_nets [list write ]] 175 | close_design 176 | open_run synth_1 -name synth_1 177 | show_objects -name NET_ONLY [get_nets -hierarchical -top_net_of_hierarchical_group "*done*" ] 178 | delete_debug_core [get_debug_cores {u_ila_0 }] 179 | create_debug_core u_ila_0 ila 180 | set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] 181 | set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] 182 | set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] 183 | set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] 184 | set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] 185 | set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] 186 | set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] 187 | set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] 188 | set_property port_width 1 [get_debug_ports u_ila_0/clk] 189 | connect_debug_port u_ila_0/clk [get_nets [list u_xilinx_pll/inst/clk_out1 ]] 190 | set_property port_width 32 [get_debug_ports u_ila_0/probe0] 191 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] 192 | connect_debug_port u_ila_0/probe0 [get_nets [list {addr[0]} {addr[1]} {addr[2]} {addr[3]} {addr[4]} {addr[5]} {addr[6]} {addr[7]} {addr[8]} {addr[9]} {addr[10]} {addr[11]} {addr[12]} {addr[13]} {addr[14]} {addr[15]} {addr[16]} {addr[17]} {addr[18]} {addr[19]} {addr[20]} {addr[21]} {addr[22]} {addr[23]} {addr[24]} {addr[25]} {addr[26]} {addr[27]} {addr[28]} {addr[29]} {addr[30]} {addr[31]} ]] 193 | create_debug_port u_ila_0 probe 194 | set_property port_width 32 [get_debug_ports u_ila_0/probe1] 195 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] 196 | connect_debug_port u_ila_0/probe1 [get_nets [list {rdata[0]} {rdata[1]} {rdata[2]} {rdata[3]} {rdata[4]} {rdata[5]} {rdata[6]} {rdata[7]} {rdata[8]} {rdata[9]} {rdata[10]} {rdata[11]} {rdata[12]} {rdata[13]} {rdata[14]} {rdata[15]} {rdata[16]} {rdata[17]} {rdata[18]} {rdata[19]} {rdata[20]} {rdata[21]} {rdata[22]} {rdata[23]} {rdata[24]} {rdata[25]} {rdata[26]} {rdata[27]} {rdata[28]} {rdata[29]} {rdata[30]} {rdata[31]} ]] 197 | create_debug_port u_ila_0 probe 198 | set_property port_width 32 [get_debug_ports u_ila_0/probe2] 199 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] 200 | connect_debug_port u_ila_0/probe2 [get_nets [list {wdata[0]} {wdata[1]} {wdata[2]} {wdata[3]} {wdata[4]} {wdata[5]} {wdata[6]} {wdata[7]} {wdata[8]} {wdata[9]} {wdata[10]} {wdata[11]} {wdata[12]} {wdata[13]} {wdata[14]} {wdata[15]} {wdata[16]} {wdata[17]} {wdata[18]} {wdata[19]} {wdata[20]} {wdata[21]} {wdata[22]} {wdata[23]} {wdata[24]} {wdata[25]} {wdata[26]} {wdata[27]} {wdata[28]} {wdata[29]} {wdata[30]} {wdata[31]} ]] 201 | create_debug_port u_ila_0 probe 202 | set_property port_width 1 [get_debug_ports u_ila_0/probe3] 203 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] 204 | connect_debug_port u_ila_0/probe3 [get_nets [list done_OBUF ]] 205 | create_debug_port u_ila_0 probe 206 | set_property port_width 1 [get_debug_ports u_ila_0/probe4] 207 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] 208 | connect_debug_port u_ila_0/probe4 [get_nets [list resetn ]] 209 | create_debug_port u_ila_0 probe 210 | set_property port_width 1 [get_debug_ports u_ila_0/probe5] 211 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] 212 | connect_debug_port u_ila_0/probe5 [get_nets [list scan_mode ]] 213 | create_debug_port u_ila_0 probe 214 | set_property port_width 1 [get_debug_ports u_ila_0/probe6] 215 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] 216 | connect_debug_port u_ila_0/probe6 [get_nets [list sel ]] 217 | create_debug_port u_ila_0 probe 218 | set_property port_width 1 [get_debug_ports u_ila_0/probe7] 219 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] 220 | connect_debug_port u_ila_0/probe7 [get_nets [list write ]] 221 | save_constraints 222 | reset_run synth_1 223 | launch_runs synth_1 224 | wait_on_run synth_1 225 | close_design 226 | open_run synth_1 -name synth_1 227 | show_objects -name NET_ONLY [get_nets -hierarchical -top_net_of_hierarchical_group "*rd*" ] 228 | delete_debug_core [get_debug_cores {u_ila_0 }] 229 | create_debug_core u_ila_0 ila 230 | set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] 231 | set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] 232 | set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] 233 | set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] 234 | set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] 235 | set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] 236 | set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] 237 | set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] 238 | set_property port_width 1 [get_debug_ports u_ila_0/clk] 239 | connect_debug_port u_ila_0/clk [get_nets [list u_xilinx_pll/inst/clk_out1 ]] 240 | set_property port_width 32 [get_debug_ports u_ila_0/probe0] 241 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] 242 | connect_debug_port u_ila_0/probe0 [get_nets [list {wdata[0]} {wdata[1]} {wdata[2]} {wdata[3]} {wdata[4]} {wdata[5]} {wdata[6]} {wdata[7]} {wdata[8]} {wdata[9]} {wdata[10]} {wdata[11]} {wdata[12]} {wdata[13]} {wdata[14]} {wdata[15]} {wdata[16]} {wdata[17]} {wdata[18]} {wdata[19]} {wdata[20]} {wdata[21]} {wdata[22]} {wdata[23]} {wdata[24]} {wdata[25]} {wdata[26]} {wdata[27]} {wdata[28]} {wdata[29]} {wdata[30]} {wdata[31]} ]] 243 | create_debug_port u_ila_0 probe 244 | set_property port_width 32 [get_debug_ports u_ila_0/probe1] 245 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] 246 | connect_debug_port u_ila_0/probe1 [get_nets [list {rdata[0]} {rdata[1]} {rdata[2]} {rdata[3]} {rdata[4]} {rdata[5]} {rdata[6]} {rdata[7]} {rdata[8]} {rdata[9]} {rdata[10]} {rdata[11]} {rdata[12]} {rdata[13]} {rdata[14]} {rdata[15]} {rdata[16]} {rdata[17]} {rdata[18]} {rdata[19]} {rdata[20]} {rdata[21]} {rdata[22]} {rdata[23]} {rdata[24]} {rdata[25]} {rdata[26]} {rdata[27]} {rdata[28]} {rdata[29]} {rdata[30]} {rdata[31]} ]] 247 | create_debug_port u_ila_0 probe 248 | set_property port_width 4 [get_debug_ports u_ila_0/probe2] 249 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] 250 | connect_debug_port u_ila_0/probe2 [get_nets [list {rd[0]} {rd[1]} {rd[2]} {rd[3]} ]] 251 | create_debug_port u_ila_0 probe 252 | set_property port_width 32 [get_debug_ports u_ila_0/probe3] 253 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] 254 | connect_debug_port u_ila_0/probe3 [get_nets [list {addr[0]} {addr[1]} {addr[2]} {addr[3]} {addr[4]} {addr[5]} {addr[6]} {addr[7]} {addr[8]} {addr[9]} {addr[10]} {addr[11]} {addr[12]} {addr[13]} {addr[14]} {addr[15]} {addr[16]} {addr[17]} {addr[18]} {addr[19]} {addr[20]} {addr[21]} {addr[22]} {addr[23]} {addr[24]} {addr[25]} {addr[26]} {addr[27]} {addr[28]} {addr[29]} {addr[30]} {addr[31]} ]] 255 | create_debug_port u_ila_0 probe 256 | set_property port_width 1 [get_debug_ports u_ila_0/probe4] 257 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] 258 | connect_debug_port u_ila_0/probe4 [get_nets [list done_OBUF ]] 259 | create_debug_port u_ila_0 probe 260 | set_property port_width 1 [get_debug_ports u_ila_0/probe5] 261 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] 262 | connect_debug_port u_ila_0/probe5 [get_nets [list resetn ]] 263 | create_debug_port u_ila_0 probe 264 | set_property port_width 1 [get_debug_ports u_ila_0/probe6] 265 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] 266 | connect_debug_port u_ila_0/probe6 [get_nets [list scan_mode ]] 267 | create_debug_port u_ila_0 probe 268 | set_property port_width 1 [get_debug_ports u_ila_0/probe7] 269 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] 270 | connect_debug_port u_ila_0/probe7 [get_nets [list sel ]] 271 | create_debug_port u_ila_0 probe 272 | set_property port_width 1 [get_debug_ports u_ila_0/probe8] 273 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] 274 | connect_debug_port u_ila_0/probe8 [get_nets [list write ]] 275 | refresh_design 276 | reset_run synth_1 277 | launch_runs synth_1 278 | wait_on_run synth_1 279 | close_design 280 | open_run synth_1 -name synth_1 281 | delete_debug_core [get_debug_cores {u_ila_0 }] 282 | create_debug_core u_ila_0 ila 283 | set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] 284 | set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] 285 | set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] 286 | set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] 287 | set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] 288 | set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] 289 | set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] 290 | set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] 291 | set_property port_width 1 [get_debug_ports u_ila_0/clk] 292 | connect_debug_port u_ila_0/clk [get_nets [list u_xilinx_pll/inst/clk_out1 ]] 293 | set_property port_width 32 [get_debug_ports u_ila_0/probe0] 294 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] 295 | connect_debug_port u_ila_0/probe0 [get_nets [list {wdata[0]} {wdata[1]} {wdata[2]} {wdata[3]} {wdata[4]} {wdata[5]} {wdata[6]} {wdata[7]} {wdata[8]} {wdata[9]} {wdata[10]} {wdata[11]} {wdata[12]} {wdata[13]} {wdata[14]} {wdata[15]} {wdata[16]} {wdata[17]} {wdata[18]} {wdata[19]} {wdata[20]} {wdata[21]} {wdata[22]} {wdata[23]} {wdata[24]} {wdata[25]} {wdata[26]} {wdata[27]} {wdata[28]} {wdata[29]} {wdata[30]} {wdata[31]} ]] 296 | create_debug_port u_ila_0 probe 297 | set_property port_width 80 [get_debug_ports u_ila_0/probe1] 298 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] 299 | connect_debug_port u_ila_0/probe1 [get_nets [list {result[0]} {result[1]} {result[2]} {result[3]} {result[4]} {result[5]} {result[6]} {result[7]} {result[8]} {result[9]} {result[10]} {result[11]} {result[12]} {result[13]} {result[14]} {result[15]} {result[16]} {result[17]} {result[18]} {result[19]} {result[20]} {result[21]} {result[22]} {result[23]} {result[24]} {result[25]} {result[26]} {result[27]} {result[28]} {result[29]} {result[30]} {result[31]} {result[32]} {result[33]} {result[34]} {result[35]} {result[36]} {result[37]} {result[38]} {result[39]} {result[40]} {result[41]} {result[42]} {result[43]} {result[44]} {result[45]} {result[46]} {result[47]} {result[48]} {result[49]} {result[50]} {result[51]} {result[52]} {result[53]} {result[54]} {result[55]} {result[56]} {result[57]} {result[58]} {result[59]} {result[60]} {result[61]} {result[62]} {result[63]} {result[64]} {result[65]} {result[66]} {result[67]} {result[68]} {result[69]} {result[70]} {result[71]} {result[72]} {result[73]} {result[74]} {result[75]} {result[76]} {result[77]} {result[78]} {result[79]} ]] 300 | create_debug_port u_ila_0 probe 301 | set_property port_width 32 [get_debug_ports u_ila_0/probe2] 302 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] 303 | connect_debug_port u_ila_0/probe2 [get_nets [list {addr[0]} {addr[1]} {addr[2]} {addr[3]} {addr[4]} {addr[5]} {addr[6]} {addr[7]} {addr[8]} {addr[9]} {addr[10]} {addr[11]} {addr[12]} {addr[13]} {addr[14]} {addr[15]} {addr[16]} {addr[17]} {addr[18]} {addr[19]} {addr[20]} {addr[21]} {addr[22]} {addr[23]} {addr[24]} {addr[25]} {addr[26]} {addr[27]} {addr[28]} {addr[29]} {addr[30]} {addr[31]} ]] 304 | create_debug_port u_ila_0 probe 305 | set_property port_width 32 [get_debug_ports u_ila_0/probe3] 306 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] 307 | connect_debug_port u_ila_0/probe3 [get_nets [list {rdata[0]} {rdata[1]} {rdata[2]} {rdata[3]} {rdata[4]} {rdata[5]} {rdata[6]} {rdata[7]} {rdata[8]} {rdata[9]} {rdata[10]} {rdata[11]} {rdata[12]} {rdata[13]} {rdata[14]} {rdata[15]} {rdata[16]} {rdata[17]} {rdata[18]} {rdata[19]} {rdata[20]} {rdata[21]} {rdata[22]} {rdata[23]} {rdata[24]} {rdata[25]} {rdata[26]} {rdata[27]} {rdata[28]} {rdata[29]} {rdata[30]} {rdata[31]} ]] 308 | create_debug_port u_ila_0 probe 309 | set_property port_width 1 [get_debug_ports u_ila_0/probe4] 310 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] 311 | connect_debug_port u_ila_0/probe4 [get_nets [list done_OBUF ]] 312 | create_debug_port u_ila_0 probe 313 | set_property port_width 1 [get_debug_ports u_ila_0/probe5] 314 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] 315 | connect_debug_port u_ila_0/probe5 [get_nets [list resetn ]] 316 | create_debug_port u_ila_0 probe 317 | set_property port_width 1 [get_debug_ports u_ila_0/probe6] 318 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] 319 | connect_debug_port u_ila_0/probe6 [get_nets [list scan_mode ]] 320 | create_debug_port u_ila_0 probe 321 | set_property port_width 1 [get_debug_ports u_ila_0/probe7] 322 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] 323 | connect_debug_port u_ila_0/probe7 [get_nets [list sel ]] 324 | create_debug_port u_ila_0 probe 325 | set_property port_width 1 [get_debug_ports u_ila_0/probe8] 326 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] 327 | connect_debug_port u_ila_0/probe8 [get_nets [list write ]] 328 | save_constraints 329 | -------------------------------------------------------------------------------- /trng_top.v: -------------------------------------------------------------------------------- 1 | /* 2 | --This confidential and proprietary code may be used 3 | --only as authorized by a licensing agreement from 4 | --RCG.TWRI. 5 | --In the event of publication, the following notice is 6 | --applicable: 7 | -- 8 | -- (C) COPYRIGHT 2016 RCG.TWRI. 9 | -- ALL RIGHTS RESERVED 10 | -- 11 | -- The entire notice above must be reproduced on all 12 | --authorized copies. 13 | -- 14 | -- Filename : trng_top.v 15 | -- Author : Sunjj 16 | -- Date : 16/09/20 17 | -- Version : 0.1 18 | -- Description : trng_top 19 | -- 20 | -- Modification History: 21 | -- Date By Version Change Description 22 | -- 23 | ======================================================== 24 | -- 16/09/20 TH 0.1 Original 25 | -- 26 | ======================================================== 27 | */ 28 | 29 | module trng_top 30 | ( 31 | input CLK_I, 32 | input RESETN_I, 33 | 34 | input SEL_I, //chip select 35 | input [31:0] ADDR_I, //address 36 | input WRITE_I, //1:write 0:read 37 | input [31:0] WDATA_I, //write data 38 | output [31:0] RDATA_I, //read data 39 | 40 | input SCAN_MODE_I //scan mode enable 41 | 42 | ); 43 | 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2016.2 (64-bit) 3 | # SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016 4 | # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 5 | # Start of session at: Thu Apr 27 17:56:21 2017 6 | # Process ID: 85004 7 | # Current directory: /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709 8 | # Command line: vivado 9 | # Log file: /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709/vivado.log 10 | # Journal file: /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709/vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709/trng/trng.xpr 14 | update_compile_order -fileset sources_1 15 | reset_run synth_1 16 | reset_run xilinx_pll_synth_1 17 | launch_runs impl_1 -to_step write_bitstream -jobs 16 18 | wait_on_run impl_1 19 | reset_run impl_1 -noclean_dir 20 | launch_runs impl_1 -to_step write_bitstream -jobs 16 21 | wait_on_run impl_1 22 | reset_run impl_1 -noclean_dir 23 | -------------------------------------------------------------------------------- /vivado.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2016.2 (64-bit) 3 | # SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016 4 | # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 5 | # Start of session at: Thu Apr 27 17:56:21 2017 6 | # Process ID: 85004 7 | # Current directory: /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709 8 | # Command line: vivado 9 | # Log file: /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709/vivado.log 10 | # Journal file: /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709/vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | open_project /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709/trng/trng.xpr 14 | INFO: [Project 1-313] Project file moved from '/proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/trng' since last save. 15 | Scanning sources... 16 | Finished scanning sources 17 | INFO: [IP_Flow 19-234] Refreshing IP repositories 18 | INFO: [IP_Flow 19-1704] No user IP repositories specified 19 | INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/tools/xilinx/vivado/2016.2/data/ip'. 20 | update_compile_order -fileset sources_1 21 | reset_run synth_1 22 | reset_run xilinx_pll_synth_1 23 | launch_runs impl_1 -to_step write_bitstream -jobs 16 24 | [Thu Apr 27 17:59:52 2017] Launched xilinx_pll_synth_1, synth_1... 25 | Run output will be captured here: 26 | xilinx_pll_synth_1: /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709/trng/trng.runs/xilinx_pll_synth_1/runme.log 27 | synth_1: /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709/trng/trng.runs/synth_1/runme.log 28 | [Thu Apr 27 17:59:52 2017] Launched impl_1... 29 | Run output will be captured here: /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709/trng/trng.runs/impl_1/runme.log 30 | reset_run impl_1 -noclean_dir 31 | launch_runs impl_1 -to_step write_bitstream -jobs 16 32 | [Thu Apr 27 18:08:09 2017] Launched impl_1... 33 | Run output will be captured here: /proj/rcpfpga/wa/wangyf/trng_ip/fpga_proj_release/vc709/trng/trng.runs/impl_1/runme.log 34 | reset_run impl_1 -noclean_dir 35 | exit 36 | INFO: [Common 17-206] Exiting Vivado at Thu Apr 27 18:09:03 2017... 37 | -------------------------------------------------------------------------------- /vivado_45080.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2016.2 (64-bit) 3 | # SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016 4 | # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 5 | # Start of session at: Thu Apr 27 15:50:04 2017 6 | # Process ID: 45080 7 | # Current directory: /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709 8 | # Command line: vivado 9 | # Log file: /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/vivado.log 10 | # Journal file: /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/vivado.jou 11 | #----------------------------------------------------------- 12 | start_gui 13 | create_project trng /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/trng -part xc7vx690tffg1761-2 14 | set_property board_part xilinx.com:vc709:part0:1.8 [current_project] 15 | add_files -norecurse /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/fpga_filelist.v 16 | add_files -fileset constrs_1 -norecurse /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/xdc/trng.xdc 17 | update_compile_order -fileset sources_1 18 | update_compile_order -fileset sim_1 19 | remove_files /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/fpga_filelist.v 20 | update_compile_order -fileset sources_1 21 | update_compile_order -fileset sim_1 22 | add_files -norecurse /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/fpga_filelist.v 23 | update_compile_order -fileset sources_1 24 | update_compile_order -fileset sim_1 25 | remove_files /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/fpga_filelist.v 26 | update_compile_order -fileset sources_1 27 | update_compile_order -fileset sim_1 28 | add_files -norecurse /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/fpga_filelist.v 29 | update_compile_order -fileset sources_1 30 | update_compile_order -fileset sim_1 31 | # Disabling source management mode. This is to allow the top design properties to be set without GUI intervention. 32 | set_property source_mgmt_mode None [current_project] 33 | set_property top trng_top [current_fileset] 34 | # Re-enabling previously disabled source management mode. 35 | set_property source_mgmt_mode All [current_project] 36 | launch_runs synth_1 -jobs 16 37 | wait_on_run synth_1 38 | open_run synth_1 -name synth_1 39 | write_edif -force /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/trng_top.edf 40 | remove_files /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/fpga_filelist.v 41 | update_compile_order -fileset sim_1 42 | update_compile_order -fileset sources_1 43 | add_files -norecurse /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/trng_top.edf 44 | add_files -norecurse {/proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/trng_top.v /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/hack/trng_drive.v /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/hack/trng_fpga_top.v} 45 | update_compile_order -fileset sources_1 46 | update_compile_order -fileset sim_1 47 | create_ip -name clk_wiz -vendor xilinx.com -library ip -version 5.3 -module_name xilinx_pll 48 | set_property -dict [list CONFIG.CLK_IN1_BOARD_INTERFACE {sys_diff_clock} CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} CONFIG.RESET_BOARD_INTERFACE {reset} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {25} CONFIG.CLK_IN1_BOARD_INTERFACE {sys_diff_clock} CONFIG.PRIM_IN_FREQ {200.000} CONFIG.RESET_BOARD_INTERFACE {reset} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.MMCM_DIVCLK_DIVIDE {2} CONFIG.MMCM_CLKFBOUT_MULT_F {9.125} CONFIG.MMCM_CLKIN1_PERIOD {5.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {36.500} CONFIG.CLKOUT1_JITTER {178.502} CONFIG.CLKOUT1_PHASE_ERROR {104.359}] [get_ips xilinx_pll] 49 | generate_target {instantiation_template} [get_files /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll.xci] 50 | update_compile_order -fileset sources_1 51 | generate_target all [get_files /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll.xci] 52 | export_ip_user_files -of_objects [get_files /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll.xci] -no_script -force -quiet 53 | create_ip_run [get_files -of_objects [get_fileset sources_1] /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll.xci] 54 | launch_run -jobs 16 xilinx_pll_synth_1 55 | export_simulation -of_objects [get_files /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/trng/trng.srcs/sources_1/ip/xilinx_pll/xilinx_pll.xci] -directory /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/trng/trng.ip_user_files/sim_scripts -ip_user_files_dir /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/trng/trng.ip_user_files -ipstatic_source_dir /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/vc709/trng/trng.ip_user_files/ipstatic -force -quiet 56 | refresh_design 57 | report_ip_status -name ip_status 58 | report_ip_status -name ip_status 59 | add_files -norecurse /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/hack/trng_fpga_define.v 60 | update_compile_order -fileset sources_1 61 | set_property file_type {Verilog Header} [get_files /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/hack/trng_fpga_define.v] 62 | set_property is_global_include true [get_files /proj/rcpfpga/wa/wangyf/trng_ip/trng_vc709/fpga/hack/trng_fpga_define.v] 63 | update_compile_order -fileset sources_1 64 | refresh_design 65 | close_design 66 | reset_run synth_1 67 | launch_runs impl_1 -to_step write_bitstream -jobs 16 68 | wait_on_run impl_1 69 | reset_run impl_1 -noclean_dir 70 | open_run synth_1 -name synth_1 71 | create_debug_core u_ila_0 ila 72 | set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0] 73 | set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] 74 | set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] 75 | set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] 76 | set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] 77 | set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] 78 | set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] 79 | set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] 80 | set_property port_width 1 [get_debug_ports u_ila_0/clk] 81 | connect_debug_port u_ila_0/clk [get_nets [list u_xilinx_pll/inst/clk_out1 ]] 82 | set_property port_width 32 [get_debug_ports u_ila_0/probe0] 83 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] 84 | connect_debug_port u_ila_0/probe0 [get_nets [list {rdata[0]} {rdata[1]} {rdata[2]} {rdata[3]} {rdata[4]} {rdata[5]} {rdata[6]} {rdata[7]} {rdata[8]} {rdata[9]} {rdata[10]} {rdata[11]} {rdata[12]} {rdata[13]} {rdata[14]} {rdata[15]} {rdata[16]} {rdata[17]} {rdata[18]} {rdata[19]} {rdata[20]} {rdata[21]} {rdata[22]} {rdata[23]} {rdata[24]} {rdata[25]} {rdata[26]} {rdata[27]} {rdata[28]} {rdata[29]} {rdata[30]} {rdata[31]} ]] 85 | create_debug_port u_ila_0 probe 86 | set_property port_width 32 [get_debug_ports u_ila_0/probe1] 87 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] 88 | connect_debug_port u_ila_0/probe1 [get_nets [list {addr[0]} {addr[1]} {addr[2]} {addr[3]} {addr[4]} {addr[5]} {addr[6]} {addr[7]} {addr[8]} {addr[9]} {addr[10]} {addr[11]} {addr[12]} {addr[13]} {addr[14]} {addr[15]} {addr[16]} {addr[17]} {addr[18]} {addr[19]} {addr[20]} {addr[21]} {addr[22]} {addr[23]} {addr[24]} {addr[25]} {addr[26]} {addr[27]} {addr[28]} {addr[29]} {addr[30]} {addr[31]} ]] 89 | create_debug_port u_ila_0 probe 90 | set_property port_width 32 [get_debug_ports u_ila_0/probe2] 91 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] 92 | connect_debug_port u_ila_0/probe2 [get_nets [list {wdata[0]} {wdata[1]} {wdata[2]} {wdata[3]} {wdata[4]} {wdata[5]} {wdata[6]} {wdata[7]} {wdata[8]} {wdata[9]} {wdata[10]} {wdata[11]} {wdata[12]} {wdata[13]} {wdata[14]} {wdata[15]} {wdata[16]} {wdata[17]} {wdata[18]} {wdata[19]} {wdata[20]} {wdata[21]} {wdata[22]} {wdata[23]} {wdata[24]} {wdata[25]} {wdata[26]} {wdata[27]} {wdata[28]} {wdata[29]} {wdata[30]} {wdata[31]} ]] 93 | create_debug_port u_ila_0 probe 94 | set_property port_width 1 [get_debug_ports u_ila_0/probe3] 95 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] 96 | connect_debug_port u_ila_0/probe3 [get_nets [list resetn ]] 97 | create_debug_port u_ila_0 probe 98 | set_property port_width 1 [get_debug_ports u_ila_0/probe4] 99 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] 100 | connect_debug_port u_ila_0/probe4 [get_nets [list scan_mode ]] 101 | create_debug_port u_ila_0 probe 102 | set_property port_width 1 [get_debug_ports u_ila_0/probe5] 103 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] 104 | connect_debug_port u_ila_0/probe5 [get_nets [list sel ]] 105 | create_debug_port u_ila_0 probe 106 | set_property port_width 1 [get_debug_ports u_ila_0/probe6] 107 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] 108 | connect_debug_port u_ila_0/probe6 [get_nets [list write ]] 109 | save_constraints -force 110 | launch_runs impl_1 -to_step write_bitstream -jobs 16 111 | wait_on_run impl_1 112 | reset_run impl_1 -prev_step 113 | launch_runs impl_1 -to_step write_bitstream -jobs 16 114 | wait_on_run impl_1 115 | set_property SEVERITY {Warning} [get_drc_checks LUTLP-1] 116 | refresh_design 117 | set_property SEVERITY {Warning} [get_drc_checks LUTLP-1] 118 | save_constraints 119 | reset_run impl_1 -prev_step 120 | launch_runs impl_1 -to_step write_bitstream -jobs 16 121 | wait_on_run impl_1 122 | reset_run synth_1 123 | launch_runs impl_1 -to_step write_bitstream -jobs 16 124 | wait_on_run impl_1 125 | close_design 126 | reset_run synth_1 127 | launch_runs impl_1 -to_step write_bitstream -jobs 16 128 | wait_on_run impl_1 129 | --------------------------------------------------------------------------------