├── .github └── workflows │ └── test.yml ├── .gitignore ├── LICENSE ├── Makefile ├── README.md ├── img └── datapath.svg ├── project ├── build.properties └── plugins.sbt ├── scalastyle-config.xml ├── scalastyle-test-config.xml ├── soc ├── .gitignore ├── README.md ├── SoC_tb.wcfg ├── peripherals │ ├── clint │ │ ├── AXIBridge.v │ │ └── Clint.v │ ├── ddr │ │ └── ResetSynchronizer.v │ ├── gpio │ │ └── confreg.v │ └── lcd │ │ └── nt35510_controller │ │ ├── component.xml │ │ ├── src │ │ └── nt35510_apb_adapter_v1_0.v │ │ └── xgui │ │ ├── nt35510_apb_adapter_v1_0_v1_0.tcl │ │ └── nt35510_controller_v1_0.tcl ├── soc.srcs │ ├── constrs_1 │ │ └── new │ │ │ ├── io.xdc │ │ │ └── timing.xdc │ ├── sim_1 │ │ └── new │ │ │ ├── SoC_tb.v │ │ │ ├── s25fl128s.mem │ │ │ ├── s25fl128s.v │ │ │ └── s25fl128sOTP.mem │ └── sources_1 │ │ ├── bd │ │ ├── mref │ │ │ ├── Clint │ │ │ │ ├── component.xml │ │ │ │ └── xgui │ │ │ │ │ └── Clint_v1_0.tcl │ │ │ ├── FuxiWrapper │ │ │ │ ├── component.xml │ │ │ │ └── xgui │ │ │ │ │ └── FuxiWrapper_v1_0.tcl │ │ │ ├── ResetSynchronizer │ │ │ │ ├── component.xml │ │ │ │ └── xgui │ │ │ │ │ └── ResetSynchronizer_v1_0.tcl │ │ │ └── confreg │ │ │ │ ├── component.xml │ │ │ │ └── xgui │ │ │ │ └── confreg_v1_0.tcl │ │ └── soc │ │ │ ├── .gitignore │ │ │ ├── ip │ │ │ ├── .gitignore │ │ │ ├── soc_Clint_0_0 │ │ │ │ ├── soc_Clint_0_0.xci │ │ │ │ └── soc_Clint_0_0.xml │ │ │ ├── soc_FuxiWrapper_0_0 │ │ │ │ ├── soc_FuxiWrapper_0_0.xci │ │ │ │ └── soc_FuxiWrapper_0_0.xml │ │ │ ├── soc_ResetSynchronizer_0_0 │ │ │ │ ├── soc_ResetSynchronizer_0_0.xci │ │ │ │ └── soc_ResetSynchronizer_0_0.xml │ │ │ ├── soc_auto_cc_0 │ │ │ │ ├── soc_auto_cc_0.xci │ │ │ │ └── soc_auto_cc_0.xml │ │ │ ├── soc_auto_cc_1 │ │ │ │ ├── soc_auto_cc_1.xci │ │ │ │ └── soc_auto_cc_1.xml │ │ │ ├── soc_auto_cc_2 │ │ │ │ ├── soc_auto_cc_2.xci │ │ │ │ └── soc_auto_cc_2.xml │ │ │ ├── soc_auto_cc_3 │ │ │ │ ├── soc_auto_cc_3.xci │ │ │ │ └── soc_auto_cc_3.xml │ │ │ ├── soc_auto_ds_0 │ │ │ │ ├── soc_auto_ds_0.xci │ │ │ │ └── soc_auto_ds_0.xml │ │ │ ├── soc_auto_pc_0 │ │ │ │ ├── soc_auto_pc_0.xci │ │ │ │ └── soc_auto_pc_0.xml │ │ │ ├── soc_auto_pc_1 │ │ │ │ ├── soc_auto_pc_1.xci │ │ │ │ └── soc_auto_pc_1.xml │ │ │ ├── soc_auto_pc_2 │ │ │ │ ├── soc_auto_pc_2.xci │ │ │ │ └── soc_auto_pc_2.xml │ │ │ ├── soc_auto_pc_3 │ │ │ │ ├── soc_auto_pc_3.xci │ │ │ │ └── soc_auto_pc_3.xml │ │ │ ├── soc_auto_pc_4 │ │ │ │ ├── soc_auto_pc_4.xci │ │ │ │ └── soc_auto_pc_4.xml │ │ │ ├── soc_auto_pc_5 │ │ │ │ ├── soc_auto_pc_5.xci │ │ │ │ └── soc_auto_pc_5.xml │ │ │ ├── soc_auto_us_0 │ │ │ │ ├── soc_auto_us_0.xci │ │ │ │ └── soc_auto_us_0.xml │ │ │ ├── soc_axi_apb_bridge_0_0 │ │ │ │ ├── soc_axi_apb_bridge_0_0.xci │ │ │ │ └── soc_axi_apb_bridge_0_0.xml │ │ │ ├── soc_axi_bram_ctrl_0_0 │ │ │ │ ├── soc_axi_bram_ctrl_0_0.xci │ │ │ │ └── soc_axi_bram_ctrl_0_0.xml │ │ │ ├── soc_axi_ethernetlite_0_0 │ │ │ │ ├── soc_axi_ethernetlite_0_0.xci │ │ │ │ └── soc_axi_ethernetlite_0_0.xml │ │ │ ├── soc_axi_intc_0_0 │ │ │ │ ├── soc_axi_intc_0_0.xci │ │ │ │ └── soc_axi_intc_0_0.xml │ │ │ ├── soc_axi_interconnect_0_0 │ │ │ │ ├── soc_axi_interconnect_0_0.xci │ │ │ │ └── soc_axi_interconnect_0_0.xml │ │ │ ├── soc_axi_interconnect_0_1 │ │ │ │ ├── soc_axi_interconnect_0_1.xci │ │ │ │ └── soc_axi_interconnect_0_1.xml │ │ │ ├── soc_axi_interconnect_0_2 │ │ │ │ ├── soc_axi_interconnect_0_2.xci │ │ │ │ └── soc_axi_interconnect_0_2.xml │ │ │ ├── soc_axi_quad_spi_0_0 │ │ │ │ ├── soc_axi_quad_spi_0_0.xci │ │ │ │ └── soc_axi_quad_spi_0_0.xml │ │ │ ├── soc_axi_quad_spi_0_1 │ │ │ │ ├── soc_axi_quad_spi_0_1.xci │ │ │ │ └── soc_axi_quad_spi_0_1.xml │ │ │ ├── soc_axi_tft_0_0 │ │ │ │ ├── soc_axi_tft_0_0.xci │ │ │ │ └── soc_axi_tft_0_0.xml │ │ │ ├── soc_axi_uart16550_0_0 │ │ │ │ ├── soc_axi_uart16550_0_0.xci │ │ │ │ └── soc_axi_uart16550_0_0.xml │ │ │ ├── soc_blk_mem_gen_0_0 │ │ │ │ ├── soc_blk_mem_gen_0_0.xci │ │ │ │ └── soc_blk_mem_gen_0_0.xml │ │ │ ├── soc_clk_wiz_0_0 │ │ │ │ ├── soc_clk_wiz_0_0.xci │ │ │ │ └── soc_clk_wiz_0_0.xml │ │ │ ├── soc_confreg_0_0 │ │ │ │ ├── soc_confreg_0_0.xci │ │ │ │ └── soc_confreg_0_0.xml │ │ │ ├── soc_ila_0_0 │ │ │ │ ├── soc_ila_0_0.xci │ │ │ │ └── soc_ila_0_0.xml │ │ │ ├── soc_mig_7series_0_0 │ │ │ │ ├── mig_a.prj │ │ │ │ ├── soc_mig_7series_0_0.xci │ │ │ │ ├── soc_mig_7series_0_0.xml │ │ │ │ └── soc_mig_7series_0_0 │ │ │ │ │ ├── example_design │ │ │ │ │ └── sim │ │ │ │ │ │ └── xsim_files.prj │ │ │ │ │ └── mig.prj │ │ │ ├── soc_nt35510_controller_0_0 │ │ │ │ ├── soc_nt35510_controller_0_0.xci │ │ │ │ └── soc_nt35510_controller_0_0.xml │ │ │ ├── soc_proc_sys_reset_0_0 │ │ │ │ ├── soc_proc_sys_reset_0_0.xci │ │ │ │ └── soc_proc_sys_reset_0_0.xml │ │ │ ├── soc_s00_data_fifo_0 │ │ │ │ ├── soc_s00_data_fifo_0.xci │ │ │ │ └── soc_s00_data_fifo_0.xml │ │ │ ├── soc_s00_data_fifo_1 │ │ │ │ ├── soc_s00_data_fifo_1.xci │ │ │ │ └── soc_s00_data_fifo_1.xml │ │ │ ├── soc_s00_data_fifo_2 │ │ │ │ ├── soc_s00_data_fifo_2.xci │ │ │ │ └── soc_s00_data_fifo_2.xml │ │ │ ├── soc_s01_data_fifo_0 │ │ │ │ ├── soc_s01_data_fifo_0.xci │ │ │ │ └── soc_s01_data_fifo_0.xml │ │ │ ├── soc_s01_data_fifo_1 │ │ │ │ ├── soc_s01_data_fifo_1.xci │ │ │ │ └── soc_s01_data_fifo_1.xml │ │ │ ├── soc_s02_data_fifo_0 │ │ │ │ ├── soc_s02_data_fifo_0.xci │ │ │ │ └── soc_s02_data_fifo_0.xml │ │ │ ├── soc_system_ila_0_0 │ │ │ │ ├── bd_0 │ │ │ │ │ └── ip │ │ │ │ │ │ ├── ip_0 │ │ │ │ │ │ ├── bd_4e6a_ila_lib_0.xci │ │ │ │ │ │ └── bd_4e6a_ila_lib_0.xml │ │ │ │ │ │ ├── ip_1 │ │ │ │ │ │ ├── bd_4e6a_g_inst_0.xci │ │ │ │ │ │ └── bd_4e6a_g_inst_0.xml │ │ │ │ │ │ ├── ip_2 │ │ │ │ │ │ ├── bd_4e6a_slot_0_aw_0.xci │ │ │ │ │ │ └── bd_4e6a_slot_0_aw_0.xml │ │ │ │ │ │ ├── ip_3 │ │ │ │ │ │ ├── bd_4e6a_slot_0_w_0.xci │ │ │ │ │ │ └── bd_4e6a_slot_0_w_0.xml │ │ │ │ │ │ ├── ip_4 │ │ │ │ │ │ ├── bd_4e6a_slot_0_b_0.xci │ │ │ │ │ │ └── bd_4e6a_slot_0_b_0.xml │ │ │ │ │ │ ├── ip_5 │ │ │ │ │ │ ├── bd_4e6a_slot_0_ar_0.xci │ │ │ │ │ │ └── bd_4e6a_slot_0_ar_0.xml │ │ │ │ │ │ └── ip_6 │ │ │ │ │ │ ├── bd_4e6a_slot_0_r_0.xci │ │ │ │ │ │ └── bd_4e6a_slot_0_r_0.xml │ │ │ │ ├── soc_system_ila_0_0.xci │ │ │ │ └── soc_system_ila_0_0.xml │ │ │ ├── soc_util_vector_logic_0_0 │ │ │ │ ├── soc_util_vector_logic_0_0.xci │ │ │ │ └── soc_util_vector_logic_0_0.xml │ │ │ ├── soc_vio_0_0 │ │ │ │ ├── soc_vio_0_0.xci │ │ │ │ └── soc_vio_0_0.xml │ │ │ ├── soc_xbar_0 │ │ │ │ ├── soc_xbar_0.xci │ │ │ │ └── soc_xbar_0.xml │ │ │ ├── soc_xbar_1 │ │ │ │ ├── soc_xbar_1.xci │ │ │ │ └── soc_xbar_1.xml │ │ │ ├── soc_xbar_2 │ │ │ │ ├── soc_xbar_2.xci │ │ │ │ └── soc_xbar_2.xml │ │ │ ├── soc_xlconcat_0_0 │ │ │ │ ├── soc_xlconcat_0_0.xci │ │ │ │ └── soc_xlconcat_0_0.xml │ │ │ ├── soc_xlconstant_0_0 │ │ │ │ ├── soc_xlconstant_0_0.xci │ │ │ │ └── soc_xlconstant_0_0.xml │ │ │ └── soc_xlconstant_0_1 │ │ │ │ ├── soc_xlconstant_0_1.xci │ │ │ │ └── soc_xlconstant_0_1.xml │ │ │ ├── soc.bd │ │ │ ├── soc.bxml │ │ │ ├── soc_ooc.xdc │ │ │ └── ui │ │ │ └── bd_e0923ae7.ui │ │ └── new │ │ ├── SoC.v │ │ ├── iobuf.v │ │ └── ocm.coe └── soc.xpr ├── src ├── main │ └── scala │ │ ├── Fuxi.scala │ │ ├── axi │ │ └── AXI.scala │ │ ├── bpu │ │ ├── BTB.scala │ │ ├── BranchPredictor.scala │ │ ├── GHR.scala │ │ └── PHT.scala │ │ ├── bus │ │ ├── CoreBus.scala │ │ ├── DataCache.scala │ │ ├── InstCache.scala │ │ ├── MMU.scala │ │ ├── SramUtils.scala │ │ ├── TLB.scala │ │ └── Uncached.scala │ │ ├── consts │ │ ├── CSR.scala │ │ ├── Control.scala │ │ ├── Exception.scala │ │ ├── Instructions.scala │ │ ├── Operations.scala │ │ ├── Paging.scala │ │ └── Parameters.scala │ │ ├── core │ │ ├── ALU.scala │ │ ├── Core.scala │ │ ├── Decoder.scala │ │ ├── Fetch.scala │ │ ├── Mem.scala │ │ ├── RegFile.scala │ │ └── WriteBack.scala │ │ ├── csr │ │ ├── CSR.scala │ │ └── CsrFile.scala │ │ ├── io │ │ ├── BranchInfoIO.scala │ │ ├── BusIO.scala │ │ ├── CsrIO.scala │ │ ├── DebugIO.scala │ │ ├── ExcMonIO.scala │ │ ├── ExceptInfoIO.scala │ │ ├── RegIO.scala │ │ └── StageIO.scala │ │ ├── lsu │ │ ├── AmoExecute.scala │ │ ├── ExclusiveMonitor.scala │ │ └── LsuDecode.scala │ │ ├── mdu │ │ ├── Divider.scala │ │ ├── MDU.scala │ │ ├── MduDecode.scala │ │ └── Multiplier.scala │ │ ├── sim │ │ ├── RAM.scala │ │ └── ROM.scala │ │ └── utils │ │ ├── BlockMem.scala │ │ ├── HazardResolver.scala │ │ ├── MidStage.scala │ │ └── PipelineController.scala └── test │ ├── resources │ ├── fib.txt │ ├── fib_trace.txt │ ├── mdu.txt │ ├── mdu_trace.txt │ ├── mecall.txt │ ├── mecall_trace.txt │ ├── secall.txt │ └── secall_trace.txt │ └── scala │ ├── bpu │ └── BranchPredictorTest.scala │ ├── bus │ └── TlbTest.scala │ ├── core │ ├── AluTest.scala │ ├── CoreTest.scala │ ├── DecoderTest.scala │ ├── FetchTest.scala │ ├── MemTest.scala │ └── WriteBackTest.scala │ ├── csr │ └── CsrFileTest.scala │ ├── lsu │ ├── AmoExecuteTest.scala │ └── ExclusiveMonitorTest.scala │ ├── mdu │ ├── DividerTest.scala │ ├── MduTest.scala │ └── MultiplierTest.scala │ ├── sim │ └── RamTest.scala │ └── utils │ └── ArgParser.scala └── verilog └── FuxiWrapper.v /.github/workflows/test.yml: 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