├── .clang-format ├── .gitignore ├── .vs └── MProtect │ └── v14 │ └── .suo ├── DdiMon ├── DdiMon.inf ├── DdiMon.vcxproj ├── DdiMon.vcxproj.filters ├── DdiMon.vcxproj.user ├── ddi_mon.cpp ├── ddi_mon.h ├── shadow_hook.cpp └── shadow_hook.h ├── HyperPlatform ├── Documents │ └── UserDocument.odt ├── HyperPlatform.sln ├── HyperPlatform │ ├── Arch │ │ ├── x64 │ │ │ └── x64.asm │ │ └── x86 │ │ │ └── x86.asm │ ├── HyperPlatform.inf │ ├── HyperPlatform.vcxproj │ ├── HyperPlatform.vcxproj.filters │ ├── asm.h │ ├── common.h │ ├── driver.cpp │ ├── driver.h │ ├── ept.cpp │ ├── ept.h │ ├── global_object.cpp │ ├── global_object.h │ ├── hotplug_callback.cpp │ ├── hotplug_callback.h │ ├── ia32_type.h │ ├── kernel_stl.cpp │ ├── log.cpp │ ├── log.h │ ├── perf_counter.h │ ├── performance.cpp │ ├── performance.h │ ├── power_callback.cpp │ ├── power_callback.h │ ├── util.cpp │ ├── util.h │ ├── util_page_constants.h │ ├── vm.cpp │ ├── vm.h │ ├── vmm.cpp │ └── vmm.h └── clean.bat ├── IMProtect ├── IMProtect.aps ├── IMProtect.cpp ├── IMProtect.h ├── IMProtect.rc ├── IMProtect.vcxproj ├── IMProtect.vcxproj.filters ├── IMProtectDlg.cpp ├── IMProtectDlg.h ├── ReadMe.txt ├── res │ ├── IMProtect.ico │ └── IMProtect.rc2 ├── resource.h ├── stdafx.cpp ├── stdafx.h └── targetver.h ├── IntoProtect32 ├── Driver.c ├── Driver.h ├── HookProtect.c ├── HookProtect.h ├── IntoProtect32.inf ├── IntoProtect32.vcxproj ├── IntoProtect32.vcxproj.filters ├── ReadMe.txt └── Trace.h ├── LICENSE ├── LMProtect ├── GetShadowSsdtSym.cpp ├── GetShadowSsdtSym.h ├── GetSysInfo.cpp ├── GetSysInfo.h ├── IMGetData.cpp ├── IMGetData.h ├── IMProtect.cpp ├── IMProtect.h ├── LMProtect.vcxproj ├── LMProtect.vcxproj.filters ├── ReadMe.txt ├── stdafx.cpp ├── stdafx.h └── targetver.h ├── MProtect.sln ├── README.md ├── capstone ├── .appveyor.yml ├── .travis.yml ├── CMakeLists.txt ├── COMPILE.TXT ├── COMPILE_CMAKE.TXT ├── COMPILE_MSVC.TXT ├── CREDITS.TXT ├── ChangeLog ├── HACK.TXT ├── LEB128.h ├── LICENSE.TXT ├── LICENSE_LLVM.TXT ├── MCDisassembler.h ├── MCFixedLenDisassembler.h ├── MCInst.c ├── MCInst.h ├── MCInstrDesc.c ├── MCInstrDesc.h ├── MCRegisterInfo.c ├── MCRegisterInfo.h ├── Makefile ├── MathExtras.h ├── README ├── RELEASE_NOTES ├── SStream.c ├── SStream.h ├── TODO ├── arch │ ├── AArch64 │ │ ├── AArch64AddressingModes.h │ │ ├── AArch64BaseInfo.c │ │ ├── AArch64BaseInfo.h │ │ ├── AArch64Disassembler.c │ │ ├── AArch64Disassembler.h │ │ ├── AArch64GenAsmWriter.inc │ │ ├── AArch64GenDisassemblerTables.inc │ │ ├── AArch64GenInstrInfo.inc │ │ ├── AArch64GenRegisterInfo.inc │ │ ├── AArch64GenSubtargetInfo.inc │ │ ├── AArch64InstPrinter.c │ │ ├── AArch64InstPrinter.h │ │ ├── AArch64Mapping.c │ │ ├── AArch64Mapping.h │ │ └── AArch64Module.c │ ├── ARM │ │ ├── ARMAddressingModes.h │ │ ├── ARMBaseInfo.h │ │ ├── ARMDisassembler.c │ │ ├── ARMDisassembler.h │ │ ├── ARMGenAsmWriter.inc │ │ ├── ARMGenDisassemblerTables.inc │ │ ├── ARMGenInstrInfo.inc │ │ ├── ARMGenRegisterInfo.inc │ │ ├── ARMGenSubtargetInfo.inc │ │ ├── ARMInstPrinter.c │ │ ├── ARMInstPrinter.h │ │ ├── ARMMapping.c │ │ ├── ARMMapping.h │ │ └── ARMModule.c │ ├── Mips │ │ ├── MipsDisassembler.c │ │ ├── MipsDisassembler.h │ │ ├── MipsGenAsmWriter.inc │ │ ├── MipsGenDisassemblerTables.inc │ │ ├── MipsGenInstrInfo.inc │ │ ├── MipsGenRegisterInfo.inc │ │ ├── MipsGenSubtargetInfo.inc │ │ ├── MipsInstPrinter.c │ │ ├── MipsInstPrinter.h │ │ ├── MipsMapping.c │ │ ├── MipsMapping.h │ │ └── MipsModule.c │ ├── PowerPC │ │ ├── PPCDisassembler.c │ │ ├── PPCDisassembler.h │ │ ├── PPCGenAsmWriter.inc │ │ ├── PPCGenDisassemblerTables.inc │ │ ├── PPCGenInstrInfo.inc │ │ ├── PPCGenRegisterInfo.inc │ │ ├── PPCGenSubtargetInfo.inc │ │ ├── PPCInstPrinter.c │ │ ├── PPCInstPrinter.h │ │ ├── PPCMapping.c │ │ ├── PPCMapping.h │ │ ├── PPCModule.c │ │ └── PPCPredicates.h │ ├── Sparc │ │ ├── Sparc.h │ │ ├── SparcDisassembler.c │ │ ├── SparcDisassembler.h │ │ ├── SparcGenAsmWriter.inc │ │ ├── SparcGenDisassemblerTables.inc │ │ ├── SparcGenInstrInfo.inc │ │ ├── SparcGenRegisterInfo.inc │ │ ├── SparcGenSubtargetInfo.inc │ │ ├── SparcInstPrinter.c │ │ ├── SparcInstPrinter.h │ │ ├── SparcMapping.c │ │ ├── SparcMapping.h │ │ └── SparcModule.c │ ├── SystemZ │ │ ├── SystemZDisassembler.c │ │ ├── SystemZDisassembler.h │ │ ├── SystemZGenAsmWriter.inc │ │ ├── SystemZGenDisassemblerTables.inc │ │ ├── SystemZGenInstrInfo.inc │ │ ├── SystemZGenRegisterInfo.inc │ │ ├── SystemZGenSubtargetInfo.inc │ │ ├── SystemZInstPrinter.c │ │ ├── SystemZInstPrinter.h │ │ ├── SystemZMCTargetDesc.c │ │ ├── SystemZMCTargetDesc.h │ │ ├── SystemZMapping.c │ │ ├── SystemZMapping.h │ │ └── SystemZModule.c │ ├── X86 │ │ ├── X86ATTInstPrinter.c │ │ ├── X86BaseInfo.h │ │ ├── X86Disassembler.c │ │ ├── X86Disassembler.h │ │ ├── X86DisassemblerDecoder.c │ │ ├── X86DisassemblerDecoder.h │ │ ├── X86DisassemblerDecoderCommon.h │ │ ├── X86GenAsmWriter.inc │ │ ├── X86GenAsmWriter1.inc │ │ ├── X86GenAsmWriter1_reduce.inc │ │ ├── X86GenAsmWriter_reduce.inc │ │ ├── X86GenDisassemblerTables.inc │ │ ├── X86GenDisassemblerTables_reduce.inc │ │ ├── X86GenInstrInfo.inc │ │ ├── X86GenInstrInfo_reduce.inc │ │ ├── X86GenRegisterInfo.inc │ │ ├── X86InstPrinter.h │ │ ├── X86IntelInstPrinter.c │ │ ├── X86Mapping.c │ │ ├── X86Mapping.h │ │ └── X86Module.c │ └── XCore │ │ ├── XCoreDisassembler.c │ │ ├── XCoreDisassembler.h │ │ ├── XCoreGenAsmWriter.inc │ │ ├── XCoreGenDisassemblerTables.inc │ │ ├── XCoreGenInstrInfo.inc │ │ ├── XCoreGenRegisterInfo.inc │ │ ├── XCoreInstPrinter.c │ │ ├── XCoreInstPrinter.h │ │ ├── XCoreMapping.c │ │ ├── XCoreMapping.h │ │ └── XCoreModule.c ├── bindings │ ├── Makefile │ ├── README │ ├── const_generator.py │ ├── java │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── README │ │ ├── Test.java │ │ ├── TestArm.java │ │ ├── TestArm64.java │ │ ├── TestMips.java │ │ ├── TestPpc.java │ │ ├── TestSparc.java │ │ ├── TestSystemz.java │ │ ├── TestX86.java │ │ ├── TestXcore.java │ │ ├── capstone │ │ │ ├── .gitignore │ │ │ ├── Arm.java │ │ │ ├── Arm64.java │ │ │ ├── Arm64_const.java │ │ │ ├── Arm_const.java │ │ │ ├── Capstone.java │ │ │ ├── Mips.java │ │ │ ├── Mips_const.java │ │ │ ├── Ppc.java │ │ │ ├── Ppc_const.java │ │ │ ├── Sparc.java │ │ │ ├── Sparc_const.java │ │ │ ├── Systemz.java │ │ │ ├── Sysz_const.java │ │ │ ├── X86.java │ │ │ ├── X86_const.java │ │ │ ├── Xcore.java │ │ │ └── Xcore_const.java │ │ └── run.sh │ ├── ocaml │ │ ├── Makefile │ │ ├── README │ │ ├── arm.ml │ │ ├── arm64.ml │ │ ├── arm64_const.ml │ │ ├── arm_const.ml │ │ ├── capstone.ml │ │ ├── mips.ml │ │ ├── mips_const.ml │ │ ├── ocaml.c │ │ ├── ppc.ml │ │ ├── ppc_const.ml │ │ ├── sparc.ml │ │ ├── sparc_const.ml │ │ ├── systemz.ml │ │ ├── sysz_const.ml │ │ ├── test.ml │ │ ├── test_arm.ml │ │ ├── test_arm64.ml │ │ ├── test_detail.ml │ │ ├── test_mips.ml │ │ ├── test_ppc.ml │ │ ├── test_sparc.ml │ │ ├── test_systemz.ml │ │ ├── test_x86.ml │ │ ├── test_xcore.ml │ │ ├── x86.ml │ │ ├── x86_const.ml │ │ ├── xcore.ml │ │ └── xcore_const.ml │ └── python │ │ ├── .gitignore │ │ ├── LICENSE.TXT │ │ ├── MANIFEST.in │ │ ├── Makefile │ │ ├── PKG-INFO.src │ │ ├── PKG-INFO.win │ │ ├── README.TXT │ │ ├── README.pypi-src │ │ ├── README.pypi-win │ │ ├── capstone │ │ ├── __init__.py │ │ ├── arm.py │ │ ├── arm64.py │ │ ├── arm64_const.py │ │ ├── arm_const.py │ │ ├── mips.py │ │ ├── mips_const.py │ │ ├── ppc.py │ │ ├── ppc_const.py │ │ ├── sparc.py │ │ ├── sparc_const.py │ │ ├── systemz.py │ │ ├── sysz_const.py │ │ ├── x86.py │ │ ├── x86_const.py │ │ ├── xcore.py │ │ └── xcore_const.py │ │ ├── prebuilt │ │ ├── win32 │ │ │ └── .gitignore │ │ └── win64 │ │ │ └── .gitignore │ │ ├── pyx │ │ ├── README │ │ ├── ccapstone.pxd │ │ └── ccapstone.pyx │ │ ├── setup.py │ │ ├── setup_cython.py │ │ ├── test.py │ │ ├── test_all.py │ │ ├── test_arm.py │ │ ├── test_arm64.py │ │ ├── test_detail.py │ │ ├── test_lite.py │ │ ├── test_mips.py │ │ ├── test_ppc.py │ │ ├── test_skipdata.py │ │ ├── test_sparc.py │ │ ├── test_systemz.py │ │ ├── test_x86.py │ │ ├── test_xcore.py │ │ └── xprint.py ├── config.mk ├── contrib │ ├── README │ ├── cs_driver │ │ ├── README │ │ ├── cs_driver.sln │ │ └── cs_driver │ │ │ ├── cs_driver.c │ │ │ ├── cs_driver.vcxproj │ │ │ └── cs_driver.vcxproj.filters │ └── windows_kernel │ │ ├── README │ │ ├── libc.cpp │ │ └── libc.h ├── cs.c ├── cs_priv.h ├── docs │ ├── BHUSA2014-capstone.pdf │ └── README ├── functions.mk ├── include │ ├── arm.h │ ├── arm64.h │ ├── capstone.h │ ├── mips.h │ ├── platform.h │ ├── ppc.h │ ├── sparc.h │ ├── systemz.h │ ├── x86.h │ └── xcore.h ├── make.sh ├── msvc │ ├── README │ ├── capstone.sln │ ├── capstone_dll │ │ └── capstone_dll.vcxproj │ ├── capstone_static │ │ └── capstone_static.vcxproj │ ├── capstone_static_winkernel │ │ ├── Debug │ │ │ ├── AArch64BaseInfo.obj │ │ │ ├── AArch64Disassembler.obj │ │ │ ├── AArch64InstPrinter.obj │ │ │ ├── AArch64Mapping.obj │ │ │ ├── AArch64Module.obj │ │ │ ├── ARMDisassembler.obj │ │ │ ├── ARMInstPrinter.obj │ │ │ ├── ARMMapping.obj │ │ │ ├── ARMModule.obj │ │ │ ├── MCInst.obj │ │ │ ├── MCInstrDesc.obj │ │ │ ├── MCRegisterInfo.obj │ │ │ ├── MipsDisassembler.obj │ │ │ ├── MipsInstPrinter.obj │ │ │ ├── MipsMapping.obj │ │ │ ├── MipsModule.obj │ │ │ ├── PPCDisassembler.obj │ │ │ ├── PPCInstPrinter.obj │ │ │ ├── PPCMapping.obj │ │ │ ├── PPCModule.obj │ │ │ ├── SStream.obj │ │ │ ├── SparcDisassembler.obj │ │ │ ├── SparcInstPrinter.obj │ │ │ ├── SparcMapping.obj │ │ │ ├── SparcModule.obj │ │ │ ├── SystemZDisassembler.obj │ │ │ ├── SystemZInstPrinter.obj │ │ │ ├── SystemZMCTargetDesc.obj │ │ │ ├── SystemZMapping.obj │ │ │ ├── SystemZModule.obj │ │ │ ├── X86ATTInstPrinter.obj │ │ │ ├── X86Disassembler.obj │ │ │ ├── X86DisassemblerDecoder.obj │ │ │ ├── X86IntelInstPrinter.obj │ │ │ ├── X86Mapping.obj │ │ │ ├── X86Module.obj │ │ │ ├── XCoreDisassembler.obj │ │ │ ├── XCoreInstPrinter.obj │ │ │ ├── XCoreMapping.obj │ │ │ ├── XCoreModule.obj │ │ │ ├── capstone.FE197816.tlog │ │ │ │ ├── CL.command.1.tlog │ │ │ │ ├── CL.read.1.tlog │ │ │ │ ├── CL.write.1.tlog │ │ │ │ └── capstone_static_winkernel.lastbuildstate │ │ │ ├── capstone_static_winkernel.log │ │ │ ├── capstone_static_winkernel.pdb │ │ │ ├── cs.obj │ │ │ ├── utils.obj │ │ │ └── winkernel_mm.obj │ │ └── capstone_static_winkernel.vcxproj │ ├── test │ │ └── test.vcxproj │ ├── test_arm │ │ └── test_arm.vcxproj │ ├── test_arm64 │ │ └── test_arm64.vcxproj │ ├── test_detail │ │ └── test_detail.vcxproj │ ├── test_iter │ │ └── test_iter.vcxproj │ ├── test_mips │ │ └── test_mips.vcxproj │ ├── test_ppc │ │ └── test_ppc.vcxproj │ ├── test_skipdata │ │ └── test_skipdata.vcxproj │ ├── test_sparc │ │ └── test_sparc.vcxproj │ ├── test_systemz │ │ └── test_systemz.vcxproj │ ├── test_winkernel │ │ └── test_winkernel.vcxproj │ ├── test_x86 │ │ └── test_x86.vcxproj │ └── test_xcore │ │ └── test_xcore.vcxproj ├── packages │ ├── freebsd │ │ └── ports │ │ │ └── devel │ │ │ └── capstone │ │ │ ├── Makefile │ │ │ ├── pkg-descr │ │ │ └── pkg-plist │ ├── homebrew │ │ ├── README │ │ └── capstone.rb │ ├── macports │ │ └── devel │ │ │ └── capstone │ │ │ ├── Portfile │ │ │ └── files │ │ │ └── patch-Makefile.diff │ └── rpm │ │ └── capstone.spec ├── pkgconfig.mk ├── suite │ ├── MC │ │ ├── AArch64 │ │ │ ├── basic-a64-instructions.s.cs │ │ │ ├── gicv3-regs.s.cs │ │ │ ├── neon-2velem.s.cs │ │ │ ├── neon-3vdiff.s.cs │ │ │ ├── neon-aba-abd.s.cs │ │ │ ├── neon-across.s.cs │ │ │ ├── neon-add-pairwise.s.cs │ │ │ ├── neon-add-sub-instructions.s.cs │ │ │ ├── neon-bitwise-instructions.s.cs │ │ │ ├── neon-compare-instructions.s.cs │ │ │ ├── neon-crypto.s.cs │ │ │ ├── neon-extract.s.cs │ │ │ ├── neon-facge-facgt.s.cs │ │ │ ├── neon-frsqrt-frecp.s.cs │ │ │ ├── neon-halving-add-sub.s.cs │ │ │ ├── neon-max-min-pairwise.s.cs │ │ │ ├── neon-max-min.s.cs │ │ │ ├── neon-mla-mls-instructions.s.cs │ │ │ ├── neon-mov.s.cs │ │ │ ├── neon-mul-div-instructions.s.cs │ │ │ ├── neon-perm.s.cs │ │ │ ├── neon-rounding-halving-add.s.cs │ │ │ ├── neon-rounding-shift.s.cs │ │ │ ├── neon-saturating-add-sub.s.cs │ │ │ ├── neon-saturating-rounding-shift.s.cs │ │ │ ├── neon-saturating-shift.s.cs │ │ │ ├── neon-scalar-abs.s.cs │ │ │ ├── neon-scalar-add-sub.s.cs │ │ │ ├── neon-scalar-by-elem-mla.s.cs │ │ │ ├── neon-scalar-by-elem-mul.s.cs │ │ │ ├── neon-scalar-by-elem-saturating-mla.s.cs │ │ │ ├── neon-scalar-by-elem-saturating-mul.s.cs │ │ │ ├── neon-scalar-compare.s.cs │ │ │ ├── neon-scalar-cvt.s.cs │ │ │ ├── neon-scalar-dup.s.cs │ │ │ ├── neon-scalar-extract-narrow.s.cs │ │ │ ├── neon-scalar-fp-compare.s.cs │ │ │ ├── neon-scalar-mul.s.cs │ │ │ ├── neon-scalar-neg.s.cs │ │ │ ├── neon-scalar-recip.s.cs │ │ │ ├── neon-scalar-reduce-pairwise.s.cs │ │ │ ├── neon-scalar-rounding-shift.s.cs │ │ │ ├── neon-scalar-saturating-add-sub.s.cs │ │ │ ├── neon-scalar-saturating-rounding-shift.s.cs │ │ │ ├── neon-scalar-saturating-shift.s.cs │ │ │ ├── neon-scalar-shift-imm.s.cs │ │ │ ├── neon-scalar-shift.s.cs │ │ │ ├── neon-shift-left-long.s.cs │ │ │ ├── neon-shift.s.cs │ │ │ ├── neon-simd-copy.s.cs │ │ │ ├── neon-simd-ldst-multi-elem.s.cs │ │ │ ├── neon-simd-ldst-one-elem.s.cs │ │ │ ├── neon-simd-misc.s.cs │ │ │ ├── neon-simd-post-ldst-multi-elem.s.cs │ │ │ ├── neon-simd-shift.s.cs │ │ │ ├── neon-tbl.s.cs │ │ │ └── trace-regs.s.cs │ │ ├── ARM │ │ │ ├── arm-aliases.s.cs │ │ │ ├── arm-arithmetic-aliases.s.cs │ │ │ ├── arm-it-block.s.cs │ │ │ ├── arm-memory-instructions.s.cs │ │ │ ├── arm-shift-encoding.s.cs │ │ │ ├── arm-thumb-trustzone.s.cs │ │ │ ├── arm-trustzone.s.cs │ │ │ ├── arm_addrmode2.s.cs │ │ │ ├── arm_addrmode3.s.cs │ │ │ ├── arm_instructions.s.cs │ │ │ ├── basic-arm-instructions-v8.s.cs │ │ │ ├── basic-arm-instructions.s.cs │ │ │ ├── basic-thumb-instructions.s.cs │ │ │ ├── basic-thumb2-instructions-v8.s.cs │ │ │ ├── basic-thumb2-instructions.s.cs │ │ │ ├── crc32-thumb.s.cs │ │ │ ├── crc32.s.cs │ │ │ ├── dot-req.s.cs │ │ │ ├── fp-armv8.s.cs │ │ │ ├── idiv-thumb.s.cs │ │ │ ├── idiv.s.cs │ │ │ ├── load-store-acquire-release-v8-thumb.s.cs │ │ │ ├── load-store-acquire-release-v8.s.cs │ │ │ ├── mode-switch.s.cs │ │ │ ├── neon-abs-encoding.s.cs │ │ │ ├── neon-absdiff-encoding.s.cs │ │ │ ├── neon-add-encoding.s.cs │ │ │ ├── neon-bitcount-encoding.s.cs │ │ │ ├── neon-bitwise-encoding.s.cs │ │ │ ├── neon-cmp-encoding.s.cs │ │ │ ├── neon-convert-encoding.s.cs │ │ │ ├── neon-crypto.s.cs │ │ │ ├── neon-dup-encoding.s.cs │ │ │ ├── neon-minmax-encoding.s.cs │ │ │ ├── neon-mov-encoding.s.cs │ │ │ ├── neon-mul-accum-encoding.s.cs │ │ │ ├── neon-mul-encoding.s.cs │ │ │ ├── neon-neg-encoding.s.cs │ │ │ ├── neon-pairwise-encoding.s.cs │ │ │ ├── neon-reciprocal-encoding.s.cs │ │ │ ├── neon-reverse-encoding.s.cs │ │ │ ├── neon-satshift-encoding.s.cs │ │ │ ├── neon-shift-encoding.s.cs │ │ │ ├── neon-shiftaccum-encoding.s.cs │ │ │ ├── neon-shuffle-encoding.s.cs │ │ │ ├── neon-sub-encoding.s.cs │ │ │ ├── neon-table-encoding.s.cs │ │ │ ├── neon-v8.s.cs │ │ │ ├── neon-vld-encoding.s.cs │ │ │ ├── neon-vst-encoding.s.cs │ │ │ ├── neon-vswp.s.cs │ │ │ ├── neont2-abs-encoding.s.cs │ │ │ ├── neont2-absdiff-encoding.s.cs │ │ │ ├── neont2-add-encoding.s.cs │ │ │ ├── neont2-bitcount-encoding.s.cs │ │ │ ├── neont2-bitwise-encoding.s.cs │ │ │ ├── neont2-cmp-encoding.s.cs │ │ │ ├── neont2-convert-encoding.s.cs │ │ │ ├── neont2-dup-encoding.s.cs │ │ │ ├── neont2-minmax-encoding.s.cs │ │ │ ├── neont2-mov-encoding.s.cs │ │ │ ├── neont2-mul-accum-encoding.s.cs │ │ │ ├── neont2-mul-encoding.s.cs │ │ │ ├── neont2-neg-encoding.s.cs │ │ │ ├── neont2-pairwise-encoding.s.cs │ │ │ ├── neont2-reciprocal-encoding.s.cs │ │ │ ├── neont2-reverse-encoding.s.cs │ │ │ ├── neont2-satshift-encoding.s.cs │ │ │ ├── neont2-shift-encoding.s.cs │ │ │ ├── neont2-shiftaccum-encoding.s.cs │ │ │ ├── neont2-shuffle-encoding.s.cs │ │ │ ├── neont2-sub-encoding.s.cs │ │ │ ├── neont2-table-encoding.s.cs │ │ │ ├── neont2-vld-encoding.s.cs │ │ │ ├── neont2-vst-encoding.s.cs │ │ │ ├── simple-fp-encoding.s.cs │ │ │ ├── thumb-fp-armv8.s.cs │ │ │ ├── thumb-hints.s.cs │ │ │ ├── thumb-neon-crypto.s.cs │ │ │ ├── thumb-neon-v8.s.cs │ │ │ ├── thumb-shift-encoding.s.cs │ │ │ ├── thumb.s.cs │ │ │ ├── thumb2-b.w-encodingT4.s.cs │ │ │ ├── thumb2-branches.s.cs │ │ │ ├── thumb2-mclass.s.cs │ │ │ ├── thumb2-narrow-dp.ll.cs │ │ │ ├── thumb2-pldw.s.cs │ │ │ ├── vfp4-thumb.s.cs │ │ │ ├── vfp4.s.cs │ │ │ ├── vpush-vpop-thumb.s.cs │ │ │ └── vpush-vpop.s.cs │ │ ├── Mips │ │ │ ├── hilo-addressing.s.cs │ │ │ ├── micromips-alu-instructions-EB.s.cs │ │ │ ├── micromips-alu-instructions.s.cs │ │ │ ├── micromips-branch-instructions-EB.s.cs │ │ │ ├── micromips-branch-instructions.s.cs │ │ │ ├── micromips-expansions.s.cs │ │ │ ├── micromips-jump-instructions-EB.s.cs │ │ │ ├── micromips-jump-instructions.s.cs │ │ │ ├── micromips-loadstore-instructions-EB.s.cs │ │ │ ├── micromips-loadstore-instructions.s.cs │ │ │ ├── micromips-loadstore-unaligned-EB.s.cs │ │ │ ├── micromips-loadstore-unaligned.s.cs │ │ │ ├── micromips-movcond-instructions-EB.s.cs │ │ │ ├── micromips-movcond-instructions.s.cs │ │ │ ├── micromips-multiply-instructions-EB.s.cs │ │ │ ├── micromips-multiply-instructions.s.cs │ │ │ ├── micromips-shift-instructions-EB.s.cs │ │ │ ├── micromips-shift-instructions.s.cs │ │ │ ├── micromips-trap-instructions-EB.s.cs │ │ │ ├── micromips-trap-instructions.s.cs │ │ │ ├── mips-alu-instructions.s.cs │ │ │ ├── mips-control-instructions-64.s.cs │ │ │ ├── mips-control-instructions.s.cs │ │ │ ├── mips-coprocessor-encodings.s.cs │ │ │ ├── mips-dsp-instructions.s.cs │ │ │ ├── mips-expansions.s.cs │ │ │ ├── mips-fpu-instructions.s.cs │ │ │ ├── mips-jump-instructions.s.cs │ │ │ ├── mips-memory-instructions.s.cs │ │ │ ├── mips-register-names.s.cs │ │ │ ├── mips64-alu-instructions.s.cs │ │ │ ├── mips64-instructions.s.cs │ │ │ ├── mips64-register-names.s.cs │ │ │ ├── mips_directives.s.cs │ │ │ ├── nabi-regs.s.cs │ │ │ ├── set-at-directive.s.cs │ │ │ ├── test_2r.s.cs │ │ │ ├── test_2rf.s.cs │ │ │ ├── test_3r.s.cs │ │ │ ├── test_3rf.s.cs │ │ │ ├── test_bit.s.cs │ │ │ ├── test_cbranch.s.cs │ │ │ ├── test_ctrlregs.s.cs │ │ │ ├── test_elm.s.cs │ │ │ ├── test_elm_insert.s.cs │ │ │ ├── test_elm_insve.s.cs │ │ │ ├── test_i10.s.cs │ │ │ ├── test_i5.s.cs │ │ │ ├── test_i8.s.cs │ │ │ ├── test_lsa.s.cs │ │ │ ├── test_mi10.s.cs │ │ │ └── test_vec.s.cs │ │ ├── PowerPC │ │ │ ├── ppc64-encoding-bookII.s.cs │ │ │ ├── ppc64-encoding-bookIII.s.cs │ │ │ ├── ppc64-encoding-ext.s.cs │ │ │ ├── ppc64-encoding-fp.s.cs │ │ │ ├── ppc64-encoding-vmx.s.cs │ │ │ ├── ppc64-encoding.s.cs │ │ │ └── ppc64-operands.s.cs │ │ ├── README │ │ ├── Sparc │ │ │ ├── sparc-alu-instructions.s.cs │ │ │ ├── sparc-atomic-instructions.s.cs │ │ │ ├── sparc-ctrl-instructions.s.cs │ │ │ ├── sparc-fp-instructions.s.cs │ │ │ ├── sparc-mem-instructions.s.cs │ │ │ ├── sparc-vis.s.cs │ │ │ ├── sparc64-alu-instructions.s.cs │ │ │ ├── sparc64-ctrl-instructions.s.cs │ │ │ ├── sparcv8-instructions.s.cs │ │ │ └── sparcv9-instructions.s.cs │ │ ├── SystemZ │ │ │ ├── insn-good-z196.s.cs │ │ │ ├── insn-good.s.cs │ │ │ └── regs-good.s.cs │ │ └── X86 │ │ │ ├── 3DNow.s.cs │ │ │ ├── address-size.s.cs │ │ │ ├── avx512-encodings.s.cs │ │ │ ├── intel-syntax-encoding.s.cs │ │ │ ├── x86-32-avx.s.cs │ │ │ ├── x86-32-fma3.s.cs │ │ │ ├── x86-32-ms-inline-asm.s.cs │ │ │ ├── x86_64-avx-clmul-encoding.s.cs │ │ │ ├── x86_64-avx-encoding.s.cs │ │ │ ├── x86_64-bmi-encoding.s.cs │ │ │ ├── x86_64-encoding.s.cs │ │ │ ├── x86_64-fma3-encoding.s.cs │ │ │ ├── x86_64-fma4-encoding.s.cs │ │ │ ├── x86_64-hle-encoding.s.cs │ │ │ ├── x86_64-imm-widths.s.cs │ │ │ ├── x86_64-rand-encoding.s.cs │ │ │ ├── x86_64-rtm-encoding.s.cs │ │ │ ├── x86_64-sse4a.s.cs │ │ │ ├── x86_64-tbm-encoding.s.cs │ │ │ └── x86_64-xop-encoding.s.cs │ ├── README │ ├── arm │ │ ├── Makefile │ │ └── test_arm_regression.c │ ├── benchmark.py │ ├── benchmark │ │ ├── Makefile │ │ └── test_iter_benchmark.c │ ├── compile_all.sh │ ├── fuzz.py │ ├── fuzz │ │ ├── Makefile │ │ ├── README │ │ └── fuzz_harness.c │ ├── patch_major_os_version.py │ ├── ppcbranch.py │ ├── python_capstone_setup.py │ ├── regress.py │ ├── regress │ │ ├── Makefile │ │ └── invalid_read_in_print_operand.c │ ├── test_all.sh │ ├── test_c.sh │ ├── test_group_name.py │ ├── test_mc.py │ ├── test_mc.sh │ ├── test_python.sh │ └── x86odd.py ├── tests │ ├── Makefile │ ├── README │ ├── test.c │ ├── test_arm.c │ ├── test_arm64.c │ ├── test_detail.c │ ├── test_iter.c │ ├── test_mips.c │ ├── test_ppc.c │ ├── test_skipdata.c │ ├── test_sparc.c │ ├── test_systemz.c │ ├── test_winkernel.cpp │ ├── test_x86.c │ └── test_xcore.c ├── utils.c ├── utils.h ├── windows │ ├── README │ ├── winkernel_mm.c │ └── winkernel_mm.h └── xcode │ ├── Capstone.xcodeproj │ ├── project.pbxproj │ ├── project.xcworkspace │ │ └── contents.xcworkspacedata │ └── xcshareddata │ │ └── xcschemes │ │ ├── Dynamic Library.xcscheme │ │ ├── Framework.xcscheme │ │ ├── Static Library.xcscheme │ │ └── Tests.xcscheme │ ├── CapstoneFramework │ └── Info.plist │ └── README.md └── clean.bat /.gitignore: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 此 .gitignore 文件已由 Microsoft(R) Visual Studio 自动创建。 3 | ################################################################################ 4 | 5 | *.db 6 | /DdiMon.VC.VC.opendb 7 | *.tlog 8 | *.tlog 9 | -------------------------------------------------------------------------------- /.vs/MProtect/v14/.suo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/.vs/MProtect/v14/.suo -------------------------------------------------------------------------------- /DdiMon/DdiMon.vcxproj.user: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | -------------------------------------------------------------------------------- /DdiMon/ddi_mon.cpp: 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All rights reserved. 2 | // Use of this source code is governed by a MIT-style license that can be 3 | // found in the LICENSE file. 4 | 5 | /// @file 6 | /// @brief Declares interfaces to driver functions. 7 | 8 | #ifndef HYPERPLATFORM_DRIVER_H_ 9 | #define HYPERPLATFORM_DRIVER_H_ 10 | 11 | extern "C" { 12 | //////////////////////////////////////////////////////////////////////////////// 13 | // 14 | // macro utilities 15 | // 16 | 17 | //////////////////////////////////////////////////////////////////////////////// 18 | // 19 | // constants and macros 20 | // 21 | 22 | //////////////////////////////////////////////////////////////////////////////// 23 | // 24 | // types 25 | // 26 | 27 | //////////////////////////////////////////////////////////////////////////////// 28 | // 29 | // prototypes 30 | // 31 | 32 | //////////////////////////////////////////////////////////////////////////////// 33 | // 34 | // variables 35 | // 36 | 37 | //////////////////////////////////////////////////////////////////////////////// 38 | // 39 | // implementations 40 | // 41 | 42 | } // extern "C" 43 | 44 | #endif // HYPERPLATFORM_DRIVER_H_ 45 | -------------------------------------------------------------------------------- /HyperPlatform/HyperPlatform/power_callback.h: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2015-2016, tandasat. All rights reserved. 2 | // Use of this source code is governed by a MIT-style license that can be 3 | // found in the LICENSE file. 4 | 5 | /// @file 6 | /// @brief Declares interfaces to power functions. 7 | 8 | #ifndef HYPERPLATFORM_POWER_CALLBACK_H_ 9 | #define HYPERPLATFORM_POWER_CALLBACK_H_ 10 | 11 | #include 12 | 13 | extern "C" { 14 | //////////////////////////////////////////////////////////////////////////////// 15 | // 16 | // macro utilities 17 | // 18 | 19 | //////////////////////////////////////////////////////////////////////////////// 20 | // 21 | // constants and macros 22 | // 23 | 24 | //////////////////////////////////////////////////////////////////////////////// 25 | // 26 | // types 27 | // 28 | 29 | //////////////////////////////////////////////////////////////////////////////// 30 | // 31 | // prototypes 32 | // 33 | 34 | _IRQL_requires_max_(PASSIVE_LEVEL) NTSTATUS PowerCallbackInitialization(); 35 | 36 | _IRQL_requires_max_(PASSIVE_LEVEL) void PowerCallbackTermination(); 37 | 38 | //////////////////////////////////////////////////////////////////////////////// 39 | // 40 | // variables 41 | // 42 | 43 | //////////////////////////////////////////////////////////////////////////////// 44 | // 45 | // implementations 46 | // 47 | 48 | } // extern "C" 49 | 50 | #endif // HYPERPLATFORM_POWER_CALLBACK_H_ 51 | -------------------------------------------------------------------------------- /HyperPlatform/clean.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | del *.sdf 3 | del *.VC.db 4 | del /s *.aps 5 | del /a:h *.suo 6 | rmdir /s /q .vs 7 | rmdir /s /q ipch 8 | rmdir /s /q x64 9 | rmdir /s /q Debug 10 | rmdir /s /q Release 11 | rmdir /s /q HyperPlatform\x64 12 | rmdir /s /q HyperPlatform\Debug 13 | rmdir /s /q HyperPlatform\Release 14 | rmdir /s /q doxygen 15 | pause 16 | -------------------------------------------------------------------------------- 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DispatcherDeviceIoControl(IN PDEVICE_OBJECT pDeviceObject, IN PIRP pIrp); 18 | 19 | void InitGlobalVar(); 20 | 21 | EXTERN_C_END 22 | -------------------------------------------------------------------------------- /IntoProtect32/HookProtect.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/IntoProtect32/HookProtect.c -------------------------------------------------------------------------------- /IntoProtect32/HookProtect.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/IntoProtect32/HookProtect.h -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | The MIT License (MIT) 2 | 3 | Copyright (c) 2016 Satoshi Tanda 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /LMProtect/GetShadowSsdtSym.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | class GetShadowSsdtSym 3 | { 4 | public: 5 | GetShadowSsdtSym(); 6 | ~GetShadowSsdtSym(); 7 | bool Init(); 8 | bool Is64Bit_OS(); 9 | 10 | private: 11 | unsigned long long Win32kBase_ = 0; 12 | void* DriverBaseTab_[2048]; 13 | bool GetWin32kBaseSuccess_ = false; 14 | }; 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /LMProtect/GetSysInfo.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/LMProtect/GetSysInfo.cpp -------------------------------------------------------------------------------- /LMProtect/GetSysInfo.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/LMProtect/GetSysInfo.h -------------------------------------------------------------------------------- /LMProtect/IMGetData.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/LMProtect/IMGetData.h -------------------------------------------------------------------------------- /LMProtect/IMProtect.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/LMProtect/IMProtect.cpp -------------------------------------------------------------------------------- /LMProtect/IMProtect.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | class IMProtect 4 | { 5 | public: 6 | IMProtect(); 7 | ~IMProtect(); 8 | bool LoadDriver(); 9 | bool ProcessProtectionRemoval(); 10 | bool ProcessProtectionAdd(const wchar_t * ProcessFileName, unsigned long ProcessId); 11 | bool ProcessHideRemoval(); 12 | bool ProcessHideAdd(const wchar_t * ProcessFileName, unsigned long ProcessId); 13 | bool UnloadNTDriver(); //shupb 14 | 15 | private: 16 | bool LoadNTDriver(const wchar_t* lpDriverName, const wchar_t* lpDriverPathName); 17 | bool Close(); 18 | void* m_hMProtect; 19 | }; 20 | 21 | -------------------------------------------------------------------------------- /LMProtect/ReadMe.txt: -------------------------------------------------------------------------------- 1 | ======================================================================== 2 | 静态库：LMProtect 项目概述 3 | ======================================================================== 4 | 5 | 应用程序向导已为您创建了此 LMProtect 库项目。 6 | 7 | 本文件概要介绍组成 LMProtect 应用程序的每个文件的内容。 8 | 9 | 10 | LMProtect.vcxproj 11 | 这是使用应用程序向导生成的 VC++ 项目的主项目文件，其中包含生成该文件的 Visual C++ 的版本信息，以及有关使用应用程序向导选择的平台、配置和项目功能的信息。 12 | 13 | LMProtect.vcxproj.filters 14 | 这是使用“应用程序向导”生成的 VC++ 项目筛选器文件。它包含有关项目文件与筛选器之间的关联信息。在 IDE 中，通过这种关联，在特定节点下以分组形式显示具有相似扩展名的文件。例如，“.cpp”文件与“源文件”筛选器关联。 15 | 16 | 17 | ///////////////////////////////////////////////////////////////////////////// 18 | 19 | StdAfx.h, StdAfx.cpp 20 | 这些文件用于生成名为 LMProtect.pch 的预编译头 (PCH) 文件和名为 StdAfx.obj 的预编译类型文件。 21 | 22 | ///////////////////////////////////////////////////////////////////////////// 23 | 其他注释: 24 | 25 | 应用程序向导使用“TODO:”注释来指示应添加或自定义的源代码部分。 26 | 27 | ///////////////////////////////////////////////////////////////////////////// 28 | -------------------------------------------------------------------------------- /LMProtect/stdafx.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/LMProtect/stdafx.cpp -------------------------------------------------------------------------------- /LMProtect/stdafx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/LMProtect/stdafx.h -------------------------------------------------------------------------------- /LMProtect/targetver.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/LMProtect/targetver.h -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # MProtect -------------------------------------------------------------------------------- /capstone/.appveyor.yml: -------------------------------------------------------------------------------- 1 | version: 3.0.4-{build} 2 | 3 | os: 4 | - Visual Studio 2015 5 | 6 | before_build: 7 | - call "C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\vcvarsall.bat" amd64 8 | 9 | build_script: 10 | - mkdir build 11 | - cd build 12 | - cmake -DCMAKE_BUILD_TYPE=RELEASE -G "NMake Makefiles" .. 13 | - nmake 14 | 15 | -------------------------------------------------------------------------------- /capstone/.travis.yml: -------------------------------------------------------------------------------- 1 | language: cpp 2 | sudo: false 3 | before_install: 4 | - export LD_LIBRARY_PATH=`pwd`/tests/:$LD_LIBRARY_PATH 5 | script: 6 | - ./make.sh 7 | - make check 8 | - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then cp libcapstone.so bindings/python/; fi 9 | - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then cp libcapstone.dylib bindings/python/; fi 10 | - cd bindings/python && make check 11 | compiler: 12 | - clang 13 | - gcc 14 | os: 15 | - linux 16 | - osx 17 | -------------------------------------------------------------------------------- /capstone/LEB128.h: -------------------------------------------------------------------------------- 1 | //===- llvm/Support/LEB128.h - [SU]LEB128 utility functions -----*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file declares some utility functions for encoding SLEB128 and 11 | // ULEB128 values. 12 | // 13 | //===----------------------------------------------------------------------===// 14 | 15 | /* Capstone Disassembly Engine */ 16 | /* By Nguyen Anh Quynh , 2013-2014 */ 17 | 18 | #ifndef CS_LLVM_SUPPORT_LEB128_H 19 | #define CS_LLVM_SUPPORT_LEB128_H 20 | 21 | #if !defined(_MSC_VER) || !defined(_KERNEL_MODE) 22 | #include 23 | #endif 24 | 25 | /// Utility function to decode a ULEB128 value. 26 | static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n) 27 | { 28 | const uint8_t *orig_p = p; 29 | uint64_t Value = 0; 30 | unsigned Shift = 0; 31 | do { 32 | Value += (*p & 0x7f) << Shift; 33 | Shift += 7; 34 | } while (*p++ >= 128); 35 | if (n) 36 | *n = (unsigned)(p - orig_p); 37 | return Value; 38 | } 39 | 40 | #endif // LLVM_SYSTEM_LEB128_H 41 | -------------------------------------------------------------------------------- /capstone/MCDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_MCDISASSEMBLER_H 5 | #define CS_MCDISASSEMBLER_H 6 | 7 | typedef enum DecodeStatus { 8 | MCDisassembler_Fail = 0, 9 | MCDisassembler_SoftFail = 1, 10 | MCDisassembler_Success = 3, 11 | } DecodeStatus; 12 | 13 | #endif 14 | 15 | -------------------------------------------------------------------------------- /capstone/MCFixedLenDisassembler.h: -------------------------------------------------------------------------------- 1 | //===-- llvm/MC/MCFixedLenDisassembler.h - Decoder driver -------*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // Fixed length disassembler decoder state machine driver. 10 | //===----------------------------------------------------------------------===// 11 | 12 | /* Capstone Disassembly Engine */ 13 | /* By Nguyen Anh Quynh , 2013-2014 */ 14 | 15 | #ifndef CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H 16 | #define CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H 17 | 18 | // Disassembler state machine opcodes. 19 | enum DecoderOps { 20 | MCD_OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len) 21 | MCD_OPC_FilterValue, // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip) 22 | MCD_OPC_CheckField, // OPC_CheckField(uint8_t Start, uint8_t Len, 23 | // uleb128 Val, uint16_t NumToSkip) 24 | MCD_OPC_CheckPredicate, // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip) 25 | MCD_OPC_Decode, // OPC_Decode(uleb128 Opcode, uleb128 DIdx) 26 | MCD_OPC_SoftFail, // OPC_SoftFail(uleb128 PMask, uleb128 NMask) 27 | MCD_OPC_Fail // OPC_Fail() 28 | }; 29 | 30 | #endif 31 | -------------------------------------------------------------------------------- /capstone/MCInstrDesc.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #include "MCInstrDesc.h" 5 | 6 | /// isPredicate - Set if this is one of the operands that made up of 7 | /// the predicate operand that controls an isPredicable() instruction. 8 | bool MCOperandInfo_isPredicate(MCOperandInfo *m) 9 | { 10 | return m->Flags & (1 << MCOI_Predicate); 11 | } 12 | 13 | /// isOptionalDef - Set if this operand is a optional def. 14 | /// 15 | bool MCOperandInfo_isOptionalDef(MCOperandInfo *m) 16 | { 17 | return m->Flags & (1 << MCOI_OptionalDef); 18 | } 19 | -------------------------------------------------------------------------------- /capstone/RELEASE_NOTES: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/capstone/RELEASE_NOTES -------------------------------------------------------------------------------- /capstone/SStream.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_SSTREAM_H_ 5 | #define CS_SSTREAM_H_ 6 | 7 | typedef struct SStream { 8 | char buffer[512]; 9 | int index; 10 | } SStream; 11 | 12 | void SStream_Init(SStream *ss); 13 | 14 | void SStream_concat(SStream *ss, const char *fmt, ...); 15 | 16 | void SStream_concat0(SStream *ss, char *s); 17 | 18 | void printInt64Bang(SStream *O, int64_t val); 19 | 20 | void printUInt64Bang(SStream *O, uint64_t val); 21 | 22 | void printInt64(SStream *O, int64_t val); 23 | 24 | void printInt32Bang(SStream *O, int32_t val); 25 | 26 | void printInt32(SStream *O, int32_t val); 27 | 28 | void printUInt32Bang(SStream *O, uint32_t val); 29 | 30 | void printUInt32(SStream *O, uint32_t val); 31 | 32 | // print number in decimal mode 33 | void printInt32BangDec(SStream *O, int32_t val); 34 | 35 | #endif 36 | -------------------------------------------------------------------------------- /capstone/TODO: -------------------------------------------------------------------------------- 1 | Issues to be solved in next versions 2 | 3 | 4 | [Core] 5 | 6 | - X86 can already handle all the malware tricks we are aware of. If you find 7 | any such instruction sequence that Capstone disassembles wrongly or fails 8 | completely, please report. Fixing this issue is always the top priority of 9 | our project. 10 | 11 | - More optimization for better performance. 12 | 13 | 14 | [Bindings] 15 | 16 | - OCaml binding is working, but still needs to support the core API better. 17 | -------------------------------------------------------------------------------- /capstone/arch/AArch64/AArch64Disassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_AARCH64_DISASSEMBLER_H 5 | #define CS_AARCH64_DISASSEMBLER_H 6 | 7 | #if !defined(_MSC_VER) || !defined(_KERNEL_MODE) 8 | #include 9 | #endif 10 | 11 | #include "../../include/capstone.h" 12 | #include "../../MCRegisterInfo.h" 13 | #include "../../MCInst.h" 14 | 15 | void AArch64_init(MCRegisterInfo *MRI); 16 | 17 | bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len, 18 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /capstone/arch/AArch64/AArch64GenSubtargetInfo.inc: -------------------------------------------------------------------------------- 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2 | |* *| 3 | |*Subtarget Enumeration Source Fragment *| 4 | |* *| 5 | |* Automatically generated file, do not edit! *| 6 | |* *| 7 | \*===----------------------------------------------------------------------===*/ 8 | 9 | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ 10 | /* By Nguyen Anh Quynh , 2013-2014 */ 11 | 12 | 13 | #ifdef GET_SUBTARGETINFO_ENUM 14 | #undef GET_SUBTARGETINFO_ENUM 15 | 16 | enum { 17 | AArch64_FeatureCRC = 1ULL << 0, 18 | AArch64_FeatureCrypto = 1ULL << 1, 19 | AArch64_FeatureFPARMv8 = 1ULL << 2, 20 | AArch64_FeatureNEON = 1ULL << 3, 21 | AArch64_FeatureZCRegMove = 1ULL << 4, 22 | AArch64_FeatureZCZeroing = 1ULL << 5, 23 | AArch64_ProcA53 = 1ULL << 6, 24 | AArch64_ProcA57 = 1ULL << 7, 25 | AArch64_ProcCyclone = 1ULL << 8 26 | }; 27 | 28 | #endif // GET_SUBTARGETINFO_ENUM 29 | 30 | -------------------------------------------------------------------------------- /capstone/arch/AArch64/AArch64InstPrinter.h: -------------------------------------------------------------------------------- 1 | //===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This class prints an AArch64 MCInst to a .s file. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | /* Capstone Disassembly Engine */ 15 | /* By Nguyen Anh Quynh , 2013-2014 */ 16 | 17 | #ifndef CS_LLVM_AARCH64INSTPRINTER_H 18 | #define CS_LLVM_AARCH64INSTPRINTER_H 19 | 20 | #include "../../MCInst.h" 21 | #include "../../MCRegisterInfo.h" 22 | #include "../../SStream.h" 23 | 24 | void AArch64_printInst(MCInst *MI, SStream *O, void *); 25 | 26 | void AArch64_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm, MCInst *mci); 27 | 28 | #endif 29 | -------------------------------------------------------------------------------- /capstone/arch/AArch64/AArch64Mapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_ARM64_MAP_H 5 | #define CS_ARM64_MAP_H 6 | 7 | #include "../../include/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *AArch64_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *AArch64_insn_name(csh handle, unsigned int id); 16 | 17 | const char *AArch64_group_name(csh handle, unsigned int id); 18 | 19 | // map instruction name to public instruction ID 20 | arm64_reg AArch64_map_insn(const char *name); 21 | 22 | // map internal vregister to public register 23 | arm64_reg AArch64_map_vregister(unsigned int r); 24 | 25 | void arm64_op_addReg(MCInst *MI, int reg); 26 | 27 | void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp); 28 | 29 | void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp); 30 | 31 | void arm64_op_addFP(MCInst *MI, float fp); 32 | 33 | void arm64_op_addImm(MCInst *MI, int64_t imm); 34 | 35 | #endif 36 | -------------------------------------------------------------------------------- /capstone/arch/AArch64/AArch64Module.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Dang Hoang Vu 2013 */ 3 | 4 | #ifdef CAPSTONE_HAS_ARM64 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "AArch64Disassembler.h" 9 | #include "AArch64InstPrinter.h" 10 | #include "AArch64Mapping.h" 11 | 12 | static cs_err init(cs_struct *ud) 13 | { 14 | MCRegisterInfo *mri; 15 | 16 | // verify if requested mode is valid 17 | if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_BIG_ENDIAN)) 18 | return CS_ERR_MODE; 19 | 20 | mri = cs_mem_malloc(sizeof(*mri)); 21 | 22 | AArch64_init(mri); 23 | ud->printer = AArch64_printInst; 24 | ud->printer_info = mri; 25 | ud->getinsn_info = mri; 26 | ud->disasm = AArch64_getInstruction; 27 | ud->reg_name = AArch64_reg_name; 28 | ud->insn_id = AArch64_get_insn_id; 29 | ud->insn_name = AArch64_insn_name; 30 | ud->group_name = AArch64_group_name; 31 | ud->post_printer = AArch64_post_printer; 32 | 33 | return CS_ERR_OK; 34 | } 35 | 36 | static cs_err option(cs_struct *handle, cs_opt_type type, size_t value) 37 | { 38 | return CS_ERR_OK; 39 | } 40 | 41 | static void destroy(cs_struct *handle) 42 | { 43 | } 44 | 45 | void AArch64_enable(void) 46 | { 47 | arch_init[CS_ARCH_ARM64] = init; 48 | arch_option[CS_ARCH_ARM64] = option; 49 | arch_destroy[CS_ARCH_ARM64] = destroy; 50 | 51 | // support this arch 52 | all_arch |= (1 << CS_ARCH_ARM64); 53 | } 54 | 55 | #endif 56 | -------------------------------------------------------------------------------- /capstone/arch/ARM/ARMDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_ARMDISASSEMBLER_H 5 | #define CS_ARMDISASSEMBLER_H 6 | 7 | #include "../../include/capstone.h" 8 | #include "../../MCRegisterInfo.h" 9 | 10 | void ARM_init(MCRegisterInfo *MRI); 11 | 12 | bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); 13 | 14 | bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); 15 | 16 | uint64_t ARM_getFeatureBits(unsigned int mode); 17 | 18 | #endif 19 | -------------------------------------------------------------------------------- /capstone/arch/ARM/ARMMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_ARM_MAP_H 5 | #define CS_ARM_MAP_H 6 | 7 | #include "../../include/capstone.h" 8 | #include "../../utils.h" 9 | 10 | // return name of regiser in friendly string 11 | const char *ARM_reg_name(csh handle, unsigned int reg); 12 | const char *ARM_reg_name2(csh handle, unsigned int reg); 13 | 14 | // given internal insn id, return public instruction ID 15 | void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 16 | 17 | const char *ARM_insn_name(csh handle, unsigned int id); 18 | 19 | const char *ARM_group_name(csh handle, unsigned int id); 20 | 21 | // check if this insn is relative branch 22 | bool ARM_rel_branch(cs_struct *h, unsigned int insn_id); 23 | 24 | bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id); 25 | 26 | #endif 27 | -------------------------------------------------------------------------------- /capstone/arch/Mips/MipsDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_MIPSDISASSEMBLER_H 5 | #define CS_MIPSDISASSEMBLER_H 6 | 7 | #include "../../include/capstone.h" 8 | 9 | #include "../../include/capstone.h" 10 | #include "../../MCRegisterInfo.h" 11 | 12 | void Mips_init(MCRegisterInfo *MRI); 13 | 14 | bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len, 15 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 16 | 17 | bool Mips64_getInstruction(csh handle, const uint8_t *code, size_t code_len, 18 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /capstone/arch/Mips/MipsInstPrinter.h: -------------------------------------------------------------------------------- 1 | //=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This class prints a Mips MCInst to a .s file. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | /* Capstone Disassembly Engine */ 15 | /* By Nguyen Anh Quynh , 2013-2014 */ 16 | 17 | #ifndef CS_MIPSINSTPRINTER_H 18 | #define CS_MIPSINSTPRINTER_H 19 | 20 | #include "../../MCInst.h" 21 | #include "../../SStream.h" 22 | 23 | void Mips_printInst(MCInst *MI, SStream *O, void *info); 24 | 25 | #endif 26 | -------------------------------------------------------------------------------- /capstone/arch/Mips/MipsMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_MIPS_MAP_H 5 | #define CS_MIPS_MAP_H 6 | 7 | #include "../../include/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *Mips_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *Mips_insn_name(csh handle, unsigned int id); 16 | 17 | const char *Mips_group_name(csh handle, unsigned int id); 18 | 19 | // map instruction name to instruction ID 20 | mips_reg Mips_map_insn(const char *name); 21 | 22 | // map internal raw register to 'public' register 23 | mips_reg Mips_map_register(unsigned int r); 24 | 25 | #endif 26 | -------------------------------------------------------------------------------- /capstone/arch/PowerPC/PPCDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_PPCDISASSEMBLER_H 5 | #define CS_PPCDISASSEMBLER_H 6 | 7 | #if !defined(_MSC_VER) || !defined(_KERNEL_MODE) 8 | #include 9 | #endif 10 | 11 | #include "../../include/capstone.h" 12 | #include "../../MCRegisterInfo.h" 13 | #include "../../MCInst.h" 14 | 15 | void PPC_init(MCRegisterInfo *MRI); 16 | 17 | bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len, 18 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 19 | 20 | #endif 21 | 22 | -------------------------------------------------------------------------------- /capstone/arch/PowerPC/PPCInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_PPCINSTPRINTER_H 5 | #define CS_PPCINSTPRINTER_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../SStream.h" 10 | 11 | void PPC_printInst(MCInst *MI, SStream *O, void *Info); 12 | 13 | void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /capstone/arch/PowerPC/PPCMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_PPC_MAP_H 5 | #define CS_PPC_MAP_H 6 | 7 | #include "../../include/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *PPC_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *PPC_insn_name(csh handle, unsigned int id); 16 | const char *PPC_group_name(csh handle, unsigned int id); 17 | 18 | // map internal raw register to 'public' register 19 | ppc_reg PPC_map_register(unsigned int r); 20 | 21 | struct ppc_alias { 22 | unsigned int id; // instruction id 23 | int cc; // code condition 24 | const char *mnem; 25 | }; 26 | 27 | // given alias mnemonic, return instruction ID & CC 28 | bool PPC_alias_insn(const char *name, struct ppc_alias *alias); 29 | 30 | // check if this insn is relative branch 31 | bool PPC_abs_branch(cs_struct *h, unsigned int id); 32 | 33 | #endif 34 | 35 | -------------------------------------------------------------------------------- /capstone/arch/Sparc/SparcDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_SPARCDISASSEMBLER_H 5 | #define CS_SPARCDISASSEMBLER_H 6 | 7 | #if !defined(_MSC_VER) || !defined(_KERNEL_MODE) 8 | #include 9 | #endif 10 | 11 | #include "../../include/capstone.h" 12 | #include "../../MCRegisterInfo.h" 13 | #include "../../MCInst.h" 14 | 15 | void Sparc_init(MCRegisterInfo *MRI); 16 | 17 | bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, 18 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 19 | 20 | #endif 21 | 22 | -------------------------------------------------------------------------------- /capstone/arch/Sparc/SparcGenSubtargetInfo.inc: -------------------------------------------------------------------------------- 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2 | |* *| 3 | |*Subtarget Enumeration Source Fragment *| 4 | |* *| 5 | |* Automatically generated file, do not edit! *| 6 | |* *| 7 | \*===----------------------------------------------------------------------===*/ 8 | 9 | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ 10 | /* By Nguyen Anh Quynh , 2013-2014 */ 11 | 12 | 13 | #ifdef GET_SUBTARGETINFO_ENUM 14 | #undef GET_SUBTARGETINFO_ENUM 15 | 16 | enum { 17 | Sparc_FeatureHardQuad = 1ULL << 0, 18 | Sparc_FeatureV8Deprecated = 1ULL << 1, 19 | Sparc_FeatureV9 = 1ULL << 2, 20 | Sparc_FeatureVIS = 1ULL << 3, 21 | Sparc_FeatureVIS2 = 1ULL << 4, 22 | Sparc_FeatureVIS3 = 1ULL << 5, 23 | Sparc_UsePopc = 1ULL << 6 24 | }; 25 | 26 | #endif // GET_SUBTARGETINFO_ENUM 27 | 28 | -------------------------------------------------------------------------------- /capstone/arch/Sparc/SparcInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_SPARCINSTPRINTER_H 5 | #define CS_SPARCINSTPRINTER_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../SStream.h" 10 | 11 | void Sparc_printInst(MCInst *MI, SStream *O, void *Info); 12 | 13 | void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); 14 | 15 | void Sparc_addReg(MCInst *MI, int reg); 16 | 17 | #endif 18 | -------------------------------------------------------------------------------- /capstone/arch/Sparc/SparcMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_SPARC_MAP_H 5 | #define CS_SPARC_MAP_H 6 | 7 | #include "../../include/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *Sparc_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *Sparc_insn_name(csh handle, unsigned int id); 16 | 17 | const char *Sparc_group_name(csh handle, unsigned int id); 18 | 19 | // map internal raw register to 'public' register 20 | sparc_reg Sparc_map_register(unsigned int r); 21 | 22 | // map instruction name to instruction ID (public) 23 | // this is for alias instructions only 24 | sparc_reg Sparc_map_insn(const char *name); 25 | 26 | // map CC string to CC id 27 | sparc_cc Sparc_map_ICC(const char *name); 28 | 29 | sparc_cc Sparc_map_FCC(const char *name); 30 | 31 | sparc_hint Sparc_map_hint(const char *name); 32 | 33 | #endif 34 | 35 | -------------------------------------------------------------------------------- /capstone/arch/SystemZ/SystemZDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_SYSZDISASSEMBLER_H 5 | #define CS_SYSZDISASSEMBLER_H 6 | 7 | #if !defined(_MSC_VER) || !defined(_KERNEL_MODE) 8 | #include 9 | #endif 10 | 11 | #include "../../include/capstone.h" 12 | #include "../../MCRegisterInfo.h" 13 | #include "../../MCInst.h" 14 | 15 | void SystemZ_init(MCRegisterInfo *MRI); 16 | 17 | bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, 18 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 19 | 20 | #endif 21 | 22 | -------------------------------------------------------------------------------- /capstone/arch/SystemZ/SystemZGenSubtargetInfo.inc: -------------------------------------------------------------------------------- 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2 | |* *| 3 | |*Subtarget Enumeration Source Fragment *| 4 | |* *| 5 | |* Automatically generated file, do not edit! *| 6 | |* *| 7 | \*===----------------------------------------------------------------------===*/ 8 | 9 | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ 10 | /* By Nguyen Anh Quynh , 2013-2014 */ 11 | 12 | 13 | #ifdef GET_SUBTARGETINFO_ENUM 14 | #undef GET_SUBTARGETINFO_ENUM 15 | 16 | enum { 17 | SystemZ_FeatureDistinctOps = 1ULL << 0, 18 | SystemZ_FeatureFPExtension = 1ULL << 1, 19 | SystemZ_FeatureFastSerialization = 1ULL << 2, 20 | SystemZ_FeatureHighWord = 1ULL << 3, 21 | SystemZ_FeatureInterlockedAccess1 = 1ULL << 4, 22 | SystemZ_FeatureLoadStoreOnCond = 1ULL << 5 23 | }; 24 | 25 | #endif // GET_SUBTARGETINFO_ENUM 26 | 27 | -------------------------------------------------------------------------------- /capstone/arch/SystemZ/SystemZInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_SYSZINSTPRINTER_H 5 | #define CS_SYSZINSTPRINTER_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../SStream.h" 10 | 11 | void SystemZ_printInst(MCInst *MI, SStream *O, void *Info); 12 | 13 | void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /capstone/arch/SystemZ/SystemZMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_SYSZ_MAP_H 5 | #define CS_SYSZ_MAP_H 6 | 7 | #include "../../include/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *SystemZ_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *SystemZ_insn_name(csh handle, unsigned int id); 16 | 17 | const char *SystemZ_group_name(csh handle, unsigned int id); 18 | 19 | // map internal raw register to 'public' register 20 | sysz_reg SystemZ_map_register(unsigned int r); 21 | 22 | #endif 23 | 24 | -------------------------------------------------------------------------------- /capstone/arch/SystemZ/SystemZModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifdef CAPSTONE_HAS_SYSZ 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "SystemZDisassembler.h" 9 | #include "SystemZInstPrinter.h" 10 | #include "SystemZMapping.h" 11 | 12 | static cs_err init(cs_struct *ud) 13 | { 14 | MCRegisterInfo *mri; 15 | 16 | mri = cs_mem_malloc(sizeof(*mri)); 17 | 18 | SystemZ_init(mri); 19 | ud->printer = SystemZ_printInst; 20 | ud->printer_info = mri; 21 | ud->getinsn_info = mri; 22 | ud->disasm = SystemZ_getInstruction; 23 | ud->post_printer = SystemZ_post_printer; 24 | 25 | ud->reg_name = SystemZ_reg_name; 26 | ud->insn_id = SystemZ_get_insn_id; 27 | ud->insn_name = SystemZ_insn_name; 28 | ud->group_name = SystemZ_group_name; 29 | 30 | return CS_ERR_OK; 31 | } 32 | 33 | static cs_err option(cs_struct *handle, cs_opt_type type, size_t value) 34 | { 35 | if (type == CS_OPT_SYNTAX) 36 | handle->syntax = (int) value; 37 | 38 | return CS_ERR_OK; 39 | } 40 | 41 | static void destroy(cs_struct *handle) 42 | { 43 | } 44 | 45 | void SystemZ_enable(void) 46 | { 47 | arch_init[CS_ARCH_SYSZ] = init; 48 | arch_option[CS_ARCH_SYSZ] = option; 49 | arch_destroy[CS_ARCH_SYSZ] = destroy; 50 | 51 | // support this arch 52 | all_arch |= (1 << CS_ARCH_SYSZ); 53 | } 54 | 55 | #endif 56 | -------------------------------------------------------------------------------- /capstone/arch/X86/X86InstPrinter.h: -------------------------------------------------------------------------------- 1 | //= X86IntelInstPrinter.h - Convert X86 MCInst to assembly syntax -*- C++ -*-=// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This class prints an X86 MCInst to Intel style .s file syntax. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | /* Capstone Disassembly Engine */ 15 | /* By Nguyen Anh Quynh , 2013-2014 */ 16 | 17 | #ifndef CS_X86_INSTPRINTER_H 18 | #define CS_X86_INSTPRINTER_H 19 | 20 | #include "../../MCInst.h" 21 | #include "../../SStream.h" 22 | 23 | void X86_Intel_printInst(MCInst *MI, SStream *OS, void *Info); 24 | void X86_ATT_printInst(MCInst *MI, SStream *OS, void *Info); 25 | 26 | #endif 27 | -------------------------------------------------------------------------------- /capstone/arch/XCore/XCoreDisassembler.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_XCOREDISASSEMBLER_H 5 | #define CS_XCOREDISASSEMBLER_H 6 | 7 | #if !defined(_MSC_VER) || !defined(_KERNEL_MODE) 8 | #include 9 | #endif 10 | 11 | #include "../../include/capstone.h" 12 | #include "../../MCRegisterInfo.h" 13 | #include "../../MCInst.h" 14 | 15 | void XCore_init(MCRegisterInfo *MRI); 16 | 17 | bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, 18 | MCInst *instr, uint16_t *size, uint64_t address, void *info); 19 | 20 | #endif 21 | 22 | -------------------------------------------------------------------------------- /capstone/arch/XCore/XCoreInstPrinter.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_XCOREINSTPRINTER_H 5 | #define CS_XCOREINSTPRINTER_H 6 | 7 | #include "../../MCInst.h" 8 | #include "../../MCRegisterInfo.h" 9 | #include "../../SStream.h" 10 | 11 | void XCore_printInst(MCInst *MI, SStream *O, void *Info); 12 | 13 | void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); 14 | 15 | // extract details from assembly code @code 16 | void XCore_insn_extract(MCInst *MI, const char *code); 17 | 18 | #endif 19 | -------------------------------------------------------------------------------- /capstone/arch/XCore/XCoreMapping.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifndef CS_XCORE_MAP_H 5 | #define CS_XCORE_MAP_H 6 | 7 | #include "../../include/capstone.h" 8 | 9 | // return name of regiser in friendly string 10 | const char *XCore_reg_name(csh handle, unsigned int reg); 11 | 12 | // given internal insn id, return public instruction info 13 | void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); 14 | 15 | const char *XCore_insn_name(csh handle, unsigned int id); 16 | 17 | const char *XCore_group_name(csh handle, unsigned int id); 18 | 19 | // map internal raw register to 'public' register 20 | xcore_reg XCore_map_register(unsigned int r); 21 | 22 | // map register name to register ID 23 | xcore_reg XCore_reg_id(char *name); 24 | 25 | #endif 26 | 27 | -------------------------------------------------------------------------------- /capstone/arch/XCore/XCoreModule.c: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Nguyen Anh Quynh , 2013-2014 */ 3 | 4 | #ifdef CAPSTONE_HAS_XCORE 5 | 6 | #include "../../utils.h" 7 | #include "../../MCRegisterInfo.h" 8 | #include "XCoreDisassembler.h" 9 | #include "XCoreInstPrinter.h" 10 | #include "XCoreMapping.h" 11 | 12 | static cs_err init(cs_struct *ud) 13 | { 14 | MCRegisterInfo *mri; 15 | 16 | mri = cs_mem_malloc(sizeof(*mri)); 17 | 18 | XCore_init(mri); 19 | ud->printer = XCore_printInst; 20 | ud->printer_info = mri; 21 | ud->getinsn_info = mri; 22 | ud->disasm = XCore_getInstruction; 23 | ud->post_printer = XCore_post_printer; 24 | 25 | ud->reg_name = XCore_reg_name; 26 | ud->insn_id = XCore_get_insn_id; 27 | ud->insn_name = XCore_insn_name; 28 | ud->group_name = XCore_group_name; 29 | 30 | return CS_ERR_OK; 31 | } 32 | 33 | static cs_err option(cs_struct *handle, cs_opt_type type, size_t value) 34 | { 35 | return CS_ERR_OK; 36 | } 37 | 38 | static void destroy(cs_struct *handle) 39 | { 40 | } 41 | 42 | void XCore_enable(void) 43 | { 44 | arch_init[CS_ARCH_XCORE] = init; 45 | arch_option[CS_ARCH_XCORE] = option; 46 | arch_destroy[CS_ARCH_XCORE] = destroy; 47 | 48 | // support this arch 49 | all_arch |= (1 << CS_ARCH_XCORE); 50 | } 51 | 52 | #endif 53 | -------------------------------------------------------------------------------- /capstone/bindings/java/.gitignore: -------------------------------------------------------------------------------- 1 | *.class 2 | tags 3 | -------------------------------------------------------------------------------- /capstone/bindings/java/README: -------------------------------------------------------------------------------- 1 | This has been tested with OpenJDK version 6 & 7 on Ubuntu-12.04 and 2 | Arch Linux-3.11, 64-bit. 3 | 4 | - OpenJDK is required to compile and run this test code. 5 | For example, install OpenJDK 6 with: 6 | 7 | $ sudo apt-get install openjdk-6-jre-headless openjdk-6-jdk 8 | 9 | - Java Native Access is required to run the code, you can install it with: 10 | 11 | $ sudo apt-get install libjna-java 12 | 13 | - To compile and run this Java test code: 14 | 15 | $ make 16 | $ ./run.sh 17 | 18 | 19 | This directory contains some test code to show how to use Capstone API. 20 | 21 | - Test.java 22 | This code shows the most simple form of API where we only want to get basic 23 | information out of disassembled instruction, such as address, mnemonic and 24 | operand string. 25 | 26 | - Test_.java 27 | These code show how to retrieve architecture-specific information for each 28 | architecture. 29 | -------------------------------------------------------------------------------- /capstone/bindings/java/capstone/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/capstone/bindings/java/capstone/.gitignore -------------------------------------------------------------------------------- /capstone/bindings/java/run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | JNA=/usr/share/java/jna.jar 3 | 4 | if [ ! -f ${JNA} ]; then 5 | if [ ! -f /usr/share/java/jna/jna.jar ]; then 6 | echo "*** Unable to find jna.jar *** "; 7 | exit; 8 | else 9 | JNA=/usr/share/java/jna/jna.jar; 10 | fi 11 | fi 12 | 13 | case "$1" in 14 | "") java -classpath ${JNA}:. Test ;; 15 | "test") java -classpath ${JNA}:. Test ;; 16 | "arm") java -classpath ${JNA}:. TestArm ;; 17 | "arm64") java -classpath ${JNA}:. TestArm64 ;; 18 | "mips") java -classpath ${JNA}:. TestMips ;; 19 | "x86") java -classpath ${JNA}:. TestX86 ;; 20 | "xcore") java -classpath ${JNA}:. TestXcore; ;; 21 | "ppc") java -classpath ${JNA}:. TestPpc ;; 22 | "sparc") java -classpath ${JNA}:. TestSparc ;; 23 | "systemz") java -classpath ${JNA}:. TestSystemz ;; 24 | * ) echo "Usage: ./run.sh [arm|arm64|mips|ppc|sparc|systemz|x86]"; exit 1;; 25 | esac 26 | -------------------------------------------------------------------------------- /capstone/bindings/ocaml/README: -------------------------------------------------------------------------------- 1 | To compile Ocaml binding, Ocaml toolchain is needed. On Ubuntu Linux, 2 | you can install Ocaml with: 3 | 4 | $ sudo apt-get install ocaml-nox 5 | 6 | To compile Ocaml binding, simply run "make" on the command line. 7 | 8 | 9 | This directory also contains some test code to show how to use Capstone API. 10 | 11 | - test.ml 12 | This code shows the most simple form of API where we only want to get basic 13 | information out of disassembled instruction, such as address, mnemonic and 14 | operand string. 15 | 16 | - test_detail.ml: 17 | This code shows how to access to architecture-neutral information in disassembled 18 | instructions, such as implicit registers read/written, or groups of instructions 19 | that this instruction belong to. 20 | 21 | - test_.ml 22 | These code show how to access architecture-specific information for each 23 | architecture. 24 | -------------------------------------------------------------------------------- /capstone/bindings/ocaml/arm.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Nguyen Anh Quynh , 2013-2014 *) 3 | 4 | open Arm_const 5 | 6 | let _CS_OP_ARCH = 5;; 7 | let _CS_OP_CIMM = _CS_OP_ARCH (* C-Immediate *) 8 | let _CS_OP_PIMM = _CS_OP_ARCH + 1 (* P-Immediate *) 9 | 10 | 11 | (* architecture specific info of instruction *) 12 | type arm_op_shift = { 13 | shift_type: int; (* TODO: covert this to pattern like arm_op_value? *) 14 | shift_value: int; 15 | } 16 | 17 | type arm_op_mem = { 18 | base: int; 19 | index: int; 20 | scale: int; 21 | disp: int 22 | } 23 | 24 | type arm_op_value = 25 | | ARM_OP_INVALID of int 26 | | ARM_OP_REG of int 27 | | ARM_OP_CIMM of int 28 | | ARM_OP_PIMM of int 29 | | ARM_OP_IMM of int 30 | | ARM_OP_FP of float 31 | | ARM_OP_MEM of arm_op_mem 32 | | ARM_OP_SETEND of int 33 | 34 | type arm_op = { 35 | vector_index: int; 36 | shift: arm_op_shift; 37 | value: arm_op_value; 38 | subtracted: bool; 39 | } 40 | 41 | type cs_arm = { 42 | usermode: bool; 43 | vector_size: int; 44 | vector_data: int; 45 | cps_mode: int; 46 | cps_flag: int; 47 | cc: int; 48 | update_flags: bool; 49 | writeback: bool; 50 | mem_barrier: int; 51 | operands: arm_op array; 52 | } 53 | -------------------------------------------------------------------------------- /capstone/bindings/ocaml/arm64.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Nguyen Anh Quynh , 2013-2014 *) 3 | 4 | open Arm64_const 5 | 6 | (* architecture specific info of instruction *) 7 | type arm64_op_shift = { 8 | shift_type: int; 9 | shift_value: int; 10 | } 11 | 12 | type arm64_op_mem = { 13 | base: int; 14 | index: int; 15 | disp: int 16 | } 17 | 18 | type arm64_op_value = 19 | | ARM64_OP_INVALID of int 20 | | ARM64_OP_REG of int 21 | | ARM64_OP_CIMM of int 22 | | ARM64_OP_IMM of int 23 | | ARM64_OP_FP of float 24 | | ARM64_OP_MEM of arm64_op_mem 25 | | ARM64_OP_REG_MRS of int 26 | | ARM64_OP_REG_MSR of int 27 | | ARM64_OP_PSTATE of int 28 | | ARM64_OP_SYS of int 29 | | ARM64_OP_PREFETCH of int 30 | | ARM64_OP_BARRIER of int 31 | 32 | type arm64_op = { 33 | vector_index: int; 34 | vas: int; 35 | vess: int; 36 | shift: arm64_op_shift; 37 | ext: int; 38 | value: arm64_op_value; 39 | } 40 | 41 | type cs_arm64 = { 42 | cc: int; 43 | update_flags: bool; 44 | writeback: bool; 45 | operands: arm64_op array; 46 | } 47 | -------------------------------------------------------------------------------- /capstone/bindings/ocaml/mips.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Nguyen Anh Quynh , 2013-2014 *) 3 | 4 | open Mips_const 5 | 6 | (* architecture specific info of instruction *) 7 | type mips_op_mem = { 8 | base: int; 9 | disp: int 10 | } 11 | 12 | type mips_op_value = 13 | | MIPS_OP_INVALID of int 14 | | MIPS_OP_REG of int 15 | | MIPS_OP_IMM of int 16 | | MIPS_OP_MEM of mips_op_mem 17 | 18 | type mips_op = { 19 | value: mips_op_value; 20 | } 21 | 22 | type cs_mips = { 23 | operands: mips_op array; 24 | } 25 | -------------------------------------------------------------------------------- /capstone/bindings/ocaml/ppc.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Guillaume Jeanne , 2014> *) 3 | 4 | open Ppc_const 5 | 6 | type ppc_op_mem = { 7 | base: int; 8 | disp: int; 9 | } 10 | 11 | type ppc_op_crx = { 12 | scale: int; 13 | reg: int; 14 | cond: int; 15 | } 16 | 17 | type ppc_op_value = 18 | | PPC_OP_INVALID of int 19 | | PPC_OP_REG of int 20 | | PPC_OP_IMM of int 21 | | PPC_OP_MEM of ppc_op_mem 22 | | PPC_OP_CRX of ppc_op_crx 23 | 24 | type ppc_op = { 25 | value: ppc_op_value; 26 | } 27 | 28 | type cs_ppc = { 29 | bc: int; 30 | bh: int; 31 | update_cr0: bool; 32 | operands: ppc_op array; 33 | } 34 | 35 | -------------------------------------------------------------------------------- /capstone/bindings/ocaml/sparc.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Guillaume Jeanne , 2014> *) 3 | 4 | open Sparc_const 5 | 6 | type sparc_op_mem = { 7 | base: int; 8 | index: int; 9 | disp: int; 10 | } 11 | 12 | type sparc_op_value = 13 | | SPARC_OP_INVALID of int 14 | | SPARC_OP_REG of int 15 | | SPARC_OP_IMM of int 16 | | SPARC_OP_MEM of sparc_op_mem 17 | 18 | type sparc_op = { 19 | value: sparc_op_value; 20 | } 21 | 22 | type cs_sparc = { 23 | cc: int; 24 | hint: int; 25 | operands: sparc_op array; 26 | } 27 | 28 | -------------------------------------------------------------------------------- /capstone/bindings/ocaml/systemz.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Guillaume Jeanne , 2014> *) 3 | 4 | open Sysz_const 5 | 6 | type sysz_op_mem = { 7 | base: int; 8 | index: int; 9 | length: int64; 10 | disp: int64; 11 | } 12 | 13 | type sysz_op_value = 14 | | SYSZ_OP_INVALID of int 15 | | SYSZ_OP_REG of int 16 | | SYSZ_OP_ACREG of int 17 | | SYSZ_OP_IMM of int 18 | | SYSZ_OP_MEM of sysz_op_mem 19 | 20 | type sysz_op = { 21 | value: sysz_op_value; 22 | } 23 | 24 | type cs_sysz = { 25 | cc: int; 26 | operands: sysz_op array; 27 | } 28 | -------------------------------------------------------------------------------- /capstone/bindings/ocaml/x86.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Nguyen Anh Quynh , 2013-2014 *) 3 | 4 | open X86_const 5 | 6 | (* architecture specific info of instruction *) 7 | type x86_op_mem = { 8 | segment: int; 9 | base: int; 10 | index: int; 11 | scale: int; 12 | disp: int; 13 | } 14 | 15 | type x86_op_value = 16 | | X86_OP_INVALID of int 17 | | X86_OP_REG of int 18 | | X86_OP_IMM of int 19 | | X86_OP_FP of float 20 | | X86_OP_MEM of x86_op_mem 21 | 22 | type x86_op = { 23 | value: x86_op_value; 24 | size: int; 25 | avx_bcast: int; 26 | avx_zero_opmask: int; 27 | } 28 | 29 | type cs_x86 = { 30 | prefix: int array; 31 | opcode: int array; 32 | rex: int; 33 | addr_size: int; 34 | modrm: int; 35 | sib: int; 36 | disp: int; 37 | sib_index: int; 38 | sib_scale: int; 39 | sib_base: int; 40 | sse_cc: int; 41 | avx_cc: int; 42 | avx_sae: int; 43 | avx_rm: int; 44 | operands: x86_op array; 45 | } 46 | -------------------------------------------------------------------------------- /capstone/bindings/ocaml/xcore.ml: -------------------------------------------------------------------------------- 1 | (* Capstone Disassembly Engine 2 | * By Guillaume Jeanne , 2014> *) 3 | 4 | open Xcore_const 5 | 6 | type xcore_op_mem = { 7 | base: int; 8 | index: int; 9 | disp: int; 10 | direct: int; 11 | } 12 | 13 | type xcore_op_value = 14 | | XCORE_OP_INVALID of int 15 | | XCORE_OP_REG of int 16 | | XCORE_OP_IMM of int 17 | | XCORE_OP_MEM of xcore_op_mem 18 | 19 | type xcore_op = { 20 | value: xcore_op_value; 21 | } 22 | 23 | type cs_xcore = { 24 | operands: xcore_op array; 25 | } 26 | 27 | -------------------------------------------------------------------------------- /capstone/bindings/python/.gitignore: -------------------------------------------------------------------------------- 1 | MANIFEST 2 | dist/ 3 | src/ -------------------------------------------------------------------------------- /capstone/bindings/python/MANIFEST.in: -------------------------------------------------------------------------------- 1 | recursive-include capstone * 2 | recursive-include prebuilt * 3 | include LICENSE.TXT 4 | include README 5 | -------------------------------------------------------------------------------- /capstone/bindings/python/PKG-INFO.src: -------------------------------------------------------------------------------- 1 | Metadata-Version: 1.3 2 | Name: capstone 3 | Version: 3.0.4 4 | Author: Nguyen Anh Quynh 5 | Author-email: aquynh at gmail com 6 | Maintainer: Nguyen Anh Quynh 7 | Maintainer-email: aquynh at gmail com 8 | Home-page: http://www.capstone-engine.org 9 | Download-url: www.capstone-engine.org 10 | Summary: Capstone disassembly framework 11 | License: BSD 12 | Description: Capstone is a lightweight multi-platform, multi-architecture disassembly framework with some advanced features. Further information is available at the homepage http://www.capstone-engine.org 13 | Keywords: disassembly reverse binary arm arm64 aarch64 powerpc ppc mips x86 x86_64 sparc systemz xcore 14 | Platform: Windows MacOSX Linux NetBSD FreeBSD OpenBSD Solaris Android iOS 15 | -------------------------------------------------------------------------------- /capstone/bindings/python/PKG-INFO.win: -------------------------------------------------------------------------------- 1 | Metadata-Version: 1.3 2 | Name: capstone 3 | Version: 3.0.4 4 | Author: Nguyen Anh Quynh 5 | Author-email: aquynh at gmail com 6 | Maintainer: Nguyen Anh Quynh 7 | Maintainer-email: aquynh at gmail com 8 | Home-page: http://www.capstone-engine.org 9 | Download-url: www.capstone-engine.org 10 | Summary: Capstone disassembly framework with Windows prebuilt core ready inside. 11 | License: BSD 12 | Description: Capstone is a lightweight multi-platform, multi-architecture disassembly framework with some advanced features. Further information is available at the homepage http://www.capstone-engine.org 13 | Keywords: disassembly reverse binary arm arm64 aarch64 powerpc ppc mips x86 x86_64 sparc systemz xcore 14 | Platform: Windows MacOSX Linux NetBSD FreeBSD OpenBSD Solaris Android iOS 15 | -------------------------------------------------------------------------------- /capstone/bindings/python/capstone/mips.py: -------------------------------------------------------------------------------- 1 | # Capstone Python bindings, by Nguyen Anh Quynnh 2 | 3 | import ctypes 4 | from . import copy_ctypes_list 5 | from .mips_const import * 6 | 7 | # define the API 8 | class MipsOpMem(ctypes.Structure): 9 | _fields_ = ( 10 | ('base', ctypes.c_uint), 11 | ('disp', ctypes.c_int64), 12 | ) 13 | 14 | class MipsOpValue(ctypes.Union): 15 | _fields_ = ( 16 | ('reg', ctypes.c_uint), 17 | ('imm', ctypes.c_int64), 18 | ('mem', MipsOpMem), 19 | ) 20 | 21 | class MipsOp(ctypes.Structure): 22 | _fields_ = ( 23 | ('type', ctypes.c_uint), 24 | ('value', MipsOpValue), 25 | ) 26 | 27 | @property 28 | def imm(self): 29 | return self.value.imm 30 | 31 | @property 32 | def reg(self): 33 | return self.value.reg 34 | 35 | @property 36 | def mem(self): 37 | return self.value.mem 38 | 39 | 40 | class CsMips(ctypes.Structure): 41 | _fields_ = ( 42 | ('op_count', ctypes.c_uint8), 43 | ('operands', MipsOp * 8), 44 | ) 45 | 46 | def get_arch_info(a): 47 | return copy_ctypes_list(a.operands[:a.op_count]) 48 | 49 | -------------------------------------------------------------------------------- /capstone/bindings/python/capstone/sparc.py: -------------------------------------------------------------------------------- 1 | # Capstone Python bindings, by Nguyen Anh Quynnh 2 | 3 | import ctypes 4 | from . import copy_ctypes_list 5 | from .sparc_const import * 6 | 7 | # define the API 8 | class SparcOpMem(ctypes.Structure): 9 | _fields_ = ( 10 | ('base', ctypes.c_uint8), 11 | ('index', ctypes.c_uint8), 12 | ('disp', ctypes.c_int32), 13 | ) 14 | 15 | class SparcOpValue(ctypes.Union): 16 | _fields_ = ( 17 | ('reg', ctypes.c_uint), 18 | ('imm', ctypes.c_int32), 19 | ('mem', SparcOpMem), 20 | ) 21 | 22 | class SparcOp(ctypes.Structure): 23 | _fields_ = ( 24 | ('type', ctypes.c_uint), 25 | ('value', SparcOpValue), 26 | ) 27 | 28 | @property 29 | def imm(self): 30 | return self.value.imm 31 | 32 | @property 33 | def reg(self): 34 | return self.value.reg 35 | 36 | @property 37 | def mem(self): 38 | return self.value.mem 39 | 40 | 41 | class CsSparc(ctypes.Structure): 42 | _fields_ = ( 43 | ('cc', ctypes.c_uint), 44 | ('hint', ctypes.c_uint), 45 | ('op_count', ctypes.c_uint8), 46 | ('operands', SparcOp * 4), 47 | ) 48 | 49 | def get_arch_info(a): 50 | return (a.cc, a.hint, copy_ctypes_list(a.operands[:a.op_count])) 51 | 52 | -------------------------------------------------------------------------------- /capstone/bindings/python/capstone/systemz.py: -------------------------------------------------------------------------------- 1 | # Capstone Python bindings, by Nguyen Anh Quynnh 2 | 3 | import ctypes 4 | from . import copy_ctypes_list 5 | from .sysz_const import * 6 | 7 | # define the API 8 | class SyszOpMem(ctypes.Structure): 9 | _fields_ = ( 10 | ('base', ctypes.c_uint8), 11 | ('index', ctypes.c_uint8), 12 | ('length', ctypes.c_uint64), 13 | ('disp', ctypes.c_int64), 14 | ) 15 | 16 | class SyszOpValue(ctypes.Union): 17 | _fields_ = ( 18 | ('reg', ctypes.c_uint), 19 | ('imm', ctypes.c_int64), 20 | ('mem', SyszOpMem), 21 | ) 22 | 23 | class SyszOp(ctypes.Structure): 24 | _fields_ = ( 25 | ('type', ctypes.c_uint), 26 | ('value', SyszOpValue), 27 | ) 28 | 29 | @property 30 | def imm(self): 31 | return self.value.imm 32 | 33 | @property 34 | def reg(self): 35 | return self.value.reg 36 | 37 | @property 38 | def mem(self): 39 | return self.value.mem 40 | 41 | 42 | class CsSysz(ctypes.Structure): 43 | _fields_ = ( 44 | ('cc', ctypes.c_uint), 45 | ('op_count', ctypes.c_uint8), 46 | ('operands', SyszOp * 6), 47 | ) 48 | 49 | def get_arch_info(a): 50 | return (a.cc, copy_ctypes_list(a.operands[:a.op_count])) 51 | 52 | -------------------------------------------------------------------------------- /capstone/bindings/python/capstone/xcore.py: -------------------------------------------------------------------------------- 1 | # Capstone Python bindings, by Nguyen Anh Quynnh 2 | 3 | import ctypes 4 | from . import copy_ctypes_list 5 | from .xcore_const import * 6 | 7 | # define the API 8 | class XcoreOpMem(ctypes.Structure): 9 | _fields_ = ( 10 | ('base', ctypes.c_uint8), 11 | ('index', ctypes.c_uint8), 12 | ('disp', ctypes.c_int32), 13 | ('direct', ctypes.c_int), 14 | ) 15 | 16 | class XcoreOpValue(ctypes.Union): 17 | _fields_ = ( 18 | ('reg', ctypes.c_uint), 19 | ('imm', ctypes.c_int32), 20 | ('mem', XcoreOpMem), 21 | ) 22 | 23 | class XcoreOp(ctypes.Structure): 24 | _fields_ = ( 25 | ('type', ctypes.c_uint), 26 | ('value', XcoreOpValue), 27 | ) 28 | 29 | @property 30 | def imm(self): 31 | return self.value.imm 32 | 33 | @property 34 | def reg(self): 35 | return self.value.reg 36 | 37 | @property 38 | def mem(self): 39 | return self.value.mem 40 | 41 | 42 | class CsXcore(ctypes.Structure): 43 | _fields_ = ( 44 | ('op_count', ctypes.c_uint8), 45 | ('operands', XcoreOp * 8), 46 | ) 47 | 48 | def get_arch_info(a): 49 | return (copy_ctypes_list(a.operands[:a.op_count])) 50 | 51 | -------------------------------------------------------------------------------- /capstone/bindings/python/prebuilt/win32/.gitignore: -------------------------------------------------------------------------------- 1 | capstone.dll 2 | # Except this file 3 | !.gitignore 4 | -------------------------------------------------------------------------------- /capstone/bindings/python/prebuilt/win64/.gitignore: -------------------------------------------------------------------------------- 1 | capstone.dll 2 | # Except this file 3 | !.gitignore 4 | -------------------------------------------------------------------------------- /capstone/bindings/python/pyx/README: -------------------------------------------------------------------------------- 1 | This directory contains Cython files. 2 | -------------------------------------------------------------------------------- /capstone/bindings/python/test_all.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | import test, test_arm, test_arm64, test_detail, test_lite, test_mips, test_ppc, \ 4 | test_x86, test_skipdata, test_sparc, test_systemz 5 | 6 | 7 | test.test_class() 8 | test_arm.test_class() 9 | test_arm64.test_class() 10 | test_detail.test_class() 11 | test_lite.test_class() 12 | test_mips.test_class() 13 | test_ppc.test_class() 14 | test_sparc.test_class() 15 | test_systemz.test_class() 16 | test_x86.test_class() 17 | test_skipdata.test_class() 18 | -------------------------------------------------------------------------------- /capstone/bindings/python/xprint.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | # Capstone Python bindings, by Nguyen Anh Quynnh 3 | 4 | from __future__ import print_function 5 | import sys 6 | _python3 = sys.version_info.major == 3 7 | 8 | 9 | def to_hex(s): 10 | if _python3: 11 | return " ".join("0x{0:02x}".format(c) for c in s) # <-- Python 3 is OK 12 | else: 13 | return " ".join("0x{0:02x}".format(ord(c)) for c in s) 14 | 15 | def to_hex2(s): 16 | if _python3: 17 | r = "".join("{0:02x}".format(c) for c in s) # <-- Python 3 is OK 18 | else: 19 | r = "".join("{0:02x}".format(ord(c)) for c in s) 20 | while r[0] == '0': r = r[1:] 21 | return r 22 | 23 | def to_x(s): 24 | from struct import pack 25 | if not s: return '0' 26 | x = pack(">q", s) 27 | while x[0] in ('\0', 0): x = x[1:] 28 | return to_hex2(x) 29 | 30 | def to_x_32(s): 31 | from struct import pack 32 | if not s: return '0' 33 | x = pack(">i", s) 34 | while x[0] in ('\0', 0): x = x[1:] 35 | return to_hex2(x) 36 | -------------------------------------------------------------------------------- /capstone/contrib/README: -------------------------------------------------------------------------------- 1 | This directory contains contributions that do not belong to the core engine. 2 | Code here might be helpful for those who want to integrate Capstone into 3 | their own projects. 4 | 5 | The license of these code was defined by their authors. 6 | -------------------------------------------------------------------------------- /capstone/contrib/cs_driver/README: -------------------------------------------------------------------------------- 1 | This directory contains a sample project for using Capstone from a Windows 2 | driver. Open cs_driver.sln with Visual Studio 2013 or newer and see cs_driver.c 3 | for details. 4 | 5 | For prerequisites to compile Capstone for drivers, see COMPILE_MSVC.TXT. 6 | -------------------------------------------------------------------------------- /capstone/contrib/cs_driver/cs_driver/cs_driver.vcxproj.filters: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | {4FC737F1-C7A5-4376-A066-2A32D752A2FF} 6 | cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx 7 | 8 | 9 | {93995380-89BD-4b04-88EB-625FBE52EBFB} 10 | h;hpp;hxx;hm;inl;inc;xsd 11 | 12 | 13 | {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} 14 | rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms 15 | 16 | 17 | {8E41214B-6785-4CFE-B992-037D68949A14} 18 | inf;inv;inx;mof;mc; 19 | 20 | 21 | 22 | 23 | Source Files 24 | 25 | 26 | -------------------------------------------------------------------------------- /capstone/contrib/windows_kernel/README: -------------------------------------------------------------------------------- 1 | For Windows kernel programming, the SDK does not offer some functions 2 | needed by Capstone. The missing functions are: 3 | 4 | - Memory allocations: malloc(), calloc(), realloc() & free(). 5 | - Format input variables & write out result to char buffer: vsnprintf() 6 | 7 | This directory contains some code providing above-mentioned functions, so you can 8 | integrate Capstone with your Windows-kernel drivers using C++. 9 | 10 | All the code here is contributed by Peter Hlavaty 11 | See the full example with Capstone integration at https://github.com/zer0mem/libc.git 12 | -------------------------------------------------------------------------------- /capstone/contrib/windows_kernel/libc.h: -------------------------------------------------------------------------------- 1 | /** 2 | * @file libc.h 3 | * @author created by: Peter Hlavaty 4 | */ 5 | 6 | #pragma once 7 | 8 | #include 9 | 10 | EXTERN_C 11 | __drv_when(return!=0, __drv_allocatesMem(pBlock)) 12 | __checkReturn 13 | __drv_maxIRQL(DISPATCH_LEVEL) 14 | __bcount_opt(size) 15 | void* __cdecl malloc(__in size_t size); 16 | 17 | 18 | EXTERN_C 19 | __drv_when(return != 0, __drv_allocatesMem(p)) 20 | __checkReturn 21 | __drv_maxIRQL(DISPATCH_LEVEL) 22 | __bcount_opt(size * n) 23 | void* __cdecl calloc(size_t n, size_t size); 24 | 25 | 26 | EXTERN_C 27 | __drv_when(return!=0, __drv_allocatesMem(inblock)) 28 | __checkReturn 29 | __drv_maxIRQL(DISPATCH_LEVEL) 30 | __bcount_opt(size) 31 | void* __cdecl realloc(__in_opt void* ptr, __in size_t size); 32 | 33 | 34 | EXTERN_C 35 | __drv_maxIRQL(DISPATCH_LEVEL) 36 | void __cdecl free(__inout_opt __drv_freesMem(Mem) void* ptr); 37 | 38 | 39 | int __cdecl vsnprintf(char *buffer, size_t count, 40 | const char *format, va_list argptr); 41 | -------------------------------------------------------------------------------- /capstone/docs/BHUSA2014-capstone.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/capstone/docs/BHUSA2014-capstone.pdf -------------------------------------------------------------------------------- /capstone/functions.mk: -------------------------------------------------------------------------------- 1 | # Capstone Disassembly Engine 2 | # Common functions used by Makefile & tests/Makefile 3 | 4 | define compile 5 | ${CC} ${CFLAGS} -c $< -o $@ 6 | endef 7 | 8 | 9 | define log 10 | @printf " %-7s %s\n" "$(1)" "$(2)" 11 | endef 12 | 13 | -------------------------------------------------------------------------------- /capstone/msvc/README: -------------------------------------------------------------------------------- 1 | This directory includes all the necessary files to compile Capstone on Windows 2 | using Microsoft Visual Studio (VS). 3 | 4 | 5 | NOTE: 6 | 7 | (1) Visual Studio 2010 or newer versions is required. Open "capstone.sln" to 8 | build the libraries & test code with Visual Studio. The resulted binaries 9 | are put under either msvc/Debug, msvc/Release, msvc/x64/Debug, or 10 | msvc/x64/Release, depending on how you choose to compile them. 11 | 12 | (2) The solution (capstone.sln) & all project files (*.vcxproj) are made in 13 | Visual Studio 2010, so if you open them using newer version, an extra step 14 | is needed to convert them to current version. Just accept this when 15 | asked at the initial dialog, and proceed to build the solution normally 16 | afterwards. 17 | 18 | (3) The capstone_static_winkernel and test_winkernel projects are for Windows 19 | kernel drivers and excluded from build by default. In order to build them, 20 | you need to install Visual Studio 2013 or newer versions, and Windows Driver 21 | Kit 8.1 Update 1 or newer versions, then check "Build" check boxes for those 22 | projects on the Configuration Manager through the [Build] menu. 23 | -------------------------------------------------------------------------------- /capstone/msvc/capstone_static_winkernel/Debug/AArch64BaseInfo.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/capstone/msvc/capstone_static_winkernel/Debug/AArch64BaseInfo.obj -------------------------------------------------------------------------------- /capstone/msvc/capstone_static_winkernel/Debug/AArch64Disassembler.obj: -------------------------------------------------------------------------------- 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#TargetFrameworkVersion=v4.5:PlatformToolSet=WindowsKernelModeDriver10.0:EnableManagedIncrementalBuild=false:VCToolArchitecture=Native32Bit:WindowsTargetPlatformVersion=10.0.14393.0 2 | Debug|Win32|E:\OneDrive\程序代码\Repos\MProtect\| 3 | -------------------------------------------------------------------------------- /capstone/msvc/capstone_static_winkernel/Debug/capstone_static_winkernel.log: -------------------------------------------------------------------------------- 1 |  Building 'capstone_static_winkernel' with toolset 'WindowsKernelModeDriver10.0' and the 'Desktop' target platform. 2 | AArch64BaseInfo.c 3 | AArch64Disassembler.c 4 | AArch64InstPrinter.c 5 | AArch64Mapping.c 6 | AArch64Module.c 7 | ARMDisassembler.c 8 | ARMInstPrinter.c 9 | ARMMapping.c 10 | ARMModule.c 11 | MipsDisassembler.c 12 | MipsInstPrinter.c 13 | MipsMapping.c 14 | MipsModule.c 15 | PPCDisassembler.c 16 | PPCInstPrinter.c 17 | PPCMapping.c 18 | PPCModule.c 19 | SparcDisassembler.c 20 | SparcInstPrinter.c 21 | SparcMapping.c 22 | 正在生成代码... 23 | 正在编译... 24 | SparcModule.c 25 | SystemZDisassembler.c 26 | SystemZInstPrinter.c 27 | SystemZMapping.c 28 | SystemZMCTargetDesc.c 29 | SystemZModule.c 30 | X86ATTInstPrinter.c 31 | X86Disassembler.c 32 | X86DisassemblerDecoder.c 33 | X86IntelInstPrinter.c 34 | X86Mapping.c 35 | X86Module.c 36 | XCoreInstPrinter.c 37 | XCoreDisassembler.c 38 | XCoreMapping.c 39 | XCoreModule.c 40 | cs.c 41 | MCInst.c 42 | MCInstrDesc.c 43 | MCRegisterInfo.c 44 | 正在生成代码... 45 | 正在编译... 46 | SStream.c 47 | utils.c 48 | winkernel_mm.c 49 | 正在生成代码... 50 | capstone_static_winkernel.vcxproj -> E:\OneDrive\程序代码\Repos\MProtect\Debug\capstone_static_winkernel.lib 51 | -------------------------------------------------------------------------------- /capstone/msvc/capstone_static_winkernel/Debug/capstone_static_winkernel.pdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/capstone/msvc/capstone_static_winkernel/Debug/capstone_static_winkernel.pdb -------------------------------------------------------------------------------- /capstone/msvc/capstone_static_winkernel/Debug/cs.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/capstone/msvc/capstone_static_winkernel/Debug/cs.obj -------------------------------------------------------------------------------- /capstone/msvc/capstone_static_winkernel/Debug/utils.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/capstone/msvc/capstone_static_winkernel/Debug/utils.obj -------------------------------------------------------------------------------- /capstone/msvc/capstone_static_winkernel/Debug/winkernel_mm.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MechanicsMingYan/MProtect/ada986f3c5ae381fbba2be5bf7dea58cfcead46b/capstone/msvc/capstone_static_winkernel/Debug/winkernel_mm.obj -------------------------------------------------------------------------------- /capstone/packages/freebsd/ports/devel/capstone/Makefile: -------------------------------------------------------------------------------- 1 | # $FreeBSD$ 2 | 3 | PORTNAME= capstone 4 | PORTVERSION= 3.0.3 5 | CATEGORIES= devel 6 | MASTER_SITES= http://capstone-engine.org/download/${PORTVERSION}/ 7 | 8 | MAINTAINER= oliver.pntr@gmail.com 9 | COMMENT= Multi-platform, multi-architecture disassembly framework 10 | 11 | LICENSE= BSD3CLAUSE 12 | 13 | USES= gmake 14 | USE_LDCONFIG= yes 15 | 16 | MAKE_ENV+= INSTALL_LIB="${INSTALL_LIB}" \ 17 | INSTALL_DATA="${INSTALL_DATA}" 18 | 19 | post-build: 20 | # The pkgconfig file is generated and points to stagedir 21 | ${REINPLACE_CMD} -e '/libdir/s|\(libdir=\)\(.*\)\(devel/capstone/work/stage\)|\1|g' ${WRKSRC}/capstone.pc 22 | 23 | .include 24 | -------------------------------------------------------------------------------- /capstone/packages/freebsd/ports/devel/capstone/pkg-descr: -------------------------------------------------------------------------------- 1 | Capstone is a lightweight multi-platform, multi-architecture disassembly 2 | framework. 3 | 4 | Features: 5 | * Supported architectures: ARM, ARM64 (aka ARMv8), Mips, PowerPC, Sparc, 6 | SystemZ, X86, X86_64 & XCore. 7 | * Clean/simple/lightweight/intuitive architecture-neutral API 8 | * Provide details on disassembled instruction (called "decomposer") 9 | * Provide some semantics of the disassembled instruction, such as list of 10 | implicit registers read & written. 11 | * Implemented in pure C language, with bindings for Python, Ruby, C#, Java, 12 | Javascript, GO, OCaml & Vala available. 13 | * Native support for Windows & *nix (including MacOSX, Linux, *BSD & Solaris) 14 | * Thread-safe by design 15 | * Distributed under the open source BSD license 16 | 17 | WWW: http://capstone-engine.org/ 18 | -------------------------------------------------------------------------------- /capstone/packages/freebsd/ports/devel/capstone/pkg-plist: -------------------------------------------------------------------------------- 1 | include/capstone/arm.h 2 | include/capstone/arm64.h 3 | include/capstone/capstone.h 4 | include/capstone/mips.h 5 | include/capstone/ppc.h 6 | include/capstone/sparc.h 7 | include/capstone/systemz.h 8 | include/capstone/x86.h 9 | include/capstone/xcore.h 10 | include/capstone/platform.h 11 | lib/libcapstone.a 12 | lib/libcapstone.so 13 | libdata/pkgconfig/capstone.pc 14 | @dirrmtry include/capstone 15 | -------------------------------------------------------------------------------- /capstone/packages/homebrew/README: -------------------------------------------------------------------------------- 1 | This directory contains the Homebrew formula for Capstone. 2 | File capstone.rb should be put in its directory Library/Formula. 3 | -------------------------------------------------------------------------------- /capstone/packages/homebrew/capstone.rb: -------------------------------------------------------------------------------- 1 | require "formula" 2 | 3 | class Capstone < Formula 4 | homepage "http://capstone-engine.org" 5 | url "http://capstone-engine.org/download/3.0.1/capstone-3.0.1.tgz" 6 | sha1 "7f206c853c6b8d05de22e919c2455ab661654093" 7 | 8 | bottle do 9 | cellar :any 10 | sha1 "319b41766dd67e3017b83b1ce3df3cc81e6feb6a" => :yosemite 11 | sha1 "4f1bbe6b886c174924b1996aac7ed8d9850ff773" => :mavericks 12 | sha1 "5a73b99066037a6270f550e07bee8cbcb8e30a2c" => :mountain_lion 13 | end 14 | 15 | def install 16 | # Capstone's Make script ignores the prefix env and was installing 17 | # in /usr/local directly. So just inreplace the prefix for less pain. 18 | # https://github.com/aquynh/capstone/issues/228 19 | inreplace "make.sh", "export PREFIX=/usr/local", "export PREFIX=#{prefix}" 20 | 21 | ENV["HOMEBREW_CAPSTONE"] = "1" 22 | system "./make.sh" 23 | system "./make.sh", "install" 24 | end 25 | 26 | test do 27 | # Given the build issues around prefix, check is actually in the Cellar. 28 | assert File.exist? "#{lib}/libcapstone.a" 29 | end 30 | end 31 | -------------------------------------------------------------------------------- /capstone/packages/macports/devel/capstone/files/patch-Makefile.diff: -------------------------------------------------------------------------------- 1 | --- Makefile 2 | +++ Makefile 3 | @@ -246,14 +246,6 @@ EXT = dylib 4 | VERSION_EXT = $(API_MAJOR).$(EXT) 5 | $(LIBNAME)_LDFLAGS += -dynamiclib -install_name lib$(LIBNAME).$(VERSION_EXT) -current_version $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) -compatibility_version $(PKG_MAJOR).$(PKG_MINOR) 6 | AR_EXT = a 7 | -# Homebrew wants to make sure its formula does not disable FORTIFY_SOURCE 8 | -# However, this is not really necessary because 'CAPSTONE_USE_SYS_DYN_MEM=yes' by default 9 | -ifneq ($(HOMEBREW_CAPSTONE),1) 10 | -ifneq ($(CAPSTONE_USE_SYS_DYN_MEM),yes) 11 | -# remove string check because OSX kernel complains about missing symbols 12 | -CFLAGS += -D_FORTIFY_SOURCE=0 13 | -endif 14 | -endif 15 | else 16 | $(LIBNAME)_LDFLAGS += -shared 17 | # Cygwin? 18 | -------------------------------------------------------------------------------- /capstone/pkgconfig.mk: -------------------------------------------------------------------------------- 1 | # Package version of Capstone for Makefile. 2 | # To be used to generate capstone.pc for pkg-config 3 | 4 | # version major & minor 5 | PKG_MAJOR = 3 6 | PKG_MINOR = 0 7 | 8 | # version bugfix level. Example: PKG_EXTRA = 1 9 | PKG_EXTRA = 4 10 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-aba-abd.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x7c,0x22,0x2e = uaba v0.8b, v1.8b, v2.8b 3 | 0x20,0x7c,0x22,0x6e = uaba v0.16b, v1.16b, v2.16b 4 | 0x20,0x7c,0x62,0x2e = uaba v0.4h, v1.4h, v2.4h 5 | 0x20,0x7c,0x62,0x6e = uaba v0.8h, v1.8h, v2.8h 6 | 0x20,0x7c,0xa2,0x2e = uaba v0.2s, v1.2s, v2.2s 7 | 0x20,0x7c,0xa2,0x6e = uaba v0.4s, v1.4s, v2.4s 8 | 0x20,0x7c,0x22,0x0e = saba v0.8b, v1.8b, v2.8b 9 | 0x20,0x7c,0x22,0x4e = saba v0.16b, v1.16b, v2.16b 10 | 0x20,0x7c,0x62,0x0e = saba v0.4h, v1.4h, v2.4h 11 | 0x20,0x7c,0x62,0x4e = saba v0.8h, v1.8h, v2.8h 12 | 0x20,0x7c,0xa2,0x0e = saba v0.2s, v1.2s, v2.2s 13 | 0x20,0x7c,0xa2,0x4e = saba v0.4s, v1.4s, v2.4s 14 | 0x20,0x74,0x22,0x2e = uabd v0.8b, v1.8b, v2.8b 15 | 0x20,0x74,0x22,0x6e = uabd v0.16b, v1.16b, v2.16b 16 | 0x20,0x74,0x62,0x2e = uabd v0.4h, v1.4h, v2.4h 17 | 0x20,0x74,0x62,0x6e = uabd v0.8h, v1.8h, v2.8h 18 | 0x20,0x74,0xa2,0x2e = uabd v0.2s, v1.2s, v2.2s 19 | 0x20,0x74,0xa2,0x6e = uabd v0.4s, v1.4s, v2.4s 20 | 0x20,0x74,0x22,0x0e = sabd v0.8b, v1.8b, v2.8b 21 | 0x20,0x74,0x22,0x4e = sabd v0.16b, v1.16b, v2.16b 22 | 0x20,0x74,0x62,0x0e = sabd v0.4h, v1.4h, v2.4h 23 | 0x20,0x74,0x62,0x4e = sabd v0.8h, v1.8h, v2.8h 24 | 0x20,0x74,0xa2,0x0e = sabd v0.2s, v1.2s, v2.2s 25 | 0x20,0x74,0xa2,0x4e = sabd v0.4s, v1.4s, v2.4s 26 | 0x20,0xd4,0xa2,0x2e = fabd v0.2s, v1.2s, v2.2s 27 | 0xff,0xd5,0xb0,0x6e = fabd v31.4s, v15.4s, v16.4s 28 | 0x07,0xd5,0xf9,0x6e = fabd v7.2d, v8.2d, v25.2d 29 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-add-pairwise.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0xbc,0x22,0x0e = addp v0.8b, v1.8b, v2.8b 3 | 0x20,0xbc,0x22,0x4e = addp v0.16b, v1.16b, v2.16b 4 | 0x20,0xbc,0x62,0x0e = addp v0.4h, v1.4h, v2.4h 5 | 0x20,0xbc,0x62,0x4e = addp v0.8h, v1.8h, v2.8h 6 | 0x20,0xbc,0xa2,0x0e = addp v0.2s, v1.2s, v2.2s 7 | 0x20,0xbc,0xa2,0x4e = addp v0.4s, v1.4s, v2.4s 8 | 0x20,0xbc,0xe2,0x4e = addp v0.2d, v1.2d, v2.2d 9 | 0x20,0xd4,0x22,0x2e = faddp v0.2s, v1.2s, v2.2s 10 | 0x20,0xd4,0x22,0x6e = faddp v0.4s, v1.4s, v2.4s 11 | 0x20,0xd4,0x62,0x6e = faddp v0.2d, v1.2d, v2.2d 12 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-add-sub-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x84,0x22,0x0e = add v0.8b, v1.8b, v2.8b 3 | 0x20,0x84,0x22,0x4e = add v0.16b, v1.16b, v2.16b 4 | 0x20,0x84,0x62,0x0e = add v0.4h, v1.4h, v2.4h 5 | 0x20,0x84,0x62,0x4e = add v0.8h, v1.8h, v2.8h 6 | 0x20,0x84,0xa2,0x0e = add v0.2s, v1.2s, v2.2s 7 | 0x20,0x84,0xa2,0x4e = add v0.4s, v1.4s, v2.4s 8 | 0x20,0x84,0xe2,0x4e = add v0.2d, v1.2d, v2.2d 9 | 0x20,0x84,0x22,0x2e = sub v0.8b, v1.8b, v2.8b 10 | 0x20,0x84,0x22,0x6e = sub v0.16b, v1.16b, v2.16b 11 | 0x20,0x84,0x62,0x2e = sub v0.4h, v1.4h, v2.4h 12 | 0x20,0x84,0x62,0x6e = sub v0.8h, v1.8h, v2.8h 13 | 0x20,0x84,0xa2,0x2e = sub v0.2s, v1.2s, v2.2s 14 | 0x20,0x84,0xa2,0x6e = sub v0.4s, v1.4s, v2.4s 15 | 0x20,0x84,0xe2,0x6e = sub v0.2d, v1.2d, v2.2d 16 | 0x20,0xd4,0x22,0x0e = fadd v0.2s, v1.2s, v2.2s 17 | 0x20,0xd4,0x22,0x4e = fadd v0.4s, v1.4s, v2.4s 18 | 0x20,0xd4,0x62,0x4e = fadd v0.2d, v1.2d, v2.2d 19 | 0x20,0xd4,0xa2,0x0e = fsub v0.2s, v1.2s, v2.2s 20 | 0x20,0xd4,0xa2,0x4e = fsub v0.4s, v1.4s, v2.4s 21 | 0x20,0xd4,0xe2,0x4e = fsub v0.2d, v1.2d, v2.2d 22 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-bitwise-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x1c,0x22,0x0e = and v0.8b, v1.8b, v2.8b 3 | 0x20,0x1c,0x22,0x4e = and v0.16b, v1.16b, v2.16b 4 | 0x20,0x1c,0xa2,0x0e = orr v0.8b, v1.8b, v2.8b 5 | 0x20,0x1c,0xa2,0x4e = orr v0.16b, v1.16b, v2.16b 6 | 0x20,0x1c,0x22,0x2e = eor v0.8b, v1.8b, v2.8b 7 | 0x20,0x1c,0x22,0x6e = eor v0.16b, v1.16b, v2.16b 8 | 0x20,0x1c,0xa2,0x2e = bit v0.8b, v1.8b, v2.8b 9 | 0x20,0x1c,0xa2,0x6e = bit v0.16b, v1.16b, v2.16b 10 | 0x20,0x1c,0xe2,0x2e = bif v0.8b, v1.8b, v2.8b 11 | 0x20,0x1c,0xe2,0x6e = bif v0.16b, v1.16b, v2.16b 12 | 0x20,0x1c,0x62,0x2e = bsl v0.8b, v1.8b, v2.8b 13 | 0x20,0x1c,0x62,0x6e = bsl v0.16b, v1.16b, v2.16b 14 | 0x20,0x1c,0xe2,0x0e = orn v0.8b, v1.8b, v2.8b 15 | 0x20,0x1c,0xe2,0x4e = orn v0.16b, v1.16b, v2.16b 16 | 0x20,0x1c,0x62,0x0e = bic v0.8b, v1.8b, v2.8b 17 | 0x20,0x1c,0x62,0x4e = bic v0.16b, v1.16b, v2.16b 18 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-crypto.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x48,0x28,0x4e = aese v0.16b, v1.16b 3 | 0x20,0x58,0x28,0x4e = aesd v0.16b, v1.16b 4 | 0x20,0x68,0x28,0x4e = aesmc v0.16b, v1.16b 5 | 0x20,0x78,0x28,0x4e = aesimc v0.16b, v1.16b 6 | 0x20,0x08,0x28,0x5e = sha1h s0, s1 7 | 0x20,0x18,0x28,0x5e = sha1su1 v0.4s, v1.4s 8 | 0x20,0x28,0x28,0x5e = sha256su0 v0.4s, v1.4s 9 | 0x20,0x00,0x02,0x5e = sha1c q0, s1, v2.4s 10 | 0x20,0x10,0x02,0x5e = sha1p q0, s1, v2.4s 11 | 0x20,0x20,0x02,0x5e = sha1m q0, s1, v2.4s 12 | 0x20,0x30,0x02,0x5e = sha1su0 v0.4s, v1.4s, v2.4s 13 | 0x20,0x40,0x02,0x5e = sha256h q0, q1, v2.4s 14 | 0x20,0x50,0x02,0x5e = sha256h2 q0, q1, v2.4s 15 | 0x20,0x60,0x02,0x5e = sha256su1 v0.4s, v1.4s, v2.4s 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-extract.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x18,0x02,0x2e = ext v0.8b, v1.8b, v2.8b, #0x3 3 | 0x20,0x18,0x02,0x6e = ext v0.16b, v1.16b, v2.16b, #0x3 4 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-facge-facgt.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0xe0,0xef,0x30,0x2e = facge v0.2s, v31.2s, v16.2s 3 | 0xe4,0xec,0x2f,0x6e = facge v4.4s, v7.4s, v15.4s 4 | 0x5d,0xec,0x65,0x6e = facge v29.2d, v2.2d, v5.2d 5 | 0xe0,0xef,0x30,0x2e = facge v0.2s, v31.2s, v16.2s 6 | 0xe4,0xec,0x2f,0x6e = facge v4.4s, v7.4s, v15.4s 7 | 0x5d,0xec,0x65,0x6e = facge v29.2d, v2.2d, v5.2d 8 | 0xbf,0xef,0xbc,0x6e = facgt v31.4s, v29.4s, v28.4s 9 | 0x03,0xed,0xac,0x2e = facgt v3.2s, v8.2s, v12.2s 10 | 0xf1,0xed,0xed,0x6e = facgt v17.2d, v15.2d, v13.2d 11 | 0xbf,0xef,0xbc,0x6e = facgt v31.4s, v29.4s, v28.4s 12 | 0x03,0xed,0xac,0x2e = facgt v3.2s, v8.2s, v12.2s 13 | 0xf1,0xed,0xed,0x6e = facgt v17.2d, v15.2d, v13.2d 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-frsqrt-frecp.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0xe0,0xff,0xb0,0x0e = frsqrts v0.2s, v31.2s, v16.2s 3 | 0xe4,0xfc,0xaf,0x4e = frsqrts v4.4s, v7.4s, v15.4s 4 | 0x5d,0xfc,0xe5,0x4e = frsqrts v29.2d, v2.2d, v5.2d 5 | 0xbf,0xff,0x3c,0x4e = frecps v31.4s, v29.4s, v28.4s 6 | 0x03,0xfd,0x2c,0x0e = frecps v3.2s, v8.2s, v12.2s 7 | 0xf1,0xfd,0x6d,0x4e = frecps v17.2d, v15.2d, v13.2d 8 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-halving-add-sub.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x04,0x22,0x0e = shadd v0.8b, v1.8b, v2.8b 3 | 0x20,0x04,0x22,0x4e = shadd v0.16b, v1.16b, v2.16b 4 | 0x20,0x04,0x62,0x0e = shadd v0.4h, v1.4h, v2.4h 5 | 0x20,0x04,0x62,0x4e = shadd v0.8h, v1.8h, v2.8h 6 | 0x20,0x04,0xa2,0x0e = shadd v0.2s, v1.2s, v2.2s 7 | 0x20,0x04,0xa2,0x4e = shadd v0.4s, v1.4s, v2.4s 8 | 0x20,0x04,0x22,0x2e = uhadd v0.8b, v1.8b, v2.8b 9 | 0x20,0x04,0x22,0x6e = uhadd v0.16b, v1.16b, v2.16b 10 | 0x20,0x04,0x62,0x2e = uhadd v0.4h, v1.4h, v2.4h 11 | 0x20,0x04,0x62,0x6e = uhadd v0.8h, v1.8h, v2.8h 12 | 0x20,0x04,0xa2,0x2e = uhadd v0.2s, v1.2s, v2.2s 13 | 0x20,0x04,0xa2,0x6e = uhadd v0.4s, v1.4s, v2.4s 14 | 0x20,0x24,0x22,0x0e = shsub v0.8b, v1.8b, v2.8b 15 | 0x20,0x24,0x22,0x4e = shsub v0.16b, v1.16b, v2.16b 16 | 0x20,0x24,0x62,0x0e = shsub v0.4h, v1.4h, v2.4h 17 | 0x20,0x24,0x62,0x4e = shsub v0.8h, v1.8h, v2.8h 18 | 0x20,0x24,0xa2,0x0e = shsub v0.2s, v1.2s, v2.2s 19 | 0x20,0x24,0xa2,0x4e = shsub v0.4s, v1.4s, v2.4s 20 | 0x20,0x24,0x22,0x2e = uhsub v0.8b, v1.8b, v2.8b 21 | 0x20,0x24,0x22,0x6e = uhsub v0.16b, v1.16b, v2.16b 22 | 0x20,0x24,0x62,0x2e = uhsub v0.4h, v1.4h, v2.4h 23 | 0x20,0x24,0x62,0x6e = uhsub v0.8h, v1.8h, v2.8h 24 | 0x20,0x24,0xa2,0x2e = uhsub v0.2s, v1.2s, v2.2s 25 | 0x20,0x24,0xa2,0x6e = uhsub v0.4s, v1.4s, v2.4s 26 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-mla-mls-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x94,0x22,0x0e = mla v0.8b, v1.8b, v2.8b 3 | 0x20,0x94,0x22,0x4e = mla v0.16b, v1.16b, v2.16b 4 | 0x20,0x94,0x62,0x0e = mla v0.4h, v1.4h, v2.4h 5 | 0x20,0x94,0x62,0x4e = mla v0.8h, v1.8h, v2.8h 6 | 0x20,0x94,0xa2,0x0e = mla v0.2s, v1.2s, v2.2s 7 | 0x20,0x94,0xa2,0x4e = mla v0.4s, v1.4s, v2.4s 8 | 0x20,0x94,0x22,0x2e = mls v0.8b, v1.8b, v2.8b 9 | 0x20,0x94,0x22,0x6e = mls v0.16b, v1.16b, v2.16b 10 | 0x20,0x94,0x62,0x2e = mls v0.4h, v1.4h, v2.4h 11 | 0x20,0x94,0x62,0x6e = mls v0.8h, v1.8h, v2.8h 12 | 0x20,0x94,0xa2,0x2e = mls v0.2s, v1.2s, v2.2s 13 | 0x20,0x94,0xa2,0x6e = mls v0.4s, v1.4s, v2.4s 14 | 0x20,0xcc,0x22,0x0e = fmla v0.2s, v1.2s, v2.2s 15 | 0x20,0xcc,0x22,0x4e = fmla v0.4s, v1.4s, v2.4s 16 | 0x20,0xcc,0x62,0x4e = fmla v0.2d, v1.2d, v2.2d 17 | 0x20,0xcc,0xa2,0x0e = fmls v0.2s, v1.2s, v2.2s 18 | 0x20,0xcc,0xa2,0x4e = fmls v0.4s, v1.4s, v2.4s 19 | 0x20,0xcc,0xe2,0x4e = fmls v0.2d, v1.2d, v2.2d 20 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-mul-div-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x9c,0x22,0x0e = mul v0.8b, v1.8b, v2.8b 3 | 0x20,0x9c,0x22,0x4e = mul v0.16b, v1.16b, v2.16b 4 | 0x20,0x9c,0x62,0x0e = mul v0.4h, v1.4h, v2.4h 5 | 0x20,0x9c,0x62,0x4e = mul v0.8h, v1.8h, v2.8h 6 | 0x20,0x9c,0xa2,0x0e = mul v0.2s, v1.2s, v2.2s 7 | 0x20,0x9c,0xa2,0x4e = mul v0.4s, v1.4s, v2.4s 8 | 0x20,0xdc,0x22,0x2e = fmul v0.2s, v1.2s, v2.2s 9 | 0x20,0xdc,0x22,0x6e = fmul v0.4s, v1.4s, v2.4s 10 | 0x20,0xdc,0x62,0x6e = fmul v0.2d, v1.2d, v2.2d 11 | 0x20,0xfc,0x22,0x2e = fdiv v0.2s, v1.2s, v2.2s 12 | 0x20,0xfc,0x22,0x6e = fdiv v0.4s, v1.4s, v2.4s 13 | 0x20,0xfc,0x62,0x6e = fdiv v0.2d, v1.2d, v2.2d 14 | 0xf1,0x9f,0x30,0x2e = pmul v17.8b, v31.8b, v16.8b 15 | 0x20,0x9c,0x22,0x6e = pmul v0.16b, v1.16b, v2.16b 16 | 0x22,0xb7,0x63,0x0e = sqdmulh v2.4h, v25.4h, v3.4h 17 | 0xac,0xb4,0x6d,0x4e = sqdmulh v12.8h, v5.8h, v13.8h 18 | 0x23,0xb4,0xbe,0x0e = sqdmulh v3.2s, v1.2s, v30.2s 19 | 0x22,0xb7,0x63,0x2e = sqrdmulh v2.4h, v25.4h, v3.4h 20 | 0xac,0xb4,0x6d,0x6e = sqrdmulh v12.8h, v5.8h, v13.8h 21 | 0x23,0xb4,0xbe,0x2e = sqrdmulh v3.2s, v1.2s, v30.2s 22 | 0xb5,0xdc,0x2d,0x0e = fmulx v21.2s, v5.2s, v13.2s 23 | 0x21,0xdf,0x23,0x4e = fmulx v1.4s, v25.4s, v3.4s 24 | 0xdf,0xde,0x62,0x4e = fmulx v31.2d, v22.2d, v2.2d 25 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-rounding-halving-add.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x14,0x22,0x0e = srhadd v0.8b, v1.8b, v2.8b 3 | 0x20,0x14,0x22,0x4e = srhadd v0.16b, v1.16b, v2.16b 4 | 0x20,0x14,0x62,0x0e = srhadd v0.4h, v1.4h, v2.4h 5 | 0x20,0x14,0x62,0x4e = srhadd v0.8h, v1.8h, v2.8h 6 | 0x20,0x14,0xa2,0x0e = srhadd v0.2s, v1.2s, v2.2s 7 | 0x20,0x14,0xa2,0x4e = srhadd v0.4s, v1.4s, v2.4s 8 | 0x20,0x14,0x22,0x2e = urhadd v0.8b, v1.8b, v2.8b 9 | 0x20,0x14,0x22,0x6e = urhadd v0.16b, v1.16b, v2.16b 10 | 0x20,0x14,0x62,0x2e = urhadd v0.4h, v1.4h, v2.4h 11 | 0x20,0x14,0x62,0x6e = urhadd v0.8h, v1.8h, v2.8h 12 | 0x20,0x14,0xa2,0x2e = urhadd v0.2s, v1.2s, v2.2s 13 | 0x20,0x14,0xa2,0x6e = urhadd v0.4s, v1.4s, v2.4s 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-rounding-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x54,0x22,0x0e = srshl v0.8b, v1.8b, v2.8b 3 | 0x20,0x54,0x22,0x4e = srshl v0.16b, v1.16b, v2.16b 4 | 0x20,0x54,0x62,0x0e = srshl v0.4h, v1.4h, v2.4h 5 | 0x20,0x54,0x62,0x4e = srshl v0.8h, v1.8h, v2.8h 6 | 0x20,0x54,0xa2,0x0e = srshl v0.2s, v1.2s, v2.2s 7 | 0x20,0x54,0xa2,0x4e = srshl v0.4s, v1.4s, v2.4s 8 | 0x20,0x54,0xe2,0x4e = srshl v0.2d, v1.2d, v2.2d 9 | 0x20,0x54,0x22,0x2e = urshl v0.8b, v1.8b, v2.8b 10 | 0x20,0x54,0x22,0x6e = urshl v0.16b, v1.16b, v2.16b 11 | 0x20,0x54,0x62,0x2e = urshl v0.4h, v1.4h, v2.4h 12 | 0x20,0x54,0x62,0x6e = urshl v0.8h, v1.8h, v2.8h 13 | 0x20,0x54,0xa2,0x2e = urshl v0.2s, v1.2s, v2.2s 14 | 0x20,0x54,0xa2,0x6e = urshl v0.4s, v1.4s, v2.4s 15 | 0x20,0x54,0xe2,0x6e = urshl v0.2d, v1.2d, v2.2d 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-saturating-rounding-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x5c,0x22,0x0e = sqrshl v0.8b, v1.8b, v2.8b 3 | 0x20,0x5c,0x22,0x4e = sqrshl v0.16b, v1.16b, v2.16b 4 | 0x20,0x5c,0x62,0x0e = sqrshl v0.4h, v1.4h, v2.4h 5 | 0x20,0x5c,0x62,0x4e = sqrshl v0.8h, v1.8h, v2.8h 6 | 0x20,0x5c,0xa2,0x0e = sqrshl v0.2s, v1.2s, v2.2s 7 | 0x20,0x5c,0xa2,0x4e = sqrshl v0.4s, v1.4s, v2.4s 8 | 0x20,0x5c,0xe2,0x4e = sqrshl v0.2d, v1.2d, v2.2d 9 | 0x20,0x5c,0x22,0x2e = uqrshl v0.8b, v1.8b, v2.8b 10 | 0x20,0x5c,0x22,0x6e = uqrshl v0.16b, v1.16b, v2.16b 11 | 0x20,0x5c,0x62,0x2e = uqrshl v0.4h, v1.4h, v2.4h 12 | 0x20,0x5c,0x62,0x6e = uqrshl v0.8h, v1.8h, v2.8h 13 | 0x20,0x5c,0xa2,0x2e = uqrshl v0.2s, v1.2s, v2.2s 14 | 0x20,0x5c,0xa2,0x6e = uqrshl v0.4s, v1.4s, v2.4s 15 | 0x20,0x5c,0xe2,0x6e = uqrshl v0.2d, v1.2d, v2.2d 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-saturating-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x4c,0x22,0x0e = sqshl v0.8b, v1.8b, v2.8b 3 | 0x20,0x4c,0x22,0x4e = sqshl v0.16b, v1.16b, v2.16b 4 | 0x20,0x4c,0x62,0x0e = sqshl v0.4h, v1.4h, v2.4h 5 | 0x20,0x4c,0x62,0x4e = sqshl v0.8h, v1.8h, v2.8h 6 | 0x20,0x4c,0xa2,0x0e = sqshl v0.2s, v1.2s, v2.2s 7 | 0x20,0x4c,0xa2,0x4e = sqshl v0.4s, v1.4s, v2.4s 8 | 0x20,0x4c,0xe2,0x4e = sqshl v0.2d, v1.2d, v2.2d 9 | 0x20,0x4c,0x22,0x2e = uqshl v0.8b, v1.8b, v2.8b 10 | 0x20,0x4c,0x22,0x6e = uqshl v0.16b, v1.16b, v2.16b 11 | 0x20,0x4c,0x62,0x2e = uqshl v0.4h, v1.4h, v2.4h 12 | 0x20,0x4c,0x62,0x6e = uqshl v0.8h, v1.8h, v2.8h 13 | 0x20,0x4c,0xa2,0x2e = uqshl v0.2s, v1.2s, v2.2s 14 | 0x20,0x4c,0xa2,0x6e = uqshl v0.4s, v1.4s, v2.4s 15 | 0x20,0x4c,0xe2,0x6e = uqshl v0.2d, v1.2d, v2.2d 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-abs.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x1d,0xbb,0xe0,0x5e = abs d29, d24 3 | 0x1d,0xd7,0xb4,0x7e = fabd s29, s24, s20 4 | 0x1d,0xd7,0xf4,0x7e = fabd d29, d24, d20 5 | 0xd3,0x79,0x20,0x5e = sqabs b19, b14 6 | 0xf5,0x79,0x60,0x5e = sqabs h21, h15 7 | 0x94,0x79,0xa0,0x5e = sqabs s20, s12 8 | 0x92,0x79,0xe0,0x5e = sqabs d18, d12 9 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-add-sub.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x1f,0x84,0xf0,0x5e = add d31, d0, d16 3 | 0xe1,0x84,0xe8,0x7e = sub d1, d7, d8 4 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-by-elem-mla.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x10,0x81,0x5f = fmla s0, s1, v1.s[0] 3 | 0x7e,0x11,0xa1,0x5f = fmla s30, s11, v1.s[1] 4 | 0xa4,0x18,0x87,0x5f = fmla s4, s5, v7.s[2] 5 | 0xd0,0x1a,0xb0,0x5f = fmla s16, s22, v16.s[3] 6 | 0x20,0x10,0xc1,0x5f = fmla d0, d1, v1.d[0] 7 | 0x7e,0x19,0xc1,0x5f = fmla d30, d11, v1.d[1] 8 | 0x62,0x50,0x84,0x5f = fmls s2, s3, v4.s[0] 9 | 0x5d,0x51,0xbc,0x5f = fmls s29, s10, v28.s[1] 10 | 0x85,0x59,0x97,0x5f = fmls s5, s12, v23.s[2] 11 | 0x27,0x5a,0xba,0x5f = fmls s7, s17, v26.s[3] 12 | 0x20,0x50,0xc1,0x5f = fmls d0, d1, v1.d[0] 13 | 0x7e,0x59,0xc1,0x5f = fmls d30, d11, v1.d[1] 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-by-elem-mul.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x90,0x81,0x5f = fmul s0, s1, v1.s[0] 3 | 0x7e,0x91,0xa1,0x5f = fmul s30, s11, v1.s[1] 4 | 0xa4,0x98,0x87,0x5f = fmul s4, s5, v7.s[2] 5 | 0xd0,0x9a,0xb0,0x5f = fmul s16, s22, v16.s[3] 6 | 0x20,0x90,0xc1,0x5f = fmul d0, d1, v1.d[0] 7 | 0x7e,0x99,0xc1,0x5f = fmul d30, d11, v1.d[1] 8 | 0x46,0x90,0x88,0x7f = fmulx s6, s2, v8.s[0] 9 | 0x67,0x90,0xad,0x7f = fmulx s7, s3, v13.s[1] 10 | 0xe9,0x98,0x89,0x7f = fmulx s9, s7, v9.s[2] 11 | 0xad,0x9a,0xaa,0x7f = fmulx s13, s21, v10.s[3] 12 | 0x2f,0x91,0xc7,0x7f = fmulx d15, d9, v7.d[0] 13 | 0x8d,0x99,0xcb,0x7f = fmulx d13, d12, v11.d[1] 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x00,0x30,0x40,0x5f = sqdmlal s0, h0, v0.h[0] 3 | 0x27,0x30,0x74,0x5f = sqdmlal s7, h1, v4.h[3] 4 | 0x0b,0x3a,0x48,0x5f = sqdmlal s11, h16, v8.h[4] 5 | 0xde,0x3b,0x7f,0x5f = sqdmlal s30, h30, v15.h[7] 6 | 0x00,0x30,0x83,0x5f = sqdmlal d0, s0, v3.s[0] 7 | 0xde,0x3b,0xbe,0x5f = sqdmlal d30, s30, v30.s[3] 8 | 0x28,0x31,0xae,0x5f = sqdmlal d8, s9, v14.s[1] 9 | 0x21,0x70,0x41,0x5f = sqdmlsl s1, h1, v1.h[0] 10 | 0x48,0x70,0x55,0x5f = sqdmlsl s8, h2, v5.h[1] 11 | 0xac,0x71,0x6e,0x5f = sqdmlsl s12, h13, v14.h[2] 12 | 0x9d,0x7b,0x7b,0x5f = sqdmlsl s29, h28, v11.h[7] 13 | 0x21,0x70,0x8d,0x5f = sqdmlsl d1, s1, v13.s[0] 14 | 0xff,0x7b,0x9f,0x5f = sqdmlsl d31, s31, v31.s[2] 15 | 0x50,0x7a,0xbc,0x5f = sqdmlsl d16, s18, v28.s[3] 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x21,0xb0,0x51,0x5f = sqdmull s1, h1, v1.h[1] 3 | 0x48,0xb0,0x65,0x5f = sqdmull s8, h2, v5.h[2] 4 | 0x2c,0xb2,0x79,0x5f = sqdmull s12, h17, v9.h[3] 5 | 0xff,0xbb,0x7f,0x5f = sqdmull s31, h31, v15.h[7] 6 | 0x21,0xb0,0x84,0x5f = sqdmull d1, s1, v4.s[0] 7 | 0xff,0xbb,0xbf,0x5f = sqdmull d31, s31, v31.s[3] 8 | 0x49,0xb1,0x8f,0x5f = sqdmull d9, s10, v15.s[0] 9 | 0x20,0xc0,0x40,0x5f = sqdmulh h0, h1, v0.h[0] 10 | 0x6a,0xc9,0x4a,0x5f = sqdmulh h10, h11, v10.h[4] 11 | 0xb4,0xca,0x7f,0x5f = sqdmulh h20, h21, v15.h[7] 12 | 0x59,0xcb,0xbb,0x5f = sqdmulh s25, s26, v27.s[3] 13 | 0xc2,0xc0,0x87,0x5f = sqdmulh s2, s6, v7.s[0] 14 | 0xdf,0xd3,0x6e,0x5f = sqrdmulh h31, h30, v14.h[2] 15 | 0x21,0xd8,0x41,0x5f = sqrdmulh h1, h1, v1.h[4] 16 | 0xd5,0xda,0x7f,0x5f = sqrdmulh h21, h22, v15.h[7] 17 | 0xc5,0xd8,0x87,0x5f = sqrdmulh s5, s6, v7.s[2] 18 | 0x54,0xd3,0xbb,0x5f = sqrdmulh s20, s26, v27.s[1] 19 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-compare.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0xb4,0x8e,0xf6,0x7e = cmeq d20, d21, d22 3 | 0xb4,0x9a,0xe0,0x5e = cmeq d20, d21, #0x0 4 | 0xb4,0x3e,0xf6,0x7e = cmhs d20, d21, d22 5 | 0xb4,0x3e,0xf6,0x5e = cmge d20, d21, d22 6 | 0xb4,0x8a,0xe0,0x7e = cmge d20, d21, #0x0 7 | 0xb4,0x36,0xf6,0x7e = cmhi d20, d21, d22 8 | 0xb4,0x36,0xf6,0x5e = cmgt d20, d21, d22 9 | 0xb4,0x8a,0xe0,0x5e = cmgt d20, d21, #0x0 10 | 0xb4,0x9a,0xe0,0x7e = cmle d20, d21, #0x0 11 | 0xb4,0xaa,0xe0,0x5e = cmlt d20, d21, #0x0 12 | 0xb4,0x8e,0xf6,0x5e = cmtst d20, d21, d22 13 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-cvt.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0xb6,0xd9,0x21,0x5e = scvtf s22, s13 3 | 0x95,0xd9,0x61,0x5e = scvtf d21, d12 4 | 0xb6,0xd9,0x21,0x7e = ucvtf s22, s13 5 | 0xd5,0xd9,0x61,0x7e = ucvtf d21, d14 6 | 0xb6,0xe5,0x20,0x5f = scvtf s22, s13, #32 7 | 0x95,0xe5,0x40,0x5f = scvtf d21, d12, #64 8 | 0xb6,0xe5,0x20,0x7f = ucvtf s22, s13, #32 9 | 0xd5,0xe5,0x40,0x7f = ucvtf d21, d14, #64 10 | 0x95,0xfd,0x3f,0x5f = fcvtzs s21, s12, #1 11 | 0x95,0xfd,0x7f,0x5f = fcvtzs d21, d12, #1 12 | 0x95,0xfd,0x3f,0x7f = fcvtzu s21, s12, #1 13 | 0x95,0xfd,0x7f,0x7f = fcvtzu d21, d12, #1 14 | 0xb6,0x69,0x61,0x7e = fcvtxn s22, d13 15 | 0xac,0xc9,0x21,0x5e = fcvtas s12, s13 16 | 0xd5,0xc9,0x61,0x5e = fcvtas d21, d14 17 | 0xac,0xc9,0x21,0x7e = fcvtau s12, s13 18 | 0xd5,0xc9,0x61,0x7e = fcvtau d21, d14 19 | 0xb6,0xb9,0x21,0x5e = fcvtms s22, s13 20 | 0xd5,0xb9,0x61,0x5e = fcvtms d21, d14 21 | 0xac,0xb9,0x21,0x7e = fcvtmu s12, s13 22 | 0xd5,0xb9,0x61,0x7e = fcvtmu d21, d14 23 | 0xb6,0xa9,0x21,0x5e = fcvtns s22, s13 24 | 0xd5,0xa9,0x61,0x5e = fcvtns d21, d14 25 | 0xac,0xa9,0x21,0x7e = fcvtnu s12, s13 26 | 0xd5,0xa9,0x61,0x7e = fcvtnu d21, d14 27 | 0xb6,0xa9,0xa1,0x5e = fcvtps s22, s13 28 | 0xd5,0xa9,0xe1,0x5e = fcvtps d21, d14 29 | 0xac,0xa9,0xa1,0x7e = fcvtpu s12, s13 30 | 0xd5,0xa9,0xe1,0x7e = fcvtpu d21, d14 31 | 0xac,0xb9,0xa1,0x5e = fcvtzs s12, s13 32 | 0xd5,0xb9,0xe1,0x5e = fcvtzs d21, d14 33 | 0xac,0xb9,0xa1,0x7e = fcvtzu s12, s13 34 | 0xd5,0xb9,0xe1,0x7e = fcvtzu d21, d14 35 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-dup.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x00,0x04,0x1f,0x5e = dup b0, v0.b[15] 3 | 0x01,0x04,0x0f,0x5e = dup b1, v0.b[7] 4 | 0x11,0x04,0x01,0x5e = dup b17, v0.b[0] 5 | 0xe5,0x07,0x1e,0x5e = dup h5, v31.h[7] 6 | 0x29,0x04,0x12,0x5e = dup h9, v1.h[4] 7 | 0x2b,0x06,0x02,0x5e = dup h11, v17.h[0] 8 | 0x42,0x04,0x1c,0x5e = dup s2, v2.s[3] 9 | 0xa4,0x06,0x04,0x5e = dup s4, v21.s[0] 10 | 0xbf,0x06,0x14,0x5e = dup s31, v21.s[2] 11 | 0xa3,0x04,0x08,0x5e = dup d3, v5.d[0] 12 | 0xa6,0x04,0x18,0x5e = dup d6, v5.d[1] 13 | 0x00,0x04,0x1f,0x5e = dup b0, v0.b[15] 14 | 0x01,0x04,0x0f,0x5e = dup b1, v0.b[7] 15 | 0x11,0x04,0x01,0x5e = dup b17, v0.b[0] 16 | 0xe5,0x07,0x1e,0x5e = dup h5, v31.h[7] 17 | 0x29,0x04,0x12,0x5e = dup h9, v1.h[4] 18 | 0x2b,0x06,0x02,0x5e = dup h11, v17.h[0] 19 | 0x42,0x04,0x1c,0x5e = dup s2, v2.s[3] 20 | 0xa4,0x06,0x04,0x5e = dup s4, v21.s[0] 21 | 0xbf,0x06,0x14,0x5e = dup s31, v21.s[2] 22 | 0xa3,0x04,0x08,0x5e = dup d3, v5.d[0] 23 | 0xa6,0x04,0x18,0x5e = dup d6, v5.d[1] 24 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-extract-narrow.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0xd3,0x29,0x21,0x7e = sqxtun b19, h14 3 | 0xf5,0x29,0x61,0x7e = sqxtun h21, s15 4 | 0x94,0x29,0xa1,0x7e = sqxtun s20, d12 5 | 0x52,0x4a,0x21,0x5e = sqxtn b18, h18 6 | 0x34,0x4a,0x61,0x5e = sqxtn h20, s17 7 | 0xd3,0x49,0xa1,0x5e = sqxtn s19, d14 8 | 0x52,0x4a,0x21,0x7e = uqxtn b18, h18 9 | 0x34,0x4a,0x61,0x7e = uqxtn h20, s17 10 | 0xd3,0x49,0xa1,0x7e = uqxtn s19, d14 11 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-fp-compare.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x6a,0xe5,0x2c,0x5e = fcmeq s10, s11, s12 3 | 0xb4,0xe6,0x76,0x5e = fcmeq d20, d21, d22 4 | 0x6a,0xd9,0xa0,0x5e = fcmeq s10, s11, #0.0 5 | 0xb4,0xda,0xe0,0x5e = fcmeq d20, d21, #0.0 6 | 0x6a,0xe5,0x2c,0x7e = fcmge s10, s11, s12 7 | 0xb4,0xe6,0x76,0x7e = fcmge d20, d21, d22 8 | 0x6a,0xc9,0xa0,0x7e = fcmge s10, s11, #0.0 9 | 0xb4,0xca,0xe0,0x7e = fcmge d20, d21, #0.0 10 | 0x6a,0xe5,0xac,0x7e = fcmgt s10, s11, s12 11 | 0xb4,0xe6,0xf6,0x7e = fcmgt d20, d21, d22 12 | 0x6a,0xc9,0xa0,0x5e = fcmgt s10, s11, #0.0 13 | 0xb4,0xca,0xe0,0x5e = fcmgt d20, d21, #0.0 14 | 0x6a,0xd9,0xa0,0x7e = fcmle s10, s11, #0.0 15 | 0xb4,0xda,0xe0,0x7e = fcmle d20, d21, #0.0 16 | 0x6a,0xe9,0xa0,0x5e = fcmlt s10, s11, #0.0 17 | 0xb4,0xea,0xe0,0x5e = fcmlt d20, d21, #0.0 18 | 0x6a,0xed,0x2c,0x7e = facge s10, s11, s12 19 | 0xb4,0xee,0x76,0x7e = facge d20, d21, d22 20 | 0x6a,0xed,0xac,0x7e = facgt s10, s11, s12 21 | 0xb4,0xee,0xf6,0x7e = facgt d20, d21, d22 22 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-mul.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x6a,0xb5,0x6c,0x5e = sqdmulh h10, h11, h12 3 | 0xb4,0xb6,0xa2,0x5e = sqdmulh s20, s21, s2 4 | 0x6a,0xb5,0x6c,0x7e = sqrdmulh h10, h11, h12 5 | 0xb4,0xb6,0xa2,0x7e = sqrdmulh s20, s21, s2 6 | 0xd4,0xde,0x2f,0x5e = fmulx s20, s22, s15 7 | 0x77,0xdd,0x61,0x5e = fmulx d23, d11, d1 8 | 0x71,0x93,0x6c,0x5e = sqdmlal s17, h27, h12 9 | 0x13,0x93,0xac,0x5e = sqdmlal d19, s24, s12 10 | 0x8e,0xb1,0x79,0x5e = sqdmlsl s14, h12, h25 11 | 0xec,0xb2,0xad,0x5e = sqdmlsl d12, s23, s13 12 | 0xcc,0xd2,0x6c,0x5e = sqdmull s12, h22, h12 13 | 0xcf,0xd2,0xac,0x5e = sqdmull d15, s22, s12 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-neg.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x1d,0xbb,0xe0,0x7e = neg d29, d24 3 | 0xd3,0x79,0x20,0x7e = sqneg b19, b14 4 | 0xf5,0x79,0x60,0x7e = sqneg h21, h15 5 | 0x94,0x79,0xa0,0x7e = sqneg s20, s12 6 | 0x92,0x79,0xe0,0x7e = sqneg d18, d12 7 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-recip.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x15,0xfe,0x2d,0x5e = frecps s21, s16, s13 3 | 0xd6,0xff,0x75,0x5e = frecps d22, d30, d21 4 | 0xb5,0xfc,0xac,0x5e = frsqrts s21, s5, s12 5 | 0xc8,0xfe,0xf2,0x5e = frsqrts d8, d22, d18 6 | 0xd3,0xd9,0xa1,0x5e = frecpe s19, s14 7 | 0xad,0xd9,0xe1,0x5e = frecpe d13, d13 8 | 0x52,0xf9,0xa1,0x5e = frecpx s18, s10 9 | 0x70,0xfa,0xe1,0x5e = frecpx d16, d19 10 | 0xb6,0xd9,0xa1,0x7e = frsqrte s22, s13 11 | 0x95,0xd9,0xe1,0x7e = frsqrte d21, d12 12 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-reduce-pairwise.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0xb8,0xf1,0x5e = addp d0, v1.2d 3 | 0x34,0xd8,0x70,0x7e = faddp d20, v1.2d 4 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-rounding-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0xf1,0x57,0xe8,0x5e = srshl d17, d31, d8 3 | 0xf1,0x57,0xe8,0x7e = urshl d17, d31, d8 4 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-saturating-add-sub.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x0c,0x22,0x5e = sqadd b0, b1, b2 3 | 0x6a,0x0d,0x6c,0x5e = sqadd h10, h11, h12 4 | 0xb4,0x0e,0xa2,0x5e = sqadd s20, s21, s2 5 | 0xf1,0x0f,0xe8,0x5e = sqadd d17, d31, d8 6 | 0x20,0x0c,0x22,0x7e = uqadd b0, b1, b2 7 | 0x6a,0x0d,0x6c,0x7e = uqadd h10, h11, h12 8 | 0xb4,0x0e,0xa2,0x7e = uqadd s20, s21, s2 9 | 0xf1,0x0f,0xe8,0x7e = uqadd d17, d31, d8 10 | 0x20,0x2c,0x22,0x5e = sqsub b0, b1, b2 11 | 0x6a,0x2d,0x6c,0x5e = sqsub h10, h11, h12 12 | 0xb4,0x2e,0xa2,0x5e = sqsub s20, s21, s2 13 | 0xf1,0x2f,0xe8,0x5e = sqsub d17, d31, d8 14 | 0x20,0x2c,0x22,0x7e = uqsub b0, b1, b2 15 | 0x6a,0x2d,0x6c,0x7e = uqsub h10, h11, h12 16 | 0xb4,0x2e,0xa2,0x7e = uqsub s20, s21, s2 17 | 0xf1,0x2f,0xe8,0x7e = uqsub d17, d31, d8 18 | 0xd3,0x39,0x20,0x5e = suqadd b19, b14 19 | 0xf4,0x39,0x60,0x5e = suqadd h20, h15 20 | 0x95,0x39,0xa0,0x5e = suqadd s21, s12 21 | 0xd2,0x3a,0xe0,0x5e = suqadd d18, d22 22 | 0xd3,0x39,0x20,0x7e = usqadd b19, b14 23 | 0xf4,0x39,0x60,0x7e = usqadd h20, h15 24 | 0x95,0x39,0xa0,0x7e = usqadd s21, s12 25 | 0xd2,0x3a,0xe0,0x7e = usqadd d18, d22 26 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x5c,0x22,0x5e = sqrshl b0, b1, b2 3 | 0x6a,0x5d,0x6c,0x5e = sqrshl h10, h11, h12 4 | 0xb4,0x5e,0xa2,0x5e = sqrshl s20, s21, s2 5 | 0xf1,0x5f,0xe8,0x5e = sqrshl d17, d31, d8 6 | 0x20,0x5c,0x22,0x7e = uqrshl b0, b1, b2 7 | 0x6a,0x5d,0x6c,0x7e = uqrshl h10, h11, h12 8 | 0xb4,0x5e,0xa2,0x7e = uqrshl s20, s21, s2 9 | 0xf1,0x5f,0xe8,0x7e = uqrshl d17, d31, d8 10 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-saturating-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x4c,0x22,0x5e = sqshl b0, b1, b2 3 | 0x6a,0x4d,0x6c,0x5e = sqshl h10, h11, h12 4 | 0xb4,0x4e,0xa2,0x5e = sqshl s20, s21, s2 5 | 0xf1,0x4f,0xe8,0x5e = sqshl d17, d31, d8 6 | 0x20,0x4c,0x22,0x7e = uqshl b0, b1, b2 7 | 0x6a,0x4d,0x6c,0x7e = uqshl h10, h11, h12 8 | 0xb4,0x4e,0xa2,0x7e = uqshl s20, s21, s2 9 | 0xf1,0x4f,0xe8,0x7e = uqshl d17, d31, d8 10 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-scalar-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0xf1,0x47,0xe8,0x5e = sshl d17, d31, d8 3 | 0xf1,0x47,0xe8,0x7e = ushl d17, d31, d8 4 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-shift-left-long.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0xa4,0x0b,0x0f = sshll v0.8h, v1.8b, #3 3 | 0x20,0xa4,0x13,0x0f = sshll v0.4s, v1.4h, #3 4 | 0x20,0xa4,0x23,0x0f = sshll v0.2d, v1.2s, #3 5 | 0x20,0xa4,0x0b,0x4f = sshll2 v0.8h, v1.16b, #3 6 | 0x20,0xa4,0x13,0x4f = sshll2 v0.4s, v1.8h, #3 7 | 0x20,0xa4,0x23,0x4f = sshll2 v0.2d, v1.4s, #3 8 | 0x20,0xa4,0x0b,0x2f = ushll v0.8h, v1.8b, #3 9 | 0x20,0xa4,0x13,0x2f = ushll v0.4s, v1.4h, #3 10 | 0x20,0xa4,0x23,0x2f = ushll v0.2d, v1.2s, #3 11 | 0x20,0xa4,0x0b,0x6f = ushll2 v0.8h, v1.16b, #3 12 | 0x20,0xa4,0x13,0x6f = ushll2 v0.4s, v1.8h, #3 13 | 0x20,0xa4,0x23,0x6f = ushll2 v0.2d, v1.4s, #3 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-shift.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x44,0x22,0x0e = sshl v0.8b, v1.8b, v2.8b 3 | 0x20,0x44,0x22,0x4e = sshl v0.16b, v1.16b, v2.16b 4 | 0x20,0x44,0x62,0x0e = sshl v0.4h, v1.4h, v2.4h 5 | 0x20,0x44,0x62,0x4e = sshl v0.8h, v1.8h, v2.8h 6 | 0x20,0x44,0xa2,0x0e = sshl v0.2s, v1.2s, v2.2s 7 | 0x20,0x44,0xa2,0x4e = sshl v0.4s, v1.4s, v2.4s 8 | 0x20,0x44,0xe2,0x4e = sshl v0.2d, v1.2d, v2.2d 9 | 0x20,0x44,0x22,0x2e = ushl v0.8b, v1.8b, v2.8b 10 | 0x20,0x44,0x22,0x6e = ushl v0.16b, v1.16b, v2.16b 11 | 0x20,0x44,0x62,0x2e = ushl v0.4h, v1.4h, v2.4h 12 | 0x20,0x44,0x62,0x6e = ushl v0.8h, v1.8h, v2.8h 13 | 0x20,0x44,0xa2,0x2e = ushl v0.2s, v1.2s, v2.2s 14 | 0x20,0x44,0xa2,0x6e = ushl v0.4s, v1.4s, v2.4s 15 | 0x20,0x44,0xe2,0x6e = ushl v0.2d, v1.2d, v2.2d 16 | 0x20,0x54,0x0b,0x0f = shl v0.8b, v1.8b, #3 17 | 0x20,0x54,0x13,0x0f = shl v0.4h, v1.4h, #3 18 | 0x20,0x54,0x23,0x0f = shl v0.2s, v1.2s, #3 19 | 0x20,0x54,0x0b,0x4f = shl v0.16b, v1.16b, #3 20 | 0x20,0x54,0x13,0x4f = shl v0.8h, v1.8h, #3 21 | 0x20,0x54,0x23,0x4f = shl v0.4s, v1.4s, #3 22 | 0x20,0x54,0x43,0x4f = shl v0.2d, v1.2d, #3 23 | -------------------------------------------------------------------------------- /capstone/suite/MC/AArch64/neon-tbl.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM64, 0, None 2 | 0x20,0x00,0x02,0x0e = tbl v0.8b, {v1.16b}, v2.8b 3 | 0x20,0x20,0x02,0x0e = tbl v0.8b, {v1.16b, v2.16b}, v2.8b 4 | 0x20,0x40,0x02,0x0e = tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b 5 | 0x20,0x60,0x02,0x0e = tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b 6 | 0xe0,0x63,0x02,0x0e = tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b 7 | 0x20,0x00,0x02,0x4e = tbl v0.16b, {v1.16b}, v2.16b 8 | 0x20,0x20,0x02,0x4e = tbl v0.16b, {v1.16b, v2.16b}, v2.16b 9 | 0x20,0x40,0x02,0x4e = tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b 10 | 0x20,0x60,0x02,0x4e = tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b 11 | 0xc0,0x63,0x02,0x4e = tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b 12 | 0x20,0x10,0x02,0x0e = tbx v0.8b, {v1.16b}, v2.8b 13 | 0x20,0x30,0x02,0x0e = tbx v0.8b, {v1.16b, v2.16b}, v2.8b 14 | 0x20,0x50,0x02,0x0e = tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b 15 | 0x20,0x70,0x02,0x0e = tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b 16 | 0xe0,0x73,0x02,0x0e = tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b 17 | 0x20,0x10,0x02,0x4e = tbx v0.16b, {v1.16b}, v2.16b 18 | 0x20,0x30,0x02,0x4e = tbx v0.16b, {v1.16b, v2.16b}, v2.16b 19 | 0x20,0x50,0x02,0x4e = tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b 20 | 0x20,0x70,0x02,0x4e = tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b 21 | 0xc0,0x73,0x02,0x4e = tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b 22 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/arm-aliases.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x03,0x10,0x82,0xe0 = add r1, r2, r3 3 | 0x03,0x10,0x42,0xe0 = sub r1, r2, r3 4 | 0x03,0x10,0x22,0xe0 = eor r1, r2, r3 5 | 0x03,0x10,0x82,0xe1 = orr r1, r2, r3 6 | 0x03,0x10,0x02,0xe0 = and r1, r2, r3 7 | 0x03,0x10,0xc2,0xe1 = bic r1, r2, r3 8 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/arm-it-block.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x03,0x20,0xa0,0x01 = moveq r2, r3 3 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/arm-thumb-trustzone.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xff,0xf7,0x00,0x80 = smc #15 3 | 0x0c,0xbf = ite eq 4 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/arm-trustzone.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x7f,0x00,0x60,0xe1 = smc #15 3 | 0x70,0x00,0x60,0x01 = smceq #0 4 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/arm_addrmode2.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x02,0x10,0xb0,0xe6 = ldrt r1, [r0], r2 3 | 0xa2,0x11,0xb0,0xe6 = ldrt r1, [r0], r2, lsr #3 4 | 0x04,0x10,0xb0,0xe4 = ldrt r1, [r0], #4 5 | 0x02,0x10,0xf0,0xe6 = ldrbt r1, [r0], r2 6 | 0xa2,0x11,0xf0,0xe6 = ldrbt r1, [r0], r2, lsr #3 7 | 0x04,0x10,0xf0,0xe4 = ldrbt r1, [r0], #4 8 | 0x02,0x10,0xa0,0xe6 = strt r1, [r0], r2 9 | 0xa2,0x11,0xa0,0xe6 = strt r1, [r0], r2, lsr #3 10 | 0x04,0x10,0xa0,0xe4 = strt r1, [r0], #4 11 | 0x02,0x10,0xe0,0xe6 = strbt r1, [r0], r2 12 | 0xa2,0x11,0xe0,0xe6 = strbt r1, [r0], r2, lsr #3 13 | 0x04,0x10,0xe0,0xe4 = strbt r1, [r0], #4 14 | 0xa2,0x11,0xb0,0xe7 = ldr r1, [r0, r2, lsr #3]! 15 | 0xa2,0x11,0xf0,0xe7 = ldrb r1, [r0, r2, lsr #3]! 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/arm_addrmode3.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0xd2,0x10,0xb0,0xe0 = ldrsbt r1, [r0], r2 3 | 0xd4,0x10,0xf0,0xe0 = ldrsbt r1, [r0], #4 4 | 0xf2,0x10,0xb0,0xe0 = ldrsht r1, [r0], r2 5 | 0xf4,0x10,0xf0,0xe0 = ldrsht r1, [r0], #4 6 | 0xb2,0x10,0xb0,0xe0 = ldrht r1, [r0], r2 7 | 0xb4,0x10,0xf0,0xe0 = ldrht r1, [r0], #4 8 | 0xb2,0x10,0xa0,0xe0 = strht r1, [r0], r2 9 | 0xb4,0x10,0xe0,0xe0 = strht r1, [r0], #4 10 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/arm_instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x1e,0xff,0x2f,0xe1 = bx lr 3 | 0xa0,0x0d,0xe1,0xf2 = vqdmull.s32 q8, d17, d16 4 | 0x03,0x10,0x02,0xe0 = and r1, r2, r3 5 | 0x03,0x10,0x12,0xe0 = ands r1, r2, r3 6 | 0x03,0x10,0x22,0xe0 = eor r1, r2, r3 7 | 0x03,0x10,0x32,0xe0 = eors r1, r2, r3 8 | 0x03,0x10,0x42,0xe0 = sub r1, r2, r3 9 | 0x03,0x10,0x52,0xe0 = subs r1, r2, r3 10 | 0x03,0x10,0x82,0xe0 = add r1, r2, r3 11 | 0x03,0x10,0x92,0xe0 = adds r1, r2, r3 12 | 0x03,0x10,0xa2,0xe0 = adc r1, r2, r3 13 | 0x03,0x10,0xc2,0xe1 = bic r1, r2, r3 14 | 0x03,0x10,0xd2,0xe1 = bics r1, r2, r3 15 | 0x02,0x10,0xa0,0xe1 = mov r1, r2 16 | 0x02,0x10,0xe0,0xe1 = mvn r1, r2 17 | 0x02,0x10,0xf0,0xe1 = mvns r1, r2 18 | 0x90,0x02,0xcb,0xe7 = bfi r0, r0, #5, #7 19 | 0x7a,0x00,0x20,0xe1 = bkpt #10 20 | 0x81,0x17,0x11,0xee = cdp p7, #1, c1, c1, c1, #4 21 | 0x81,0x17,0x11,0xfe = cdp2 p7, #1, c1, c1, c1, #4 22 | 0x13,0x14,0x82,0xe0 = add r1, r2, r3, lsl r4 23 | 0x30,0x0f,0xa6,0xe6 = ssat16 r0, #7, r0 24 | 0x00,0x00,0x0a,0xf1 = cpsie none, #0 25 | 0xb0,0x30,0x42,0xe1 = strh r3, [r2, #-0] 26 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/basic-arm-instructions-v8.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 2 | 0x59,0xf0,0x7f,0xf5 = dmb ishld 3 | 0x51,0xf0,0x7f,0xf5 = dmb oshld 4 | 0x55,0xf0,0x7f,0xf5 = dmb nshld 5 | 0x5d,0xf0,0x7f,0xf5 = dmb ld 6 | 0x49,0xf0,0x7f,0xf5 = dsb ishld 7 | 0x41,0xf0,0x7f,0xf5 = dsb oshld 8 | 0x45,0xf0,0x7f,0xf5 = dsb nshld 9 | 0x4d,0xf0,0x7f,0xf5 = dsb ld 10 | 0x05,0xf0,0x20,0xe3 = sevl 11 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/basic-thumb2-instructions-v8.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 2 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/crc32-thumb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 2 | 0xc1,0xfa,0x82,0xf0 = crc32b r0, r1, r2 3 | 0xc1,0xfa,0x92,0xf0 = crc32h r0, r1, r2 4 | 0xc1,0xfa,0xa2,0xf0 = crc32w r0, r1, r2 5 | 0xd1,0xfa,0x82,0xf0 = crc32cb r0, r1, r2 6 | 0xd1,0xfa,0x92,0xf0 = crc32ch r0, r1, r2 7 | 0xd1,0xfa,0xa2,0xf0 = crc32cw r0, r1, r2 8 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/crc32.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 2 | 0x42,0x00,0x01,0xe1 = crc32b r0, r1, r2 3 | 0x42,0x00,0x21,0xe1 = crc32h r0, r1, r2 4 | 0x42,0x00,0x41,0xe1 = crc32w r0, r1, r2 5 | 0x42,0x02,0x01,0xe1 = crc32cb r0, r1, r2 6 | 0x42,0x02,0x21,0xe1 = crc32ch r0, r1, r2 7 | 0x42,0x02,0x41,0xe1 = crc32cw r0, r1, r2 8 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/dot-req.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x05,0xb0,0xa0,0xe1 = mov r11, r5 3 | 0x06,0x10,0xa0,0xe1 = mov r1, r6 4 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/idiv-thumb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x92,0xfb,0xf3,0xf1 = sdiv r1, r2, r3 3 | 0xb4,0xfb,0xf5,0xf3 = udiv r3, r4, r5 4 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/idiv.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x12,0xf3,0x11,0xe7 = sdiv r1, r2, r3 3 | 0x14,0xf5,0x33,0xe7 = udiv r3, r4, r5 4 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/load-store-acquire-release-v8-thumb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 2 | 0xd4,0xe8,0xcf,0x3f = ldaexb r3, [r4] 3 | 0xd5,0xe8,0xdf,0x2f = ldaexh r2, [r5] 4 | 0xd7,0xe8,0xef,0x1f = ldaex r1, [r7] 5 | 0xd8,0xe8,0xff,0x67 = ldaexd r6, r7, [r8] 6 | 0xc4,0xe8,0xc1,0x3f = stlexb r1, r3, [r4] 7 | 0xc5,0xe8,0xd4,0x2f = stlexh r4, r2, [r5] 8 | 0xc7,0xe8,0xe2,0x1f = stlex r2, r1, [r7] 9 | 0xc8,0xe8,0xf6,0x23 = stlexd r6, r2, r3, [r8] 10 | 0xd6,0xe8,0xaf,0x5f = lda r5, [r6] 11 | 0xd6,0xe8,0x8f,0x5f = ldab r5, [r6] 12 | 0xd9,0xe8,0x9f,0xcf = ldah r12, [r9] 13 | 0xc0,0xe8,0xaf,0x3f = stl r3, [r0] 14 | 0xc1,0xe8,0x8f,0x2f = stlb r2, [r1] 15 | 0xc3,0xe8,0x9f,0x2f = stlh r2, [r3] 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/load-store-acquire-release-v8.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 2 | 0x9f,0x3e,0xd4,0xe1 = ldaexb r3, [r4] 3 | 0x9f,0x2e,0xf5,0xe1 = ldaexh r2, [r5] 4 | 0x9f,0x1e,0x97,0xe1 = ldaex r1, [r7] 5 | 0x9f,0x6e,0xb8,0xe1 = ldaexd r6, r7, [r8] 6 | 0x93,0x1e,0xc4,0xe1 = stlexb r1, r3, [r4] 7 | 0x92,0x4e,0xe5,0xe1 = stlexh r4, r2, [r5] 8 | 0x91,0x2e,0x87,0xe1 = stlex r2, r1, [r7] 9 | 0x92,0x6e,0xa8,0xe1 = stlexd r6, r2, r3, [r8] 10 | 0x9f,0x5c,0x96,0xe1 = lda r5, [r6] 11 | 0x9f,0x5c,0xd6,0xe1 = ldab r5, [r6] 12 | 0x9f,0xcc,0xf9,0xe1 = ldah r12, [r9] 13 | 0x93,0xfc,0x80,0xe1 = stl r3, [r0] 14 | 0x92,0xfc,0xc1,0xe1 = stlb r2, [r1] 15 | 0x92,0xfc,0xe3,0xe1 = stlh r2, [r3] 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/mode-switch.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x00,0xeb,0x01,0x00 = add.w r0, r0, r1 3 | 0x01,0x00,0x80,0xe0 = add r0, r0, r1 4 | 0x40,0x18 = adds r0, r0, r1 5 | 0x01,0x00,0x80,0xe0 = add r0, r0, r1 6 | 0x00,0xeb,0x01,0x00 = add.w r0, r0, r1 7 | 0x40,0x18 = adds r0, r0, r1 8 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neon-abs-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x20,0x03,0xf1,0xf3 = vabs.s8 d16, d16 3 | 0x20,0x03,0xf5,0xf3 = vabs.s16 d16, d16 4 | 0x20,0x03,0xf9,0xf3 = vabs.s32 d16, d16 5 | 0x20,0x07,0xf9,0xf3 = vabs.f32 d16, d16 6 | 0x60,0x03,0xf1,0xf3 = vabs.s8 q8, q8 7 | 0x60,0x03,0xf5,0xf3 = vabs.s16 q8, q8 8 | 0x60,0x03,0xf9,0xf3 = vabs.s32 q8, q8 9 | 0x60,0x07,0xf9,0xf3 = vabs.f32 q8, q8 10 | 0x20,0x07,0xf0,0xf3 = vqabs.s8 d16, d16 11 | 0x20,0x07,0xf4,0xf3 = vqabs.s16 d16, d16 12 | 0x20,0x07,0xf8,0xf3 = vqabs.s32 d16, d16 13 | 0x60,0x07,0xf0,0xf3 = vqabs.s8 q8, q8 14 | 0x60,0x07,0xf4,0xf3 = vqabs.s16 q8, q8 15 | 0x60,0x07,0xf8,0xf3 = vqabs.s32 q8, q8 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neon-bitcount-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x20,0x05,0xf0,0xf3 = vcnt.8 d16, d16 3 | 0x60,0x05,0xf0,0xf3 = vcnt.8 q8, q8 4 | 0xa0,0x04,0xf0,0xf3 = vclz.i8 d16, d16 5 | 0xa0,0x04,0xf4,0xf3 = vclz.i16 d16, d16 6 | 0xa0,0x04,0xf8,0xf3 = vclz.i32 d16, d16 7 | 0xe0,0x04,0xf0,0xf3 = vclz.i8 q8, q8 8 | 0xe0,0x04,0xf4,0xf3 = vclz.i16 q8, q8 9 | 0xe0,0x04,0xf8,0xf3 = vclz.i32 q8, q8 10 | 0x20,0x04,0xf0,0xf3 = vcls.s8 d16, d16 11 | 0x20,0x04,0xf4,0xf3 = vcls.s16 d16, d16 12 | 0x20,0x04,0xf8,0xf3 = vcls.s32 d16, d16 13 | 0x60,0x04,0xf0,0xf3 = vcls.s8 q8, q8 14 | 0x60,0x04,0xf4,0xf3 = vcls.s16 q8, q8 15 | 0x60,0x04,0xf8,0xf3 = vcls.s32 q8, q8 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neon-convert-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x20,0x07,0xfb,0xf3 = vcvt.s32.f32 d16, d16 3 | 0xa0,0x07,0xfb,0xf3 = vcvt.u32.f32 d16, d16 4 | 0x20,0x06,0xfb,0xf3 = vcvt.f32.s32 d16, d16 5 | 0xa0,0x06,0xfb,0xf3 = vcvt.f32.u32 d16, d16 6 | 0x60,0x07,0xfb,0xf3 = vcvt.s32.f32 q8, q8 7 | 0xe0,0x07,0xfb,0xf3 = vcvt.u32.f32 q8, q8 8 | 0x60,0x06,0xfb,0xf3 = vcvt.f32.s32 q8, q8 9 | 0xe0,0x06,0xfb,0xf3 = vcvt.f32.u32 q8, q8 10 | 0x30,0x0f,0xff,0xf2 = vcvt.s32.f32 d16, d16, #1 11 | 0x20,0x07,0xfb,0xf3 = vcvt.s32.f32 d16, d16 12 | 0x30,0x0f,0xff,0xf3 = vcvt.u32.f32 d16, d16, #1 13 | 0xa0,0x07,0xfb,0xf3 = vcvt.u32.f32 d16, d16 14 | 0x30,0x0e,0xff,0xf2 = vcvt.f32.s32 d16, d16, #1 15 | 0x20,0x06,0xfb,0xf3 = vcvt.f32.s32 d16, d16 16 | 0x30,0x0e,0xff,0xf3 = vcvt.f32.u32 d16, d16, #1 17 | 0xa0,0x06,0xfb,0xf3 = vcvt.f32.u32 d16, d16 18 | 0x70,0x0f,0xff,0xf2 = vcvt.s32.f32 q8, q8, #1 19 | 0x60,0x07,0xfb,0xf3 = vcvt.s32.f32 q8, q8 20 | 0x70,0x0f,0xff,0xf3 = vcvt.u32.f32 q8, q8, #1 21 | 0xe0,0x07,0xfb,0xf3 = vcvt.u32.f32 q8, q8 22 | 0x70,0x0e,0xff,0xf2 = vcvt.f32.s32 q8, q8, #1 23 | 0x60,0x06,0xfb,0xf3 = vcvt.f32.s32 q8, q8 24 | 0x70,0x0e,0xff,0xf3 = vcvt.f32.u32 q8, q8, #1 25 | 0xe0,0x06,0xfb,0xf3 = vcvt.f32.u32 q8, q8 26 | 0x20,0x07,0xf6,0xf3 = vcvt.f32.f16 q8, d16 27 | 0x20,0x06,0xf6,0xf3 = vcvt.f16.f32 d16, q8 28 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neon-crypto.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 2 | 0x42,0x03,0xb0,0xf3 = aesd.8 q0, q1 3 | 0x02,0x03,0xb0,0xf3 = aese.8 q0, q1 4 | 0xc2,0x03,0xb0,0xf3 = aesimc.8 q0, q1 5 | 0x82,0x03,0xb0,0xf3 = aesmc.8 q0, q1 6 | 0xc2,0x02,0xb9,0xf3 = sha1h.32 q0, q1 7 | 0x82,0x03,0xba,0xf3 = sha1su1.32 q0, q1 8 | 0xc2,0x03,0xba,0xf3 = sha256su0.32 q0, q1 9 | 0x44,0x0c,0x02,0xf2 = sha1c.32 q0, q1, q2 10 | 0x44,0x0c,0x22,0xf2 = sha1m.32 q0, q1, q2 11 | 0x44,0x0c,0x12,0xf2 = sha1p.32 q0, q1, q2 12 | 0x44,0x0c,0x32,0xf2 = sha1su0.32 q0, q1, q2 13 | 0x44,0x0c,0x02,0xf3 = sha256h.32 q0, q1, q2 14 | 0x44,0x0c,0x12,0xf3 = sha256h2.32 q0, q1, q2 15 | 0x44,0x0c,0x22,0xf3 = sha256su1.32 q0, q1, q2 16 | 0xa1,0x0e,0xe0,0xf2 = vmull.p64 q8, d16, d17 17 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neon-dup-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x90,0x0b,0xc0,0xee = vdup.8 d16, r0 3 | 0xb0,0x0b,0x80,0xee = vdup.16 d16, r0 4 | 0x90,0x0b,0x80,0xee = vdup.32 d16, r0 5 | 0x90,0x0b,0xe0,0xee = vdup.8 q8, r0 6 | 0xb0,0x0b,0xa0,0xee = vdup.16 q8, r0 7 | 0x90,0x0b,0xa0,0xee = vdup.32 q8, r0 8 | 0x20,0x0c,0xf3,0xf3 = vdup.8 d16, d16[1] 9 | 0x20,0x0c,0xf6,0xf3 = vdup.16 d16, d16[1] 10 | 0x20,0x0c,0xfc,0xf3 = vdup.32 d16, d16[1] 11 | 0x60,0x0c,0xf3,0xf3 = vdup.8 q8, d16[1] 12 | 0x60,0x0c,0xf6,0xf3 = vdup.16 q8, d16[1] 13 | 0x60,0x0c,0xfc,0xf3 = vdup.32 q8, d16[1] 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neon-neg-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0xa0,0x03,0xf1,0xf3 = vneg.s8 d16, d16 3 | 0xa0,0x03,0xf5,0xf3 = vneg.s16 d16, d16 4 | 0xa0,0x03,0xf9,0xf3 = vneg.s32 d16, d16 5 | 0xa0,0x07,0xf9,0xf3 = vneg.f32 d16, d16 6 | 0xe0,0x03,0xf1,0xf3 = vneg.s8 q8, q8 7 | 0xe0,0x03,0xf5,0xf3 = vneg.s16 q8, q8 8 | 0xe0,0x03,0xf9,0xf3 = vneg.s32 q8, q8 9 | 0xe0,0x07,0xf9,0xf3 = vneg.f32 q8, q8 10 | 0xa0,0x07,0xf0,0xf3 = vqneg.s8 d16, d16 11 | 0xa0,0x07,0xf4,0xf3 = vqneg.s16 d16, d16 12 | 0xa0,0x07,0xf8,0xf3 = vqneg.s32 d16, d16 13 | 0xe0,0x07,0xf0,0xf3 = vqneg.s8 q8, q8 14 | 0xe0,0x07,0xf4,0xf3 = vqneg.s16 q8, q8 15 | 0xe0,0x07,0xf8,0xf3 = vqneg.s32 q8, q8 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neon-reciprocal-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x20,0x04,0xfb,0xf3 = vrecpe.u32 d16, d16 3 | 0x60,0x04,0xfb,0xf3 = vrecpe.u32 q8, q8 4 | 0x20,0x05,0xfb,0xf3 = vrecpe.f32 d16, d16 5 | 0x60,0x05,0xfb,0xf3 = vrecpe.f32 q8, q8 6 | 0xb1,0x0f,0x40,0xf2 = vrecps.f32 d16, d16, d17 7 | 0xf2,0x0f,0x40,0xf2 = vrecps.f32 q8, q8, q9 8 | 0xa0,0x04,0xfb,0xf3 = vrsqrte.u32 d16, d16 9 | 0xe0,0x04,0xfb,0xf3 = vrsqrte.u32 q8, q8 10 | 0xa0,0x05,0xfb,0xf3 = vrsqrte.f32 d16, d16 11 | 0xe0,0x05,0xfb,0xf3 = vrsqrte.f32 q8, q8 12 | 0xb1,0x0f,0x60,0xf2 = vrsqrts.f32 d16, d16, d17 13 | 0xf2,0x0f,0x60,0xf2 = vrsqrts.f32 q8, q8, q9 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neon-reverse-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x20,0x00,0xf0,0xf3 = vrev64.8 d16, d16 3 | 0x20,0x00,0xf4,0xf3 = vrev64.16 d16, d16 4 | 0x20,0x00,0xf8,0xf3 = vrev64.32 d16, d16 5 | 0x60,0x00,0xf0,0xf3 = vrev64.8 q8, q8 6 | 0x60,0x00,0xf4,0xf3 = vrev64.16 q8, q8 7 | 0x60,0x00,0xf8,0xf3 = vrev64.32 q8, q8 8 | 0xa0,0x00,0xf0,0xf3 = vrev32.8 d16, d16 9 | 0xa0,0x00,0xf4,0xf3 = vrev32.16 d16, d16 10 | 0xe0,0x00,0xf0,0xf3 = vrev32.8 q8, q8 11 | 0xe0,0x00,0xf4,0xf3 = vrev32.16 q8, q8 12 | 0x20,0x01,0xf0,0xf3 = vrev16.8 d16, d16 13 | 0x60,0x01,0xf0,0xf3 = vrev16.8 q8, q8 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neon-table-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0xa0,0x08,0xf1,0xf3 = vtbl.8 d16, {d17}, d16 3 | 0xa2,0x09,0xf0,0xf3 = vtbl.8 d16, {d16, d17}, d18 4 | 0xa4,0x0a,0xf0,0xf3 = vtbl.8 d16, {d16, d17, d18}, d20 5 | 0xa4,0x0b,0xf0,0xf3 = vtbl.8 d16, {d16, d17, d18, d19}, d20 6 | 0xe1,0x28,0xf0,0xf3 = vtbx.8 d18, {d16}, d17 7 | 0xe2,0x39,0xf0,0xf3 = vtbx.8 d19, {d16, d17}, d18 8 | 0xe5,0x4a,0xf0,0xf3 = vtbx.8 d20, {d16, d17, d18}, d21 9 | 0xe5,0x4b,0xf0,0xf3 = vtbx.8 d20, {d16, d17, d18, d19}, d21 10 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neon-vswp.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x02,0x10,0xb2,0xf3 = vswp d1, d2 3 | 0x44,0x20,0xb2,0xf3 = vswp q1, q2 4 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neont2-abs-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xf1,0xff,0x20,0x03 = vabs.s8 d16, d16 3 | 0xf5,0xff,0x20,0x03 = vabs.s16 d16, d16 4 | 0xf9,0xff,0x20,0x03 = vabs.s32 d16, d16 5 | 0xf9,0xff,0x20,0x07 = vabs.f32 d16, d16 6 | 0xf1,0xff,0x60,0x03 = vabs.s8 q8, q8 7 | 0xf5,0xff,0x60,0x03 = vabs.s16 q8, q8 8 | 0xf9,0xff,0x60,0x03 = vabs.s32 q8, q8 9 | 0xf9,0xff,0x60,0x07 = vabs.f32 q8, q8 10 | 0xf0,0xff,0x20,0x07 = vqabs.s8 d16, d16 11 | 0xf4,0xff,0x20,0x07 = vqabs.s16 d16, d16 12 | 0xf8,0xff,0x20,0x07 = vqabs.s32 d16, d16 13 | 0xf0,0xff,0x60,0x07 = vqabs.s8 q8, q8 14 | 0xf4,0xff,0x60,0x07 = vqabs.s16 q8, q8 15 | 0xf8,0xff,0x60,0x07 = vqabs.s32 q8, q8 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neont2-bitcount-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xf0,0xff,0x20,0x05 = vcnt.8 d16, d16 3 | 0xf0,0xff,0x60,0x05 = vcnt.8 q8, q8 4 | 0xf0,0xff,0xa0,0x04 = vclz.i8 d16, d16 5 | 0xf4,0xff,0xa0,0x04 = vclz.i16 d16, d16 6 | 0xf8,0xff,0xa0,0x04 = vclz.i32 d16, d16 7 | 0xf0,0xff,0xe0,0x04 = vclz.i8 q8, q8 8 | 0xf4,0xff,0xe0,0x04 = vclz.i16 q8, q8 9 | 0xf8,0xff,0xe0,0x04 = vclz.i32 q8, q8 10 | 0xf0,0xff,0x20,0x04 = vcls.s8 d16, d16 11 | 0xf4,0xff,0x20,0x04 = vcls.s16 d16, d16 12 | 0xf8,0xff,0x20,0x04 = vcls.s32 d16, d16 13 | 0xf0,0xff,0x60,0x04 = vcls.s8 q8, q8 14 | 0xf4,0xff,0x60,0x04 = vcls.s16 q8, q8 15 | 0xf8,0xff,0x60,0x04 = vcls.s32 q8, q8 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neont2-bitwise-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0x41,0xef,0xb0,0x01 = vand d16, d17, d16 3 | 0x40,0xef,0xf2,0x01 = vand q8, q8, q9 4 | 0x41,0xff,0xb0,0x01 = veor d16, d17, d16 5 | 0x40,0xff,0xf2,0x01 = veor q8, q8, q9 6 | 0x61,0xef,0xb0,0x01 = vorr d16, d17, d16 7 | 0x60,0xef,0xf2,0x01 = vorr q8, q8, q9 8 | 0x51,0xef,0xb0,0x01 = vbic d16, d17, d16 9 | 0x50,0xef,0xf2,0x01 = vbic q8, q8, q9 10 | 0x71,0xef,0xb0,0x01 = vorn d16, d17, d16 11 | 0x70,0xef,0xf2,0x01 = vorn q8, q8, q9 12 | 0xf0,0xff,0xa0,0x05 = vmvn d16, d16 13 | 0xf0,0xff,0xe0,0x05 = vmvn q8, q8 14 | 0x51,0xff,0xb0,0x21 = vbsl d18, d17, d16 15 | 0x54,0xff,0xf2,0x01 = vbsl q8, q10, q9 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neont2-cmp-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xfb,0xff,0x20,0x07 = vcvt.s32.f32 d16, d16 3 | 0xfb,0xff,0xa0,0x07 = vcvt.u32.f32 d16, d16 4 | 0xfb,0xff,0x20,0x06 = vcvt.f32.s32 d16, d16 5 | 0xfb,0xff,0xa0,0x06 = vcvt.f32.u32 d16, d16 6 | 0xfb,0xff,0x60,0x07 = vcvt.s32.f32 q8, q8 7 | 0xfb,0xff,0xe0,0x07 = vcvt.u32.f32 q8, q8 8 | 0xfb,0xff,0x60,0x06 = vcvt.f32.s32 q8, q8 9 | 0xfb,0xff,0xe0,0x06 = vcvt.f32.u32 q8, q8 10 | 0xff,0xef,0x30,0x0f = vcvt.s32.f32 d16, d16, #1 11 | 0xff,0xff,0x30,0x0f = vcvt.u32.f32 d16, d16, #1 12 | 0xff,0xef,0x30,0x0e = vcvt.f32.s32 d16, d16, #1 13 | 0xff,0xff,0x30,0x0e = vcvt.f32.u32 d16, d16, #1 14 | 0xff,0xef,0x70,0x0f = vcvt.s32.f32 q8, q8, #1 15 | 0xff,0xff,0x70,0x0f = vcvt.u32.f32 q8, q8, #1 16 | 0xff,0xef,0x70,0x0e = vcvt.f32.s32 q8, q8, #1 17 | 0xff,0xff,0x70,0x0e = vcvt.f32.u32 q8, q8, #1 18 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neont2-convert-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xfb,0xff,0x20,0x07 = vcvt.s32.f32 d16, d16 3 | 0xfb,0xff,0xa0,0x07 = vcvt.u32.f32 d16, d16 4 | 0xfb,0xff,0x20,0x06 = vcvt.f32.s32 d16, d16 5 | 0xfb,0xff,0xa0,0x06 = vcvt.f32.u32 d16, d16 6 | 0xfb,0xff,0x60,0x07 = vcvt.s32.f32 q8, q8 7 | 0xfb,0xff,0xe0,0x07 = vcvt.u32.f32 q8, q8 8 | 0xfb,0xff,0x60,0x06 = vcvt.f32.s32 q8, q8 9 | 0xfb,0xff,0xe0,0x06 = vcvt.f32.u32 q8, q8 10 | 0xff,0xef,0x30,0x0f = vcvt.s32.f32 d16, d16, #1 11 | 0xff,0xff,0x30,0x0f = vcvt.u32.f32 d16, d16, #1 12 | 0xff,0xef,0x30,0x0e = vcvt.f32.s32 d16, d16, #1 13 | 0xff,0xff,0x30,0x0e = vcvt.f32.u32 d16, d16, #1 14 | 0xff,0xef,0x70,0x0f = vcvt.s32.f32 q8, q8, #1 15 | 0xff,0xff,0x70,0x0f = vcvt.u32.f32 q8, q8, #1 16 | 0xff,0xef,0x70,0x0e = vcvt.f32.s32 q8, q8, #1 17 | 0xff,0xff,0x70,0x0e = vcvt.f32.u32 q8, q8, #1 18 | 0xf6,0xff,0x20,0x07 = vcvt.f32.f16 q8, d16 19 | 0xf6,0xff,0x20,0x06 = vcvt.f16.f32 d16, q8 20 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neont2-dup-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xc0,0xee,0x90,0x1b = vdup.8 d16, r1 3 | 0x8f,0xee,0x30,0x2b = vdup.16 d15, r2 4 | 0x8e,0xee,0x10,0x3b = vdup.32 d14, r3 5 | 0xe2,0xee,0x90,0x4b = vdup.8 q9, r4 6 | 0xa0,0xee,0xb0,0x5b = vdup.16 q8, r5 7 | 0xae,0xee,0x10,0x6b = vdup.32 q7, r6 8 | 0xf1,0xff,0x0b,0x0c = vdup.8 d16, d11[0] 9 | 0xf2,0xff,0x0c,0x1c = vdup.16 d17, d12[0] 10 | 0xf4,0xff,0x0d,0x2c = vdup.32 d18, d13[0] 11 | 0xb1,0xff,0x4a,0x6c = vdup.8 q3, d10[0] 12 | 0xf2,0xff,0x49,0x2c = vdup.16 q9, d9[0] 13 | 0xf4,0xff,0x48,0x0c = vdup.32 q8, d8[0] 14 | 0xf3,0xff,0x0b,0x0c = vdup.8 d16, d11[1] 15 | 0xf6,0xff,0x0c,0x1c = vdup.16 d17, d12[1] 16 | 0xfc,0xff,0x0d,0x2c = vdup.32 d18, d13[1] 17 | 0xb3,0xff,0x4a,0x6c = vdup.8 q3, d10[1] 18 | 0xf6,0xff,0x49,0x2c = vdup.16 q9, d9[1] 19 | 0xfc,0xff,0x48,0x0c = vdup.32 q8, d8[1] 20 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neont2-neg-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xf1,0xff,0xa0,0x03 = vneg.s8 d16, d16 3 | 0xf5,0xff,0xa0,0x03 = vneg.s16 d16, d16 4 | 0xf9,0xff,0xa0,0x03 = vneg.s32 d16, d16 5 | 0xf9,0xff,0xa0,0x07 = vneg.f32 d16, d16 6 | 0xf1,0xff,0xe0,0x03 = vneg.s8 q8, q8 7 | 0xf5,0xff,0xe0,0x03 = vneg.s16 q8, q8 8 | 0xf9,0xff,0xe0,0x03 = vneg.s32 q8, q8 9 | 0xf9,0xff,0xe0,0x07 = vneg.f32 q8, q8 10 | 0xf0,0xff,0xa0,0x07 = vqneg.s8 d16, d16 11 | 0xf4,0xff,0xa0,0x07 = vqneg.s16 d16, d16 12 | 0xf8,0xff,0xa0,0x07 = vqneg.s32 d16, d16 13 | 0xf0,0xff,0xe0,0x07 = vqneg.s8 q8, q8 14 | 0xf4,0xff,0xe0,0x07 = vqneg.s16 q8, q8 15 | 0xf8,0xff,0xe0,0x07 = vqneg.s32 q8, q8 16 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neont2-reciprocal-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xfb,0xff,0x20,0x04 = vrecpe.u32 d16, d16 3 | 0xfb,0xff,0x60,0x04 = vrecpe.u32 q8, q8 4 | 0xfb,0xff,0x20,0x05 = vrecpe.f32 d16, d16 5 | 0xfb,0xff,0x60,0x05 = vrecpe.f32 q8, q8 6 | 0x40,0xef,0xb1,0x0f = vrecps.f32 d16, d16, d17 7 | 0x40,0xef,0xf2,0x0f = vrecps.f32 q8, q8, q9 8 | 0xfb,0xff,0xa0,0x04 = vrsqrte.u32 d16, d16 9 | 0xfb,0xff,0xe0,0x04 = vrsqrte.u32 q8, q8 10 | 0xfb,0xff,0xa0,0x05 = vrsqrte.f32 d16, d16 11 | 0xfb,0xff,0xe0,0x05 = vrsqrte.f32 q8, q8 12 | 0x60,0xef,0xb1,0x0f = vrsqrts.f32 d16, d16, d17 13 | 0x60,0xef,0xf2,0x0f = vrsqrts.f32 q8, q8, q9 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neont2-reverse-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xf0,0xff,0x20,0x00 = vrev64.8 d16, d16 3 | 0xf4,0xff,0x20,0x00 = vrev64.16 d16, d16 4 | 0xf8,0xff,0x20,0x00 = vrev64.32 d16, d16 5 | 0xf0,0xff,0x60,0x00 = vrev64.8 q8, q8 6 | 0xf4,0xff,0x60,0x00 = vrev64.16 q8, q8 7 | 0xf8,0xff,0x60,0x00 = vrev64.32 q8, q8 8 | 0xf0,0xff,0xa0,0x00 = vrev32.8 d16, d16 9 | 0xf4,0xff,0xa0,0x00 = vrev32.16 d16, d16 10 | 0xf0,0xff,0xe0,0x00 = vrev32.8 q8, q8 11 | 0xf4,0xff,0xe0,0x00 = vrev32.16 q8, q8 12 | 0xf0,0xff,0x20,0x01 = vrev16.8 d16, d16 13 | 0xf0,0xff,0x60,0x01 = vrev16.8 q8, q8 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neont2-shuffle-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xf1,0xef,0xa0,0x03 = vext.8 d16, d17, d16, #3 3 | 0xf1,0xef,0xa0,0x05 = vext.8 d16, d17, d16, #5 4 | 0xf2,0xef,0xe0,0x03 = vext.8 q8, q9, q8, #3 5 | 0xf2,0xef,0xe0,0x07 = vext.8 q8, q9, q8, #7 6 | 0xf1,0xef,0xa0,0x06 = vext.16 d16, d17, d16, #3 7 | 0xf2,0xef,0xe0,0x0c = vext.32 q8, q9, q8, #3 8 | 0xf2,0xff,0xa0,0x10 = vtrn.8 d17, d16 9 | 0xf6,0xff,0xa0,0x10 = vtrn.16 d17, d16 10 | 0xfa,0xff,0xa0,0x10 = vtrn.32 d17, d16 11 | 0xf2,0xff,0xe0,0x20 = vtrn.8 q9, q8 12 | 0xf6,0xff,0xe0,0x20 = vtrn.16 q9, q8 13 | 0xfa,0xff,0xe0,0x20 = vtrn.32 q9, q8 14 | 0xf2,0xff,0x20,0x11 = vuzp.8 d17, d16 15 | 0xf6,0xff,0x20,0x11 = vuzp.16 d17, d16 16 | 0xf2,0xff,0x60,0x21 = vuzp.8 q9, q8 17 | 0xf6,0xff,0x60,0x21 = vuzp.16 q9, q8 18 | 0xfa,0xff,0x60,0x21 = vuzp.32 q9, q8 19 | 0xf2,0xff,0xa0,0x11 = vzip.8 d17, d16 20 | 0xf6,0xff,0xa0,0x11 = vzip.16 d17, d16 21 | 0xf2,0xff,0xe0,0x21 = vzip.8 q9, q8 22 | 0xf6,0xff,0xe0,0x21 = vzip.16 q9, q8 23 | 0xfa,0xff,0xe0,0x21 = vzip.32 q9, q8 24 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neont2-sub-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xf1,0xef,0xa0,0x03 = vext.8 d16, d17, d16, #3 3 | 0xf1,0xef,0xa0,0x05 = vext.8 d16, d17, d16, #5 4 | 0xf2,0xef,0xe0,0x03 = vext.8 q8, q9, q8, #3 5 | 0xf2,0xef,0xe0,0x07 = vext.8 q8, q9, q8, #7 6 | 0xf1,0xef,0xa0,0x06 = vext.16 d16, d17, d16, #3 7 | 0xf2,0xef,0xe0,0x0c = vext.32 q8, q9, q8, #3 8 | 0xf2,0xff,0xa0,0x10 = vtrn.8 d17, d16 9 | 0xf6,0xff,0xa0,0x10 = vtrn.16 d17, d16 10 | 0xfa,0xff,0xa0,0x10 = vtrn.32 d17, d16 11 | 0xf2,0xff,0xe0,0x20 = vtrn.8 q9, q8 12 | 0xf6,0xff,0xe0,0x20 = vtrn.16 q9, q8 13 | 0xfa,0xff,0xe0,0x20 = vtrn.32 q9, q8 14 | 0xf2,0xff,0x20,0x11 = vuzp.8 d17, d16 15 | 0xf6,0xff,0x20,0x11 = vuzp.16 d17, d16 16 | 0xf2,0xff,0x60,0x21 = vuzp.8 q9, q8 17 | 0xf6,0xff,0x60,0x21 = vuzp.16 q9, q8 18 | 0xfa,0xff,0x60,0x21 = vuzp.32 q9, q8 19 | 0xf2,0xff,0xa0,0x11 = vzip.8 d17, d16 20 | 0xf6,0xff,0xa0,0x11 = vzip.16 d17, d16 21 | 0xf2,0xff,0xe0,0x21 = vzip.8 q9, q8 22 | 0xf6,0xff,0xe0,0x21 = vzip.16 q9, q8 23 | 0xfa,0xff,0xe0,0x21 = vzip.32 q9, q8 24 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/neont2-table-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, None 2 | 0xf1,0xff,0xa0,0x08 = vtbl.8 d16, {d17}, d16 3 | 0xf0,0xff,0xa2,0x09 = vtbl.8 d16, {d16, d17}, d18 4 | 0xf0,0xff,0xa4,0x0a = vtbl.8 d16, {d16, d17, d18}, d20 5 | 0xf0,0xff,0xa4,0x0b = vtbl.8 d16, {d16, d17, d18, d19}, d20 6 | 0xf0,0xff,0xe1,0x28 = vtbx.8 d18, {d16}, d17 7 | 0xf0,0xff,0xe2,0x39 = vtbx.8 d19, {d16, d17}, d18 8 | 0xf0,0xff,0xe5,0x4a = vtbx.8 d20, {d16, d17, d18}, d21 9 | 0xf0,0xff,0xe5,0x4b = vtbx.8 d20, {d16, d17, d18, d19}, d21 10 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/thumb-hints.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, 2 | 0x00,0xbf = nop 3 | 0x10,0xbf = yield 4 | 0x20,0xbf = wfe 5 | 0x30,0xbf = wfi 6 | 0x40,0xbf = sev 7 | 0xbf,0xf3,0x5f,0x8f = dmb sy 8 | 0xbf,0xf3,0x5f,0x8f = dmb sy 9 | 0xbf,0xf3,0x4f,0x8f = dsb sy 10 | 0xbf,0xf3,0x4f,0x8f = dsb sy 11 | 0xbf,0xf3,0x6f,0x8f = isb sy 12 | 0xbf,0xf3,0x6f,0x8f = isb sy 13 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/thumb-neon-crypto.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 2 | 0xb0,0xff,0x42,0x03 = aesd.8 q0, q1 3 | 0xb0,0xff,0x02,0x03 = aese.8 q0, q1 4 | 0xb0,0xff,0xc2,0x03 = aesimc.8 q0, q1 5 | 0xb0,0xff,0x82,0x03 = aesmc.8 q0, q1 6 | 0xb9,0xff,0xc2,0x02 = sha1h.32 q0, q1 7 | 0xba,0xff,0x82,0x03 = sha1su1.32 q0, q1 8 | 0xba,0xff,0xc2,0x03 = sha256su0.32 q0, q1 9 | 0x02,0xef,0x44,0x0c = sha1c.32 q0, q1, q2 10 | 0x22,0xef,0x44,0x0c = sha1m.32 q0, q1, q2 11 | 0x12,0xef,0x44,0x0c = sha1p.32 q0, q1, q2 12 | 0x32,0xef,0x44,0x0c = sha1su0.32 q0, q1, q2 13 | 0x02,0xff,0x44,0x0c = sha256h.32 q0, q1, q2 14 | 0x12,0xff,0x44,0x0c = sha256h2.32 q0, q1, q2 15 | 0x22,0xff,0x44,0x0c = sha256su1.32 q0, q1, q2 16 | 0xe0,0xef,0xa1,0x0e = vmull.p64 q8, d16, d17 17 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/thumb-shift-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, 2 | 0x6e,0xeb,0x00,0x0c = sbc.w r12, lr, r0 3 | 0x68,0xeb,0x19,0x01 = sbc.w r1, r8, r9, lsr #32 4 | 0x67,0xeb,0x1f,0x42 = sbc.w r2, r7, pc, lsr #16 5 | 0x66,0xeb,0x0a,0x03 = sbc.w r3, r6, r10 6 | 0x65,0xeb,0x0e,0x44 = sbc.w r4, r5, lr, lsl #16 7 | 0x64,0xeb,0x2b,0x05 = sbc.w r5, r4, r11, asr #32 8 | 0x63,0xeb,0x2d,0x46 = sbc.w r6, r3, sp, asr #16 9 | 0x62,0xeb,0x3c,0x07 = sbc.w r7, r2, r12, rrx 10 | 0x61,0xeb,0x30,0x48 = sbc.w r8, r1, r0, ror #16 11 | 0x0e,0xea,0x00,0x0c = and.w r12, lr, r0 12 | 0x08,0xea,0x19,0x01 = and.w r1, r8, r9, lsr #32 13 | 0x07,0xea,0x1f,0x42 = and.w r2, r7, pc, lsr #16 14 | 0x06,0xea,0x0a,0x03 = and.w r3, r6, r10 15 | 0x05,0xea,0x0e,0x44 = and.w r4, r5, lr, lsl #16 16 | 0x04,0xea,0x2b,0x05 = and.w r5, r4, r11, asr #32 17 | 0x03,0xea,0x2d,0x46 = and.w r6, r3, sp, asr #16 18 | 0x02,0xea,0x3c,0x07 = and.w r7, r2, r12, rrx 19 | 0x01,0xea,0x30,0x48 = and.w r8, r1, r0, ror #16 20 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/thumb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, 2 | 0x91,0x42 = cmp r1, r2 3 | 0x16,0xbc = pop {r1, r2, r4} 4 | 0xfe,0xde = trap 5 | 0xc8,0x47 = blx r9 6 | 0xd0,0x47 = blx r10 7 | 0x1a,0xba = rev r2, r3 8 | 0x63,0xba = rev16 r3, r4 9 | 0xf5,0xba = revsh r5, r6 10 | 0x5a,0xb2 = sxtb r2, r3 11 | 0x1a,0xb2 = sxth r2, r3 12 | 0x2c,0x42 = tst r4, r5 13 | 0xf3,0xb2 = uxtb r3, r6 14 | 0xb3,0xb2 = uxth r3, r6 15 | 0x8b,0x58 = ldr r3, [r1, r2] 16 | 0x02,0xbe = bkpt #2 17 | 0xc0,0x46 = mov r8, r8 18 | 0x67,0xb6 = cpsie aif 19 | 0x78,0x46 = mov r0, pc 20 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/thumb2-b.w-encodingT4.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, 2 | 0x36,0xf0,0x06,0xbc = b.w #223244 3 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/thumb2-pldw.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, 2 | 0xb0,0xf8,0x01,0xf1 = pldw [r0, #257] 3 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/vfp4-thumb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, 2 | 0xe2,0xee,0xa1,0x0b = vfma.f64 d16, d18, d17 3 | 0xa2,0xee,0x00,0x1a = vfma.f32 s2, s4, s0 4 | 0x42,0xef,0xb1,0x0c = vfma.f32 d16, d18, d17 5 | 0x08,0xef,0x50,0x4c = vfma.f32 q2, q4, q0 6 | 0xd2,0xee,0xe1,0x0b = vfnma.f64 d16, d18, d17 7 | 0x92,0xee,0x40,0x1a = vfnma.f32 s2, s4, s0 8 | 0xe2,0xee,0xe1,0x0b = vfms.f64 d16, d18, d17 9 | 0xa2,0xee,0x40,0x1a = vfms.f32 s2, s4, s0 10 | 0x62,0xef,0xb1,0x0c = vfms.f32 d16, d18, d17 11 | 0x28,0xef,0x50,0x4c = vfms.f32 q2, q4, q0 12 | 0xd2,0xee,0xa1,0x0b = vfnms.f64 d16, d18, d17 13 | 0x92,0xee,0x00,0x1a = vfnms.f32 s2, s4, s0 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/vfp4.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0xa1,0x0b,0xe2,0xee = vfma.f64 d16, d18, d17 3 | 0x00,0x1a,0xa2,0xee = vfma.f32 s2, s4, s0 4 | 0xb1,0x0c,0x42,0xf2 = vfma.f32 d16, d18, d17 5 | 0x50,0x4c,0x08,0xf2 = vfma.f32 q2, q4, q0 6 | 0xe1,0x0b,0xd2,0xee = vfnma.f64 d16, d18, d17 7 | 0x40,0x1a,0x92,0xee = vfnma.f32 s2, s4, s0 8 | 0xe1,0x0b,0xe2,0xee = vfms.f64 d16, d18, d17 9 | 0x40,0x1a,0xa2,0xee = vfms.f32 s2, s4, s0 10 | 0xb1,0x0c,0x62,0xf2 = vfms.f32 d16, d18, d17 11 | 0x50,0x4c,0x28,0xf2 = vfms.f32 q2, q4, q0 12 | 0xa1,0x0b,0xd2,0xee = vfnms.f64 d16, d18, d17 13 | 0x00,0x1a,0x92,0xee = vfnms.f32 s2, s4, s0 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/vpush-vpop-thumb.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_THUMB, 2 | 0x2d,0xed,0x0a,0x8b = vpush {d8, d9, d10, d11, d12} 3 | 0x2d,0xed,0x05,0x4a = vpush {s8, s9, s10, s11, s12} 4 | 0xbd,0xec,0x0a,0x8b = vpop {d8, d9, d10, d11, d12} 5 | 0xbd,0xec,0x05,0x4a = vpop {s8, s9, s10, s11, s12} 6 | 0x2d,0xed,0x0a,0x8b = vpush {d8, d9, d10, d11, d12} 7 | 0x2d,0xed,0x05,0x4a = vpush {s8, s9, s10, s11, s12} 8 | 0xbd,0xec,0x0a,0x8b = vpop {d8, d9, d10, d11, d12} 9 | 0xbd,0xec,0x05,0x4a = vpop {s8, s9, s10, s11, s12} 10 | -------------------------------------------------------------------------------- /capstone/suite/MC/ARM/vpush-vpop.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_ARM, CS_MODE_ARM, None 2 | 0x0a,0x8b,0x2d,0xed = vpush {d8, d9, d10, d11, d12} 3 | 0x05,0x4a,0x2d,0xed = vpush {s8, s9, s10, s11, s12} 4 | 0x0a,0x8b,0xbd,0xec = vpop {d8, d9, d10, d11, d12} 5 | 0x05,0x4a,0xbd,0xec = vpop {s8, s9, s10, s11, s12} 6 | 0x0a,0x8b,0x2d,0xed = vpush {d8, d9, d10, d11, d12} 7 | 0x05,0x4a,0x2d,0xed = vpush {s8, s9, s10, s11, s12} 8 | 0x0a,0x8b,0xbd,0xec = vpop {d8, d9, d10, d11, d12} 9 | 0x05,0x4a,0xbd,0xec = vpop {s8, s9, s10, s11, s12} 10 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/hilo-addressing.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x3c,0x04,0xde,0xae = lui $4, %hi(addr) 3 | 0x03,0xe0,0x00,0x08 = jr $31 4 | 0x80,0x82,0xbe,0xef = lb $2, %lo(addr)($4) 5 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-alu-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO, None 2 | 0x00,0xe6,0x49,0x10 = add $9, $6, $7 3 | 0x11,0x26,0x45,0x67 = addi $9, $6, 17767 4 | 0x31,0x26,0xc5,0x67 = addiu $9, $6, -15001 5 | 0x11,0x26,0x45,0x67 = addi $9, $6, 17767 6 | 0x31,0x26,0xc5,0x67 = addiu $9, $6, -15001 7 | 0x00,0xe6,0x49,0x50 = addu $9, $6, $7 8 | 0x00,0xe6,0x49,0x90 = sub $9, $6, $7 9 | 0x00,0xa3,0x21,0xd0 = subu $4, $3, $5 10 | 0x00,0xe0,0x31,0x90 = neg $6, $7 11 | 0x00,0xe0,0x31,0xd0 = negu $6, $7 12 | 0x00,0x08,0x39,0x50 = move $7, $8 13 | 0x00,0xa3,0x1b,0x50 = slt $3, $3, $5 14 | 0x90,0x63,0x00,0x67 = slti $3, $3, 103 15 | 0x90,0x63,0x00,0x67 = slti $3, $3, 103 16 | 0xb0,0x63,0x00,0x67 = sltiu $3, $3, 103 17 | 0x00,0xa3,0x1b,0x90 = sltu $3, $3, $5 18 | 0x41,0xa9,0x45,0x67 = lui $9, 17767 19 | 0x00,0xe6,0x4a,0x50 = and $9, $6, $7 20 | 0xd1,0x26,0x45,0x67 = andi $9, $6, 17767 21 | 0xd1,0x26,0x45,0x67 = andi $9, $6, 17767 22 | 0x00,0xa4,0x1a,0x90 = or $3, $4, $5 23 | 0x51,0x26,0x45,0x67 = ori $9, $6, 17767 24 | 0x00,0xa3,0x1b,0x10 = xor $3, $3, $5 25 | 0x71,0x26,0x45,0x67 = xori $9, $6, 17767 26 | 0x71,0x26,0x45,0x67 = xori $9, $6, 17767 27 | 0x00,0xe6,0x4a,0xd0 = nor $9, $6, $7 28 | 0x00,0x08,0x3a,0xd0 = not $7, $8 29 | 0x00,0xe6,0x4a,0x10 = mul $9, $6, $7 30 | 0x00,0xe9,0x8b,0x3c = mult $9, $7 31 | 0x00,0xe9,0x9b,0x3c = multu $9, $7 32 | 0x00,0xe9,0xab,0x3c = div $zero, $9, $7 33 | 0x00,0xe9,0xbb,0x3c = divu $zero, $9, $7 34 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-alu-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0xe6,0x00,0x10,0x49 = add $9, $6, $7 3 | 0x26,0x11,0x67,0x45 = addi $9, $6, 17767 4 | 0x26,0x31,0x67,0xc5 = addiu $9, $6, -15001 5 | 0x26,0x11,0x67,0x45 = addi $9, $6, 17767 6 | 0x26,0x31,0x67,0xc5 = addiu $9, $6, -15001 7 | 0xe6,0x00,0x50,0x49 = addu $9, $6, $7 8 | 0xe6,0x00,0x90,0x49 = sub $9, $6, $7 9 | 0xa3,0x00,0xd0,0x21 = subu $4, $3, $5 10 | 0xe0,0x00,0x90,0x31 = neg $6, $7 11 | 0xe0,0x00,0xd0,0x31 = negu $6, $7 12 | 0x08,0x00,0x50,0x39 = move $7, $8 13 | 0xa3,0x00,0x50,0x1b = slt $3, $3, $5 14 | 0x63,0x90,0x67,0x00 = slti $3, $3, 103 15 | 0x63,0x90,0x67,0x00 = slti $3, $3, 103 16 | 0x63,0xb0,0x67,0x00 = sltiu $3, $3, 103 17 | 0xa3,0x00,0x90,0x1b = sltu $3, $3, $5 18 | 0xa9,0x41,0x67,0x45 = lui $9, 17767 19 | 0xe6,0x00,0x50,0x4a = and $9, $6, $7 20 | 0x26,0xd1,0x67,0x45 = andi $9, $6, 17767 21 | 0x26,0xd1,0x67,0x45 = andi $9, $6, 17767 22 | 0xa4,0x00,0x90,0x1a = or $3, $4, $5 23 | 0x26,0x51,0x67,0x45 = ori $9, $6, 17767 24 | 0xa3,0x00,0x10,0x1b = xor $3, $3, $5 25 | 0x26,0x71,0x67,0x45 = xori $9, $6, 17767 26 | 0x26,0x71,0x67,0x45 = xori $9, $6, 17767 27 | 0xe6,0x00,0xd0,0x4a = nor $9, $6, $7 28 | 0x08,0x00,0xd0,0x3a = not $7, $8 29 | 0xe6,0x00,0x10,0x4a = mul $9, $6, $7 30 | 0xe9,0x00,0x3c,0x8b = mult $9, $7 31 | 0xe9,0x00,0x3c,0x9b = multu $9, $7 32 | 0xe9,0x00,0x3c,0xab = div $zero, $9, $7 33 | 0xe9,0x00,0x3c,0xbb = divu $zero, $9, $7 34 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-branch-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x94,0x00,0x02,0x9a = b 1332 3 | 0x94,0xc9,0x02,0x9a = beq $9, $6, 1332 4 | 0x40,0x46,0x02,0x9a = bgez $6, 1332 5 | 0x40,0x66,0x02,0x9a = bgezal $6, 1332 6 | 0x40,0x26,0x02,0x9a = bltzal $6, 1332 7 | 0x40,0xc6,0x02,0x9a = bgtz $6, 1332 8 | 0x40,0x86,0x02,0x9a = blez $6, 1332 9 | 0xb4,0xc9,0x02,0x9a = bne $9, $6, 1332 10 | 0x40,0x60,0x02,0x9a = bal 1332 11 | 0x40,0x06,0x02,0x9a = bltz $6, 1332 12 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-branch-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0x00,0x94,0x9a,0x02 = b 1332 3 | 0xc9,0x94,0x9a,0x02 = beq $9, $6, 1332 4 | 0x46,0x40,0x9a,0x02 = bgez $6, 1332 5 | 0x66,0x40,0x9a,0x02 = bgezal $6, 1332 6 | 0x26,0x40,0x9a,0x02 = bltzal $6, 1332 7 | 0xc6,0x40,0x9a,0x02 = bgtz $6, 1332 8 | 0x86,0x40,0x9a,0x02 = blez $6, 1332 9 | 0xc9,0xb4,0x9a,0x02 = bne $9, $6, 1332 10 | 0x60,0x40,0x9a,0x02 = bal 1332 11 | 0x06,0x40,0x9a,0x02 = bltz $6, 1332 12 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-expansions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0xa0,0x50,0x7b,0x00 = ori $5, $zero, 123 3 | 0xc0,0x30,0xd7,0xf6 = addiu $6, $zero, -2345 4 | 0xa7,0x41,0x01,0x00 = lui $7, 1 5 | 0xe7,0x50,0x02,0x00 = ori $7, $7, 2 6 | 0x80,0x30,0x14,0x00 = addiu $4, $zero, 20 7 | 0xa7,0x41,0x01,0x00 = lui $7, 1 8 | 0xe7,0x50,0x02,0x00 = ori $7, $7, 2 9 | 0x85,0x30,0x14,0x00 = addiu $4, $5, 20 10 | 0xa7,0x41,0x01,0x00 = lui $7, 1 11 | 0xe7,0x50,0x02,0x00 = ori $7, $7, 2 12 | 0x07,0x01,0x50,0x39 = addu $7, $7, $8 13 | 0x8a,0x00,0x50,0x51 = addu $10, $10, $4 14 | 0x21,0x01,0x50,0x09 = addu $1, $1, $9 15 | 0xaa,0x41,0x0a,0x00 = lui $10, 10 16 | 0x8a,0x00,0x50,0x51 = addu $10, $10, $4 17 | 0x4a,0xfd,0x7b,0x00 = lw $10, 123($10) 18 | 0xa1,0x41,0x02,0x00 = lui $1, 2 19 | 0x21,0x01,0x50,0x09 = addu $1, $1, $9 20 | 0x41,0xf9,0x40,0xe2 = sw $10, 57920($1) 21 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-jump-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0xd4,0x00,0x02,0x98 = j 1328 3 | 0xf4,0x00,0x02,0x98 = jal 1328 4 | 0x03,0xe6,0x0f,0x3c = jalr $6 5 | 0x00,0x07,0x0f,0x3c = jr $7 6 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-jump-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0x00,0xd4,0x98,0x02 = j 1328 3 | 0x00,0xf4,0x98,0x02 = jal 1328 4 | 0xe6,0x03,0x3c,0x0f = jalr $6 5 | 0x07,0x00,0x3c,0x0f = jr $7 6 | 0x07,0x00,0x3c,0x0f = jr $7 7 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-loadstore-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x1c,0xa4,0x00,0x08 = lb $5, 8($4) 3 | 0x14,0xc4,0x00,0x08 = lbu $6, 8($4) 4 | 0x3c,0x44,0x00,0x08 = lh $2, 8($4) 5 | 0x34,0x82,0x00,0x08 = lhu $4, 8($2) 6 | 0xfc,0xc5,0x00,0x04 = lw $6, 4($5) 7 | 0x18,0xa4,0x00,0x08 = sb $5, 8($4) 8 | 0x38,0x44,0x00,0x08 = sh $2, 8($4) 9 | 0xf8,0xa6,0x00,0x04 = sw $5, 4($6) 10 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-loadstore-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0xa4,0x1c,0x08,0x00 = lb $5, 8($4) 3 | 0xc4,0x14,0x08,0x00 = lbu $6, 8($4) 4 | 0x44,0x3c,0x08,0x00 = lh $2, 8($4) 5 | 0x82,0x34,0x08,0x00 = lhu $4, 8($2) 6 | 0xc5,0xfc,0x04,0x00 = lw $6, 4($5) 7 | 0xa4,0x18,0x08,0x00 = sb $5, 8($4) 8 | 0x44,0x38,0x08,0x00 = sh $2, 8($4) 9 | 0xa6,0xf8,0x04,0x00 = sw $5, 4($6) 10 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-loadstore-unaligned-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x60,0x85,0x00,0x10 = lwl $4, 16($5) 3 | 0x60,0x85,0x10,0x10 = lwr $4, 16($5) 4 | 0x60,0x85,0x80,0x10 = swl $4, 16($5) 5 | 0x60,0x85,0x90,0x10 = swr $4, 16($5) 6 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-loadstore-unaligned.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0x85,0x60,0x10,0x00 = lwl $4, 16($5) 3 | 0x85,0x60,0x10,0x10 = lwr $4, 16($5) 4 | 0x85,0x60,0x10,0x80 = swl $4, 16($5) 5 | 0x85,0x60,0x10,0x90 = swr $4, 16($5) 6 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-movcond-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x00,0xe6,0x48,0x58 = movz $9, $6, $7 3 | 0x00,0xe6,0x48,0x18 = movn $9, $6, $7 4 | 0x55,0x26,0x09,0x7b = movt $9, $6, $fcc0 5 | 0x55,0x26,0x01,0x7b = movf $9, $6, $fcc0 6 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-movcond-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0xe6,0x00,0x58,0x48 = movz $9, $6, $7 3 | 0xe6,0x00,0x18,0x48 = movn $9, $6, $7 4 | 0x26,0x55,0x7b,0x09 = movt $9, $6, $fcc0 5 | 0x26,0x55,0x7b,0x01 = movf $9, $6, $fcc0 6 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-multiply-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x00,0xa4,0xcb,0x3c = madd $4, $5 3 | 0x00,0xa4,0xdb,0x3c = maddu $4, $5 4 | 0x00,0xa4,0xeb,0x3c = msub $4, $5 5 | 0x00,0xa4,0xfb,0x3c = msubu $4, $5 6 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-multiply-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0xa4,0x00,0x3c,0xcb = madd $4, $5 3 | 0xa4,0x00,0x3c,0xdb = maddu $4, $5 4 | 0xa4,0x00,0x3c,0xeb = msub $4, $5 5 | 0xa4,0x00,0x3c,0xfb = msubu $4, $5 6 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-shift-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x00,0x83,0x38,0x00 = sll $4, $3, 7 3 | 0x00,0x65,0x10,0x10 = sllv $2, $3, $5 4 | 0x00,0x83,0x38,0x80 = sra $4, $3, 7 5 | 0x00,0x65,0x10,0x90 = srav $2, $3, $5 6 | 0x00,0x83,0x38,0x40 = srl $4, $3, 7 7 | 0x00,0x65,0x10,0x50 = srlv $2, $3, $5 8 | 0x01,0x26,0x38,0xc0 = rotr $9, $6, 7 9 | 0x00,0xc7,0x48,0xd0 = rotrv $9, $6, $7 10 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-shift-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0x83,0x00,0x00,0x38 = sll $4, $3, 7 3 | 0x65,0x00,0x10,0x10 = sllv $2, $3, $5 4 | 0x83,0x00,0x80,0x38 = sra $4, $3, 7 5 | 0x65,0x00,0x90,0x10 = srav $2, $3, $5 6 | 0x83,0x00,0x40,0x38 = srl $4, $3, 7 7 | 0x65,0x00,0x50,0x10 = srlv $2, $3, $5 8 | 0x26,0x01,0xc0,0x38 = rotr $9, $6, 7 9 | 0xc7,0x00,0xd0,0x48 = rotrv $9, $6, $7 10 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-trap-instructions-EB.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 2 | 0x01,0x28,0x00,0x3c = teq $8, $9 3 | 0x01,0x28,0x02,0x3c = tge $8, $9 4 | 0x01,0x28,0x04,0x3c = tgeu $8, $9 5 | 0x01,0x28,0x08,0x3c = tlt $8, $9 6 | 0x01,0x28,0x0a,0x3c = tltu $8, $9 7 | 0x01,0x28,0x0c,0x3c = tne $8, $9 8 | 0x41,0xc9,0x45,0x67 = teqi $9, 17767 9 | 0x41,0x29,0x45,0x67 = tgei $9, 17767 10 | 0x41,0x69,0x45,0x67 = tgeiu $9, 17767 11 | 0x41,0x09,0x45,0x67 = tlti $9, 17767 12 | 0x41,0x49,0x45,0x67 = tltiu $9, 17767 13 | 0x41,0x89,0x45,0x67 = tnei $9, 17767 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/micromips-trap-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 2 | 0x28,0x01,0x3c,0x00 = teq $8, $9 3 | 0x28,0x01,0x3c,0x02 = tge $8, $9 4 | 0x28,0x01,0x3c,0x04 = tgeu $8, $9 5 | 0x28,0x01,0x3c,0x08 = tlt $8, $9 6 | 0x28,0x01,0x3c,0x0a = tltu $8, $9 7 | 0x28,0x01,0x3c,0x0c = tne $8, $9 8 | 0xc9,0x41,0x67,0x45 = teqi $9, 17767 9 | 0x29,0x41,0x67,0x45 = tgei $9, 17767 10 | 0x69,0x41,0x67,0x45 = tgeiu $9, 17767 11 | 0x09,0x41,0x67,0x45 = tlti $9, 17767 12 | 0x49,0x41,0x67,0x45 = tltiu $9, 17767 13 | 0x89,0x41,0x67,0x45 = tnei $9, 17767 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/mips-control-instructions-64.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None 2 | 0x00,0x00,0x00,0x0d = break 3 | 0x00,0x07,0x00,0x0d = break 7, 0 4 | 0x00,0x07,0x01,0x4d = break 7, 5 5 | 0x00,0x00,0x00,0x0c = syscall 6 | 0x00,0x0d,0x15,0x0c = syscall 13396 7 | 0x42,0x00,0x00,0x18 = eret 8 | 0x42,0x00,0x00,0x1f = deret 9 | 0x41,0x60,0x60,0x00 = di 10 | 0x41,0x60,0x60,0x00 = di 11 | 0x41,0x6a,0x60,0x00 = di $10 12 | 0x41,0x60,0x60,0x20 = ei 13 | 0x41,0x60,0x60,0x20 = ei 14 | 0x41,0x6a,0x60,0x20 = ei $10 15 | 0x42,0x00,0x00,0x20 = wait 16 | 0x00,0x03,0x00,0x34 = teq $zero, $3 17 | 0x00,0x03,0x00,0x74 = teq $zero, $3, 1 18 | 0x04,0x6c,0x00,0x01 = teqi $3, 1 19 | 0x00,0x03,0x00,0x30 = tge $zero, $3 20 | 0x00,0x03,0x00,0xf0 = tge $zero, $3, 3 21 | 0x04,0x68,0x00,0x03 = tgei $3, 3 22 | 0x00,0x03,0x00,0x31 = tgeu $zero, $3 23 | 0x00,0x03,0x01,0xf1 = tgeu $zero, $3, 7 24 | 0x04,0x69,0x00,0x07 = tgeiu $3, 7 25 | 0x00,0x03,0x00,0x32 = tlt $zero, $3 26 | 0x00,0x03,0x07,0xf2 = tlt $zero, $3, 31 27 | 0x04,0x6a,0x00,0x1f = tlti $3, 31 28 | 0x00,0x03,0x00,0x33 = tltu $zero, $3 29 | 0x00,0x03,0x3f,0xf3 = tltu $zero, $3, 255 30 | 0x04,0x6b,0x00,0xff = tltiu $3, 255 31 | 0x00,0x03,0x00,0x36 = tne $zero, $3 32 | 0x00,0x03,0xff,0xf6 = tne $zero, $3, 1023 33 | 0x04,0x6e,0x03,0xff = tnei $3, 1023 34 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/mips-control-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x00,0x00,0x00,0x0d = break 3 | 0x00,0x07,0x00,0x0d = break 7, 0 4 | 0x00,0x07,0x01,0x4d = break 7, 5 5 | 0x00,0x00,0x00,0x0c = syscall 6 | 0x00,0x0d,0x15,0x0c = syscall 13396 7 | 0x42,0x00,0x00,0x18 = eret 8 | 0x42,0x00,0x00,0x1f = deret 9 | 0x41,0x60,0x60,0x00 = di 10 | 0x41,0x60,0x60,0x00 = di 11 | 0x41,0x6a,0x60,0x00 = di $10 12 | 0x41,0x60,0x60,0x20 = ei 13 | 0x41,0x60,0x60,0x20 = ei 14 | 0x41,0x6a,0x60,0x20 = ei $10 15 | 0x42,0x00,0x00,0x20 = wait 16 | 0x00,0x03,0x00,0x34 = teq $zero, $3 17 | 0x00,0x03,0x00,0x74 = teq $zero, $3, 1 18 | 0x04,0x6c,0x00,0x01 = teqi $3, 1 19 | 0x00,0x03,0x00,0x30 = tge $zero, $3 20 | 0x00,0x03,0x00,0xf0 = tge $zero, $3, 3 21 | 0x04,0x68,0x00,0x03 = tgei $3, 3 22 | 0x00,0x03,0x00,0x31 = tgeu $zero, $3 23 | 0x00,0x03,0x01,0xf1 = tgeu $zero, $3, 7 24 | 0x04,0x69,0x00,0x07 = tgeiu $3, 7 25 | 0x00,0x03,0x00,0x32 = tlt $zero, $3 26 | 0x00,0x03,0x07,0xf2 = tlt $zero, $3, 31 27 | 0x04,0x6a,0x00,0x1f = tlti $3, 31 28 | 0x00,0x03,0x00,0x33 = tltu $zero, $3 29 | 0x00,0x03,0x3f,0xf3 = tltu $zero, $3, 255 30 | 0x04,0x6b,0x00,0xff = tltiu $3, 255 31 | 0x00,0x03,0x00,0x36 = tne $zero, $3 32 | 0x00,0x03,0xff,0xf6 = tne $zero, $3, 1023 33 | 0x04,0x6e,0x03,0xff = tnei $3, 1023 34 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/mips-coprocessor-encodings.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None 2 | 0x40,0xac,0x80,0x02 = dmtc0 $12, $16, 2 3 | 0x40,0xac,0x80,0x00 = dmtc0 $12, $16, 0 4 | 0x40,0x8c,0x80,0x02 = mtc0 $12, $16, 2 5 | 0x40,0x8c,0x80,0x00 = mtc0 $12, $16, 0 6 | 0x40,0x2c,0x80,0x02 = dmfc0 $12, $16, 2 7 | 0x40,0x2c,0x80,0x00 = dmfc0 $12, $16, 0 8 | 0x40,0x0c,0x80,0x02 = mfc0 $12, $16, 2 9 | 0x40,0x0c,0x80,0x00 = mfc0 $12, $16, 0 10 | 0x48,0xac,0x80,0x02 = dmtc2 $12, $16, 2 11 | 0x48,0xac,0x80,0x00 = dmtc2 $12, $16, 0 12 | 0x48,0x8c,0x80,0x02 = mtc2 $12, $16, 2 13 | 0x48,0x8c,0x80,0x00 = mtc2 $12, $16, 0 14 | 0x48,0x2c,0x80,0x02 = dmfc2 $12, $16, 2 15 | 0x48,0x2c,0x80,0x00 = dmfc2 $12, $16, 0 16 | 0x48,0x0c,0x80,0x02 = mfc2 $12, $16, 2 17 | 0x48,0x0c,0x80,0x00 = mfc2 $12, $16, 0 18 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/mips-expansions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32, None 2 | 0x7b,0x00,0x05,0x34 = ori $5, $zero, 123 3 | 0xd7,0xf6,0x06,0x24 = addiu $6, $zero, -2345 4 | 0x01,0x00,0x07,0x3c = lui $7, 1 5 | 0x02,0x00,0xe7,0x34 = ori $7, $7, 2 6 | 0x14,0x00,0x04,0x24 = addiu $4, $zero, 20 7 | 0x01,0x00,0x07,0x3c = lui $7, 1 8 | 0x02,0x00,0xe7,0x34 = ori $7, $7, 2 9 | 0x14,0x00,0xa4,0x24 = addiu $4, $5, 20 10 | 0x01,0x00,0x07,0x3c = lui $7, 1 11 | 0x02,0x00,0xe7,0x34 = ori $7, $7, 2 12 | 0x21,0x38,0xe8,0x00 = addu $7, $7, $8 13 | 0x21,0x50,0x44,0x01 = addu $10, $10, $4 14 | 0x21,0x08,0x29,0x00 = addu $1, $1, $9 15 | 0x0a,0x00,0x0a,0x3c = lui $10, 10 16 | 0x21,0x50,0x44,0x01 = addu $10, $10, $4 17 | 0x7b,0x00,0x4a,0x8d = lw $10, 123($10) 18 | 0x02,0x00,0x01,0x3c = lui $1, 2 19 | 0x21,0x08,0x29,0x00 = addu $1, $1, $9 20 | 0x40,0xe2,0x2a,0xac = sw $10, 57920($1) 21 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/mips-jump-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32, None 2 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/mips-memory-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32, None 2 | 0x10,0x00,0xa4,0xa0 = sb $4, 16($5) 3 | 0x10,0x00,0xa4,0xe0 = sc $4, 16($5) 4 | 0x10,0x00,0xa4,0xa4 = sh $4, 16($5) 5 | 0x10,0x00,0xa4,0xac = sw $4, 16($5) 6 | 0x00,0x00,0xa7,0xac = sw $7, 0($5) 7 | 0x10,0x00,0xa2,0xe4 = swc1 $f2, 16($5) 8 | 0x10,0x00,0xa4,0xa8 = swl $4, 16($5) 9 | 0x04,0x00,0xa4,0x80 = lb $4, 4($5) 10 | 0x04,0x00,0xa4,0x8c = lw $4, 4($5) 11 | 0x04,0x00,0xa4,0x90 = lbu $4, 4($5) 12 | 0x04,0x00,0xa4,0x84 = lh $4, 4($5) 13 | 0x04,0x00,0xa4,0x94 = lhu $4, 4($5) 14 | 0x04,0x00,0xa4,0xc0 = ll $4, 4($5) 15 | 0x04,0x00,0xa4,0x8c = lw $4, 4($5) 16 | 0x00,0x00,0xe7,0x8c = lw $7, 0($7) 17 | 0x10,0x00,0xa2,0x8f = lw $2, 16($sp) 18 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/mips64-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS64, None 2 | 0x81,0x00,0x42,0x4d = ldxc1 $f2, $2($10) 3 | 0x09,0x40,0x24,0x4f = sdxc1 $f8, $4($25) 4 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/mips_directives.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x10,0x00,0x01,0x4d = b 1332 3 | 0x08,0x00,0x01,0x4c = j 1328 4 | 0x0c,0x00,0x01,0x4c = jal 1328 5 | 0x10,0x00,0x01,0x4d = b 1332 6 | 0x00,0x00,0x00,0x00 = nop 7 | 0x08,0x00,0x01,0x4c = j 1328 8 | 0x00,0x00,0x00,0x00 = nop 9 | 0x0c,0x00,0x01,0x4c = jal 1328 10 | 0x00,0x00,0x00,0x00 = nop 11 | 0x46,0x00,0x39,0x85 = abs.s $f6, $f7 12 | 0x01,0xef,0x18,0x24 = and $3, $15, $15 13 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/nabi-regs.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None 2 | 0x02,0x04,0x80,0x20 = add $16, $16, $4 3 | 0x02,0x06,0x80,0x20 = add $16, $16, $6 4 | 0x02,0x07,0x80,0x20 = add $16, $16, $7 5 | 0x02,0x08,0x80,0x20 = add $16, $16, $8 6 | 0x02,0x09,0x80,0x20 = add $16, $16, $9 7 | 0x02,0x0a,0x80,0x20 = add $16, $16, $10 8 | 0x02,0x0b,0x80,0x20 = add $16, $16, $11 9 | 0x02,0x0c,0x80,0x20 = add $16, $16, $12 10 | 0x02,0x0d,0x80,0x20 = add $16, $16, $13 11 | 0x02,0x0e,0x80,0x20 = add $16, $16, $14 12 | 0x02,0x0f,0x80,0x20 = add $16, $16, $15 13 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/set-at-directive.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32, None 2 | 0x08,0x00,0x60,0x00 = jr $3 3 | 0x08,0x00,0x80,0x03 = jr $gp 4 | 0x08,0x00,0xc0,0x03 = jr $fp 5 | 0x08,0x00,0xa0,0x03 = jr $sp 6 | 0x08,0x00,0xe0,0x03 = jr $ra 7 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/test_2r.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x7b,0x00,0x4f,0x9e = fill.b $w30, $9 3 | 0x7b,0x01,0xbf,0xde = fill.h $w31, $23 4 | 0x7b,0x02,0xc4,0x1e = fill.w $w16, $24 5 | 0x7b,0x08,0x05,0x5e = nloc.b $w21, $w0 6 | 0x7b,0x09,0xfc,0x9e = nloc.h $w18, $w31 7 | 0x7b,0x0a,0xb8,0x9e = nloc.w $w2, $w23 8 | 0x7b,0x0b,0x51,0x1e = nloc.d $w4, $w10 9 | 0x7b,0x0c,0x17,0xde = nlzc.b $w31, $w2 10 | 0x7b,0x0d,0xb6,0xde = nlzc.h $w27, $w22 11 | 0x7b,0x0e,0xea,0x9e = nlzc.w $w10, $w29 12 | 0x7b,0x0f,0x4e,0x5e = nlzc.d $w25, $w9 13 | 0x7b,0x04,0x95,0x1e = pcnt.b $w20, $w18 14 | 0x7b,0x05,0x40,0x1e = pcnt.h $w0, $w8 15 | 0x7b,0x06,0x4d,0xde = pcnt.w $w23, $w9 16 | 0x7b,0x07,0xc5,0x5e = pcnt.d $w21, $w24 17 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/test_cbranch.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x47,0x80,0x00,0x01 = bnz.b $w0, 4 3 | 0x47,0xa1,0x00,0x04 = bnz.h $w1, 16 4 | 0x47,0xc2,0x00,0x20 = bnz.w $w2, 128 5 | 0x47,0xe3,0xff,0xe0 = bnz.d $w3, -128 6 | 0x45,0xe0,0x00,0x01 = bnz.v $w0, 4 7 | 0x47,0x00,0x00,0x20 = bz.b $w0, 128 8 | 0x47,0x21,0x00,0x40 = bz.h $w1, 256 9 | 0x47,0x42,0x00,0x80 = bz.w $w2, 512 10 | 0x47,0x63,0xff,0x00 = bz.d $w3, -1024 11 | 0x45,0x60,0x00,0x01 = bz.v $w0, 4 12 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/test_ctrlregs.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x78,0x7e,0x00,0x59 = cfcmsa $1, $0 3 | 0x78,0x7e,0x00,0x59 = cfcmsa $1, $0 4 | 0x78,0x7e,0x08,0x99 = cfcmsa $2, $1 5 | 0x78,0x7e,0x08,0x99 = cfcmsa $2, $1 6 | 0x78,0x7e,0x10,0xd9 = cfcmsa $3, $2 7 | 0x78,0x7e,0x10,0xd9 = cfcmsa $3, $2 8 | 0x78,0x7e,0x19,0x19 = cfcmsa $4, $3 9 | 0x78,0x7e,0x19,0x19 = cfcmsa $4, $3 10 | 0x78,0x7e,0x21,0x59 = cfcmsa $5, $4 11 | 0x78,0x7e,0x21,0x59 = cfcmsa $5, $4 12 | 0x78,0x7e,0x29,0x99 = cfcmsa $6, $5 13 | 0x78,0x7e,0x29,0x99 = cfcmsa $6, $5 14 | 0x78,0x7e,0x31,0xd9 = cfcmsa $7, $6 15 | 0x78,0x7e,0x31,0xd9 = cfcmsa $7, $6 16 | 0x78,0x7e,0x3a,0x19 = cfcmsa $8, $7 17 | 0x78,0x7e,0x3a,0x19 = cfcmsa $8, $7 18 | 0x78,0x3e,0x08,0x19 = ctcmsa $0, $1 19 | 0x78,0x3e,0x08,0x19 = ctcmsa $0, $1 20 | 0x78,0x3e,0x10,0x59 = ctcmsa $1, $2 21 | 0x78,0x3e,0x10,0x59 = ctcmsa $1, $2 22 | 0x78,0x3e,0x18,0x99 = ctcmsa $2, $3 23 | 0x78,0x3e,0x18,0x99 = ctcmsa $2, $3 24 | 0x78,0x3e,0x20,0xd9 = ctcmsa $3, $4 25 | 0x78,0x3e,0x20,0xd9 = ctcmsa $3, $4 26 | 0x78,0x3e,0x29,0x19 = ctcmsa $4, $5 27 | 0x78,0x3e,0x29,0x19 = ctcmsa $4, $5 28 | 0x78,0x3e,0x31,0x59 = ctcmsa $5, $6 29 | 0x78,0x3e,0x31,0x59 = ctcmsa $5, $6 30 | 0x78,0x3e,0x39,0x99 = ctcmsa $6, $7 31 | 0x78,0x3e,0x39,0x99 = ctcmsa $6, $7 32 | 0x78,0x3e,0x41,0xd9 = ctcmsa $7, $8 33 | 0x78,0x3e,0x41,0xd9 = ctcmsa $7, $8 34 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/test_elm.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x78,0x82,0x43,0x59 = copy_s.b $13, $w8[2] 3 | 0x78,0xa0,0xc8,0x59 = copy_s.h $1, $w25[0] 4 | 0x78,0xb1,0x2d,0x99 = copy_s.w $22, $w5[1] 5 | 0x78,0xc4,0xa5,0x99 = copy_u.b $22, $w20[4] 6 | 0x78,0xe0,0x25,0x19 = copy_u.h $20, $w4[0] 7 | 0x78,0xf2,0x6f,0x99 = copy_u.w $fp, $w13[2] 8 | 0x78,0x04,0xe8,0x19 = sldi.b $w0, $w29[4] 9 | 0x78,0x20,0x8a,0x19 = sldi.h $w8, $w17[0] 10 | 0x78,0x32,0xdd,0x19 = sldi.w $w20, $w27[2] 11 | 0x78,0x38,0x61,0x19 = sldi.d $w4, $w12[0] 12 | 0x78,0x42,0x1e,0x59 = splati.b $w25, $w3[2] 13 | 0x78,0x61,0xe6,0x19 = splati.h $w24, $w28[1] 14 | 0x78,0x70,0x93,0x59 = splati.w $w13, $w18[0] 15 | 0x78,0x78,0x0f,0x19 = splati.d $w28, $w1[0] 16 | 0x78,0xbe,0xc5,0xd9 = move.v $w23, $w24 17 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/test_elm_insert.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x79,0x03,0xed,0xd9 = insert.b $w23[3], $sp 3 | 0x79,0x22,0x2d,0x19 = insert.h $w20[2], $5 4 | 0x79,0x32,0x7a,0x19 = insert.w $w8[2], $15 5 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/test_elm_insve.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x79,0x43,0x4e,0x59 = insve.b $w25[3], $w9[0] 3 | 0x79,0x62,0x16,0x19 = insve.h $w24[2], $w2[0] 4 | 0x79,0x72,0x68,0x19 = insve.w $w0[2], $w13[0] 5 | 0x79,0x78,0x90,0xd9 = insve.d $w3[0], $w18[0] 6 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/test_i10.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x7b,0x06,0x32,0x07 = ldi.b $w8, 198 3 | 0x7b,0x29,0xcd,0x07 = ldi.h $w20, 313 4 | 0x7b,0x4f,0x66,0x07 = ldi.w $w24, 492 5 | 0x7b,0x7a,0x66,0xc7 = ldi.d $w27, -180 6 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/test_i8.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x78,0x30,0xe8,0x80 = andi.b $w2, $w29, 48 3 | 0x78,0x7e,0xb1,0x81 = bmnzi.b $w6, $w22, 126 4 | 0x79,0x58,0x0e,0xc1 = bmzi.b $w27, $w1, 88 5 | 0x7a,0xbd,0x1f,0x41 = bseli.b $w29, $w3, 189 6 | 0x7a,0x38,0x88,0x40 = nori.b $w1, $w17, 56 7 | 0x79,0x87,0xa6,0x80 = ori.b $w26, $w20, 135 8 | 0x78,0x69,0xf4,0xc2 = shf.b $w19, $w30, 105 9 | 0x79,0x4c,0x44,0x42 = shf.h $w17, $w8, 76 10 | 0x7a,0x5d,0x1b,0x82 = shf.w $w14, $w3, 93 11 | 0x7b,0x14,0x54,0x00 = xori.b $w16, $w10, 20 12 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/test_lsa.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x01,0x2a,0x40,0x05 = lsa $8, $9, $10, 1 3 | 0x01,0x2a,0x40,0x45 = lsa $8, $9, $10, 2 4 | 0x01,0x2a,0x40,0x85 = lsa $8, $9, $10, 3 5 | 0x01,0x2a,0x40,0xc5 = lsa $8, $9, $10, 4 6 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/test_mi10.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x7a,0x00,0x08,0x20 = ld.b $w0, -512($1) 3 | 0x78,0x00,0x10,0x60 = ld.b $w1, 0($2) 4 | 0x79,0xff,0x18,0xa0 = ld.b $w2, 511($3) 5 | 0x7a,0x00,0x20,0xe1 = ld.h $w3, -1024($4) 6 | 0x7b,0x00,0x29,0x21 = ld.h $w4, -512($5) 7 | 0x78,0x00,0x31,0x61 = ld.h $w5, 0($6) 8 | 0x79,0x00,0x39,0xa1 = ld.h $w6, 512($7) 9 | 0x79,0xff,0x41,0xe1 = ld.h $w7, 1022($8) 10 | 0x7a,0x00,0x4a,0x22 = ld.w $w8, -2048($9) 11 | 0x7b,0x00,0x52,0x62 = ld.w $w9, -1024($10) 12 | 0x7b,0x80,0x5a,0xa2 = ld.w $w10, -512($11) 13 | 0x78,0x80,0x62,0xe2 = ld.w $w11, 512($12) 14 | 0x79,0x00,0x6b,0x22 = ld.w $w12, 1024($13) 15 | 0x79,0xff,0x73,0x62 = ld.w $w13, 2044($14) 16 | 0x7a,0x00,0x7b,0xa3 = ld.d $w14, -4096($15) 17 | 0x7b,0x00,0x83,0xe3 = ld.d $w15, -2048($16) 18 | 0x7b,0x80,0x8c,0x23 = ld.d $w16, -1024($17) 19 | 0x7b,0xc0,0x94,0x63 = ld.d $w17, -512($18) 20 | 0x78,0x00,0x9c,0xa3 = ld.d $w18, 0($19) 21 | 0x78,0x40,0xa4,0xe3 = ld.d $w19, 512($20) 22 | 0x78,0x80,0xad,0x23 = ld.d $w20, 1024($21) 23 | 0x79,0x00,0xb5,0x63 = ld.d $w21, 2048($22) 24 | 0x79,0xff,0xbd,0xa3 = ld.d $w22, 4088($23) 25 | -------------------------------------------------------------------------------- /capstone/suite/MC/Mips/test_vec.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 2 | 0x78,0x1b,0xa6,0x5e = and.v $w25, $w20, $w27 3 | 0x78,0x87,0x34,0x5e = bmnz.v $w17, $w6, $w7 4 | 0x78,0xa9,0x88,0xde = bmz.v $w3, $w17, $w9 5 | 0x78,0xce,0x02,0x1e = bsel.v $w8, $w0, $w14 6 | 0x78,0x40,0xf9,0xde = nor.v $w7, $w31, $w0 7 | 0x78,0x3e,0xd6,0x1e = or.v $w24, $w26, $w30 8 | 0x78,0x6f,0xd9,0xde = xor.v $w7, $w27, $w15 9 | -------------------------------------------------------------------------------- /capstone/suite/MC/PowerPC/ppc64-encoding-bookII.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME 2 | 0x7c,0x02,0x1f,0xac = icbi 2, 3 3 | 0x7c,0x02,0x1a,0x2c = dcbt 2, 3 4 | 0x7c,0x02,0x19,0xec = dcbtst 2, 3 5 | 0x7c,0x02,0x1f,0xec = dcbz 2, 3 6 | 0x7c,0x02,0x18,0x6c = dcbst 2, 3 7 | 0x4c,0x00,0x01,0x2c = isync 8 | 0x7c,0x43,0x21,0x2d = stwcx. 2, 3, 4 9 | 0x7c,0x43,0x21,0xad = stdcx. 2, 3, 4 10 | 0x7c,0x40,0x04,0xac = sync 2 11 | 0x7c,0x00,0x06,0xac = eieio 12 | 0x7c,0x40,0x00,0x7c = wait 2 13 | 0x7c,0x02,0x18,0xac = dcbf 2, 3 14 | 0x7c,0x43,0x20,0x28 = lwarx 2, 3, 4 15 | 0x7c,0x43,0x20,0xa8 = ldarx 2, 3, 4 16 | 0x7c,0x00,0x04,0xac = sync 0 17 | 0x7c,0x00,0x04,0xac = sync 0 18 | 0x7c,0x20,0x04,0xac = sync 1 19 | 0x7c,0x40,0x04,0xac = sync 2 20 | 0x7c,0x00,0x00,0x7c = wait 0 21 | 0x7c,0x20,0x00,0x7c = wait 1 22 | 0x7c,0x40,0x00,0x7c = wait 2 23 | 0x7c,0x5b,0x1a,0xe6 = mftb 2, 123 24 | 0x7c,0x4c,0x42,0xe6 = mftb 2, 268 25 | 0x7c,0x4d,0x42,0xe6 = mftb 2, 269 26 | -------------------------------------------------------------------------------- /capstone/suite/MC/PowerPC/ppc64-encoding-bookIII.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME 2 | 0x7c,0x80,0x01,0x24 = mtmsr 4, 0 3 | 0x7c,0x81,0x01,0x24 = mtmsr 4, 1 4 | 0x7c,0x80,0x00,0xa6 = mfmsr 4 5 | 0x7c,0x80,0x01,0x64 = mtmsrd 4, 0 6 | 0x7c,0x81,0x01,0x64 = mtmsrd 4, 1 7 | 0x7c,0x90,0x42,0xa6 = mfspr 4, 272 8 | 0x7c,0x91,0x42,0xa6 = mfspr 4, 273 9 | 0x7c,0x92,0x42,0xa6 = mfspr 4, 274 10 | 0x7c,0x93,0x42,0xa6 = mfspr 4, 275 11 | 0x7c,0x90,0x43,0xa6 = mtspr 272, 4 12 | 0x7c,0x91,0x43,0xa6 = mtspr 273, 4 13 | 0x7c,0x92,0x43,0xa6 = mtspr 274, 4 14 | 0x7c,0x93,0x43,0xa6 = mtspr 275, 4 15 | 0x7c,0x90,0x43,0xa6 = mtspr 272, 4 16 | 0x7c,0x91,0x43,0xa6 = mtspr 273, 4 17 | 0x7c,0x92,0x43,0xa6 = mtspr 274, 4 18 | 0x7c,0x93,0x43,0xa6 = mtspr 275, 4 19 | 0x7c,0x98,0x43,0xa6 = mtspr 280, 4 20 | 0x7c,0x96,0x02,0xa6 = mfspr 4, 22 21 | 0x7c,0x96,0x03,0xa6 = mtspr 22, 4 22 | 0x7c,0x9f,0x42,0xa6 = mfspr 4, 287 23 | 0x7c,0x99,0x02,0xa6 = mfspr 4, 25 24 | 0x7c,0x99,0x03,0xa6 = mtspr 25, 4 25 | 0x7c,0x9a,0x02,0xa6 = mfspr 4, 26 26 | 0x7c,0x9a,0x03,0xa6 = mtspr 26, 4 27 | 0x7c,0x9b,0x02,0xa6 = mfspr 4, 27 28 | 0x7c,0x9b,0x03,0xa6 = mtspr 27, 4 29 | 0x7c,0x00,0x23,0x64 = slbie 4 30 | 0x7c,0x80,0x2b,0x24 = slbmte 4, 5 31 | 0x7c,0x80,0x2f,0x26 = slbmfee 4, 5 32 | 0x7c,0x00,0x03,0xe4 = slbia 33 | 0x7c,0x00,0x04,0x6c = tlbsync 34 | 0x7c,0x00,0x22,0x24 = tlbiel 4 35 | 0x7c,0x00,0x22,0x64 = tlbie 4,0 36 | -------------------------------------------------------------------------------- /capstone/suite/MC/PowerPC/ppc64-operands.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME 2 | 0x7c,0x22,0x1a,0x14 = add 1, 2, 3 3 | 0x7c,0x22,0x1a,0x14 = add 1, 2, 3 4 | 0x7c,0x00,0x02,0x14 = add 0, 0, 0 5 | 0x7f,0xff,0xfa,0x14 = add 31, 31, 31 6 | 0x38,0x20,0x00,0x00 = addi 1, 0, 0 7 | 0x38,0x20,0x00,0x00 = addi 1, 0, 0 8 | 0x38,0x22,0x00,0x00 = addi 1, 2, 0 9 | 0x38,0x20,0x80,0x00 = addi 1, 0, -32768 10 | 0x38,0x20,0x7f,0xff = addi 1, 0, 32767 11 | 0x60,0x41,0x00,0x00 = ori 1, 2, 0 12 | 0x60,0x41,0xff,0xff = ori 1, 2, 65535 13 | 0x3c,0x20,0x00,0x00 = addis 1, 0, 0 14 | 0x3c,0x20,0xff,0xff = addis 1, 0, -1 15 | 0x80,0x20,0x00,0x00 = lwz 1, 0(0) 16 | 0x80,0x20,0x00,0x00 = lwz 1, 0(0) 17 | 0x80,0x3f,0x00,0x00 = lwz 1, 0(31) 18 | 0x80,0x3f,0x00,0x00 = lwz 1, 0(31) 19 | 0x80,0x22,0x80,0x00 = lwz 1, -32768(2) 20 | 0x80,0x22,0x7f,0xff = lwz 1, 32767(2) 21 | 0xe8,0x20,0x00,0x00 = ld 1, 0(0) 22 | 0xe8,0x20,0x00,0x00 = ld 1, 0(0) 23 | 0xe8,0x3f,0x00,0x00 = ld 1, 0(31) 24 | 0xe8,0x3f,0x00,0x00 = ld 1, 0(31) 25 | 0xe8,0x22,0x80,0x00 = ld 1, -32768(2) 26 | 0xe8,0x22,0x7f,0xfc = ld 1, 32764(2) 27 | 0xe8,0x22,0x00,0x04 = ld 1, 4(2) 28 | 0xe8,0x22,0xff,0xfc = ld 1, -4(2) 29 | 0x48,0x00,0x04,0x00 = b .+1024 30 | 0x48,0x00,0x04,0x02 = ba 1024 31 | 0x41,0x82,0x04,0x00 = beq 0, .+1024 32 | 0x41,0x82,0x04,0x02 = beqa 0, 1024 33 | -------------------------------------------------------------------------------- /capstone/suite/MC/README: -------------------------------------------------------------------------------- 1 | Input files for testing Capstone engine. 2 | 3 | Format of input files: 4 | 5 | # ARCH, MODE, OPTION 6 | hexcode = assembly 7 | -------------------------------------------------------------------------------- /capstone/suite/MC/Sparc/sparc-atomic-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0x81,0x43,0xe0,0x0f = membar 15 3 | 0x81,0x43,0xc0,0x00 = stbar 4 | 0xd4,0x7e,0x00,0x16 = swap [%i0+%l6], %o2 5 | 0xd4,0x7e,0x20,0x20 = swap [%i0+32], %o2 6 | 0xd5,0xe6,0x10,0x16 = cas [%i0], %l6, %o2 7 | 0xd5,0xf6,0x10,0x16 = casx [%i0], %l6, %o2 8 | -------------------------------------------------------------------------------- /capstone/suite/MC/Sparc/sparc-ctrl-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0x9f,0xc0,0x40,0x1a = call %g1+%i2 3 | 0x9f,0xc2,0x60,0x08 = call %o1+8 4 | 0x9f,0xc0,0x60,0x00 = call %g1 5 | 0x81,0xc0,0x40,0x1a = jmp %g1+%i2 6 | 0x81,0xc2,0x60,0x08 = jmp %o1+8 7 | 0x81,0xc0,0x60,0x00 = jmp %g1 8 | 0x85,0xc0,0x40,0x1a = jmpl %g1+%i2, %g2 9 | 0x85,0xc2,0x60,0x08 = jmpl %o1+8, %g2 10 | 0x85,0xc0,0x60,0x00 = jmpl %g1, %g2 11 | 0x81,0xcf,0xe0,0x08 = rett %i7+8 12 | -------------------------------------------------------------------------------- /capstone/suite/MC/Sparc/sparc-mem-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0xd4,0x4e,0x00,0x16 = ldsb [%i0+%l6], %o2 3 | 0xd4,0x4e,0x20,0x20 = ldsb [%i0+32], %o2 4 | 0xd8,0x48,0x60,0x00 = ldsb [%g1], %o4 5 | 0xd4,0x56,0x00,0x16 = ldsh [%i0+%l6], %o2 6 | 0xd4,0x56,0x20,0x20 = ldsh [%i0+32], %o2 7 | 0xd8,0x50,0x60,0x00 = ldsh [%g1], %o4 8 | 0xd4,0x0e,0x00,0x16 = ldub [%i0+%l6], %o2 9 | 0xd4,0x0e,0x20,0x20 = ldub [%i0+32], %o2 10 | 0xd4,0x08,0x60,0x00 = ldub [%g1], %o2 11 | 0xd4,0x16,0x00,0x16 = lduh [%i0+%l6], %o2 12 | 0xd4,0x16,0x20,0x20 = lduh [%i0+32], %o2 13 | 0xd4,0x10,0x60,0x00 = lduh [%g1], %o2 14 | 0xd4,0x06,0x00,0x16 = ld [%i0+%l6], %o2 15 | 0xd4,0x06,0x20,0x20 = ld [%i0+32], %o2 16 | 0xd4,0x00,0x60,0x00 = ld [%g1], %o2 17 | 0xd4,0x2e,0x00,0x16 = stb %o2, [%i0+%l6] 18 | 0xd4,0x2e,0x20,0x20 = stb %o2, [%i0+32] 19 | 0xd4,0x28,0x60,0x00 = stb %o2, [%g1] 20 | 0xd4,0x36,0x00,0x16 = sth %o2, [%i0+%l6] 21 | 0xd4,0x36,0x20,0x20 = sth %o2, [%i0+32] 22 | 0xd4,0x30,0x60,0x00 = sth %o2, [%g1] 23 | 0xd4,0x26,0x00,0x16 = st %o2, [%i0+%l6] 24 | 0xd4,0x26,0x20,0x20 = st %o2, [%i0+32] 25 | 0xd4,0x20,0x60,0x00 = st %o2, [%g1] 26 | -------------------------------------------------------------------------------- /capstone/suite/MC/Sparc/sparc-vis.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0xbf,0xb0,0x0c,0x20 = fzeros %f31 3 | -------------------------------------------------------------------------------- /capstone/suite/MC/Sparc/sparc64-alu-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0xb1,0x28,0x50,0x1a = sllx %g1, %i2, %i0 3 | 0xb1,0x28,0x70,0x3f = sllx %g1, 63, %i0 4 | 0xb1,0x30,0x50,0x1a = srlx %g1, %i2, %i0 5 | 0xb1,0x30,0x70,0x3f = srlx %g1, 63, %i0 6 | 0xb1,0x38,0x50,0x1a = srax %g1, %i2, %i0 7 | 0xb1,0x38,0x70,0x3f = srax %g1, 63, %i0 8 | 0xb0,0x48,0x40,0x1a = mulx %g1, %i2, %i0 9 | 0xb0,0x48,0x60,0x3f = mulx %g1, 63, %i0 10 | 0xb1,0x68,0x40,0x1a = sdivx %g1, %i2, %i0 11 | 0xb1,0x68,0x60,0x3f = sdivx %g1, 63, %i0 12 | 0xb0,0x68,0x40,0x1a = udivx %g1, %i2, %i0 13 | 0xb0,0x68,0x60,0x3f = udivx %g1, 63, %i0 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/Sparc/sparcv8-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | 0x81,0xa8,0x0a,0x24 = fcmps %f0, %f4 3 | 0x81,0xa8,0x0a,0x44 = fcmpd %f0, %f4 4 | 0x81,0xa8,0x0a,0x64 = fcmpq %f0, %f4 5 | 0x81,0xa8,0x0a,0xa4 = fcmpes %f0, %f4 6 | 0x81,0xa8,0x0a,0xc4 = fcmped %f0, %f4 7 | 0x81,0xa8,0x0a,0xe4 = fcmpeq %f0, %f4 8 | -------------------------------------------------------------------------------- /capstone/suite/MC/Sparc/sparcv9-instructions.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 2 | -------------------------------------------------------------------------------- /capstone/suite/MC/X86/3DNow.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT 2 | 0x0f,0x0f,0xca,0xbf = pavgusb %mm2, %mm1 3 | 0x67,0x0f,0x0f,0x5c,0x16,0x09,0xbf = pavgusb 9(%esi,%edx), %mm3 4 | 0x0f,0x0f,0xca,0x1d = pf2id %mm2, %mm1 5 | 0x67,0x0f,0x0f,0x5c,0x16,0x09,0x1d = pf2id 9(%esi,%edx), %mm3 6 | 0x0f,0x0f,0xca,0xae = pfacc %mm2, %mm1 7 | 0x0f,0x0f,0xca,0x9e = pfadd %mm2, %mm1 8 | 0x0f,0x0f,0xca,0xb0 = pfcmpeq %mm2, %mm1 9 | 0x0f,0x0f,0xca,0x90 = pfcmpge %mm2, %mm1 10 | 0x0f,0x0f,0xca,0xa0 = pfcmpgt %mm2, %mm1 11 | 0x0f,0x0f,0xca,0xa4 = pfmax %mm2, %mm1 12 | 0x0f,0x0f,0xca,0x94 = pfmin %mm2, %mm1 13 | 0x0f,0x0f,0xca,0xb4 = pfmul %mm2, %mm1 14 | 0x0f,0x0f,0xca,0x96 = pfrcp %mm2, %mm1 15 | 0x0f,0x0f,0xca,0xa6 = pfrcpit1 %mm2, %mm1 16 | 0x0f,0x0f,0xca,0xb6 = pfrcpit2 %mm2, %mm1 17 | 0x0f,0x0f,0xca,0xa7 = pfrsqit1 %mm2, %mm1 18 | 0x0f,0x0f,0xca,0x97 = pfrsqrt %mm2, %mm1 19 | 0x0f,0x0f,0xca,0x9a = pfsub %mm2, %mm1 20 | 0x0f,0x0f,0xca,0xaa = pfsubr %mm2, %mm1 21 | 0x0f,0x0f,0xca,0x0d = pi2fd %mm2, %mm1 22 | 0x0f,0x0f,0xca,0xb7 = pmulhrw %mm2, %mm1 23 | 0x0f,0x0e = femms 24 | 0x0f,0x0d,0x00 = prefetch (%eax) 25 | 0x0f,0x0f,0xca,0x1c = pf2iw %mm2, %mm1 26 | 0x0f,0x0f,0xca,0x0c = pi2fw %mm2, %mm1 27 | 0x0f,0x0f,0xca,0x8a = pfnacc %mm2, %mm1 28 | 0x0f,0x0f,0xca,0x8e = pfpnacc %mm2, %mm1 29 | 0x0f,0x0f,0xca,0xbb = pswapd %mm2, %mm1 30 | -------------------------------------------------------------------------------- /capstone/suite/MC/X86/address-size.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | 0x67,0xc6,0x06,0x00 = movb $0x0, (%esi) 3 | 0xc6,0x06,0x00 = movb $0x0, (%rsi) 4 | 0x67,0xc6,0x06,0x00 = movb $0x0, (%si) 5 | 0xc6,0x06,0x00 = movb $0x0, (%esi) 6 | -------------------------------------------------------------------------------- /capstone/suite/MC/X86/avx512-encodings.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | 0x62,0xa3,0x55,0x48,0x38,0xcd,0x01 = vinserti32x4 $1, %xmm21, %zmm5, %zmm17 3 | 0x62,0xe3,0x1d,0x40,0x38,0x4f,0x10,0x01 = vinserti32x4 $1, 256(%rdi), %zmm28, %zmm17 4 | 0x62,0x33,0x7d,0x48,0x39,0xc9,0x01 = vextracti32x4 $1, %zmm9, %xmm17 5 | 0x62,0x33,0xfd,0x48,0x3b,0xc9,0x01 = vextracti64x4 $1, %zmm9, %ymm17 6 | 0x62,0x73,0xfd,0x48,0x3b,0x4f,0x10,0x01 = vextracti64x4 $1, %zmm9, 512(%rdi) 7 | 0x62,0xb1,0x35,0x40,0x72,0xe1,0x02 = vpsrad $2, %zmm17, %zmm25 8 | 0x62,0xf1,0x35,0x40,0x72,0x64,0xb7,0x08,0x02 = vpsrad $2, 512(%rdi, %rsi, 4), %zmm25 9 | 0x62,0x21,0x1d,0x48,0xe2,0xc9 = vpsrad %xmm17, %zmm12, %zmm25 10 | 0x62,0x61,0x1d,0x48,0xe2,0x4c,0xb7,0x20 = vpsrad 512(%rdi, %rsi, 4), %zmm12, %zmm25 11 | 0x62,0xf2,0x7d,0xc9,0x58,0xc8 = vpbroadcastd %xmm0, %zmm1 {%k1} {z} 12 | 0x62,0xf1,0xfe,0x4b,0x6f,0xc8 = vmovdqu64 %zmm0, %zmm1 {%k3} 13 | -------------------------------------------------------------------------------- /capstone/suite/MC/X86/intel-syntax-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, None 2 | 0x66,0x83,0xf0,0x0c = xor ax, 12 3 | 0x83,0xf0,0x0c = xor eax, 12 4 | 0x48,0x83,0xf0,0x0c = xor rax, 12 5 | 0x66,0x83,0xc8,0x0c = or ax, 12 6 | 0x83,0xc8,0x0c = or eax, 12 7 | 0x48,0x83,0xc8,0x0c = or rax, 12 8 | 0x66,0x83,0xf8,0x0c = cmp ax, 12 9 | 0x83,0xf8,0x0c = cmp eax, 12 10 | 0x48,0x83,0xf8,0x0c = cmp rax, 12 11 | 0x48,0x89,0x44,0x24,0xf0 = mov QWORD PTR [RSP - 16], RAX 12 | 0x66,0x83,0xc0,0xf4 = add ax, -12 13 | 0x83,0xc0,0xf4 = add eax, -12 14 | 0x48,0x83,0xc0,0xf4 = add rax, -12 15 | 0x66,0x83,0xd0,0xf4 = adc ax, -12 16 | 0x83,0xd0,0xf4 = adc eax, -12 17 | 0x48,0x83,0xd0,0xf4 = adc rax, -12 18 | 0x66,0x83,0xd8,0xf4 = sbb ax, -12 19 | 0x83,0xd8,0xf4 = sbb eax, -12 20 | 0x48,0x83,0xd8,0xf4 = sbb rax, -12 21 | 0x66,0x83,0xf8,0xf4 = cmp ax, -12 22 | 0x83,0xf8,0xf4 = cmp eax, -12 23 | 0x48,0x83,0xf8,0xf4 = cmp rax, -12 24 | 0xf2,0x0f,0x10,0x2c,0x25,0xf8,0xff,0xff,0xff = movsd XMM5, QWORD PTR [-8] 25 | 0xd1,0xe7 = shl EDI, 1 26 | 0x0f,0xc2,0xd1,0x01 = cmpltps XMM2, XMM1 27 | 0xc3 = ret 28 | 0xcb = retf 29 | 0xc2,0x08,0x00 = ret 8 30 | 0xca,0x08,0x00 = retf 8 31 | -------------------------------------------------------------------------------- /capstone/suite/MC/X86/x86-32-ms-inline-asm.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT 2 | 0x8b,0x03 = movl (%ebx), %eax 3 | 0x89,0x4b,0x04 = movl %ecx, 4(%ebx) 4 | 0x8b,0x04,0x85,0x04,0x00,0x00,0x00 = movl 4(, %eax, 4), %eax 5 | 0x8b,0x04,0x85,0x04,0x00,0x00,0x00 = movl 4(, %eax, 4), %eax 6 | 0x8b,0x04,0x06 = movl (%esi, %eax), %eax 7 | 0x8b,0x04,0x06 = movl (%esi, %eax), %eax 8 | 0x8b,0x04,0x86 = movl (%esi, %eax, 4), %eax 9 | 0x8b,0x04,0x86 = movl (%esi, %eax, 4), %eax 10 | 0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax 11 | 0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax 12 | 0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax 13 | 0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax 14 | 0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax 15 | 0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax 16 | 0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax 17 | 0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax 18 | 0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax 19 | 0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax 20 | 0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax 21 | 0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax 22 | 0x8b,0x44,0x46,0x10 = movl 16(%esi, %eax, 2), %eax 23 | 0x0f,0x18,0x40,0x40 = prefetchnta 64(%eax) 24 | 0x60 = pushal 25 | 0x61 = popal 26 | 0x60 = pushal 27 | 0x61 = popal 28 | -------------------------------------------------------------------------------- /capstone/suite/MC/X86/x86_64-avx-clmul-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | 0xc4,0x43,0x29,0x44,0xdc,0x11 = vpclmulhqhqdq %xmm12, %xmm10, %xmm11 3 | 0xc4,0x63,0x29,0x44,0x28,0x11 = vpclmulhqhqdq (%rax), %xmm10, %xmm13 4 | 0xc4,0x43,0x29,0x44,0xdc,0x01 = vpclmulhqlqdq %xmm12, %xmm10, %xmm11 5 | 0xc4,0x63,0x29,0x44,0x28,0x01 = vpclmulhqlqdq (%rax), %xmm10, %xmm13 6 | 0xc4,0x43,0x29,0x44,0xdc,0x10 = vpclmullqhqdq %xmm12, %xmm10, %xmm11 7 | 0xc4,0x63,0x29,0x44,0x28,0x10 = vpclmullqhqdq (%rax), %xmm10, %xmm13 8 | 0xc4,0x43,0x29,0x44,0xdc,0x00 = vpclmullqlqdq %xmm12, %xmm10, %xmm11 9 | 0xc4,0x63,0x29,0x44,0x28,0x00 = vpclmullqlqdq (%rax), %xmm10, %xmm13 10 | 0xc4,0x43,0x29,0x44,0xdc,0x11 = vpclmulqdq $17, %xmm12, %xmm10, %xmm11 11 | 0xc4,0x63,0x29,0x44,0x28,0x11 = vpclmulqdq $17, (%rax), %xmm10, %xmm13 12 | -------------------------------------------------------------------------------- /capstone/suite/MC/X86/x86_64-hle-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, None 2 | 0xf2 = repne 3 | 0xf3 = rep 4 | -------------------------------------------------------------------------------- /capstone/suite/MC/X86/x86_64-imm-widths.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | 0x04,0x00 = addb $0x00, %al 3 | 0x04,0x7f = addb $0x7F, %al 4 | 0x04,0x80 = addb $0x80, %al 5 | 0x04,0xff = addb $0xFF, %al 6 | 0x66,0x83,0xc0,0x00 = addw $0x0000, %ax 7 | 0x66,0x83,0xc0,0x7f = addw $0x007F, %ax 8 | 0x66,0x83,0xc0,0x80 = addw $0x80, %ax 9 | 0x66,0x83,0xc0,0xff = addw $0xFFFF, %ax 10 | 0x83,0xc0,0x00 = addl $0x00000000, %eax 11 | 0x83,0xc0,0x7f = addl $0x0000007F, %eax 12 | 0x05,0x80,0xff,0x00,0x00 = addl $0xFF80, %eax 13 | 0x05,0xff,0xff,0x00,0x00 = addl $0xFFFF, %eax 14 | 0x83,0xc0,0x80 = addl $0xFFFFFF80, %eax 15 | 0x83,0xc0,0xff = addl $0xFFFFFFFF, %eax 16 | 0x48,0x83,0xc0,0x00 = addq $0x0000000000000000, %rax 17 | 0x48,0x83,0xc0,0x7f = addq $0x000000000000007F, %rax 18 | 0x48,0x83,0xc0,0x80 = addq $0xFFFFFFFFFFFFFF80, %rax 19 | 0x48,0x83,0xc0,0xff = addq $0xFFFFFFFFFFFFFFFF, %rax 20 | 0x48,0x83,0xc0,0x00 = addq $0x0000000000000000, %rax 21 | 0x48,0x05,0x80,0xff,0x00,0x00 = addq $0xFF80, %rax 22 | 0x48,0x05,0xff,0xff,0x00,0x00 = addq $0xFFFF, %rax 23 | 0x48,0xb8,0x80,0xff,0xff,0xff,0x00,0x00,0x00,0x00 = movabsq $0xFFFFFF80, %rax 24 | 0x48,0xb8,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00 = movabsq $0xFFFFFFFF, %rax 25 | 0x48,0x05,0xff,0xff,0xff,0x7f = addq $0x000000007FFFFFFF, %rax 26 | 0x48,0x05,0x00,0x00,0x00,0x80 = addq $0xFFFFFFFF80000000, %rax 27 | 0x48,0x05,0x00,0xff,0xff,0xff = addq $0xFFFFFFFFFFFFFF00, %rax 28 | -------------------------------------------------------------------------------- /capstone/suite/MC/X86/x86_64-rand-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | 0x66,0x0f,0xc7,0xf0 = rdrandw %ax 3 | 0x0f,0xc7,0xf0 = rdrandl %eax 4 | 0x48,0x0f,0xc7,0xf0 = rdrandq %rax 5 | 0x66,0x41,0x0f,0xc7,0xf3 = rdrandw %r11w 6 | 0x41,0x0f,0xc7,0xf3 = rdrandl %r11d 7 | 0x49,0x0f,0xc7,0xf3 = rdrandq %r11 8 | 0x66,0x0f,0xc7,0xf8 = rdseedw %ax 9 | 0x0f,0xc7,0xf8 = rdseedl %eax 10 | 0x48,0x0f,0xc7,0xf8 = rdseedq %rax 11 | 0x66,0x41,0x0f,0xc7,0xfb = rdseedw %r11w 12 | 0x41,0x0f,0xc7,0xfb = rdseedl %r11d 13 | 0x49,0x0f,0xc7,0xfb = rdseedq %r11 14 | -------------------------------------------------------------------------------- /capstone/suite/MC/X86/x86_64-rtm-encoding.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | 0x0f,0x01,0xd5 = xend 3 | 0x0f,0x01,0xd6 = xtest 4 | 0xc6,0xf8,0x0d = xabort $13 5 | -------------------------------------------------------------------------------- /capstone/suite/MC/X86/x86_64-sse4a.s.cs: -------------------------------------------------------------------------------- 1 | # CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 2 | -------------------------------------------------------------------------------- /capstone/suite/README: -------------------------------------------------------------------------------- 1 | This directory contains some tools used by developers of Capstone project. 2 | Average users should ignore all the contents here. 3 | 4 | 5 | - arm/ 6 | Test some ARM's special input. 7 | 8 | - MC/ 9 | Input used to test various architectures & modes. 10 | 11 | - benchmark.py 12 | This script benchmarks Python binding by disassembling some random code. 13 | 14 | - test_*.sh 15 | Run all the tests and send the output to external file to be compared later. 16 | This is useful when we want to verify if a commit (wrongly) changes 17 | the disassemble result. 18 | 19 | - compile_all.sh 20 | Compile Capstone for all platforms (*nix32, clang, cygwin, cross-compile) & 21 | report the result as pass or fail. 22 | 23 | - fuzz.py 24 | This simple script disassembles random code for all archs (or selected arch) 25 | in order to find segfaults. 26 | 27 | - test_mc.sh 28 | This script compares the output of Capstone with LLVM's llvm-mc with the 29 | input coming from MC/. This relies on test_mc.py to do all the hard works. 30 | 31 | - x86odd.py 32 | Test some tricky X86 instructions. 33 | 34 | - ppcbranch.py 35 | Test some tricky branch PPC instructions. 36 | -------------------------------------------------------------------------------- /capstone/suite/arm/Makefile: -------------------------------------------------------------------------------- 1 | # Sample Makefile for Capstone Disassembly Engine 2 | 3 | LIBNAME = capstone 4 | 5 | test_arm_regression: test_arm_regression.o 6 | ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@ 7 | 8 | %.o: %.c 9 | ${CC} -c -I../../include $< -o $@ 10 | 11 | clean: 12 | rm -rf *.o test_arm_regression 13 | -------------------------------------------------------------------------------- /capstone/suite/benchmark/Makefile: -------------------------------------------------------------------------------- 1 | # Sample Makefile for Capstone Disassembly Engine 2 | 3 | LIBNAME = capstone 4 | 5 | test_iter_benchmark: test_iter_benchmark.o 6 | ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@ 7 | 8 | %.o: %.c 9 | ${CC} -c -I../../include $< -o $@ 10 | 11 | clean: 12 | rm -rf *.o test_iter_benchmark 13 | -------------------------------------------------------------------------------- /capstone/suite/compile_all.sh: -------------------------------------------------------------------------------- 1 | #! /bin/bash 2 | # By Daniel Godas-Lopez. 3 | 4 | export LD_LIBRARY_PATH=. 5 | 6 | for x in default nix32 cross-win32 cross-win64 cygwin-mingw32 cygwin-mingw64 bsd clang gcc; do 7 | echo -n "Compiling: $x ... " 8 | ./compile.sh $x &> /dev/null 9 | 10 | if [ $? == 0 ]; then 11 | echo "-> PASS" 12 | else 13 | echo -e "-> FAILED\n" 14 | continue 15 | fi 16 | 17 | for t in test test_arm test_arm64 test_detail test_mips test_x86 test_ppc; do 18 | ./tests/$t &> /dev/null 19 | 20 | if [ $? -eq 0 ]; then 21 | echo " Run $t -> PASS" 22 | else 23 | echo " Run $t -> FAIL" 24 | fi 25 | done 26 | 27 | echo 28 | done 29 | 30 | make clean &> /dev/null 31 | -------------------------------------------------------------------------------- /capstone/suite/fuzz/Makefile: -------------------------------------------------------------------------------- 1 | LIBNAME = capstone 2 | 3 | fuzz_harness: fuzz_harness.o 4 | ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@ 5 | 6 | %.o: %.c 7 | ${CC} -c -I../../include $< -o $@ 8 | 9 | clean: 10 | rm -rf *.o fuzz_harness 11 | -------------------------------------------------------------------------------- /capstone/suite/fuzz/README: -------------------------------------------------------------------------------- 1 | This directory contains a fuzz testing harness for Capstone. 2 | Run "make" to compile this code. 3 | -------------------------------------------------------------------------------- /capstone/suite/patch_major_os_version.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | # By Daniel Pistelli & Nguyen Tan Cong 3 | 4 | # This script is to patch DLL/EXE MajorVersion to 5, 5 | # so they can be loaded by Windows XP. 6 | # This is the problem introduced by compiling on Windows 7, using VS2013. 7 | 8 | import sys, struct 9 | 10 | if len(sys.argv) < 2: 11 | print("Usage: %s " % sys.argv[0]) 12 | sys.exit(0) 13 | 14 | pe_file_path = sys.argv[1] 15 | 16 | with open(pe_file_path, "rb") as f: 17 | b = f.read() 18 | 19 | if not b.startswith("MZ"): 20 | print("Not a PE file") 21 | sys.exit(0) 22 | 23 | e_lfanew = struct.unpack_from(" 2 | 3 | #define BINARY "\x3b\x30\x62\x93\x5d\x61\x03\xe8" 4 | 5 | int main(int argc, char **argv, char **envp) { 6 | csh handle; 7 | if (cs_open(CS_ARCH_X86, CS_MODE_64, &handle)) { 8 | printf("cs_open(…) failed\n"); 9 | return 1; 10 | } 11 | cs_insn *insn; 12 | cs_disasm(handle, (uint8_t *)BINARY, sizeof(BINARY) - 1, 0x1000, 0, &insn); 13 | return 0; 14 | } 15 | -------------------------------------------------------------------------------- /capstone/suite/test_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # dump test output to /tmp/ for diffing 4 | # this is useful to detect if a change modifies any disasm output 5 | 6 | # syntax: test_all.sh 7 | 8 | ./test_archs.py > /tmp/$1_arch 9 | ./test_c.sh $1_c 10 | -------------------------------------------------------------------------------- /capstone/suite/test_c.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Run all the Python tests, and send the output that to a file to be compared later 4 | # This is useful when we want to verify if a commit (wrongly) changes the disassemble result. 5 | 6 | ../tests/test > /tmp/$1 7 | ../tests/test_detail >> /tmp/$1 8 | ../tests/test_skipdata >> /tmp/$1 9 | ../tests/test_iter >> /tmp/$1 10 | ../tests/test_arm >> /tmp/$1 11 | ../tests/test_arm64 >> /tmp/$1 12 | ../tests/test_mips >> /tmp/$1 13 | ../tests/test_ppc >> /tmp/$1 14 | ../tests/test_sparc >> /tmp/$1 15 | ../tests/test_x86 >> /tmp/$1 16 | ../tests/test_systemz >> /tmp/$1 17 | ../tests/test_xcore >> /tmp/$1 18 | -------------------------------------------------------------------------------- /capstone/suite/test_mc.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # This script test all architectures by default. 4 | # At the output are all the mismatches between Capstone (CS) & LLVM (MC). 5 | # While most differences coming from the fact that Capstone uses more friendly 6 | # number format, some mismatches might be because Capstone is based on older 7 | # version of LLVM (which should be fixed in the next release) 8 | 9 | find MC/ -name *.cs | ./test_mc.py 10 | 11 | # To test just one architecture, specify the corresponsing dir: 12 | # $ find MC/X86 -name *.cs | ./test_mc.py 13 | 14 | # To test just one input file, run test_mc.py with that file: 15 | # $ ./test_mc.py MC/X86/x86-32-fma3.s.cs 16 | -------------------------------------------------------------------------------- /capstone/suite/test_python.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Run all the Python tests, and send the output that to a file to be compared later 4 | # This is useful when we want to verify if a commit (wrongly) changes the disassemble result. 5 | 6 | ../bindings/python/test.py > /tmp/$1 7 | ../bindings/python/test_detail.py >> /tmp/$1 8 | ../bindings/python/test_arm.py >> /tmp/$1 9 | ../bindings/python/test_arm64.py >> /tmp/$1 10 | ../bindings/python/test_mips.py >> /tmp/$1 11 | ../bindings/python/test_ppc.py >> /tmp/$1 12 | ../bindings/python/test_sparc.py >> /tmp/$1 13 | ../bindings/python/test_x86.py >> /tmp/$1 14 | -------------------------------------------------------------------------------- /capstone/tests/README: -------------------------------------------------------------------------------- 1 | This directory contains some test code to show how to use Capstone API. 2 | 3 | - test.c 4 | This code shows the most simple form of API where we only want to get basic 5 | information out of disassembled instruction, such as address, mnemonic and 6 | operand string. 7 | 8 | - test_detail.c: 9 | This code shows how to access to architecture-neutral information in disassembled 10 | instructions, such as implicit registers read/written, or groups of instructions 11 | that this instruction belong to. 12 | 13 | - test_skipdata.c: 14 | This code shows how to use SKIPDATA option to skip broken instructions (most likely 15 | some data mixed with instructions) and continue to decode at the next legitimate 16 | instructions. 17 | 18 | - test_iter.c: 19 | This code shows how to use the API cs_disasm_iter() to decode one instruction at 20 | a time inside a loop. 21 | 22 | - test_.c 23 | These code show how to access architecture-specific information for each 24 | architecture. 25 | 26 | - test_winkernel.cpp 27 | This code shows how to use Capstone from a Windows driver. 28 | -------------------------------------------------------------------------------- /capstone/windows/README: -------------------------------------------------------------------------------- 1 | This directory contains code specific to Windows platforms. 2 | -------------------------------------------------------------------------------- /capstone/windows/winkernel_mm.h: -------------------------------------------------------------------------------- 1 | /* Capstone Disassembly Engine */ 2 | /* By Satoshi Tanda , 2016 */ 3 | 4 | #ifndef CS_WINDOWS_WINKERNEL_MM_H 5 | #define CS_WINDOWS_WINKERNEL_MM_H 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include 12 | 13 | void CAPSTONE_API cs_winkernel_free(void *ptr); 14 | void * CAPSTONE_API cs_winkernel_malloc(size_t size); 15 | void * CAPSTONE_API cs_winkernel_calloc(size_t n, size_t size); 16 | void * CAPSTONE_API cs_winkernel_realloc(void *ptr, size_t size); 17 | int CAPSTONE_API cs_winkernel_vsnprintf(char *buffer, size_t count, const char *format, va_list argptr); 18 | 19 | #ifdef __cplusplus 20 | } 21 | #endif 22 | 23 | #endif // CS_WINDOWS_WINKERNEL_MM_H 24 | -------------------------------------------------------------------------------- /capstone/xcode/Capstone.xcodeproj/project.xcworkspace/contents.xcworkspacedata: -------------------------------------------------------------------------------- 1 | 2 | 4 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /capstone/xcode/CapstoneFramework/Info.plist: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | CFBundleDevelopmentRegion 6 | en 7 | CFBundleExecutable 8 | $(EXECUTABLE_NAME) 9 | CFBundleIdentifier 10 | com.felixcloutier.$(PRODUCT_NAME:rfc1034identifier) 11 | CFBundleInfoDictionaryVersion 12 | 6.0 13 | CFBundleName 14 | $(PRODUCT_NAME) 15 | CFBundlePackageType 16 | FMWK 17 | CFBundleShortVersionString 18 | 1.0 19 | CFBundleSignature 20 | ???? 21 | CFBundleVersion 22 | $(CURRENT_PROJECT_VERSION) 23 | NSPrincipalClass 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /clean.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | del *.sdf 3 | del *.VC.db 4 | del /s *.aps 5 | del /a:h *.suo 6 | rmdir /s /q .vs 7 | rmdir /s /q ipch 8 | rmdir /s /q x64 9 | rmdir /s /q Debug 10 | rmdir /s /q Debug_WDK 11 | rmdir /s /q Release 12 | rmdir /s /q Release_WDK 13 | rmdir /s /q DdiMon\x64 14 | rmdir /s /q DdiMon\Debug 15 | rmdir /s /q DdiMon\Release 16 | cd HyperPlatform 17 | clean.bat 18 | --------------------------------------------------------------------------------