├── README.md ├── driver └── spi.c └── include └── driver ├── spi.h └── spi_register.h /README.md: -------------------------------------------------------------------------------- 1 | ESP8266 SPI Driver 2 | ======== 3 | 4 | Some general information about the SPI hardware and my investigations into the control registers are on http://d.av.id.au/blog/ for those who want a deeper insight into how the code works. 5 | 6 | HSPI Hardware Pins 7 | ======== 8 | 9 | |Pin Name| GPIO # | HSPI Function | 10 | |--------|--------|---------------| 11 | |MTDI | GPIO12 | MISO (DIN) | 12 | |MTCK | GPIO13 | MOSI (DOUT) | 13 | |MTMS | GPIO14 | CLOCK | 14 | |MTDO | GPIO15 | CS / SS | 15 | 16 | Main SPI Transaction Function 17 | ======== 18 | Perform an SPI transaction. 19 | 20 | spi_transaction(spi_no, cmd_bits, cmd_data, addr_bits, addr_data, dout_bits, dout_data, din_bits, dummy_bits) 21 | 22 | spi_no: SPI or HSPI 23 | 24 | cmd_bits: length of command. Set to 0 to disable command component. 25 | 26 | cmd_data: Command data to send. 27 | 28 | addr_bits: length of address. Set to 0 to disable address component. 29 | 30 | addr_data: Address data to send. 31 | 32 | dout_bits: Length of data payload to send. Set to 0 to disable data out component. 33 | 34 | dout_data: Data payload to send. 35 | 36 | din_bits: Length of data payload to receive. Set to 0 if not receiving any data. 37 | 38 | dummy_bits: Number of dummy bits to insert. 39 | 40 | Data Structure of SPI Transaction 41 | 42 | [COMMAND]+[ADDRESS]+[DataOUT]+[DUMMYBITS]+[DataIN] 43 | 44 | If no data is set to be received, then the Dummy bits are inserted before DataOUT. 45 | 46 | [COMMAND]+[ADDRESS]+[DUMMYBITS]+[DataOUT] 47 | 48 | Example: 49 | 50 | 51 | Writing data to EEPROM 52 | 53 | Command = 0b101 (3 bit write command) 54 | 55 | Address = 0b111110011 or 0x1F3 (9 bit data address) 56 | 57 | Data = 0b11001100 or 0xCC (8 bits of data) 58 | 59 | SPI Transaction Packet = 0b10111111001111001100 or 0xBF3CC 60 | 61 | spi_transaction(HSPI, 3, 0b101, 9, 0x1F3, 8, 0xCC, 0, 0); 62 | 63 | 64 | Reading data from EEPROM 65 | 66 | Command = 0b110 (3 bit read command) 67 | 68 | Address = 0b111110011 or 0x1F3 (9 bit data address) 69 | 70 | (8 bits of data to read) 71 | 72 | SPI Transaction Packet = 0b11011111001100000000 or 0xDF300 //last 8 zeros are to clock 8 bits from the EEPROM 73 | 74 | data_read = (uint8) spi_transaction(HSPI, 3, 0b101, 9, 0x1F3, 0, 0, 8, 0); 75 | 76 | 77 | Basic Transmit Functions 78 | ======== 79 | 80 | Send 'n' bits of data: 81 | spi_txd(spi_no, bits, data) 82 | 83 | Send 8 bits of data (1 BYTE): 84 | spi_tx8(spi_no, data) 85 | 86 | Send 16 bits of data (1 WORD): 87 | spi_tx16(spi_no, data) 88 | 89 | Send 32 bits of data (1 DWORD): 90 | spi_tx32(spi_no, data) 91 | 92 | Example: 93 | 94 | uint8 byte = 0xEF; 95 | 96 | uint16 word = 0xBEEF; 97 | 98 | uint32 dword = 0xDEADBEEF; 99 | 100 | uint16 9bit = 0b101010101; 101 | 102 | spi_tx8(HSPI, byte); 103 | 104 | spi_tx16(HSPI, word); 105 | 106 | spi_tx32(HSPI, dword); 107 | 108 | spi_txd(HSPI, 9, 9bit); 109 | 110 | 111 | Basic Receive Functions 112 | ======== 113 | 114 | Receive 'n' bits of data: 115 | spi_rxd(spi_no, bits) 116 | 117 | Receive 8 bits of data (1 BYTE): 118 | spi_rx8(spi_no) 119 | 120 | Receive 16 bits of data (1 WORD): 121 | spi_rx16(spi_no) 122 | 123 | Receive 32 bits of data (1 DWORD): 124 | spi_rx32(spi_no) 125 | 126 | Example: 127 | 128 | uint8 byte; 129 | 130 | uint16 word; 131 | 132 | uint32 dword; 133 | 134 | uint16 9bit; 135 | 136 | byte = (uint8) spi_rx8(HSPI); //returned value is uint32. Cast to uint8 137 | 138 | word = (uint16) spi_rx16(HSPI); //returned value is uint32. Cast to uint16 139 | 140 | dword = spi_rx32(HSPI); //No type casting needed 141 | 142 | 9bit = (uint16) spi_rxd(HSPI, 9); //returned value is uint32. Cast to uint16 143 | 144 | 145 | 146 | -------------------------------------------------------------------------------- /driver/spi.c: -------------------------------------------------------------------------------- 1 | /* 2 | * The MIT License (MIT) 3 | * 4 | * Copyright (c) 2015 David Ogilvy (MetalPhreak) 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | * 13 | * The above copyright notice and this permission notice shall be included in all 14 | * copies or substantial portions of the Software. 15 | * 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | * SOFTWARE. 23 | */ 24 | 25 | 26 | #include "driver/spi.h" 27 | 28 | 29 | //////////////////////////////////////////////////////////////////////////////// 30 | // 31 | // Function Name: spi_init 32 | // Description: Wrapper to setup HSPI/SPI GPIO pins and default SPI clock 33 | // Parameters: spi_no - SPI (0) or HSPI (1) 34 | // 35 | //////////////////////////////////////////////////////////////////////////////// 36 | 37 | void spi_init(uint8 spi_no){ 38 | 39 | if(spi_no > 1) return; //Only SPI and HSPI are valid spi modules. 40 | 41 | spi_init_gpio(spi_no, SPI_CLK_USE_DIV); 42 | spi_clock(spi_no, SPI_CLK_PREDIV, SPI_CLK_CNTDIV); 43 | spi_tx_byte_order(spi_no, SPI_BYTE_ORDER_HIGH_TO_LOW); 44 | spi_rx_byte_order(spi_no, SPI_BYTE_ORDER_HIGH_TO_LOW); 45 | 46 | SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CS_SETUP|SPI_CS_HOLD); 47 | CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_FLASH_MODE); 48 | 49 | } 50 | 51 | //////////////////////////////////////////////////////////////////////////////// 52 | 53 | //////////////////////////////////////////////////////////////////////////////// 54 | // 55 | // Function Name: spi_mode 56 | // Description: Configures SPI mode parameters for clock edge and clock polarity. 57 | // Parameters: spi_no - SPI (0) or HSPI (1) 58 | // spi_cpha - (0) Data is valid on clock leading edge 59 | // (1) Data is valid on clock trailing edge 60 | // spi_cpol - (0) Clock is low when inactive 61 | // (1) Clock is high when inactive 62 | // 63 | //////////////////////////////////////////////////////////////////////////////// 64 | 65 | void spi_mode(uint8 spi_no, uint8 spi_cpha,uint8 spi_cpol){ 66 | if(!spi_cpha == !spi_cpol) { 67 | CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_CK_OUT_EDGE); 68 | } else { 69 | SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CK_OUT_EDGE); 70 | } 71 | 72 | if (spi_cpol) { 73 | SET_PERI_REG_MASK(SPI_PIN(spi_no), SPI_IDLE_EDGE); 74 | } else { 75 | CLEAR_PERI_REG_MASK(SPI_PIN(spi_no), SPI_IDLE_EDGE); 76 | } 77 | } 78 | 79 | 80 | //////////////////////////////////////////////////////////////////////////////// 81 | 82 | //////////////////////////////////////////////////////////////////////////////// 83 | // 84 | // Function Name: spi_init_gpio 85 | // Description: Initialises the GPIO pins for use as SPI pins. 86 | // Parameters: spi_no - SPI (0) or HSPI (1) 87 | // sysclk_as_spiclk - SPI_CLK_80MHZ_NODIV (1) if using 80MHz 88 | // sysclock for SPI clock. 89 | // SPI_CLK_USE_DIV (0) if using divider to 90 | // get lower SPI clock speed. 91 | // 92 | //////////////////////////////////////////////////////////////////////////////// 93 | 94 | void spi_init_gpio(uint8 spi_no, uint8 sysclk_as_spiclk){ 95 | 96 | // if(spi_no > 1) return; //Not required. Valid spi_no is checked with if/elif below. 97 | 98 | uint32 clock_div_flag = 0; 99 | if(sysclk_as_spiclk){ 100 | clock_div_flag = 0x0001; 101 | } 102 | 103 | if(spi_no==SPI){ 104 | WRITE_PERI_REG(PERIPHS_IO_MUX, 0x005|(clock_div_flag<<8)); //Set bit 8 if 80MHz sysclock required 105 | PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, 1); 106 | PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 1); 107 | PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, 1); 108 | PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, 1); 109 | }else if(spi_no==HSPI){ 110 | WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105|(clock_div_flag<<9)); //Set bit 9 if 80MHz sysclock required 111 | PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2); //GPIO12 is HSPI MISO pin (Master Data In) 112 | PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2); //GPIO13 is HSPI MOSI pin (Master Data Out) 113 | PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2); //GPIO14 is HSPI CLK pin (Clock) 114 | PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, 2); //GPIO15 is HSPI CS pin (Chip Select / Slave Select) 115 | } 116 | 117 | } 118 | 119 | //////////////////////////////////////////////////////////////////////////////// 120 | 121 | //////////////////////////////////////////////////////////////////////////////// 122 | // 123 | // Function Name: spi_clock 124 | // Description: sets up the control registers for the SPI clock 125 | // Parameters: spi_no - SPI (0) or HSPI (1) 126 | // prediv - predivider value (actual division value) 127 | // cntdiv - postdivider value (actual division value) 128 | // Set either divider to 0 to disable all division (80MHz sysclock) 129 | // 130 | //////////////////////////////////////////////////////////////////////////////// 131 | 132 | void spi_clock(uint8 spi_no, uint16 prediv, uint8 cntdiv){ 133 | 134 | if(spi_no > 1) return; 135 | 136 | if((prediv==0)|(cntdiv==0)){ 137 | 138 | WRITE_PERI_REG(SPI_CLOCK(spi_no), SPI_CLK_EQU_SYSCLK); 139 | 140 | } else { 141 | 142 | WRITE_PERI_REG(SPI_CLOCK(spi_no), 143 | (((prediv-1)&SPI_CLKDIV_PRE)<>1)&SPI_CLKCNT_H)< 1) return; 174 | 175 | if(byte_order){ 176 | SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_WR_BYTE_ORDER); 177 | } else { 178 | CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_WR_BYTE_ORDER); 179 | } 180 | } 181 | //////////////////////////////////////////////////////////////////////////////// 182 | 183 | //////////////////////////////////////////////////////////////////////////////// 184 | // 185 | // Function Name: spi_rx_byte_order 186 | // Description: Setup the byte order for shifting data into buffer 187 | // Parameters: spi_no - SPI (0) or HSPI (1) 188 | // byte_order - SPI_BYTE_ORDER_HIGH_TO_LOW (1) 189 | // Data is read in starting with Bit31 and down to Bit0 190 | // 191 | // SPI_BYTE_ORDER_LOW_TO_HIGH (0) 192 | // Data is read in starting with the lowest BYTE, from 193 | // MSB to LSB, followed by the second lowest BYTE, from 194 | // MSB to LSB, followed by the second highest BYTE, from 195 | // MSB to LSB, followed by the highest BYTE, from MSB to LSB 196 | // 0xABCDEFGH would be read as 0xGHEFCDAB 197 | // 198 | // 199 | //////////////////////////////////////////////////////////////////////////////// 200 | 201 | void spi_rx_byte_order(uint8 spi_no, uint8 byte_order){ 202 | 203 | if(spi_no > 1) return; 204 | 205 | if(byte_order){ 206 | SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_RD_BYTE_ORDER); 207 | } else { 208 | CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_RD_BYTE_ORDER); 209 | } 210 | } 211 | //////////////////////////////////////////////////////////////////////////////// 212 | 213 | //////////////////////////////////////////////////////////////////////////////// 214 | // 215 | // Function Name: spi_transaction 216 | // Description: SPI transaction function 217 | // Parameters: spi_no - SPI (0) or HSPI (1) 218 | // cmd_bits - actual number of bits to transmit 219 | // cmd_data - command data 220 | // addr_bits - actual number of bits to transmit 221 | // addr_data - address data 222 | // dout_bits - actual number of bits to transmit 223 | // dout_data - output data 224 | // din_bits - actual number of bits to receive 225 | // 226 | // Returns: read data - uint32 containing read in data only if RX was set 227 | // 0 - something went wrong (or actual read data was 0) 228 | // 1 - data sent ok (or actual read data is 1) 229 | // Note: all data is assumed to be stored in the lower bits of 230 | // the data variables (for anything <32 bits). 231 | // 232 | //////////////////////////////////////////////////////////////////////////////// 233 | 234 | uint32 spi_transaction(uint8 spi_no, uint8 cmd_bits, uint16 cmd_data, uint32 addr_bits, uint32 addr_data, uint32 dout_bits, uint32 dout_data, 235 | uint32 din_bits, uint32 dummy_bits){ 236 | 237 | if(spi_no > 1) return 0; //Check for a valid SPI 238 | 239 | //code for custom Chip Select as GPIO PIN here 240 | 241 | while(spi_busy(spi_no)); //wait for SPI to be ready 242 | 243 | //########## Enable SPI Functions ##########// 244 | //disable MOSI, MISO, ADDR, COMMAND, DUMMY in case previously set. 245 | CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MOSI|SPI_USR_MISO|SPI_USR_COMMAND|SPI_USR_ADDR|SPI_USR_DUMMY); 246 | 247 | //enable functions based on number of bits. 0 bits = disabled. 248 | //This is rather inefficient but allows for a very generic function. 249 | //CMD ADDR and MOSI are set below to save on an extra if statement. 250 | // if(cmd_bits) {SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_COMMAND);} 251 | // if(addr_bits) {SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_ADDR);} 252 | if(din_bits) {SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MISO);} 253 | if(dummy_bits) {SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_DUMMY);} 254 | //########## END SECTION ##########// 255 | 256 | //########## Setup Bitlengths ##########// 257 | WRITE_PERI_REG(SPI_USER1(spi_no), ((addr_bits-1)&SPI_USR_ADDR_BITLEN)<>8)&0xff) | ((command<<8)&0xff00); //swap byte order 268 | WRITE_PERI_REG(SPI_USER2(spi_no), ((((cmd_bits-1)&SPI_USR_COMMAND_BITLEN)<>(32-(dout_bits - dout_extra_bits)))&dout_data)); 298 | } else { 299 | WRITE_PERI_REG(SPI_W0(spi_no), dout_data); 300 | } 301 | } 302 | } 303 | //########## END SECTION ##########// 304 | 305 | //########## Begin SPI Transaction ##########// 306 | SET_PERI_REG_MASK(SPI_CMD(spi_no), SPI_USR); 307 | //########## END SECTION ##########// 308 | 309 | //########## Return DIN data ##########// 310 | if(din_bits) { 311 | while(spi_busy(spi_no)); //wait for SPI transaction to complete 312 | 313 | if(READ_PERI_REG(SPI_USER(spi_no))&SPI_RD_BYTE_ORDER) { 314 | return READ_PERI_REG(SPI_W0(spi_no)) >> (32-din_bits); //Assuming data in is written to MSB. TBC 315 | } else { 316 | return READ_PERI_REG(SPI_W0(spi_no)); //Read in the same way as DOUT is sent. Note existing contents of SPI_W0 remain unless overwritten! 317 | } 318 | 319 | return 0; //something went wrong 320 | } 321 | //########## END SECTION ##########// 322 | 323 | //Transaction completed 324 | return 1; //success 325 | } 326 | 327 | //////////////////////////////////////////////////////////////////////////////// 328 | 329 | /*/////////////////////////////////////////////////////////////////////////////// 330 | // 331 | // Function Name: func 332 | // Description: 333 | // Parameters: 334 | // 335 | //////////////////////////////////////////////////////////////////////////////// 336 | 337 | void func(params){ 338 | 339 | } 340 | 341 | ///////////////////////////////////////////////////////////////////////////////*/ 342 | 343 | 344 | -------------------------------------------------------------------------------- /include/driver/spi.h: -------------------------------------------------------------------------------- 1 | /* 2 | * The MIT License (MIT) 3 | * 4 | * Copyright (c) 2015 David Ogilvy (MetalPhreak) 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | * 13 | * The above copyright notice and this permission notice shall be included in all 14 | * copies or substantial portions of the Software. 15 | * 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | * SOFTWARE. 23 | */ 24 | 25 | #ifndef SPI_APP_H 26 | #define SPI_APP_H 27 | 28 | #include "spi_register.h" 29 | #include "ets_sys.h" 30 | #include "osapi.h" 31 | //#include "uart.h" 32 | #include "os_type.h" 33 | 34 | //Define SPI hardware modules 35 | #define SPI 0 36 | #define HSPI 1 37 | 38 | #define SPI_CLK_USE_DIV 0 39 | #define SPI_CLK_80MHZ_NODIV 1 40 | 41 | #define SPI_BYTE_ORDER_HIGH_TO_LOW 1 42 | #define SPI_BYTE_ORDER_LOW_TO_HIGH 0 43 | 44 | #ifndef CPU_CLK_FREQ //Should already be defined in eagle_soc.h 45 | #define CPU_CLK_FREQ 80*1000000 46 | #endif 47 | 48 | //Define some default SPI clock settings 49 | #define SPI_CLK_PREDIV 10 50 | #define SPI_CLK_CNTDIV 2 51 | #define SPI_CLK_FREQ CPU_CLK_FREQ/(SPI_CLK_PREDIV*SPI_CLK_CNTDIV) // 80 / 20 = 4 MHz 52 | 53 | 54 | 55 | 56 | 57 | void spi_init(uint8 spi_no); 58 | void spi_mode(uint8 spi_no, uint8 spi_cpha,uint8 spi_cpol); 59 | void spi_init_gpio(uint8 spi_no, uint8 sysclk_as_spiclk); 60 | void spi_clock(uint8 spi_no, uint16 prediv, uint8 cntdiv); 61 | void spi_tx_byte_order(uint8 spi_no, uint8 byte_order); 62 | void spi_rx_byte_order(uint8 spi_no, uint8 byte_order); 63 | uint32 spi_transaction(uint8 spi_no, uint8 cmd_bits, uint16 cmd_data, uint32 addr_bits, uint32 addr_data, uint32 dout_bits, uint32 dout_data, uint32 din_bits, uint32 dummy_bits); 64 | 65 | //Expansion Macros 66 | #define spi_busy(spi_no) READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR 67 | 68 | #define spi_txd(spi_no, bits, data) spi_transaction(spi_no, 0, 0, 0, 0, bits, (uint32) data, 0, 0) 69 | #define spi_tx8(spi_no, data) spi_transaction(spi_no, 0, 0, 0, 0, 8, (uint32) data, 0, 0) 70 | #define spi_tx16(spi_no, data) spi_transaction(spi_no, 0, 0, 0, 0, 16, (uint32) data, 0, 0) 71 | #define spi_tx32(spi_no, data) spi_transaction(spi_no, 0, 0, 0, 0, 32, (uint32) data, 0, 0) 72 | 73 | #define spi_rxd(spi_no, bits) spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, bits, 0) 74 | #define spi_rx8(spi_no) spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, 8, 0) 75 | #define spi_rx16(spi_no) spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, 16, 0) 76 | #define spi_rx32(spi_no) spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, 32, 0) 77 | 78 | #endif 79 | 80 | -------------------------------------------------------------------------------- /include/driver/spi_register.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2010 - 2011 Espressif System 3 | * Modified by David Ogilvy (MetalPhreak) 4 | * Based on original file included in SDK 1.0.0 5 | * 6 | * Missing defines from previous SDK versions have 7 | * been added and are noted with comments. The 8 | * names of these defines are likely to change. 9 | */ 10 | 11 | #ifndef SPI_REGISTER_H_INCLUDED 12 | #define SPI_REGISTER_H_INCLUDED 13 | 14 | #define REG_SPI_BASE(i) (0x60000200-i*0x100) 15 | 16 | #define SPI_CMD(i) (REG_SPI_BASE(i) + 0x0) 17 | #define SPI_FLASH_READ (BIT(31)) //From previous SDK 18 | #define SPI_FLASH_WREN (BIT(30)) //From previous SDK 19 | #define SPI_FLASH_WRDI (BIT(29)) //From previous SDK 20 | #define SPI_FLASH_RDID (BIT(28)) //From previous SDK 21 | #define SPI_FLASH_RDSR (BIT(27)) //From previous SDK 22 | #define SPI_FLASH_WRSR (BIT(26)) //From previous SDK 23 | #define SPI_FLASH_PP (BIT(25)) //From previous SDK 24 | #define SPI_FLASH_SE (BIT(24)) //From previous SDK 25 | #define SPI_FLASH_BE (BIT(23)) //From previous SDK 26 | #define SPI_FLASH_CE (BIT(22)) //From previous SDK 27 | #define SPI_FLASH_DP (BIT(21)) //From previous SDK 28 | #define SPI_FLASH_RES (BIT(20)) //From previous SDK 29 | #define SPI_FLASH_HPM (BIT(19)) //From previous SDK 30 | #define SPI_USR (BIT(18)) 31 | 32 | #define SPI_ADDR(i) (REG_SPI_BASE(i) + 0x4) 33 | 34 | #define SPI_CTRL(i) (REG_SPI_BASE(i) + 0x8) 35 | #define SPI_WR_BIT_ORDER (BIT(26)) 36 | #define SPI_RD_BIT_ORDER (BIT(25)) 37 | #define SPI_QIO_MODE (BIT(24)) 38 | #define SPI_DIO_MODE (BIT(23)) 39 | #define SPI_TWO_BYTE_STATUS_EN (BIT(22)) //From previous SDK 40 | #define SPI_WP_REG (BIT(21)) //From previous SDK 41 | #define SPI_QOUT_MODE (BIT(20)) 42 | #define SPI_SHARE_BUS (BIT(19)) //From previous SDK 43 | #define SPI_HOLD_MODE (BIT(18)) //From previous SDK 44 | #define SPI_ENABLE_AHB (BIT(17)) //From previous SDK 45 | #define SPI_SST_AAI (BIT(16)) //From previous SDK 46 | #define SPI_RESANDRES (BIT(15)) //From previous SDK 47 | #define SPI_DOUT_MODE (BIT(14)) 48 | #define SPI_FASTRD_MODE (BIT(13)) 49 | 50 | #define SPI_CTRL1(i) (REG_SPI_BASE (i) + 0xC) //From previous SDK. Removed _FLASH_ from name to match other registers. 51 | #define SPI_CS_HOLD_DELAY 0x0000000F //Espressif BBS 52 | #define SPI_CS_HOLD_DELAY_S 28 //Espressif BBS 53 | #define SPI_CS_HOLD_DELAY_RES 0x00000FFF //Espressif BBS 54 | #define SPI_CS_HOLD_DELAY_RES_S 16 //Espressif BBS 55 | #define SPI_BUS_TIMER_LIMIT 0x0000FFFF //From previous SDK 56 | #define SPI_BUS_TIMER_LIMIT_S 0 //From previous SDK 57 | 58 | 59 | #define SPI_RD_STATUS(i) (REG_SPI_BASE(i) + 0x10) 60 | #define SPI_STATUS_EXT 0x000000FF //From previous SDK 61 | #define SPI_STATUS_EXT_S 24 //From previous SDK 62 | #define SPI_WB_MODE 0x000000FF //From previous SDK 63 | #define SPI_WB_MODE_S 16 //From previous SDK 64 | #define SPI_FLASH_STATUS_PRO_FLAG (BIT(7)) //From previous SDK 65 | #define SPI_FLASH_TOP_BOT_PRO_FLAG (BIT(5)) //From previous SDK 66 | #define SPI_FLASH_BP2 (BIT(4)) //From previous SDK 67 | #define SPI_FLASH_BP1 (BIT(3)) //From previous SDK 68 | #define SPI_FLASH_BP0 (BIT(2)) //From previous SDK 69 | #define SPI_FLASH_WRENABLE_FLAG (BIT(1)) //From previous SDK 70 | #define SPI_FLASH_BUSY_FLAG (BIT(0)) //From previous SDK 71 | 72 | #define SPI_CTRL2(i) (REG_SPI_BASE(i) + 0x14) 73 | #define SPI_CS_DELAY_NUM 0x0000000F 74 | #define SPI_CS_DELAY_NUM_S 28 75 | #define SPI_CS_DELAY_MODE 0x00000003 76 | #define SPI_CS_DELAY_MODE_S 26 77 | #define SPI_MOSI_DELAY_NUM 0x00000007 78 | #define SPI_MOSI_DELAY_NUM_S 23 79 | #define SPI_MOSI_DELAY_MODE 0x00000003 //mode 0 : posedge; data set at positive edge of clk 80 | //mode 1 : negedge + 1 cycle delay, only if freq<10MHz ; data set at negitive edge of clk 81 | //mode 2 : Do not use this mode. 82 | #define SPI_MOSI_DELAY_MODE_S 21 83 | #define SPI_MISO_DELAY_NUM 0x00000007 84 | #define SPI_MISO_DELAY_NUM_S 18 85 | #define SPI_MISO_DELAY_MODE 0x00000003 86 | #define SPI_MISO_DELAY_MODE_S 16 87 | #define SPI_CK_OUT_HIGH_MODE 0x0000000F 88 | #define SPI_CK_OUT_HIGH_MODE_S 12 89 | #define SPI_CK_OUT_LOW_MODE 0x0000000F 90 | #define SPI_CK_OUT_LOW_MODE_S 8 91 | #define SPI_HOLD_TIME 0x0000000F 92 | #define SPI_HOLD_TIME_S 4 93 | #define SPI_SETUP_TIME 0x0000000F 94 | #define SPI_SETUP_TIME_S 0 95 | 96 | #define SPI_CLOCK(i) (REG_SPI_BASE(i) + 0x18) 97 | #define SPI_CLK_EQU_SYSCLK (BIT(31)) 98 | #define SPI_CLKDIV_PRE 0x00001FFF 99 | #define SPI_CLKDIV_PRE_S 18 100 | #define SPI_CLKCNT_N 0x0000003F 101 | #define SPI_CLKCNT_N_S 12 102 | #define SPI_CLKCNT_H 0x0000003F 103 | #define SPI_CLKCNT_H_S 6 104 | #define SPI_CLKCNT_L 0x0000003F 105 | #define SPI_CLKCNT_L_S 0 106 | 107 | #define SPI_USER(i) (REG_SPI_BASE(i) + 0x1C) 108 | #define SPI_USR_COMMAND (BIT(31)) 109 | #define SPI_USR_ADDR (BIT(30)) 110 | #define SPI_USR_DUMMY (BIT(29)) 111 | #define SPI_USR_MISO (BIT(28)) 112 | #define SPI_USR_MOSI (BIT(27)) 113 | #define SPI_USR_DUMMY_IDLE (BIT(26)) //From previous SDK 114 | #define SPI_USR_MOSI_HIGHPART (BIT(25)) 115 | #define SPI_USR_MISO_HIGHPART (BIT(24)) 116 | #define SPI_USR_PREP_HOLD (BIT(23)) //From previous SDK 117 | #define SPI_USR_CMD_HOLD (BIT(22)) //From previous SDK 118 | #define SPI_USR_ADDR_HOLD (BIT(21)) //From previous SDK 119 | #define SPI_USR_DUMMY_HOLD (BIT(20)) //From previous SDK 120 | #define SPI_USR_DIN_HOLD (BIT(19)) //From previous SDK 121 | #define SPI_USR_DOUT_HOLD (BIT(18)) //From previous SDK 122 | #define SPI_USR_HOLD_POL (BIT(17)) //From previous SDK 123 | #define SPI_SIO (BIT(16)) 124 | #define SPI_FWRITE_QIO (BIT(15)) 125 | #define SPI_FWRITE_DIO (BIT(14)) 126 | #define SPI_FWRITE_QUAD (BIT(13)) 127 | #define SPI_FWRITE_DUAL (BIT(12)) 128 | #define SPI_WR_BYTE_ORDER (BIT(11)) 129 | #define SPI_RD_BYTE_ORDER (BIT(10)) 130 | #define SPI_AHB_ENDIAN_MODE 0x00000003 //From previous SDK 131 | #define SPI_AHB_ENDIAN_MODE_S 8 //From previous SDK 132 | #define SPI_CK_OUT_EDGE (BIT(7)) 133 | #define SPI_CK_I_EDGE (BIT(6)) 134 | #define SPI_CS_SETUP (BIT(5)) 135 | #define SPI_CS_HOLD (BIT(4)) 136 | #define SPI_AHB_USR_COMMAND (BIT(3)) //From previous SDK 137 | #define SPI_FLASH_MODE (BIT(2)) 138 | #define SPI_AHB_USR_COMMAND_4BYTE (BIT(1)) //From previous SDK 139 | #define SPI_DOUTDIN (BIT(0)) //From previous SDK 140 | 141 | //AHB = http://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture ? 142 | 143 | 144 | #define SPI_USER1(i) (REG_SPI_BASE(i) + 0x20) 145 | #define SPI_USR_ADDR_BITLEN 0x0000003F 146 | #define SPI_USR_ADDR_BITLEN_S 26 147 | #define SPI_USR_MOSI_BITLEN 0x000001FF 148 | #define SPI_USR_MOSI_BITLEN_S 17 149 | #define SPI_USR_MISO_BITLEN 0x000001FF 150 | #define SPI_USR_MISO_BITLEN_S 8 151 | #define SPI_USR_DUMMY_CYCLELEN 0x000000FF 152 | #define SPI_USR_DUMMY_CYCLELEN_S 0 153 | 154 | #define SPI_USER2(i) (REG_SPI_BASE(i) + 0x24) 155 | #define SPI_USR_COMMAND_BITLEN 0x0000000F 156 | #define SPI_USR_COMMAND_BITLEN_S 28 157 | #define SPI_USR_COMMAND_VALUE 0x0000FFFF 158 | #define SPI_USR_COMMAND_VALUE_S 0 159 | 160 | #define SPI_WR_STATUS(i) (REG_SPI_BASE(i) + 0x28) 161 | //previously defined as SPI_FLASH_USER3. No further info available. 162 | 163 | #define SPI_PIN(i) (REG_SPI_BASE(i) + 0x2C) 164 | #define SPI_IDLE_EDGE (BIT(29)) 165 | #define SPI_CS2_DIS (BIT(2)) 166 | #define SPI_CS1_DIS (BIT(1)) 167 | #define SPI_CS0_DIS (BIT(0)) 168 | 169 | #define SPI_SLAVE(i) (REG_SPI_BASE(i) + 0x30) 170 | #define SPI_SYNC_RESET (BIT(31)) 171 | #define SPI_SLAVE_MODE (BIT(30)) 172 | #define SPI_SLV_WR_RD_BUF_EN (BIT(29)) 173 | #define SPI_SLV_WR_RD_STA_EN (BIT(28)) 174 | #define SPI_SLV_CMD_DEFINE (BIT(27)) 175 | #define SPI_TRANS_CNT 0x0000000F 176 | #define SPI_TRANS_CNT_S 23 177 | #define SPI_SLV_LAST_STATE 0x00000007 //From previous SDK 178 | #define SPI_SLV_LAST_STATE_S 20 //From previous SDK 179 | #define SPI_SLV_LAST_COMMAND 0x00000007 //From previous SDK 180 | #define SPI_SLV_LAST_COMMAND_S 17 //From previous SDK 181 | #define SPI_CS_I_MODE 0x00000003 //From previous SDK 182 | #define SPI_CS_I_MODE_S 10 //From previous SDK 183 | #define SPI_TRANS_DONE_EN (BIT(9)) 184 | #define SPI_SLV_WR_STA_DONE_EN (BIT(8)) 185 | #define SPI_SLV_RD_STA_DONE_EN (BIT(7)) 186 | #define SPI_SLV_WR_BUF_DONE_EN (BIT(6)) 187 | #define SPI_SLV_RD_BUF_DONE_EN (BIT(5)) 188 | #define SLV_SPI_INT_EN 0x0000001f 189 | #define SLV_SPI_INT_EN_S 5 190 | #define SPI_TRANS_DONE (BIT(4)) 191 | #define SPI_SLV_WR_STA_DONE (BIT(3)) 192 | #define SPI_SLV_RD_STA_DONE (BIT(2)) 193 | #define SPI_SLV_WR_BUF_DONE (BIT(1)) 194 | #define SPI_SLV_RD_BUF_DONE (BIT(0)) 195 | 196 | #define SPI_SLAVE1(i) (REG_SPI_BASE(i) + 0x34) 197 | #define SPI_SLV_STATUS_BITLEN 0x0000001F 198 | #define SPI_SLV_STATUS_BITLEN_S 27 199 | #define SPI_SLV_STATUS_FAST_EN (BIT(26)) //From previous SDK 200 | #define SPI_SLV_STATUS_READBACK (BIT(25)) //From previous SDK 201 | #define SPI_SLV_BUF_BITLEN 0x000001FF 202 | #define SPI_SLV_BUF_BITLEN_S 16 203 | #define SPI_SLV_RD_ADDR_BITLEN 0x0000003F 204 | #define SPI_SLV_RD_ADDR_BITLEN_S 10 205 | #define SPI_SLV_WR_ADDR_BITLEN 0x0000003F 206 | #define SPI_SLV_WR_ADDR_BITLEN_S 4 207 | #define SPI_SLV_WRSTA_DUMMY_EN (BIT(3)) 208 | #define SPI_SLV_RDSTA_DUMMY_EN (BIT(2)) 209 | #define SPI_SLV_WRBUF_DUMMY_EN (BIT(1)) 210 | #define SPI_SLV_RDBUF_DUMMY_EN (BIT(0)) 211 | 212 | 213 | 214 | #define SPI_SLAVE2(i) (REG_SPI_BASE(i) + 0x38) 215 | #define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0X000000FF 216 | #define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24 217 | #define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0X000000FF 218 | #define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16 219 | #define SPI_SLV_WRSTR_DUMMY_CYCLELEN 0X000000FF 220 | #define SPI_SLV_WRSTR_DUMMY_CYCLELEN_S 8 221 | #define SPI_SLV_RDSTR_DUMMY_CYCLELEN 0x000000FF 222 | #define SPI_SLV_RDSTR_DUMMY_CYCLELEN_S 0 223 | 224 | #define SPI_SLAVE3(i) (REG_SPI_BASE(i) + 0x3C) 225 | #define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF 226 | #define SPI_SLV_WRSTA_CMD_VALUE_S 24 227 | #define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF 228 | #define SPI_SLV_RDSTA_CMD_VALUE_S 16 229 | #define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF 230 | #define SPI_SLV_WRBUF_CMD_VALUE_S 8 231 | #define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF 232 | #define SPI_SLV_RDBUF_CMD_VALUE_S 0 233 | 234 | //Previous SDKs referred to these following registers as SPI_C0 etc. 235 | 236 | #define SPI_W0(i) (REG_SPI_BASE(i) +0x40) 237 | #define SPI_W1(i) (REG_SPI_BASE(i) +0x44) 238 | #define SPI_W2(i) (REG_SPI_BASE(i) +0x48) 239 | #define SPI_W3(i) (REG_SPI_BASE(i) +0x4C) 240 | #define SPI_W4(i) (REG_SPI_BASE(i) +0x50) 241 | #define SPI_W5(i) (REG_SPI_BASE(i) +0x54) 242 | #define SPI_W6(i) (REG_SPI_BASE(i) +0x58) 243 | #define SPI_W7(i) (REG_SPI_BASE(i) +0x5C) 244 | #define SPI_W8(i) (REG_SPI_BASE(i) +0x60) 245 | #define SPI_W9(i) (REG_SPI_BASE(i) +0x64) 246 | #define SPI_W10(i) (REG_SPI_BASE(i) +0x68) 247 | #define SPI_W11(i) (REG_SPI_BASE(i) +0x6C) 248 | #define SPI_W12(i) (REG_SPI_BASE(i) +0x70) 249 | #define SPI_W13(i) (REG_SPI_BASE(i) +0x74) 250 | #define SPI_W14(i) (REG_SPI_BASE(i) +0x78) 251 | #define SPI_W15(i) (REG_SPI_BASE(i) +0x7C) 252 | 253 | // +0x80 to +0xBC could be SPI_W16 through SPI_W31? 254 | 255 | // +0xC0 to +0xEC not currently defined. 256 | 257 | #define SPI_EXT0(i) (REG_SPI_BASE(i) + 0xF0) //From previous SDK. Removed _FLASH_ from name to match other registers. 258 | #define SPI_T_PP_ENA (BIT(31)) //From previous SDK 259 | #define SPI_T_PP_SHIFT 0x0000000F //From previous SDK 260 | #define SPI_T_PP_SHIFT_S 16 //From previous SDK 261 | #define SPI_T_PP_TIME 0x00000FFF //From previous SDK 262 | #define SPI_T_PP_TIME_S 0 //From previous SDK 263 | 264 | #define SPI_EXT1(i) (REG_SPI_BASE(i) + 0xF4) //From previous SDK. Removed _FLASH_ from name to match other registers. 265 | #define SPI_T_ERASE_ENA (BIT(31)) //From previous SDK 266 | #define SPI_T_ERASE_SHIFT 0x0000000F //From previous SDK 267 | #define SPI_T_ERASE_SHIFT_S 16 //From previous SDK 268 | #define SPI_T_ERASE_TIME 0x00000FFF //From previous SDK 269 | #define SPI_T_ERASE_TIME_S 0 //From previous SDK 270 | 271 | #define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8) //From previous SDK. Removed _FLASH_ from name to match other registers. 272 | #define SPI_ST 0x00000007 //From previous SDK 273 | #define SPI_ST_S 0 //From previous SDK 274 | 275 | #define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC) 276 | #define SPI_INT_HOLD_ENA 0x00000003 277 | #define SPI_INT_HOLD_ENA_S 0 278 | #endif // SPI_REGISTER_H_INCLUDED 279 | --------------------------------------------------------------------------------