├── readme.txt ├── circuit for timer examples.png ├── OverflowTimer.c └── CompareTimer.c /readme.txt: -------------------------------------------------------------------------------- 1 | The video pretty much explains it all: 2 | https://www.youtube.com/watch?v=6Te-p_aq2oU -------------------------------------------------------------------------------- /circuit for timer examples.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/MicrocontrollersAndMore/Atmel_Programming_Tutorial_6_Timers_and_Counters/HEAD/circuit for timer examples.png -------------------------------------------------------------------------------- /OverflowTimer.c: -------------------------------------------------------------------------------- 1 | // OverflowTimer.c 2 | 3 | // LED on PC4 (pin 27) 4 | // LED on PC5 (pin 28) 5 | 6 | #ifndef F_CPU // if F_CPU was not defined in Project -> Properties 7 | #define F_CPU 1000000UL // define it now as 1 MHz unsigned long 8 | #endif 9 | 10 | #include // this is always included in AVR programs 11 | #include 12 | 13 | /////////////////////////////////////////////////////////////////////////////////////////////////// 14 | int main(void) { 15 | 16 | DDRC |= (1 << PC5) | (1 << PC4); // set PC5 (pin 28) and PC4 (pin 27) for output 17 | 18 | /* 19 | TCCR0A - Timer/Counter 0 Control Register A 20 | 21 | bit 7 6 5 4 3 2 1 0 22 | name COM0A1 COM0A0 COM0B1 COM0B0 - - WGM01 WGM00 23 | set to 0 0 0 0 0 0 0 0 24 | 25 | COM0A1 = 0 normal port operation, OC0A disconnected 26 | COM0A0 = 0 27 | 28 | COM0B1 = 0 normal port operation, OC0B disconnected 29 | COM0B0 = 0 30 | 31 | bit 3 = 0 32 | bit 2 = 0 33 | 34 | WGM01 = 0 "Normal" timer/counter mode 35 | WGM00 = 0 36 | */ 37 | TCCR0A = 0b00000000; 38 | 39 | /* 40 | TCCR0B - Timer/Counter 0 Control Register B 41 | 42 | bit 7 6 5 4 3 2 1 0 43 | name FOC0A FOC0B - - WGM02 CS02 CS01 CS00 44 | set to 0 0 0 0 0 1 0 1 45 | 46 | FOC0A = 0 don't use Force Output Compare A 47 | FOC0B = 0 48 | 49 | bit 5 = 0 50 | bit 4 = 0 51 | 52 | WGM02 = 0 "Normal" timer/counter mode, see TCCR0A 53 | 54 | CS02 = 1 55 | CS01 = 0 clock / 1024 56 | CS00 = 1 57 | */ 58 | TCCR0B = 0b00000101; 59 | 60 | /* 61 | TIMSK0 - Timer/Counter 0 Interrupt Mask Register 62 | 63 | bit 7 6 5 4 3 2 1 0 64 | name - - - - - OCIE0B OCIE0A TOIE0 65 | set to 0 0 0 0 0 0 0 1 66 | 67 | bit 7 = 0 don't use Force Output Compare A 68 | bit 6 = 0 69 | bit 5 = 0 70 | bit 4 = 0 71 | bit 3 = 0 72 | OCIE0B = 0 don't enable Timer/Counter 0 Output Compare Match B Interrupt 73 | OCIE0A = 0 don't enable Timer/Counter 0 Output Compare Match A Interrupt Enable 74 | TOIE0 = 1 enable Timer/Counter 0 Overflow Interrupt 75 | */ 76 | TIMSK0 = 0b00000001; 77 | 78 | /* 79 | TCCR1A - Timer/Counter1 Control Register A 80 | 81 | bit 7 6 5 4 3 2 1 0 82 | name COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 83 | set to 0 0 0 0 0 0 0 0 84 | 85 | COM1A1 = 0 normal port operation, OC1A disconnected 86 | COM1A0 = 0 87 | 88 | COM1B1 = 0 normal port operation, OC1B disconnected 89 | COM1B0 = 0 90 | 91 | bit 3 = 0 92 | bit 2 = 0 93 | 94 | WGM11 = 0 "Normal" timer/counter mode 95 | WGM10 = 0 96 | */ 97 | TCCR1A = 0b00000000; 98 | 99 | /* 100 | TCCR1B - Timer/Counter1 Control Register B 101 | 102 | bit 7 6 5 4 3 2 1 0 103 | name ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 104 | set to 0 0 0 0 0 0 1 0 105 | 106 | ICNC1 = 0 don't use Input Capture Noise Canceler 107 | ICES1 = 0 don't use Input Capture Edge Select 108 | 109 | bit 5 = 0 110 | 111 | WGM13 = 0 112 | WGM12 = 0 "Normal" timer/counter mode, see TCCR1A 113 | 114 | CS12 = 0 115 | CS11 = 1 clock / 8 116 | CS10 = 0 117 | */ 118 | TCCR1B = 0b00000010; 119 | 120 | /* 121 | TCCR1C - Timer/Counter1 Control Register C 122 | 123 | bit 7 6 5 4 3 2 1 0 124 | name FOC1A FOC1B - - - - - - 125 | set to 0 0 0 0 0 0 0 0 126 | 127 | FOC1A = 0 don't use Force Output Compare for Channel A 128 | FOC1B = 0 don't use Force Output Compare for Channel B 129 | 130 | bit 5 = 0 131 | bit 4 = 0 132 | bit 3 = 0 133 | bit 2 = 0 134 | bit 1 = 0 135 | bit 0 = 0 136 | */ 137 | TCCR1C = 0b00000000; 138 | 139 | /* 140 | TIMSK1 - Timer/Counter 1 Interrupt Mask Register 141 | 142 | bit 7 6 5 4 3 2 1 0 143 | name - - ICIE1 - - OCIE1B OCIE1A TOIE1 144 | set to 0 0 0 0 0 0 0 1 145 | 146 | bit 7 = 0 147 | bit 6 = 0 148 | ICIE1 = 0 don't use Input Capture Interrupt Enable 149 | bit 4 = 0 150 | bit 3 = 0 151 | OCIE1B = 0 don't enable Timer/Counter 1 Output Compare Match B Interrupt 152 | OCIE1A = 0 don't enable Timer/Counter 1 Output Compare Match A Interrupt Enable 153 | TOIE1 = 1 enable Timer/Counter 1 Overflow Interrupt 154 | */ 155 | TIMSK1 = 0b00000001; 156 | 157 | sei(); // enable interrupts 158 | 159 | while (1) { } 160 | 161 | return(0); // should never get here, this is to prevent a compiler warning 162 | } 163 | 164 | /////////////////////////////////////////////////////////////////////////////////////////////////// 165 | ISR(TIMER0_OVF_vect) { 166 | PORTC ^= (1 << PC4); 167 | } 168 | 169 | /////////////////////////////////////////////////////////////////////////////////////////////////// 170 | ISR(TIMER1_OVF_vect) { 171 | PORTC ^= (1 << PC5); 172 | } 173 | 174 | 175 | 176 | -------------------------------------------------------------------------------- /CompareTimer.c: -------------------------------------------------------------------------------- 1 | // CompareTimer.c 2 | 3 | // LED on PC4 (pin 27) 4 | // LED on PC5 (pin 28) 5 | 6 | #ifndef F_CPU // if F_CPU was not defined in Project -> Properties 7 | #define F_CPU 1000000UL // define it now as 1 MHz unsigned long 8 | #endif 9 | 10 | #include // this is always included in AVR programs 11 | #include 12 | 13 | /////////////////////////////////////////////////////////////////////////////////////////////////// 14 | int main(void) { 15 | 16 | DDRC |= (1 << PC5) | (1 << PC4); // set PC5 (pin 28) and PC4 (pin 27) for output 17 | 18 | /* 19 | TCCR0A - Timer/Counter 0 Control Register A 20 | 21 | bit 7 6 5 4 3 2 1 0 22 | name COM0A1 COM0A0 COM0B1 COM0B0 - - WGM01 WGM00 23 | set to 0 0 0 0 0 0 1 0 24 | 25 | COM0A1 = 0 normal port operation, OC0A disconnected 26 | COM0A0 = 0 27 | 28 | COM0B1 = 0 normal port operation, OC0B disconnected 29 | COM0B0 = 0 30 | 31 | bit 3 = 0 32 | bit 2 = 0 33 | 34 | WGM01 = 1 CTC (Clear Timer on Compare match) mode, see TCCR0B also 35 | WGM00 = 0 TCNT0 will count up to value in OCR0A, then signal timer 0 compare interrupt 36 | */ 37 | TCCR0A = 0b00000010; 38 | 39 | /* 40 | TCCR0B - Timer/Counter 0 Control Register B 41 | 42 | bit 7 6 5 4 3 2 1 0 43 | name FOC0A FOC0B - - WGM02 CS02 CS01 CS00 44 | set to 0 0 0 0 0 1 0 1 45 | 46 | FOC0A = 0 don't use Force Output Compare A 47 | FOC0B = 0 48 | 49 | bit 5 = 0 50 | bit 4 = 0 51 | 52 | WGM02 = 0 CTC (Clear Timer on Compare match) mode, see TCCR0A also 53 | 54 | CS02 = 1 55 | CS01 = 0 clock / 1024 56 | CS00 = 1 57 | */ 58 | TCCR0B = 0b00000101; 59 | 60 | /* 61 | TIMSK0 - Timer/Counter 0 Interrupt Mask Register 62 | 63 | bit 7 6 5 4 3 2 1 0 64 | name - - - - - OCIE0B OCIE0A TOIE0 65 | set to 0 0 0 0 0 0 1 0 66 | 67 | bit 7 = 0 don't use Force Output Compare A 68 | bit 6 = 0 69 | bit 5 = 0 70 | bit 4 = 0 71 | bit 3 = 0 72 | OCIE0B = 0 don't enable Timer/Counter 0 Output Compare Match B Interrupt 73 | OCIE0A = 1 enable Timer/Counter 0 Output Compare Match A Interrupt Enable 74 | TOIE0 = 0 don't enable Timer/Counter 0 Overflow Interrupt 75 | */ 76 | TIMSK0 = 0b00000010; 77 | 78 | /* 79 | TCCR1A - Timer/Counter1 Control Register A 80 | 81 | bit 7 6 5 4 3 2 1 0 82 | name COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 83 | set to 0 0 0 0 0 0 0 0 84 | 85 | COM1A1 = 0 normal port operation, OC1A disconnected 86 | COM1A0 = 0 87 | 88 | COM1B1 = 0 normal port operation, OC1B disconnected 89 | COM1B0 = 0 90 | 91 | bit 3 = 0 92 | bit 2 = 0 93 | 94 | WGM11 = 0 CTC (Clear Timer on Compare match) mode, see TCCR1B also 95 | WGM10 = 0 TCNT1H/TCNT1L will count up to value in OCR1AH/OCR1AL, then signal timer 1 compare interrupt 96 | */ 97 | TCCR1A = 0b00000000; 98 | 99 | /* 100 | TCCR1B - Timer/Counter1 Control Register B 101 | 102 | bit 7 6 5 4 3 2 1 0 103 | name ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 104 | set to 0 0 0 0 1 0 1 0 105 | 106 | ICNC1 = 0 don't use Input Capture Noise Canceler 107 | ICES1 = 0 don't use Input Capture Edge Select 108 | 109 | bit 5 = 0 110 | 111 | WGM13 = 0 CTC (Clear Timer on Compare match) mode, see TCCR1A also 112 | WGM12 = 1 113 | 114 | CS12 = 0 115 | CS11 = 1 clock / 8 116 | CS10 = 0 117 | */ 118 | TCCR1B = 0b00001010; 119 | 120 | /* 121 | TCCR1C - Timer/Counter1 Control Register C 122 | 123 | bit 7 6 5 4 3 2 1 0 124 | name FOC1A FOC1B - - - - - - 125 | set to 0 0 0 0 0 0 0 0 126 | 127 | FOC1A = 0 don't use Force Output Compare for Channel A 128 | FOC1B = 0 don't use Force Output Compare for Channel B 129 | 130 | bit 5 = 0 131 | bit 4 = 0 132 | bit 3 = 0 133 | bit 2 = 0 134 | bit 1 = 0 135 | bit 0 = 0 136 | */ 137 | TCCR1C = 0b00000000; 138 | 139 | /* 140 | TIMSK1 - Timer/Counter 1 Interrupt Mask Register 141 | 142 | bit 7 6 5 4 3 2 1 0 143 | name - - ICIE1 - - OCIE1B OCIE1A TOIE1 144 | set to 0 0 0 0 0 0 1 0 145 | 146 | bit 7 = 0 147 | bit 6 = 0 148 | ICIE1 = 0 don't use Input Capture Interrupt Enable 149 | bit 4 = 0 150 | bit 3 = 0 151 | OCIE1B = 0 don't enable Timer/Counter 1 Output Compare Match B Interrupt 152 | OCIE1A = 1 enable Timer/Counter 1 Output Compare Match A Interrupt Enable 153 | TOIE1 = 0 don't enable Timer/Counter 1 Overflow Interrupt 154 | */ 155 | TIMSK1 = 0b00000010; 156 | 157 | // these values will make the timers run for 1/2 as long per cycle as the previous program where the timers were set to interrupt on overflow, 158 | // but you could set these values more or less as needed for any purpose 159 | OCR0A = 0b10000000; 160 | 161 | OCR1AH = 0b10000000; 162 | OCR1AL = 0b00000000; 163 | 164 | sei(); // enable interrupts 165 | 166 | while (1) { } 167 | 168 | return(0); // should never get here, this is to prevent a compiler warning 169 | } 170 | 171 | /////////////////////////////////////////////////////////////////////////////////////////////////// 172 | ISR(TIMER0_COMPA_vect) { 173 | PORTC ^= (1 << PC4); 174 | } 175 | 176 | /////////////////////////////////////////////////////////////////////////////////////////////////// 177 | ISR(TIMER1_COMPA_vect) { 178 | PORTC ^= (1 << PC5); 179 | } 180 | 181 | 182 | 183 | 184 | --------------------------------------------------------------------------------