├── Separate.jpg ├── OpenExcel.jpg ├── Separate-1.jpg ├── Separate-2.jpg ├── TakePlace.jpg ├── music ├── 001.MID ├── 002.MID ├── 003.MID ├── 004.MID ├── 005.MID ├── 006.MID ├── 007.MID ├── 008.MID └── README.md ├── ConfigMidFile.jpg ├── SelectColumnB.jpg ├── sources ├── MP3.bit └── new │ ├── TimeBCD.v │ ├── Divider.v │ ├── TimeCnt.v │ ├── SWSet.v │ ├── VolSet.v │ ├── ClkGenerator.v │ ├── SegDisplay.v │ ├── VolDecoder.v │ ├── UartReceiver.v │ ├── Bluetooth.v │ ├── Rotation.v │ └── MP3.v ├── ConfigMidFileSucceed.jpg ├── README.md └── constrs └── mp3.xdc /Separate.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Mionger/mp3-player/HEAD/Separate.jpg -------------------------------------------------------------------------------- /OpenExcel.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Mionger/mp3-player/HEAD/OpenExcel.jpg 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-------------------------------------------------------------------------------- /music/README.md: -------------------------------------------------------------------------------- 1 | Refere the [README](https://github.com/Mionger/mp3-player/edit/master/README.md "README") for config of the midi files 2 | -------------------------------------------------------------------------------- /sources/new/TimeBCD.v: -------------------------------------------------------------------------------- 1 | module Time_BCD 2 | ( 3 | DI, 4 | DO 5 | ); 6 | input [15:0] DI; 7 | output [15:0] DO; 8 | 9 | assign DO[3:0]=DI % 10; 10 | assign DO[7:4]=(DI/10)%6; 11 | assign DO[11:8]=(DI/60)%10; 12 | assign DO[15:12]=DI/600; 13 | endmodule -------------------------------------------------------------------------------- /sources/new/Divider.v: -------------------------------------------------------------------------------- 1 | module Divider #(parameter N=100000) 2 | ( 3 | DI, 4 | DO 5 | ); 6 | input DI; 7 | output reg DO=0; 8 | 9 | integer t_cnt=0; 10 | always @(posedge DI)begin 11 | if(t_cnt 4 | develop information: 5 | OS : Win10 6 | language : Verilog HDL 7 | software : Vivado 2016 8 | developer : Mion-ger Park 9 | update time : 2019-2-10 10 | version : v 0.1.2 11 | 12 | 13 | 
  
14 | UPDATE 2019-2-10 v 0.1.2
15 |   Add User Manual Part II
16 |
17 | 18 | 
  
19 | UPDATE 2019-2-3 v 0.1.1
20 |   Add User Manual Part I
21 |
22 | 23 | 
  
24 | UPDATE 2019-1-23 v 0.1.0
25 |   1.Finish the implement of MP3 Player
26 |   2.Add README.md
27 |
28 | 29 | ## User Manual 30 | ### I.Config the midi file 31 | 1.Tool Software : BmpToMif.exe 32 | [BmpToMif.exe Download URL](http://www.xdowns.com/soft/4/25/2013/Soft_113895.html "Download") 33 | 2.Generate the Mif file 34 | ![](https://github.com/Mionger/mp3-player/blob/master/ConfigMidFile.jpg) 35 | 3.Click the "生成Mif文件" 36 | 4.Generate the Mif file successfully 37 | ![](https://github.com/Mionger/mp3-player/blob/master/ConfigMidFileSucceed.jpg) 38 | 39 | ### II.Config the binary file 40 | 1.Tool Software : Microsoft Excel 41 | 2.Open the Mif file by Excel 42 | ![](https://github.com/Mionger/mp3-player/blob/master/OpenExcel.jpg) 43 | 3.Select the Column B 44 | ![](https://github.com/Mionger/mp3-player/blob/master/SelectColumnB.jpg) 45 | 4.Separate the Column by ':' 46 | ![](https://github.com/Mionger/mp3-player/blob/master/Separate.jpg) 47 | ![](https://github.com/Mionger/mp3-player/blob/master/Separate-1.jpg) 48 | ![](https://github.com/Mionger/mp3-player/blob/master/Separate-2.jpg) 49 | 5.Take place all the ';' with ',' 50 | ![](https://github.com/Mionger/mp3-player/blob/master/TakePlace.jpg) 51 | 6.Save the file 52 | -------------------------------------------------------------------------------- /sources/new/SegDisplay.v: -------------------------------------------------------------------------------- 1 | module Seg_Display 2 | ( 3 | CLK, 4 | DI, 5 | DO, 6 | SHF, 7 | DOT 8 | ); 9 | input CLK; 10 | input [31:0] DI; 11 | output reg [6:0] DO; 12 | output reg [7:0] SHF=8'b01111111; 13 | output reg DOT; 14 | 15 | reg [5:0] shr=0; 16 | 17 | wire [31:0] show_data; 18 | assign show_data[31:16]=DI[31:16]; 19 | Time_BCD time_bcd(DI[15:0],show_data[15:0]); 20 | 21 | wire clk_t; 22 | Divider #(200000)divider(CLK,clk_t); 23 | always @(posedge clk_t) begin 24 | SHF<={SHF[6:0],SHF[7]}; 25 | shr<=shr+4; 26 | if(SHF[1]==0) begin 27 | DOT<=0; 28 | end 29 | else begin 30 | DOT<=1; 31 | end 32 | case({show_data[shr+3],show_data[shr+2],show_data[shr+1],show_data[shr]}) 33 | 4'b0000: begin 34 | DO<=7'b1000000; 35 | end 36 | 4'b0001: begin 37 | DO<=7'b1111001; 38 | end 39 | 4'b0010: begin 40 | DO<=7'b0100100; 41 | end 42 | 4'b0011: begin 43 | DO<=7'b0110000; 44 | end 45 | 4'b0100: begin 46 | DO<=7'b0011001; 47 | end 48 | 4'b0101: begin 49 | DO<=7'b0010010; 50 | end 51 | 4'b0110: begin 52 | DO<=7'b0000010; 53 | end 54 | 4'b0111: begin 55 | DO<=7'b1111000; 56 | end 57 | 4'b1000: begin 58 | DO<=7'b0000000; 59 | end 60 | 4'b1001: begin 61 | DO<=7'b0010000; 62 | end 63 | default: begin 64 | DO<=7'b1111111; 65 | end 66 | endcase 67 | end 68 | 69 | endmodule -------------------------------------------------------------------------------- /sources/new/VolDecoder.v: -------------------------------------------------------------------------------- 1 | module Vol_Decoder 2 | ( 3 | DI, 4 | DO 5 | ); 6 | 7 | input [15:0]DI; 8 | output reg [15:0]DO; 9 | 10 | always@(*)begin 11 | case (DI) 12 | 16'h0000:begin 13 | DO=16'b1111111111111111; 14 | end 15 | 16'h1010:begin 16 | DO=16'b0111111111111111; 17 | end 18 | 16'h2020:begin 19 | DO=16'b0011111111111111; 20 | end 21 | 16'h3030:begin 22 | DO=16'b0001111111111111; 23 | end 24 | 16'h4040:begin 25 | DO=16'b0000111111111111; 26 | end 27 | 16'h5050:begin 28 | DO=16'b0000011111111111; 29 | end 30 | 16'h6060:begin 31 | DO=16'b0000001111111111; 32 | end 33 | 16'h7070:begin 34 | DO=16'b0000000111111111; 35 | end 36 | 16'h8080:begin 37 | DO=16'b0000000011111111; 38 | end 39 | 16'h9090:begin 40 | DO=16'b0000000001111111; 41 | end 42 | 16'hA0A0:begin 43 | DO=16'b0000000000111111; 44 | end 45 | 16'hB0B0:begin 46 | DO=16'b0000000000011111; 47 | end 48 | 16'hC0C0:begin 49 | DO=16'b0000000000001111; 50 | end 51 | 16'hD0D0:begin 52 | DO=16'b0000000000000111; 53 | end 54 | 16'hE0E0:begin 55 | DO=16'b0000000000000011; 56 | end 57 | 16'hF0F0:begin 58 | DO=16'b0000000000000001; 59 | end 60 | default: begin 61 | ; 62 | end 63 | endcase 64 | end 65 | endmodule -------------------------------------------------------------------------------- /sources/new/UartReceiver.v: -------------------------------------------------------------------------------- 1 | module Uart_Receiver 2 | ( 3 | CLK, 4 | CLK_SMP, 5 | RST_N, 6 | 7 | RXD, 8 | RXD_OVER, 9 | RXD_DATA 10 | ); 11 | 12 | input CLK; 13 | input CLK_SMP; 14 | input RST_N; 15 | 16 | input RXD; 17 | output RXD_OVER; 18 | output reg [7:0]RXD_DATA; 19 | 20 | reg rxd_sync_r0; 21 | reg rxd_sync_r1; 22 | always@(posedge CLK or negedge RST_N) begin 23 | if(!RST_N) begin 24 | rxd_sync_r0 <= 1; 25 | rxd_sync_r1 <= 1; 26 | end 27 | else if(CLK_SMP == 1) begin 28 | rxd_sync_r0 <= RXD; 29 | rxd_sync_r1 <= rxd_sync_r0; 30 | end 31 | end 32 | wire rxd_sync = rxd_sync_r1; 33 | 34 | parameter R_IDLE = 1'b0; 35 | parameter R_SAMPLE = 1'b1; 36 | reg rxd_state; 37 | reg [3:0] smp_cnt; 38 | reg [2:0] rxd_cnt; 39 | always@(posedge CLK or negedge RST_N) begin 40 | if(!RST_N) begin 41 | smp_cnt <= 0; 42 | rxd_cnt <= 0; 43 | RXD_DATA <= 0; 44 | rxd_state <= R_IDLE; 45 | end 46 | else if(CLK_SMP == 1) begin 47 | case(rxd_state) 48 | R_IDLE:begin 49 | rxd_cnt <= 0; 50 | if(rxd_sync == 1'b0)begin 51 | smp_cnt <= smp_cnt + 1'b1; 52 | if(smp_cnt == 4'd7) 53 | rxd_state <= R_SAMPLE; 54 | end 55 | else 56 | smp_cnt <= 0; 57 | end 58 | 59 | R_SAMPLE:begin 60 | smp_cnt <= smp_cnt +1'b1; 61 | if(smp_cnt == 4'd7) begin 62 | rxd_cnt <= rxd_cnt +1'b1; 63 | if(rxd_cnt == 4'd7) 64 | rxd_state <= R_IDLE; 65 | case(rxd_cnt) 66 | 3'd0: RXD_DATA[0] <= rxd_sync; 67 | 3'd1: RXD_DATA[1] <= rxd_sync; 68 | 3'd2: RXD_DATA[2] <= rxd_sync; 69 | 3'd3: RXD_DATA[3] <= rxd_sync; 70 | 3'd4: RXD_DATA[4] <= rxd_sync; 71 | 3'd5: RXD_DATA[5] <= rxd_sync; 72 | 3'd6: RXD_DATA[6] <= rxd_sync; 73 | 3'd7: RXD_DATA[7] <= rxd_sync; 74 | endcase 75 | end 76 | end 77 | endcase 78 | end 79 | end 80 | wire rxd_flag_r = (rxd_cnt == 4'd7) ? 1'b1 : 1'b0; 81 | 82 | 83 | reg rxd_flag_r0; 84 | reg rxd_flag_r1; 85 | always@(posedge CLK or negedge RST_N) begin 86 | if(!RST_N) begin 87 | rxd_flag_r0 <= 0; 88 | rxd_flag_r1 <= 0; 89 | end 90 | else begin 91 | rxd_flag_r0 <= rxd_flag_r; 92 | rxd_flag_r1 <= rxd_flag_r0; 93 | end 94 | end 95 | assign RXD_OVER = ~rxd_flag_r1 & rxd_flag_r0; 96 | 97 | endmodule -------------------------------------------------------------------------------- /sources/new/Bluetooth.v: -------------------------------------------------------------------------------- 1 | module Bluetooth 2 | ( 3 | CLK, 4 | RST, 5 | 6 | UART_RXD, 7 | 8 | PREV, 9 | NEXT, 10 | UP, 11 | DOWN, 12 | 13 | RXD_DATA, 14 | SW 15 | ); 16 | 17 | input CLK; 18 | input RST; 19 | input UART_RXD; 20 | 21 | output reg[2:0] PREV; 22 | output reg[2:0] NEXT; 23 | output reg UP; 24 | output reg DOWN; 25 | 26 | output [7:0]RXD_DATA; 27 | input [2:0]SW; 28 | 29 | wire clk_smp; 30 | Clk_Generator clk_generator(CLK,RST,clk_smp); 31 | 32 | wire[7:0]rxd_data; 33 | wire rxd_over; 34 | assign RXD_DATA=rxd_data; 35 | Uart_Receiver uart_receiver(CLK,clk_smp,RST,UART_RXD,rxd_over,rxd_data); 36 | 37 | always@(posedge CLK)begin 38 | case (rxd_data) 39 | 8'h55:begin 40 | PREV <= 1; 41 | end 42 | 8'h5A:begin 43 | NEXT <= 1; 44 | end 45 | 8'hA5:begin 46 | UP <= 1; 47 | end 48 | 8'hAA:begin 49 | DOWN <= 1; 50 | end 51 | 8'h91:begin 52 | PREV<=SW; 53 | NEXT<=0; 54 | end 55 | 8'h92:begin 56 | if(SW>=1)begin 57 | PREV=SW-1; 58 | NEXT<=0; 59 | end 60 | else begin 61 | PREV<=0; 62 | NEXT<=1-SW; 63 | end 64 | end 65 | 8'h93:begin 66 | if(SW>=2)begin 67 | PREV=SW-2; 68 | NEXT<=0; 69 | end 70 | else begin 71 | PREV<=0; 72 | NEXT<=2-SW; 73 | end 74 | end 75 | 8'h94:begin 76 | if(SW>=3)begin 77 | PREV=SW-3; 78 | NEXT<=0; 79 | end 80 | else begin 81 | PREV<=0; 82 | NEXT<=3-SW; 83 | end 84 | end 85 | 8'h95:begin 86 | if(SW>=4)begin 87 | PREV=SW-4; 88 | NEXT<=0; 89 | end 90 | else begin 91 | PREV<=0; 92 | NEXT<=4-SW; 93 | end 94 | end 95 | 8'h96:begin 96 | if(SW>=5)begin 97 | PREV=SW-5; 98 | NEXT<=0; 99 | end 100 | else begin 101 | PREV<=0; 102 | NEXT<=5-SW; 103 | end 104 | end 105 | 8'h97:begin 106 | if(SW>=6)begin 107 | PREV=SW-6; 108 | NEXT<=0; 109 | end 110 | else begin 111 | PREV<=0; 112 | NEXT<=6-SW; 113 | end 114 | end 115 | default:begin 116 | PREV <= 0; 117 | NEXT <= 0; 118 | UP <= 0; 119 | DOWN <= 0; 120 | end 121 | endcase 122 | end 123 | 124 | endmodule -------------------------------------------------------------------------------- /sources/new/Rotation.v: -------------------------------------------------------------------------------- 1 | module Rotation 2 | ( 3 | CLK, 4 | SIA, 5 | SIB, 6 | SW, 7 | Dir_O 8 | ); 9 | 10 | input CLK; 11 | input SIA; 12 | input SIB; 13 | input SW; 14 | output [1:0]Dir_O; 15 | 16 | reg [1:0]dir=0; 17 | 18 | reg sia1=1; 19 | reg sia2=1; 20 | wire sia_debounce=sia1 && sia2 && SIA; 21 | always@(posedge CLK or negedge SW) begin 22 | if(SW==0) begin 23 | sia1<=1; 24 | sia2<=1; 25 | end 26 | else begin 27 | sia1<=SIA; 28 | sia2<=sia1; 29 | end 30 | end 31 | 32 | reg sib1=1; 33 | reg sib2=1; 34 | wire sib_debounce=sib1 && sib2 && SIB; 35 | always@(posedge CLK or negedge SW) begin 36 | if(SW==0) begin 37 | sib1<=1; 38 | sib2<=1; 39 | end 40 | else begin 41 | sib1<=SIB; 42 | sib2<=sib1; 43 | end 44 | end 45 | 46 | reg sia3=1; 47 | reg sia4=1; 48 | wire sia_raise=sia3 && ~sia4; 49 | wire sia_fall=~sia3 && sia4; 50 | always@(posedge CLK or negedge SW) begin 51 | if(SW==0) begin 52 | sia3<=1; 53 | sia3<=1; 54 | end 55 | else begin 56 | sia3<=sia_debounce; 57 | sia4<=sia3; 58 | end 59 | end 60 | 61 | 62 | parameter IDLE = 3'd0; 63 | parameter LEFT_START = 3'd1; 64 | parameter LEFT = 3'd2; 65 | parameter LEFT_OVER = 3'd3; 66 | parameter RIGHT_START = 3'd4; 67 | parameter RIGHT = 3'd5; 68 | parameter RIGHT_OVER = 3'd6; 69 | reg [2:0]current_state=IDLE; 70 | reg [2:0]next_state; 71 | 72 | always@(posedge CLK) begin 73 | if(SW==0)begin 74 | current_state<=IDLE; 75 | end 76 | else begin 77 | current_state<=next_state; 78 | end 79 | end 80 | 81 | always@(*)begin 82 | case (current_state) 83 | IDLE:begin 84 | if(sia_raise)begin 85 | if(sib_debounce==1'b1)begin 86 | next_state<=RIGHT_START; 87 | end 88 | else begin 89 | next_state<=LEFT_START; 90 | end 91 | end 92 | else begin 93 | next_state=IDLE; 94 | end 95 | end 96 | LEFT_START:begin 97 | next_state<=LEFT; 98 | end 99 | LEFT:begin 100 | if(sia_fall && sib_debounce==1'b0)begin 101 | next_state=LEFT_OVER; 102 | end 103 | else begin 104 | next_state=LEFT; 105 | end 106 | end 107 | LEFT_OVER:begin 108 | next_state=IDLE; 109 | end 110 | RIGHT_START:begin 111 | next_state<=RIGHT; 112 | end 113 | RIGHT:begin 114 | if(sia_fall && sib_debounce==1'b1)begin 115 | next_state=RIGHT_OVER; 116 | end 117 | else begin 118 | next_state=RIGHT; 119 | end 120 | end 121 | RIGHT_OVER:begin 122 | next_state=IDLE; 123 | end 124 | default:begin 125 | next_state=IDLE; 126 | end 127 | endcase 128 | end 129 | 130 | always@(*)begin 131 | case (current_state) 132 | IDLE:begin 133 | dir<=2'b00; 134 | end 135 | LEFT_START:begin 136 | dir<=2'b00; 137 | end 138 | LEFT:begin 139 | dir<=2'b10; 140 | end 141 | LEFT_OVER:begin 142 | dir<=2'b00; 143 | end 144 | RIGHT_START:begin 145 | dir<=2'b00; 146 | end 147 | RIGHT:begin 148 | dir<=2'b01; 149 | end 150 | RIGHT_OVER:begin 151 | dir<=2'b00; 152 | end 153 | default:begin 154 | dir<=2'b00; 155 | end 156 | endcase 157 | end 158 | 159 | assign Dir_O = dir; 160 | 161 | endmodule -------------------------------------------------------------------------------- /constrs/mp3.xdc: -------------------------------------------------------------------------------- 1 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[15]}] 2 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[14]}] 3 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[13]}] 4 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[12]}] 5 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[11]}] 6 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[10]}] 7 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[9]}] 8 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[8]}] 9 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}] 10 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}] 11 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}] 12 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}] 13 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}] 14 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}] 15 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}] 16 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}] 17 | set_property IOSTANDARD LVCMOS33 [get_ports CLK] 18 | set_property PACKAGE_PIN E3 [get_ports CLK] 19 | set_property PACKAGE_PIN H17 [get_ports {LED[0]}] 20 | set_property PACKAGE_PIN K15 [get_ports {LED[1]}] 21 | set_property PACKAGE_PIN J13 [get_ports {LED[2]}] 22 | set_property PACKAGE_PIN N14 [get_ports {LED[3]}] 23 | set_property PACKAGE_PIN R18 [get_ports {LED[4]}] 24 | set_property PACKAGE_PIN V17 [get_ports {LED[5]}] 25 | set_property PACKAGE_PIN U17 [get_ports {LED[6]}] 26 | set_property PACKAGE_PIN U16 [get_ports {LED[7]}] 27 | set_property PACKAGE_PIN V16 [get_ports {LED[8]}] 28 | set_property PACKAGE_PIN T15 [get_ports {LED[9]}] 29 | set_property PACKAGE_PIN U14 [get_ports {LED[10]}] 30 | set_property PACKAGE_PIN T16 [get_ports {LED[11]}] 31 | set_property PACKAGE_PIN V15 [get_ports {LED[12]}] 32 | set_property PACKAGE_PIN V14 [get_ports {LED[13]}] 33 | set_property PACKAGE_PIN V12 [get_ports {LED[14]}] 34 | set_property PACKAGE_PIN V11 [get_ports {LED[15]}] 35 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_DO[6]}] 36 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_DO[5]}] 37 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_DO[4]}] 38 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_DO[3]}] 39 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_DO[2]}] 40 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_DO[1]}] 41 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_DO[0]}] 42 | set_property PACKAGE_PIN T10 [get_ports {SEG_DISPLAY_DO[0]}] 43 | set_property PACKAGE_PIN R10 [get_ports {SEG_DISPLAY_DO[1]}] 44 | set_property PACKAGE_PIN K16 [get_ports {SEG_DISPLAY_DO[2]}] 45 | set_property PACKAGE_PIN K13 [get_ports {SEG_DISPLAY_DO[3]}] 46 | set_property PACKAGE_PIN P15 [get_ports {SEG_DISPLAY_DO[4]}] 47 | set_property PACKAGE_PIN T11 [get_ports {SEG_DISPLAY_DO[5]}] 48 | set_property PACKAGE_PIN L18 [get_ports {SEG_DISPLAY_DO[6]}] 49 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_SHF[7]}] 50 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_SHF[6]}] 51 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_SHF[5]}] 52 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_SHF[4]}] 53 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_SHF[3]}] 54 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_SHF[2]}] 55 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_SHF[1]}] 56 | set_property IOSTANDARD LVCMOS33 [get_ports {SEG_DISPLAY_SHF[0]}] 57 | set_property PACKAGE_PIN J17 [get_ports {SEG_DISPLAY_SHF[0]}] 58 | set_property PACKAGE_PIN J18 [get_ports {SEG_DISPLAY_SHF[1]}] 59 | set_property PACKAGE_PIN T9 [get_ports {SEG_DISPLAY_SHF[2]}] 60 | set_property PACKAGE_PIN J14 [get_ports {SEG_DISPLAY_SHF[3]}] 61 | set_property PACKAGE_PIN P14 [get_ports {SEG_DISPLAY_SHF[4]}] 62 | set_property PACKAGE_PIN T14 [get_ports {SEG_DISPLAY_SHF[5]}] 63 | set_property PACKAGE_PIN K2 [get_ports {SEG_DISPLAY_SHF[6]}] 64 | set_property PACKAGE_PIN U13 [get_ports {SEG_DISPLAY_SHF[7]}] 65 | set_property IOSTANDARD LVCMOS33 [get_ports SEG_DISPLAY_DOT] 66 | set_property PACKAGE_PIN H15 [get_ports SEG_DISPLAY_DOT] 67 | set_property IOSTANDARD LVCMOS33 [get_ports RST] 68 | set_property PACKAGE_PIN V10 [get_ports RST] 69 | set_property IOSTANDARD LVCMOS33 [get_ports ROTATION_SIA] 70 | set_property IOSTANDARD LVCMOS33 [get_ports ROTATION_SIB] 71 | set_property IOSTANDARD LVCMOS33 [get_ports ROTATION_SW] 72 | set_property PACKAGE_PIN F16 [get_ports ROTATION_SIA] 73 | set_property PACKAGE_PIN G16 [get_ports ROTATION_SIB] 74 | set_property PACKAGE_PIN H14 [get_ports ROTATION_SW] 75 | set_property IOSTANDARD LVCMOS33 [get_ports MP3_CS] 76 | set_property IOSTANDARD LVCMOS33 [get_ports MP3_DCS] 77 | set_property IOSTANDARD LVCMOS33 [get_ports MP3_DREQ] 78 | set_property IOSTANDARD LVCMOS33 [get_ports MP3_MISO] 79 | set_property IOSTANDARD LVCMOS33 [get_ports MP3_MOSI] 80 | set_property IOSTANDARD LVCMOS33 [get_ports MP3_RSET] 81 | set_property IOSTANDARD LVCMOS33 [get_ports MP3_SCLK] 82 | set_property PACKAGE_PIN K1 [get_ports MP3_DCS] 83 | set_property PACKAGE_PIN F6 [get_ports MP3_RSET] 84 | set_property PACKAGE_PIN J2 [get_ports MP3_DREQ] 85 | set_property PACKAGE_PIN E7 [get_ports MP3_CS] 86 | set_property PACKAGE_PIN J3 [get_ports MP3_SCLK] 87 | set_property PACKAGE_PIN J4 [get_ports MP3_MOSI] 88 | set_property PACKAGE_PIN E6 [get_ports MP3_MISO] 89 | 90 | set_property IOSTANDARD LVCMOS33 [get_ports UART_RXD] 91 | set_property PACKAGE_PIN G17 [get_ports UART_RXD] 92 | 93 | -------------------------------------------------------------------------------- /sources/new/MP3.v: -------------------------------------------------------------------------------- 1 | module MP3 2 | ( 3 | CLK, 4 | 5 | RST, 6 | 7 | MP3_RSET, 8 | MP3_CS, 9 | MP3_DCS, 10 | 11 | MP3_MOSI, 12 | MP3_MISO, 13 | MP3_SCLK, 14 | MP3_DREQ, 15 | 16 | ROTATION_SW, 17 | ROTATION_SIA, 18 | ROTATION_SIB, 19 | 20 | UART_RXD, 21 | 22 | SEG_DISPLAY_DOT, 23 | SEG_DISPLAY_SHF, 24 | SEG_DISPLAY_DO, 25 | 26 | LED 27 | ); 28 | input CLK; 29 | 30 | input RST; 31 | 32 | output reg MP3_RSET=1; 33 | output reg MP3_CS=1; 34 | output reg MP3_DCS=1; 35 | output reg MP3_MOSI=0; 36 | input MP3_MISO; 37 | output reg MP3_SCLK=0; 38 | input MP3_DREQ; 39 | 40 | input ROTATION_SW; 41 | input ROTATION_SIA; 42 | input ROTATION_SIB; 43 | 44 | input UART_RXD; 45 | 46 | output SEG_DISPLAY_DOT; 47 | output [7:0] SEG_DISPLAY_SHF; 48 | output [6:0] SEG_DISPLAY_DO; 49 | 50 | output [15:0] LED; 51 | 52 | 53 | 54 | //分频 55 | wire clk; 56 | Divider #(100) divider(CLK,clk); 57 | 58 | //命令 59 | integer cnt=0; 60 | integer cmd_cnt=0; 61 | parameter cmd_cnt_max=4; 62 | reg [31:0] next_cmd; 63 | reg [127:0] cmd_init={32'h02000804,32'h02000804,32'h020B0000,32'h020000800}; 64 | reg [127:0] cmd={32'h02000804,32'h02000804,32'h020B0000,32'h020000800}; 65 | 66 | //时间显示 67 | wire [2:0] sw; 68 | wire [15:0] time_sec; 69 | Time_Cnt time_cnt(clk,pos[14:0]==0,time_sec); 70 | Seg_Display seg_display(CLK,{13'b0,sw[2:0],time_sec[15:0]},SEG_DISPLAY_DO,SEG_DISPLAY_SHF,SEG_DISPLAY_DOT); 71 | 72 | //蓝牙 73 | wire [2:0]bluetooth_prev; 74 | wire [2:0]bluetooth_next; 75 | wire bluetooth_up; 76 | wire bluetooth_down; 77 | wire [7:0]rxd_data; 78 | wire uart_rxd; 79 | Bluetooth bluetooth(CLK,RST,UART_RXD,bluetooth_prev,bluetooth_next,bluetooth_up,bluetooth_down,rxd_data,sw);// 80 | 81 | //音量 82 | wire [15:0] vol; 83 | wire [1:0]dir; 84 | wire [15:0]vol_de; 85 | Rotation rotation(clk,ROTATION_SIA,ROTATION_SIB,ROTATION_SW,dir); 86 | 87 | wire up; 88 | wire down; 89 | assign up = bluetooth_up | dir[1]; 90 | assign down= bluetooth_down | dir[0]; 91 | Vol_Set vol_set(clk,up,down,vol); 92 | Vol_Decoder vol_decoder(vol,vol_de); 93 | assign LED=vol_de; 94 | 95 | //切换 96 | reg [2:0] pre_sw=0; 97 | wire [2:0]prev; 98 | wire [2:0]next; 99 | assign prev=bluetooth_prev; 100 | assign next=bluetooth_next; 101 | SW_Set sw_set(clk,prev,next,sw); 102 | 103 | //读取数据 104 | wire [15:0] data0; 105 | wire [15:0] data1; 106 | wire [15:0] data2; 107 | wire [15:0] data3; 108 | wire [15:0] data4; 109 | wire [15:0] data5; 110 | wire [15:0] data6; 111 | reg [15:0] data; 112 | reg [20:0] pos=0; 113 | blk_mem_gen_0 music_0(.clka(CLK),.wea(0),.addra(pos[12:0]),.dina(0),.douta(data0)); 114 | blk_mem_gen_1 music_1(.clka(CLK),.wea(0),.addra(pos[12:0]),.dina(0),.douta(data1)); 115 | blk_mem_gen_2 music_2(.clka(CLK),.wea(0),.addra(pos[12:0]),.dina(0),.douta(data2)); 116 | blk_mem_gen_3 music_3(.clka(CLK),.wea(0),.addra(pos[12:0]),.dina(0),.douta(data3)); 117 | blk_mem_gen_4 music_4(.clka(CLK),.wea(0),.addra(pos[12:0]),.dina(0),.douta(data4)); 118 | blk_mem_gen_5 music_5(.clka(CLK),.wea(0),.addra(pos[12:0]),.dina(0),.douta(data5)); 119 | blk_mem_gen_6 music_6(.clka(CLK),.wea(0),.addra(pos[12:0]),.dina(0),.douta(data6)); 120 | 121 | parameter INITIALIZE = 3'd0; 122 | parameter SEND_CMD = 3'd1; 123 | parameter CHECK = 3'd2; 124 | parameter DATA_SEND = 3'd3; 125 | parameter RSET_OVER = 3'd4; 126 | parameter VOL_SET_PRE = 3'd5; 127 | parameter VOL_SET = 3'd6; 128 | 129 | reg[2:0] state=0; 130 | always @(posedge clk) begin 131 | pre_sw<=sw; 132 | if(~RST || pre_sw!=sw) begin 133 | MP3_RSET<=0; 134 | cmd_cnt<=0; 135 | state<=RSET_OVER; 136 | cmd<=cmd_init; 137 | MP3_SCLK<=0; 138 | MP3_CS<=1; 139 | MP3_DCS<=1; 140 | cnt<=0; 141 | pos<=0; 142 | end 143 | else begin 144 | case(state) 145 | INITIALIZE:begin 146 | MP3_SCLK<=0; 147 | if(cmd_cnt>=cmd_cnt_max) begin 148 | state<=CHECK; 149 | end 150 | else if(MP3_DREQ) begin 151 | MP3_CS<=0; 152 | cnt<=1; 153 | state<=SEND_CMD; 154 | MP3_MOSI<=cmd[127]; 155 | cmd<={cmd[126:0],cmd[127]}; 156 | end 157 | end 158 | SEND_CMD:begin 159 | if(MP3_DREQ) begin 160 | if(MP3_SCLK) begin 161 | if(cnt<32)begin 162 | cnt<=cnt+1; 163 | MP3_MOSI<=cmd[127]; 164 | cmd<={cmd[126:0],cmd[127]}; 165 | end 166 | else begin 167 | MP3_CS<=1; 168 | cnt<=0; 169 | cmd_cnt<=cmd_cnt+1; 170 | state<=INITIALIZE; 171 | end 172 | end 173 | MP3_SCLK<=~MP3_SCLK; 174 | end 175 | end 176 | CHECK:begin 177 | if(vol[15:0]!=cmd_init[47:32]) begin 178 | state<=VOL_SET_PRE; 179 | next_cmd<={16'h020B,vol[15:0]}; 180 | end 181 | else if(MP3_DREQ) begin 182 | MP3_DCS<=0; 183 | MP3_SCLK<=0; 184 | state<=DATA_SEND; 185 | case (sw) 186 | 3'd0:begin 187 | data<={data0[14:0],data0[15]}; 188 | MP3_MOSI<=data0[15]; 189 | end 190 | 3'd1:begin 191 | data<={data1[14:0],data1[15]}; 192 | MP3_MOSI<=data1[15]; 193 | end 194 | 3'd2:begin 195 | data<={data2[14:0],data2[15]}; 196 | MP3_MOSI<=data2[15]; 197 | end 198 | 3'd3:begin 199 | data<={data3[14:0],data3[15]}; 200 | MP3_MOSI<=data3[15]; 201 | end 202 | 3'd4:begin 203 | data<={data4[14:0],data4[15]}; 204 | MP3_MOSI<=data4[15]; 205 | end 206 | 3'd5:begin 207 | data<={data5[14:0],data5[15]}; 208 | MP3_MOSI<=data5[15]; 209 | end 210 | 3'd6:begin 211 | data<={data6[14:0],data6[15]}; 212 | MP3_MOSI<=data6[15]; 213 | end 214 | default:begin 215 | data<={data0[14:0],data0[15]}; 216 | MP3_MOSI<=data0[15]; 217 | end 218 | endcase 219 | 220 | cnt<=1; 221 | end 222 | cmd_init[47:32]<=vol; 223 | end 224 | DATA_SEND:begin 225 | if(MP3_SCLK)begin 226 | if(cnt<16)begin 227 | cnt<=cnt+1; 228 | MP3_MOSI<=data[15]; 229 | data<={data[14:0],data[15]}; 230 | end 231 | else begin 232 | MP3_DCS<=1; 233 | pos<=pos+1; 234 | state<=CHECK; 235 | end 236 | end 237 | MP3_SCLK<=~MP3_SCLK; 238 | end 239 | RSET_OVER:begin 240 | if(cnt<1000000) begin 241 | cnt<=cnt+1; 242 | end 243 | else begin 244 | cnt<=0; 245 | state<=INITIALIZE; 246 | MP3_RSET<=1; 247 | end 248 | end 249 | VOL_SET_PRE:begin 250 | if(MP3_DREQ) begin 251 | MP3_CS<=0; 252 | cnt<=1; 253 | state<=VOL_SET; 254 | MP3_MOSI<=next_cmd[31]; 255 | next_cmd<={next_cmd[30:0],next_cmd[31]}; 256 | end 257 | end 258 | VOL_SET:begin 259 | if(MP3_DREQ) begin 260 | if(MP3_SCLK) begin 261 | if(cnt<32)begin 262 | cnt<=cnt+1; 263 | MP3_MOSI<=next_cmd[31]; 264 | next_cmd<={next_cmd[30:0],next_cmd[31]}; 265 | end 266 | else begin 267 | MP3_CS<=1; 268 | cnt<=0; 269 | state<=CHECK; 270 | end 271 | end 272 | MP3_SCLK<=~MP3_SCLK; 273 | end 274 | end 275 | default:begin 276 | ; 277 | end 278 | endcase 279 | end 280 | end 281 | 282 | endmodule 283 | --------------------------------------------------------------------------------