├── Behavior Simulation ├── ALU.v ├── CLZ.v ├── CP0.v ├── CPU.v ├── Controller.v ├── DIV.v ├── DMEM.v ├── Decoder.v ├── HI_LO.v ├── IMEM.v ├── MUL.v ├── MUX.v ├── PC.v ├── Regfile.v ├── dist_mem_gen_0.mif ├── dist_mem_gen_0.v ├── dist_mem_gen_v8_0.v └── sccomp_dataflow.v ├── MIPS官方文档.pdf ├── Post-Synthesis Timing Simulation ├── CPU54.xdc ├── Divider.v └── sccomp_dataflow.v ├── README.md ├── 指令操作时间表.xls ├── 数据通路.pdf └── 数据通路总图.pdf /Behavior Simulation/ALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Misaka-N/TJCS-SingleCircleCPU54/HEAD/Behavior Simulation/ALU.v -------------------------------------------------------------------------------- /Behavior Simulation/CLZ.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Misaka-N/TJCS-SingleCircleCPU54/HEAD/Behavior Simulation/CLZ.v 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